1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version : public Abstract_VM_Version {
32 public:
33 // cpuid result register layouts. These are all unions of a uint32_t
34 // (in case anyone wants access to the register as a whole) and a bitfield.
35
36 union StdCpuid1Eax {
37 uint32_t value;
38 struct {
39 uint32_t stepping : 4,
40 model : 4,
41 family : 4,
42 proc_type : 2,
43 : 2,
44 ext_model : 4,
45 ext_family : 8,
46 : 4;
47 } bits;
48 };
49
50 union StdCpuid1Ebx { // example, unused
51 uint32_t value;
52 struct {
53 uint32_t brand_id : 8,
54 clflush_size : 8,
55 threads_per_cpu : 8,
56 apic_id : 8;
57 } bits;
58 };
59
60 union StdCpuid1Ecx {
61 uint32_t value;
62 struct {
63 uint32_t sse3 : 1,
64 : 2,
65 monitor : 1,
66 : 1,
67 vmx : 1,
68 : 1,
69 est : 1,
70 : 1,
71 ssse3 : 1,
72 cid : 1,
73 : 2,
74 cmpxchg16: 1,
75 : 4,
76 dca : 1,
77 sse4_1 : 1,
78 sse4_2 : 1,
79 : 2,
80 popcnt : 1,
81 : 8;
82 } bits;
83 };
84
85 union StdCpuid1Edx {
86 uint32_t value;
87 struct {
88 uint32_t : 4,
89 tsc : 1,
90 : 3,
91 cmpxchg8 : 1,
92 : 6,
93 cmov : 1,
94 : 7,
95 mmx : 1,
96 fxsr : 1,
97 sse : 1,
98 sse2 : 1,
99 : 1,
100 ht : 1,
101 : 3;
102 } bits;
103 };
104
105 union DcpCpuid4Eax {
106 uint32_t value;
107 struct {
108 uint32_t cache_type : 5,
109 : 21,
110 cores_per_cpu : 6;
111 } bits;
112 };
113
114 union DcpCpuid4Ebx {
115 uint32_t value;
116 struct {
117 uint32_t L1_line_size : 12,
118 partitions : 10,
119 associativity : 10;
120 } bits;
121 };
122
123 union TplCpuidBEbx {
124 uint32_t value;
125 struct {
126 uint32_t logical_cpus : 16,
127 : 16;
128 } bits;
129 };
130
131 union ExtCpuid1Ecx {
132 uint32_t value;
133 struct {
134 uint32_t LahfSahf : 1,
135 CmpLegacy : 1,
136 : 4,
137 lzcnt : 1,
138 sse4a : 1,
139 misalignsse : 1,
140 prefetchw : 1,
141 : 22;
142 } bits;
143 };
144
145 union ExtCpuid1Edx {
146 uint32_t value;
147 struct {
148 uint32_t : 22,
149 mmx_amd : 1,
150 mmx : 1,
151 fxsr : 1,
152 : 4,
153 long_mode : 1,
154 tdnow2 : 1,
155 tdnow : 1;
156 } bits;
157 };
158
159 union ExtCpuid5Ex {
160 uint32_t value;
161 struct {
162 uint32_t L1_line_size : 8,
163 L1_tag_lines : 8,
164 L1_assoc : 8,
165 L1_size : 8;
166 } bits;
167 };
168
169 union ExtCpuid8Ecx {
170 uint32_t value;
171 struct {
172 uint32_t cores_per_cpu : 8,
173 : 24;
174 } bits;
175 };
176
177 protected:
178 static int _cpu;
179 static int _model;
180 static int _stepping;
181 static int _cpuFeatures; // features returned by the "cpuid" instruction
182 // 0 if this instruction is not available
183 static const char* _features_str;
184
185 enum {
186 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
187 CPU_CMOV = (1 << 1),
188 CPU_FXSR = (1 << 2),
189 CPU_HT = (1 << 3),
190 CPU_MMX = (1 << 4),
191 CPU_3DNOW = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
192 CPU_SSE = (1 << 6),
193 CPU_SSE2 = (1 << 7),
194 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
195 CPU_SSSE3 = (1 << 9),
196 CPU_SSE4A = (1 << 10),
197 CPU_SSE4_1 = (1 << 11),
198 CPU_SSE4_2 = (1 << 12),
199 CPU_POPCNT = (1 << 13),
200 CPU_LZCNT = (1 << 14)
201 } cpuFeatureFlags;
202
203 // cpuid information block. All info derived from executing cpuid with
204 // various function numbers is stored here. Intel and AMD info is
205 // merged in this block: accessor methods disentangle it.
206 //
207 // The info block is laid out in subblocks of 4 dwords corresponding to
208 // eax, ebx, ecx and edx, whether or not they contain anything useful.
209 struct CpuidInfo {
210 // cpuid function 0
211 uint32_t std_max_function;
212 uint32_t std_vendor_name_0;
213 uint32_t std_vendor_name_1;
214 uint32_t std_vendor_name_2;
215
216 // cpuid function 1
217 StdCpuid1Eax std_cpuid1_eax;
218 StdCpuid1Ebx std_cpuid1_ebx;
219 StdCpuid1Ecx std_cpuid1_ecx;
220 StdCpuid1Edx std_cpuid1_edx;
221
222 // cpuid function 4 (deterministic cache parameters)
223 DcpCpuid4Eax dcp_cpuid4_eax;
224 DcpCpuid4Ebx dcp_cpuid4_ebx;
225 uint32_t dcp_cpuid4_ecx; // unused currently
226 uint32_t dcp_cpuid4_edx; // unused currently
227
228 // cpuid function 0xB (processor topology)
229 // ecx = 0
230 uint32_t tpl_cpuidB0_eax;
231 TplCpuidBEbx tpl_cpuidB0_ebx;
232 uint32_t tpl_cpuidB0_ecx; // unused currently
233 uint32_t tpl_cpuidB0_edx; // unused currently
234
235 // ecx = 1
236 uint32_t tpl_cpuidB1_eax;
237 TplCpuidBEbx tpl_cpuidB1_ebx;
238 uint32_t tpl_cpuidB1_ecx; // unused currently
239 uint32_t tpl_cpuidB1_edx; // unused currently
240
241 // ecx = 2
242 uint32_t tpl_cpuidB2_eax;
243 TplCpuidBEbx tpl_cpuidB2_ebx;
244 uint32_t tpl_cpuidB2_ecx; // unused currently
245 uint32_t tpl_cpuidB2_edx; // unused currently
246
247 // cpuid function 0x80000000 // example, unused
248 uint32_t ext_max_function;
249 uint32_t ext_vendor_name_0;
250 uint32_t ext_vendor_name_1;
251 uint32_t ext_vendor_name_2;
252
253 // cpuid function 0x80000001
254 uint32_t ext_cpuid1_eax; // reserved
255 uint32_t ext_cpuid1_ebx; // reserved
256 ExtCpuid1Ecx ext_cpuid1_ecx;
257 ExtCpuid1Edx ext_cpuid1_edx;
258
259 // cpuid functions 0x80000002 thru 0x80000004: example, unused
260 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
261 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
262 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
263
264 // cpuid function 0x80000005 //AMD L1, Intel reserved
265 uint32_t ext_cpuid5_eax; // unused currently
266 uint32_t ext_cpuid5_ebx; // reserved
267 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
268 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
269
270 // cpuid function 0x80000008
271 uint32_t ext_cpuid8_eax; // unused currently
272 uint32_t ext_cpuid8_ebx; // reserved
273 ExtCpuid8Ecx ext_cpuid8_ecx;
274 uint32_t ext_cpuid8_edx; // reserved
275 };
276
277 // The actual cpuid info block
278 static CpuidInfo _cpuid_info;
279
280 // Extractors and predicates
281 static uint32_t extended_cpu_family() {
282 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
283 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
284 return result;
285 }
286 static uint32_t extended_cpu_model() {
287 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
288 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
289 return result;
290 }
291 static uint32_t cpu_stepping() {
292 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
293 return result;
294 }
295 static uint logical_processor_count() {
296 uint result = threads_per_core();
297 return result;
298 }
299 static uint32_t feature_flags() {
300 uint32_t result = 0;
301 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
302 result |= CPU_CX8;
303 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
304 result |= CPU_CMOV;
305 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
306 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
307 result |= CPU_FXSR;
308 // HT flag is set for multi-core processors also.
309 if (threads_per_core() > 1)
310 result |= CPU_HT;
311 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
312 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
313 result |= CPU_MMX;
314 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
315 result |= CPU_SSE;
316 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
317 result |= CPU_SSE2;
318 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
319 result |= CPU_SSE3;
320 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
321 result |= CPU_SSSE3;
322 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
323 result |= CPU_SSE4_1;
324 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
325 result |= CPU_SSE4_2;
326 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
327 result |= CPU_POPCNT;
328
329 // AMD features.
330 if (is_amd()) {
331 if (_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0)
332 result |= CPU_3DNOW;
333 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
334 result |= CPU_LZCNT;
335 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
336 result |= CPU_SSE4A;
337 }
338
339 return result;
340 }
341
342 static void get_processor_features();
343
344 public:
345 // Offsets for cpuid asm stub
346 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
347 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
348 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
349 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
350 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
351 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
352 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
353 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
354 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
355
356 // Initialization
357 static void initialize();
358
359 // Asserts
360 static void assert_is_initialized() {
361 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
362 }
363
364 //
365 // Processor family:
366 // 3 - 386
367 // 4 - 486
368 // 5 - Pentium
369 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
370 // Pentium M, Core Solo, Core Duo, Core2 Duo
371 // family 6 model: 9, 13, 14, 15
372 // 0x0f - Pentium 4, Opteron
373 //
374 // Note: The cpu family should be used to select between
375 // instruction sequences which are valid on all Intel
376 // processors. Use the feature test functions below to
377 // determine whether a particular instruction is supported.
378 //
379 static int cpu_family() { return _cpu;}
380 static bool is_P6() { return cpu_family() >= 6; }
381
382 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
383 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
384
385 static bool supports_processor_topology() {
386 return (_cpuid_info.std_max_function >= 0xB) &&
387 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
388 // Some cpus have max cpuid >= 0xB but do not support processor topology.
389 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
390 }
391
392 static uint cores_per_cpu() {
393 uint result = 1;
394 if (is_intel()) {
395 if (supports_processor_topology()) {
396 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
397 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
398 } else {
399 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
400 }
401 } else if (is_amd()) {
402 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
403 }
404 return result;
405 }
406
407 static uint threads_per_core() {
408 uint result = 1;
409 if (is_intel() && supports_processor_topology()) {
410 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
411 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
412 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
413 cores_per_cpu();
414 }
415 return result;
416 }
417
418 static intx L1_data_cache_line_size() {
419 intx result = 0;
420 if (is_intel()) {
421 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
422 } else if (is_amd()) {
423 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
424 }
425 if (result < 32) // not defined ?
426 result = 32; // 32 bytes by default on x86 and other x64
427 return result;
428 }
429
430 //
431 // Feature identification
432 //
433 static bool supports_cpuid() { return _cpuFeatures != 0; }
434 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
435 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
436 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
437 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
438 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
439 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
440 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
441 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
442 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
443 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
444 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
445 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
446 //
447 // AMD features
448 //
449 static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; }
450 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
451 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; }
452 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
453 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
454
455 static bool supports_compare_and_exchange() { return true; }
456
457 static const char* cpu_features() { return _features_str; }
458
459 static intx allocate_prefetch_distance() {
460 // This method should be called before allocate_prefetch_style().
461 //
462 // Hardware prefetching (distance/size in bytes):
463 // Pentium 3 - 64 / 32
464 // Pentium 4 - 256 / 128
465 // Athlon - 64 / 32 ????
466 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
467 // Core - 128 / 64
468 //
469 // Software prefetching (distance in bytes / instruction with best score):
470 // Pentium 3 - 128 / prefetchnta
471 // Pentium 4 - 512 / prefetchnta
472 // Athlon - 128 / prefetchnta
473 // Opteron - 256 / prefetchnta
474 // Core - 256 / prefetchnta
475 // It will be used only when AllocatePrefetchStyle > 0
476
477 intx count = AllocatePrefetchDistance;
478 if (count < 0) { // default ?
479 if (is_amd()) { // AMD
480 if (supports_sse2())
481 count = 256; // Opteron
482 else
483 count = 128; // Athlon
484 } else { // Intel
485 if (supports_sse2())
486 if (cpu_family() == 6) {
487 count = 256; // Pentium M, Core, Core2
488 } else {
489 count = 512; // Pentium 4
490 }
491 else
492 count = 128; // Pentium 3 (and all other old CPUs)
493 }
494 }
495 return count;
496 }
497 static intx allocate_prefetch_style() {
498 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
499 // Return 0 if AllocatePrefetchDistance was not defined.
500 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
501 }
502
503 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
504 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
505 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
506 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
507
508 // gc copy/scan is disabled if prefetchw isn't supported, because
509 // Prefetch::write emits an inlined prefetchw on Linux.
510 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
511 // The used prefetcht0 instruction works for both amd64 and em64t.
512 static intx prefetch_copy_interval_in_bytes() {
513 intx interval = PrefetchCopyIntervalInBytes;
514 return interval >= 0 ? interval : 576;
515 }
516 static intx prefetch_scan_interval_in_bytes() {
517 intx interval = PrefetchScanIntervalInBytes;
518 return interval >= 0 ? interval : 576;
519 }
520 static intx prefetch_fields_ahead() {
521 intx count = PrefetchFieldsAhead;
522 return count >= 0 ? count : 1;
523 }
524 };
525
526 #endif // CPU_X86_VM_VM_VERSION_X86_HPP