src/cpu/sparc/vm/assembler_sparc.hpp
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@@ -20,10 +20,13 @@
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
+#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
+#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
+
class BiasedLockingCounters;
// <sys/trap.h> promises that the system will not use traps 16-31
#define ST_RESERVED_FOR_USER_0 0x10
@@ -2498,5 +2501,7 @@
#ifdef ASSERT
// On RISC, there's no benefit to verifying instruction boundaries.
inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
#endif
+
+#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP