1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "assembler_x86.inline.hpp"
27 #include "gc_interface/collectedHeap.inline.hpp"
28 #include "interpreter/interpreter.hpp"
29 #include "memory/cardTableModRefBS.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/methodHandles.hpp"
32 #include "runtime/biasedLocking.hpp"
33 #include "runtime/interfaceSupport.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #ifndef SERIALGC
39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
41 #include "gc_implementation/g1/heapRegion.hpp"
42 #endif
43
44 // Implementation of AddressLiteral
45
46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
47 _is_lval = false;
48 _target = target;
49 switch (rtype) {
50 case relocInfo::oop_type:
51 // Oops are a special case. Normally they would be their own section
52 // but in cases like icBuffer they are literals in the code stream that
53 // we don't have a section for. We use none so that we get a literal address
54 // which is always patchable.
55 break;
56 case relocInfo::external_word_type:
57 _rspec = external_word_Relocation::spec(target);
58 break;
59 case relocInfo::internal_word_type:
60 _rspec = internal_word_Relocation::spec(target);
61 break;
62 case relocInfo::opt_virtual_call_type:
63 _rspec = opt_virtual_call_Relocation::spec();
64 break;
65 case relocInfo::static_call_type:
66 _rspec = static_call_Relocation::spec();
67 break;
68 case relocInfo::runtime_call_type:
69 _rspec = runtime_call_Relocation::spec();
70 break;
71 case relocInfo::poll_type:
72 case relocInfo::poll_return_type:
73 _rspec = Relocation::spec_simple(rtype);
74 break;
75 case relocInfo::none:
76 break;
77 default:
78 ShouldNotReachHere();
79 break;
80 }
81 }
82
83 // Implementation of Address
84
85 #ifdef _LP64
86
87 Address Address::make_array(ArrayAddress adr) {
88 // Not implementable on 64bit machines
89 // Should have been handled higher up the call chain.
90 ShouldNotReachHere();
91 return Address();
92 }
93
94 // exceedingly dangerous constructor
95 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
96 _base = noreg;
97 _index = noreg;
98 _scale = no_scale;
99 _disp = disp;
100 switch (rtype) {
101 case relocInfo::external_word_type:
102 _rspec = external_word_Relocation::spec(loc);
103 break;
104 case relocInfo::internal_word_type:
105 _rspec = internal_word_Relocation::spec(loc);
106 break;
107 case relocInfo::runtime_call_type:
108 // HMM
109 _rspec = runtime_call_Relocation::spec();
110 break;
111 case relocInfo::poll_type:
112 case relocInfo::poll_return_type:
113 _rspec = Relocation::spec_simple(rtype);
114 break;
115 case relocInfo::none:
116 break;
117 default:
118 ShouldNotReachHere();
119 }
120 }
121 #else // LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 AddressLiteral base = adr.base();
125 Address index = adr.index();
126 assert(index._disp == 0, "must not have disp"); // maybe it can?
127 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
128 array._rspec = base._rspec;
129 return array;
130 }
131
132 // exceedingly dangerous constructor
133 Address::Address(address loc, RelocationHolder spec) {
134 _base = noreg;
135 _index = noreg;
136 _scale = no_scale;
137 _disp = (intptr_t) loc;
138 _rspec = spec;
139 }
140
141 #endif // _LP64
142
143
144
145 // Convert the raw encoding form into the form expected by the constructor for
146 // Address. An index of 4 (rsp) corresponds to having no index, so convert
147 // that to noreg for the Address constructor.
148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
149 RelocationHolder rspec;
150 if (disp_is_oop) {
151 rspec = Relocation::spec_simple(relocInfo::oop_type);
152 }
153 bool valid_index = index != rsp->encoding();
154 if (valid_index) {
155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
156 madr._rspec = rspec;
157 return madr;
158 } else {
159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
160 madr._rspec = rspec;
161 return madr;
162 }
163 }
164
165 // Implementation of Assembler
166
167 int AbstractAssembler::code_fill_byte() {
168 return (u_char)'\xF4'; // hlt
169 }
170
171 // make this go away someday
172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
173 if (rtype == relocInfo::none)
174 emit_long(data);
175 else emit_data(data, Relocation::spec_simple(rtype), format);
176 }
177
178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
179 assert(imm_operand == 0, "default format must be immediate in this file");
180 assert(inst_mark() != NULL, "must be inside InstructionMark");
181 if (rspec.type() != relocInfo::none) {
182 #ifdef ASSERT
183 check_relocation(rspec, format);
184 #endif
185 // Do not use AbstractAssembler::relocate, which is not intended for
186 // embedded words. Instead, relocate to the enclosing instruction.
187
188 // hack. call32 is too wide for mask so use disp32
189 if (format == call32_operand)
190 code_section()->relocate(inst_mark(), rspec, disp32_operand);
191 else
192 code_section()->relocate(inst_mark(), rspec, format);
193 }
194 emit_long(data);
195 }
196
197 static int encode(Register r) {
198 int enc = r->encoding();
199 if (enc >= 8) {
200 enc -= 8;
201 }
202 return enc;
203 }
204
205 static int encode(XMMRegister r) {
206 int enc = r->encoding();
207 if (enc >= 8) {
208 enc -= 8;
209 }
210 return enc;
211 }
212
213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
214 assert(dst->has_byte_register(), "must have byte register");
215 assert(isByte(op1) && isByte(op2), "wrong opcode");
216 assert(isByte(imm8), "not a byte");
217 assert((op1 & 0x01) == 0, "should be 8bit operation");
218 emit_byte(op1);
219 emit_byte(op2 | encode(dst));
220 emit_byte(imm8);
221 }
222
223
224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
225 assert(isByte(op1) && isByte(op2), "wrong opcode");
226 assert((op1 & 0x01) == 1, "should be 32bit operation");
227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
228 if (is8bit(imm32)) {
229 emit_byte(op1 | 0x02); // set sign bit
230 emit_byte(op2 | encode(dst));
231 emit_byte(imm32 & 0xFF);
232 } else {
233 emit_byte(op1);
234 emit_byte(op2 | encode(dst));
235 emit_long(imm32);
236 }
237 }
238
239 // immediate-to-memory forms
240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
241 assert((op1 & 0x01) == 1, "should be 32bit operation");
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
243 if (is8bit(imm32)) {
244 emit_byte(op1 | 0x02); // set sign bit
245 emit_operand(rm, adr, 1);
246 emit_byte(imm32 & 0xFF);
247 } else {
248 emit_byte(op1);
249 emit_operand(rm, adr, 4);
250 emit_long(imm32);
251 }
252 }
253
254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
255 LP64_ONLY(ShouldNotReachHere());
256 assert(isByte(op1) && isByte(op2), "wrong opcode");
257 assert((op1 & 0x01) == 1, "should be 32bit operation");
258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
259 InstructionMark im(this);
260 emit_byte(op1);
261 emit_byte(op2 | encode(dst));
262 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
263 }
264
265
266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
267 assert(isByte(op1) && isByte(op2), "wrong opcode");
268 emit_byte(op1);
269 emit_byte(op2 | encode(dst) << 3 | encode(src));
270 }
271
272
273 void Assembler::emit_operand(Register reg, Register base, Register index,
274 Address::ScaleFactor scale, int disp,
275 RelocationHolder const& rspec,
276 int rip_relative_correction) {
277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
278
279 // Encode the registers as needed in the fields they are used in
280
281 int regenc = encode(reg) << 3;
282 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
283 int baseenc = base->is_valid() ? encode(base) : 0;
284
285 if (base->is_valid()) {
286 if (index->is_valid()) {
287 assert(scale != Address::no_scale, "inconsistent address");
288 // [base + index*scale + disp]
289 if (disp == 0 && rtype == relocInfo::none &&
290 base != rbp LP64_ONLY(&& base != r13)) {
291 // [base + index*scale]
292 // [00 reg 100][ss index base]
293 assert(index != rsp, "illegal addressing mode");
294 emit_byte(0x04 | regenc);
295 emit_byte(scale << 6 | indexenc | baseenc);
296 } else if (is8bit(disp) && rtype == relocInfo::none) {
297 // [base + index*scale + imm8]
298 // [01 reg 100][ss index base] imm8
299 assert(index != rsp, "illegal addressing mode");
300 emit_byte(0x44 | regenc);
301 emit_byte(scale << 6 | indexenc | baseenc);
302 emit_byte(disp & 0xFF);
303 } else {
304 // [base + index*scale + disp32]
305 // [10 reg 100][ss index base] disp32
306 assert(index != rsp, "illegal addressing mode");
307 emit_byte(0x84 | regenc);
308 emit_byte(scale << 6 | indexenc | baseenc);
309 emit_data(disp, rspec, disp32_operand);
310 }
311 } else if (base == rsp LP64_ONLY(|| base == r12)) {
312 // [rsp + disp]
313 if (disp == 0 && rtype == relocInfo::none) {
314 // [rsp]
315 // [00 reg 100][00 100 100]
316 emit_byte(0x04 | regenc);
317 emit_byte(0x24);
318 } else if (is8bit(disp) && rtype == relocInfo::none) {
319 // [rsp + imm8]
320 // [01 reg 100][00 100 100] disp8
321 emit_byte(0x44 | regenc);
322 emit_byte(0x24);
323 emit_byte(disp & 0xFF);
324 } else {
325 // [rsp + imm32]
326 // [10 reg 100][00 100 100] disp32
327 emit_byte(0x84 | regenc);
328 emit_byte(0x24);
329 emit_data(disp, rspec, disp32_operand);
330 }
331 } else {
332 // [base + disp]
333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
334 if (disp == 0 && rtype == relocInfo::none &&
335 base != rbp LP64_ONLY(&& base != r13)) {
336 // [base]
337 // [00 reg base]
338 emit_byte(0x00 | regenc | baseenc);
339 } else if (is8bit(disp) && rtype == relocInfo::none) {
340 // [base + disp8]
341 // [01 reg base] disp8
342 emit_byte(0x40 | regenc | baseenc);
343 emit_byte(disp & 0xFF);
344 } else {
345 // [base + disp32]
346 // [10 reg base] disp32
347 emit_byte(0x80 | regenc | baseenc);
348 emit_data(disp, rspec, disp32_operand);
349 }
350 }
351 } else {
352 if (index->is_valid()) {
353 assert(scale != Address::no_scale, "inconsistent address");
354 // [index*scale + disp]
355 // [00 reg 100][ss index 101] disp32
356 assert(index != rsp, "illegal addressing mode");
357 emit_byte(0x04 | regenc);
358 emit_byte(scale << 6 | indexenc | 0x05);
359 emit_data(disp, rspec, disp32_operand);
360 } else if (rtype != relocInfo::none ) {
361 // [disp] (64bit) RIP-RELATIVE (32bit) abs
362 // [00 000 101] disp32
363
364 emit_byte(0x05 | regenc);
365 // Note that the RIP-rel. correction applies to the generated
366 // disp field, but _not_ to the target address in the rspec.
367
368 // disp was created by converting the target address minus the pc
369 // at the start of the instruction. That needs more correction here.
370 // intptr_t disp = target - next_ip;
371 assert(inst_mark() != NULL, "must be inside InstructionMark");
372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
373 int64_t adjusted = disp;
374 // Do rip-rel adjustment for 64bit
375 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
376 assert(is_simm32(adjusted),
377 "must be 32bit offset (RIP relative address)");
378 emit_data((int32_t) adjusted, rspec, disp32_operand);
379
380 } else {
381 // 32bit never did this, did everything as the rip-rel/disp code above
382 // [disp] ABSOLUTE
383 // [00 reg 100][00 100 101] disp32
384 emit_byte(0x04 | regenc);
385 emit_byte(0x25);
386 emit_data(disp, rspec, disp32_operand);
387 }
388 }
389 }
390
391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
392 Address::ScaleFactor scale, int disp,
393 RelocationHolder const& rspec) {
394 emit_operand((Register)reg, base, index, scale, disp, rspec);
395 }
396
397 // Secret local extension to Assembler::WhichOperand:
398 #define end_pc_operand (_WhichOperand_limit)
399
400 address Assembler::locate_operand(address inst, WhichOperand which) {
401 // Decode the given instruction, and return the address of
402 // an embedded 32-bit operand word.
403
404 // If "which" is disp32_operand, selects the displacement portion
405 // of an effective address specifier.
406 // If "which" is imm64_operand, selects the trailing immediate constant.
407 // If "which" is call32_operand, selects the displacement of a call or jump.
408 // Caller is responsible for ensuring that there is such an operand,
409 // and that it is 32/64 bits wide.
410
411 // If "which" is end_pc_operand, find the end of the instruction.
412
413 address ip = inst;
414 bool is_64bit = false;
415
416 debug_only(bool has_disp32 = false);
417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
418
419 again_after_prefix:
420 switch (0xFF & *ip++) {
421
422 // These convenience macros generate groups of "case" labels for the switch.
423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
425 case (x)+4: case (x)+5: case (x)+6: case (x)+7
426 #define REP16(x) REP8((x)+0): \
427 case REP8((x)+8)
428
429 case CS_segment:
430 case SS_segment:
431 case DS_segment:
432 case ES_segment:
433 case FS_segment:
434 case GS_segment:
435 // Seems dubious
436 LP64_ONLY(assert(false, "shouldn't have that prefix"));
437 assert(ip == inst+1, "only one prefix allowed");
438 goto again_after_prefix;
439
440 case 0x67:
441 case REX:
442 case REX_B:
443 case REX_X:
444 case REX_XB:
445 case REX_R:
446 case REX_RB:
447 case REX_RX:
448 case REX_RXB:
449 NOT_LP64(assert(false, "64bit prefixes"));
450 goto again_after_prefix;
451
452 case REX_W:
453 case REX_WB:
454 case REX_WX:
455 case REX_WXB:
456 case REX_WR:
457 case REX_WRB:
458 case REX_WRX:
459 case REX_WRXB:
460 NOT_LP64(assert(false, "64bit prefixes"));
461 is_64bit = true;
462 goto again_after_prefix;
463
464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
465 case 0x88: // movb a, r
466 case 0x89: // movl a, r
467 case 0x8A: // movb r, a
468 case 0x8B: // movl r, a
469 case 0x8F: // popl a
470 debug_only(has_disp32 = true);
471 break;
472
473 case 0x68: // pushq #32
474 if (which == end_pc_operand) {
475 return ip + 4;
476 }
477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
478 return ip; // not produced by emit_operand
479
480 case 0x66: // movw ... (size prefix)
481 again_after_size_prefix2:
482 switch (0xFF & *ip++) {
483 case REX:
484 case REX_B:
485 case REX_X:
486 case REX_XB:
487 case REX_R:
488 case REX_RB:
489 case REX_RX:
490 case REX_RXB:
491 case REX_W:
492 case REX_WB:
493 case REX_WX:
494 case REX_WXB:
495 case REX_WR:
496 case REX_WRB:
497 case REX_WRX:
498 case REX_WRXB:
499 NOT_LP64(assert(false, "64bit prefix found"));
500 goto again_after_size_prefix2;
501 case 0x8B: // movw r, a
502 case 0x89: // movw a, r
503 debug_only(has_disp32 = true);
504 break;
505 case 0xC7: // movw a, #16
506 debug_only(has_disp32 = true);
507 tail_size = 2; // the imm16
508 break;
509 case 0x0F: // several SSE/SSE2 variants
510 ip--; // reparse the 0x0F
511 goto again_after_prefix;
512 default:
513 ShouldNotReachHere();
514 }
515 break;
516
517 case REP8(0xB8): // movl/q r, #32/#64(oop?)
518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
519 // these asserts are somewhat nonsensical
520 #ifndef _LP64
521 assert(which == imm_operand || which == disp32_operand, "");
522 #else
523 assert((which == call32_operand || which == imm_operand) && is_64bit ||
524 which == narrow_oop_operand && !is_64bit, "");
525 #endif // _LP64
526 return ip;
527
528 case 0x69: // imul r, a, #32
529 case 0xC7: // movl a, #32(oop?)
530 tail_size = 4;
531 debug_only(has_disp32 = true); // has both kinds of operands!
532 break;
533
534 case 0x0F: // movx..., etc.
535 switch (0xFF & *ip++) {
536 case 0x12: // movlps
537 case 0x28: // movaps
538 case 0x2E: // ucomiss
539 case 0x2F: // comiss
540 case 0x54: // andps
541 case 0x55: // andnps
542 case 0x56: // orps
543 case 0x57: // xorps
544 case 0x6E: // movd
545 case 0x7E: // movd
546 case 0xAE: // ldmxcsr a
547 // 64bit side says it these have both operands but that doesn't
548 // appear to be true
549 debug_only(has_disp32 = true);
550 break;
551
552 case 0xAD: // shrd r, a, %cl
553 case 0xAF: // imul r, a
554 case 0xBE: // movsbl r, a (movsxb)
555 case 0xBF: // movswl r, a (movsxw)
556 case 0xB6: // movzbl r, a (movzxb)
557 case 0xB7: // movzwl r, a (movzxw)
558 case REP16(0x40): // cmovl cc, r, a
559 case 0xB0: // cmpxchgb
560 case 0xB1: // cmpxchg
561 case 0xC1: // xaddl
562 case 0xC7: // cmpxchg8
563 case REP16(0x90): // setcc a
564 debug_only(has_disp32 = true);
565 // fall out of the switch to decode the address
566 break;
567
568 case 0xAC: // shrd r, a, #8
569 debug_only(has_disp32 = true);
570 tail_size = 1; // the imm8
571 break;
572
573 case REP16(0x80): // jcc rdisp32
574 if (which == end_pc_operand) return ip + 4;
575 assert(which == call32_operand, "jcc has no disp32 or imm");
576 return ip;
577 default:
578 ShouldNotReachHere();
579 }
580 break;
581
582 case 0x81: // addl a, #32; addl r, #32
583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
584 // on 32bit in the case of cmpl, the imm might be an oop
585 tail_size = 4;
586 debug_only(has_disp32 = true); // has both kinds of operands!
587 break;
588
589 case 0x83: // addl a, #8; addl r, #8
590 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
591 debug_only(has_disp32 = true); // has both kinds of operands!
592 tail_size = 1;
593 break;
594
595 case 0x9B:
596 switch (0xFF & *ip++) {
597 case 0xD9: // fnstcw a
598 debug_only(has_disp32 = true);
599 break;
600 default:
601 ShouldNotReachHere();
602 }
603 break;
604
605 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
606 case REP4(0x10): // adc...
607 case REP4(0x20): // and...
608 case REP4(0x30): // xor...
609 case REP4(0x08): // or...
610 case REP4(0x18): // sbb...
611 case REP4(0x28): // sub...
612 case 0xF7: // mull a
613 case 0x8D: // lea r, a
614 case 0x87: // xchg r, a
615 case REP4(0x38): // cmp...
616 case 0x85: // test r, a
617 debug_only(has_disp32 = true); // has both kinds of operands!
618 break;
619
620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
621 case 0xC6: // movb a, #8
622 case 0x80: // cmpb a, #8
623 case 0x6B: // imul r, a, #8
624 debug_only(has_disp32 = true); // has both kinds of operands!
625 tail_size = 1; // the imm8
626 break;
627
628 case 0xE8: // call rdisp32
629 case 0xE9: // jmp rdisp32
630 if (which == end_pc_operand) return ip + 4;
631 assert(which == call32_operand, "call has no disp32 or imm");
632 return ip;
633
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
637 case 0xDD: // fld_d a; fst_d a; fstp_d a
638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
639 case 0xDF: // fild_d a; fistp_d a
640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
643 debug_only(has_disp32 = true);
644 break;
645
646 case 0xF0: // Lock
647 assert(os::is_MP(), "only on MP");
648 goto again_after_prefix;
649
650 case 0xF3: // For SSE
651 case 0xF2: // For SSE2
652 switch (0xFF & *ip++) {
653 case REX:
654 case REX_B:
655 case REX_X:
656 case REX_XB:
657 case REX_R:
658 case REX_RB:
659 case REX_RX:
660 case REX_RXB:
661 case REX_W:
662 case REX_WB:
663 case REX_WX:
664 case REX_WXB:
665 case REX_WR:
666 case REX_WRB:
667 case REX_WRX:
668 case REX_WRXB:
669 NOT_LP64(assert(false, "found 64bit prefix"));
670 ip++;
671 default:
672 ip++;
673 }
674 debug_only(has_disp32 = true); // has both kinds of operands!
675 break;
676
677 default:
678 ShouldNotReachHere();
679
680 #undef REP8
681 #undef REP16
682 }
683
684 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
685 #ifdef _LP64
686 assert(which != imm_operand, "instruction is not a movq reg, imm64");
687 #else
688 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
689 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
690 #endif // LP64
691 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
692
693 // parse the output of emit_operand
694 int op2 = 0xFF & *ip++;
695 int base = op2 & 0x07;
696 int op3 = -1;
697 const int b100 = 4;
698 const int b101 = 5;
699 if (base == b100 && (op2 >> 6) != 3) {
700 op3 = 0xFF & *ip++;
701 base = op3 & 0x07; // refetch the base
702 }
703 // now ip points at the disp (if any)
704
705 switch (op2 >> 6) {
706 case 0:
707 // [00 reg 100][ss index base]
708 // [00 reg 100][00 100 esp]
709 // [00 reg base]
710 // [00 reg 100][ss index 101][disp32]
711 // [00 reg 101] [disp32]
712
713 if (base == b101) {
714 if (which == disp32_operand)
715 return ip; // caller wants the disp32
716 ip += 4; // skip the disp32
717 }
718 break;
719
720 case 1:
721 // [01 reg 100][ss index base][disp8]
722 // [01 reg 100][00 100 esp][disp8]
723 // [01 reg base] [disp8]
724 ip += 1; // skip the disp8
725 break;
726
727 case 2:
728 // [10 reg 100][ss index base][disp32]
729 // [10 reg 100][00 100 esp][disp32]
730 // [10 reg base] [disp32]
731 if (which == disp32_operand)
732 return ip; // caller wants the disp32
733 ip += 4; // skip the disp32
734 break;
735
736 case 3:
737 // [11 reg base] (not a memory addressing mode)
738 break;
739 }
740
741 if (which == end_pc_operand) {
742 return ip + tail_size;
743 }
744
745 #ifdef _LP64
746 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
747 #else
748 assert(which == imm_operand, "instruction has only an imm field");
749 #endif // LP64
750 return ip;
751 }
752
753 address Assembler::locate_next_instruction(address inst) {
754 // Secretly share code with locate_operand:
755 return locate_operand(inst, end_pc_operand);
756 }
757
758
759 #ifdef ASSERT
760 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
761 address inst = inst_mark();
762 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
763 address opnd;
764
765 Relocation* r = rspec.reloc();
766 if (r->type() == relocInfo::none) {
767 return;
768 } else if (r->is_call() || format == call32_operand) {
769 // assert(format == imm32_operand, "cannot specify a nonzero format");
770 opnd = locate_operand(inst, call32_operand);
771 } else if (r->is_data()) {
772 assert(format == imm_operand || format == disp32_operand
773 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
774 opnd = locate_operand(inst, (WhichOperand)format);
775 } else {
776 assert(format == imm_operand, "cannot specify a format");
777 return;
778 }
779 assert(opnd == pc(), "must put operand where relocs can find it");
780 }
781 #endif // ASSERT
782
783 void Assembler::emit_operand32(Register reg, Address adr) {
784 assert(reg->encoding() < 8, "no extended registers");
785 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
786 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
787 adr._rspec);
788 }
789
790 void Assembler::emit_operand(Register reg, Address adr,
791 int rip_relative_correction) {
792 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
793 adr._rspec,
794 rip_relative_correction);
795 }
796
797 void Assembler::emit_operand(XMMRegister reg, Address adr) {
798 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
799 adr._rspec);
800 }
801
802 // MMX operations
803 void Assembler::emit_operand(MMXRegister reg, Address adr) {
804 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
805 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
806 }
807
808 // work around gcc (3.2.1-7a) bug
809 void Assembler::emit_operand(Address adr, MMXRegister reg) {
810 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
811 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
812 }
813
814
815 void Assembler::emit_farith(int b1, int b2, int i) {
816 assert(isByte(b1) && isByte(b2), "wrong opcode");
817 assert(0 <= i && i < 8, "illegal stack offset");
818 emit_byte(b1);
819 emit_byte(b2 + i);
820 }
821
822
823 // Now the Assembler instruction (identical for 32/64 bits)
824
825 void Assembler::adcl(Register dst, int32_t imm32) {
826 prefix(dst);
827 emit_arith(0x81, 0xD0, dst, imm32);
828 }
829
830 void Assembler::adcl(Register dst, Address src) {
831 InstructionMark im(this);
832 prefix(src, dst);
833 emit_byte(0x13);
834 emit_operand(dst, src);
835 }
836
837 void Assembler::adcl(Register dst, Register src) {
838 (void) prefix_and_encode(dst->encoding(), src->encoding());
839 emit_arith(0x13, 0xC0, dst, src);
840 }
841
842 void Assembler::addl(Address dst, int32_t imm32) {
843 InstructionMark im(this);
844 prefix(dst);
845 emit_arith_operand(0x81, rax, dst, imm32);
846 }
847
848 void Assembler::addl(Address dst, Register src) {
849 InstructionMark im(this);
850 prefix(dst, src);
851 emit_byte(0x01);
852 emit_operand(src, dst);
853 }
854
855 void Assembler::addl(Register dst, int32_t imm32) {
856 prefix(dst);
857 emit_arith(0x81, 0xC0, dst, imm32);
858 }
859
860 void Assembler::addl(Register dst, Address src) {
861 InstructionMark im(this);
862 prefix(src, dst);
863 emit_byte(0x03);
864 emit_operand(dst, src);
865 }
866
867 void Assembler::addl(Register dst, Register src) {
868 (void) prefix_and_encode(dst->encoding(), src->encoding());
869 emit_arith(0x03, 0xC0, dst, src);
870 }
871
872 void Assembler::addr_nop_4() {
873 // 4 bytes: NOP DWORD PTR [EAX+0]
874 emit_byte(0x0F);
875 emit_byte(0x1F);
876 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
877 emit_byte(0); // 8-bits offset (1 byte)
878 }
879
880 void Assembler::addr_nop_5() {
881 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
882 emit_byte(0x0F);
883 emit_byte(0x1F);
884 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
885 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
886 emit_byte(0); // 8-bits offset (1 byte)
887 }
888
889 void Assembler::addr_nop_7() {
890 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
891 emit_byte(0x0F);
892 emit_byte(0x1F);
893 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
894 emit_long(0); // 32-bits offset (4 bytes)
895 }
896
897 void Assembler::addr_nop_8() {
898 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
899 emit_byte(0x0F);
900 emit_byte(0x1F);
901 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
902 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
903 emit_long(0); // 32-bits offset (4 bytes)
904 }
905
906 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
907 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
908 emit_byte(0xF2);
909 int encode = prefix_and_encode(dst->encoding(), src->encoding());
910 emit_byte(0x0F);
911 emit_byte(0x58);
912 emit_byte(0xC0 | encode);
913 }
914
915 void Assembler::addsd(XMMRegister dst, Address src) {
916 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
917 InstructionMark im(this);
918 emit_byte(0xF2);
919 prefix(src, dst);
920 emit_byte(0x0F);
921 emit_byte(0x58);
922 emit_operand(dst, src);
923 }
924
925 void Assembler::addss(XMMRegister dst, XMMRegister src) {
926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
927 emit_byte(0xF3);
928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
929 emit_byte(0x0F);
930 emit_byte(0x58);
931 emit_byte(0xC0 | encode);
932 }
933
934 void Assembler::addss(XMMRegister dst, Address src) {
935 NOT_LP64(assert(VM_Version::supports_sse(), ""));
936 InstructionMark im(this);
937 emit_byte(0xF3);
938 prefix(src, dst);
939 emit_byte(0x0F);
940 emit_byte(0x58);
941 emit_operand(dst, src);
942 }
943
944 void Assembler::andl(Register dst, int32_t imm32) {
945 prefix(dst);
946 emit_arith(0x81, 0xE0, dst, imm32);
947 }
948
949 void Assembler::andl(Register dst, Address src) {
950 InstructionMark im(this);
951 prefix(src, dst);
952 emit_byte(0x23);
953 emit_operand(dst, src);
954 }
955
956 void Assembler::andl(Register dst, Register src) {
957 (void) prefix_and_encode(dst->encoding(), src->encoding());
958 emit_arith(0x23, 0xC0, dst, src);
959 }
960
961 void Assembler::andpd(XMMRegister dst, Address src) {
962 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
963 InstructionMark im(this);
964 emit_byte(0x66);
965 prefix(src, dst);
966 emit_byte(0x0F);
967 emit_byte(0x54);
968 emit_operand(dst, src);
969 }
970
971 void Assembler::bsfl(Register dst, Register src) {
972 int encode = prefix_and_encode(dst->encoding(), src->encoding());
973 emit_byte(0x0F);
974 emit_byte(0xBC);
975 emit_byte(0xC0 | encode);
976 }
977
978 void Assembler::bsrl(Register dst, Register src) {
979 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
980 int encode = prefix_and_encode(dst->encoding(), src->encoding());
981 emit_byte(0x0F);
982 emit_byte(0xBD);
983 emit_byte(0xC0 | encode);
984 }
985
986 void Assembler::bswapl(Register reg) { // bswap
987 int encode = prefix_and_encode(reg->encoding());
988 emit_byte(0x0F);
989 emit_byte(0xC8 | encode);
990 }
991
992 void Assembler::call(Label& L, relocInfo::relocType rtype) {
993 // suspect disp32 is always good
994 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
995
996 if (L.is_bound()) {
997 const int long_size = 5;
998 int offs = (int)( target(L) - pc() );
999 assert(offs <= 0, "assembler error");
1000 InstructionMark im(this);
1001 // 1110 1000 #32-bit disp
1002 emit_byte(0xE8);
1003 emit_data(offs - long_size, rtype, operand);
1004 } else {
1005 InstructionMark im(this);
1006 // 1110 1000 #32-bit disp
1007 L.add_patch_at(code(), locator());
1008
1009 emit_byte(0xE8);
1010 emit_data(int(0), rtype, operand);
1011 }
1012 }
1013
1014 void Assembler::call(Register dst) {
1015 // This was originally using a 32bit register encoding
1016 // and surely we want 64bit!
1017 // this is a 32bit encoding but in 64bit mode the default
1018 // operand size is 64bit so there is no need for the
1019 // wide prefix. So prefix only happens if we use the
1020 // new registers. Much like push/pop.
1021 int x = offset();
1022 // this may be true but dbx disassembles it as if it
1023 // were 32bits...
1024 // int encode = prefix_and_encode(dst->encoding());
1025 // if (offset() != x) assert(dst->encoding() >= 8, "what?");
1026 int encode = prefixq_and_encode(dst->encoding());
1027
1028 emit_byte(0xFF);
1029 emit_byte(0xD0 | encode);
1030 }
1031
1032
1033 void Assembler::call(Address adr) {
1034 InstructionMark im(this);
1035 prefix(adr);
1036 emit_byte(0xFF);
1037 emit_operand(rdx, adr);
1038 }
1039
1040 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1041 assert(entry != NULL, "call most probably wrong");
1042 InstructionMark im(this);
1043 emit_byte(0xE8);
1044 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1045 assert(is_simm32(disp), "must be 32bit offset (call2)");
1046 // Technically, should use call32_operand, but this format is
1047 // implied by the fact that we're emitting a call instruction.
1048
1049 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1050 emit_data((int) disp, rspec, operand);
1051 }
1052
1053 void Assembler::cdql() {
1054 emit_byte(0x99);
1055 }
1056
1057 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1058 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1059 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1060 emit_byte(0x0F);
1061 emit_byte(0x40 | cc);
1062 emit_byte(0xC0 | encode);
1063 }
1064
1065
1066 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1067 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1068 prefix(src, dst);
1069 emit_byte(0x0F);
1070 emit_byte(0x40 | cc);
1071 emit_operand(dst, src);
1072 }
1073
1074 void Assembler::cmpb(Address dst, int imm8) {
1075 InstructionMark im(this);
1076 prefix(dst);
1077 emit_byte(0x80);
1078 emit_operand(rdi, dst, 1);
1079 emit_byte(imm8);
1080 }
1081
1082 void Assembler::cmpl(Address dst, int32_t imm32) {
1083 InstructionMark im(this);
1084 prefix(dst);
1085 emit_byte(0x81);
1086 emit_operand(rdi, dst, 4);
1087 emit_long(imm32);
1088 }
1089
1090 void Assembler::cmpl(Register dst, int32_t imm32) {
1091 prefix(dst);
1092 emit_arith(0x81, 0xF8, dst, imm32);
1093 }
1094
1095 void Assembler::cmpl(Register dst, Register src) {
1096 (void) prefix_and_encode(dst->encoding(), src->encoding());
1097 emit_arith(0x3B, 0xC0, dst, src);
1098 }
1099
1100
1101 void Assembler::cmpl(Register dst, Address src) {
1102 InstructionMark im(this);
1103 prefix(src, dst);
1104 emit_byte(0x3B);
1105 emit_operand(dst, src);
1106 }
1107
1108 void Assembler::cmpw(Address dst, int imm16) {
1109 InstructionMark im(this);
1110 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1111 emit_byte(0x66);
1112 emit_byte(0x81);
1113 emit_operand(rdi, dst, 2);
1114 emit_word(imm16);
1115 }
1116
1117 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1118 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1119 // The ZF is set if the compared values were equal, and cleared otherwise.
1120 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1121 if (Atomics & 2) {
1122 // caveat: no instructionmark, so this isn't relocatable.
1123 // Emit a synthetic, non-atomic, CAS equivalent.
1124 // Beware. The synthetic form sets all ICCs, not just ZF.
1125 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1126 cmpl(rax, adr);
1127 movl(rax, adr);
1128 if (reg != rax) {
1129 Label L ;
1130 jcc(Assembler::notEqual, L);
1131 movl(adr, reg);
1132 bind(L);
1133 }
1134 } else {
1135 InstructionMark im(this);
1136 prefix(adr, reg);
1137 emit_byte(0x0F);
1138 emit_byte(0xB1);
1139 emit_operand(reg, adr);
1140 }
1141 }
1142
1143 void Assembler::comisd(XMMRegister dst, Address src) {
1144 // NOTE: dbx seems to decode this as comiss even though the
1145 // 0x66 is there. Strangly ucomisd comes out correct
1146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1147 emit_byte(0x66);
1148 comiss(dst, src);
1149 }
1150
1151 void Assembler::comiss(XMMRegister dst, Address src) {
1152 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1153
1154 InstructionMark im(this);
1155 prefix(src, dst);
1156 emit_byte(0x0F);
1157 emit_byte(0x2F);
1158 emit_operand(dst, src);
1159 }
1160
1161 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1162 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1163 emit_byte(0xF3);
1164 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1165 emit_byte(0x0F);
1166 emit_byte(0xE6);
1167 emit_byte(0xC0 | encode);
1168 }
1169
1170 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1171 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1172 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1173 emit_byte(0x0F);
1174 emit_byte(0x5B);
1175 emit_byte(0xC0 | encode);
1176 }
1177
1178 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1179 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1180 emit_byte(0xF2);
1181 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1182 emit_byte(0x0F);
1183 emit_byte(0x5A);
1184 emit_byte(0xC0 | encode);
1185 }
1186
1187 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1188 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1189 emit_byte(0xF2);
1190 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1191 emit_byte(0x0F);
1192 emit_byte(0x2A);
1193 emit_byte(0xC0 | encode);
1194 }
1195
1196 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1197 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1198 emit_byte(0xF3);
1199 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1200 emit_byte(0x0F);
1201 emit_byte(0x2A);
1202 emit_byte(0xC0 | encode);
1203 }
1204
1205 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1207 emit_byte(0xF3);
1208 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1209 emit_byte(0x0F);
1210 emit_byte(0x5A);
1211 emit_byte(0xC0 | encode);
1212 }
1213
1214 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1215 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1216 emit_byte(0xF2);
1217 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1218 emit_byte(0x0F);
1219 emit_byte(0x2C);
1220 emit_byte(0xC0 | encode);
1221 }
1222
1223 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1224 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1225 emit_byte(0xF3);
1226 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1227 emit_byte(0x0F);
1228 emit_byte(0x2C);
1229 emit_byte(0xC0 | encode);
1230 }
1231
1232 void Assembler::decl(Address dst) {
1233 // Don't use it directly. Use MacroAssembler::decrement() instead.
1234 InstructionMark im(this);
1235 prefix(dst);
1236 emit_byte(0xFF);
1237 emit_operand(rcx, dst);
1238 }
1239
1240 void Assembler::divsd(XMMRegister dst, Address src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionMark im(this);
1243 emit_byte(0xF2);
1244 prefix(src, dst);
1245 emit_byte(0x0F);
1246 emit_byte(0x5E);
1247 emit_operand(dst, src);
1248 }
1249
1250 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1251 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1252 emit_byte(0xF2);
1253 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1254 emit_byte(0x0F);
1255 emit_byte(0x5E);
1256 emit_byte(0xC0 | encode);
1257 }
1258
1259 void Assembler::divss(XMMRegister dst, Address src) {
1260 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1261 InstructionMark im(this);
1262 emit_byte(0xF3);
1263 prefix(src, dst);
1264 emit_byte(0x0F);
1265 emit_byte(0x5E);
1266 emit_operand(dst, src);
1267 }
1268
1269 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1270 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1271 emit_byte(0xF3);
1272 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1273 emit_byte(0x0F);
1274 emit_byte(0x5E);
1275 emit_byte(0xC0 | encode);
1276 }
1277
1278 void Assembler::emms() {
1279 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1280 emit_byte(0x0F);
1281 emit_byte(0x77);
1282 }
1283
1284 void Assembler::hlt() {
1285 emit_byte(0xF4);
1286 }
1287
1288 void Assembler::idivl(Register src) {
1289 int encode = prefix_and_encode(src->encoding());
1290 emit_byte(0xF7);
1291 emit_byte(0xF8 | encode);
1292 }
1293
1294 void Assembler::imull(Register dst, Register src) {
1295 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1296 emit_byte(0x0F);
1297 emit_byte(0xAF);
1298 emit_byte(0xC0 | encode);
1299 }
1300
1301
1302 void Assembler::imull(Register dst, Register src, int value) {
1303 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1304 if (is8bit(value)) {
1305 emit_byte(0x6B);
1306 emit_byte(0xC0 | encode);
1307 emit_byte(value);
1308 } else {
1309 emit_byte(0x69);
1310 emit_byte(0xC0 | encode);
1311 emit_long(value);
1312 }
1313 }
1314
1315 void Assembler::incl(Address dst) {
1316 // Don't use it directly. Use MacroAssembler::increment() instead.
1317 InstructionMark im(this);
1318 prefix(dst);
1319 emit_byte(0xFF);
1320 emit_operand(rax, dst);
1321 }
1322
1323 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1324 InstructionMark im(this);
1325 relocate(rtype);
1326 assert((0 <= cc) && (cc < 16), "illegal cc");
1327 if (L.is_bound()) {
1328 address dst = target(L);
1329 assert(dst != NULL, "jcc most probably wrong");
1330
1331 const int short_size = 2;
1332 const int long_size = 6;
1333 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1334 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1335 // 0111 tttn #8-bit disp
1336 emit_byte(0x70 | cc);
1337 emit_byte((offs - short_size) & 0xFF);
1338 } else {
1339 // 0000 1111 1000 tttn #32-bit disp
1340 assert(is_simm32(offs - long_size),
1341 "must be 32bit offset (call4)");
1342 emit_byte(0x0F);
1343 emit_byte(0x80 | cc);
1344 emit_long(offs - long_size);
1345 }
1346 } else {
1347 // Note: could eliminate cond. jumps to this jump if condition
1348 // is the same however, seems to be rather unlikely case.
1349 // Note: use jccb() if label to be bound is very close to get
1350 // an 8-bit displacement
1351 L.add_patch_at(code(), locator());
1352 emit_byte(0x0F);
1353 emit_byte(0x80 | cc);
1354 emit_long(0);
1355 }
1356 }
1357
1358 void Assembler::jccb(Condition cc, Label& L) {
1359 if (L.is_bound()) {
1360 const int short_size = 2;
1361 address entry = target(L);
1362 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1363 "Dispacement too large for a short jmp");
1364 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1365 // 0111 tttn #8-bit disp
1366 emit_byte(0x70 | cc);
1367 emit_byte((offs - short_size) & 0xFF);
1368 } else {
1369 InstructionMark im(this);
1370 L.add_patch_at(code(), locator());
1371 emit_byte(0x70 | cc);
1372 emit_byte(0);
1373 }
1374 }
1375
1376 void Assembler::jmp(Address adr) {
1377 InstructionMark im(this);
1378 prefix(adr);
1379 emit_byte(0xFF);
1380 emit_operand(rsp, adr);
1381 }
1382
1383 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1384 if (L.is_bound()) {
1385 address entry = target(L);
1386 assert(entry != NULL, "jmp most probably wrong");
1387 InstructionMark im(this);
1388 const int short_size = 2;
1389 const int long_size = 5;
1390 intptr_t offs = entry - _code_pos;
1391 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1392 emit_byte(0xEB);
1393 emit_byte((offs - short_size) & 0xFF);
1394 } else {
1395 emit_byte(0xE9);
1396 emit_long(offs - long_size);
1397 }
1398 } else {
1399 // By default, forward jumps are always 32-bit displacements, since
1400 // we can't yet know where the label will be bound. If you're sure that
1401 // the forward jump will not run beyond 256 bytes, use jmpb to
1402 // force an 8-bit displacement.
1403 InstructionMark im(this);
1404 relocate(rtype);
1405 L.add_patch_at(code(), locator());
1406 emit_byte(0xE9);
1407 emit_long(0);
1408 }
1409 }
1410
1411 void Assembler::jmp(Register entry) {
1412 int encode = prefix_and_encode(entry->encoding());
1413 emit_byte(0xFF);
1414 emit_byte(0xE0 | encode);
1415 }
1416
1417 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1418 InstructionMark im(this);
1419 emit_byte(0xE9);
1420 assert(dest != NULL, "must have a target");
1421 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1422 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1423 emit_data(disp, rspec.reloc(), call32_operand);
1424 }
1425
1426 void Assembler::jmpb(Label& L) {
1427 if (L.is_bound()) {
1428 const int short_size = 2;
1429 address entry = target(L);
1430 assert(is8bit((entry - _code_pos) + short_size),
1431 "Dispacement too large for a short jmp");
1432 assert(entry != NULL, "jmp most probably wrong");
1433 intptr_t offs = entry - _code_pos;
1434 emit_byte(0xEB);
1435 emit_byte((offs - short_size) & 0xFF);
1436 } else {
1437 InstructionMark im(this);
1438 L.add_patch_at(code(), locator());
1439 emit_byte(0xEB);
1440 emit_byte(0);
1441 }
1442 }
1443
1444 void Assembler::ldmxcsr( Address src) {
1445 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1446 InstructionMark im(this);
1447 prefix(src);
1448 emit_byte(0x0F);
1449 emit_byte(0xAE);
1450 emit_operand(as_Register(2), src);
1451 }
1452
1453 void Assembler::leal(Register dst, Address src) {
1454 InstructionMark im(this);
1455 #ifdef _LP64
1456 emit_byte(0x67); // addr32
1457 prefix(src, dst);
1458 #endif // LP64
1459 emit_byte(0x8D);
1460 emit_operand(dst, src);
1461 }
1462
1463 void Assembler::lock() {
1464 if (Atomics & 1) {
1465 // Emit either nothing, a NOP, or a NOP: prefix
1466 emit_byte(0x90) ;
1467 } else {
1468 emit_byte(0xF0);
1469 }
1470 }
1471
1472 void Assembler::lzcntl(Register dst, Register src) {
1473 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1474 emit_byte(0xF3);
1475 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1476 emit_byte(0x0F);
1477 emit_byte(0xBD);
1478 emit_byte(0xC0 | encode);
1479 }
1480
1481 // Emit mfence instruction
1482 void Assembler::mfence() {
1483 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1484 emit_byte( 0x0F );
1485 emit_byte( 0xAE );
1486 emit_byte( 0xF0 );
1487 }
1488
1489 void Assembler::mov(Register dst, Register src) {
1490 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1491 }
1492
1493 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1495 int dstenc = dst->encoding();
1496 int srcenc = src->encoding();
1497 emit_byte(0x66);
1498 if (dstenc < 8) {
1499 if (srcenc >= 8) {
1500 prefix(REX_B);
1501 srcenc -= 8;
1502 }
1503 } else {
1504 if (srcenc < 8) {
1505 prefix(REX_R);
1506 } else {
1507 prefix(REX_RB);
1508 srcenc -= 8;
1509 }
1510 dstenc -= 8;
1511 }
1512 emit_byte(0x0F);
1513 emit_byte(0x28);
1514 emit_byte(0xC0 | dstenc << 3 | srcenc);
1515 }
1516
1517 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1518 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1519 int dstenc = dst->encoding();
1520 int srcenc = src->encoding();
1521 if (dstenc < 8) {
1522 if (srcenc >= 8) {
1523 prefix(REX_B);
1524 srcenc -= 8;
1525 }
1526 } else {
1527 if (srcenc < 8) {
1528 prefix(REX_R);
1529 } else {
1530 prefix(REX_RB);
1531 srcenc -= 8;
1532 }
1533 dstenc -= 8;
1534 }
1535 emit_byte(0x0F);
1536 emit_byte(0x28);
1537 emit_byte(0xC0 | dstenc << 3 | srcenc);
1538 }
1539
1540 void Assembler::movb(Register dst, Address src) {
1541 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1542 InstructionMark im(this);
1543 prefix(src, dst, true);
1544 emit_byte(0x8A);
1545 emit_operand(dst, src);
1546 }
1547
1548
1549 void Assembler::movb(Address dst, int imm8) {
1550 InstructionMark im(this);
1551 prefix(dst);
1552 emit_byte(0xC6);
1553 emit_operand(rax, dst, 1);
1554 emit_byte(imm8);
1555 }
1556
1557
1558 void Assembler::movb(Address dst, Register src) {
1559 assert(src->has_byte_register(), "must have byte register");
1560 InstructionMark im(this);
1561 prefix(dst, src, true);
1562 emit_byte(0x88);
1563 emit_operand(src, dst);
1564 }
1565
1566 void Assembler::movdl(XMMRegister dst, Register src) {
1567 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1568 emit_byte(0x66);
1569 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1570 emit_byte(0x0F);
1571 emit_byte(0x6E);
1572 emit_byte(0xC0 | encode);
1573 }
1574
1575 void Assembler::movdl(Register dst, XMMRegister src) {
1576 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1577 emit_byte(0x66);
1578 // swap src/dst to get correct prefix
1579 int encode = prefix_and_encode(src->encoding(), dst->encoding());
1580 emit_byte(0x0F);
1581 emit_byte(0x7E);
1582 emit_byte(0xC0 | encode);
1583 }
1584
1585 void Assembler::movdqa(XMMRegister dst, Address src) {
1586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1587 InstructionMark im(this);
1588 emit_byte(0x66);
1589 prefix(src, dst);
1590 emit_byte(0x0F);
1591 emit_byte(0x6F);
1592 emit_operand(dst, src);
1593 }
1594
1595 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1597 emit_byte(0x66);
1598 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1599 emit_byte(0x0F);
1600 emit_byte(0x6F);
1601 emit_byte(0xC0 | encode);
1602 }
1603
1604 void Assembler::movdqa(Address dst, XMMRegister src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 InstructionMark im(this);
1607 emit_byte(0x66);
1608 prefix(dst, src);
1609 emit_byte(0x0F);
1610 emit_byte(0x7F);
1611 emit_operand(src, dst);
1612 }
1613
1614 void Assembler::movdqu(XMMRegister dst, Address src) {
1615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1616 InstructionMark im(this);
1617 emit_byte(0xF3);
1618 prefix(src, dst);
1619 emit_byte(0x0F);
1620 emit_byte(0x6F);
1621 emit_operand(dst, src);
1622 }
1623
1624 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1626 emit_byte(0xF3);
1627 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1628 emit_byte(0x0F);
1629 emit_byte(0x6F);
1630 emit_byte(0xC0 | encode);
1631 }
1632
1633 void Assembler::movdqu(Address dst, XMMRegister src) {
1634 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1635 InstructionMark im(this);
1636 emit_byte(0xF3);
1637 prefix(dst, src);
1638 emit_byte(0x0F);
1639 emit_byte(0x7F);
1640 emit_operand(src, dst);
1641 }
1642
1643 // Uses zero extension on 64bit
1644
1645 void Assembler::movl(Register dst, int32_t imm32) {
1646 int encode = prefix_and_encode(dst->encoding());
1647 emit_byte(0xB8 | encode);
1648 emit_long(imm32);
1649 }
1650
1651 void Assembler::movl(Register dst, Register src) {
1652 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1653 emit_byte(0x8B);
1654 emit_byte(0xC0 | encode);
1655 }
1656
1657 void Assembler::movl(Register dst, Address src) {
1658 InstructionMark im(this);
1659 prefix(src, dst);
1660 emit_byte(0x8B);
1661 emit_operand(dst, src);
1662 }
1663
1664 void Assembler::movl(Address dst, int32_t imm32) {
1665 InstructionMark im(this);
1666 prefix(dst);
1667 emit_byte(0xC7);
1668 emit_operand(rax, dst, 4);
1669 emit_long(imm32);
1670 }
1671
1672 void Assembler::movl(Address dst, Register src) {
1673 InstructionMark im(this);
1674 prefix(dst, src);
1675 emit_byte(0x89);
1676 emit_operand(src, dst);
1677 }
1678
1679 // New cpus require to use movsd and movss to avoid partial register stall
1680 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1681 // The selection is done in MacroAssembler::movdbl() and movflt().
1682 void Assembler::movlpd(XMMRegister dst, Address src) {
1683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1684 InstructionMark im(this);
1685 emit_byte(0x66);
1686 prefix(src, dst);
1687 emit_byte(0x0F);
1688 emit_byte(0x12);
1689 emit_operand(dst, src);
1690 }
1691
1692 void Assembler::movq( MMXRegister dst, Address src ) {
1693 assert( VM_Version::supports_mmx(), "" );
1694 emit_byte(0x0F);
1695 emit_byte(0x6F);
1696 emit_operand(dst, src);
1697 }
1698
1699 void Assembler::movq( Address dst, MMXRegister src ) {
1700 assert( VM_Version::supports_mmx(), "" );
1701 emit_byte(0x0F);
1702 emit_byte(0x7F);
1703 // workaround gcc (3.2.1-7a) bug
1704 // In that version of gcc with only an emit_operand(MMX, Address)
1705 // gcc will tail jump and try and reverse the parameters completely
1706 // obliterating dst in the process. By having a version available
1707 // that doesn't need to swap the args at the tail jump the bug is
1708 // avoided.
1709 emit_operand(dst, src);
1710 }
1711
1712 void Assembler::movq(XMMRegister dst, Address src) {
1713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1714 InstructionMark im(this);
1715 emit_byte(0xF3);
1716 prefix(src, dst);
1717 emit_byte(0x0F);
1718 emit_byte(0x7E);
1719 emit_operand(dst, src);
1720 }
1721
1722 void Assembler::movq(Address dst, XMMRegister src) {
1723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1724 InstructionMark im(this);
1725 emit_byte(0x66);
1726 prefix(dst, src);
1727 emit_byte(0x0F);
1728 emit_byte(0xD6);
1729 emit_operand(src, dst);
1730 }
1731
1732 void Assembler::movsbl(Register dst, Address src) { // movsxb
1733 InstructionMark im(this);
1734 prefix(src, dst);
1735 emit_byte(0x0F);
1736 emit_byte(0xBE);
1737 emit_operand(dst, src);
1738 }
1739
1740 void Assembler::movsbl(Register dst, Register src) { // movsxb
1741 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1742 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1743 emit_byte(0x0F);
1744 emit_byte(0xBE);
1745 emit_byte(0xC0 | encode);
1746 }
1747
1748 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1750 emit_byte(0xF2);
1751 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1752 emit_byte(0x0F);
1753 emit_byte(0x10);
1754 emit_byte(0xC0 | encode);
1755 }
1756
1757 void Assembler::movsd(XMMRegister dst, Address src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionMark im(this);
1760 emit_byte(0xF2);
1761 prefix(src, dst);
1762 emit_byte(0x0F);
1763 emit_byte(0x10);
1764 emit_operand(dst, src);
1765 }
1766
1767 void Assembler::movsd(Address dst, XMMRegister src) {
1768 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1769 InstructionMark im(this);
1770 emit_byte(0xF2);
1771 prefix(dst, src);
1772 emit_byte(0x0F);
1773 emit_byte(0x11);
1774 emit_operand(src, dst);
1775 }
1776
1777 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1778 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1779 emit_byte(0xF3);
1780 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1781 emit_byte(0x0F);
1782 emit_byte(0x10);
1783 emit_byte(0xC0 | encode);
1784 }
1785
1786 void Assembler::movss(XMMRegister dst, Address src) {
1787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1788 InstructionMark im(this);
1789 emit_byte(0xF3);
1790 prefix(src, dst);
1791 emit_byte(0x0F);
1792 emit_byte(0x10);
1793 emit_operand(dst, src);
1794 }
1795
1796 void Assembler::movss(Address dst, XMMRegister src) {
1797 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1798 InstructionMark im(this);
1799 emit_byte(0xF3);
1800 prefix(dst, src);
1801 emit_byte(0x0F);
1802 emit_byte(0x11);
1803 emit_operand(src, dst);
1804 }
1805
1806 void Assembler::movswl(Register dst, Address src) { // movsxw
1807 InstructionMark im(this);
1808 prefix(src, dst);
1809 emit_byte(0x0F);
1810 emit_byte(0xBF);
1811 emit_operand(dst, src);
1812 }
1813
1814 void Assembler::movswl(Register dst, Register src) { // movsxw
1815 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1816 emit_byte(0x0F);
1817 emit_byte(0xBF);
1818 emit_byte(0xC0 | encode);
1819 }
1820
1821 void Assembler::movw(Address dst, int imm16) {
1822 InstructionMark im(this);
1823
1824 emit_byte(0x66); // switch to 16-bit mode
1825 prefix(dst);
1826 emit_byte(0xC7);
1827 emit_operand(rax, dst, 2);
1828 emit_word(imm16);
1829 }
1830
1831 void Assembler::movw(Register dst, Address src) {
1832 InstructionMark im(this);
1833 emit_byte(0x66);
1834 prefix(src, dst);
1835 emit_byte(0x8B);
1836 emit_operand(dst, src);
1837 }
1838
1839 void Assembler::movw(Address dst, Register src) {
1840 InstructionMark im(this);
1841 emit_byte(0x66);
1842 prefix(dst, src);
1843 emit_byte(0x89);
1844 emit_operand(src, dst);
1845 }
1846
1847 void Assembler::movzbl(Register dst, Address src) { // movzxb
1848 InstructionMark im(this);
1849 prefix(src, dst);
1850 emit_byte(0x0F);
1851 emit_byte(0xB6);
1852 emit_operand(dst, src);
1853 }
1854
1855 void Assembler::movzbl(Register dst, Register src) { // movzxb
1856 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1857 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1858 emit_byte(0x0F);
1859 emit_byte(0xB6);
1860 emit_byte(0xC0 | encode);
1861 }
1862
1863 void Assembler::movzwl(Register dst, Address src) { // movzxw
1864 InstructionMark im(this);
1865 prefix(src, dst);
1866 emit_byte(0x0F);
1867 emit_byte(0xB7);
1868 emit_operand(dst, src);
1869 }
1870
1871 void Assembler::movzwl(Register dst, Register src) { // movzxw
1872 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1873 emit_byte(0x0F);
1874 emit_byte(0xB7);
1875 emit_byte(0xC0 | encode);
1876 }
1877
1878 void Assembler::mull(Address src) {
1879 InstructionMark im(this);
1880 prefix(src);
1881 emit_byte(0xF7);
1882 emit_operand(rsp, src);
1883 }
1884
1885 void Assembler::mull(Register src) {
1886 int encode = prefix_and_encode(src->encoding());
1887 emit_byte(0xF7);
1888 emit_byte(0xE0 | encode);
1889 }
1890
1891 void Assembler::mulsd(XMMRegister dst, Address src) {
1892 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1893 InstructionMark im(this);
1894 emit_byte(0xF2);
1895 prefix(src, dst);
1896 emit_byte(0x0F);
1897 emit_byte(0x59);
1898 emit_operand(dst, src);
1899 }
1900
1901 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1903 emit_byte(0xF2);
1904 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1905 emit_byte(0x0F);
1906 emit_byte(0x59);
1907 emit_byte(0xC0 | encode);
1908 }
1909
1910 void Assembler::mulss(XMMRegister dst, Address src) {
1911 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1912 InstructionMark im(this);
1913 emit_byte(0xF3);
1914 prefix(src, dst);
1915 emit_byte(0x0F);
1916 emit_byte(0x59);
1917 emit_operand(dst, src);
1918 }
1919
1920 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1922 emit_byte(0xF3);
1923 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1924 emit_byte(0x0F);
1925 emit_byte(0x59);
1926 emit_byte(0xC0 | encode);
1927 }
1928
1929 void Assembler::negl(Register dst) {
1930 int encode = prefix_and_encode(dst->encoding());
1931 emit_byte(0xF7);
1932 emit_byte(0xD8 | encode);
1933 }
1934
1935 void Assembler::nop(int i) {
1936 #ifdef ASSERT
1937 assert(i > 0, " ");
1938 // The fancy nops aren't currently recognized by debuggers making it a
1939 // pain to disassemble code while debugging. If asserts are on clearly
1940 // speed is not an issue so simply use the single byte traditional nop
1941 // to do alignment.
1942
1943 for (; i > 0 ; i--) emit_byte(0x90);
1944 return;
1945
1946 #endif // ASSERT
1947
1948 if (UseAddressNop && VM_Version::is_intel()) {
1949 //
1950 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1951 // 1: 0x90
1952 // 2: 0x66 0x90
1953 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1954 // 4: 0x0F 0x1F 0x40 0x00
1955 // 5: 0x0F 0x1F 0x44 0x00 0x00
1956 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1957 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1958 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1959 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1960 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1961 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1962
1963 // The rest coding is Intel specific - don't use consecutive address nops
1964
1965 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1966 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1967 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1968 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1969
1970 while(i >= 15) {
1971 // For Intel don't generate consecutive addess nops (mix with regular nops)
1972 i -= 15;
1973 emit_byte(0x66); // size prefix
1974 emit_byte(0x66); // size prefix
1975 emit_byte(0x66); // size prefix
1976 addr_nop_8();
1977 emit_byte(0x66); // size prefix
1978 emit_byte(0x66); // size prefix
1979 emit_byte(0x66); // size prefix
1980 emit_byte(0x90); // nop
1981 }
1982 switch (i) {
1983 case 14:
1984 emit_byte(0x66); // size prefix
1985 case 13:
1986 emit_byte(0x66); // size prefix
1987 case 12:
1988 addr_nop_8();
1989 emit_byte(0x66); // size prefix
1990 emit_byte(0x66); // size prefix
1991 emit_byte(0x66); // size prefix
1992 emit_byte(0x90); // nop
1993 break;
1994 case 11:
1995 emit_byte(0x66); // size prefix
1996 case 10:
1997 emit_byte(0x66); // size prefix
1998 case 9:
1999 emit_byte(0x66); // size prefix
2000 case 8:
2001 addr_nop_8();
2002 break;
2003 case 7:
2004 addr_nop_7();
2005 break;
2006 case 6:
2007 emit_byte(0x66); // size prefix
2008 case 5:
2009 addr_nop_5();
2010 break;
2011 case 4:
2012 addr_nop_4();
2013 break;
2014 case 3:
2015 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2016 emit_byte(0x66); // size prefix
2017 case 2:
2018 emit_byte(0x66); // size prefix
2019 case 1:
2020 emit_byte(0x90); // nop
2021 break;
2022 default:
2023 assert(i == 0, " ");
2024 }
2025 return;
2026 }
2027 if (UseAddressNop && VM_Version::is_amd()) {
2028 //
2029 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2030 // 1: 0x90
2031 // 2: 0x66 0x90
2032 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2033 // 4: 0x0F 0x1F 0x40 0x00
2034 // 5: 0x0F 0x1F 0x44 0x00 0x00
2035 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2036 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2037 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2038 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2039 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2040 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2041
2042 // The rest coding is AMD specific - use consecutive address nops
2043
2044 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2045 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2046 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2047 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2048 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2049 // Size prefixes (0x66) are added for larger sizes
2050
2051 while(i >= 22) {
2052 i -= 11;
2053 emit_byte(0x66); // size prefix
2054 emit_byte(0x66); // size prefix
2055 emit_byte(0x66); // size prefix
2056 addr_nop_8();
2057 }
2058 // Generate first nop for size between 21-12
2059 switch (i) {
2060 case 21:
2061 i -= 1;
2062 emit_byte(0x66); // size prefix
2063 case 20:
2064 case 19:
2065 i -= 1;
2066 emit_byte(0x66); // size prefix
2067 case 18:
2068 case 17:
2069 i -= 1;
2070 emit_byte(0x66); // size prefix
2071 case 16:
2072 case 15:
2073 i -= 8;
2074 addr_nop_8();
2075 break;
2076 case 14:
2077 case 13:
2078 i -= 7;
2079 addr_nop_7();
2080 break;
2081 case 12:
2082 i -= 6;
2083 emit_byte(0x66); // size prefix
2084 addr_nop_5();
2085 break;
2086 default:
2087 assert(i < 12, " ");
2088 }
2089
2090 // Generate second nop for size between 11-1
2091 switch (i) {
2092 case 11:
2093 emit_byte(0x66); // size prefix
2094 case 10:
2095 emit_byte(0x66); // size prefix
2096 case 9:
2097 emit_byte(0x66); // size prefix
2098 case 8:
2099 addr_nop_8();
2100 break;
2101 case 7:
2102 addr_nop_7();
2103 break;
2104 case 6:
2105 emit_byte(0x66); // size prefix
2106 case 5:
2107 addr_nop_5();
2108 break;
2109 case 4:
2110 addr_nop_4();
2111 break;
2112 case 3:
2113 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2114 emit_byte(0x66); // size prefix
2115 case 2:
2116 emit_byte(0x66); // size prefix
2117 case 1:
2118 emit_byte(0x90); // nop
2119 break;
2120 default:
2121 assert(i == 0, " ");
2122 }
2123 return;
2124 }
2125
2126 // Using nops with size prefixes "0x66 0x90".
2127 // From AMD Optimization Guide:
2128 // 1: 0x90
2129 // 2: 0x66 0x90
2130 // 3: 0x66 0x66 0x90
2131 // 4: 0x66 0x66 0x66 0x90
2132 // 5: 0x66 0x66 0x90 0x66 0x90
2133 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2134 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2135 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2136 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2137 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2138 //
2139 while(i > 12) {
2140 i -= 4;
2141 emit_byte(0x66); // size prefix
2142 emit_byte(0x66);
2143 emit_byte(0x66);
2144 emit_byte(0x90); // nop
2145 }
2146 // 1 - 12 nops
2147 if(i > 8) {
2148 if(i > 9) {
2149 i -= 1;
2150 emit_byte(0x66);
2151 }
2152 i -= 3;
2153 emit_byte(0x66);
2154 emit_byte(0x66);
2155 emit_byte(0x90);
2156 }
2157 // 1 - 8 nops
2158 if(i > 4) {
2159 if(i > 6) {
2160 i -= 1;
2161 emit_byte(0x66);
2162 }
2163 i -= 3;
2164 emit_byte(0x66);
2165 emit_byte(0x66);
2166 emit_byte(0x90);
2167 }
2168 switch (i) {
2169 case 4:
2170 emit_byte(0x66);
2171 case 3:
2172 emit_byte(0x66);
2173 case 2:
2174 emit_byte(0x66);
2175 case 1:
2176 emit_byte(0x90);
2177 break;
2178 default:
2179 assert(i == 0, " ");
2180 }
2181 }
2182
2183 void Assembler::notl(Register dst) {
2184 int encode = prefix_and_encode(dst->encoding());
2185 emit_byte(0xF7);
2186 emit_byte(0xD0 | encode );
2187 }
2188
2189 void Assembler::orl(Address dst, int32_t imm32) {
2190 InstructionMark im(this);
2191 prefix(dst);
2192 emit_byte(0x81);
2193 emit_operand(rcx, dst, 4);
2194 emit_long(imm32);
2195 }
2196
2197 void Assembler::orl(Register dst, int32_t imm32) {
2198 prefix(dst);
2199 emit_arith(0x81, 0xC8, dst, imm32);
2200 }
2201
2202
2203 void Assembler::orl(Register dst, Address src) {
2204 InstructionMark im(this);
2205 prefix(src, dst);
2206 emit_byte(0x0B);
2207 emit_operand(dst, src);
2208 }
2209
2210
2211 void Assembler::orl(Register dst, Register src) {
2212 (void) prefix_and_encode(dst->encoding(), src->encoding());
2213 emit_arith(0x0B, 0xC0, dst, src);
2214 }
2215
2216 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2217 assert(VM_Version::supports_sse4_2(), "");
2218
2219 InstructionMark im(this);
2220 emit_byte(0x66);
2221 prefix(src, dst);
2222 emit_byte(0x0F);
2223 emit_byte(0x3A);
2224 emit_byte(0x61);
2225 emit_operand(dst, src);
2226 emit_byte(imm8);
2227 }
2228
2229 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2230 assert(VM_Version::supports_sse4_2(), "");
2231
2232 emit_byte(0x66);
2233 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2234 emit_byte(0x0F);
2235 emit_byte(0x3A);
2236 emit_byte(0x61);
2237 emit_byte(0xC0 | encode);
2238 emit_byte(imm8);
2239 }
2240
2241 // generic
2242 void Assembler::pop(Register dst) {
2243 int encode = prefix_and_encode(dst->encoding());
2244 emit_byte(0x58 | encode);
2245 }
2246
2247 void Assembler::popcntl(Register dst, Address src) {
2248 assert(VM_Version::supports_popcnt(), "must support");
2249 InstructionMark im(this);
2250 emit_byte(0xF3);
2251 prefix(src, dst);
2252 emit_byte(0x0F);
2253 emit_byte(0xB8);
2254 emit_operand(dst, src);
2255 }
2256
2257 void Assembler::popcntl(Register dst, Register src) {
2258 assert(VM_Version::supports_popcnt(), "must support");
2259 emit_byte(0xF3);
2260 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2261 emit_byte(0x0F);
2262 emit_byte(0xB8);
2263 emit_byte(0xC0 | encode);
2264 }
2265
2266 void Assembler::popf() {
2267 emit_byte(0x9D);
2268 }
2269
2270 #ifndef _LP64 // no 32bit push/pop on amd64
2271 void Assembler::popl(Address dst) {
2272 // NOTE: this will adjust stack by 8byte on 64bits
2273 InstructionMark im(this);
2274 prefix(dst);
2275 emit_byte(0x8F);
2276 emit_operand(rax, dst);
2277 }
2278 #endif
2279
2280 void Assembler::prefetch_prefix(Address src) {
2281 prefix(src);
2282 emit_byte(0x0F);
2283 }
2284
2285 void Assembler::prefetchnta(Address src) {
2286 NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
2287 InstructionMark im(this);
2288 prefetch_prefix(src);
2289 emit_byte(0x18);
2290 emit_operand(rax, src); // 0, src
2291 }
2292
2293 void Assembler::prefetchr(Address src) {
2294 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2295 InstructionMark im(this);
2296 prefetch_prefix(src);
2297 emit_byte(0x0D);
2298 emit_operand(rax, src); // 0, src
2299 }
2300
2301 void Assembler::prefetcht0(Address src) {
2302 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2303 InstructionMark im(this);
2304 prefetch_prefix(src);
2305 emit_byte(0x18);
2306 emit_operand(rcx, src); // 1, src
2307 }
2308
2309 void Assembler::prefetcht1(Address src) {
2310 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2311 InstructionMark im(this);
2312 prefetch_prefix(src);
2313 emit_byte(0x18);
2314 emit_operand(rdx, src); // 2, src
2315 }
2316
2317 void Assembler::prefetcht2(Address src) {
2318 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2319 InstructionMark im(this);
2320 prefetch_prefix(src);
2321 emit_byte(0x18);
2322 emit_operand(rbx, src); // 3, src
2323 }
2324
2325 void Assembler::prefetchw(Address src) {
2326 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2327 InstructionMark im(this);
2328 prefetch_prefix(src);
2329 emit_byte(0x0D);
2330 emit_operand(rcx, src); // 1, src
2331 }
2332
2333 void Assembler::prefix(Prefix p) {
2334 a_byte(p);
2335 }
2336
2337 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2338 assert(isByte(mode), "invalid value");
2339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2340
2341 emit_byte(0x66);
2342 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2343 emit_byte(0x0F);
2344 emit_byte(0x70);
2345 emit_byte(0xC0 | encode);
2346 emit_byte(mode & 0xFF);
2347
2348 }
2349
2350 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2351 assert(isByte(mode), "invalid value");
2352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2353
2354 InstructionMark im(this);
2355 emit_byte(0x66);
2356 prefix(src, dst);
2357 emit_byte(0x0F);
2358 emit_byte(0x70);
2359 emit_operand(dst, src);
2360 emit_byte(mode & 0xFF);
2361 }
2362
2363 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2364 assert(isByte(mode), "invalid value");
2365 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2366
2367 emit_byte(0xF2);
2368 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2369 emit_byte(0x0F);
2370 emit_byte(0x70);
2371 emit_byte(0xC0 | encode);
2372 emit_byte(mode & 0xFF);
2373 }
2374
2375 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2376 assert(isByte(mode), "invalid value");
2377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2378
2379 InstructionMark im(this);
2380 emit_byte(0xF2);
2381 prefix(src, dst); // QQ new
2382 emit_byte(0x0F);
2383 emit_byte(0x70);
2384 emit_operand(dst, src);
2385 emit_byte(mode & 0xFF);
2386 }
2387
2388 void Assembler::psrlq(XMMRegister dst, int shift) {
2389 // HMM Table D-1 says sse2 or mmx
2390 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2391
2392 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
2393 emit_byte(0x66);
2394 emit_byte(0x0F);
2395 emit_byte(0x73);
2396 emit_byte(0xC0 | encode);
2397 emit_byte(shift);
2398 }
2399
2400 void Assembler::ptest(XMMRegister dst, Address src) {
2401 assert(VM_Version::supports_sse4_1(), "");
2402
2403 InstructionMark im(this);
2404 emit_byte(0x66);
2405 prefix(src, dst);
2406 emit_byte(0x0F);
2407 emit_byte(0x38);
2408 emit_byte(0x17);
2409 emit_operand(dst, src);
2410 }
2411
2412 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2413 assert(VM_Version::supports_sse4_1(), "");
2414
2415 emit_byte(0x66);
2416 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2417 emit_byte(0x0F);
2418 emit_byte(0x38);
2419 emit_byte(0x17);
2420 emit_byte(0xC0 | encode);
2421 }
2422
2423 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2424 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2425 emit_byte(0x66);
2426 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2427 emit_byte(0x0F);
2428 emit_byte(0x60);
2429 emit_byte(0xC0 | encode);
2430 }
2431
2432 void Assembler::push(int32_t imm32) {
2433 // in 64bits we push 64bits onto the stack but only
2434 // take a 32bit immediate
2435 emit_byte(0x68);
2436 emit_long(imm32);
2437 }
2438
2439 void Assembler::push(Register src) {
2440 int encode = prefix_and_encode(src->encoding());
2441
2442 emit_byte(0x50 | encode);
2443 }
2444
2445 void Assembler::pushf() {
2446 emit_byte(0x9C);
2447 }
2448
2449 #ifndef _LP64 // no 32bit push/pop on amd64
2450 void Assembler::pushl(Address src) {
2451 // Note this will push 64bit on 64bit
2452 InstructionMark im(this);
2453 prefix(src);
2454 emit_byte(0xFF);
2455 emit_operand(rsi, src);
2456 }
2457 #endif
2458
2459 void Assembler::pxor(XMMRegister dst, Address src) {
2460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2461 InstructionMark im(this);
2462 emit_byte(0x66);
2463 prefix(src, dst);
2464 emit_byte(0x0F);
2465 emit_byte(0xEF);
2466 emit_operand(dst, src);
2467 }
2468
2469 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2470 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2471 InstructionMark im(this);
2472 emit_byte(0x66);
2473 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2474 emit_byte(0x0F);
2475 emit_byte(0xEF);
2476 emit_byte(0xC0 | encode);
2477 }
2478
2479 void Assembler::rcll(Register dst, int imm8) {
2480 assert(isShiftCount(imm8), "illegal shift count");
2481 int encode = prefix_and_encode(dst->encoding());
2482 if (imm8 == 1) {
2483 emit_byte(0xD1);
2484 emit_byte(0xD0 | encode);
2485 } else {
2486 emit_byte(0xC1);
2487 emit_byte(0xD0 | encode);
2488 emit_byte(imm8);
2489 }
2490 }
2491
2492 // copies data from [esi] to [edi] using rcx pointer sized words
2493 // generic
2494 void Assembler::rep_mov() {
2495 emit_byte(0xF3);
2496 // MOVSQ
2497 LP64_ONLY(prefix(REX_W));
2498 emit_byte(0xA5);
2499 }
2500
2501 // sets rcx pointer sized words with rax, value at [edi]
2502 // generic
2503 void Assembler::rep_set() { // rep_set
2504 emit_byte(0xF3);
2505 // STOSQ
2506 LP64_ONLY(prefix(REX_W));
2507 emit_byte(0xAB);
2508 }
2509
2510 // scans rcx pointer sized words at [edi] for occurance of rax,
2511 // generic
2512 void Assembler::repne_scan() { // repne_scan
2513 emit_byte(0xF2);
2514 // SCASQ
2515 LP64_ONLY(prefix(REX_W));
2516 emit_byte(0xAF);
2517 }
2518
2519 #ifdef _LP64
2520 // scans rcx 4 byte words at [edi] for occurance of rax,
2521 // generic
2522 void Assembler::repne_scanl() { // repne_scan
2523 emit_byte(0xF2);
2524 // SCASL
2525 emit_byte(0xAF);
2526 }
2527 #endif
2528
2529 void Assembler::ret(int imm16) {
2530 if (imm16 == 0) {
2531 emit_byte(0xC3);
2532 } else {
2533 emit_byte(0xC2);
2534 emit_word(imm16);
2535 }
2536 }
2537
2538 void Assembler::sahf() {
2539 #ifdef _LP64
2540 // Not supported in 64bit mode
2541 ShouldNotReachHere();
2542 #endif
2543 emit_byte(0x9E);
2544 }
2545
2546 void Assembler::sarl(Register dst, int imm8) {
2547 int encode = prefix_and_encode(dst->encoding());
2548 assert(isShiftCount(imm8), "illegal shift count");
2549 if (imm8 == 1) {
2550 emit_byte(0xD1);
2551 emit_byte(0xF8 | encode);
2552 } else {
2553 emit_byte(0xC1);
2554 emit_byte(0xF8 | encode);
2555 emit_byte(imm8);
2556 }
2557 }
2558
2559 void Assembler::sarl(Register dst) {
2560 int encode = prefix_and_encode(dst->encoding());
2561 emit_byte(0xD3);
2562 emit_byte(0xF8 | encode);
2563 }
2564
2565 void Assembler::sbbl(Address dst, int32_t imm32) {
2566 InstructionMark im(this);
2567 prefix(dst);
2568 emit_arith_operand(0x81, rbx, dst, imm32);
2569 }
2570
2571 void Assembler::sbbl(Register dst, int32_t imm32) {
2572 prefix(dst);
2573 emit_arith(0x81, 0xD8, dst, imm32);
2574 }
2575
2576
2577 void Assembler::sbbl(Register dst, Address src) {
2578 InstructionMark im(this);
2579 prefix(src, dst);
2580 emit_byte(0x1B);
2581 emit_operand(dst, src);
2582 }
2583
2584 void Assembler::sbbl(Register dst, Register src) {
2585 (void) prefix_and_encode(dst->encoding(), src->encoding());
2586 emit_arith(0x1B, 0xC0, dst, src);
2587 }
2588
2589 void Assembler::setb(Condition cc, Register dst) {
2590 assert(0 <= cc && cc < 16, "illegal cc");
2591 int encode = prefix_and_encode(dst->encoding(), true);
2592 emit_byte(0x0F);
2593 emit_byte(0x90 | cc);
2594 emit_byte(0xC0 | encode);
2595 }
2596
2597 void Assembler::shll(Register dst, int imm8) {
2598 assert(isShiftCount(imm8), "illegal shift count");
2599 int encode = prefix_and_encode(dst->encoding());
2600 if (imm8 == 1 ) {
2601 emit_byte(0xD1);
2602 emit_byte(0xE0 | encode);
2603 } else {
2604 emit_byte(0xC1);
2605 emit_byte(0xE0 | encode);
2606 emit_byte(imm8);
2607 }
2608 }
2609
2610 void Assembler::shll(Register dst) {
2611 int encode = prefix_and_encode(dst->encoding());
2612 emit_byte(0xD3);
2613 emit_byte(0xE0 | encode);
2614 }
2615
2616 void Assembler::shrl(Register dst, int imm8) {
2617 assert(isShiftCount(imm8), "illegal shift count");
2618 int encode = prefix_and_encode(dst->encoding());
2619 emit_byte(0xC1);
2620 emit_byte(0xE8 | encode);
2621 emit_byte(imm8);
2622 }
2623
2624 void Assembler::shrl(Register dst) {
2625 int encode = prefix_and_encode(dst->encoding());
2626 emit_byte(0xD3);
2627 emit_byte(0xE8 | encode);
2628 }
2629
2630 // copies a single word from [esi] to [edi]
2631 void Assembler::smovl() {
2632 emit_byte(0xA5);
2633 }
2634
2635 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2636 // HMM Table D-1 says sse2
2637 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2639 emit_byte(0xF2);
2640 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2641 emit_byte(0x0F);
2642 emit_byte(0x51);
2643 emit_byte(0xC0 | encode);
2644 }
2645
2646 void Assembler::stmxcsr( Address dst) {
2647 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2648 InstructionMark im(this);
2649 prefix(dst);
2650 emit_byte(0x0F);
2651 emit_byte(0xAE);
2652 emit_operand(as_Register(3), dst);
2653 }
2654
2655 void Assembler::subl(Address dst, int32_t imm32) {
2656 InstructionMark im(this);
2657 prefix(dst);
2658 if (is8bit(imm32)) {
2659 emit_byte(0x83);
2660 emit_operand(rbp, dst, 1);
2661 emit_byte(imm32 & 0xFF);
2662 } else {
2663 emit_byte(0x81);
2664 emit_operand(rbp, dst, 4);
2665 emit_long(imm32);
2666 }
2667 }
2668
2669 void Assembler::subl(Register dst, int32_t imm32) {
2670 prefix(dst);
2671 emit_arith(0x81, 0xE8, dst, imm32);
2672 }
2673
2674 void Assembler::subl(Address dst, Register src) {
2675 InstructionMark im(this);
2676 prefix(dst, src);
2677 emit_byte(0x29);
2678 emit_operand(src, dst);
2679 }
2680
2681 void Assembler::subl(Register dst, Address src) {
2682 InstructionMark im(this);
2683 prefix(src, dst);
2684 emit_byte(0x2B);
2685 emit_operand(dst, src);
2686 }
2687
2688 void Assembler::subl(Register dst, Register src) {
2689 (void) prefix_and_encode(dst->encoding(), src->encoding());
2690 emit_arith(0x2B, 0xC0, dst, src);
2691 }
2692
2693 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2695 emit_byte(0xF2);
2696 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2697 emit_byte(0x0F);
2698 emit_byte(0x5C);
2699 emit_byte(0xC0 | encode);
2700 }
2701
2702 void Assembler::subsd(XMMRegister dst, Address src) {
2703 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2704 InstructionMark im(this);
2705 emit_byte(0xF2);
2706 prefix(src, dst);
2707 emit_byte(0x0F);
2708 emit_byte(0x5C);
2709 emit_operand(dst, src);
2710 }
2711
2712 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2713 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2714 emit_byte(0xF3);
2715 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2716 emit_byte(0x0F);
2717 emit_byte(0x5C);
2718 emit_byte(0xC0 | encode);
2719 }
2720
2721 void Assembler::subss(XMMRegister dst, Address src) {
2722 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2723 InstructionMark im(this);
2724 emit_byte(0xF3);
2725 prefix(src, dst);
2726 emit_byte(0x0F);
2727 emit_byte(0x5C);
2728 emit_operand(dst, src);
2729 }
2730
2731 void Assembler::testb(Register dst, int imm8) {
2732 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2733 (void) prefix_and_encode(dst->encoding(), true);
2734 emit_arith_b(0xF6, 0xC0, dst, imm8);
2735 }
2736
2737 void Assembler::testl(Register dst, int32_t imm32) {
2738 // not using emit_arith because test
2739 // doesn't support sign-extension of
2740 // 8bit operands
2741 int encode = dst->encoding();
2742 if (encode == 0) {
2743 emit_byte(0xA9);
2744 } else {
2745 encode = prefix_and_encode(encode);
2746 emit_byte(0xF7);
2747 emit_byte(0xC0 | encode);
2748 }
2749 emit_long(imm32);
2750 }
2751
2752 void Assembler::testl(Register dst, Register src) {
2753 (void) prefix_and_encode(dst->encoding(), src->encoding());
2754 emit_arith(0x85, 0xC0, dst, src);
2755 }
2756
2757 void Assembler::testl(Register dst, Address src) {
2758 InstructionMark im(this);
2759 prefix(src, dst);
2760 emit_byte(0x85);
2761 emit_operand(dst, src);
2762 }
2763
2764 void Assembler::ucomisd(XMMRegister dst, Address src) {
2765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2766 emit_byte(0x66);
2767 ucomiss(dst, src);
2768 }
2769
2770 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2772 emit_byte(0x66);
2773 ucomiss(dst, src);
2774 }
2775
2776 void Assembler::ucomiss(XMMRegister dst, Address src) {
2777 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2778
2779 InstructionMark im(this);
2780 prefix(src, dst);
2781 emit_byte(0x0F);
2782 emit_byte(0x2E);
2783 emit_operand(dst, src);
2784 }
2785
2786 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2788 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2789 emit_byte(0x0F);
2790 emit_byte(0x2E);
2791 emit_byte(0xC0 | encode);
2792 }
2793
2794
2795 void Assembler::xaddl(Address dst, Register src) {
2796 InstructionMark im(this);
2797 prefix(dst, src);
2798 emit_byte(0x0F);
2799 emit_byte(0xC1);
2800 emit_operand(src, dst);
2801 }
2802
2803 void Assembler::xchgl(Register dst, Address src) { // xchg
2804 InstructionMark im(this);
2805 prefix(src, dst);
2806 emit_byte(0x87);
2807 emit_operand(dst, src);
2808 }
2809
2810 void Assembler::xchgl(Register dst, Register src) {
2811 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2812 emit_byte(0x87);
2813 emit_byte(0xc0 | encode);
2814 }
2815
2816 void Assembler::xorl(Register dst, int32_t imm32) {
2817 prefix(dst);
2818 emit_arith(0x81, 0xF0, dst, imm32);
2819 }
2820
2821 void Assembler::xorl(Register dst, Address src) {
2822 InstructionMark im(this);
2823 prefix(src, dst);
2824 emit_byte(0x33);
2825 emit_operand(dst, src);
2826 }
2827
2828 void Assembler::xorl(Register dst, Register src) {
2829 (void) prefix_and_encode(dst->encoding(), src->encoding());
2830 emit_arith(0x33, 0xC0, dst, src);
2831 }
2832
2833 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2834 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2835 emit_byte(0x66);
2836 xorps(dst, src);
2837 }
2838
2839 void Assembler::xorpd(XMMRegister dst, Address src) {
2840 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2841 InstructionMark im(this);
2842 emit_byte(0x66);
2843 prefix(src, dst);
2844 emit_byte(0x0F);
2845 emit_byte(0x57);
2846 emit_operand(dst, src);
2847 }
2848
2849
2850 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2851 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2852 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2853 emit_byte(0x0F);
2854 emit_byte(0x57);
2855 emit_byte(0xC0 | encode);
2856 }
2857
2858 void Assembler::xorps(XMMRegister dst, Address src) {
2859 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2860 InstructionMark im(this);
2861 prefix(src, dst);
2862 emit_byte(0x0F);
2863 emit_byte(0x57);
2864 emit_operand(dst, src);
2865 }
2866
2867 #ifndef _LP64
2868 // 32bit only pieces of the assembler
2869
2870 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2871 // NO PREFIX AS NEVER 64BIT
2872 InstructionMark im(this);
2873 emit_byte(0x81);
2874 emit_byte(0xF8 | src1->encoding());
2875 emit_data(imm32, rspec, 0);
2876 }
2877
2878 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2879 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2880 InstructionMark im(this);
2881 emit_byte(0x81);
2882 emit_operand(rdi, src1);
2883 emit_data(imm32, rspec, 0);
2884 }
2885
2886 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
2887 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
2888 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
2889 void Assembler::cmpxchg8(Address adr) {
2890 InstructionMark im(this);
2891 emit_byte(0x0F);
2892 emit_byte(0xc7);
2893 emit_operand(rcx, adr);
2894 }
2895
2896 void Assembler::decl(Register dst) {
2897 // Don't use it directly. Use MacroAssembler::decrementl() instead.
2898 emit_byte(0x48 | dst->encoding());
2899 }
2900
2901 #endif // _LP64
2902
2903 // 64bit typically doesn't use the x87 but needs to for the trig funcs
2904
2905 void Assembler::fabs() {
2906 emit_byte(0xD9);
2907 emit_byte(0xE1);
2908 }
2909
2910 void Assembler::fadd(int i) {
2911 emit_farith(0xD8, 0xC0, i);
2912 }
2913
2914 void Assembler::fadd_d(Address src) {
2915 InstructionMark im(this);
2916 emit_byte(0xDC);
2917 emit_operand32(rax, src);
2918 }
2919
2920 void Assembler::fadd_s(Address src) {
2921 InstructionMark im(this);
2922 emit_byte(0xD8);
2923 emit_operand32(rax, src);
2924 }
2925
2926 void Assembler::fadda(int i) {
2927 emit_farith(0xDC, 0xC0, i);
2928 }
2929
2930 void Assembler::faddp(int i) {
2931 emit_farith(0xDE, 0xC0, i);
2932 }
2933
2934 void Assembler::fchs() {
2935 emit_byte(0xD9);
2936 emit_byte(0xE0);
2937 }
2938
2939 void Assembler::fcom(int i) {
2940 emit_farith(0xD8, 0xD0, i);
2941 }
2942
2943 void Assembler::fcomp(int i) {
2944 emit_farith(0xD8, 0xD8, i);
2945 }
2946
2947 void Assembler::fcomp_d(Address src) {
2948 InstructionMark im(this);
2949 emit_byte(0xDC);
2950 emit_operand32(rbx, src);
2951 }
2952
2953 void Assembler::fcomp_s(Address src) {
2954 InstructionMark im(this);
2955 emit_byte(0xD8);
2956 emit_operand32(rbx, src);
2957 }
2958
2959 void Assembler::fcompp() {
2960 emit_byte(0xDE);
2961 emit_byte(0xD9);
2962 }
2963
2964 void Assembler::fcos() {
2965 emit_byte(0xD9);
2966 emit_byte(0xFF);
2967 }
2968
2969 void Assembler::fdecstp() {
2970 emit_byte(0xD9);
2971 emit_byte(0xF6);
2972 }
2973
2974 void Assembler::fdiv(int i) {
2975 emit_farith(0xD8, 0xF0, i);
2976 }
2977
2978 void Assembler::fdiv_d(Address src) {
2979 InstructionMark im(this);
2980 emit_byte(0xDC);
2981 emit_operand32(rsi, src);
2982 }
2983
2984 void Assembler::fdiv_s(Address src) {
2985 InstructionMark im(this);
2986 emit_byte(0xD8);
2987 emit_operand32(rsi, src);
2988 }
2989
2990 void Assembler::fdiva(int i) {
2991 emit_farith(0xDC, 0xF8, i);
2992 }
2993
2994 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
2995 // is erroneous for some of the floating-point instructions below.
2996
2997 void Assembler::fdivp(int i) {
2998 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
2999 }
3000
3001 void Assembler::fdivr(int i) {
3002 emit_farith(0xD8, 0xF8, i);
3003 }
3004
3005 void Assembler::fdivr_d(Address src) {
3006 InstructionMark im(this);
3007 emit_byte(0xDC);
3008 emit_operand32(rdi, src);
3009 }
3010
3011 void Assembler::fdivr_s(Address src) {
3012 InstructionMark im(this);
3013 emit_byte(0xD8);
3014 emit_operand32(rdi, src);
3015 }
3016
3017 void Assembler::fdivra(int i) {
3018 emit_farith(0xDC, 0xF0, i);
3019 }
3020
3021 void Assembler::fdivrp(int i) {
3022 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3023 }
3024
3025 void Assembler::ffree(int i) {
3026 emit_farith(0xDD, 0xC0, i);
3027 }
3028
3029 void Assembler::fild_d(Address adr) {
3030 InstructionMark im(this);
3031 emit_byte(0xDF);
3032 emit_operand32(rbp, adr);
3033 }
3034
3035 void Assembler::fild_s(Address adr) {
3036 InstructionMark im(this);
3037 emit_byte(0xDB);
3038 emit_operand32(rax, adr);
3039 }
3040
3041 void Assembler::fincstp() {
3042 emit_byte(0xD9);
3043 emit_byte(0xF7);
3044 }
3045
3046 void Assembler::finit() {
3047 emit_byte(0x9B);
3048 emit_byte(0xDB);
3049 emit_byte(0xE3);
3050 }
3051
3052 void Assembler::fist_s(Address adr) {
3053 InstructionMark im(this);
3054 emit_byte(0xDB);
3055 emit_operand32(rdx, adr);
3056 }
3057
3058 void Assembler::fistp_d(Address adr) {
3059 InstructionMark im(this);
3060 emit_byte(0xDF);
3061 emit_operand32(rdi, adr);
3062 }
3063
3064 void Assembler::fistp_s(Address adr) {
3065 InstructionMark im(this);
3066 emit_byte(0xDB);
3067 emit_operand32(rbx, adr);
3068 }
3069
3070 void Assembler::fld1() {
3071 emit_byte(0xD9);
3072 emit_byte(0xE8);
3073 }
3074
3075 void Assembler::fld_d(Address adr) {
3076 InstructionMark im(this);
3077 emit_byte(0xDD);
3078 emit_operand32(rax, adr);
3079 }
3080
3081 void Assembler::fld_s(Address adr) {
3082 InstructionMark im(this);
3083 emit_byte(0xD9);
3084 emit_operand32(rax, adr);
3085 }
3086
3087
3088 void Assembler::fld_s(int index) {
3089 emit_farith(0xD9, 0xC0, index);
3090 }
3091
3092 void Assembler::fld_x(Address adr) {
3093 InstructionMark im(this);
3094 emit_byte(0xDB);
3095 emit_operand32(rbp, adr);
3096 }
3097
3098 void Assembler::fldcw(Address src) {
3099 InstructionMark im(this);
3100 emit_byte(0xd9);
3101 emit_operand32(rbp, src);
3102 }
3103
3104 void Assembler::fldenv(Address src) {
3105 InstructionMark im(this);
3106 emit_byte(0xD9);
3107 emit_operand32(rsp, src);
3108 }
3109
3110 void Assembler::fldlg2() {
3111 emit_byte(0xD9);
3112 emit_byte(0xEC);
3113 }
3114
3115 void Assembler::fldln2() {
3116 emit_byte(0xD9);
3117 emit_byte(0xED);
3118 }
3119
3120 void Assembler::fldz() {
3121 emit_byte(0xD9);
3122 emit_byte(0xEE);
3123 }
3124
3125 void Assembler::flog() {
3126 fldln2();
3127 fxch();
3128 fyl2x();
3129 }
3130
3131 void Assembler::flog10() {
3132 fldlg2();
3133 fxch();
3134 fyl2x();
3135 }
3136
3137 void Assembler::fmul(int i) {
3138 emit_farith(0xD8, 0xC8, i);
3139 }
3140
3141 void Assembler::fmul_d(Address src) {
3142 InstructionMark im(this);
3143 emit_byte(0xDC);
3144 emit_operand32(rcx, src);
3145 }
3146
3147 void Assembler::fmul_s(Address src) {
3148 InstructionMark im(this);
3149 emit_byte(0xD8);
3150 emit_operand32(rcx, src);
3151 }
3152
3153 void Assembler::fmula(int i) {
3154 emit_farith(0xDC, 0xC8, i);
3155 }
3156
3157 void Assembler::fmulp(int i) {
3158 emit_farith(0xDE, 0xC8, i);
3159 }
3160
3161 void Assembler::fnsave(Address dst) {
3162 InstructionMark im(this);
3163 emit_byte(0xDD);
3164 emit_operand32(rsi, dst);
3165 }
3166
3167 void Assembler::fnstcw(Address src) {
3168 InstructionMark im(this);
3169 emit_byte(0x9B);
3170 emit_byte(0xD9);
3171 emit_operand32(rdi, src);
3172 }
3173
3174 void Assembler::fnstsw_ax() {
3175 emit_byte(0xdF);
3176 emit_byte(0xE0);
3177 }
3178
3179 void Assembler::fprem() {
3180 emit_byte(0xD9);
3181 emit_byte(0xF8);
3182 }
3183
3184 void Assembler::fprem1() {
3185 emit_byte(0xD9);
3186 emit_byte(0xF5);
3187 }
3188
3189 void Assembler::frstor(Address src) {
3190 InstructionMark im(this);
3191 emit_byte(0xDD);
3192 emit_operand32(rsp, src);
3193 }
3194
3195 void Assembler::fsin() {
3196 emit_byte(0xD9);
3197 emit_byte(0xFE);
3198 }
3199
3200 void Assembler::fsqrt() {
3201 emit_byte(0xD9);
3202 emit_byte(0xFA);
3203 }
3204
3205 void Assembler::fst_d(Address adr) {
3206 InstructionMark im(this);
3207 emit_byte(0xDD);
3208 emit_operand32(rdx, adr);
3209 }
3210
3211 void Assembler::fst_s(Address adr) {
3212 InstructionMark im(this);
3213 emit_byte(0xD9);
3214 emit_operand32(rdx, adr);
3215 }
3216
3217 void Assembler::fstp_d(Address adr) {
3218 InstructionMark im(this);
3219 emit_byte(0xDD);
3220 emit_operand32(rbx, adr);
3221 }
3222
3223 void Assembler::fstp_d(int index) {
3224 emit_farith(0xDD, 0xD8, index);
3225 }
3226
3227 void Assembler::fstp_s(Address adr) {
3228 InstructionMark im(this);
3229 emit_byte(0xD9);
3230 emit_operand32(rbx, adr);
3231 }
3232
3233 void Assembler::fstp_x(Address adr) {
3234 InstructionMark im(this);
3235 emit_byte(0xDB);
3236 emit_operand32(rdi, adr);
3237 }
3238
3239 void Assembler::fsub(int i) {
3240 emit_farith(0xD8, 0xE0, i);
3241 }
3242
3243 void Assembler::fsub_d(Address src) {
3244 InstructionMark im(this);
3245 emit_byte(0xDC);
3246 emit_operand32(rsp, src);
3247 }
3248
3249 void Assembler::fsub_s(Address src) {
3250 InstructionMark im(this);
3251 emit_byte(0xD8);
3252 emit_operand32(rsp, src);
3253 }
3254
3255 void Assembler::fsuba(int i) {
3256 emit_farith(0xDC, 0xE8, i);
3257 }
3258
3259 void Assembler::fsubp(int i) {
3260 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3261 }
3262
3263 void Assembler::fsubr(int i) {
3264 emit_farith(0xD8, 0xE8, i);
3265 }
3266
3267 void Assembler::fsubr_d(Address src) {
3268 InstructionMark im(this);
3269 emit_byte(0xDC);
3270 emit_operand32(rbp, src);
3271 }
3272
3273 void Assembler::fsubr_s(Address src) {
3274 InstructionMark im(this);
3275 emit_byte(0xD8);
3276 emit_operand32(rbp, src);
3277 }
3278
3279 void Assembler::fsubra(int i) {
3280 emit_farith(0xDC, 0xE0, i);
3281 }
3282
3283 void Assembler::fsubrp(int i) {
3284 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3285 }
3286
3287 void Assembler::ftan() {
3288 emit_byte(0xD9);
3289 emit_byte(0xF2);
3290 emit_byte(0xDD);
3291 emit_byte(0xD8);
3292 }
3293
3294 void Assembler::ftst() {
3295 emit_byte(0xD9);
3296 emit_byte(0xE4);
3297 }
3298
3299 void Assembler::fucomi(int i) {
3300 // make sure the instruction is supported (introduced for P6, together with cmov)
3301 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3302 emit_farith(0xDB, 0xE8, i);
3303 }
3304
3305 void Assembler::fucomip(int i) {
3306 // make sure the instruction is supported (introduced for P6, together with cmov)
3307 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3308 emit_farith(0xDF, 0xE8, i);
3309 }
3310
3311 void Assembler::fwait() {
3312 emit_byte(0x9B);
3313 }
3314
3315 void Assembler::fxch(int i) {
3316 emit_farith(0xD9, 0xC8, i);
3317 }
3318
3319 void Assembler::fyl2x() {
3320 emit_byte(0xD9);
3321 emit_byte(0xF1);
3322 }
3323
3324
3325 #ifndef _LP64
3326
3327 void Assembler::incl(Register dst) {
3328 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3329 emit_byte(0x40 | dst->encoding());
3330 }
3331
3332 void Assembler::lea(Register dst, Address src) {
3333 leal(dst, src);
3334 }
3335
3336 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3337 InstructionMark im(this);
3338 emit_byte(0xC7);
3339 emit_operand(rax, dst);
3340 emit_data((int)imm32, rspec, 0);
3341 }
3342
3343 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3344 InstructionMark im(this);
3345 int encode = prefix_and_encode(dst->encoding());
3346 emit_byte(0xB8 | encode);
3347 emit_data((int)imm32, rspec, 0);
3348 }
3349
3350 void Assembler::popa() { // 32bit
3351 emit_byte(0x61);
3352 }
3353
3354 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3355 InstructionMark im(this);
3356 emit_byte(0x68);
3357 emit_data(imm32, rspec, 0);
3358 }
3359
3360 void Assembler::pusha() { // 32bit
3361 emit_byte(0x60);
3362 }
3363
3364 void Assembler::set_byte_if_not_zero(Register dst) {
3365 emit_byte(0x0F);
3366 emit_byte(0x95);
3367 emit_byte(0xE0 | dst->encoding());
3368 }
3369
3370 void Assembler::shldl(Register dst, Register src) {
3371 emit_byte(0x0F);
3372 emit_byte(0xA5);
3373 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3374 }
3375
3376 void Assembler::shrdl(Register dst, Register src) {
3377 emit_byte(0x0F);
3378 emit_byte(0xAD);
3379 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3380 }
3381
3382 #else // LP64
3383
3384 void Assembler::set_byte_if_not_zero(Register dst) {
3385 int enc = prefix_and_encode(dst->encoding(), true);
3386 emit_byte(0x0F);
3387 emit_byte(0x95);
3388 emit_byte(0xE0 | enc);
3389 }
3390
3391 // 64bit only pieces of the assembler
3392 // This should only be used by 64bit instructions that can use rip-relative
3393 // it cannot be used by instructions that want an immediate value.
3394
3395 bool Assembler::reachable(AddressLiteral adr) {
3396 int64_t disp;
3397 // None will force a 64bit literal to the code stream. Likely a placeholder
3398 // for something that will be patched later and we need to certain it will
3399 // always be reachable.
3400 if (adr.reloc() == relocInfo::none) {
3401 return false;
3402 }
3403 if (adr.reloc() == relocInfo::internal_word_type) {
3404 // This should be rip relative and easily reachable.
3405 return true;
3406 }
3407 if (adr.reloc() == relocInfo::virtual_call_type ||
3408 adr.reloc() == relocInfo::opt_virtual_call_type ||
3409 adr.reloc() == relocInfo::static_call_type ||
3410 adr.reloc() == relocInfo::static_stub_type ) {
3411 // This should be rip relative within the code cache and easily
3412 // reachable until we get huge code caches. (At which point
3413 // ic code is going to have issues).
3414 return true;
3415 }
3416 if (adr.reloc() != relocInfo::external_word_type &&
3417 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3418 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3419 adr.reloc() != relocInfo::runtime_call_type ) {
3420 return false;
3421 }
3422
3423 // Stress the correction code
3424 if (ForceUnreachable) {
3425 // Must be runtimecall reloc, see if it is in the codecache
3426 // Flipping stuff in the codecache to be unreachable causes issues
3427 // with things like inline caches where the additional instructions
3428 // are not handled.
3429 if (CodeCache::find_blob(adr._target) == NULL) {
3430 return false;
3431 }
3432 }
3433 // For external_word_type/runtime_call_type if it is reachable from where we
3434 // are now (possibly a temp buffer) and where we might end up
3435 // anywhere in the codeCache then we are always reachable.
3436 // This would have to change if we ever save/restore shared code
3437 // to be more pessimistic.
3438
3439 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3440 if (!is_simm32(disp)) return false;
3441 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3442 if (!is_simm32(disp)) return false;
3443
3444 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3445
3446 // Because rip relative is a disp + address_of_next_instruction and we
3447 // don't know the value of address_of_next_instruction we apply a fudge factor
3448 // to make sure we will be ok no matter the size of the instruction we get placed into.
3449 // We don't have to fudge the checks above here because they are already worst case.
3450
3451 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3452 // + 4 because better safe than sorry.
3453 const int fudge = 12 + 4;
3454 if (disp < 0) {
3455 disp -= fudge;
3456 } else {
3457 disp += fudge;
3458 }
3459 return is_simm32(disp);
3460 }
3461
3462 void Assembler::emit_data64(jlong data,
3463 relocInfo::relocType rtype,
3464 int format) {
3465 if (rtype == relocInfo::none) {
3466 emit_long64(data);
3467 } else {
3468 emit_data64(data, Relocation::spec_simple(rtype), format);
3469 }
3470 }
3471
3472 void Assembler::emit_data64(jlong data,
3473 RelocationHolder const& rspec,
3474 int format) {
3475 assert(imm_operand == 0, "default format must be immediate in this file");
3476 assert(imm_operand == format, "must be immediate");
3477 assert(inst_mark() != NULL, "must be inside InstructionMark");
3478 // Do not use AbstractAssembler::relocate, which is not intended for
3479 // embedded words. Instead, relocate to the enclosing instruction.
3480 code_section()->relocate(inst_mark(), rspec, format);
3481 #ifdef ASSERT
3482 check_relocation(rspec, format);
3483 #endif
3484 emit_long64(data);
3485 }
3486
3487 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3488 if (reg_enc >= 8) {
3489 prefix(REX_B);
3490 reg_enc -= 8;
3491 } else if (byteinst && reg_enc >= 4) {
3492 prefix(REX);
3493 }
3494 return reg_enc;
3495 }
3496
3497 int Assembler::prefixq_and_encode(int reg_enc) {
3498 if (reg_enc < 8) {
3499 prefix(REX_W);
3500 } else {
3501 prefix(REX_WB);
3502 reg_enc -= 8;
3503 }
3504 return reg_enc;
3505 }
3506
3507 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3508 if (dst_enc < 8) {
3509 if (src_enc >= 8) {
3510 prefix(REX_B);
3511 src_enc -= 8;
3512 } else if (byteinst && src_enc >= 4) {
3513 prefix(REX);
3514 }
3515 } else {
3516 if (src_enc < 8) {
3517 prefix(REX_R);
3518 } else {
3519 prefix(REX_RB);
3520 src_enc -= 8;
3521 }
3522 dst_enc -= 8;
3523 }
3524 return dst_enc << 3 | src_enc;
3525 }
3526
3527 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
3528 if (dst_enc < 8) {
3529 if (src_enc < 8) {
3530 prefix(REX_W);
3531 } else {
3532 prefix(REX_WB);
3533 src_enc -= 8;
3534 }
3535 } else {
3536 if (src_enc < 8) {
3537 prefix(REX_WR);
3538 } else {
3539 prefix(REX_WRB);
3540 src_enc -= 8;
3541 }
3542 dst_enc -= 8;
3543 }
3544 return dst_enc << 3 | src_enc;
3545 }
3546
3547 void Assembler::prefix(Register reg) {
3548 if (reg->encoding() >= 8) {
3549 prefix(REX_B);
3550 }
3551 }
3552
3553 void Assembler::prefix(Address adr) {
3554 if (adr.base_needs_rex()) {
3555 if (adr.index_needs_rex()) {
3556 prefix(REX_XB);
3557 } else {
3558 prefix(REX_B);
3559 }
3560 } else {
3561 if (adr.index_needs_rex()) {
3562 prefix(REX_X);
3563 }
3564 }
3565 }
3566
3567 void Assembler::prefixq(Address adr) {
3568 if (adr.base_needs_rex()) {
3569 if (adr.index_needs_rex()) {
3570 prefix(REX_WXB);
3571 } else {
3572 prefix(REX_WB);
3573 }
3574 } else {
3575 if (adr.index_needs_rex()) {
3576 prefix(REX_WX);
3577 } else {
3578 prefix(REX_W);
3579 }
3580 }
3581 }
3582
3583
3584 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
3585 if (reg->encoding() < 8) {
3586 if (adr.base_needs_rex()) {
3587 if (adr.index_needs_rex()) {
3588 prefix(REX_XB);
3589 } else {
3590 prefix(REX_B);
3591 }
3592 } else {
3593 if (adr.index_needs_rex()) {
3594 prefix(REX_X);
3595 } else if (reg->encoding() >= 4 ) {
3596 prefix(REX);
3597 }
3598 }
3599 } else {
3600 if (adr.base_needs_rex()) {
3601 if (adr.index_needs_rex()) {
3602 prefix(REX_RXB);
3603 } else {
3604 prefix(REX_RB);
3605 }
3606 } else {
3607 if (adr.index_needs_rex()) {
3608 prefix(REX_RX);
3609 } else {
3610 prefix(REX_R);
3611 }
3612 }
3613 }
3614 }
3615
3616 void Assembler::prefixq(Address adr, Register src) {
3617 if (src->encoding() < 8) {
3618 if (adr.base_needs_rex()) {
3619 if (adr.index_needs_rex()) {
3620 prefix(REX_WXB);
3621 } else {
3622 prefix(REX_WB);
3623 }
3624 } else {
3625 if (adr.index_needs_rex()) {
3626 prefix(REX_WX);
3627 } else {
3628 prefix(REX_W);
3629 }
3630 }
3631 } else {
3632 if (adr.base_needs_rex()) {
3633 if (adr.index_needs_rex()) {
3634 prefix(REX_WRXB);
3635 } else {
3636 prefix(REX_WRB);
3637 }
3638 } else {
3639 if (adr.index_needs_rex()) {
3640 prefix(REX_WRX);
3641 } else {
3642 prefix(REX_WR);
3643 }
3644 }
3645 }
3646 }
3647
3648 void Assembler::prefix(Address adr, XMMRegister reg) {
3649 if (reg->encoding() < 8) {
3650 if (adr.base_needs_rex()) {
3651 if (adr.index_needs_rex()) {
3652 prefix(REX_XB);
3653 } else {
3654 prefix(REX_B);
3655 }
3656 } else {
3657 if (adr.index_needs_rex()) {
3658 prefix(REX_X);
3659 }
3660 }
3661 } else {
3662 if (adr.base_needs_rex()) {
3663 if (adr.index_needs_rex()) {
3664 prefix(REX_RXB);
3665 } else {
3666 prefix(REX_RB);
3667 }
3668 } else {
3669 if (adr.index_needs_rex()) {
3670 prefix(REX_RX);
3671 } else {
3672 prefix(REX_R);
3673 }
3674 }
3675 }
3676 }
3677
3678 void Assembler::adcq(Register dst, int32_t imm32) {
3679 (void) prefixq_and_encode(dst->encoding());
3680 emit_arith(0x81, 0xD0, dst, imm32);
3681 }
3682
3683 void Assembler::adcq(Register dst, Address src) {
3684 InstructionMark im(this);
3685 prefixq(src, dst);
3686 emit_byte(0x13);
3687 emit_operand(dst, src);
3688 }
3689
3690 void Assembler::adcq(Register dst, Register src) {
3691 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3692 emit_arith(0x13, 0xC0, dst, src);
3693 }
3694
3695 void Assembler::addq(Address dst, int32_t imm32) {
3696 InstructionMark im(this);
3697 prefixq(dst);
3698 emit_arith_operand(0x81, rax, dst,imm32);
3699 }
3700
3701 void Assembler::addq(Address dst, Register src) {
3702 InstructionMark im(this);
3703 prefixq(dst, src);
3704 emit_byte(0x01);
3705 emit_operand(src, dst);
3706 }
3707
3708 void Assembler::addq(Register dst, int32_t imm32) {
3709 (void) prefixq_and_encode(dst->encoding());
3710 emit_arith(0x81, 0xC0, dst, imm32);
3711 }
3712
3713 void Assembler::addq(Register dst, Address src) {
3714 InstructionMark im(this);
3715 prefixq(src, dst);
3716 emit_byte(0x03);
3717 emit_operand(dst, src);
3718 }
3719
3720 void Assembler::addq(Register dst, Register src) {
3721 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3722 emit_arith(0x03, 0xC0, dst, src);
3723 }
3724
3725 void Assembler::andq(Register dst, int32_t imm32) {
3726 (void) prefixq_and_encode(dst->encoding());
3727 emit_arith(0x81, 0xE0, dst, imm32);
3728 }
3729
3730 void Assembler::andq(Register dst, Address src) {
3731 InstructionMark im(this);
3732 prefixq(src, dst);
3733 emit_byte(0x23);
3734 emit_operand(dst, src);
3735 }
3736
3737 void Assembler::andq(Register dst, Register src) {
3738 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3739 emit_arith(0x23, 0xC0, dst, src);
3740 }
3741
3742 void Assembler::bsfq(Register dst, Register src) {
3743 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3744 emit_byte(0x0F);
3745 emit_byte(0xBC);
3746 emit_byte(0xC0 | encode);
3747 }
3748
3749 void Assembler::bsrq(Register dst, Register src) {
3750 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
3751 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3752 emit_byte(0x0F);
3753 emit_byte(0xBD);
3754 emit_byte(0xC0 | encode);
3755 }
3756
3757 void Assembler::bswapq(Register reg) {
3758 int encode = prefixq_and_encode(reg->encoding());
3759 emit_byte(0x0F);
3760 emit_byte(0xC8 | encode);
3761 }
3762
3763 void Assembler::cdqq() {
3764 prefix(REX_W);
3765 emit_byte(0x99);
3766 }
3767
3768 void Assembler::clflush(Address adr) {
3769 prefix(adr);
3770 emit_byte(0x0F);
3771 emit_byte(0xAE);
3772 emit_operand(rdi, adr);
3773 }
3774
3775 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3776 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3777 emit_byte(0x0F);
3778 emit_byte(0x40 | cc);
3779 emit_byte(0xC0 | encode);
3780 }
3781
3782 void Assembler::cmovq(Condition cc, Register dst, Address src) {
3783 InstructionMark im(this);
3784 prefixq(src, dst);
3785 emit_byte(0x0F);
3786 emit_byte(0x40 | cc);
3787 emit_operand(dst, src);
3788 }
3789
3790 void Assembler::cmpq(Address dst, int32_t imm32) {
3791 InstructionMark im(this);
3792 prefixq(dst);
3793 emit_byte(0x81);
3794 emit_operand(rdi, dst, 4);
3795 emit_long(imm32);
3796 }
3797
3798 void Assembler::cmpq(Register dst, int32_t imm32) {
3799 (void) prefixq_and_encode(dst->encoding());
3800 emit_arith(0x81, 0xF8, dst, imm32);
3801 }
3802
3803 void Assembler::cmpq(Address dst, Register src) {
3804 InstructionMark im(this);
3805 prefixq(dst, src);
3806 emit_byte(0x3B);
3807 emit_operand(src, dst);
3808 }
3809
3810 void Assembler::cmpq(Register dst, Register src) {
3811 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3812 emit_arith(0x3B, 0xC0, dst, src);
3813 }
3814
3815 void Assembler::cmpq(Register dst, Address src) {
3816 InstructionMark im(this);
3817 prefixq(src, dst);
3818 emit_byte(0x3B);
3819 emit_operand(dst, src);
3820 }
3821
3822 void Assembler::cmpxchgq(Register reg, Address adr) {
3823 InstructionMark im(this);
3824 prefixq(adr, reg);
3825 emit_byte(0x0F);
3826 emit_byte(0xB1);
3827 emit_operand(reg, adr);
3828 }
3829
3830 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
3831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3832 emit_byte(0xF2);
3833 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3834 emit_byte(0x0F);
3835 emit_byte(0x2A);
3836 emit_byte(0xC0 | encode);
3837 }
3838
3839 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
3840 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3841 emit_byte(0xF3);
3842 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3843 emit_byte(0x0F);
3844 emit_byte(0x2A);
3845 emit_byte(0xC0 | encode);
3846 }
3847
3848 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3850 emit_byte(0xF2);
3851 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3852 emit_byte(0x0F);
3853 emit_byte(0x2C);
3854 emit_byte(0xC0 | encode);
3855 }
3856
3857 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
3858 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3859 emit_byte(0xF3);
3860 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3861 emit_byte(0x0F);
3862 emit_byte(0x2C);
3863 emit_byte(0xC0 | encode);
3864 }
3865
3866 void Assembler::decl(Register dst) {
3867 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3868 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
3869 int encode = prefix_and_encode(dst->encoding());
3870 emit_byte(0xFF);
3871 emit_byte(0xC8 | encode);
3872 }
3873
3874 void Assembler::decq(Register dst) {
3875 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3876 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3877 int encode = prefixq_and_encode(dst->encoding());
3878 emit_byte(0xFF);
3879 emit_byte(0xC8 | encode);
3880 }
3881
3882 void Assembler::decq(Address dst) {
3883 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3884 InstructionMark im(this);
3885 prefixq(dst);
3886 emit_byte(0xFF);
3887 emit_operand(rcx, dst);
3888 }
3889
3890 void Assembler::fxrstor(Address src) {
3891 prefixq(src);
3892 emit_byte(0x0F);
3893 emit_byte(0xAE);
3894 emit_operand(as_Register(1), src);
3895 }
3896
3897 void Assembler::fxsave(Address dst) {
3898 prefixq(dst);
3899 emit_byte(0x0F);
3900 emit_byte(0xAE);
3901 emit_operand(as_Register(0), dst);
3902 }
3903
3904 void Assembler::idivq(Register src) {
3905 int encode = prefixq_and_encode(src->encoding());
3906 emit_byte(0xF7);
3907 emit_byte(0xF8 | encode);
3908 }
3909
3910 void Assembler::imulq(Register dst, Register src) {
3911 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3912 emit_byte(0x0F);
3913 emit_byte(0xAF);
3914 emit_byte(0xC0 | encode);
3915 }
3916
3917 void Assembler::imulq(Register dst, Register src, int value) {
3918 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3919 if (is8bit(value)) {
3920 emit_byte(0x6B);
3921 emit_byte(0xC0 | encode);
3922 emit_byte(value);
3923 } else {
3924 emit_byte(0x69);
3925 emit_byte(0xC0 | encode);
3926 emit_long(value);
3927 }
3928 }
3929
3930 void Assembler::incl(Register dst) {
3931 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3932 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3933 int encode = prefix_and_encode(dst->encoding());
3934 emit_byte(0xFF);
3935 emit_byte(0xC0 | encode);
3936 }
3937
3938 void Assembler::incq(Register dst) {
3939 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3940 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3941 int encode = prefixq_and_encode(dst->encoding());
3942 emit_byte(0xFF);
3943 emit_byte(0xC0 | encode);
3944 }
3945
3946 void Assembler::incq(Address dst) {
3947 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3948 InstructionMark im(this);
3949 prefixq(dst);
3950 emit_byte(0xFF);
3951 emit_operand(rax, dst);
3952 }
3953
3954 void Assembler::lea(Register dst, Address src) {
3955 leaq(dst, src);
3956 }
3957
3958 void Assembler::leaq(Register dst, Address src) {
3959 InstructionMark im(this);
3960 prefixq(src, dst);
3961 emit_byte(0x8D);
3962 emit_operand(dst, src);
3963 }
3964
3965 void Assembler::mov64(Register dst, int64_t imm64) {
3966 InstructionMark im(this);
3967 int encode = prefixq_and_encode(dst->encoding());
3968 emit_byte(0xB8 | encode);
3969 emit_long64(imm64);
3970 }
3971
3972 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
3973 InstructionMark im(this);
3974 int encode = prefixq_and_encode(dst->encoding());
3975 emit_byte(0xB8 | encode);
3976 emit_data64(imm64, rspec);
3977 }
3978
3979 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3980 InstructionMark im(this);
3981 int encode = prefix_and_encode(dst->encoding());
3982 emit_byte(0xB8 | encode);
3983 emit_data((int)imm32, rspec, narrow_oop_operand);
3984 }
3985
3986 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3987 InstructionMark im(this);
3988 prefix(dst);
3989 emit_byte(0xC7);
3990 emit_operand(rax, dst, 4);
3991 emit_data((int)imm32, rspec, narrow_oop_operand);
3992 }
3993
3994 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3995 InstructionMark im(this);
3996 int encode = prefix_and_encode(src1->encoding());
3997 emit_byte(0x81);
3998 emit_byte(0xF8 | encode);
3999 emit_data((int)imm32, rspec, narrow_oop_operand);
4000 }
4001
4002 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4003 InstructionMark im(this);
4004 prefix(src1);
4005 emit_byte(0x81);
4006 emit_operand(rax, src1, 4);
4007 emit_data((int)imm32, rspec, narrow_oop_operand);
4008 }
4009
4010 void Assembler::lzcntq(Register dst, Register src) {
4011 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4012 emit_byte(0xF3);
4013 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4014 emit_byte(0x0F);
4015 emit_byte(0xBD);
4016 emit_byte(0xC0 | encode);
4017 }
4018
4019 void Assembler::movdq(XMMRegister dst, Register src) {
4020 // table D-1 says MMX/SSE2
4021 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4022 emit_byte(0x66);
4023 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4024 emit_byte(0x0F);
4025 emit_byte(0x6E);
4026 emit_byte(0xC0 | encode);
4027 }
4028
4029 void Assembler::movdq(Register dst, XMMRegister src) {
4030 // table D-1 says MMX/SSE2
4031 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4032 emit_byte(0x66);
4033 // swap src/dst to get correct prefix
4034 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4035 emit_byte(0x0F);
4036 emit_byte(0x7E);
4037 emit_byte(0xC0 | encode);
4038 }
4039
4040 void Assembler::movq(Register dst, Register src) {
4041 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4042 emit_byte(0x8B);
4043 emit_byte(0xC0 | encode);
4044 }
4045
4046 void Assembler::movq(Register dst, Address src) {
4047 InstructionMark im(this);
4048 prefixq(src, dst);
4049 emit_byte(0x8B);
4050 emit_operand(dst, src);
4051 }
4052
4053 void Assembler::movq(Address dst, Register src) {
4054 InstructionMark im(this);
4055 prefixq(dst, src);
4056 emit_byte(0x89);
4057 emit_operand(src, dst);
4058 }
4059
4060 void Assembler::movsbq(Register dst, Address src) {
4061 InstructionMark im(this);
4062 prefixq(src, dst);
4063 emit_byte(0x0F);
4064 emit_byte(0xBE);
4065 emit_operand(dst, src);
4066 }
4067
4068 void Assembler::movsbq(Register dst, Register src) {
4069 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4070 emit_byte(0x0F);
4071 emit_byte(0xBE);
4072 emit_byte(0xC0 | encode);
4073 }
4074
4075 void Assembler::movslq(Register dst, int32_t imm32) {
4076 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4077 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4078 // as a result we shouldn't use until tested at runtime...
4079 ShouldNotReachHere();
4080 InstructionMark im(this);
4081 int encode = prefixq_and_encode(dst->encoding());
4082 emit_byte(0xC7 | encode);
4083 emit_long(imm32);
4084 }
4085
4086 void Assembler::movslq(Address dst, int32_t imm32) {
4087 assert(is_simm32(imm32), "lost bits");
4088 InstructionMark im(this);
4089 prefixq(dst);
4090 emit_byte(0xC7);
4091 emit_operand(rax, dst, 4);
4092 emit_long(imm32);
4093 }
4094
4095 void Assembler::movslq(Register dst, Address src) {
4096 InstructionMark im(this);
4097 prefixq(src, dst);
4098 emit_byte(0x63);
4099 emit_operand(dst, src);
4100 }
4101
4102 void Assembler::movslq(Register dst, Register src) {
4103 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4104 emit_byte(0x63);
4105 emit_byte(0xC0 | encode);
4106 }
4107
4108 void Assembler::movswq(Register dst, Address src) {
4109 InstructionMark im(this);
4110 prefixq(src, dst);
4111 emit_byte(0x0F);
4112 emit_byte(0xBF);
4113 emit_operand(dst, src);
4114 }
4115
4116 void Assembler::movswq(Register dst, Register src) {
4117 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4118 emit_byte(0x0F);
4119 emit_byte(0xBF);
4120 emit_byte(0xC0 | encode);
4121 }
4122
4123 void Assembler::movzbq(Register dst, Address src) {
4124 InstructionMark im(this);
4125 prefixq(src, dst);
4126 emit_byte(0x0F);
4127 emit_byte(0xB6);
4128 emit_operand(dst, src);
4129 }
4130
4131 void Assembler::movzbq(Register dst, Register src) {
4132 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4133 emit_byte(0x0F);
4134 emit_byte(0xB6);
4135 emit_byte(0xC0 | encode);
4136 }
4137
4138 void Assembler::movzwq(Register dst, Address src) {
4139 InstructionMark im(this);
4140 prefixq(src, dst);
4141 emit_byte(0x0F);
4142 emit_byte(0xB7);
4143 emit_operand(dst, src);
4144 }
4145
4146 void Assembler::movzwq(Register dst, Register src) {
4147 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4148 emit_byte(0x0F);
4149 emit_byte(0xB7);
4150 emit_byte(0xC0 | encode);
4151 }
4152
4153 void Assembler::negq(Register dst) {
4154 int encode = prefixq_and_encode(dst->encoding());
4155 emit_byte(0xF7);
4156 emit_byte(0xD8 | encode);
4157 }
4158
4159 void Assembler::notq(Register dst) {
4160 int encode = prefixq_and_encode(dst->encoding());
4161 emit_byte(0xF7);
4162 emit_byte(0xD0 | encode);
4163 }
4164
4165 void Assembler::orq(Address dst, int32_t imm32) {
4166 InstructionMark im(this);
4167 prefixq(dst);
4168 emit_byte(0x81);
4169 emit_operand(rcx, dst, 4);
4170 emit_long(imm32);
4171 }
4172
4173 void Assembler::orq(Register dst, int32_t imm32) {
4174 (void) prefixq_and_encode(dst->encoding());
4175 emit_arith(0x81, 0xC8, dst, imm32);
4176 }
4177
4178 void Assembler::orq(Register dst, Address src) {
4179 InstructionMark im(this);
4180 prefixq(src, dst);
4181 emit_byte(0x0B);
4182 emit_operand(dst, src);
4183 }
4184
4185 void Assembler::orq(Register dst, Register src) {
4186 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4187 emit_arith(0x0B, 0xC0, dst, src);
4188 }
4189
4190 void Assembler::popa() { // 64bit
4191 movq(r15, Address(rsp, 0));
4192 movq(r14, Address(rsp, wordSize));
4193 movq(r13, Address(rsp, 2 * wordSize));
4194 movq(r12, Address(rsp, 3 * wordSize));
4195 movq(r11, Address(rsp, 4 * wordSize));
4196 movq(r10, Address(rsp, 5 * wordSize));
4197 movq(r9, Address(rsp, 6 * wordSize));
4198 movq(r8, Address(rsp, 7 * wordSize));
4199 movq(rdi, Address(rsp, 8 * wordSize));
4200 movq(rsi, Address(rsp, 9 * wordSize));
4201 movq(rbp, Address(rsp, 10 * wordSize));
4202 // skip rsp
4203 movq(rbx, Address(rsp, 12 * wordSize));
4204 movq(rdx, Address(rsp, 13 * wordSize));
4205 movq(rcx, Address(rsp, 14 * wordSize));
4206 movq(rax, Address(rsp, 15 * wordSize));
4207
4208 addq(rsp, 16 * wordSize);
4209 }
4210
4211 void Assembler::popcntq(Register dst, Address src) {
4212 assert(VM_Version::supports_popcnt(), "must support");
4213 InstructionMark im(this);
4214 emit_byte(0xF3);
4215 prefixq(src, dst);
4216 emit_byte(0x0F);
4217 emit_byte(0xB8);
4218 emit_operand(dst, src);
4219 }
4220
4221 void Assembler::popcntq(Register dst, Register src) {
4222 assert(VM_Version::supports_popcnt(), "must support");
4223 emit_byte(0xF3);
4224 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4225 emit_byte(0x0F);
4226 emit_byte(0xB8);
4227 emit_byte(0xC0 | encode);
4228 }
4229
4230 void Assembler::popq(Address dst) {
4231 InstructionMark im(this);
4232 prefixq(dst);
4233 emit_byte(0x8F);
4234 emit_operand(rax, dst);
4235 }
4236
4237 void Assembler::pusha() { // 64bit
4238 // we have to store original rsp. ABI says that 128 bytes
4239 // below rsp are local scratch.
4240 movq(Address(rsp, -5 * wordSize), rsp);
4241
4242 subq(rsp, 16 * wordSize);
4243
4244 movq(Address(rsp, 15 * wordSize), rax);
4245 movq(Address(rsp, 14 * wordSize), rcx);
4246 movq(Address(rsp, 13 * wordSize), rdx);
4247 movq(Address(rsp, 12 * wordSize), rbx);
4248 // skip rsp
4249 movq(Address(rsp, 10 * wordSize), rbp);
4250 movq(Address(rsp, 9 * wordSize), rsi);
4251 movq(Address(rsp, 8 * wordSize), rdi);
4252 movq(Address(rsp, 7 * wordSize), r8);
4253 movq(Address(rsp, 6 * wordSize), r9);
4254 movq(Address(rsp, 5 * wordSize), r10);
4255 movq(Address(rsp, 4 * wordSize), r11);
4256 movq(Address(rsp, 3 * wordSize), r12);
4257 movq(Address(rsp, 2 * wordSize), r13);
4258 movq(Address(rsp, wordSize), r14);
4259 movq(Address(rsp, 0), r15);
4260 }
4261
4262 void Assembler::pushq(Address src) {
4263 InstructionMark im(this);
4264 prefixq(src);
4265 emit_byte(0xFF);
4266 emit_operand(rsi, src);
4267 }
4268
4269 void Assembler::rclq(Register dst, int imm8) {
4270 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4271 int encode = prefixq_and_encode(dst->encoding());
4272 if (imm8 == 1) {
4273 emit_byte(0xD1);
4274 emit_byte(0xD0 | encode);
4275 } else {
4276 emit_byte(0xC1);
4277 emit_byte(0xD0 | encode);
4278 emit_byte(imm8);
4279 }
4280 }
4281 void Assembler::sarq(Register dst, int imm8) {
4282 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4283 int encode = prefixq_and_encode(dst->encoding());
4284 if (imm8 == 1) {
4285 emit_byte(0xD1);
4286 emit_byte(0xF8 | encode);
4287 } else {
4288 emit_byte(0xC1);
4289 emit_byte(0xF8 | encode);
4290 emit_byte(imm8);
4291 }
4292 }
4293
4294 void Assembler::sarq(Register dst) {
4295 int encode = prefixq_and_encode(dst->encoding());
4296 emit_byte(0xD3);
4297 emit_byte(0xF8 | encode);
4298 }
4299 void Assembler::sbbq(Address dst, int32_t imm32) {
4300 InstructionMark im(this);
4301 prefixq(dst);
4302 emit_arith_operand(0x81, rbx, dst, imm32);
4303 }
4304
4305 void Assembler::sbbq(Register dst, int32_t imm32) {
4306 (void) prefixq_and_encode(dst->encoding());
4307 emit_arith(0x81, 0xD8, dst, imm32);
4308 }
4309
4310 void Assembler::sbbq(Register dst, Address src) {
4311 InstructionMark im(this);
4312 prefixq(src, dst);
4313 emit_byte(0x1B);
4314 emit_operand(dst, src);
4315 }
4316
4317 void Assembler::sbbq(Register dst, Register src) {
4318 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4319 emit_arith(0x1B, 0xC0, dst, src);
4320 }
4321
4322 void Assembler::shlq(Register dst, int imm8) {
4323 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4324 int encode = prefixq_and_encode(dst->encoding());
4325 if (imm8 == 1) {
4326 emit_byte(0xD1);
4327 emit_byte(0xE0 | encode);
4328 } else {
4329 emit_byte(0xC1);
4330 emit_byte(0xE0 | encode);
4331 emit_byte(imm8);
4332 }
4333 }
4334
4335 void Assembler::shlq(Register dst) {
4336 int encode = prefixq_and_encode(dst->encoding());
4337 emit_byte(0xD3);
4338 emit_byte(0xE0 | encode);
4339 }
4340
4341 void Assembler::shrq(Register dst, int imm8) {
4342 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4343 int encode = prefixq_and_encode(dst->encoding());
4344 emit_byte(0xC1);
4345 emit_byte(0xE8 | encode);
4346 emit_byte(imm8);
4347 }
4348
4349 void Assembler::shrq(Register dst) {
4350 int encode = prefixq_and_encode(dst->encoding());
4351 emit_byte(0xD3);
4352 emit_byte(0xE8 | encode);
4353 }
4354
4355 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4356 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4357 InstructionMark im(this);
4358 emit_byte(0xF2);
4359 prefix(src, dst);
4360 emit_byte(0x0F);
4361 emit_byte(0x51);
4362 emit_operand(dst, src);
4363 }
4364
4365 void Assembler::subq(Address dst, int32_t imm32) {
4366 InstructionMark im(this);
4367 prefixq(dst);
4368 if (is8bit(imm32)) {
4369 emit_byte(0x83);
4370 emit_operand(rbp, dst, 1);
4371 emit_byte(imm32 & 0xFF);
4372 } else {
4373 emit_byte(0x81);
4374 emit_operand(rbp, dst, 4);
4375 emit_long(imm32);
4376 }
4377 }
4378
4379 void Assembler::subq(Register dst, int32_t imm32) {
4380 (void) prefixq_and_encode(dst->encoding());
4381 emit_arith(0x81, 0xE8, dst, imm32);
4382 }
4383
4384 void Assembler::subq(Address dst, Register src) {
4385 InstructionMark im(this);
4386 prefixq(dst, src);
4387 emit_byte(0x29);
4388 emit_operand(src, dst);
4389 }
4390
4391 void Assembler::subq(Register dst, Address src) {
4392 InstructionMark im(this);
4393 prefixq(src, dst);
4394 emit_byte(0x2B);
4395 emit_operand(dst, src);
4396 }
4397
4398 void Assembler::subq(Register dst, Register src) {
4399 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4400 emit_arith(0x2B, 0xC0, dst, src);
4401 }
4402
4403 void Assembler::testq(Register dst, int32_t imm32) {
4404 // not using emit_arith because test
4405 // doesn't support sign-extension of
4406 // 8bit operands
4407 int encode = dst->encoding();
4408 if (encode == 0) {
4409 prefix(REX_W);
4410 emit_byte(0xA9);
4411 } else {
4412 encode = prefixq_and_encode(encode);
4413 emit_byte(0xF7);
4414 emit_byte(0xC0 | encode);
4415 }
4416 emit_long(imm32);
4417 }
4418
4419 void Assembler::testq(Register dst, Register src) {
4420 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4421 emit_arith(0x85, 0xC0, dst, src);
4422 }
4423
4424 void Assembler::xaddq(Address dst, Register src) {
4425 InstructionMark im(this);
4426 prefixq(dst, src);
4427 emit_byte(0x0F);
4428 emit_byte(0xC1);
4429 emit_operand(src, dst);
4430 }
4431
4432 void Assembler::xchgq(Register dst, Address src) {
4433 InstructionMark im(this);
4434 prefixq(src, dst);
4435 emit_byte(0x87);
4436 emit_operand(dst, src);
4437 }
4438
4439 void Assembler::xchgq(Register dst, Register src) {
4440 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4441 emit_byte(0x87);
4442 emit_byte(0xc0 | encode);
4443 }
4444
4445 void Assembler::xorq(Register dst, Register src) {
4446 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4447 emit_arith(0x33, 0xC0, dst, src);
4448 }
4449
4450 void Assembler::xorq(Register dst, Address src) {
4451 InstructionMark im(this);
4452 prefixq(src, dst);
4453 emit_byte(0x33);
4454 emit_operand(dst, src);
4455 }
4456
4457 #endif // !LP64
4458
4459 static Assembler::Condition reverse[] = {
4460 Assembler::noOverflow /* overflow = 0x0 */ ,
4461 Assembler::overflow /* noOverflow = 0x1 */ ,
4462 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4463 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4464 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4465 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4466 Assembler::above /* belowEqual = 0x6 */ ,
4467 Assembler::belowEqual /* above = 0x7 */ ,
4468 Assembler::positive /* negative = 0x8 */ ,
4469 Assembler::negative /* positive = 0x9 */ ,
4470 Assembler::noParity /* parity = 0xa */ ,
4471 Assembler::parity /* noParity = 0xb */ ,
4472 Assembler::greaterEqual /* less = 0xc */ ,
4473 Assembler::less /* greaterEqual = 0xd */ ,
4474 Assembler::greater /* lessEqual = 0xe */ ,
4475 Assembler::lessEqual /* greater = 0xf, */
4476
4477 };
4478
4479
4480 // Implementation of MacroAssembler
4481
4482 // First all the versions that have distinct versions depending on 32/64 bit
4483 // Unless the difference is trivial (1 line or so).
4484
4485 #ifndef _LP64
4486
4487 // 32bit versions
4488
4489 Address MacroAssembler::as_Address(AddressLiteral adr) {
4490 return Address(adr.target(), adr.rspec());
4491 }
4492
4493 Address MacroAssembler::as_Address(ArrayAddress adr) {
4494 return Address::make_array(adr);
4495 }
4496
4497 int MacroAssembler::biased_locking_enter(Register lock_reg,
4498 Register obj_reg,
4499 Register swap_reg,
4500 Register tmp_reg,
4501 bool swap_reg_contains_mark,
4502 Label& done,
4503 Label* slow_case,
4504 BiasedLockingCounters* counters) {
4505 assert(UseBiasedLocking, "why call this otherwise?");
4506 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4507 assert_different_registers(lock_reg, obj_reg, swap_reg);
4508
4509 if (PrintBiasedLockingStatistics && counters == NULL)
4510 counters = BiasedLocking::counters();
4511
4512 bool need_tmp_reg = false;
4513 if (tmp_reg == noreg) {
4514 need_tmp_reg = true;
4515 tmp_reg = lock_reg;
4516 } else {
4517 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4518 }
4519 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4520 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4521 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4522 Address saved_mark_addr(lock_reg, 0);
4523
4524 // Biased locking
4525 // See whether the lock is currently biased toward our thread and
4526 // whether the epoch is still valid
4527 // Note that the runtime guarantees sufficient alignment of JavaThread
4528 // pointers to allow age to be placed into low bits
4529 // First check to see whether biasing is even enabled for this object
4530 Label cas_label;
4531 int null_check_offset = -1;
4532 if (!swap_reg_contains_mark) {
4533 null_check_offset = offset();
4534 movl(swap_reg, mark_addr);
4535 }
4536 if (need_tmp_reg) {
4537 push(tmp_reg);
4538 }
4539 movl(tmp_reg, swap_reg);
4540 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4541 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4542 if (need_tmp_reg) {
4543 pop(tmp_reg);
4544 }
4545 jcc(Assembler::notEqual, cas_label);
4546 // The bias pattern is present in the object's header. Need to check
4547 // whether the bias owner and the epoch are both still current.
4548 // Note that because there is no current thread register on x86 we
4549 // need to store off the mark word we read out of the object to
4550 // avoid reloading it and needing to recheck invariants below. This
4551 // store is unfortunate but it makes the overall code shorter and
4552 // simpler.
4553 movl(saved_mark_addr, swap_reg);
4554 if (need_tmp_reg) {
4555 push(tmp_reg);
4556 }
4557 get_thread(tmp_reg);
4558 xorl(swap_reg, tmp_reg);
4559 if (swap_reg_contains_mark) {
4560 null_check_offset = offset();
4561 }
4562 movl(tmp_reg, klass_addr);
4563 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4564 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4565 if (need_tmp_reg) {
4566 pop(tmp_reg);
4567 }
4568 if (counters != NULL) {
4569 cond_inc32(Assembler::zero,
4570 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4571 }
4572 jcc(Assembler::equal, done);
4573
4574 Label try_revoke_bias;
4575 Label try_rebias;
4576
4577 // At this point we know that the header has the bias pattern and
4578 // that we are not the bias owner in the current epoch. We need to
4579 // figure out more details about the state of the header in order to
4580 // know what operations can be legally performed on the object's
4581 // header.
4582
4583 // If the low three bits in the xor result aren't clear, that means
4584 // the prototype header is no longer biased and we have to revoke
4585 // the bias on this object.
4586 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4587 jcc(Assembler::notZero, try_revoke_bias);
4588
4589 // Biasing is still enabled for this data type. See whether the
4590 // epoch of the current bias is still valid, meaning that the epoch
4591 // bits of the mark word are equal to the epoch bits of the
4592 // prototype header. (Note that the prototype header's epoch bits
4593 // only change at a safepoint.) If not, attempt to rebias the object
4594 // toward the current thread. Note that we must be absolutely sure
4595 // that the current epoch is invalid in order to do this because
4596 // otherwise the manipulations it performs on the mark word are
4597 // illegal.
4598 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4599 jcc(Assembler::notZero, try_rebias);
4600
4601 // The epoch of the current bias is still valid but we know nothing
4602 // about the owner; it might be set or it might be clear. Try to
4603 // acquire the bias of the object using an atomic operation. If this
4604 // fails we will go in to the runtime to revoke the object's bias.
4605 // Note that we first construct the presumed unbiased header so we
4606 // don't accidentally blow away another thread's valid bias.
4607 movl(swap_reg, saved_mark_addr);
4608 andl(swap_reg,
4609 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4610 if (need_tmp_reg) {
4611 push(tmp_reg);
4612 }
4613 get_thread(tmp_reg);
4614 orl(tmp_reg, swap_reg);
4615 if (os::is_MP()) {
4616 lock();
4617 }
4618 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4619 if (need_tmp_reg) {
4620 pop(tmp_reg);
4621 }
4622 // If the biasing toward our thread failed, this means that
4623 // another thread succeeded in biasing it toward itself and we
4624 // need to revoke that bias. The revocation will occur in the
4625 // interpreter runtime in the slow case.
4626 if (counters != NULL) {
4627 cond_inc32(Assembler::zero,
4628 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4629 }
4630 if (slow_case != NULL) {
4631 jcc(Assembler::notZero, *slow_case);
4632 }
4633 jmp(done);
4634
4635 bind(try_rebias);
4636 // At this point we know the epoch has expired, meaning that the
4637 // current "bias owner", if any, is actually invalid. Under these
4638 // circumstances _only_, we are allowed to use the current header's
4639 // value as the comparison value when doing the cas to acquire the
4640 // bias in the current epoch. In other words, we allow transfer of
4641 // the bias from one thread to another directly in this situation.
4642 //
4643 // FIXME: due to a lack of registers we currently blow away the age
4644 // bits in this situation. Should attempt to preserve them.
4645 if (need_tmp_reg) {
4646 push(tmp_reg);
4647 }
4648 get_thread(tmp_reg);
4649 movl(swap_reg, klass_addr);
4650 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4651 movl(swap_reg, saved_mark_addr);
4652 if (os::is_MP()) {
4653 lock();
4654 }
4655 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4656 if (need_tmp_reg) {
4657 pop(tmp_reg);
4658 }
4659 // If the biasing toward our thread failed, then another thread
4660 // succeeded in biasing it toward itself and we need to revoke that
4661 // bias. The revocation will occur in the runtime in the slow case.
4662 if (counters != NULL) {
4663 cond_inc32(Assembler::zero,
4664 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4665 }
4666 if (slow_case != NULL) {
4667 jcc(Assembler::notZero, *slow_case);
4668 }
4669 jmp(done);
4670
4671 bind(try_revoke_bias);
4672 // The prototype mark in the klass doesn't have the bias bit set any
4673 // more, indicating that objects of this data type are not supposed
4674 // to be biased any more. We are going to try to reset the mark of
4675 // this object to the prototype value and fall through to the
4676 // CAS-based locking scheme. Note that if our CAS fails, it means
4677 // that another thread raced us for the privilege of revoking the
4678 // bias of this particular object, so it's okay to continue in the
4679 // normal locking code.
4680 //
4681 // FIXME: due to a lack of registers we currently blow away the age
4682 // bits in this situation. Should attempt to preserve them.
4683 movl(swap_reg, saved_mark_addr);
4684 if (need_tmp_reg) {
4685 push(tmp_reg);
4686 }
4687 movl(tmp_reg, klass_addr);
4688 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4689 if (os::is_MP()) {
4690 lock();
4691 }
4692 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4693 if (need_tmp_reg) {
4694 pop(tmp_reg);
4695 }
4696 // Fall through to the normal CAS-based lock, because no matter what
4697 // the result of the above CAS, some thread must have succeeded in
4698 // removing the bias bit from the object's header.
4699 if (counters != NULL) {
4700 cond_inc32(Assembler::zero,
4701 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4702 }
4703
4704 bind(cas_label);
4705
4706 return null_check_offset;
4707 }
4708 void MacroAssembler::call_VM_leaf_base(address entry_point,
4709 int number_of_arguments) {
4710 call(RuntimeAddress(entry_point));
4711 increment(rsp, number_of_arguments * wordSize);
4712 }
4713
4714 void MacroAssembler::cmpoop(Address src1, jobject obj) {
4715 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4716 }
4717
4718 void MacroAssembler::cmpoop(Register src1, jobject obj) {
4719 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4720 }
4721
4722 void MacroAssembler::extend_sign(Register hi, Register lo) {
4723 // According to Intel Doc. AP-526, "Integer Divide", p.18.
4724 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
4725 cdql();
4726 } else {
4727 movl(hi, lo);
4728 sarl(hi, 31);
4729 }
4730 }
4731
4732 void MacroAssembler::fat_nop() {
4733 // A 5 byte nop that is safe for patching (see patch_verified_entry)
4734 emit_byte(0x26); // es:
4735 emit_byte(0x2e); // cs:
4736 emit_byte(0x64); // fs:
4737 emit_byte(0x65); // gs:
4738 emit_byte(0x90);
4739 }
4740
4741 void MacroAssembler::jC2(Register tmp, Label& L) {
4742 // set parity bit if FPU flag C2 is set (via rax)
4743 save_rax(tmp);
4744 fwait(); fnstsw_ax();
4745 sahf();
4746 restore_rax(tmp);
4747 // branch
4748 jcc(Assembler::parity, L);
4749 }
4750
4751 void MacroAssembler::jnC2(Register tmp, Label& L) {
4752 // set parity bit if FPU flag C2 is set (via rax)
4753 save_rax(tmp);
4754 fwait(); fnstsw_ax();
4755 sahf();
4756 restore_rax(tmp);
4757 // branch
4758 jcc(Assembler::noParity, L);
4759 }
4760
4761 // 32bit can do a case table jump in one instruction but we no longer allow the base
4762 // to be installed in the Address class
4763 void MacroAssembler::jump(ArrayAddress entry) {
4764 jmp(as_Address(entry));
4765 }
4766
4767 // Note: y_lo will be destroyed
4768 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
4769 // Long compare for Java (semantics as described in JVM spec.)
4770 Label high, low, done;
4771
4772 cmpl(x_hi, y_hi);
4773 jcc(Assembler::less, low);
4774 jcc(Assembler::greater, high);
4775 // x_hi is the return register
4776 xorl(x_hi, x_hi);
4777 cmpl(x_lo, y_lo);
4778 jcc(Assembler::below, low);
4779 jcc(Assembler::equal, done);
4780
4781 bind(high);
4782 xorl(x_hi, x_hi);
4783 increment(x_hi);
4784 jmp(done);
4785
4786 bind(low);
4787 xorl(x_hi, x_hi);
4788 decrementl(x_hi);
4789
4790 bind(done);
4791 }
4792
4793 void MacroAssembler::lea(Register dst, AddressLiteral src) {
4794 mov_literal32(dst, (int32_t)src.target(), src.rspec());
4795 }
4796
4797 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
4798 // leal(dst, as_Address(adr));
4799 // see note in movl as to why we must use a move
4800 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
4801 }
4802
4803 void MacroAssembler::leave() {
4804 mov(rsp, rbp);
4805 pop(rbp);
4806 }
4807
4808 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
4809 // Multiplication of two Java long values stored on the stack
4810 // as illustrated below. Result is in rdx:rax.
4811 //
4812 // rsp ---> [ ?? ] \ \
4813 // .... | y_rsp_offset |
4814 // [ y_lo ] / (in bytes) | x_rsp_offset
4815 // [ y_hi ] | (in bytes)
4816 // .... |
4817 // [ x_lo ] /
4818 // [ x_hi ]
4819 // ....
4820 //
4821 // Basic idea: lo(result) = lo(x_lo * y_lo)
4822 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
4823 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
4824 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
4825 Label quick;
4826 // load x_hi, y_hi and check if quick
4827 // multiplication is possible
4828 movl(rbx, x_hi);
4829 movl(rcx, y_hi);
4830 movl(rax, rbx);
4831 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
4832 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
4833 // do full multiplication
4834 // 1st step
4835 mull(y_lo); // x_hi * y_lo
4836 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
4837 // 2nd step
4838 movl(rax, x_lo);
4839 mull(rcx); // x_lo * y_hi
4840 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
4841 // 3rd step
4842 bind(quick); // note: rbx, = 0 if quick multiply!
4843 movl(rax, x_lo);
4844 mull(y_lo); // x_lo * y_lo
4845 addl(rdx, rbx); // correct hi(x_lo * y_lo)
4846 }
4847
4848 void MacroAssembler::lneg(Register hi, Register lo) {
4849 negl(lo);
4850 adcl(hi, 0);
4851 negl(hi);
4852 }
4853
4854 void MacroAssembler::lshl(Register hi, Register lo) {
4855 // Java shift left long support (semantics as described in JVM spec., p.305)
4856 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
4857 // shift value is in rcx !
4858 assert(hi != rcx, "must not use rcx");
4859 assert(lo != rcx, "must not use rcx");
4860 const Register s = rcx; // shift count
4861 const int n = BitsPerWord;
4862 Label L;
4863 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4864 cmpl(s, n); // if (s < n)
4865 jcc(Assembler::less, L); // else (s >= n)
4866 movl(hi, lo); // x := x << n
4867 xorl(lo, lo);
4868 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4869 bind(L); // s (mod n) < n
4870 shldl(hi, lo); // x := x << s
4871 shll(lo);
4872 }
4873
4874
4875 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
4876 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
4877 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
4878 assert(hi != rcx, "must not use rcx");
4879 assert(lo != rcx, "must not use rcx");
4880 const Register s = rcx; // shift count
4881 const int n = BitsPerWord;
4882 Label L;
4883 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4884 cmpl(s, n); // if (s < n)
4885 jcc(Assembler::less, L); // else (s >= n)
4886 movl(lo, hi); // x := x >> n
4887 if (sign_extension) sarl(hi, 31);
4888 else xorl(hi, hi);
4889 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4890 bind(L); // s (mod n) < n
4891 shrdl(lo, hi); // x := x >> s
4892 if (sign_extension) sarl(hi);
4893 else shrl(hi);
4894 }
4895
4896 void MacroAssembler::movoop(Register dst, jobject obj) {
4897 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4898 }
4899
4900 void MacroAssembler::movoop(Address dst, jobject obj) {
4901 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4902 }
4903
4904 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
4905 if (src.is_lval()) {
4906 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
4907 } else {
4908 movl(dst, as_Address(src));
4909 }
4910 }
4911
4912 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
4913 movl(as_Address(dst), src);
4914 }
4915
4916 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
4917 movl(dst, as_Address(src));
4918 }
4919
4920 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
4921 void MacroAssembler::movptr(Address dst, intptr_t src) {
4922 movl(dst, src);
4923 }
4924
4925
4926 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
4927 movsd(dst, as_Address(src));
4928 }
4929
4930 void MacroAssembler::pop_callee_saved_registers() {
4931 pop(rcx);
4932 pop(rdx);
4933 pop(rdi);
4934 pop(rsi);
4935 }
4936
4937 void MacroAssembler::pop_fTOS() {
4938 fld_d(Address(rsp, 0));
4939 addl(rsp, 2 * wordSize);
4940 }
4941
4942 void MacroAssembler::push_callee_saved_registers() {
4943 push(rsi);
4944 push(rdi);
4945 push(rdx);
4946 push(rcx);
4947 }
4948
4949 void MacroAssembler::push_fTOS() {
4950 subl(rsp, 2 * wordSize);
4951 fstp_d(Address(rsp, 0));
4952 }
4953
4954
4955 void MacroAssembler::pushoop(jobject obj) {
4956 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
4957 }
4958
4959
4960 void MacroAssembler::pushptr(AddressLiteral src) {
4961 if (src.is_lval()) {
4962 push_literal32((int32_t)src.target(), src.rspec());
4963 } else {
4964 pushl(as_Address(src));
4965 }
4966 }
4967
4968 void MacroAssembler::set_word_if_not_zero(Register dst) {
4969 xorl(dst, dst);
4970 set_byte_if_not_zero(dst);
4971 }
4972
4973 static void pass_arg0(MacroAssembler* masm, Register arg) {
4974 masm->push(arg);
4975 }
4976
4977 static void pass_arg1(MacroAssembler* masm, Register arg) {
4978 masm->push(arg);
4979 }
4980
4981 static void pass_arg2(MacroAssembler* masm, Register arg) {
4982 masm->push(arg);
4983 }
4984
4985 static void pass_arg3(MacroAssembler* masm, Register arg) {
4986 masm->push(arg);
4987 }
4988
4989 #ifndef PRODUCT
4990 extern "C" void findpc(intptr_t x);
4991 #endif
4992
4993 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
4994 // In order to get locks to work, we need to fake a in_VM state
4995 JavaThread* thread = JavaThread::current();
4996 JavaThreadState saved_state = thread->thread_state();
4997 thread->set_thread_state(_thread_in_vm);
4998 if (ShowMessageBoxOnError) {
4999 JavaThread* thread = JavaThread::current();
5000 JavaThreadState saved_state = thread->thread_state();
5001 thread->set_thread_state(_thread_in_vm);
5002 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5003 ttyLocker ttyl;
5004 BytecodeCounter::print();
5005 }
5006 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5007 // This is the value of eip which points to where verify_oop will return.
5008 if (os::message_box(msg, "Execution stopped, print registers?")) {
5009 ttyLocker ttyl;
5010 tty->print_cr("eip = 0x%08x", eip);
5011 #ifndef PRODUCT
5012 if ((WizardMode || Verbose) && PrintMiscellaneous) {
5013 tty->cr();
5014 findpc(eip);
5015 tty->cr();
5016 }
5017 #endif
5018 tty->print_cr("rax = 0x%08x", rax);
5019 tty->print_cr("rbx = 0x%08x", rbx);
5020 tty->print_cr("rcx = 0x%08x", rcx);
5021 tty->print_cr("rdx = 0x%08x", rdx);
5022 tty->print_cr("rdi = 0x%08x", rdi);
5023 tty->print_cr("rsi = 0x%08x", rsi);
5024 tty->print_cr("rbp = 0x%08x", rbp);
5025 tty->print_cr("rsp = 0x%08x", rsp);
5026 BREAKPOINT;
5027 assert(false, "start up GDB");
5028 }
5029 } else {
5030 ttyLocker ttyl;
5031 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5032 assert(false, "DEBUG MESSAGE");
5033 }
5034 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5035 }
5036
5037 void MacroAssembler::stop(const char* msg) {
5038 ExternalAddress message((address)msg);
5039 // push address of message
5040 pushptr(message.addr());
5041 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5042 pusha(); // push registers
5043 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5044 hlt();
5045 }
5046
5047 void MacroAssembler::warn(const char* msg) {
5048 push_CPU_state();
5049
5050 ExternalAddress message((address) msg);
5051 // push address of message
5052 pushptr(message.addr());
5053
5054 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5055 addl(rsp, wordSize); // discard argument
5056 pop_CPU_state();
5057 }
5058
5059 #else // _LP64
5060
5061 // 64 bit versions
5062
5063 Address MacroAssembler::as_Address(AddressLiteral adr) {
5064 // amd64 always does this as a pc-rel
5065 // we can be absolute or disp based on the instruction type
5066 // jmp/call are displacements others are absolute
5067 assert(!adr.is_lval(), "must be rval");
5068 assert(reachable(adr), "must be");
5069 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5070
5071 }
5072
5073 Address MacroAssembler::as_Address(ArrayAddress adr) {
5074 AddressLiteral base = adr.base();
5075 lea(rscratch1, base);
5076 Address index = adr.index();
5077 assert(index._disp == 0, "must not have disp"); // maybe it can?
5078 Address array(rscratch1, index._index, index._scale, index._disp);
5079 return array;
5080 }
5081
5082 int MacroAssembler::biased_locking_enter(Register lock_reg,
5083 Register obj_reg,
5084 Register swap_reg,
5085 Register tmp_reg,
5086 bool swap_reg_contains_mark,
5087 Label& done,
5088 Label* slow_case,
5089 BiasedLockingCounters* counters) {
5090 assert(UseBiasedLocking, "why call this otherwise?");
5091 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5092 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5093 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5094 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5095 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5096 Address saved_mark_addr(lock_reg, 0);
5097
5098 if (PrintBiasedLockingStatistics && counters == NULL)
5099 counters = BiasedLocking::counters();
5100
5101 // Biased locking
5102 // See whether the lock is currently biased toward our thread and
5103 // whether the epoch is still valid
5104 // Note that the runtime guarantees sufficient alignment of JavaThread
5105 // pointers to allow age to be placed into low bits
5106 // First check to see whether biasing is even enabled for this object
5107 Label cas_label;
5108 int null_check_offset = -1;
5109 if (!swap_reg_contains_mark) {
5110 null_check_offset = offset();
5111 movq(swap_reg, mark_addr);
5112 }
5113 movq(tmp_reg, swap_reg);
5114 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5115 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5116 jcc(Assembler::notEqual, cas_label);
5117 // The bias pattern is present in the object's header. Need to check
5118 // whether the bias owner and the epoch are both still current.
5119 load_prototype_header(tmp_reg, obj_reg);
5120 orq(tmp_reg, r15_thread);
5121 xorq(tmp_reg, swap_reg);
5122 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5123 if (counters != NULL) {
5124 cond_inc32(Assembler::zero,
5125 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5126 }
5127 jcc(Assembler::equal, done);
5128
5129 Label try_revoke_bias;
5130 Label try_rebias;
5131
5132 // At this point we know that the header has the bias pattern and
5133 // that we are not the bias owner in the current epoch. We need to
5134 // figure out more details about the state of the header in order to
5135 // know what operations can be legally performed on the object's
5136 // header.
5137
5138 // If the low three bits in the xor result aren't clear, that means
5139 // the prototype header is no longer biased and we have to revoke
5140 // the bias on this object.
5141 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5142 jcc(Assembler::notZero, try_revoke_bias);
5143
5144 // Biasing is still enabled for this data type. See whether the
5145 // epoch of the current bias is still valid, meaning that the epoch
5146 // bits of the mark word are equal to the epoch bits of the
5147 // prototype header. (Note that the prototype header's epoch bits
5148 // only change at a safepoint.) If not, attempt to rebias the object
5149 // toward the current thread. Note that we must be absolutely sure
5150 // that the current epoch is invalid in order to do this because
5151 // otherwise the manipulations it performs on the mark word are
5152 // illegal.
5153 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5154 jcc(Assembler::notZero, try_rebias);
5155
5156 // The epoch of the current bias is still valid but we know nothing
5157 // about the owner; it might be set or it might be clear. Try to
5158 // acquire the bias of the object using an atomic operation. If this
5159 // fails we will go in to the runtime to revoke the object's bias.
5160 // Note that we first construct the presumed unbiased header so we
5161 // don't accidentally blow away another thread's valid bias.
5162 andq(swap_reg,
5163 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5164 movq(tmp_reg, swap_reg);
5165 orq(tmp_reg, r15_thread);
5166 if (os::is_MP()) {
5167 lock();
5168 }
5169 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5170 // If the biasing toward our thread failed, this means that
5171 // another thread succeeded in biasing it toward itself and we
5172 // need to revoke that bias. The revocation will occur in the
5173 // interpreter runtime in the slow case.
5174 if (counters != NULL) {
5175 cond_inc32(Assembler::zero,
5176 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5177 }
5178 if (slow_case != NULL) {
5179 jcc(Assembler::notZero, *slow_case);
5180 }
5181 jmp(done);
5182
5183 bind(try_rebias);
5184 // At this point we know the epoch has expired, meaning that the
5185 // current "bias owner", if any, is actually invalid. Under these
5186 // circumstances _only_, we are allowed to use the current header's
5187 // value as the comparison value when doing the cas to acquire the
5188 // bias in the current epoch. In other words, we allow transfer of
5189 // the bias from one thread to another directly in this situation.
5190 //
5191 // FIXME: due to a lack of registers we currently blow away the age
5192 // bits in this situation. Should attempt to preserve them.
5193 load_prototype_header(tmp_reg, obj_reg);
5194 orq(tmp_reg, r15_thread);
5195 if (os::is_MP()) {
5196 lock();
5197 }
5198 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5199 // If the biasing toward our thread failed, then another thread
5200 // succeeded in biasing it toward itself and we need to revoke that
5201 // bias. The revocation will occur in the runtime in the slow case.
5202 if (counters != NULL) {
5203 cond_inc32(Assembler::zero,
5204 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5205 }
5206 if (slow_case != NULL) {
5207 jcc(Assembler::notZero, *slow_case);
5208 }
5209 jmp(done);
5210
5211 bind(try_revoke_bias);
5212 // The prototype mark in the klass doesn't have the bias bit set any
5213 // more, indicating that objects of this data type are not supposed
5214 // to be biased any more. We are going to try to reset the mark of
5215 // this object to the prototype value and fall through to the
5216 // CAS-based locking scheme. Note that if our CAS fails, it means
5217 // that another thread raced us for the privilege of revoking the
5218 // bias of this particular object, so it's okay to continue in the
5219 // normal locking code.
5220 //
5221 // FIXME: due to a lack of registers we currently blow away the age
5222 // bits in this situation. Should attempt to preserve them.
5223 load_prototype_header(tmp_reg, obj_reg);
5224 if (os::is_MP()) {
5225 lock();
5226 }
5227 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5228 // Fall through to the normal CAS-based lock, because no matter what
5229 // the result of the above CAS, some thread must have succeeded in
5230 // removing the bias bit from the object's header.
5231 if (counters != NULL) {
5232 cond_inc32(Assembler::zero,
5233 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5234 }
5235
5236 bind(cas_label);
5237
5238 return null_check_offset;
5239 }
5240
5241 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5242 Label L, E;
5243
5244 #ifdef _WIN64
5245 // Windows always allocates space for it's register args
5246 assert(num_args <= 4, "only register arguments supported");
5247 subq(rsp, frame::arg_reg_save_area_bytes);
5248 #endif
5249
5250 // Align stack if necessary
5251 testl(rsp, 15);
5252 jcc(Assembler::zero, L);
5253
5254 subq(rsp, 8);
5255 {
5256 call(RuntimeAddress(entry_point));
5257 }
5258 addq(rsp, 8);
5259 jmp(E);
5260
5261 bind(L);
5262 {
5263 call(RuntimeAddress(entry_point));
5264 }
5265
5266 bind(E);
5267
5268 #ifdef _WIN64
5269 // restore stack pointer
5270 addq(rsp, frame::arg_reg_save_area_bytes);
5271 #endif
5272
5273 }
5274
5275 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5276 assert(!src2.is_lval(), "should use cmpptr");
5277
5278 if (reachable(src2)) {
5279 cmpq(src1, as_Address(src2));
5280 } else {
5281 lea(rscratch1, src2);
5282 Assembler::cmpq(src1, Address(rscratch1, 0));
5283 }
5284 }
5285
5286 int MacroAssembler::corrected_idivq(Register reg) {
5287 // Full implementation of Java ldiv and lrem; checks for special
5288 // case as described in JVM spec., p.243 & p.271. The function
5289 // returns the (pc) offset of the idivl instruction - may be needed
5290 // for implicit exceptions.
5291 //
5292 // normal case special case
5293 //
5294 // input : rax: dividend min_long
5295 // reg: divisor (may not be eax/edx) -1
5296 //
5297 // output: rax: quotient (= rax idiv reg) min_long
5298 // rdx: remainder (= rax irem reg) 0
5299 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5300 static const int64_t min_long = 0x8000000000000000;
5301 Label normal_case, special_case;
5302
5303 // check for special case
5304 cmp64(rax, ExternalAddress((address) &min_long));
5305 jcc(Assembler::notEqual, normal_case);
5306 xorl(rdx, rdx); // prepare rdx for possible special case (where
5307 // remainder = 0)
5308 cmpq(reg, -1);
5309 jcc(Assembler::equal, special_case);
5310
5311 // handle normal case
5312 bind(normal_case);
5313 cdqq();
5314 int idivq_offset = offset();
5315 idivq(reg);
5316
5317 // normal and special case exit
5318 bind(special_case);
5319
5320 return idivq_offset;
5321 }
5322
5323 void MacroAssembler::decrementq(Register reg, int value) {
5324 if (value == min_jint) { subq(reg, value); return; }
5325 if (value < 0) { incrementq(reg, -value); return; }
5326 if (value == 0) { ; return; }
5327 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5328 /* else */ { subq(reg, value) ; return; }
5329 }
5330
5331 void MacroAssembler::decrementq(Address dst, int value) {
5332 if (value == min_jint) { subq(dst, value); return; }
5333 if (value < 0) { incrementq(dst, -value); return; }
5334 if (value == 0) { ; return; }
5335 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5336 /* else */ { subq(dst, value) ; return; }
5337 }
5338
5339 void MacroAssembler::fat_nop() {
5340 // A 5 byte nop that is safe for patching (see patch_verified_entry)
5341 // Recommened sequence from 'Software Optimization Guide for the AMD
5342 // Hammer Processor'
5343 emit_byte(0x66);
5344 emit_byte(0x66);
5345 emit_byte(0x90);
5346 emit_byte(0x66);
5347 emit_byte(0x90);
5348 }
5349
5350 void MacroAssembler::incrementq(Register reg, int value) {
5351 if (value == min_jint) { addq(reg, value); return; }
5352 if (value < 0) { decrementq(reg, -value); return; }
5353 if (value == 0) { ; return; }
5354 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5355 /* else */ { addq(reg, value) ; return; }
5356 }
5357
5358 void MacroAssembler::incrementq(Address dst, int value) {
5359 if (value == min_jint) { addq(dst, value); return; }
5360 if (value < 0) { decrementq(dst, -value); return; }
5361 if (value == 0) { ; return; }
5362 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5363 /* else */ { addq(dst, value) ; return; }
5364 }
5365
5366 // 32bit can do a case table jump in one instruction but we no longer allow the base
5367 // to be installed in the Address class
5368 void MacroAssembler::jump(ArrayAddress entry) {
5369 lea(rscratch1, entry.base());
5370 Address dispatch = entry.index();
5371 assert(dispatch._base == noreg, "must be");
5372 dispatch._base = rscratch1;
5373 jmp(dispatch);
5374 }
5375
5376 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5377 ShouldNotReachHere(); // 64bit doesn't use two regs
5378 cmpq(x_lo, y_lo);
5379 }
5380
5381 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5382 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5383 }
5384
5385 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5386 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5387 movptr(dst, rscratch1);
5388 }
5389
5390 void MacroAssembler::leave() {
5391 // %%% is this really better? Why not on 32bit too?
5392 emit_byte(0xC9); // LEAVE
5393 }
5394
5395 void MacroAssembler::lneg(Register hi, Register lo) {
5396 ShouldNotReachHere(); // 64bit doesn't use two regs
5397 negq(lo);
5398 }
5399
5400 void MacroAssembler::movoop(Register dst, jobject obj) {
5401 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5402 }
5403
5404 void MacroAssembler::movoop(Address dst, jobject obj) {
5405 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5406 movq(dst, rscratch1);
5407 }
5408
5409 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5410 if (src.is_lval()) {
5411 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5412 } else {
5413 if (reachable(src)) {
5414 movq(dst, as_Address(src));
5415 } else {
5416 lea(rscratch1, src);
5417 movq(dst, Address(rscratch1,0));
5418 }
5419 }
5420 }
5421
5422 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5423 movq(as_Address(dst), src);
5424 }
5425
5426 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5427 movq(dst, as_Address(src));
5428 }
5429
5430 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5431 void MacroAssembler::movptr(Address dst, intptr_t src) {
5432 mov64(rscratch1, src);
5433 movq(dst, rscratch1);
5434 }
5435
5436 // These are mostly for initializing NULL
5437 void MacroAssembler::movptr(Address dst, int32_t src) {
5438 movslq(dst, src);
5439 }
5440
5441 void MacroAssembler::movptr(Register dst, int32_t src) {
5442 mov64(dst, (intptr_t)src);
5443 }
5444
5445 void MacroAssembler::pushoop(jobject obj) {
5446 movoop(rscratch1, obj);
5447 push(rscratch1);
5448 }
5449
5450 void MacroAssembler::pushptr(AddressLiteral src) {
5451 lea(rscratch1, src);
5452 if (src.is_lval()) {
5453 push(rscratch1);
5454 } else {
5455 pushq(Address(rscratch1, 0));
5456 }
5457 }
5458
5459 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5460 bool clear_pc) {
5461 // we must set sp to zero to clear frame
5462 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
5463 // must clear fp, so that compiled frames are not confused; it is
5464 // possible that we need it only for debugging
5465 if (clear_fp) {
5466 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
5467 }
5468
5469 if (clear_pc) {
5470 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
5471 }
5472 }
5473
5474 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
5475 Register last_java_fp,
5476 address last_java_pc) {
5477 // determine last_java_sp register
5478 if (!last_java_sp->is_valid()) {
5479 last_java_sp = rsp;
5480 }
5481
5482 // last_java_fp is optional
5483 if (last_java_fp->is_valid()) {
5484 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
5485 last_java_fp);
5486 }
5487
5488 // last_java_pc is optional
5489 if (last_java_pc != NULL) {
5490 Address java_pc(r15_thread,
5491 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
5492 lea(rscratch1, InternalAddress(last_java_pc));
5493 movptr(java_pc, rscratch1);
5494 }
5495
5496 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
5497 }
5498
5499 static void pass_arg0(MacroAssembler* masm, Register arg) {
5500 if (c_rarg0 != arg ) {
5501 masm->mov(c_rarg0, arg);
5502 }
5503 }
5504
5505 static void pass_arg1(MacroAssembler* masm, Register arg) {
5506 if (c_rarg1 != arg ) {
5507 masm->mov(c_rarg1, arg);
5508 }
5509 }
5510
5511 static void pass_arg2(MacroAssembler* masm, Register arg) {
5512 if (c_rarg2 != arg ) {
5513 masm->mov(c_rarg2, arg);
5514 }
5515 }
5516
5517 static void pass_arg3(MacroAssembler* masm, Register arg) {
5518 if (c_rarg3 != arg ) {
5519 masm->mov(c_rarg3, arg);
5520 }
5521 }
5522
5523 void MacroAssembler::stop(const char* msg) {
5524 address rip = pc();
5525 pusha(); // get regs on stack
5526 lea(c_rarg0, ExternalAddress((address) msg));
5527 lea(c_rarg1, InternalAddress(rip));
5528 movq(c_rarg2, rsp); // pass pointer to regs array
5529 andq(rsp, -16); // align stack as required by ABI
5530 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
5531 hlt();
5532 }
5533
5534 void MacroAssembler::warn(const char* msg) {
5535 push(r12);
5536 movq(r12, rsp);
5537 andq(rsp, -16); // align stack as required by push_CPU_state and call
5538
5539 push_CPU_state(); // keeps alignment at 16 bytes
5540 lea(c_rarg0, ExternalAddress((address) msg));
5541 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
5542 pop_CPU_state();
5543
5544 movq(rsp, r12);
5545 pop(r12);
5546 }
5547
5548 #ifndef PRODUCT
5549 extern "C" void findpc(intptr_t x);
5550 #endif
5551
5552 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
5553 // In order to get locks to work, we need to fake a in_VM state
5554 if (ShowMessageBoxOnError ) {
5555 JavaThread* thread = JavaThread::current();
5556 JavaThreadState saved_state = thread->thread_state();
5557 thread->set_thread_state(_thread_in_vm);
5558 #ifndef PRODUCT
5559 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5560 ttyLocker ttyl;
5561 BytecodeCounter::print();
5562 }
5563 #endif
5564 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5565 // XXX correct this offset for amd64
5566 // This is the value of eip which points to where verify_oop will return.
5567 if (os::message_box(msg, "Execution stopped, print registers?")) {
5568 ttyLocker ttyl;
5569 tty->print_cr("rip = 0x%016lx", pc);
5570 #ifndef PRODUCT
5571 tty->cr();
5572 findpc(pc);
5573 tty->cr();
5574 #endif
5575 tty->print_cr("rax = 0x%016lx", regs[15]);
5576 tty->print_cr("rbx = 0x%016lx", regs[12]);
5577 tty->print_cr("rcx = 0x%016lx", regs[14]);
5578 tty->print_cr("rdx = 0x%016lx", regs[13]);
5579 tty->print_cr("rdi = 0x%016lx", regs[8]);
5580 tty->print_cr("rsi = 0x%016lx", regs[9]);
5581 tty->print_cr("rbp = 0x%016lx", regs[10]);
5582 tty->print_cr("rsp = 0x%016lx", regs[11]);
5583 tty->print_cr("r8 = 0x%016lx", regs[7]);
5584 tty->print_cr("r9 = 0x%016lx", regs[6]);
5585 tty->print_cr("r10 = 0x%016lx", regs[5]);
5586 tty->print_cr("r11 = 0x%016lx", regs[4]);
5587 tty->print_cr("r12 = 0x%016lx", regs[3]);
5588 tty->print_cr("r13 = 0x%016lx", regs[2]);
5589 tty->print_cr("r14 = 0x%016lx", regs[1]);
5590 tty->print_cr("r15 = 0x%016lx", regs[0]);
5591 BREAKPOINT;
5592 }
5593 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5594 } else {
5595 ttyLocker ttyl;
5596 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
5597 msg);
5598 }
5599 }
5600
5601 #endif // _LP64
5602
5603 // Now versions that are common to 32/64 bit
5604
5605 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5606 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5607 }
5608
5609 void MacroAssembler::addptr(Register dst, Register src) {
5610 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5611 }
5612
5613 void MacroAssembler::addptr(Address dst, Register src) {
5614 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5615 }
5616
5617 void MacroAssembler::align(int modulus) {
5618 if (offset() % modulus != 0) {
5619 nop(modulus - (offset() % modulus));
5620 }
5621 }
5622
5623 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5624 if (reachable(src)) {
5625 andpd(dst, as_Address(src));
5626 } else {
5627 lea(rscratch1, src);
5628 andpd(dst, Address(rscratch1, 0));
5629 }
5630 }
5631
5632 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5633 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5634 }
5635
5636 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5637 pushf();
5638 if (os::is_MP())
5639 lock();
5640 incrementl(counter_addr);
5641 popf();
5642 }
5643
5644 // Writes to stack successive pages until offset reached to check for
5645 // stack overflow + shadow pages. This clobbers tmp.
5646 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5647 movptr(tmp, rsp);
5648 // Bang stack for total size given plus shadow page size.
5649 // Bang one page at a time because large size can bang beyond yellow and
5650 // red zones.
5651 Label loop;
5652 bind(loop);
5653 movl(Address(tmp, (-os::vm_page_size())), size );
5654 subptr(tmp, os::vm_page_size());
5655 subl(size, os::vm_page_size());
5656 jcc(Assembler::greater, loop);
5657
5658 // Bang down shadow pages too.
5659 // The -1 because we already subtracted 1 page.
5660 for (int i = 0; i< StackShadowPages-1; i++) {
5661 // this could be any sized move but this is can be a debugging crumb
5662 // so the bigger the better.
5663 movptr(Address(tmp, (-i*os::vm_page_size())), size );
5664 }
5665 }
5666
5667 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
5668 assert(UseBiasedLocking, "why call this otherwise?");
5669
5670 // Check for biased locking unlock case, which is a no-op
5671 // Note: we do not have to check the thread ID for two reasons.
5672 // First, the interpreter checks for IllegalMonitorStateException at
5673 // a higher level. Second, if the bias was revoked while we held the
5674 // lock, the object could not be rebiased toward another thread, so
5675 // the bias bit would be clear.
5676 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
5677 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
5678 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
5679 jcc(Assembler::equal, done);
5680 }
5681
5682 void MacroAssembler::c2bool(Register x) {
5683 // implements x == 0 ? 0 : 1
5684 // note: must only look at least-significant byte of x
5685 // since C-style booleans are stored in one byte
5686 // only! (was bug)
5687 andl(x, 0xFF);
5688 setb(Assembler::notZero, x);
5689 }
5690
5691 // Wouldn't need if AddressLiteral version had new name
5692 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
5693 Assembler::call(L, rtype);
5694 }
5695
5696 void MacroAssembler::call(Register entry) {
5697 Assembler::call(entry);
5698 }
5699
5700 void MacroAssembler::call(AddressLiteral entry) {
5701 if (reachable(entry)) {
5702 Assembler::call_literal(entry.target(), entry.rspec());
5703 } else {
5704 lea(rscratch1, entry);
5705 Assembler::call(rscratch1);
5706 }
5707 }
5708
5709 // Implementation of call_VM versions
5710
5711 void MacroAssembler::call_VM(Register oop_result,
5712 address entry_point,
5713 bool check_exceptions) {
5714 Label C, E;
5715 call(C, relocInfo::none);
5716 jmp(E);
5717
5718 bind(C);
5719 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
5720 ret(0);
5721
5722 bind(E);
5723 }
5724
5725 void MacroAssembler::call_VM(Register oop_result,
5726 address entry_point,
5727 Register arg_1,
5728 bool check_exceptions) {
5729 Label C, E;
5730 call(C, relocInfo::none);
5731 jmp(E);
5732
5733 bind(C);
5734 pass_arg1(this, arg_1);
5735 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
5736 ret(0);
5737
5738 bind(E);
5739 }
5740
5741 void MacroAssembler::call_VM(Register oop_result,
5742 address entry_point,
5743 Register arg_1,
5744 Register arg_2,
5745 bool check_exceptions) {
5746 Label C, E;
5747 call(C, relocInfo::none);
5748 jmp(E);
5749
5750 bind(C);
5751
5752 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5753
5754 pass_arg2(this, arg_2);
5755 pass_arg1(this, arg_1);
5756 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
5757 ret(0);
5758
5759 bind(E);
5760 }
5761
5762 void MacroAssembler::call_VM(Register oop_result,
5763 address entry_point,
5764 Register arg_1,
5765 Register arg_2,
5766 Register arg_3,
5767 bool check_exceptions) {
5768 Label C, E;
5769 call(C, relocInfo::none);
5770 jmp(E);
5771
5772 bind(C);
5773
5774 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5775 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5776 pass_arg3(this, arg_3);
5777
5778 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5779 pass_arg2(this, arg_2);
5780
5781 pass_arg1(this, arg_1);
5782 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
5783 ret(0);
5784
5785 bind(E);
5786 }
5787
5788 void MacroAssembler::call_VM(Register oop_result,
5789 Register last_java_sp,
5790 address entry_point,
5791 int number_of_arguments,
5792 bool check_exceptions) {
5793 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
5794 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
5795 }
5796
5797 void MacroAssembler::call_VM(Register oop_result,
5798 Register last_java_sp,
5799 address entry_point,
5800 Register arg_1,
5801 bool check_exceptions) {
5802 pass_arg1(this, arg_1);
5803 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
5804 }
5805
5806 void MacroAssembler::call_VM(Register oop_result,
5807 Register last_java_sp,
5808 address entry_point,
5809 Register arg_1,
5810 Register arg_2,
5811 bool check_exceptions) {
5812
5813 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5814 pass_arg2(this, arg_2);
5815 pass_arg1(this, arg_1);
5816 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
5817 }
5818
5819 void MacroAssembler::call_VM(Register oop_result,
5820 Register last_java_sp,
5821 address entry_point,
5822 Register arg_1,
5823 Register arg_2,
5824 Register arg_3,
5825 bool check_exceptions) {
5826 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5827 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5828 pass_arg3(this, arg_3);
5829 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5830 pass_arg2(this, arg_2);
5831 pass_arg1(this, arg_1);
5832 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
5833 }
5834
5835 void MacroAssembler::call_VM_base(Register oop_result,
5836 Register java_thread,
5837 Register last_java_sp,
5838 address entry_point,
5839 int number_of_arguments,
5840 bool check_exceptions) {
5841 // determine java_thread register
5842 if (!java_thread->is_valid()) {
5843 #ifdef _LP64
5844 java_thread = r15_thread;
5845 #else
5846 java_thread = rdi;
5847 get_thread(java_thread);
5848 #endif // LP64
5849 }
5850 // determine last_java_sp register
5851 if (!last_java_sp->is_valid()) {
5852 last_java_sp = rsp;
5853 }
5854 // debugging support
5855 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
5856 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
5857 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
5858 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
5859
5860 // push java thread (becomes first argument of C function)
5861
5862 NOT_LP64(push(java_thread); number_of_arguments++);
5863 LP64_ONLY(mov(c_rarg0, r15_thread));
5864
5865 // set last Java frame before call
5866 assert(last_java_sp != rbp, "can't use ebp/rbp");
5867
5868 // Only interpreter should have to set fp
5869 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
5870
5871 // do the call, remove parameters
5872 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
5873
5874 // restore the thread (cannot use the pushed argument since arguments
5875 // may be overwritten by C code generated by an optimizing compiler);
5876 // however can use the register value directly if it is callee saved.
5877 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
5878 // rdi & rsi (also r15) are callee saved -> nothing to do
5879 #ifdef ASSERT
5880 guarantee(java_thread != rax, "change this code");
5881 push(rax);
5882 { Label L;
5883 get_thread(rax);
5884 cmpptr(java_thread, rax);
5885 jcc(Assembler::equal, L);
5886 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
5887 bind(L);
5888 }
5889 pop(rax);
5890 #endif
5891 } else {
5892 get_thread(java_thread);
5893 }
5894 // reset last Java frame
5895 // Only interpreter should have to clear fp
5896 reset_last_Java_frame(java_thread, true, false);
5897
5898 #ifndef CC_INTERP
5899 // C++ interp handles this in the interpreter
5900 check_and_handle_popframe(java_thread);
5901 check_and_handle_earlyret(java_thread);
5902 #endif /* CC_INTERP */
5903
5904 if (check_exceptions) {
5905 // check for pending exceptions (java_thread is set upon return)
5906 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
5907 #ifndef _LP64
5908 jump_cc(Assembler::notEqual,
5909 RuntimeAddress(StubRoutines::forward_exception_entry()));
5910 #else
5911 // This used to conditionally jump to forward_exception however it is
5912 // possible if we relocate that the branch will not reach. So we must jump
5913 // around so we can always reach
5914
5915 Label ok;
5916 jcc(Assembler::equal, ok);
5917 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
5918 bind(ok);
5919 #endif // LP64
5920 }
5921
5922 // get oop result if there is one and reset the value in the thread
5923 if (oop_result->is_valid()) {
5924 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
5925 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
5926 verify_oop(oop_result, "broken oop in call_VM_base");
5927 }
5928 }
5929
5930 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
5931
5932 // Calculate the value for last_Java_sp
5933 // somewhat subtle. call_VM does an intermediate call
5934 // which places a return address on the stack just under the
5935 // stack pointer as the user finsihed with it. This allows
5936 // use to retrieve last_Java_pc from last_Java_sp[-1].
5937 // On 32bit we then have to push additional args on the stack to accomplish
5938 // the actual requested call. On 64bit call_VM only can use register args
5939 // so the only extra space is the return address that call_VM created.
5940 // This hopefully explains the calculations here.
5941
5942 #ifdef _LP64
5943 // We've pushed one address, correct last_Java_sp
5944 lea(rax, Address(rsp, wordSize));
5945 #else
5946 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
5947 #endif // LP64
5948
5949 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
5950
5951 }
5952
5953 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
5954 call_VM_leaf_base(entry_point, number_of_arguments);
5955 }
5956
5957 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
5958 pass_arg0(this, arg_0);
5959 call_VM_leaf(entry_point, 1);
5960 }
5961
5962 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
5963
5964 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5965 pass_arg1(this, arg_1);
5966 pass_arg0(this, arg_0);
5967 call_VM_leaf(entry_point, 2);
5968 }
5969
5970 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
5971 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
5972 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5973 pass_arg2(this, arg_2);
5974 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5975 pass_arg1(this, arg_1);
5976 pass_arg0(this, arg_0);
5977 call_VM_leaf(entry_point, 3);
5978 }
5979
5980 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
5981 }
5982
5983 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
5984 }
5985
5986 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
5987 if (reachable(src1)) {
5988 cmpl(as_Address(src1), imm);
5989 } else {
5990 lea(rscratch1, src1);
5991 cmpl(Address(rscratch1, 0), imm);
5992 }
5993 }
5994
5995 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
5996 assert(!src2.is_lval(), "use cmpptr");
5997 if (reachable(src2)) {
5998 cmpl(src1, as_Address(src2));
5999 } else {
6000 lea(rscratch1, src2);
6001 cmpl(src1, Address(rscratch1, 0));
6002 }
6003 }
6004
6005 void MacroAssembler::cmp32(Register src1, int32_t imm) {
6006 Assembler::cmpl(src1, imm);
6007 }
6008
6009 void MacroAssembler::cmp32(Register src1, Address src2) {
6010 Assembler::cmpl(src1, src2);
6011 }
6012
6013 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6014 ucomisd(opr1, opr2);
6015
6016 Label L;
6017 if (unordered_is_less) {
6018 movl(dst, -1);
6019 jcc(Assembler::parity, L);
6020 jcc(Assembler::below , L);
6021 movl(dst, 0);
6022 jcc(Assembler::equal , L);
6023 increment(dst);
6024 } else { // unordered is greater
6025 movl(dst, 1);
6026 jcc(Assembler::parity, L);
6027 jcc(Assembler::above , L);
6028 movl(dst, 0);
6029 jcc(Assembler::equal , L);
6030 decrementl(dst);
6031 }
6032 bind(L);
6033 }
6034
6035 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6036 ucomiss(opr1, opr2);
6037
6038 Label L;
6039 if (unordered_is_less) {
6040 movl(dst, -1);
6041 jcc(Assembler::parity, L);
6042 jcc(Assembler::below , L);
6043 movl(dst, 0);
6044 jcc(Assembler::equal , L);
6045 increment(dst);
6046 } else { // unordered is greater
6047 movl(dst, 1);
6048 jcc(Assembler::parity, L);
6049 jcc(Assembler::above , L);
6050 movl(dst, 0);
6051 jcc(Assembler::equal , L);
6052 decrementl(dst);
6053 }
6054 bind(L);
6055 }
6056
6057
6058 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6059 if (reachable(src1)) {
6060 cmpb(as_Address(src1), imm);
6061 } else {
6062 lea(rscratch1, src1);
6063 cmpb(Address(rscratch1, 0), imm);
6064 }
6065 }
6066
6067 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6068 #ifdef _LP64
6069 if (src2.is_lval()) {
6070 movptr(rscratch1, src2);
6071 Assembler::cmpq(src1, rscratch1);
6072 } else if (reachable(src2)) {
6073 cmpq(src1, as_Address(src2));
6074 } else {
6075 lea(rscratch1, src2);
6076 Assembler::cmpq(src1, Address(rscratch1, 0));
6077 }
6078 #else
6079 if (src2.is_lval()) {
6080 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6081 } else {
6082 cmpl(src1, as_Address(src2));
6083 }
6084 #endif // _LP64
6085 }
6086
6087 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6088 assert(src2.is_lval(), "not a mem-mem compare");
6089 #ifdef _LP64
6090 // moves src2's literal address
6091 movptr(rscratch1, src2);
6092 Assembler::cmpq(src1, rscratch1);
6093 #else
6094 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6095 #endif // _LP64
6096 }
6097
6098 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6099 if (reachable(adr)) {
6100 if (os::is_MP())
6101 lock();
6102 cmpxchgptr(reg, as_Address(adr));
6103 } else {
6104 lea(rscratch1, adr);
6105 if (os::is_MP())
6106 lock();
6107 cmpxchgptr(reg, Address(rscratch1, 0));
6108 }
6109 }
6110
6111 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6112 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6113 }
6114
6115 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6116 if (reachable(src)) {
6117 comisd(dst, as_Address(src));
6118 } else {
6119 lea(rscratch1, src);
6120 comisd(dst, Address(rscratch1, 0));
6121 }
6122 }
6123
6124 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6125 if (reachable(src)) {
6126 comiss(dst, as_Address(src));
6127 } else {
6128 lea(rscratch1, src);
6129 comiss(dst, Address(rscratch1, 0));
6130 }
6131 }
6132
6133
6134 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6135 Condition negated_cond = negate_condition(cond);
6136 Label L;
6137 jcc(negated_cond, L);
6138 atomic_incl(counter_addr);
6139 bind(L);
6140 }
6141
6142 int MacroAssembler::corrected_idivl(Register reg) {
6143 // Full implementation of Java idiv and irem; checks for
6144 // special case as described in JVM spec., p.243 & p.271.
6145 // The function returns the (pc) offset of the idivl
6146 // instruction - may be needed for implicit exceptions.
6147 //
6148 // normal case special case
6149 //
6150 // input : rax,: dividend min_int
6151 // reg: divisor (may not be rax,/rdx) -1
6152 //
6153 // output: rax,: quotient (= rax, idiv reg) min_int
6154 // rdx: remainder (= rax, irem reg) 0
6155 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6156 const int min_int = 0x80000000;
6157 Label normal_case, special_case;
6158
6159 // check for special case
6160 cmpl(rax, min_int);
6161 jcc(Assembler::notEqual, normal_case);
6162 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6163 cmpl(reg, -1);
6164 jcc(Assembler::equal, special_case);
6165
6166 // handle normal case
6167 bind(normal_case);
6168 cdql();
6169 int idivl_offset = offset();
6170 idivl(reg);
6171
6172 // normal and special case exit
6173 bind(special_case);
6174
6175 return idivl_offset;
6176 }
6177
6178
6179
6180 void MacroAssembler::decrementl(Register reg, int value) {
6181 if (value == min_jint) {subl(reg, value) ; return; }
6182 if (value < 0) { incrementl(reg, -value); return; }
6183 if (value == 0) { ; return; }
6184 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6185 /* else */ { subl(reg, value) ; return; }
6186 }
6187
6188 void MacroAssembler::decrementl(Address dst, int value) {
6189 if (value == min_jint) {subl(dst, value) ; return; }
6190 if (value < 0) { incrementl(dst, -value); return; }
6191 if (value == 0) { ; return; }
6192 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6193 /* else */ { subl(dst, value) ; return; }
6194 }
6195
6196 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6197 assert (shift_value > 0, "illegal shift value");
6198 Label _is_positive;
6199 testl (reg, reg);
6200 jcc (Assembler::positive, _is_positive);
6201 int offset = (1 << shift_value) - 1 ;
6202
6203 if (offset == 1) {
6204 incrementl(reg);
6205 } else {
6206 addl(reg, offset);
6207 }
6208
6209 bind (_is_positive);
6210 sarl(reg, shift_value);
6211 }
6212
6213 // !defined(COMPILER2) is because of stupid core builds
6214 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6215 void MacroAssembler::empty_FPU_stack() {
6216 if (VM_Version::supports_mmx()) {
6217 emms();
6218 } else {
6219 for (int i = 8; i-- > 0; ) ffree(i);
6220 }
6221 }
6222 #endif // !LP64 || C1 || !C2
6223
6224
6225 // Defines obj, preserves var_size_in_bytes
6226 void MacroAssembler::eden_allocate(Register obj,
6227 Register var_size_in_bytes,
6228 int con_size_in_bytes,
6229 Register t1,
6230 Label& slow_case) {
6231 assert(obj == rax, "obj must be in rax, for cmpxchg");
6232 assert_different_registers(obj, var_size_in_bytes, t1);
6233 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6234 jmp(slow_case);
6235 } else {
6236 Register end = t1;
6237 Label retry;
6238 bind(retry);
6239 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6240 movptr(obj, heap_top);
6241 if (var_size_in_bytes == noreg) {
6242 lea(end, Address(obj, con_size_in_bytes));
6243 } else {
6244 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6245 }
6246 // if end < obj then we wrapped around => object too long => slow case
6247 cmpptr(end, obj);
6248 jcc(Assembler::below, slow_case);
6249 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6250 jcc(Assembler::above, slow_case);
6251 // Compare obj with the top addr, and if still equal, store the new top addr in
6252 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6253 // it otherwise. Use lock prefix for atomicity on MPs.
6254 locked_cmpxchgptr(end, heap_top);
6255 jcc(Assembler::notEqual, retry);
6256 }
6257 }
6258
6259 void MacroAssembler::enter() {
6260 push(rbp);
6261 mov(rbp, rsp);
6262 }
6263
6264 void MacroAssembler::fcmp(Register tmp) {
6265 fcmp(tmp, 1, true, true);
6266 }
6267
6268 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
6269 assert(!pop_right || pop_left, "usage error");
6270 if (VM_Version::supports_cmov()) {
6271 assert(tmp == noreg, "unneeded temp");
6272 if (pop_left) {
6273 fucomip(index);
6274 } else {
6275 fucomi(index);
6276 }
6277 if (pop_right) {
6278 fpop();
6279 }
6280 } else {
6281 assert(tmp != noreg, "need temp");
6282 if (pop_left) {
6283 if (pop_right) {
6284 fcompp();
6285 } else {
6286 fcomp(index);
6287 }
6288 } else {
6289 fcom(index);
6290 }
6291 // convert FPU condition into eflags condition via rax,
6292 save_rax(tmp);
6293 fwait(); fnstsw_ax();
6294 sahf();
6295 restore_rax(tmp);
6296 }
6297 // condition codes set as follows:
6298 //
6299 // CF (corresponds to C0) if x < y
6300 // PF (corresponds to C2) if unordered
6301 // ZF (corresponds to C3) if x = y
6302 }
6303
6304 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
6305 fcmp2int(dst, unordered_is_less, 1, true, true);
6306 }
6307
6308 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
6309 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
6310 Label L;
6311 if (unordered_is_less) {
6312 movl(dst, -1);
6313 jcc(Assembler::parity, L);
6314 jcc(Assembler::below , L);
6315 movl(dst, 0);
6316 jcc(Assembler::equal , L);
6317 increment(dst);
6318 } else { // unordered is greater
6319 movl(dst, 1);
6320 jcc(Assembler::parity, L);
6321 jcc(Assembler::above , L);
6322 movl(dst, 0);
6323 jcc(Assembler::equal , L);
6324 decrementl(dst);
6325 }
6326 bind(L);
6327 }
6328
6329 void MacroAssembler::fld_d(AddressLiteral src) {
6330 fld_d(as_Address(src));
6331 }
6332
6333 void MacroAssembler::fld_s(AddressLiteral src) {
6334 fld_s(as_Address(src));
6335 }
6336
6337 void MacroAssembler::fld_x(AddressLiteral src) {
6338 Assembler::fld_x(as_Address(src));
6339 }
6340
6341 void MacroAssembler::fldcw(AddressLiteral src) {
6342 Assembler::fldcw(as_Address(src));
6343 }
6344
6345 void MacroAssembler::fpop() {
6346 ffree();
6347 fincstp();
6348 }
6349
6350 void MacroAssembler::fremr(Register tmp) {
6351 save_rax(tmp);
6352 { Label L;
6353 bind(L);
6354 fprem();
6355 fwait(); fnstsw_ax();
6356 #ifdef _LP64
6357 testl(rax, 0x400);
6358 jcc(Assembler::notEqual, L);
6359 #else
6360 sahf();
6361 jcc(Assembler::parity, L);
6362 #endif // _LP64
6363 }
6364 restore_rax(tmp);
6365 // Result is in ST0.
6366 // Note: fxch & fpop to get rid of ST1
6367 // (otherwise FPU stack could overflow eventually)
6368 fxch(1);
6369 fpop();
6370 }
6371
6372
6373 void MacroAssembler::incrementl(AddressLiteral dst) {
6374 if (reachable(dst)) {
6375 incrementl(as_Address(dst));
6376 } else {
6377 lea(rscratch1, dst);
6378 incrementl(Address(rscratch1, 0));
6379 }
6380 }
6381
6382 void MacroAssembler::incrementl(ArrayAddress dst) {
6383 incrementl(as_Address(dst));
6384 }
6385
6386 void MacroAssembler::incrementl(Register reg, int value) {
6387 if (value == min_jint) {addl(reg, value) ; return; }
6388 if (value < 0) { decrementl(reg, -value); return; }
6389 if (value == 0) { ; return; }
6390 if (value == 1 && UseIncDec) { incl(reg) ; return; }
6391 /* else */ { addl(reg, value) ; return; }
6392 }
6393
6394 void MacroAssembler::incrementl(Address dst, int value) {
6395 if (value == min_jint) {addl(dst, value) ; return; }
6396 if (value < 0) { decrementl(dst, -value); return; }
6397 if (value == 0) { ; return; }
6398 if (value == 1 && UseIncDec) { incl(dst) ; return; }
6399 /* else */ { addl(dst, value) ; return; }
6400 }
6401
6402 void MacroAssembler::jump(AddressLiteral dst) {
6403 if (reachable(dst)) {
6404 jmp_literal(dst.target(), dst.rspec());
6405 } else {
6406 lea(rscratch1, dst);
6407 jmp(rscratch1);
6408 }
6409 }
6410
6411 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
6412 if (reachable(dst)) {
6413 InstructionMark im(this);
6414 relocate(dst.reloc());
6415 const int short_size = 2;
6416 const int long_size = 6;
6417 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
6418 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
6419 // 0111 tttn #8-bit disp
6420 emit_byte(0x70 | cc);
6421 emit_byte((offs - short_size) & 0xFF);
6422 } else {
6423 // 0000 1111 1000 tttn #32-bit disp
6424 emit_byte(0x0F);
6425 emit_byte(0x80 | cc);
6426 emit_long(offs - long_size);
6427 }
6428 } else {
6429 #ifdef ASSERT
6430 warning("reversing conditional branch");
6431 #endif /* ASSERT */
6432 Label skip;
6433 jccb(reverse[cc], skip);
6434 lea(rscratch1, dst);
6435 Assembler::jmp(rscratch1);
6436 bind(skip);
6437 }
6438 }
6439
6440 void MacroAssembler::ldmxcsr(AddressLiteral src) {
6441 if (reachable(src)) {
6442 Assembler::ldmxcsr(as_Address(src));
6443 } else {
6444 lea(rscratch1, src);
6445 Assembler::ldmxcsr(Address(rscratch1, 0));
6446 }
6447 }
6448
6449 int MacroAssembler::load_signed_byte(Register dst, Address src) {
6450 int off;
6451 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6452 off = offset();
6453 movsbl(dst, src); // movsxb
6454 } else {
6455 off = load_unsigned_byte(dst, src);
6456 shll(dst, 24);
6457 sarl(dst, 24);
6458 }
6459 return off;
6460 }
6461
6462 // Note: load_signed_short used to be called load_signed_word.
6463 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
6464 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
6465 // The term "word" in HotSpot means a 32- or 64-bit machine word.
6466 int MacroAssembler::load_signed_short(Register dst, Address src) {
6467 int off;
6468 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6469 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
6470 // version but this is what 64bit has always done. This seems to imply
6471 // that users are only using 32bits worth.
6472 off = offset();
6473 movswl(dst, src); // movsxw
6474 } else {
6475 off = load_unsigned_short(dst, src);
6476 shll(dst, 16);
6477 sarl(dst, 16);
6478 }
6479 return off;
6480 }
6481
6482 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
6483 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6484 // and "3.9 Partial Register Penalties", p. 22).
6485 int off;
6486 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
6487 off = offset();
6488 movzbl(dst, src); // movzxb
6489 } else {
6490 xorl(dst, dst);
6491 off = offset();
6492 movb(dst, src);
6493 }
6494 return off;
6495 }
6496
6497 // Note: load_unsigned_short used to be called load_unsigned_word.
6498 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
6499 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6500 // and "3.9 Partial Register Penalties", p. 22).
6501 int off;
6502 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
6503 off = offset();
6504 movzwl(dst, src); // movzxw
6505 } else {
6506 xorl(dst, dst);
6507 off = offset();
6508 movw(dst, src);
6509 }
6510 return off;
6511 }
6512
6513 void MacroAssembler::load_sized_value(Register dst, Address src,
6514 size_t size_in_bytes, bool is_signed) {
6515 switch (size_in_bytes) {
6516 #ifndef _LP64
6517 // For case 8, caller is responsible for manually loading
6518 // the second word into another register.
6519 case 8: movl(dst, src); break;
6520 #else
6521 case 8: movq(dst, src); break;
6522 #endif
6523 case 4: movl(dst, src); break;
6524 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
6525 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
6526 default: ShouldNotReachHere();
6527 }
6528 }
6529
6530 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
6531 if (reachable(dst)) {
6532 movl(as_Address(dst), src);
6533 } else {
6534 lea(rscratch1, dst);
6535 movl(Address(rscratch1, 0), src);
6536 }
6537 }
6538
6539 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
6540 if (reachable(src)) {
6541 movl(dst, as_Address(src));
6542 } else {
6543 lea(rscratch1, src);
6544 movl(dst, Address(rscratch1, 0));
6545 }
6546 }
6547
6548 // C++ bool manipulation
6549
6550 void MacroAssembler::movbool(Register dst, Address src) {
6551 if(sizeof(bool) == 1)
6552 movb(dst, src);
6553 else if(sizeof(bool) == 2)
6554 movw(dst, src);
6555 else if(sizeof(bool) == 4)
6556 movl(dst, src);
6557 else
6558 // unsupported
6559 ShouldNotReachHere();
6560 }
6561
6562 void MacroAssembler::movbool(Address dst, bool boolconst) {
6563 if(sizeof(bool) == 1)
6564 movb(dst, (int) boolconst);
6565 else if(sizeof(bool) == 2)
6566 movw(dst, (int) boolconst);
6567 else if(sizeof(bool) == 4)
6568 movl(dst, (int) boolconst);
6569 else
6570 // unsupported
6571 ShouldNotReachHere();
6572 }
6573
6574 void MacroAssembler::movbool(Address dst, Register src) {
6575 if(sizeof(bool) == 1)
6576 movb(dst, src);
6577 else if(sizeof(bool) == 2)
6578 movw(dst, src);
6579 else if(sizeof(bool) == 4)
6580 movl(dst, src);
6581 else
6582 // unsupported
6583 ShouldNotReachHere();
6584 }
6585
6586 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
6587 movb(as_Address(dst), src);
6588 }
6589
6590 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
6591 if (reachable(src)) {
6592 if (UseXmmLoadAndClearUpper) {
6593 movsd (dst, as_Address(src));
6594 } else {
6595 movlpd(dst, as_Address(src));
6596 }
6597 } else {
6598 lea(rscratch1, src);
6599 if (UseXmmLoadAndClearUpper) {
6600 movsd (dst, Address(rscratch1, 0));
6601 } else {
6602 movlpd(dst, Address(rscratch1, 0));
6603 }
6604 }
6605 }
6606
6607 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
6608 if (reachable(src)) {
6609 movss(dst, as_Address(src));
6610 } else {
6611 lea(rscratch1, src);
6612 movss(dst, Address(rscratch1, 0));
6613 }
6614 }
6615
6616 void MacroAssembler::movptr(Register dst, Register src) {
6617 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6618 }
6619
6620 void MacroAssembler::movptr(Register dst, Address src) {
6621 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6622 }
6623
6624 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6625 void MacroAssembler::movptr(Register dst, intptr_t src) {
6626 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6627 }
6628
6629 void MacroAssembler::movptr(Address dst, Register src) {
6630 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6631 }
6632
6633 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
6634 if (reachable(src)) {
6635 movss(dst, as_Address(src));
6636 } else {
6637 lea(rscratch1, src);
6638 movss(dst, Address(rscratch1, 0));
6639 }
6640 }
6641
6642 void MacroAssembler::null_check(Register reg, int offset) {
6643 if (needs_explicit_null_check(offset)) {
6644 // provoke OS NULL exception if reg = NULL by
6645 // accessing M[reg] w/o changing any (non-CC) registers
6646 // NOTE: cmpl is plenty here to provoke a segv
6647 cmpptr(rax, Address(reg, 0));
6648 // Note: should probably use testl(rax, Address(reg, 0));
6649 // may be shorter code (however, this version of
6650 // testl needs to be implemented first)
6651 } else {
6652 // nothing to do, (later) access of M[reg + offset]
6653 // will provoke OS NULL exception if reg = NULL
6654 }
6655 }
6656
6657 void MacroAssembler::os_breakpoint() {
6658 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
6659 // (e.g., MSVC can't call ps() otherwise)
6660 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
6661 }
6662
6663 void MacroAssembler::pop_CPU_state() {
6664 pop_FPU_state();
6665 pop_IU_state();
6666 }
6667
6668 void MacroAssembler::pop_FPU_state() {
6669 NOT_LP64(frstor(Address(rsp, 0));)
6670 LP64_ONLY(fxrstor(Address(rsp, 0));)
6671 addptr(rsp, FPUStateSizeInWords * wordSize);
6672 }
6673
6674 void MacroAssembler::pop_IU_state() {
6675 popa();
6676 LP64_ONLY(addq(rsp, 8));
6677 popf();
6678 }
6679
6680 // Save Integer and Float state
6681 // Warning: Stack must be 16 byte aligned (64bit)
6682 void MacroAssembler::push_CPU_state() {
6683 push_IU_state();
6684 push_FPU_state();
6685 }
6686
6687 void MacroAssembler::push_FPU_state() {
6688 subptr(rsp, FPUStateSizeInWords * wordSize);
6689 #ifndef _LP64
6690 fnsave(Address(rsp, 0));
6691 fwait();
6692 #else
6693 fxsave(Address(rsp, 0));
6694 #endif // LP64
6695 }
6696
6697 void MacroAssembler::push_IU_state() {
6698 // Push flags first because pusha kills them
6699 pushf();
6700 // Make sure rsp stays 16-byte aligned
6701 LP64_ONLY(subq(rsp, 8));
6702 pusha();
6703 }
6704
6705 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
6706 // determine java_thread register
6707 if (!java_thread->is_valid()) {
6708 java_thread = rdi;
6709 get_thread(java_thread);
6710 }
6711 // we must set sp to zero to clear frame
6712 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
6713 if (clear_fp) {
6714 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
6715 }
6716
6717 if (clear_pc)
6718 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
6719
6720 }
6721
6722 void MacroAssembler::restore_rax(Register tmp) {
6723 if (tmp == noreg) pop(rax);
6724 else if (tmp != rax) mov(rax, tmp);
6725 }
6726
6727 void MacroAssembler::round_to(Register reg, int modulus) {
6728 addptr(reg, modulus - 1);
6729 andptr(reg, -modulus);
6730 }
6731
6732 void MacroAssembler::save_rax(Register tmp) {
6733 if (tmp == noreg) push(rax);
6734 else if (tmp != rax) mov(tmp, rax);
6735 }
6736
6737 // Write serialization page so VM thread can do a pseudo remote membar.
6738 // We use the current thread pointer to calculate a thread specific
6739 // offset to write to within the page. This minimizes bus traffic
6740 // due to cache line collision.
6741 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
6742 movl(tmp, thread);
6743 shrl(tmp, os::get_serialize_page_shift_count());
6744 andl(tmp, (os::vm_page_size() - sizeof(int)));
6745
6746 Address index(noreg, tmp, Address::times_1);
6747 ExternalAddress page(os::get_memory_serialize_page());
6748
6749 // Size of store must match masking code above
6750 movl(as_Address(ArrayAddress(page, index)), tmp);
6751 }
6752
6753 // Calls to C land
6754 //
6755 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
6756 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
6757 // has to be reset to 0. This is required to allow proper stack traversal.
6758 void MacroAssembler::set_last_Java_frame(Register java_thread,
6759 Register last_java_sp,
6760 Register last_java_fp,
6761 address last_java_pc) {
6762 // determine java_thread register
6763 if (!java_thread->is_valid()) {
6764 java_thread = rdi;
6765 get_thread(java_thread);
6766 }
6767 // determine last_java_sp register
6768 if (!last_java_sp->is_valid()) {
6769 last_java_sp = rsp;
6770 }
6771
6772 // last_java_fp is optional
6773
6774 if (last_java_fp->is_valid()) {
6775 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
6776 }
6777
6778 // last_java_pc is optional
6779
6780 if (last_java_pc != NULL) {
6781 lea(Address(java_thread,
6782 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
6783 InternalAddress(last_java_pc));
6784
6785 }
6786 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
6787 }
6788
6789 void MacroAssembler::shlptr(Register dst, int imm8) {
6790 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
6791 }
6792
6793 void MacroAssembler::shrptr(Register dst, int imm8) {
6794 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
6795 }
6796
6797 void MacroAssembler::sign_extend_byte(Register reg) {
6798 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
6799 movsbl(reg, reg); // movsxb
6800 } else {
6801 shll(reg, 24);
6802 sarl(reg, 24);
6803 }
6804 }
6805
6806 void MacroAssembler::sign_extend_short(Register reg) {
6807 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6808 movswl(reg, reg); // movsxw
6809 } else {
6810 shll(reg, 16);
6811 sarl(reg, 16);
6812 }
6813 }
6814
6815 //////////////////////////////////////////////////////////////////////////////////
6816 #ifndef SERIALGC
6817
6818 void MacroAssembler::g1_write_barrier_pre(Register obj,
6819 #ifndef _LP64
6820 Register thread,
6821 #endif
6822 Register tmp,
6823 Register tmp2,
6824 bool tosca_live) {
6825 LP64_ONLY(Register thread = r15_thread;)
6826 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6827 PtrQueue::byte_offset_of_active()));
6828
6829 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6830 PtrQueue::byte_offset_of_index()));
6831 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6832 PtrQueue::byte_offset_of_buf()));
6833
6834
6835 Label done;
6836 Label runtime;
6837
6838 // if (!marking_in_progress) goto done;
6839 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
6840 cmpl(in_progress, 0);
6841 } else {
6842 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
6843 cmpb(in_progress, 0);
6844 }
6845 jcc(Assembler::equal, done);
6846
6847 // if (x.f == NULL) goto done;
6848 #ifdef _LP64
6849 load_heap_oop(tmp2, Address(obj, 0));
6850 #else
6851 movptr(tmp2, Address(obj, 0));
6852 #endif
6853 cmpptr(tmp2, (int32_t) NULL_WORD);
6854 jcc(Assembler::equal, done);
6855
6856 // Can we store original value in the thread's buffer?
6857
6858 #ifdef _LP64
6859 movslq(tmp, index);
6860 cmpq(tmp, 0);
6861 #else
6862 cmpl(index, 0);
6863 #endif
6864 jcc(Assembler::equal, runtime);
6865 #ifdef _LP64
6866 subq(tmp, wordSize);
6867 movl(index, tmp);
6868 addq(tmp, buffer);
6869 #else
6870 subl(index, wordSize);
6871 movl(tmp, buffer);
6872 addl(tmp, index);
6873 #endif
6874 movptr(Address(tmp, 0), tmp2);
6875 jmp(done);
6876 bind(runtime);
6877 // save the live input values
6878 if(tosca_live) push(rax);
6879 push(obj);
6880 #ifdef _LP64
6881 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread);
6882 #else
6883 push(thread);
6884 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread);
6885 pop(thread);
6886 #endif
6887 pop(obj);
6888 if(tosca_live) pop(rax);
6889 bind(done);
6890
6891 }
6892
6893 void MacroAssembler::g1_write_barrier_post(Register store_addr,
6894 Register new_val,
6895 #ifndef _LP64
6896 Register thread,
6897 #endif
6898 Register tmp,
6899 Register tmp2) {
6900
6901 LP64_ONLY(Register thread = r15_thread;)
6902 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6903 PtrQueue::byte_offset_of_index()));
6904 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6905 PtrQueue::byte_offset_of_buf()));
6906 BarrierSet* bs = Universe::heap()->barrier_set();
6907 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
6908 Label done;
6909 Label runtime;
6910
6911 // Does store cross heap regions?
6912
6913 movptr(tmp, store_addr);
6914 xorptr(tmp, new_val);
6915 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
6916 jcc(Assembler::equal, done);
6917
6918 // crosses regions, storing NULL?
6919
6920 cmpptr(new_val, (int32_t) NULL_WORD);
6921 jcc(Assembler::equal, done);
6922
6923 // storing region crossing non-NULL, is card already dirty?
6924
6925 ExternalAddress cardtable((address) ct->byte_map_base);
6926 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
6927 #ifdef _LP64
6928 const Register card_addr = tmp;
6929
6930 movq(card_addr, store_addr);
6931 shrq(card_addr, CardTableModRefBS::card_shift);
6932
6933 lea(tmp2, cardtable);
6934
6935 // get the address of the card
6936 addq(card_addr, tmp2);
6937 #else
6938 const Register card_index = tmp;
6939
6940 movl(card_index, store_addr);
6941 shrl(card_index, CardTableModRefBS::card_shift);
6942
6943 Address index(noreg, card_index, Address::times_1);
6944 const Register card_addr = tmp;
6945 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
6946 #endif
6947 cmpb(Address(card_addr, 0), 0);
6948 jcc(Assembler::equal, done);
6949
6950 // storing a region crossing, non-NULL oop, card is clean.
6951 // dirty card and log.
6952
6953 movb(Address(card_addr, 0), 0);
6954
6955 cmpl(queue_index, 0);
6956 jcc(Assembler::equal, runtime);
6957 subl(queue_index, wordSize);
6958 movptr(tmp2, buffer);
6959 #ifdef _LP64
6960 movslq(rscratch1, queue_index);
6961 addq(tmp2, rscratch1);
6962 movq(Address(tmp2, 0), card_addr);
6963 #else
6964 addl(tmp2, queue_index);
6965 movl(Address(tmp2, 0), card_index);
6966 #endif
6967 jmp(done);
6968
6969 bind(runtime);
6970 // save the live input values
6971 push(store_addr);
6972 push(new_val);
6973 #ifdef _LP64
6974 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
6975 #else
6976 push(thread);
6977 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
6978 pop(thread);
6979 #endif
6980 pop(new_val);
6981 pop(store_addr);
6982
6983 bind(done);
6984
6985 }
6986
6987 #endif // SERIALGC
6988 //////////////////////////////////////////////////////////////////////////////////
6989
6990
6991 void MacroAssembler::store_check(Register obj) {
6992 // Does a store check for the oop in register obj. The content of
6993 // register obj is destroyed afterwards.
6994 store_check_part_1(obj);
6995 store_check_part_2(obj);
6996 }
6997
6998 void MacroAssembler::store_check(Register obj, Address dst) {
6999 store_check(obj);
7000 }
7001
7002
7003 // split the store check operation so that other instructions can be scheduled inbetween
7004 void MacroAssembler::store_check_part_1(Register obj) {
7005 BarrierSet* bs = Universe::heap()->barrier_set();
7006 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7007 shrptr(obj, CardTableModRefBS::card_shift);
7008 }
7009
7010 void MacroAssembler::store_check_part_2(Register obj) {
7011 BarrierSet* bs = Universe::heap()->barrier_set();
7012 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7013 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
7014 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7015
7016 // The calculation for byte_map_base is as follows:
7017 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
7018 // So this essentially converts an address to a displacement and
7019 // it will never need to be relocated. On 64bit however the value may be too
7020 // large for a 32bit displacement
7021
7022 intptr_t disp = (intptr_t) ct->byte_map_base;
7023 if (is_simm32(disp)) {
7024 Address cardtable(noreg, obj, Address::times_1, disp);
7025 movb(cardtable, 0);
7026 } else {
7027 // By doing it as an ExternalAddress disp could be converted to a rip-relative
7028 // displacement and done in a single instruction given favorable mapping and
7029 // a smarter version of as_Address. Worst case it is two instructions which
7030 // is no worse off then loading disp into a register and doing as a simple
7031 // Address() as above.
7032 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
7033 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
7034 // in some cases we'll get a single instruction version.
7035
7036 ExternalAddress cardtable((address)disp);
7037 Address index(noreg, obj, Address::times_1);
7038 movb(as_Address(ArrayAddress(cardtable, index)), 0);
7039 }
7040 }
7041
7042 void MacroAssembler::subptr(Register dst, int32_t imm32) {
7043 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
7044 }
7045
7046 void MacroAssembler::subptr(Register dst, Register src) {
7047 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
7048 }
7049
7050 void MacroAssembler::test32(Register src1, AddressLiteral src2) {
7051 // src2 must be rval
7052
7053 if (reachable(src2)) {
7054 testl(src1, as_Address(src2));
7055 } else {
7056 lea(rscratch1, src2);
7057 testl(src1, Address(rscratch1, 0));
7058 }
7059 }
7060
7061 // C++ bool manipulation
7062 void MacroAssembler::testbool(Register dst) {
7063 if(sizeof(bool) == 1)
7064 testb(dst, 0xff);
7065 else if(sizeof(bool) == 2) {
7066 // testw implementation needed for two byte bools
7067 ShouldNotReachHere();
7068 } else if(sizeof(bool) == 4)
7069 testl(dst, dst);
7070 else
7071 // unsupported
7072 ShouldNotReachHere();
7073 }
7074
7075 void MacroAssembler::testptr(Register dst, Register src) {
7076 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
7077 }
7078
7079 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
7080 void MacroAssembler::tlab_allocate(Register obj,
7081 Register var_size_in_bytes,
7082 int con_size_in_bytes,
7083 Register t1,
7084 Register t2,
7085 Label& slow_case) {
7086 assert_different_registers(obj, t1, t2);
7087 assert_different_registers(obj, var_size_in_bytes, t1);
7088 Register end = t2;
7089 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
7090
7091 verify_tlab();
7092
7093 NOT_LP64(get_thread(thread));
7094
7095 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
7096 if (var_size_in_bytes == noreg) {
7097 lea(end, Address(obj, con_size_in_bytes));
7098 } else {
7099 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
7100 }
7101 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
7102 jcc(Assembler::above, slow_case);
7103
7104 // update the tlab top pointer
7105 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
7106
7107 // recover var_size_in_bytes if necessary
7108 if (var_size_in_bytes == end) {
7109 subptr(var_size_in_bytes, obj);
7110 }
7111 verify_tlab();
7112 }
7113
7114 // Preserves rbx, and rdx.
7115 void MacroAssembler::tlab_refill(Label& retry,
7116 Label& try_eden,
7117 Label& slow_case) {
7118 Register top = rax;
7119 Register t1 = rcx;
7120 Register t2 = rsi;
7121 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
7122 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
7123 Label do_refill, discard_tlab;
7124
7125 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
7126 // No allocation in the shared eden.
7127 jmp(slow_case);
7128 }
7129
7130 NOT_LP64(get_thread(thread_reg));
7131
7132 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7133 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7134
7135 // calculate amount of free space
7136 subptr(t1, top);
7137 shrptr(t1, LogHeapWordSize);
7138
7139 // Retain tlab and allocate object in shared space if
7140 // the amount free in the tlab is too large to discard.
7141 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
7142 jcc(Assembler::lessEqual, discard_tlab);
7143
7144 // Retain
7145 // %%% yuck as movptr...
7146 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
7147 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
7148 if (TLABStats) {
7149 // increment number of slow_allocations
7150 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
7151 }
7152 jmp(try_eden);
7153
7154 bind(discard_tlab);
7155 if (TLABStats) {
7156 // increment number of refills
7157 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
7158 // accumulate wastage -- t1 is amount free in tlab
7159 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
7160 }
7161
7162 // if tlab is currently allocated (top or end != null) then
7163 // fill [top, end + alignment_reserve) with array object
7164 testptr (top, top);
7165 jcc(Assembler::zero, do_refill);
7166
7167 // set up the mark word
7168 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
7169 // set the length to the remaining space
7170 subptr(t1, typeArrayOopDesc::header_size(T_INT));
7171 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
7172 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
7173 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
7174 // set klass to intArrayKlass
7175 // dubious reloc why not an oop reloc?
7176 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
7177 // store klass last. concurrent gcs assumes klass length is valid if
7178 // klass field is not null.
7179 store_klass(top, t1);
7180
7181 // refill the tlab with an eden allocation
7182 bind(do_refill);
7183 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7184 shlptr(t1, LogHeapWordSize);
7185 // add object_size ??
7186 eden_allocate(top, t1, 0, t2, slow_case);
7187
7188 // Check that t1 was preserved in eden_allocate.
7189 #ifdef ASSERT
7190 if (UseTLAB) {
7191 Label ok;
7192 Register tsize = rsi;
7193 assert_different_registers(tsize, thread_reg, t1);
7194 push(tsize);
7195 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7196 shlptr(tsize, LogHeapWordSize);
7197 cmpptr(t1, tsize);
7198 jcc(Assembler::equal, ok);
7199 stop("assert(t1 != tlab size)");
7200 should_not_reach_here();
7201
7202 bind(ok);
7203 pop(tsize);
7204 }
7205 #endif
7206 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
7207 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
7208 addptr(top, t1);
7209 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
7210 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
7211 verify_tlab();
7212 jmp(retry);
7213 }
7214
7215 static const double pi_4 = 0.7853981633974483;
7216
7217 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
7218 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
7219 // was attempted in this code; unfortunately it appears that the
7220 // switch to 80-bit precision and back causes this to be
7221 // unprofitable compared with simply performing a runtime call if
7222 // the argument is out of the (-pi/4, pi/4) range.
7223
7224 Register tmp = noreg;
7225 if (!VM_Version::supports_cmov()) {
7226 // fcmp needs a temporary so preserve rbx,
7227 tmp = rbx;
7228 push(tmp);
7229 }
7230
7231 Label slow_case, done;
7232
7233 ExternalAddress pi4_adr = (address)&pi_4;
7234 if (reachable(pi4_adr)) {
7235 // x ?<= pi/4
7236 fld_d(pi4_adr);
7237 fld_s(1); // Stack: X PI/4 X
7238 fabs(); // Stack: |X| PI/4 X
7239 fcmp(tmp);
7240 jcc(Assembler::above, slow_case);
7241
7242 // fastest case: -pi/4 <= x <= pi/4
7243 switch(trig) {
7244 case 's':
7245 fsin();
7246 break;
7247 case 'c':
7248 fcos();
7249 break;
7250 case 't':
7251 ftan();
7252 break;
7253 default:
7254 assert(false, "bad intrinsic");
7255 break;
7256 }
7257 jmp(done);
7258 }
7259
7260 // slow case: runtime call
7261 bind(slow_case);
7262 // Preserve registers across runtime call
7263 pusha();
7264 int incoming_argument_and_return_value_offset = -1;
7265 if (num_fpu_regs_in_use > 1) {
7266 // Must preserve all other FPU regs (could alternatively convert
7267 // SharedRuntime::dsin and dcos into assembly routines known not to trash
7268 // FPU state, but can not trust C compiler)
7269 NEEDS_CLEANUP;
7270 // NOTE that in this case we also push the incoming argument to
7271 // the stack and restore it later; we also use this stack slot to
7272 // hold the return value from dsin or dcos.
7273 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7274 subptr(rsp, sizeof(jdouble));
7275 fstp_d(Address(rsp, 0));
7276 }
7277 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
7278 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
7279 }
7280 subptr(rsp, sizeof(jdouble));
7281 fstp_d(Address(rsp, 0));
7282 #ifdef _LP64
7283 movdbl(xmm0, Address(rsp, 0));
7284 #endif // _LP64
7285
7286 // NOTE: we must not use call_VM_leaf here because that requires a
7287 // complete interpreter frame in debug mode -- same bug as 4387334
7288 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
7289 // do proper 64bit abi
7290
7291 NEEDS_CLEANUP;
7292 // Need to add stack banging before this runtime call if it needs to
7293 // be taken; however, there is no generic stack banging routine at
7294 // the MacroAssembler level
7295 switch(trig) {
7296 case 's':
7297 {
7298 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
7299 }
7300 break;
7301 case 'c':
7302 {
7303 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
7304 }
7305 break;
7306 case 't':
7307 {
7308 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
7309 }
7310 break;
7311 default:
7312 assert(false, "bad intrinsic");
7313 break;
7314 }
7315 #ifdef _LP64
7316 movsd(Address(rsp, 0), xmm0);
7317 fld_d(Address(rsp, 0));
7318 #endif // _LP64
7319 addptr(rsp, sizeof(jdouble));
7320 if (num_fpu_regs_in_use > 1) {
7321 // Must save return value to stack and then restore entire FPU stack
7322 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
7323 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7324 fld_d(Address(rsp, 0));
7325 addptr(rsp, sizeof(jdouble));
7326 }
7327 }
7328 popa();
7329
7330 // Come here with result in F-TOS
7331 bind(done);
7332
7333 if (tmp != noreg) {
7334 pop(tmp);
7335 }
7336 }
7337
7338
7339 // Look up the method for a megamorphic invokeinterface call.
7340 // The target method is determined by <intf_klass, itable_index>.
7341 // The receiver klass is in recv_klass.
7342 // On success, the result will be in method_result, and execution falls through.
7343 // On failure, execution transfers to the given label.
7344 void MacroAssembler::lookup_interface_method(Register recv_klass,
7345 Register intf_klass,
7346 RegisterOrConstant itable_index,
7347 Register method_result,
7348 Register scan_temp,
7349 Label& L_no_such_interface) {
7350 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
7351 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
7352 "caller must use same register for non-constant itable index as for method");
7353
7354 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
7355 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
7356 int itentry_off = itableMethodEntry::method_offset_in_bytes();
7357 int scan_step = itableOffsetEntry::size() * wordSize;
7358 int vte_size = vtableEntry::size() * wordSize;
7359 Address::ScaleFactor times_vte_scale = Address::times_ptr;
7360 assert(vte_size == wordSize, "else adjust times_vte_scale");
7361
7362 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
7363
7364 // %%% Could store the aligned, prescaled offset in the klassoop.
7365 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
7366 if (HeapWordsPerLong > 1) {
7367 // Round up to align_object_offset boundary
7368 // see code for instanceKlass::start_of_itable!
7369 round_to(scan_temp, BytesPerLong);
7370 }
7371
7372 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
7373 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
7374 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
7375
7376 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
7377 // if (scan->interface() == intf) {
7378 // result = (klass + scan->offset() + itable_index);
7379 // }
7380 // }
7381 Label search, found_method;
7382
7383 for (int peel = 1; peel >= 0; peel--) {
7384 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
7385 cmpptr(intf_klass, method_result);
7386
7387 if (peel) {
7388 jccb(Assembler::equal, found_method);
7389 } else {
7390 jccb(Assembler::notEqual, search);
7391 // (invert the test to fall through to found_method...)
7392 }
7393
7394 if (!peel) break;
7395
7396 bind(search);
7397
7398 // Check that the previous entry is non-null. A null entry means that
7399 // the receiver class doesn't implement the interface, and wasn't the
7400 // same as when the caller was compiled.
7401 testptr(method_result, method_result);
7402 jcc(Assembler::zero, L_no_such_interface);
7403 addptr(scan_temp, scan_step);
7404 }
7405
7406 bind(found_method);
7407
7408 // Got a hit.
7409 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
7410 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
7411 }
7412
7413
7414 void MacroAssembler::check_klass_subtype(Register sub_klass,
7415 Register super_klass,
7416 Register temp_reg,
7417 Label& L_success) {
7418 Label L_failure;
7419 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
7420 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
7421 bind(L_failure);
7422 }
7423
7424
7425 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
7426 Register super_klass,
7427 Register temp_reg,
7428 Label* L_success,
7429 Label* L_failure,
7430 Label* L_slow_path,
7431 RegisterOrConstant super_check_offset) {
7432 assert_different_registers(sub_klass, super_klass, temp_reg);
7433 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
7434 if (super_check_offset.is_register()) {
7435 assert_different_registers(sub_klass, super_klass,
7436 super_check_offset.as_register());
7437 } else if (must_load_sco) {
7438 assert(temp_reg != noreg, "supply either a temp or a register offset");
7439 }
7440
7441 Label L_fallthrough;
7442 int label_nulls = 0;
7443 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7444 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7445 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
7446 assert(label_nulls <= 1, "at most one NULL in the batch");
7447
7448 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7449 Klass::secondary_super_cache_offset_in_bytes());
7450 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
7451 Klass::super_check_offset_offset_in_bytes());
7452 Address super_check_offset_addr(super_klass, sco_offset);
7453
7454 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
7455 // range of a jccb. If this routine grows larger, reconsider at
7456 // least some of these.
7457 #define local_jcc(assembler_cond, label) \
7458 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
7459 else jcc( assembler_cond, label) /*omit semi*/
7460
7461 // Hacked jmp, which may only be used just before L_fallthrough.
7462 #define final_jmp(label) \
7463 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
7464 else jmp(label) /*omit semi*/
7465
7466 // If the pointers are equal, we are done (e.g., String[] elements).
7467 // This self-check enables sharing of secondary supertype arrays among
7468 // non-primary types such as array-of-interface. Otherwise, each such
7469 // type would need its own customized SSA.
7470 // We move this check to the front of the fast path because many
7471 // type checks are in fact trivially successful in this manner,
7472 // so we get a nicely predicted branch right at the start of the check.
7473 cmpptr(sub_klass, super_klass);
7474 local_jcc(Assembler::equal, *L_success);
7475
7476 // Check the supertype display:
7477 if (must_load_sco) {
7478 // Positive movl does right thing on LP64.
7479 movl(temp_reg, super_check_offset_addr);
7480 super_check_offset = RegisterOrConstant(temp_reg);
7481 }
7482 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
7483 cmpptr(super_klass, super_check_addr); // load displayed supertype
7484
7485 // This check has worked decisively for primary supers.
7486 // Secondary supers are sought in the super_cache ('super_cache_addr').
7487 // (Secondary supers are interfaces and very deeply nested subtypes.)
7488 // This works in the same check above because of a tricky aliasing
7489 // between the super_cache and the primary super display elements.
7490 // (The 'super_check_addr' can address either, as the case requires.)
7491 // Note that the cache is updated below if it does not help us find
7492 // what we need immediately.
7493 // So if it was a primary super, we can just fail immediately.
7494 // Otherwise, it's the slow path for us (no success at this point).
7495
7496 if (super_check_offset.is_register()) {
7497 local_jcc(Assembler::equal, *L_success);
7498 cmpl(super_check_offset.as_register(), sc_offset);
7499 if (L_failure == &L_fallthrough) {
7500 local_jcc(Assembler::equal, *L_slow_path);
7501 } else {
7502 local_jcc(Assembler::notEqual, *L_failure);
7503 final_jmp(*L_slow_path);
7504 }
7505 } else if (super_check_offset.as_constant() == sc_offset) {
7506 // Need a slow path; fast failure is impossible.
7507 if (L_slow_path == &L_fallthrough) {
7508 local_jcc(Assembler::equal, *L_success);
7509 } else {
7510 local_jcc(Assembler::notEqual, *L_slow_path);
7511 final_jmp(*L_success);
7512 }
7513 } else {
7514 // No slow path; it's a fast decision.
7515 if (L_failure == &L_fallthrough) {
7516 local_jcc(Assembler::equal, *L_success);
7517 } else {
7518 local_jcc(Assembler::notEqual, *L_failure);
7519 final_jmp(*L_success);
7520 }
7521 }
7522
7523 bind(L_fallthrough);
7524
7525 #undef local_jcc
7526 #undef final_jmp
7527 }
7528
7529
7530 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
7531 Register super_klass,
7532 Register temp_reg,
7533 Register temp2_reg,
7534 Label* L_success,
7535 Label* L_failure,
7536 bool set_cond_codes) {
7537 assert_different_registers(sub_klass, super_klass, temp_reg);
7538 if (temp2_reg != noreg)
7539 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
7540 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
7541
7542 Label L_fallthrough;
7543 int label_nulls = 0;
7544 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7545 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7546 assert(label_nulls <= 1, "at most one NULL in the batch");
7547
7548 // a couple of useful fields in sub_klass:
7549 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
7550 Klass::secondary_supers_offset_in_bytes());
7551 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7552 Klass::secondary_super_cache_offset_in_bytes());
7553 Address secondary_supers_addr(sub_klass, ss_offset);
7554 Address super_cache_addr( sub_klass, sc_offset);
7555
7556 // Do a linear scan of the secondary super-klass chain.
7557 // This code is rarely used, so simplicity is a virtue here.
7558 // The repne_scan instruction uses fixed registers, which we must spill.
7559 // Don't worry too much about pre-existing connections with the input regs.
7560
7561 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
7562 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
7563
7564 // Get super_klass value into rax (even if it was in rdi or rcx).
7565 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
7566 if (super_klass != rax || UseCompressedOops) {
7567 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
7568 mov(rax, super_klass);
7569 }
7570 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
7571 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
7572
7573 #ifndef PRODUCT
7574 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
7575 ExternalAddress pst_counter_addr((address) pst_counter);
7576 NOT_LP64( incrementl(pst_counter_addr) );
7577 LP64_ONLY( lea(rcx, pst_counter_addr) );
7578 LP64_ONLY( incrementl(Address(rcx, 0)) );
7579 #endif //PRODUCT
7580
7581 // We will consult the secondary-super array.
7582 movptr(rdi, secondary_supers_addr);
7583 // Load the array length. (Positive movl does right thing on LP64.)
7584 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
7585 // Skip to start of data.
7586 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7587
7588 // Scan RCX words at [RDI] for an occurrence of RAX.
7589 // Set NZ/Z based on last compare.
7590 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
7591 // not change flags (only scas instruction which is repeated sets flags).
7592 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
7593 #ifdef _LP64
7594 // This part is tricky, as values in supers array could be 32 or 64 bit wide
7595 // and we store values in objArrays always encoded, thus we need to encode
7596 // the value of rax before repne. Note that rax is dead after the repne.
7597 if (UseCompressedOops) {
7598 encode_heap_oop_not_null(rax); // Changes flags.
7599 // The superclass is never null; it would be a basic system error if a null
7600 // pointer were to sneak in here. Note that we have already loaded the
7601 // Klass::super_check_offset from the super_klass in the fast path,
7602 // so if there is a null in that register, we are already in the afterlife.
7603 testl(rax,rax); // Set Z = 0
7604 repne_scanl();
7605 } else
7606 #endif // _LP64
7607 {
7608 testptr(rax,rax); // Set Z = 0
7609 repne_scan();
7610 }
7611 // Unspill the temp. registers:
7612 if (pushed_rdi) pop(rdi);
7613 if (pushed_rcx) pop(rcx);
7614 if (pushed_rax) pop(rax);
7615
7616 if (set_cond_codes) {
7617 // Special hack for the AD files: rdi is guaranteed non-zero.
7618 assert(!pushed_rdi, "rdi must be left non-NULL");
7619 // Also, the condition codes are properly set Z/NZ on succeed/failure.
7620 }
7621
7622 if (L_failure == &L_fallthrough)
7623 jccb(Assembler::notEqual, *L_failure);
7624 else jcc(Assembler::notEqual, *L_failure);
7625
7626 // Success. Cache the super we found and proceed in triumph.
7627 movptr(super_cache_addr, super_klass);
7628
7629 if (L_success != &L_fallthrough) {
7630 jmp(*L_success);
7631 }
7632
7633 #undef IS_A_TEMP
7634
7635 bind(L_fallthrough);
7636 }
7637
7638
7639 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7640 ucomisd(dst, as_Address(src));
7641 }
7642
7643 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7644 ucomiss(dst, as_Address(src));
7645 }
7646
7647 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7648 if (reachable(src)) {
7649 xorpd(dst, as_Address(src));
7650 } else {
7651 lea(rscratch1, src);
7652 xorpd(dst, Address(rscratch1, 0));
7653 }
7654 }
7655
7656 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7657 if (reachable(src)) {
7658 xorps(dst, as_Address(src));
7659 } else {
7660 lea(rscratch1, src);
7661 xorps(dst, Address(rscratch1, 0));
7662 }
7663 }
7664
7665 void MacroAssembler::verify_oop(Register reg, const char* s) {
7666 if (!VerifyOops) return;
7667
7668 // Pass register number to verify_oop_subroutine
7669 char* b = new char[strlen(s) + 50];
7670 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
7671 #ifdef _LP64
7672 push(rscratch1); // save r10, trashed by movptr()
7673 #endif
7674 push(rax); // save rax,
7675 push(reg); // pass register argument
7676 ExternalAddress buffer((address) b);
7677 // avoid using pushptr, as it modifies scratch registers
7678 // and our contract is not to modify anything
7679 movptr(rax, buffer.addr());
7680 push(rax);
7681 // call indirectly to solve generation ordering problem
7682 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7683 call(rax);
7684 // Caller pops the arguments (oop, message) and restores rax, r10
7685 }
7686
7687
7688 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
7689 Register tmp,
7690 int offset) {
7691 intptr_t value = *delayed_value_addr;
7692 if (value != 0)
7693 return RegisterOrConstant(value + offset);
7694
7695 // load indirectly to solve generation ordering problem
7696 movptr(tmp, ExternalAddress((address) delayed_value_addr));
7697
7698 #ifdef ASSERT
7699 { Label L;
7700 testptr(tmp, tmp);
7701 if (WizardMode) {
7702 jcc(Assembler::notZero, L);
7703 char* buf = new char[40];
7704 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
7705 stop(buf);
7706 } else {
7707 jccb(Assembler::notZero, L);
7708 hlt();
7709 }
7710 bind(L);
7711 }
7712 #endif
7713
7714 if (offset != 0)
7715 addptr(tmp, offset);
7716
7717 return RegisterOrConstant(tmp);
7718 }
7719
7720
7721 // registers on entry:
7722 // - rax ('check' register): required MethodType
7723 // - rcx: method handle
7724 // - rdx, rsi, or ?: killable temp
7725 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
7726 Register temp_reg,
7727 Label& wrong_method_type) {
7728 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg));
7729 // compare method type against that of the receiver
7730 if (UseCompressedOops) {
7731 load_heap_oop(temp_reg, type_addr);
7732 cmpptr(mtype_reg, temp_reg);
7733 } else {
7734 cmpptr(mtype_reg, type_addr);
7735 }
7736 jcc(Assembler::notEqual, wrong_method_type);
7737 }
7738
7739
7740 // A method handle has a "vmslots" field which gives the size of its
7741 // argument list in JVM stack slots. This field is either located directly
7742 // in every method handle, or else is indirectly accessed through the
7743 // method handle's MethodType. This macro hides the distinction.
7744 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
7745 Register temp_reg) {
7746 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
7747 // load mh.type.form.vmslots
7748 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) {
7749 // hoist vmslots into every mh to avoid dependent load chain
7750 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)));
7751 } else {
7752 Register temp2_reg = vmslots_reg;
7753 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)));
7754 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)));
7755 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)));
7756 }
7757 }
7758
7759
7760 // registers on entry:
7761 // - rcx: method handle
7762 // - rdx: killable temp (interpreted only)
7763 // - rax: killable temp (compiled only)
7764 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
7765 assert(mh_reg == rcx, "caller must put MH object in rcx");
7766 assert_different_registers(mh_reg, temp_reg);
7767
7768 // pick out the interpreted side of the handler
7769 // NOTE: vmentry is not an oop!
7770 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg)));
7771
7772 // off we go...
7773 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes()));
7774
7775 // for the various stubs which take control at this point,
7776 // see MethodHandles::generate_method_handle_stub
7777 }
7778
7779
7780 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
7781 int extra_slot_offset) {
7782 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
7783 int stackElementSize = Interpreter::stackElementSize;
7784 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
7785 #ifdef ASSERT
7786 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
7787 assert(offset1 - offset == stackElementSize, "correct arithmetic");
7788 #endif
7789 Register scale_reg = noreg;
7790 Address::ScaleFactor scale_factor = Address::no_scale;
7791 if (arg_slot.is_constant()) {
7792 offset += arg_slot.as_constant() * stackElementSize;
7793 } else {
7794 scale_reg = arg_slot.as_register();
7795 scale_factor = Address::times(stackElementSize);
7796 }
7797 offset += wordSize; // return PC is on stack
7798 return Address(rsp, scale_reg, scale_factor, offset);
7799 }
7800
7801
7802 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
7803 if (!VerifyOops) return;
7804
7805 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
7806 // Pass register number to verify_oop_subroutine
7807 char* b = new char[strlen(s) + 50];
7808 sprintf(b, "verify_oop_addr: %s", s);
7809
7810 #ifdef _LP64
7811 push(rscratch1); // save r10, trashed by movptr()
7812 #endif
7813 push(rax); // save rax,
7814 // addr may contain rsp so we will have to adjust it based on the push
7815 // we just did
7816 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
7817 // stores rax into addr which is backwards of what was intended.
7818 if (addr.uses(rsp)) {
7819 lea(rax, addr);
7820 pushptr(Address(rax, BytesPerWord));
7821 } else {
7822 pushptr(addr);
7823 }
7824
7825 ExternalAddress buffer((address) b);
7826 // pass msg argument
7827 // avoid using pushptr, as it modifies scratch registers
7828 // and our contract is not to modify anything
7829 movptr(rax, buffer.addr());
7830 push(rax);
7831
7832 // call indirectly to solve generation ordering problem
7833 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7834 call(rax);
7835 // Caller pops the arguments (addr, message) and restores rax, r10.
7836 }
7837
7838 void MacroAssembler::verify_tlab() {
7839 #ifdef ASSERT
7840 if (UseTLAB && VerifyOops) {
7841 Label next, ok;
7842 Register t1 = rsi;
7843 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
7844
7845 push(t1);
7846 NOT_LP64(push(thread_reg));
7847 NOT_LP64(get_thread(thread_reg));
7848
7849 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7850 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
7851 jcc(Assembler::aboveEqual, next);
7852 stop("assert(top >= start)");
7853 should_not_reach_here();
7854
7855 bind(next);
7856 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7857 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7858 jcc(Assembler::aboveEqual, ok);
7859 stop("assert(top <= end)");
7860 should_not_reach_here();
7861
7862 bind(ok);
7863 NOT_LP64(pop(thread_reg));
7864 pop(t1);
7865 }
7866 #endif
7867 }
7868
7869 class ControlWord {
7870 public:
7871 int32_t _value;
7872
7873 int rounding_control() const { return (_value >> 10) & 3 ; }
7874 int precision_control() const { return (_value >> 8) & 3 ; }
7875 bool precision() const { return ((_value >> 5) & 1) != 0; }
7876 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7877 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7878 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7879 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7880 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7881
7882 void print() const {
7883 // rounding control
7884 const char* rc;
7885 switch (rounding_control()) {
7886 case 0: rc = "round near"; break;
7887 case 1: rc = "round down"; break;
7888 case 2: rc = "round up "; break;
7889 case 3: rc = "chop "; break;
7890 };
7891 // precision control
7892 const char* pc;
7893 switch (precision_control()) {
7894 case 0: pc = "24 bits "; break;
7895 case 1: pc = "reserved"; break;
7896 case 2: pc = "53 bits "; break;
7897 case 3: pc = "64 bits "; break;
7898 };
7899 // flags
7900 char f[9];
7901 f[0] = ' ';
7902 f[1] = ' ';
7903 f[2] = (precision ()) ? 'P' : 'p';
7904 f[3] = (underflow ()) ? 'U' : 'u';
7905 f[4] = (overflow ()) ? 'O' : 'o';
7906 f[5] = (zero_divide ()) ? 'Z' : 'z';
7907 f[6] = (denormalized()) ? 'D' : 'd';
7908 f[7] = (invalid ()) ? 'I' : 'i';
7909 f[8] = '\x0';
7910 // output
7911 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
7912 }
7913
7914 };
7915
7916 class StatusWord {
7917 public:
7918 int32_t _value;
7919
7920 bool busy() const { return ((_value >> 15) & 1) != 0; }
7921 bool C3() const { return ((_value >> 14) & 1) != 0; }
7922 bool C2() const { return ((_value >> 10) & 1) != 0; }
7923 bool C1() const { return ((_value >> 9) & 1) != 0; }
7924 bool C0() const { return ((_value >> 8) & 1) != 0; }
7925 int top() const { return (_value >> 11) & 7 ; }
7926 bool error_status() const { return ((_value >> 7) & 1) != 0; }
7927 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
7928 bool precision() const { return ((_value >> 5) & 1) != 0; }
7929 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7930 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7931 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7932 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7933 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7934
7935 void print() const {
7936 // condition codes
7937 char c[5];
7938 c[0] = (C3()) ? '3' : '-';
7939 c[1] = (C2()) ? '2' : '-';
7940 c[2] = (C1()) ? '1' : '-';
7941 c[3] = (C0()) ? '0' : '-';
7942 c[4] = '\x0';
7943 // flags
7944 char f[9];
7945 f[0] = (error_status()) ? 'E' : '-';
7946 f[1] = (stack_fault ()) ? 'S' : '-';
7947 f[2] = (precision ()) ? 'P' : '-';
7948 f[3] = (underflow ()) ? 'U' : '-';
7949 f[4] = (overflow ()) ? 'O' : '-';
7950 f[5] = (zero_divide ()) ? 'Z' : '-';
7951 f[6] = (denormalized()) ? 'D' : '-';
7952 f[7] = (invalid ()) ? 'I' : '-';
7953 f[8] = '\x0';
7954 // output
7955 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
7956 }
7957
7958 };
7959
7960 class TagWord {
7961 public:
7962 int32_t _value;
7963
7964 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
7965
7966 void print() const {
7967 printf("%04x", _value & 0xFFFF);
7968 }
7969
7970 };
7971
7972 class FPU_Register {
7973 public:
7974 int32_t _m0;
7975 int32_t _m1;
7976 int16_t _ex;
7977
7978 bool is_indefinite() const {
7979 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
7980 }
7981
7982 void print() const {
7983 char sign = (_ex < 0) ? '-' : '+';
7984 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
7985 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
7986 };
7987
7988 };
7989
7990 class FPU_State {
7991 public:
7992 enum {
7993 register_size = 10,
7994 number_of_registers = 8,
7995 register_mask = 7
7996 };
7997
7998 ControlWord _control_word;
7999 StatusWord _status_word;
8000 TagWord _tag_word;
8001 int32_t _error_offset;
8002 int32_t _error_selector;
8003 int32_t _data_offset;
8004 int32_t _data_selector;
8005 int8_t _register[register_size * number_of_registers];
8006
8007 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
8008 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
8009
8010 const char* tag_as_string(int tag) const {
8011 switch (tag) {
8012 case 0: return "valid";
8013 case 1: return "zero";
8014 case 2: return "special";
8015 case 3: return "empty";
8016 }
8017 ShouldNotReachHere();
8018 return NULL;
8019 }
8020
8021 void print() const {
8022 // print computation registers
8023 { int t = _status_word.top();
8024 for (int i = 0; i < number_of_registers; i++) {
8025 int j = (i - t) & register_mask;
8026 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
8027 st(j)->print();
8028 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
8029 }
8030 }
8031 printf("\n");
8032 // print control registers
8033 printf("ctrl = "); _control_word.print(); printf("\n");
8034 printf("stat = "); _status_word .print(); printf("\n");
8035 printf("tags = "); _tag_word .print(); printf("\n");
8036 }
8037
8038 };
8039
8040 class Flag_Register {
8041 public:
8042 int32_t _value;
8043
8044 bool overflow() const { return ((_value >> 11) & 1) != 0; }
8045 bool direction() const { return ((_value >> 10) & 1) != 0; }
8046 bool sign() const { return ((_value >> 7) & 1) != 0; }
8047 bool zero() const { return ((_value >> 6) & 1) != 0; }
8048 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
8049 bool parity() const { return ((_value >> 2) & 1) != 0; }
8050 bool carry() const { return ((_value >> 0) & 1) != 0; }
8051
8052 void print() const {
8053 // flags
8054 char f[8];
8055 f[0] = (overflow ()) ? 'O' : '-';
8056 f[1] = (direction ()) ? 'D' : '-';
8057 f[2] = (sign ()) ? 'S' : '-';
8058 f[3] = (zero ()) ? 'Z' : '-';
8059 f[4] = (auxiliary_carry()) ? 'A' : '-';
8060 f[5] = (parity ()) ? 'P' : '-';
8061 f[6] = (carry ()) ? 'C' : '-';
8062 f[7] = '\x0';
8063 // output
8064 printf("%08x flags = %s", _value, f);
8065 }
8066
8067 };
8068
8069 class IU_Register {
8070 public:
8071 int32_t _value;
8072
8073 void print() const {
8074 printf("%08x %11d", _value, _value);
8075 }
8076
8077 };
8078
8079 class IU_State {
8080 public:
8081 Flag_Register _eflags;
8082 IU_Register _rdi;
8083 IU_Register _rsi;
8084 IU_Register _rbp;
8085 IU_Register _rsp;
8086 IU_Register _rbx;
8087 IU_Register _rdx;
8088 IU_Register _rcx;
8089 IU_Register _rax;
8090
8091 void print() const {
8092 // computation registers
8093 printf("rax, = "); _rax.print(); printf("\n");
8094 printf("rbx, = "); _rbx.print(); printf("\n");
8095 printf("rcx = "); _rcx.print(); printf("\n");
8096 printf("rdx = "); _rdx.print(); printf("\n");
8097 printf("rdi = "); _rdi.print(); printf("\n");
8098 printf("rsi = "); _rsi.print(); printf("\n");
8099 printf("rbp, = "); _rbp.print(); printf("\n");
8100 printf("rsp = "); _rsp.print(); printf("\n");
8101 printf("\n");
8102 // control registers
8103 printf("flgs = "); _eflags.print(); printf("\n");
8104 }
8105 };
8106
8107
8108 class CPU_State {
8109 public:
8110 FPU_State _fpu_state;
8111 IU_State _iu_state;
8112
8113 void print() const {
8114 printf("--------------------------------------------------\n");
8115 _iu_state .print();
8116 printf("\n");
8117 _fpu_state.print();
8118 printf("--------------------------------------------------\n");
8119 }
8120
8121 };
8122
8123
8124 static void _print_CPU_state(CPU_State* state) {
8125 state->print();
8126 };
8127
8128
8129 void MacroAssembler::print_CPU_state() {
8130 push_CPU_state();
8131 push(rsp); // pass CPU state
8132 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
8133 addptr(rsp, wordSize); // discard argument
8134 pop_CPU_state();
8135 }
8136
8137
8138 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
8139 static int counter = 0;
8140 FPU_State* fs = &state->_fpu_state;
8141 counter++;
8142 // For leaf calls, only verify that the top few elements remain empty.
8143 // We only need 1 empty at the top for C2 code.
8144 if( stack_depth < 0 ) {
8145 if( fs->tag_for_st(7) != 3 ) {
8146 printf("FPR7 not empty\n");
8147 state->print();
8148 assert(false, "error");
8149 return false;
8150 }
8151 return true; // All other stack states do not matter
8152 }
8153
8154 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
8155 "bad FPU control word");
8156
8157 // compute stack depth
8158 int i = 0;
8159 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
8160 int d = i;
8161 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
8162 // verify findings
8163 if (i != FPU_State::number_of_registers) {
8164 // stack not contiguous
8165 printf("%s: stack not contiguous at ST%d\n", s, i);
8166 state->print();
8167 assert(false, "error");
8168 return false;
8169 }
8170 // check if computed stack depth corresponds to expected stack depth
8171 if (stack_depth < 0) {
8172 // expected stack depth is -stack_depth or less
8173 if (d > -stack_depth) {
8174 // too many elements on the stack
8175 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
8176 state->print();
8177 assert(false, "error");
8178 return false;
8179 }
8180 } else {
8181 // expected stack depth is stack_depth
8182 if (d != stack_depth) {
8183 // wrong stack depth
8184 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
8185 state->print();
8186 assert(false, "error");
8187 return false;
8188 }
8189 }
8190 // everything is cool
8191 return true;
8192 }
8193
8194
8195 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
8196 if (!VerifyFPU) return;
8197 push_CPU_state();
8198 push(rsp); // pass CPU state
8199 ExternalAddress msg((address) s);
8200 // pass message string s
8201 pushptr(msg.addr());
8202 push(stack_depth); // pass stack depth
8203 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
8204 addptr(rsp, 3 * wordSize); // discard arguments
8205 // check for error
8206 { Label L;
8207 testl(rax, rax);
8208 jcc(Assembler::notZero, L);
8209 int3(); // break if error condition
8210 bind(L);
8211 }
8212 pop_CPU_state();
8213 }
8214
8215 void MacroAssembler::load_klass(Register dst, Register src) {
8216 #ifdef _LP64
8217 if (UseCompressedOops) {
8218 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8219 decode_heap_oop_not_null(dst);
8220 } else
8221 #endif
8222 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8223 }
8224
8225 void MacroAssembler::load_prototype_header(Register dst, Register src) {
8226 #ifdef _LP64
8227 if (UseCompressedOops) {
8228 assert (Universe::heap() != NULL, "java heap should be initialized");
8229 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8230 if (Universe::narrow_oop_shift() != 0) {
8231 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8232 if (LogMinObjAlignmentInBytes == Address::times_8) {
8233 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8234 } else {
8235 // OK to use shift since we don't need to preserve flags.
8236 shlq(dst, LogMinObjAlignmentInBytes);
8237 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8238 }
8239 } else {
8240 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8241 }
8242 } else
8243 #endif
8244 {
8245 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8246 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8247 }
8248 }
8249
8250 void MacroAssembler::store_klass(Register dst, Register src) {
8251 #ifdef _LP64
8252 if (UseCompressedOops) {
8253 encode_heap_oop_not_null(src);
8254 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8255 } else
8256 #endif
8257 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8258 }
8259
8260 void MacroAssembler::load_heap_oop(Register dst, Address src) {
8261 #ifdef _LP64
8262 if (UseCompressedOops) {
8263 movl(dst, src);
8264 decode_heap_oop(dst);
8265 } else
8266 #endif
8267 movptr(dst, src);
8268 }
8269
8270 void MacroAssembler::store_heap_oop(Address dst, Register src) {
8271 #ifdef _LP64
8272 if (UseCompressedOops) {
8273 assert(!dst.uses(src), "not enough registers");
8274 encode_heap_oop(src);
8275 movl(dst, src);
8276 } else
8277 #endif
8278 movptr(dst, src);
8279 }
8280
8281 // Used for storing NULLs.
8282 void MacroAssembler::store_heap_oop_null(Address dst) {
8283 #ifdef _LP64
8284 if (UseCompressedOops) {
8285 movl(dst, (int32_t)NULL_WORD);
8286 } else {
8287 movslq(dst, (int32_t)NULL_WORD);
8288 }
8289 #else
8290 movl(dst, (int32_t)NULL_WORD);
8291 #endif
8292 }
8293
8294 #ifdef _LP64
8295 void MacroAssembler::store_klass_gap(Register dst, Register src) {
8296 if (UseCompressedOops) {
8297 // Store to klass gap in destination
8298 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
8299 }
8300 }
8301
8302 #ifdef ASSERT
8303 void MacroAssembler::verify_heapbase(const char* msg) {
8304 assert (UseCompressedOops, "should be compressed");
8305 assert (Universe::heap() != NULL, "java heap should be initialized");
8306 if (CheckCompressedOops) {
8307 Label ok;
8308 push(rscratch1); // cmpptr trashes rscratch1
8309 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8310 jcc(Assembler::equal, ok);
8311 stop(msg);
8312 bind(ok);
8313 pop(rscratch1);
8314 }
8315 }
8316 #endif
8317
8318 // Algorithm must match oop.inline.hpp encode_heap_oop.
8319 void MacroAssembler::encode_heap_oop(Register r) {
8320 #ifdef ASSERT
8321 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
8322 #endif
8323 verify_oop(r, "broken oop in encode_heap_oop");
8324 if (Universe::narrow_oop_base() == NULL) {
8325 if (Universe::narrow_oop_shift() != 0) {
8326 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8327 shrq(r, LogMinObjAlignmentInBytes);
8328 }
8329 return;
8330 }
8331 testq(r, r);
8332 cmovq(Assembler::equal, r, r12_heapbase);
8333 subq(r, r12_heapbase);
8334 shrq(r, LogMinObjAlignmentInBytes);
8335 }
8336
8337 void MacroAssembler::encode_heap_oop_not_null(Register r) {
8338 #ifdef ASSERT
8339 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
8340 if (CheckCompressedOops) {
8341 Label ok;
8342 testq(r, r);
8343 jcc(Assembler::notEqual, ok);
8344 stop("null oop passed to encode_heap_oop_not_null");
8345 bind(ok);
8346 }
8347 #endif
8348 verify_oop(r, "broken oop in encode_heap_oop_not_null");
8349 if (Universe::narrow_oop_base() != NULL) {
8350 subq(r, r12_heapbase);
8351 }
8352 if (Universe::narrow_oop_shift() != 0) {
8353 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8354 shrq(r, LogMinObjAlignmentInBytes);
8355 }
8356 }
8357
8358 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
8359 #ifdef ASSERT
8360 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
8361 if (CheckCompressedOops) {
8362 Label ok;
8363 testq(src, src);
8364 jcc(Assembler::notEqual, ok);
8365 stop("null oop passed to encode_heap_oop_not_null2");
8366 bind(ok);
8367 }
8368 #endif
8369 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
8370 if (dst != src) {
8371 movq(dst, src);
8372 }
8373 if (Universe::narrow_oop_base() != NULL) {
8374 subq(dst, r12_heapbase);
8375 }
8376 if (Universe::narrow_oop_shift() != 0) {
8377 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8378 shrq(dst, LogMinObjAlignmentInBytes);
8379 }
8380 }
8381
8382 void MacroAssembler::decode_heap_oop(Register r) {
8383 #ifdef ASSERT
8384 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
8385 #endif
8386 if (Universe::narrow_oop_base() == NULL) {
8387 if (Universe::narrow_oop_shift() != 0) {
8388 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8389 shlq(r, LogMinObjAlignmentInBytes);
8390 }
8391 } else {
8392 Label done;
8393 shlq(r, LogMinObjAlignmentInBytes);
8394 jccb(Assembler::equal, done);
8395 addq(r, r12_heapbase);
8396 bind(done);
8397 }
8398 verify_oop(r, "broken oop in decode_heap_oop");
8399 }
8400
8401 void MacroAssembler::decode_heap_oop_not_null(Register r) {
8402 // Note: it will change flags
8403 assert (UseCompressedOops, "should only be used for compressed headers");
8404 assert (Universe::heap() != NULL, "java heap should be initialized");
8405 // Cannot assert, unverified entry point counts instructions (see .ad file)
8406 // vtableStubs also counts instructions in pd_code_size_limit.
8407 // Also do not verify_oop as this is called by verify_oop.
8408 if (Universe::narrow_oop_shift() != 0) {
8409 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8410 shlq(r, LogMinObjAlignmentInBytes);
8411 if (Universe::narrow_oop_base() != NULL) {
8412 addq(r, r12_heapbase);
8413 }
8414 } else {
8415 assert (Universe::narrow_oop_base() == NULL, "sanity");
8416 }
8417 }
8418
8419 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
8420 // Note: it will change flags
8421 assert (UseCompressedOops, "should only be used for compressed headers");
8422 assert (Universe::heap() != NULL, "java heap should be initialized");
8423 // Cannot assert, unverified entry point counts instructions (see .ad file)
8424 // vtableStubs also counts instructions in pd_code_size_limit.
8425 // Also do not verify_oop as this is called by verify_oop.
8426 if (Universe::narrow_oop_shift() != 0) {
8427 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8428 if (LogMinObjAlignmentInBytes == Address::times_8) {
8429 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
8430 } else {
8431 if (dst != src) {
8432 movq(dst, src);
8433 }
8434 shlq(dst, LogMinObjAlignmentInBytes);
8435 if (Universe::narrow_oop_base() != NULL) {
8436 addq(dst, r12_heapbase);
8437 }
8438 }
8439 } else {
8440 assert (Universe::narrow_oop_base() == NULL, "sanity");
8441 if (dst != src) {
8442 movq(dst, src);
8443 }
8444 }
8445 }
8446
8447 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
8448 assert (UseCompressedOops, "should only be used for compressed headers");
8449 assert (Universe::heap() != NULL, "java heap should be initialized");
8450 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8451 int oop_index = oop_recorder()->find_index(obj);
8452 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8453 mov_narrow_oop(dst, oop_index, rspec);
8454 }
8455
8456 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
8457 assert (UseCompressedOops, "should only be used for compressed headers");
8458 assert (Universe::heap() != NULL, "java heap should be initialized");
8459 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8460 int oop_index = oop_recorder()->find_index(obj);
8461 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8462 mov_narrow_oop(dst, oop_index, rspec);
8463 }
8464
8465 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
8466 assert (UseCompressedOops, "should only be used for compressed headers");
8467 assert (Universe::heap() != NULL, "java heap should be initialized");
8468 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8469 int oop_index = oop_recorder()->find_index(obj);
8470 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8471 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8472 }
8473
8474 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
8475 assert (UseCompressedOops, "should only be used for compressed headers");
8476 assert (Universe::heap() != NULL, "java heap should be initialized");
8477 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8478 int oop_index = oop_recorder()->find_index(obj);
8479 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8480 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8481 }
8482
8483 void MacroAssembler::reinit_heapbase() {
8484 if (UseCompressedOops) {
8485 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8486 }
8487 }
8488 #endif // _LP64
8489
8490 // IndexOf substring.
8491 void MacroAssembler::string_indexof(Register str1, Register str2,
8492 Register cnt1, Register cnt2, Register result,
8493 XMMRegister vec, Register tmp) {
8494 assert(UseSSE42Intrinsics, "SSE4.2 is required");
8495
8496 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
8497 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP;
8498
8499 push(str1); // string addr
8500 push(str2); // substr addr
8501 push(cnt2); // substr count
8502 jmpb(PREP_FOR_SCAN);
8503
8504 // Substr count saved at sp
8505 // Substr saved at sp+1*wordSize
8506 // String saved at sp+2*wordSize
8507
8508 // Reload substr for rescan
8509 bind(RELOAD_SUBSTR);
8510 movl(cnt2, Address(rsp, 0));
8511 movptr(str2, Address(rsp, wordSize));
8512 // We came here after the beginninig of the substring was
8513 // matched but the rest of it was not so we need to search
8514 // again. Start from the next element after the previous match.
8515 subptr(str1, result); // Restore counter
8516 shrl(str1, 1);
8517 addl(cnt1, str1);
8518 decrementl(cnt1);
8519 lea(str1, Address(result, 2)); // Reload string
8520
8521 // Load substr
8522 bind(PREP_FOR_SCAN);
8523 movdqu(vec, Address(str2, 0));
8524 addl(cnt1, 8); // prime the loop
8525 subptr(str1, 16);
8526
8527 // Scan string for substr in 16-byte vectors
8528 bind(SCAN_TO_SUBSTR);
8529 subl(cnt1, 8);
8530 addptr(str1, 16);
8531
8532 // pcmpestri
8533 // inputs:
8534 // xmm - substring
8535 // rax - substring length (elements count)
8536 // mem - scaned string
8537 // rdx - string length (elements count)
8538 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
8539 // outputs:
8540 // rcx - matched index in string
8541 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
8542
8543 pcmpestri(vec, Address(str1, 0), 0x0d);
8544 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
8545 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
8546
8547 // Fallthrough: found a potential substr
8548
8549 // Make sure string is still long enough
8550 subl(cnt1, tmp);
8551 cmpl(cnt1, cnt2);
8552 jccb(Assembler::negative, RET_NOT_FOUND);
8553 // Compute start addr of substr
8554 lea(str1, Address(str1, tmp, Address::times_2));
8555 movptr(result, str1); // save
8556
8557 // Compare potential substr
8558 addl(cnt1, 8); // prime the loop
8559 addl(cnt2, 8);
8560 subptr(str1, 16);
8561 subptr(str2, 16);
8562
8563 // Scan 16-byte vectors of string and substr
8564 bind(SCAN_SUBSTR);
8565 subl(cnt1, 8);
8566 subl(cnt2, 8);
8567 addptr(str1, 16);
8568 addptr(str2, 16);
8569 movdqu(vec, Address(str2, 0));
8570 pcmpestri(vec, Address(str1, 0), 0x0d);
8571 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
8572 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
8573
8574 // Compute substr offset
8575 subptr(result, Address(rsp, 2*wordSize));
8576 shrl(result, 1); // index
8577 jmpb(CLEANUP);
8578
8579 bind(RET_NOT_FOUND);
8580 movl(result, -1);
8581
8582 bind(CLEANUP);
8583 addptr(rsp, 3*wordSize);
8584 }
8585
8586 // Compare strings.
8587 void MacroAssembler::string_compare(Register str1, Register str2,
8588 Register cnt1, Register cnt2, Register result,
8589 XMMRegister vec1, XMMRegister vec2) {
8590 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
8591
8592 // Compute the minimum of the string lengths and the
8593 // difference of the string lengths (stack).
8594 // Do the conditional move stuff
8595 movl(result, cnt1);
8596 subl(cnt1, cnt2);
8597 push(cnt1);
8598 if (VM_Version::supports_cmov()) {
8599 cmovl(Assembler::lessEqual, cnt2, result);
8600 } else {
8601 Label GT_LABEL;
8602 jccb(Assembler::greater, GT_LABEL);
8603 movl(cnt2, result);
8604 bind(GT_LABEL);
8605 }
8606
8607 // Is the minimum length zero?
8608 testl(cnt2, cnt2);
8609 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8610
8611 // Load first characters
8612 load_unsigned_short(result, Address(str1, 0));
8613 load_unsigned_short(cnt1, Address(str2, 0));
8614
8615 // Compare first characters
8616 subl(result, cnt1);
8617 jcc(Assembler::notZero, POP_LABEL);
8618 decrementl(cnt2);
8619 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8620
8621 {
8622 // Check after comparing first character to see if strings are equivalent
8623 Label LSkip2;
8624 // Check if the strings start at same location
8625 cmpptr(str1, str2);
8626 jccb(Assembler::notEqual, LSkip2);
8627
8628 // Check if the length difference is zero (from stack)
8629 cmpl(Address(rsp, 0), 0x0);
8630 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
8631
8632 // Strings might not be equivalent
8633 bind(LSkip2);
8634 }
8635
8636 // Advance to next character
8637 addptr(str1, 2);
8638 addptr(str2, 2);
8639
8640 if (UseSSE42Intrinsics) {
8641 // With SSE4.2, use double quad vector compare
8642 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8643 // Setup to compare 16-byte vectors
8644 movl(cnt1, cnt2);
8645 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count
8646 andl(cnt1, 0x00000007); // cnt1 holds the tail count
8647 testl(cnt2, cnt2);
8648 jccb(Assembler::zero, COMPARE_TAIL);
8649
8650 lea(str2, Address(str2, cnt2, Address::times_2));
8651 lea(str1, Address(str1, cnt2, Address::times_2));
8652 negptr(cnt2);
8653
8654 bind(COMPARE_VECTORS);
8655 movdqu(vec1, Address(str1, cnt2, Address::times_2));
8656 movdqu(vec2, Address(str2, cnt2, Address::times_2));
8657 pxor(vec1, vec2);
8658 ptest(vec1, vec1);
8659 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
8660 addptr(cnt2, 8);
8661 jcc(Assembler::notZero, COMPARE_VECTORS);
8662 jmpb(COMPARE_TAIL);
8663
8664 // Mismatched characters in the vectors
8665 bind(VECTOR_NOT_EQUAL);
8666 lea(str1, Address(str1, cnt2, Address::times_2));
8667 lea(str2, Address(str2, cnt2, Address::times_2));
8668 movl(cnt1, 8);
8669
8670 // Compare tail (< 8 chars), or rescan last vectors to
8671 // find 1st mismatched characters
8672 bind(COMPARE_TAIL);
8673 testl(cnt1, cnt1);
8674 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8675 movl(cnt2, cnt1);
8676 // Fallthru to tail compare
8677 }
8678
8679 // Shift str2 and str1 to the end of the arrays, negate min
8680 lea(str1, Address(str1, cnt2, Address::times_2, 0));
8681 lea(str2, Address(str2, cnt2, Address::times_2, 0));
8682 negptr(cnt2);
8683
8684 // Compare the rest of the characters
8685 bind(WHILE_HEAD_LABEL);
8686 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0));
8687 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0));
8688 subl(result, cnt1);
8689 jccb(Assembler::notZero, POP_LABEL);
8690 increment(cnt2);
8691 jcc(Assembler::notZero, WHILE_HEAD_LABEL);
8692
8693 // Strings are equal up to min length. Return the length difference.
8694 bind(LENGTH_DIFF_LABEL);
8695 pop(result);
8696 jmpb(DONE_LABEL);
8697
8698 // Discard the stored length difference
8699 bind(POP_LABEL);
8700 addptr(rsp, wordSize);
8701
8702 // That's it
8703 bind(DONE_LABEL);
8704 }
8705
8706 // Compare char[] arrays aligned to 4 bytes or substrings.
8707 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8708 Register limit, Register result, Register chr,
8709 XMMRegister vec1, XMMRegister vec2) {
8710 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
8711
8712 int length_offset = arrayOopDesc::length_offset_in_bytes();
8713 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
8714
8715 // Check the input args
8716 cmpptr(ary1, ary2);
8717 jcc(Assembler::equal, TRUE_LABEL);
8718
8719 if (is_array_equ) {
8720 // Need additional checks for arrays_equals.
8721 testptr(ary1, ary1);
8722 jcc(Assembler::zero, FALSE_LABEL);
8723 testptr(ary2, ary2);
8724 jcc(Assembler::zero, FALSE_LABEL);
8725
8726 // Check the lengths
8727 movl(limit, Address(ary1, length_offset));
8728 cmpl(limit, Address(ary2, length_offset));
8729 jcc(Assembler::notEqual, FALSE_LABEL);
8730 }
8731
8732 // count == 0
8733 testl(limit, limit);
8734 jcc(Assembler::zero, TRUE_LABEL);
8735
8736 if (is_array_equ) {
8737 // Load array address
8738 lea(ary1, Address(ary1, base_offset));
8739 lea(ary2, Address(ary2, base_offset));
8740 }
8741
8742 shll(limit, 1); // byte count != 0
8743 movl(result, limit); // copy
8744
8745 if (UseSSE42Intrinsics) {
8746 // With SSE4.2, use double quad vector compare
8747 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8748 // Compare 16-byte vectors
8749 andl(result, 0x0000000e); // tail count (in bytes)
8750 andl(limit, 0xfffffff0); // vector count (in bytes)
8751 jccb(Assembler::zero, COMPARE_TAIL);
8752
8753 lea(ary1, Address(ary1, limit, Address::times_1));
8754 lea(ary2, Address(ary2, limit, Address::times_1));
8755 negptr(limit);
8756
8757 bind(COMPARE_WIDE_VECTORS);
8758 movdqu(vec1, Address(ary1, limit, Address::times_1));
8759 movdqu(vec2, Address(ary2, limit, Address::times_1));
8760 pxor(vec1, vec2);
8761 ptest(vec1, vec1);
8762 jccb(Assembler::notZero, FALSE_LABEL);
8763 addptr(limit, 16);
8764 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8765
8766 bind(COMPARE_TAIL); // limit is zero
8767 movl(limit, result);
8768 // Fallthru to tail compare
8769 }
8770
8771 // Compare 4-byte vectors
8772 andl(limit, 0xfffffffc); // vector count (in bytes)
8773 jccb(Assembler::zero, COMPARE_CHAR);
8774
8775 lea(ary1, Address(ary1, limit, Address::times_1));
8776 lea(ary2, Address(ary2, limit, Address::times_1));
8777 negptr(limit);
8778
8779 bind(COMPARE_VECTORS);
8780 movl(chr, Address(ary1, limit, Address::times_1));
8781 cmpl(chr, Address(ary2, limit, Address::times_1));
8782 jccb(Assembler::notEqual, FALSE_LABEL);
8783 addptr(limit, 4);
8784 jcc(Assembler::notZero, COMPARE_VECTORS);
8785
8786 // Compare trailing char (final 2 bytes), if any
8787 bind(COMPARE_CHAR);
8788 testl(result, 0x2); // tail char
8789 jccb(Assembler::zero, TRUE_LABEL);
8790 load_unsigned_short(chr, Address(ary1, 0));
8791 load_unsigned_short(limit, Address(ary2, 0));
8792 cmpl(chr, limit);
8793 jccb(Assembler::notEqual, FALSE_LABEL);
8794
8795 bind(TRUE_LABEL);
8796 movl(result, 1); // return true
8797 jmpb(DONE);
8798
8799 bind(FALSE_LABEL);
8800 xorl(result, result); // return false
8801
8802 // That's it
8803 bind(DONE);
8804 }
8805
8806 #ifdef PRODUCT
8807 #define BLOCK_COMMENT(str) /* nothing */
8808 #else
8809 #define BLOCK_COMMENT(str) block_comment(str)
8810 #endif
8811
8812 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
8813 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8814 Register to, Register value, Register count,
8815 Register rtmp, XMMRegister xtmp) {
8816 assert_different_registers(to, value, count, rtmp);
8817 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8818 Label L_fill_2_bytes, L_fill_4_bytes;
8819
8820 int shift = -1;
8821 switch (t) {
8822 case T_BYTE:
8823 shift = 2;
8824 break;
8825 case T_SHORT:
8826 shift = 1;
8827 break;
8828 case T_INT:
8829 shift = 0;
8830 break;
8831 default: ShouldNotReachHere();
8832 }
8833
8834 if (t == T_BYTE) {
8835 andl(value, 0xff);
8836 movl(rtmp, value);
8837 shll(rtmp, 8);
8838 orl(value, rtmp);
8839 }
8840 if (t == T_SHORT) {
8841 andl(value, 0xffff);
8842 }
8843 if (t == T_BYTE || t == T_SHORT) {
8844 movl(rtmp, value);
8845 shll(rtmp, 16);
8846 orl(value, rtmp);
8847 }
8848
8849 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8850 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8851 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8852 // align source address at 4 bytes address boundary
8853 if (t == T_BYTE) {
8854 // One byte misalignment happens only for byte arrays
8855 testptr(to, 1);
8856 jccb(Assembler::zero, L_skip_align1);
8857 movb(Address(to, 0), value);
8858 increment(to);
8859 decrement(count);
8860 BIND(L_skip_align1);
8861 }
8862 // Two bytes misalignment happens only for byte and short (char) arrays
8863 testptr(to, 2);
8864 jccb(Assembler::zero, L_skip_align2);
8865 movw(Address(to, 0), value);
8866 addptr(to, 2);
8867 subl(count, 1<<(shift-1));
8868 BIND(L_skip_align2);
8869 }
8870 if (UseSSE < 2) {
8871 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8872 // Fill 32-byte chunks
8873 subl(count, 8 << shift);
8874 jcc(Assembler::less, L_check_fill_8_bytes);
8875 align(16);
8876
8877 BIND(L_fill_32_bytes_loop);
8878
8879 for (int i = 0; i < 32; i += 4) {
8880 movl(Address(to, i), value);
8881 }
8882
8883 addptr(to, 32);
8884 subl(count, 8 << shift);
8885 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8886 BIND(L_check_fill_8_bytes);
8887 addl(count, 8 << shift);
8888 jccb(Assembler::zero, L_exit);
8889 jmpb(L_fill_8_bytes);
8890
8891 //
8892 // length is too short, just fill qwords
8893 //
8894 BIND(L_fill_8_bytes_loop);
8895 movl(Address(to, 0), value);
8896 movl(Address(to, 4), value);
8897 addptr(to, 8);
8898 BIND(L_fill_8_bytes);
8899 subl(count, 1 << (shift + 1));
8900 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8901 // fall through to fill 4 bytes
8902 } else {
8903 Label L_fill_32_bytes;
8904 if (!UseUnalignedLoadStores) {
8905 // align to 8 bytes, we know we are 4 byte aligned to start
8906 testptr(to, 4);
8907 jccb(Assembler::zero, L_fill_32_bytes);
8908 movl(Address(to, 0), value);
8909 addptr(to, 4);
8910 subl(count, 1<<shift);
8911 }
8912 BIND(L_fill_32_bytes);
8913 {
8914 assert( UseSSE >= 2, "supported cpu only" );
8915 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8916 // Fill 32-byte chunks
8917 movdl(xtmp, value);
8918 pshufd(xtmp, xtmp, 0);
8919
8920 subl(count, 8 << shift);
8921 jcc(Assembler::less, L_check_fill_8_bytes);
8922 align(16);
8923
8924 BIND(L_fill_32_bytes_loop);
8925
8926 if (UseUnalignedLoadStores) {
8927 movdqu(Address(to, 0), xtmp);
8928 movdqu(Address(to, 16), xtmp);
8929 } else {
8930 movq(Address(to, 0), xtmp);
8931 movq(Address(to, 8), xtmp);
8932 movq(Address(to, 16), xtmp);
8933 movq(Address(to, 24), xtmp);
8934 }
8935
8936 addptr(to, 32);
8937 subl(count, 8 << shift);
8938 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8939 BIND(L_check_fill_8_bytes);
8940 addl(count, 8 << shift);
8941 jccb(Assembler::zero, L_exit);
8942 jmpb(L_fill_8_bytes);
8943
8944 //
8945 // length is too short, just fill qwords
8946 //
8947 BIND(L_fill_8_bytes_loop);
8948 movq(Address(to, 0), xtmp);
8949 addptr(to, 8);
8950 BIND(L_fill_8_bytes);
8951 subl(count, 1 << (shift + 1));
8952 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8953 }
8954 }
8955 // fill trailing 4 bytes
8956 BIND(L_fill_4_bytes);
8957 testl(count, 1<<shift);
8958 jccb(Assembler::zero, L_fill_2_bytes);
8959 movl(Address(to, 0), value);
8960 if (t == T_BYTE || t == T_SHORT) {
8961 addptr(to, 4);
8962 BIND(L_fill_2_bytes);
8963 // fill trailing 2 bytes
8964 testl(count, 1<<(shift-1));
8965 jccb(Assembler::zero, L_fill_byte);
8966 movw(Address(to, 0), value);
8967 if (t == T_BYTE) {
8968 addptr(to, 2);
8969 BIND(L_fill_byte);
8970 // fill trailing byte
8971 testl(count, 1);
8972 jccb(Assembler::zero, L_exit);
8973 movb(Address(to, 0), value);
8974 } else {
8975 BIND(L_fill_byte);
8976 }
8977 } else {
8978 BIND(L_fill_2_bytes);
8979 }
8980 BIND(L_exit);
8981 }
8982 #undef BIND
8983 #undef BLOCK_COMMENT
8984
8985
8986 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8987 switch (cond) {
8988 // Note some conditions are synonyms for others
8989 case Assembler::zero: return Assembler::notZero;
8990 case Assembler::notZero: return Assembler::zero;
8991 case Assembler::less: return Assembler::greaterEqual;
8992 case Assembler::lessEqual: return Assembler::greater;
8993 case Assembler::greater: return Assembler::lessEqual;
8994 case Assembler::greaterEqual: return Assembler::less;
8995 case Assembler::below: return Assembler::aboveEqual;
8996 case Assembler::belowEqual: return Assembler::above;
8997 case Assembler::above: return Assembler::belowEqual;
8998 case Assembler::aboveEqual: return Assembler::below;
8999 case Assembler::overflow: return Assembler::noOverflow;
9000 case Assembler::noOverflow: return Assembler::overflow;
9001 case Assembler::negative: return Assembler::positive;
9002 case Assembler::positive: return Assembler::negative;
9003 case Assembler::parity: return Assembler::noParity;
9004 case Assembler::noParity: return Assembler::parity;
9005 }
9006 ShouldNotReachHere(); return Assembler::overflow;
9007 }
9008
9009 SkipIfEqual::SkipIfEqual(
9010 MacroAssembler* masm, const bool* flag_addr, bool value) {
9011 _masm = masm;
9012 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9013 _masm->jcc(Assembler::equal, _label);
9014 }
9015
9016 SkipIfEqual::~SkipIfEqual() {
9017 _masm->bind(_label);
9018 }