1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 class BiasedLockingCounters;
29
30 // Contains all the definitions needed for x86 assembly code generation.
31
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
51
52
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
56
57 #ifdef _WIN64
58
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
63
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
68
69 #else
70
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
77
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
86
87 #endif // _WIN64
88
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
104
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
117
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
126
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
129
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
132
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138
139 #endif // _LP64
140
141 // JSR 292 fixed register usages:
142 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
143
144 // Address is an abstraction used to represent a memory location
145 // using any of the amd64 addressing modes with one object.
146 //
147 // Note: A register location is represented via a Register, not
148 // via an address for efficiency & simplicity reasons.
149
150 class ArrayAddress;
151
152 class Address VALUE_OBJ_CLASS_SPEC {
153 public:
154 enum ScaleFactor {
155 no_scale = -1,
156 times_1 = 0,
157 times_2 = 1,
158 times_4 = 2,
159 times_8 = 3,
160 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
161 };
162 static ScaleFactor times(int size) {
163 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
164 if (size == 8) return times_8;
165 if (size == 4) return times_4;
166 if (size == 2) return times_2;
167 return times_1;
168 }
169 static int scale_size(ScaleFactor scale) {
170 assert(scale != no_scale, "");
171 assert(((1 << (int)times_1) == 1 &&
172 (1 << (int)times_2) == 2 &&
173 (1 << (int)times_4) == 4 &&
174 (1 << (int)times_8) == 8), "");
175 return (1 << (int)scale);
176 }
177
178 private:
179 Register _base;
180 Register _index;
181 ScaleFactor _scale;
182 int _disp;
183 RelocationHolder _rspec;
184
185 // Easily misused constructors make them private
186 // %%% can we make these go away?
187 NOT_LP64(Address(address loc, RelocationHolder spec);)
188 Address(int disp, address loc, relocInfo::relocType rtype);
189 Address(int disp, address loc, RelocationHolder spec);
190
191 public:
192
193 int disp() { return _disp; }
194 // creation
195 Address()
196 : _base(noreg),
197 _index(noreg),
198 _scale(no_scale),
199 _disp(0) {
200 }
201
202 // No default displacement otherwise Register can be implicitly
203 // converted to 0(Register) which is quite a different animal.
204
205 Address(Register base, int disp)
206 : _base(base),
207 _index(noreg),
208 _scale(no_scale),
209 _disp(disp) {
210 }
211
212 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
213 : _base (base),
214 _index(index),
215 _scale(scale),
216 _disp (disp) {
217 assert(!index->is_valid() == (scale == Address::no_scale),
218 "inconsistent address");
219 }
220
221 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
222 : _base (base),
223 _index(index.register_or_noreg()),
224 _scale(scale),
225 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
226 if (!index.is_register()) scale = Address::no_scale;
227 assert(!_index->is_valid() == (scale == Address::no_scale),
228 "inconsistent address");
229 }
230
231 Address plus_disp(int disp) const {
232 Address a = (*this);
233 a._disp += disp;
234 return a;
235 }
236
237 // The following two overloads are used in connection with the
238 // ByteSize type (see sizes.hpp). They simplify the use of
239 // ByteSize'd arguments in assembly code. Note that their equivalent
240 // for the optimized build are the member functions with int disp
241 // argument since ByteSize is mapped to an int type in that case.
242 //
243 // Note: DO NOT introduce similar overloaded functions for WordSize
244 // arguments as in the optimized mode, both ByteSize and WordSize
245 // are mapped to the same type and thus the compiler cannot make a
246 // distinction anymore (=> compiler errors).
247
248 #ifdef ASSERT
249 Address(Register base, ByteSize disp)
250 : _base(base),
251 _index(noreg),
252 _scale(no_scale),
253 _disp(in_bytes(disp)) {
254 }
255
256 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
257 : _base(base),
258 _index(index),
259 _scale(scale),
260 _disp(in_bytes(disp)) {
261 assert(!index->is_valid() == (scale == Address::no_scale),
262 "inconsistent address");
263 }
264
265 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
266 : _base (base),
267 _index(index.register_or_noreg()),
268 _scale(scale),
269 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
270 if (!index.is_register()) scale = Address::no_scale;
271 assert(!_index->is_valid() == (scale == Address::no_scale),
272 "inconsistent address");
273 }
274
275 #endif // ASSERT
276
277 // accessors
278 bool uses(Register reg) const { return _base == reg || _index == reg; }
279 Register base() const { return _base; }
280 Register index() const { return _index; }
281 ScaleFactor scale() const { return _scale; }
282 int disp() const { return _disp; }
283
284 // Convert the raw encoding form into the form expected by the constructor for
285 // Address. An index of 4 (rsp) corresponds to having no index, so convert
286 // that to noreg for the Address constructor.
287 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
288
289 static Address make_array(ArrayAddress);
290
291 private:
292 bool base_needs_rex() const {
293 return _base != noreg && _base->encoding() >= 8;
294 }
295
296 bool index_needs_rex() const {
297 return _index != noreg &&_index->encoding() >= 8;
298 }
299
300 relocInfo::relocType reloc() const { return _rspec.type(); }
301
302 friend class Assembler;
303 friend class MacroAssembler;
304 friend class LIR_Assembler; // base/index/scale/disp
305 };
306
307 //
308 // AddressLiteral has been split out from Address because operands of this type
309 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
310 // the few instructions that need to deal with address literals are unique and the
311 // MacroAssembler does not have to implement every instruction in the Assembler
312 // in order to search for address literals that may need special handling depending
313 // on the instruction and the platform. As small step on the way to merging i486/amd64
314 // directories.
315 //
316 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
317 friend class ArrayAddress;
318 RelocationHolder _rspec;
319 // Typically we use AddressLiterals we want to use their rval
320 // However in some situations we want the lval (effect address) of the item.
321 // We provide a special factory for making those lvals.
322 bool _is_lval;
323
324 // If the target is far we'll need to load the ea of this to
325 // a register to reach it. Otherwise if near we can do rip
326 // relative addressing.
327
328 address _target;
329
330 protected:
331 // creation
332 AddressLiteral()
333 : _is_lval(false),
334 _target(NULL)
335 {}
336
337 public:
338
339
340 AddressLiteral(address target, relocInfo::relocType rtype);
341
342 AddressLiteral(address target, RelocationHolder const& rspec)
343 : _rspec(rspec),
344 _is_lval(false),
345 _target(target)
346 {}
347
348 AddressLiteral addr() {
349 AddressLiteral ret = *this;
350 ret._is_lval = true;
351 return ret;
352 }
353
354
355 private:
356
357 address target() { return _target; }
358 bool is_lval() { return _is_lval; }
359
360 relocInfo::relocType reloc() const { return _rspec.type(); }
361 const RelocationHolder& rspec() const { return _rspec; }
362
363 friend class Assembler;
364 friend class MacroAssembler;
365 friend class Address;
366 friend class LIR_Assembler;
367 };
368
369 // Convience classes
370 class RuntimeAddress: public AddressLiteral {
371
372 public:
373
374 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
375
376 };
377
378 class OopAddress: public AddressLiteral {
379
380 public:
381
382 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
383
384 };
385
386 class ExternalAddress: public AddressLiteral {
387
388 public:
389
390 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
391
392 };
393
394 class InternalAddress: public AddressLiteral {
395
396 public:
397
398 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
399
400 };
401
402 // x86 can do array addressing as a single operation since disp can be an absolute
403 // address amd64 can't. We create a class that expresses the concept but does extra
404 // magic on amd64 to get the final result
405
406 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
407 private:
408
409 AddressLiteral _base;
410 Address _index;
411
412 public:
413
414 ArrayAddress() {};
415 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
416 AddressLiteral base() { return _base; }
417 Address index() { return _index; }
418
419 };
420
421 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
422
423 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
424 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
425 // is what you get. The Assembler is generating code into a CodeBuffer.
426
427 class Assembler : public AbstractAssembler {
428 friend class AbstractAssembler; // for the non-virtual hack
429 friend class LIR_Assembler; // as_Address()
430 friend class StubGenerator;
431
432 public:
433 enum Condition { // The x86 condition codes used for conditional jumps/moves.
434 zero = 0x4,
435 notZero = 0x5,
436 equal = 0x4,
437 notEqual = 0x5,
438 less = 0xc,
439 lessEqual = 0xe,
440 greater = 0xf,
441 greaterEqual = 0xd,
442 below = 0x2,
443 belowEqual = 0x6,
444 above = 0x7,
445 aboveEqual = 0x3,
446 overflow = 0x0,
447 noOverflow = 0x1,
448 carrySet = 0x2,
449 carryClear = 0x3,
450 negative = 0x8,
451 positive = 0x9,
452 parity = 0xa,
453 noParity = 0xb
454 };
455
456 enum Prefix {
457 // segment overrides
458 CS_segment = 0x2e,
459 SS_segment = 0x36,
460 DS_segment = 0x3e,
461 ES_segment = 0x26,
462 FS_segment = 0x64,
463 GS_segment = 0x65,
464
465 REX = 0x40,
466
467 REX_B = 0x41,
468 REX_X = 0x42,
469 REX_XB = 0x43,
470 REX_R = 0x44,
471 REX_RB = 0x45,
472 REX_RX = 0x46,
473 REX_RXB = 0x47,
474
475 REX_W = 0x48,
476
477 REX_WB = 0x49,
478 REX_WX = 0x4A,
479 REX_WXB = 0x4B,
480 REX_WR = 0x4C,
481 REX_WRB = 0x4D,
482 REX_WRX = 0x4E,
483 REX_WRXB = 0x4F
484 };
485
486 enum WhichOperand {
487 // input to locate_operand, and format code for relocations
488 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
489 disp32_operand = 1, // embedded 32-bit displacement or address
490 call32_operand = 2, // embedded 32-bit self-relative displacement
491 #ifndef _LP64
492 _WhichOperand_limit = 3
493 #else
494 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
495 _WhichOperand_limit = 4
496 #endif
497 };
498
499
500
501 // NOTE: The general philopsophy of the declarations here is that 64bit versions
502 // of instructions are freely declared without the need for wrapping them an ifdef.
503 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
504 // In the .cpp file the implementations are wrapped so that they are dropped out
505 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
506 // to the size it was prior to merging up the 32bit and 64bit assemblers.
507 //
508 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
509 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
510
511 private:
512
513
514 // 64bit prefixes
515 int prefix_and_encode(int reg_enc, bool byteinst = false);
516 int prefixq_and_encode(int reg_enc);
517
518 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
519 int prefixq_and_encode(int dst_enc, int src_enc);
520
521 void prefix(Register reg);
522 void prefix(Address adr);
523 void prefixq(Address adr);
524
525 void prefix(Address adr, Register reg, bool byteinst = false);
526 void prefixq(Address adr, Register reg);
527
528 void prefix(Address adr, XMMRegister reg);
529
530 void prefetch_prefix(Address src);
531
532 // Helper functions for groups of instructions
533 void emit_arith_b(int op1, int op2, Register dst, int imm8);
534
535 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
536 // only 32bit??
537 void emit_arith(int op1, int op2, Register dst, jobject obj);
538 void emit_arith(int op1, int op2, Register dst, Register src);
539
540 void emit_operand(Register reg,
541 Register base, Register index, Address::ScaleFactor scale,
542 int disp,
543 RelocationHolder const& rspec,
544 int rip_relative_correction = 0);
545
546 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
547
548 // operands that only take the original 32bit registers
549 void emit_operand32(Register reg, Address adr);
550
551 void emit_operand(XMMRegister reg,
552 Register base, Register index, Address::ScaleFactor scale,
553 int disp,
554 RelocationHolder const& rspec);
555
556 void emit_operand(XMMRegister reg, Address adr);
557
558 void emit_operand(MMXRegister reg, Address adr);
559
560 // workaround gcc (3.2.1-7) bug
561 void emit_operand(Address adr, MMXRegister reg);
562
563
564 // Immediate-to-memory forms
565 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
566
567 void emit_farith(int b1, int b2, int i);
568
569
570 protected:
571 #ifdef ASSERT
572 void check_relocation(RelocationHolder const& rspec, int format);
573 #endif
574
575 inline void emit_long64(jlong x);
576
577 void emit_data(jint data, relocInfo::relocType rtype, int format);
578 void emit_data(jint data, RelocationHolder const& rspec, int format);
579 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
580 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
581
582
583 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
584
585 // These are all easily abused and hence protected
586
587 // 32BIT ONLY SECTION
588 #ifndef _LP64
589 // Make these disappear in 64bit mode since they would never be correct
590 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
591 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
592
593 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
594 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
595
596 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
597 #else
598 // 64BIT ONLY SECTION
599 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
600
601 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
602 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
603
604 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
605 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
606 #endif // _LP64
607
608 // These are unique in that we are ensured by the caller that the 32bit
609 // relative in these instructions will always be able to reach the potentially
610 // 64bit address described by entry. Since they can take a 64bit address they
611 // don't have the 32 suffix like the other instructions in this class.
612
613 void call_literal(address entry, RelocationHolder const& rspec);
614 void jmp_literal(address entry, RelocationHolder const& rspec);
615
616 // Avoid using directly section
617 // Instructions in this section are actually usable by anyone without danger
618 // of failure but have performance issues that are addressed my enhanced
619 // instructions which will do the proper thing base on the particular cpu.
620 // We protect them because we don't trust you...
621
622 // Don't use next inc() and dec() methods directly. INC & DEC instructions
623 // could cause a partial flag stall since they don't set CF flag.
624 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
625 // which call inc() & dec() or add() & sub() in accordance with
626 // the product flag UseIncDec value.
627
628 void decl(Register dst);
629 void decl(Address dst);
630 void decq(Register dst);
631 void decq(Address dst);
632
633 void incl(Register dst);
634 void incl(Address dst);
635 void incq(Register dst);
636 void incq(Address dst);
637
638 // New cpus require use of movsd and movss to avoid partial register stall
639 // when loading from memory. But for old Opteron use movlpd instead of movsd.
640 // The selection is done in MacroAssembler::movdbl() and movflt().
641
642 // Move Scalar Single-Precision Floating-Point Values
643 void movss(XMMRegister dst, Address src);
644 void movss(XMMRegister dst, XMMRegister src);
645 void movss(Address dst, XMMRegister src);
646
647 // Move Scalar Double-Precision Floating-Point Values
648 void movsd(XMMRegister dst, Address src);
649 void movsd(XMMRegister dst, XMMRegister src);
650 void movsd(Address dst, XMMRegister src);
651 void movlpd(XMMRegister dst, Address src);
652
653 // New cpus require use of movaps and movapd to avoid partial register stall
654 // when moving between registers.
655 void movaps(XMMRegister dst, XMMRegister src);
656 void movapd(XMMRegister dst, XMMRegister src);
657
658 // End avoid using directly
659
660
661 // Instruction prefixes
662 void prefix(Prefix p);
663
664 public:
665
666 // Creation
667 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
668
669 // Decoding
670 static address locate_operand(address inst, WhichOperand which);
671 static address locate_next_instruction(address inst);
672
673 // Utilities
674
675 #ifdef _LP64
676 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
677 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
678 #else
679 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
680 static bool is_simm32(int32_t x) { return true; }
681 #endif // LP64
682
683 // Generic instructions
684 // Does 32bit or 64bit as needed for the platform. In some sense these
685 // belong in macro assembler but there is no need for both varieties to exist
686
687 void lea(Register dst, Address src);
688
689 void mov(Register dst, Register src);
690
691 void pusha();
692 void popa();
693
694 void pushf();
695 void popf();
696
697 void push(int32_t imm32);
698
699 void push(Register src);
700
701 void pop(Register dst);
702
703 // These are dummies to prevent surprise implicit conversions to Register
704 void push(void* v);
705 void pop(void* v);
706
707
708 // These do register sized moves/scans
709 void rep_mov();
710 void rep_set();
711 void repne_scan();
712 #ifdef _LP64
713 void repne_scanl();
714 #endif
715
716 // Vanilla instructions in lexical order
717
718 void adcl(Register dst, int32_t imm32);
719 void adcl(Register dst, Address src);
720 void adcl(Register dst, Register src);
721
722 void adcq(Register dst, int32_t imm32);
723 void adcq(Register dst, Address src);
724 void adcq(Register dst, Register src);
725
726
727 void addl(Address dst, int32_t imm32);
728 void addl(Address dst, Register src);
729 void addl(Register dst, int32_t imm32);
730 void addl(Register dst, Address src);
731 void addl(Register dst, Register src);
732
733 void addq(Address dst, int32_t imm32);
734 void addq(Address dst, Register src);
735 void addq(Register dst, int32_t imm32);
736 void addq(Register dst, Address src);
737 void addq(Register dst, Register src);
738
739
740 void addr_nop_4();
741 void addr_nop_5();
742 void addr_nop_7();
743 void addr_nop_8();
744
745 // Add Scalar Double-Precision Floating-Point Values
746 void addsd(XMMRegister dst, Address src);
747 void addsd(XMMRegister dst, XMMRegister src);
748
749 // Add Scalar Single-Precision Floating-Point Values
750 void addss(XMMRegister dst, Address src);
751 void addss(XMMRegister dst, XMMRegister src);
752
753 void andl(Register dst, int32_t imm32);
754 void andl(Register dst, Address src);
755 void andl(Register dst, Register src);
756
757 void andq(Register dst, int32_t imm32);
758 void andq(Register dst, Address src);
759 void andq(Register dst, Register src);
760
761
762 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
763 void andpd(XMMRegister dst, Address src);
764 void andpd(XMMRegister dst, XMMRegister src);
765
766 void bsfl(Register dst, Register src);
767 void bsrl(Register dst, Register src);
768
769 #ifdef _LP64
770 void bsfq(Register dst, Register src);
771 void bsrq(Register dst, Register src);
772 #endif
773
774 void bswapl(Register reg);
775
776 void bswapq(Register reg);
777
778 void call(Label& L, relocInfo::relocType rtype);
779 void call(Register reg); // push pc; pc <- reg
780 void call(Address adr); // push pc; pc <- adr
781
782 void cdql();
783
784 void cdqq();
785
786 void cld() { emit_byte(0xfc); }
787
788 void clflush(Address adr);
789
790 void cmovl(Condition cc, Register dst, Register src);
791 void cmovl(Condition cc, Register dst, Address src);
792
793 void cmovq(Condition cc, Register dst, Register src);
794 void cmovq(Condition cc, Register dst, Address src);
795
796
797 void cmpb(Address dst, int imm8);
798
799 void cmpl(Address dst, int32_t imm32);
800
801 void cmpl(Register dst, int32_t imm32);
802 void cmpl(Register dst, Register src);
803 void cmpl(Register dst, Address src);
804
805 void cmpq(Address dst, int32_t imm32);
806 void cmpq(Address dst, Register src);
807
808 void cmpq(Register dst, int32_t imm32);
809 void cmpq(Register dst, Register src);
810 void cmpq(Register dst, Address src);
811
812 // these are dummies used to catch attempting to convert NULL to Register
813 void cmpl(Register dst, void* junk); // dummy
814 void cmpq(Register dst, void* junk); // dummy
815
816 void cmpw(Address dst, int imm16);
817
818 void cmpxchg8 (Address adr);
819
820 void cmpxchgl(Register reg, Address adr);
821
822 void cmpxchgq(Register reg, Address adr);
823
824 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
825 void comisd(XMMRegister dst, Address src);
826
827 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
828 void comiss(XMMRegister dst, Address src);
829
830 // Identify processor type and features
831 void cpuid() {
832 emit_byte(0x0F);
833 emit_byte(0xA2);
834 }
835
836 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
837 void cvtsd2ss(XMMRegister dst, XMMRegister src);
838
839 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
840 void cvtsi2sdl(XMMRegister dst, Register src);
841 void cvtsi2sdq(XMMRegister dst, Register src);
842
843 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
844 void cvtsi2ssl(XMMRegister dst, Register src);
845 void cvtsi2ssq(XMMRegister dst, Register src);
846
847 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
848 void cvtdq2pd(XMMRegister dst, XMMRegister src);
849
850 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
851 void cvtdq2ps(XMMRegister dst, XMMRegister src);
852
853 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
854 void cvtss2sd(XMMRegister dst, XMMRegister src);
855
856 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
857 void cvttsd2sil(Register dst, Address src);
858 void cvttsd2sil(Register dst, XMMRegister src);
859 void cvttsd2siq(Register dst, XMMRegister src);
860
861 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
862 void cvttss2sil(Register dst, XMMRegister src);
863 void cvttss2siq(Register dst, XMMRegister src);
864
865 // Divide Scalar Double-Precision Floating-Point Values
866 void divsd(XMMRegister dst, Address src);
867 void divsd(XMMRegister dst, XMMRegister src);
868
869 // Divide Scalar Single-Precision Floating-Point Values
870 void divss(XMMRegister dst, Address src);
871 void divss(XMMRegister dst, XMMRegister src);
872
873 void emms();
874
875 void fabs();
876
877 void fadd(int i);
878
879 void fadd_d(Address src);
880 void fadd_s(Address src);
881
882 // "Alternate" versions of x87 instructions place result down in FPU
883 // stack instead of on TOS
884
885 void fadda(int i); // "alternate" fadd
886 void faddp(int i = 1);
887
888 void fchs();
889
890 void fcom(int i);
891
892 void fcomp(int i = 1);
893 void fcomp_d(Address src);
894 void fcomp_s(Address src);
895
896 void fcompp();
897
898 void fcos();
899
900 void fdecstp();
901
902 void fdiv(int i);
903 void fdiv_d(Address src);
904 void fdivr_s(Address src);
905 void fdiva(int i); // "alternate" fdiv
906 void fdivp(int i = 1);
907
908 void fdivr(int i);
909 void fdivr_d(Address src);
910 void fdiv_s(Address src);
911
912 void fdivra(int i); // "alternate" reversed fdiv
913
914 void fdivrp(int i = 1);
915
916 void ffree(int i = 0);
917
918 void fild_d(Address adr);
919 void fild_s(Address adr);
920
921 void fincstp();
922
923 void finit();
924
925 void fist_s (Address adr);
926 void fistp_d(Address adr);
927 void fistp_s(Address adr);
928
929 void fld1();
930
931 void fld_d(Address adr);
932 void fld_s(Address adr);
933 void fld_s(int index);
934 void fld_x(Address adr); // extended-precision (80-bit) format
935
936 void fldcw(Address src);
937
938 void fldenv(Address src);
939
940 void fldlg2();
941
942 void fldln2();
943
944 void fldz();
945
946 void flog();
947 void flog10();
948
949 void fmul(int i);
950
951 void fmul_d(Address src);
952 void fmul_s(Address src);
953
954 void fmula(int i); // "alternate" fmul
955
956 void fmulp(int i = 1);
957
958 void fnsave(Address dst);
959
960 void fnstcw(Address src);
961
962 void fnstsw_ax();
963
964 void fprem();
965 void fprem1();
966
967 void frstor(Address src);
968
969 void fsin();
970
971 void fsqrt();
972
973 void fst_d(Address adr);
974 void fst_s(Address adr);
975
976 void fstp_d(Address adr);
977 void fstp_d(int index);
978 void fstp_s(Address adr);
979 void fstp_x(Address adr); // extended-precision (80-bit) format
980
981 void fsub(int i);
982 void fsub_d(Address src);
983 void fsub_s(Address src);
984
985 void fsuba(int i); // "alternate" fsub
986
987 void fsubp(int i = 1);
988
989 void fsubr(int i);
990 void fsubr_d(Address src);
991 void fsubr_s(Address src);
992
993 void fsubra(int i); // "alternate" reversed fsub
994
995 void fsubrp(int i = 1);
996
997 void ftan();
998
999 void ftst();
1000
1001 void fucomi(int i = 1);
1002 void fucomip(int i = 1);
1003
1004 void fwait();
1005
1006 void fxch(int i = 1);
1007
1008 void fxrstor(Address src);
1009
1010 void fxsave(Address dst);
1011
1012 void fyl2x();
1013
1014 void hlt();
1015
1016 void idivl(Register src);
1017
1018 void idivq(Register src);
1019
1020 void imull(Register dst, Register src);
1021 void imull(Register dst, Register src, int value);
1022
1023 void imulq(Register dst, Register src);
1024 void imulq(Register dst, Register src, int value);
1025
1026
1027 // jcc is the generic conditional branch generator to run-
1028 // time routines, jcc is used for branches to labels. jcc
1029 // takes a branch opcode (cc) and a label (L) and generates
1030 // either a backward branch or a forward branch and links it
1031 // to the label fixup chain. Usage:
1032 //
1033 // Label L; // unbound label
1034 // jcc(cc, L); // forward branch to unbound label
1035 // bind(L); // bind label to the current pc
1036 // jcc(cc, L); // backward branch to bound label
1037 // bind(L); // illegal: a label may be bound only once
1038 //
1039 // Note: The same Label can be used for forward and backward branches
1040 // but it may be bound only once.
1041
1042 void jcc(Condition cc, Label& L,
1043 relocInfo::relocType rtype = relocInfo::none);
1044
1045 // Conditional jump to a 8-bit offset to L.
1046 // WARNING: be very careful using this for forward jumps. If the label is
1047 // not bound within an 8-bit offset of this instruction, a run-time error
1048 // will occur.
1049 void jccb(Condition cc, Label& L);
1050
1051 void jmp(Address entry); // pc <- entry
1052
1053 // Label operations & relative jumps (PPUM Appendix D)
1054 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
1055
1056 void jmp(Register entry); // pc <- entry
1057
1058 // Unconditional 8-bit offset jump to L.
1059 // WARNING: be very careful using this for forward jumps. If the label is
1060 // not bound within an 8-bit offset of this instruction, a run-time error
1061 // will occur.
1062 void jmpb(Label& L);
1063
1064 void ldmxcsr( Address src );
1065
1066 void leal(Register dst, Address src);
1067
1068 void leaq(Register dst, Address src);
1069
1070 void lfence() {
1071 emit_byte(0x0F);
1072 emit_byte(0xAE);
1073 emit_byte(0xE8);
1074 }
1075
1076 void lock();
1077
1078 void lzcntl(Register dst, Register src);
1079
1080 #ifdef _LP64
1081 void lzcntq(Register dst, Register src);
1082 #endif
1083
1084 enum Membar_mask_bits {
1085 StoreStore = 1 << 3,
1086 LoadStore = 1 << 2,
1087 StoreLoad = 1 << 1,
1088 LoadLoad = 1 << 0
1089 };
1090
1091 // Serializes memory and blows flags
1092 void membar(Membar_mask_bits order_constraint) {
1093 if (os::is_MP()) {
1094 // We only have to handle StoreLoad
1095 if (order_constraint & StoreLoad) {
1096 // All usable chips support "locked" instructions which suffice
1097 // as barriers, and are much faster than the alternative of
1098 // using cpuid instruction. We use here a locked add [esp],0.
1099 // This is conveniently otherwise a no-op except for blowing
1100 // flags.
1101 // Any change to this code may need to revisit other places in
1102 // the code where this idiom is used, in particular the
1103 // orderAccess code.
1104 lock();
1105 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1106 }
1107 }
1108 }
1109
1110 void mfence();
1111
1112 // Moves
1113
1114 void mov64(Register dst, int64_t imm64);
1115
1116 void movb(Address dst, Register src);
1117 void movb(Address dst, int imm8);
1118 void movb(Register dst, Address src);
1119
1120 void movdl(XMMRegister dst, Register src);
1121 void movdl(Register dst, XMMRegister src);
1122
1123 // Move Double Quadword
1124 void movdq(XMMRegister dst, Register src);
1125 void movdq(Register dst, XMMRegister src);
1126
1127 // Move Aligned Double Quadword
1128 void movdqa(Address dst, XMMRegister src);
1129 void movdqa(XMMRegister dst, Address src);
1130 void movdqa(XMMRegister dst, XMMRegister src);
1131
1132 // Move Unaligned Double Quadword
1133 void movdqu(Address dst, XMMRegister src);
1134 void movdqu(XMMRegister dst, Address src);
1135 void movdqu(XMMRegister dst, XMMRegister src);
1136
1137 void movl(Register dst, int32_t imm32);
1138 void movl(Address dst, int32_t imm32);
1139 void movl(Register dst, Register src);
1140 void movl(Register dst, Address src);
1141 void movl(Address dst, Register src);
1142
1143 // These dummies prevent using movl from converting a zero (like NULL) into Register
1144 // by giving the compiler two choices it can't resolve
1145
1146 void movl(Address dst, void* junk);
1147 void movl(Register dst, void* junk);
1148
1149 #ifdef _LP64
1150 void movq(Register dst, Register src);
1151 void movq(Register dst, Address src);
1152 void movq(Address dst, Register src);
1153 #endif
1154
1155 void movq(Address dst, MMXRegister src );
1156 void movq(MMXRegister dst, Address src );
1157
1158 #ifdef _LP64
1159 // These dummies prevent using movq from converting a zero (like NULL) into Register
1160 // by giving the compiler two choices it can't resolve
1161
1162 void movq(Address dst, void* dummy);
1163 void movq(Register dst, void* dummy);
1164 #endif
1165
1166 // Move Quadword
1167 void movq(Address dst, XMMRegister src);
1168 void movq(XMMRegister dst, Address src);
1169
1170 void movsbl(Register dst, Address src);
1171 void movsbl(Register dst, Register src);
1172
1173 #ifdef _LP64
1174 void movsbq(Register dst, Address src);
1175 void movsbq(Register dst, Register src);
1176
1177 // Move signed 32bit immediate to 64bit extending sign
1178 void movslq(Address dst, int32_t imm64);
1179 void movslq(Register dst, int32_t imm64);
1180
1181 void movslq(Register dst, Address src);
1182 void movslq(Register dst, Register src);
1183 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1184 #endif
1185
1186 void movswl(Register dst, Address src);
1187 void movswl(Register dst, Register src);
1188
1189 #ifdef _LP64
1190 void movswq(Register dst, Address src);
1191 void movswq(Register dst, Register src);
1192 #endif
1193
1194 void movw(Address dst, int imm16);
1195 void movw(Register dst, Address src);
1196 void movw(Address dst, Register src);
1197
1198 void movzbl(Register dst, Address src);
1199 void movzbl(Register dst, Register src);
1200
1201 #ifdef _LP64
1202 void movzbq(Register dst, Address src);
1203 void movzbq(Register dst, Register src);
1204 #endif
1205
1206 void movzwl(Register dst, Address src);
1207 void movzwl(Register dst, Register src);
1208
1209 #ifdef _LP64
1210 void movzwq(Register dst, Address src);
1211 void movzwq(Register dst, Register src);
1212 #endif
1213
1214 void mull(Address src);
1215 void mull(Register src);
1216
1217 // Multiply Scalar Double-Precision Floating-Point Values
1218 void mulsd(XMMRegister dst, Address src);
1219 void mulsd(XMMRegister dst, XMMRegister src);
1220
1221 // Multiply Scalar Single-Precision Floating-Point Values
1222 void mulss(XMMRegister dst, Address src);
1223 void mulss(XMMRegister dst, XMMRegister src);
1224
1225 void negl(Register dst);
1226
1227 #ifdef _LP64
1228 void negq(Register dst);
1229 #endif
1230
1231 void nop(int i = 1);
1232
1233 void notl(Register dst);
1234
1235 #ifdef _LP64
1236 void notq(Register dst);
1237 #endif
1238
1239 void orl(Address dst, int32_t imm32);
1240 void orl(Register dst, int32_t imm32);
1241 void orl(Register dst, Address src);
1242 void orl(Register dst, Register src);
1243
1244 void orq(Address dst, int32_t imm32);
1245 void orq(Register dst, int32_t imm32);
1246 void orq(Register dst, Address src);
1247 void orq(Register dst, Register src);
1248
1249 // SSE4.2 string instructions
1250 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1251 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1252
1253 #ifndef _LP64 // no 32bit push/pop on amd64
1254 void popl(Address dst);
1255 #endif
1256
1257 #ifdef _LP64
1258 void popq(Address dst);
1259 #endif
1260
1261 void popcntl(Register dst, Address src);
1262 void popcntl(Register dst, Register src);
1263
1264 #ifdef _LP64
1265 void popcntq(Register dst, Address src);
1266 void popcntq(Register dst, Register src);
1267 #endif
1268
1269 // Prefetches (SSE, SSE2, 3DNOW only)
1270
1271 void prefetchnta(Address src);
1272 void prefetchr(Address src);
1273 void prefetcht0(Address src);
1274 void prefetcht1(Address src);
1275 void prefetcht2(Address src);
1276 void prefetchw(Address src);
1277
1278 // Shuffle Packed Doublewords
1279 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1280 void pshufd(XMMRegister dst, Address src, int mode);
1281
1282 // Shuffle Packed Low Words
1283 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1284 void pshuflw(XMMRegister dst, Address src, int mode);
1285
1286 // Shift Right Logical Quadword Immediate
1287 void psrlq(XMMRegister dst, int shift);
1288
1289 // Logical Compare Double Quadword
1290 void ptest(XMMRegister dst, XMMRegister src);
1291 void ptest(XMMRegister dst, Address src);
1292
1293 // Interleave Low Bytes
1294 void punpcklbw(XMMRegister dst, XMMRegister src);
1295
1296 #ifndef _LP64 // no 32bit push/pop on amd64
1297 void pushl(Address src);
1298 #endif
1299
1300 void pushq(Address src);
1301
1302 // Xor Packed Byte Integer Values
1303 void pxor(XMMRegister dst, Address src);
1304 void pxor(XMMRegister dst, XMMRegister src);
1305
1306 void rcll(Register dst, int imm8);
1307
1308 void rclq(Register dst, int imm8);
1309
1310 void ret(int imm16);
1311
1312 void sahf();
1313
1314 void sarl(Register dst, int imm8);
1315 void sarl(Register dst);
1316
1317 void sarq(Register dst, int imm8);
1318 void sarq(Register dst);
1319
1320 void sbbl(Address dst, int32_t imm32);
1321 void sbbl(Register dst, int32_t imm32);
1322 void sbbl(Register dst, Address src);
1323 void sbbl(Register dst, Register src);
1324
1325 void sbbq(Address dst, int32_t imm32);
1326 void sbbq(Register dst, int32_t imm32);
1327 void sbbq(Register dst, Address src);
1328 void sbbq(Register dst, Register src);
1329
1330 void setb(Condition cc, Register dst);
1331
1332 void shldl(Register dst, Register src);
1333
1334 void shll(Register dst, int imm8);
1335 void shll(Register dst);
1336
1337 void shlq(Register dst, int imm8);
1338 void shlq(Register dst);
1339
1340 void shrdl(Register dst, Register src);
1341
1342 void shrl(Register dst, int imm8);
1343 void shrl(Register dst);
1344
1345 void shrq(Register dst, int imm8);
1346 void shrq(Register dst);
1347
1348 void smovl(); // QQQ generic?
1349
1350 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1351 void sqrtsd(XMMRegister dst, Address src);
1352 void sqrtsd(XMMRegister dst, XMMRegister src);
1353
1354 void std() { emit_byte(0xfd); }
1355
1356 void stmxcsr( Address dst );
1357
1358 void subl(Address dst, int32_t imm32);
1359 void subl(Address dst, Register src);
1360 void subl(Register dst, int32_t imm32);
1361 void subl(Register dst, Address src);
1362 void subl(Register dst, Register src);
1363
1364 void subq(Address dst, int32_t imm32);
1365 void subq(Address dst, Register src);
1366 void subq(Register dst, int32_t imm32);
1367 void subq(Register dst, Address src);
1368 void subq(Register dst, Register src);
1369
1370
1371 // Subtract Scalar Double-Precision Floating-Point Values
1372 void subsd(XMMRegister dst, Address src);
1373 void subsd(XMMRegister dst, XMMRegister src);
1374
1375 // Subtract Scalar Single-Precision Floating-Point Values
1376 void subss(XMMRegister dst, Address src);
1377 void subss(XMMRegister dst, XMMRegister src);
1378
1379 void testb(Register dst, int imm8);
1380
1381 void testl(Register dst, int32_t imm32);
1382 void testl(Register dst, Register src);
1383 void testl(Register dst, Address src);
1384
1385 void testq(Register dst, int32_t imm32);
1386 void testq(Register dst, Register src);
1387
1388
1389 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1390 void ucomisd(XMMRegister dst, Address src);
1391 void ucomisd(XMMRegister dst, XMMRegister src);
1392
1393 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1394 void ucomiss(XMMRegister dst, Address src);
1395 void ucomiss(XMMRegister dst, XMMRegister src);
1396
1397 void xaddl(Address dst, Register src);
1398
1399 void xaddq(Address dst, Register src);
1400
1401 void xchgl(Register reg, Address adr);
1402 void xchgl(Register dst, Register src);
1403
1404 void xchgq(Register reg, Address adr);
1405 void xchgq(Register dst, Register src);
1406
1407 void xorl(Register dst, int32_t imm32);
1408 void xorl(Register dst, Address src);
1409 void xorl(Register dst, Register src);
1410
1411 void xorq(Register dst, Address src);
1412 void xorq(Register dst, Register src);
1413
1414 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1415 void xorpd(XMMRegister dst, Address src);
1416 void xorpd(XMMRegister dst, XMMRegister src);
1417
1418 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1419 void xorps(XMMRegister dst, Address src);
1420 void xorps(XMMRegister dst, XMMRegister src);
1421
1422 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1423 };
1424
1425
1426 // MacroAssembler extends Assembler by frequently used macros.
1427 //
1428 // Instructions for which a 'better' code sequence exists depending
1429 // on arguments should also go in here.
1430
1431 class MacroAssembler: public Assembler {
1432 friend class LIR_Assembler;
1433 friend class Runtime1; // as_Address()
1434 protected:
1435
1436 Address as_Address(AddressLiteral adr);
1437 Address as_Address(ArrayAddress adr);
1438
1439 // Support for VM calls
1440 //
1441 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1442 // may customize this version by overriding it for its purposes (e.g., to save/restore
1443 // additional registers when doing a VM call).
1444 #ifdef CC_INTERP
1445 // c++ interpreter never wants to use interp_masm version of call_VM
1446 #define VIRTUAL
1447 #else
1448 #define VIRTUAL virtual
1449 #endif
1450
1451 VIRTUAL void call_VM_leaf_base(
1452 address entry_point, // the entry point
1453 int number_of_arguments // the number of arguments to pop after the call
1454 );
1455
1456 // This is the base routine called by the different versions of call_VM. The interpreter
1457 // may customize this version by overriding it for its purposes (e.g., to save/restore
1458 // additional registers when doing a VM call).
1459 //
1460 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1461 // returns the register which contains the thread upon return. If a thread register has been
1462 // specified, the return value will correspond to that register. If no last_java_sp is specified
1463 // (noreg) than rsp will be used instead.
1464 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1465 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1466 Register java_thread, // the thread if computed before ; use noreg otherwise
1467 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1468 address entry_point, // the entry point
1469 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1470 bool check_exceptions // whether to check for pending exceptions after return
1471 );
1472
1473 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1474 // The implementation is only non-empty for the InterpreterMacroAssembler,
1475 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1476 virtual void check_and_handle_popframe(Register java_thread);
1477 virtual void check_and_handle_earlyret(Register java_thread);
1478
1479 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1480
1481 // helpers for FPU flag access
1482 // tmp is a temporary register, if none is available use noreg
1483 void save_rax (Register tmp);
1484 void restore_rax(Register tmp);
1485
1486 public:
1487 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1488
1489 // Support for NULL-checks
1490 //
1491 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1492 // If the accessed location is M[reg + offset] and the offset is known, provide the
1493 // offset. No explicit code generation is needed if the offset is within a certain
1494 // range (0 <= offset <= page_size).
1495
1496 void null_check(Register reg, int offset = -1);
1497 static bool needs_explicit_null_check(intptr_t offset);
1498
1499 // Required platform-specific helpers for Label::patch_instructions.
1500 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1501 void pd_patch_instruction(address branch, address target);
1502 #ifndef PRODUCT
1503 static void pd_print_patched_instruction(address branch);
1504 #endif
1505
1506 // The following 4 methods return the offset of the appropriate move instruction
1507
1508 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1509 int load_unsigned_byte(Register dst, Address src);
1510 int load_unsigned_short(Register dst, Address src);
1511
1512 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1513 int load_signed_byte(Register dst, Address src);
1514 int load_signed_short(Register dst, Address src);
1515
1516 // Support for sign-extension (hi:lo = extend_sign(lo))
1517 void extend_sign(Register hi, Register lo);
1518
1519 // Loading values by size and signed-ness
1520 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
1521
1522 // Support for inc/dec with optimal instruction selection depending on value
1523
1524 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1525 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1526
1527 void decrementl(Address dst, int value = 1);
1528 void decrementl(Register reg, int value = 1);
1529
1530 void decrementq(Register reg, int value = 1);
1531 void decrementq(Address dst, int value = 1);
1532
1533 void incrementl(Address dst, int value = 1);
1534 void incrementl(Register reg, int value = 1);
1535
1536 void incrementq(Register reg, int value = 1);
1537 void incrementq(Address dst, int value = 1);
1538
1539
1540 // Support optimal SSE move instructions.
1541 void movflt(XMMRegister dst, XMMRegister src) {
1542 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1543 else { movss (dst, src); return; }
1544 }
1545 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1546 void movflt(XMMRegister dst, AddressLiteral src);
1547 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1548
1549 void movdbl(XMMRegister dst, XMMRegister src) {
1550 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1551 else { movsd (dst, src); return; }
1552 }
1553
1554 void movdbl(XMMRegister dst, AddressLiteral src);
1555
1556 void movdbl(XMMRegister dst, Address src) {
1557 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1558 else { movlpd(dst, src); return; }
1559 }
1560 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1561
1562 void incrementl(AddressLiteral dst);
1563 void incrementl(ArrayAddress dst);
1564
1565 // Alignment
1566 void align(int modulus);
1567
1568 // Misc
1569 void fat_nop(); // 5 byte nop
1570
1571 // Stack frame creation/removal
1572 void enter();
1573 void leave();
1574
1575 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1576 // The pointer will be loaded into the thread register.
1577 void get_thread(Register thread);
1578
1579
1580 // Support for VM calls
1581 //
1582 // It is imperative that all calls into the VM are handled via the call_VM macros.
1583 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1584 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1585
1586
1587 void call_VM(Register oop_result,
1588 address entry_point,
1589 bool check_exceptions = true);
1590 void call_VM(Register oop_result,
1591 address entry_point,
1592 Register arg_1,
1593 bool check_exceptions = true);
1594 void call_VM(Register oop_result,
1595 address entry_point,
1596 Register arg_1, Register arg_2,
1597 bool check_exceptions = true);
1598 void call_VM(Register oop_result,
1599 address entry_point,
1600 Register arg_1, Register arg_2, Register arg_3,
1601 bool check_exceptions = true);
1602
1603 // Overloadings with last_Java_sp
1604 void call_VM(Register oop_result,
1605 Register last_java_sp,
1606 address entry_point,
1607 int number_of_arguments = 0,
1608 bool check_exceptions = true);
1609 void call_VM(Register oop_result,
1610 Register last_java_sp,
1611 address entry_point,
1612 Register arg_1, bool
1613 check_exceptions = true);
1614 void call_VM(Register oop_result,
1615 Register last_java_sp,
1616 address entry_point,
1617 Register arg_1, Register arg_2,
1618 bool check_exceptions = true);
1619 void call_VM(Register oop_result,
1620 Register last_java_sp,
1621 address entry_point,
1622 Register arg_1, Register arg_2, Register arg_3,
1623 bool check_exceptions = true);
1624
1625 void call_VM_leaf(address entry_point,
1626 int number_of_arguments = 0);
1627 void call_VM_leaf(address entry_point,
1628 Register arg_1);
1629 void call_VM_leaf(address entry_point,
1630 Register arg_1, Register arg_2);
1631 void call_VM_leaf(address entry_point,
1632 Register arg_1, Register arg_2, Register arg_3);
1633
1634 // last Java Frame (fills frame anchor)
1635 void set_last_Java_frame(Register thread,
1636 Register last_java_sp,
1637 Register last_java_fp,
1638 address last_java_pc);
1639
1640 // thread in the default location (r15_thread on 64bit)
1641 void set_last_Java_frame(Register last_java_sp,
1642 Register last_java_fp,
1643 address last_java_pc);
1644
1645 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1646
1647 // thread in the default location (r15_thread on 64bit)
1648 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1649
1650 // Stores
1651 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1652 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1653
1654 void g1_write_barrier_pre(Register obj,
1655 #ifndef _LP64
1656 Register thread,
1657 #endif
1658 Register tmp,
1659 Register tmp2,
1660 bool tosca_live);
1661 void g1_write_barrier_post(Register store_addr,
1662 Register new_val,
1663 #ifndef _LP64
1664 Register thread,
1665 #endif
1666 Register tmp,
1667 Register tmp2);
1668
1669
1670 // split store_check(Register obj) to enhance instruction interleaving
1671 void store_check_part_1(Register obj);
1672 void store_check_part_2(Register obj);
1673
1674 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1675 void c2bool(Register x);
1676
1677 // C++ bool manipulation
1678
1679 void movbool(Register dst, Address src);
1680 void movbool(Address dst, bool boolconst);
1681 void movbool(Address dst, Register src);
1682 void testbool(Register dst);
1683
1684 // oop manipulations
1685 void load_klass(Register dst, Register src);
1686 void store_klass(Register dst, Register src);
1687
1688 void load_heap_oop(Register dst, Address src);
1689 void store_heap_oop(Address dst, Register src);
1690
1691 // Used for storing NULL. All other oop constants should be
1692 // stored using routines that take a jobject.
1693 void store_heap_oop_null(Address dst);
1694
1695 void load_prototype_header(Register dst, Register src);
1696
1697 #ifdef _LP64
1698 void store_klass_gap(Register dst, Register src);
1699
1700 // This dummy is to prevent a call to store_heap_oop from
1701 // converting a zero (like NULL) into a Register by giving
1702 // the compiler two choices it can't resolve
1703
1704 void store_heap_oop(Address dst, void* dummy);
1705
1706 void encode_heap_oop(Register r);
1707 void decode_heap_oop(Register r);
1708 void encode_heap_oop_not_null(Register r);
1709 void decode_heap_oop_not_null(Register r);
1710 void encode_heap_oop_not_null(Register dst, Register src);
1711 void decode_heap_oop_not_null(Register dst, Register src);
1712
1713 void set_narrow_oop(Register dst, jobject obj);
1714 void set_narrow_oop(Address dst, jobject obj);
1715 void cmp_narrow_oop(Register dst, jobject obj);
1716 void cmp_narrow_oop(Address dst, jobject obj);
1717
1718 // if heap base register is used - reinit it with the correct value
1719 void reinit_heapbase();
1720
1721 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1722
1723 #endif // _LP64
1724
1725 // Int division/remainder for Java
1726 // (as idivl, but checks for special case as described in JVM spec.)
1727 // returns idivl instruction offset for implicit exception handling
1728 int corrected_idivl(Register reg);
1729
1730 // Long division/remainder for Java
1731 // (as idivq, but checks for special case as described in JVM spec.)
1732 // returns idivq instruction offset for implicit exception handling
1733 int corrected_idivq(Register reg);
1734
1735 void int3();
1736
1737 // Long operation macros for a 32bit cpu
1738 // Long negation for Java
1739 void lneg(Register hi, Register lo);
1740
1741 // Long multiplication for Java
1742 // (destroys contents of eax, ebx, ecx and edx)
1743 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1744
1745 // Long shifts for Java
1746 // (semantics as described in JVM spec.)
1747 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1748 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1749
1750 // Long compare for Java
1751 // (semantics as described in JVM spec.)
1752 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1753
1754
1755 // misc
1756
1757 // Sign extension
1758 void sign_extend_short(Register reg);
1759 void sign_extend_byte(Register reg);
1760
1761 // Division by power of 2, rounding towards 0
1762 void division_with_shift(Register reg, int shift_value);
1763
1764 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1765 //
1766 // CF (corresponds to C0) if x < y
1767 // PF (corresponds to C2) if unordered
1768 // ZF (corresponds to C3) if x = y
1769 //
1770 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1771 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1772 void fcmp(Register tmp);
1773 // Variant of the above which allows y to be further down the stack
1774 // and which only pops x and y if specified. If pop_right is
1775 // specified then pop_left must also be specified.
1776 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1777
1778 // Floating-point comparison for Java
1779 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1780 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1781 // (semantics as described in JVM spec.)
1782 void fcmp2int(Register dst, bool unordered_is_less);
1783 // Variant of the above which allows y to be further down the stack
1784 // and which only pops x and y if specified. If pop_right is
1785 // specified then pop_left must also be specified.
1786 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1787
1788 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1789 // tmp is a temporary register, if none is available use noreg
1790 void fremr(Register tmp);
1791
1792
1793 // same as fcmp2int, but using SSE2
1794 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1795 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1796
1797 // Inlined sin/cos generator for Java; must not use CPU instruction
1798 // directly on Intel as it does not have high enough precision
1799 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1800 // number of FPU stack slots in use; all but the topmost will
1801 // require saving if a slow case is necessary. Assumes argument is
1802 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1803 // this code.
1804 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1805
1806 // branch to L if FPU flag C2 is set/not set
1807 // tmp is a temporary register, if none is available use noreg
1808 void jC2 (Register tmp, Label& L);
1809 void jnC2(Register tmp, Label& L);
1810
1811 // Pop ST (ffree & fincstp combined)
1812 void fpop();
1813
1814 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1815 void push_fTOS();
1816
1817 // pops double TOS element from CPU stack and pushes on FPU stack
1818 void pop_fTOS();
1819
1820 void empty_FPU_stack();
1821
1822 void push_IU_state();
1823 void pop_IU_state();
1824
1825 void push_FPU_state();
1826 void pop_FPU_state();
1827
1828 void push_CPU_state();
1829 void pop_CPU_state();
1830
1831 // Round up to a power of two
1832 void round_to(Register reg, int modulus);
1833
1834 // Callee saved registers handling
1835 void push_callee_saved_registers();
1836 void pop_callee_saved_registers();
1837
1838 // allocation
1839 void eden_allocate(
1840 Register obj, // result: pointer to object after successful allocation
1841 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1842 int con_size_in_bytes, // object size in bytes if known at compile time
1843 Register t1, // temp register
1844 Label& slow_case // continuation point if fast allocation fails
1845 );
1846 void tlab_allocate(
1847 Register obj, // result: pointer to object after successful allocation
1848 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1849 int con_size_in_bytes, // object size in bytes if known at compile time
1850 Register t1, // temp register
1851 Register t2, // temp register
1852 Label& slow_case // continuation point if fast allocation fails
1853 );
1854 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1855
1856 // interface method calling
1857 void lookup_interface_method(Register recv_klass,
1858 Register intf_klass,
1859 RegisterOrConstant itable_index,
1860 Register method_result,
1861 Register scan_temp,
1862 Label& no_such_interface);
1863
1864 // Test sub_klass against super_klass, with fast and slow paths.
1865
1866 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1867 // One of the three labels can be NULL, meaning take the fall-through.
1868 // If super_check_offset is -1, the value is loaded up from super_klass.
1869 // No registers are killed, except temp_reg.
1870 void check_klass_subtype_fast_path(Register sub_klass,
1871 Register super_klass,
1872 Register temp_reg,
1873 Label* L_success,
1874 Label* L_failure,
1875 Label* L_slow_path,
1876 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1877
1878 // The rest of the type check; must be wired to a corresponding fast path.
1879 // It does not repeat the fast path logic, so don't use it standalone.
1880 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1881 // Updates the sub's secondary super cache as necessary.
1882 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1883 void check_klass_subtype_slow_path(Register sub_klass,
1884 Register super_klass,
1885 Register temp_reg,
1886 Register temp2_reg,
1887 Label* L_success,
1888 Label* L_failure,
1889 bool set_cond_codes = false);
1890
1891 // Simplified, combined version, good for typical uses.
1892 // Falls through on failure.
1893 void check_klass_subtype(Register sub_klass,
1894 Register super_klass,
1895 Register temp_reg,
1896 Label& L_success);
1897
1898 // method handles (JSR 292)
1899 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1900 Register temp_reg,
1901 Label& wrong_method_type);
1902 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1903 Register temp_reg);
1904 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1905 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1906
1907
1908 //----
1909 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1910
1911 // Debugging
1912
1913 // only if +VerifyOops
1914 void verify_oop(Register reg, const char* s = "broken oop");
1915 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1916
1917 // only if +VerifyFPU
1918 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1919
1920 // prints msg, dumps registers and stops execution
1921 void stop(const char* msg);
1922
1923 // prints msg and continues
1924 void warn(const char* msg);
1925
1926 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1927 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1928
1929 void os_breakpoint();
1930
1931 void untested() { stop("untested"); }
1932
1933 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1934
1935 void should_not_reach_here() { stop("should not reach here"); }
1936
1937 void print_CPU_state();
1938
1939 // Stack overflow checking
1940 void bang_stack_with_offset(int offset) {
1941 // stack grows down, caller passes positive offset
1942 assert(offset > 0, "must bang with negative offset");
1943 movl(Address(rsp, (-offset)), rax);
1944 }
1945
1946 // Writes to stack successive pages until offset reached to check for
1947 // stack overflow + shadow pages. Also, clobbers tmp
1948 void bang_stack_size(Register size, Register tmp);
1949
1950 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1951 Register tmp,
1952 int offset);
1953
1954 // Support for serializing memory accesses between threads
1955 void serialize_memory(Register thread, Register tmp);
1956
1957 void verify_tlab();
1958
1959 // Biased locking support
1960 // lock_reg and obj_reg must be loaded up with the appropriate values.
1961 // swap_reg must be rax, and is killed.
1962 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1963 // be killed; if not supplied, push/pop will be used internally to
1964 // allocate a temporary (inefficient, avoid if possible).
1965 // Optional slow case is for implementations (interpreter and C1) which branch to
1966 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1967 // Returns offset of first potentially-faulting instruction for null
1968 // check info (currently consumed only by C1). If
1969 // swap_reg_contains_mark is true then returns -1 as it is assumed
1970 // the calling code has already passed any potential faults.
1971 int biased_locking_enter(Register lock_reg, Register obj_reg,
1972 Register swap_reg, Register tmp_reg,
1973 bool swap_reg_contains_mark,
1974 Label& done, Label* slow_case = NULL,
1975 BiasedLockingCounters* counters = NULL);
1976 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1977
1978
1979 Condition negate_condition(Condition cond);
1980
1981 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1982 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1983 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1984 // here in MacroAssembler. The major exception to this rule is call
1985
1986 // Arithmetics
1987
1988
1989 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1990 void addptr(Address dst, Register src);
1991
1992 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1993 void addptr(Register dst, int32_t src);
1994 void addptr(Register dst, Register src);
1995
1996 void andptr(Register dst, int32_t src);
1997 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1998
1999 void cmp8(AddressLiteral src1, int imm);
2000
2001 // renamed to drag out the casting of address to int32_t/intptr_t
2002 void cmp32(Register src1, int32_t imm);
2003
2004 void cmp32(AddressLiteral src1, int32_t imm);
2005 // compare reg - mem, or reg - &mem
2006 void cmp32(Register src1, AddressLiteral src2);
2007
2008 void cmp32(Register src1, Address src2);
2009
2010 #ifndef _LP64
2011 void cmpoop(Address dst, jobject obj);
2012 void cmpoop(Register dst, jobject obj);
2013 #endif // _LP64
2014
2015 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2016 void cmpptr(Address src1, AddressLiteral src2);
2017
2018 void cmpptr(Register src1, AddressLiteral src2);
2019
2020 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2021 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2022 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2023
2024 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2025 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2026
2027 // cmp64 to avoild hiding cmpq
2028 void cmp64(Register src1, AddressLiteral src);
2029
2030 void cmpxchgptr(Register reg, Address adr);
2031
2032 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2033
2034
2035 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2036
2037
2038 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2039
2040 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2041
2042 void shlptr(Register dst, int32_t shift);
2043 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2044
2045 void shrptr(Register dst, int32_t shift);
2046 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2047
2048 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2049 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2050
2051 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2052
2053 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2054 void subptr(Register dst, int32_t src);
2055 void subptr(Register dst, Register src);
2056
2057
2058 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2059 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2060
2061 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2062 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2063
2064 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2065
2066
2067
2068 // Helper functions for statistics gathering.
2069 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2070 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2071 // Unconditional atomic increment.
2072 void atomic_incl(AddressLiteral counter_addr);
2073
2074 void lea(Register dst, AddressLiteral adr);
2075 void lea(Address dst, AddressLiteral adr);
2076 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2077
2078 void leal32(Register dst, Address src) { leal(dst, src); }
2079
2080 void test32(Register src1, AddressLiteral src2);
2081
2082 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2083 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2084 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2085
2086 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2087 void testptr(Register src1, Register src2);
2088
2089 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2090 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2091
2092 // Calls
2093
2094 void call(Label& L, relocInfo::relocType rtype);
2095 void call(Register entry);
2096
2097 // NOTE: this call tranfers to the effective address of entry NOT
2098 // the address contained by entry. This is because this is more natural
2099 // for jumps/calls.
2100 void call(AddressLiteral entry);
2101
2102 // Jumps
2103
2104 // NOTE: these jumps tranfer to the effective address of dst NOT
2105 // the address contained by dst. This is because this is more natural
2106 // for jumps/calls.
2107 void jump(AddressLiteral dst);
2108 void jump_cc(Condition cc, AddressLiteral dst);
2109
2110 // 32bit can do a case table jump in one instruction but we no longer allow the base
2111 // to be installed in the Address class. This jump will tranfers to the address
2112 // contained in the location described by entry (not the address of entry)
2113 void jump(ArrayAddress entry);
2114
2115 // Floating
2116
2117 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2118 void andpd(XMMRegister dst, AddressLiteral src);
2119
2120 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2121 void comiss(XMMRegister dst, AddressLiteral src);
2122
2123 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2124 void comisd(XMMRegister dst, AddressLiteral src);
2125
2126 void fldcw(Address src) { Assembler::fldcw(src); }
2127 void fldcw(AddressLiteral src);
2128
2129 void fld_s(int index) { Assembler::fld_s(index); }
2130 void fld_s(Address src) { Assembler::fld_s(src); }
2131 void fld_s(AddressLiteral src);
2132
2133 void fld_d(Address src) { Assembler::fld_d(src); }
2134 void fld_d(AddressLiteral src);
2135
2136 void fld_x(Address src) { Assembler::fld_x(src); }
2137 void fld_x(AddressLiteral src);
2138
2139 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2140 void ldmxcsr(AddressLiteral src);
2141
2142 private:
2143 // these are private because users should be doing movflt/movdbl
2144
2145 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2146 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2147 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2148 void movss(XMMRegister dst, AddressLiteral src);
2149
2150 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2151 void movlpd(XMMRegister dst, AddressLiteral src);
2152
2153 public:
2154
2155 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2156 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2157 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2158 void movsd(XMMRegister dst, AddressLiteral src);
2159
2160 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2161 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2162 void ucomiss(XMMRegister dst, AddressLiteral src);
2163
2164 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2165 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2166 void ucomisd(XMMRegister dst, AddressLiteral src);
2167
2168 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2169 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2170 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2171 void xorpd(XMMRegister dst, AddressLiteral src);
2172
2173 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2174 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2175 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2176 void xorps(XMMRegister dst, AddressLiteral src);
2177
2178 // Data
2179
2180 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2181
2182 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2183 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2184
2185 void movoop(Register dst, jobject obj);
2186 void movoop(Address dst, jobject obj);
2187
2188 void movptr(ArrayAddress dst, Register src);
2189 // can this do an lea?
2190 void movptr(Register dst, ArrayAddress src);
2191
2192 void movptr(Register dst, Address src);
2193
2194 void movptr(Register dst, AddressLiteral src);
2195
2196 void movptr(Register dst, intptr_t src);
2197 void movptr(Register dst, Register src);
2198 void movptr(Address dst, intptr_t src);
2199
2200 void movptr(Address dst, Register src);
2201
2202 #ifdef _LP64
2203 // Generally the next two are only used for moving NULL
2204 // Although there are situations in initializing the mark word where
2205 // they could be used. They are dangerous.
2206
2207 // They only exist on LP64 so that int32_t and intptr_t are not the same
2208 // and we have ambiguous declarations.
2209
2210 void movptr(Address dst, int32_t imm32);
2211 void movptr(Register dst, int32_t imm32);
2212 #endif // _LP64
2213
2214 // to avoid hiding movl
2215 void mov32(AddressLiteral dst, Register src);
2216 void mov32(Register dst, AddressLiteral src);
2217
2218 // to avoid hiding movb
2219 void movbyte(ArrayAddress dst, int src);
2220
2221 // Can push value or effective address
2222 void pushptr(AddressLiteral src);
2223
2224 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2225 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2226
2227 void pushoop(jobject obj);
2228
2229 // sign extend as need a l to ptr sized element
2230 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2231 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2232
2233 // IndexOf strings.
2234 void string_indexof(Register str1, Register str2,
2235 Register cnt1, Register cnt2, Register result,
2236 XMMRegister vec, Register tmp);
2237
2238 // Compare strings.
2239 void string_compare(Register str1, Register str2,
2240 Register cnt1, Register cnt2, Register result,
2241 XMMRegister vec1, XMMRegister vec2);
2242
2243 // Compare char[] arrays.
2244 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2245 Register limit, Register result, Register chr,
2246 XMMRegister vec1, XMMRegister vec2);
2247
2248 // Fill primitive arrays
2249 void generate_fill(BasicType t, bool aligned,
2250 Register to, Register value, Register count,
2251 Register rtmp, XMMRegister xtmp);
2252
2253 #undef VIRTUAL
2254
2255 };
2256
2257 /**
2258 * class SkipIfEqual:
2259 *
2260 * Instantiating this class will result in assembly code being output that will
2261 * jump around any code emitted between the creation of the instance and it's
2262 * automatic destruction at the end of a scope block, depending on the value of
2263 * the flag passed to the constructor, which will be checked at run-time.
2264 */
2265 class SkipIfEqual {
2266 private:
2267 MacroAssembler* _masm;
2268 Label _label;
2269
2270 public:
2271 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2272 ~SkipIfEqual();
2273 };
2274
2275 #ifdef ASSERT
2276 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2277 #endif
2278
2279 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP