1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_matcher.cpp.incl"
27
28 OptoReg::Name OptoReg::c_frame_pointer;
29
30
31
32 const int Matcher::base2reg[Type::lastype] = {
33 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
34 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
35 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
36 0, 0/*abio*/,
37 Op_RegP /* Return address */, 0, /* the memories */
38 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
39 0 /*bottom*/
40 };
41
42 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
43 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
44 RegMask Matcher::STACK_ONLY_mask;
45 RegMask Matcher::c_frame_ptr_mask;
46 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
47 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
48
49 //---------------------------Matcher-------------------------------------------
50 Matcher::Matcher( Node_List &proj_list ) :
51 PhaseTransform( Phase::Ins_Select ),
52 #ifdef ASSERT
53 _old2new_map(C->comp_arena()),
54 _new2old_map(C->comp_arena()),
55 #endif
56 _shared_nodes(C->comp_arena()),
57 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
58 _swallowed(swallowed),
59 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
60 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
61 _must_clone(must_clone), _proj_list(proj_list),
62 _register_save_policy(register_save_policy),
63 _c_reg_save_policy(c_reg_save_policy),
64 _register_save_type(register_save_type),
65 _ruleName(ruleName),
66 _allocation_started(false),
67 _states_arena(Chunk::medium_size),
68 _visited(&_states_arena),
69 _shared(&_states_arena),
70 _dontcare(&_states_arena) {
71 C->set_matcher(this);
72
73 idealreg2spillmask [Op_RegI] = NULL;
74 idealreg2spillmask [Op_RegN] = NULL;
75 idealreg2spillmask [Op_RegL] = NULL;
76 idealreg2spillmask [Op_RegF] = NULL;
77 idealreg2spillmask [Op_RegD] = NULL;
78 idealreg2spillmask [Op_RegP] = NULL;
79
80 idealreg2debugmask [Op_RegI] = NULL;
81 idealreg2debugmask [Op_RegN] = NULL;
82 idealreg2debugmask [Op_RegL] = NULL;
83 idealreg2debugmask [Op_RegF] = NULL;
84 idealreg2debugmask [Op_RegD] = NULL;
85 idealreg2debugmask [Op_RegP] = NULL;
86
87 idealreg2mhdebugmask[Op_RegI] = NULL;
88 idealreg2mhdebugmask[Op_RegN] = NULL;
89 idealreg2mhdebugmask[Op_RegL] = NULL;
90 idealreg2mhdebugmask[Op_RegF] = NULL;
91 idealreg2mhdebugmask[Op_RegD] = NULL;
92 idealreg2mhdebugmask[Op_RegP] = NULL;
93
94 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
95 }
96
97 //------------------------------warp_incoming_stk_arg------------------------
98 // This warps a VMReg into an OptoReg::Name
99 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
100 OptoReg::Name warped;
101 if( reg->is_stack() ) { // Stack slot argument?
102 warped = OptoReg::add(_old_SP, reg->reg2stack() );
103 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
104 if( warped >= _in_arg_limit )
105 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
106 if (!RegMask::can_represent(warped)) {
107 // the compiler cannot represent this method's calling sequence
108 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
109 return OptoReg::Bad;
110 }
111 return warped;
112 }
113 return OptoReg::as_OptoReg(reg);
114 }
115
116 //---------------------------compute_old_SP------------------------------------
117 OptoReg::Name Compile::compute_old_SP() {
118 int fixed = fixed_slots();
119 int preserve = in_preserve_stack_slots();
120 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
121 }
122
123
124
125 #ifdef ASSERT
126 void Matcher::verify_new_nodes_only(Node* xroot) {
127 // Make sure that the new graph only references new nodes
128 ResourceMark rm;
129 Unique_Node_List worklist;
130 VectorSet visited(Thread::current()->resource_area());
131 worklist.push(xroot);
132 while (worklist.size() > 0) {
133 Node* n = worklist.pop();
134 visited <<= n->_idx;
135 assert(C->node_arena()->contains(n), "dead node");
136 for (uint j = 0; j < n->req(); j++) {
137 Node* in = n->in(j);
138 if (in != NULL) {
139 assert(C->node_arena()->contains(in), "dead node");
140 if (!visited.test(in->_idx)) {
141 worklist.push(in);
142 }
143 }
144 }
145 }
146 }
147 #endif
148
149
150 //---------------------------match---------------------------------------------
151 void Matcher::match( ) {
152 if( MaxLabelRootDepth < 100 ) { // Too small?
153 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
154 MaxLabelRootDepth = 100;
155 }
156 // One-time initialization of some register masks.
157 init_spill_mask( C->root()->in(1) );
158 _return_addr_mask = return_addr();
159 #ifdef _LP64
160 // Pointers take 2 slots in 64-bit land
161 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
162 #endif
163
164 // Map a Java-signature return type into return register-value
165 // machine registers for 0, 1 and 2 returned values.
166 const TypeTuple *range = C->tf()->range();
167 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
168 // Get ideal-register return type
169 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
170 // Get machine return register
171 uint sop = C->start()->Opcode();
172 OptoRegPair regs = return_value(ireg, false);
173
174 // And mask for same
175 _return_value_mask = RegMask(regs.first());
176 if( OptoReg::is_valid(regs.second()) )
177 _return_value_mask.Insert(regs.second());
178 }
179
180 // ---------------
181 // Frame Layout
182
183 // Need the method signature to determine the incoming argument types,
184 // because the types determine which registers the incoming arguments are
185 // in, and this affects the matched code.
186 const TypeTuple *domain = C->tf()->domain();
187 uint argcnt = domain->cnt() - TypeFunc::Parms;
188 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
189 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
190 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
191 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
192 uint i;
193 for( i = 0; i<argcnt; i++ ) {
194 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
195 }
196
197 // Pass array of ideal registers and length to USER code (from the AD file)
198 // that will convert this to an array of register numbers.
199 const StartNode *start = C->start();
200 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
201 #ifdef ASSERT
202 // Sanity check users' calling convention. Real handy while trying to
203 // get the initial port correct.
204 { for (uint i = 0; i<argcnt; i++) {
205 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
206 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
207 _parm_regs[i].set_bad();
208 continue;
209 }
210 VMReg parm_reg = vm_parm_regs[i].first();
211 assert(parm_reg->is_valid(), "invalid arg?");
212 if (parm_reg->is_reg()) {
213 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
214 assert(can_be_java_arg(opto_parm_reg) ||
215 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
216 opto_parm_reg == inline_cache_reg(),
217 "parameters in register must be preserved by runtime stubs");
218 }
219 for (uint j = 0; j < i; j++) {
220 assert(parm_reg != vm_parm_regs[j].first(),
221 "calling conv. must produce distinct regs");
222 }
223 }
224 }
225 #endif
226
227 // Do some initial frame layout.
228
229 // Compute the old incoming SP (may be called FP) as
230 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
231 _old_SP = C->compute_old_SP();
232 assert( is_even(_old_SP), "must be even" );
233
234 // Compute highest incoming stack argument as
235 // _old_SP + out_preserve_stack_slots + incoming argument size.
236 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
237 assert( is_even(_in_arg_limit), "out_preserve must be even" );
238 for( i = 0; i < argcnt; i++ ) {
239 // Permit args to have no register
240 _calling_convention_mask[i].Clear();
241 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
242 continue;
243 }
244 // calling_convention returns stack arguments as a count of
245 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
246 // the allocators point of view, taking into account all the
247 // preserve area, locks & pad2.
248
249 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
250 if( OptoReg::is_valid(reg1))
251 _calling_convention_mask[i].Insert(reg1);
252
253 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
254 if( OptoReg::is_valid(reg2))
255 _calling_convention_mask[i].Insert(reg2);
256
257 // Saved biased stack-slot register number
258 _parm_regs[i].set_pair(reg2, reg1);
259 }
260
261 // Finally, make sure the incoming arguments take up an even number of
262 // words, in case the arguments or locals need to contain doubleword stack
263 // slots. The rest of the system assumes that stack slot pairs (in
264 // particular, in the spill area) which look aligned will in fact be
265 // aligned relative to the stack pointer in the target machine. Double
266 // stack slots will always be allocated aligned.
267 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
268
269 // Compute highest outgoing stack argument as
270 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
271 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
272 assert( is_even(_out_arg_limit), "out_preserve must be even" );
273
274 if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) {
275 // the compiler cannot represent this method's calling sequence
276 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
277 }
278
279 if (C->failing()) return; // bailed out on incoming arg failure
280
281 // ---------------
282 // Collect roots of matcher trees. Every node for which
283 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
284 // can be a valid interior of some tree.
285 find_shared( C->root() );
286 find_shared( C->top() );
287
288 C->print_method("Before Matching");
289
290 // Create new ideal node ConP #NULL even if it does exist in old space
291 // to avoid false sharing if the corresponding mach node is not used.
292 // The corresponding mach node is only used in rare cases for derived
293 // pointers.
294 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
295
296 // Swap out to old-space; emptying new-space
297 Arena *old = C->node_arena()->move_contents(C->old_arena());
298
299 // Save debug and profile information for nodes in old space:
300 _old_node_note_array = C->node_note_array();
301 if (_old_node_note_array != NULL) {
302 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
303 (C->comp_arena(), _old_node_note_array->length(),
304 0, NULL));
305 }
306
307 // Pre-size the new_node table to avoid the need for range checks.
308 grow_new_node_array(C->unique());
309
310 // Reset node counter so MachNodes start with _idx at 0
311 int nodes = C->unique(); // save value
312 C->set_unique(0);
313
314 // Recursively match trees from old space into new space.
315 // Correct leaves of new-space Nodes; they point to old-space.
316 _visited.Clear(); // Clear visit bits for xform call
317 C->set_cached_top_node(xform( C->top(), nodes ));
318 if (!C->failing()) {
319 Node* xroot = xform( C->root(), 1 );
320 if (xroot == NULL) {
321 Matcher::soft_match_failure(); // recursive matching process failed
322 C->record_method_not_compilable("instruction match failed");
323 } else {
324 // During matching shared constants were attached to C->root()
325 // because xroot wasn't available yet, so transfer the uses to
326 // the xroot.
327 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
328 Node* n = C->root()->fast_out(j);
329 if (C->node_arena()->contains(n)) {
330 assert(n->in(0) == C->root(), "should be control user");
331 n->set_req(0, xroot);
332 --j;
333 --jmax;
334 }
335 }
336
337 // Generate new mach node for ConP #NULL
338 assert(new_ideal_null != NULL, "sanity");
339 _mach_null = match_tree(new_ideal_null);
340 // Don't set control, it will confuse GCM since there are no uses.
341 // The control will be set when this node is used first time
342 // in find_base_for_derived().
343 assert(_mach_null != NULL, "");
344
345 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
346
347 #ifdef ASSERT
348 verify_new_nodes_only(xroot);
349 #endif
350 }
351 }
352 if (C->top() == NULL || C->root() == NULL) {
353 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
354 }
355 if (C->failing()) {
356 // delete old;
357 old->destruct_contents();
358 return;
359 }
360 assert( C->top(), "" );
361 assert( C->root(), "" );
362 validate_null_checks();
363
364 // Now smoke old-space
365 NOT_DEBUG( old->destruct_contents() );
366
367 // ------------------------
368 // Set up save-on-entry registers
369 Fixup_Save_On_Entry( );
370 }
371
372
373 //------------------------------Fixup_Save_On_Entry----------------------------
374 // The stated purpose of this routine is to take care of save-on-entry
375 // registers. However, the overall goal of the Match phase is to convert into
376 // machine-specific instructions which have RegMasks to guide allocation.
377 // So what this procedure really does is put a valid RegMask on each input
378 // to the machine-specific variations of all Return, TailCall and Halt
379 // instructions. It also adds edgs to define the save-on-entry values (and of
380 // course gives them a mask).
381
382 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
383 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
384 // Do all the pre-defined register masks
385 rms[TypeFunc::Control ] = RegMask::Empty;
386 rms[TypeFunc::I_O ] = RegMask::Empty;
387 rms[TypeFunc::Memory ] = RegMask::Empty;
388 rms[TypeFunc::ReturnAdr] = ret_adr;
389 rms[TypeFunc::FramePtr ] = fp;
390 return rms;
391 }
392
393 //---------------------------init_first_stack_mask-----------------------------
394 // Create the initial stack mask used by values spilling to the stack.
395 // Disallow any debug info in outgoing argument areas by setting the
396 // initial mask accordingly.
397 void Matcher::init_first_stack_mask() {
398
399 // Allocate storage for spill masks as masks for the appropriate load type.
400 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * 3*6);
401
402 idealreg2spillmask [Op_RegN] = &rms[0];
403 idealreg2spillmask [Op_RegI] = &rms[1];
404 idealreg2spillmask [Op_RegL] = &rms[2];
405 idealreg2spillmask [Op_RegF] = &rms[3];
406 idealreg2spillmask [Op_RegD] = &rms[4];
407 idealreg2spillmask [Op_RegP] = &rms[5];
408
409 idealreg2debugmask [Op_RegN] = &rms[6];
410 idealreg2debugmask [Op_RegI] = &rms[7];
411 idealreg2debugmask [Op_RegL] = &rms[8];
412 idealreg2debugmask [Op_RegF] = &rms[9];
413 idealreg2debugmask [Op_RegD] = &rms[10];
414 idealreg2debugmask [Op_RegP] = &rms[11];
415
416 idealreg2mhdebugmask[Op_RegN] = &rms[12];
417 idealreg2mhdebugmask[Op_RegI] = &rms[13];
418 idealreg2mhdebugmask[Op_RegL] = &rms[14];
419 idealreg2mhdebugmask[Op_RegF] = &rms[15];
420 idealreg2mhdebugmask[Op_RegD] = &rms[16];
421 idealreg2mhdebugmask[Op_RegP] = &rms[17];
422
423 OptoReg::Name i;
424
425 // At first, start with the empty mask
426 C->FIRST_STACK_mask().Clear();
427
428 // Add in the incoming argument area
429 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
430 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
431 C->FIRST_STACK_mask().Insert(i);
432
433 // Add in all bits past the outgoing argument area
434 guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)),
435 "must be able to represent all call arguments in reg mask");
436 init = _out_arg_limit;
437 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
438 C->FIRST_STACK_mask().Insert(i);
439
440 // Finally, set the "infinite stack" bit.
441 C->FIRST_STACK_mask().set_AllStack();
442
443 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
444 #ifdef _LP64
445 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
446 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
447 #endif
448 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
449 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
450 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
451 idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask());
452 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
453 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
454 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
455 idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask());
456 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
457 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
458
459 if (UseFPUForSpilling) {
460 // This mask logic assumes that the spill operations are
461 // symmetric and that the registers involved are the same size.
462 // On sparc for instance we may have to use 64 bit moves will
463 // kill 2 registers when used with F0-F31.
464 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
465 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
466 #ifdef _LP64
467 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
468 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
469 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
470 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
471 #else
472 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
473 #endif
474 }
475
476 // Make up debug masks. Any spill slot plus callee-save registers.
477 // Caller-save registers are assumed to be trashable by the various
478 // inline-cache fixup routines.
479 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
480 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
481 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
482 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
483 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
484 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
485
486 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
487 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
488 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
489 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
490 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
491 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
492
493 // Prevent stub compilations from attempting to reference
494 // callee-saved registers from debug info
495 bool exclude_soe = !Compile::current()->is_method_compilation();
496
497 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
498 // registers the caller has to save do not work
499 if( _register_save_policy[i] == 'C' ||
500 _register_save_policy[i] == 'A' ||
501 (_register_save_policy[i] == 'E' && exclude_soe) ) {
502 idealreg2debugmask [Op_RegN]->Remove(i);
503 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
504 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
505 idealreg2debugmask [Op_RegF]->Remove(i); // masks
506 idealreg2debugmask [Op_RegD]->Remove(i);
507 idealreg2debugmask [Op_RegP]->Remove(i);
508
509 idealreg2mhdebugmask[Op_RegN]->Remove(i);
510 idealreg2mhdebugmask[Op_RegI]->Remove(i);
511 idealreg2mhdebugmask[Op_RegL]->Remove(i);
512 idealreg2mhdebugmask[Op_RegF]->Remove(i);
513 idealreg2mhdebugmask[Op_RegD]->Remove(i);
514 idealreg2mhdebugmask[Op_RegP]->Remove(i);
515 }
516 }
517
518 // Subtract the register we use to save the SP for MethodHandle
519 // invokes to from the debug mask.
520 const RegMask save_mask = method_handle_invoke_SP_save_mask();
521 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
522 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
523 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
524 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
525 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
526 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
527 }
528
529 //---------------------------is_save_on_entry----------------------------------
530 bool Matcher::is_save_on_entry( int reg ) {
531 return
532 _register_save_policy[reg] == 'E' ||
533 _register_save_policy[reg] == 'A' || // Save-on-entry register?
534 // Also save argument registers in the trampolining stubs
535 (C->save_argument_registers() && is_spillable_arg(reg));
536 }
537
538 //---------------------------Fixup_Save_On_Entry-------------------------------
539 void Matcher::Fixup_Save_On_Entry( ) {
540 init_first_stack_mask();
541
542 Node *root = C->root(); // Short name for root
543 // Count number of save-on-entry registers.
544 uint soe_cnt = number_of_saved_registers();
545 uint i;
546
547 // Find the procedure Start Node
548 StartNode *start = C->start();
549 assert( start, "Expect a start node" );
550
551 // Save argument registers in the trampolining stubs
552 if( C->save_argument_registers() )
553 for( i = 0; i < _last_Mach_Reg; i++ )
554 if( is_spillable_arg(i) )
555 soe_cnt++;
556
557 // Input RegMask array shared by all Returns.
558 // The type for doubles and longs has a count of 2, but
559 // there is only 1 returned value
560 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
561 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
562 // Returns have 0 or 1 returned values depending on call signature.
563 // Return register is specified by return_value in the AD file.
564 if (ret_edge_cnt > TypeFunc::Parms)
565 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
566
567 // Input RegMask array shared by all Rethrows.
568 uint reth_edge_cnt = TypeFunc::Parms+1;
569 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
570 // Rethrow takes exception oop only, but in the argument 0 slot.
571 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
572 #ifdef _LP64
573 // Need two slots for ptrs in 64-bit land
574 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
575 #endif
576
577 // Input RegMask array shared by all TailCalls
578 uint tail_call_edge_cnt = TypeFunc::Parms+2;
579 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
580
581 // Input RegMask array shared by all TailJumps
582 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
583 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
584
585 // TailCalls have 2 returned values (target & moop), whose masks come
586 // from the usual MachNode/MachOper mechanism. Find a sample
587 // TailCall to extract these masks and put the correct masks into
588 // the tail_call_rms array.
589 for( i=1; i < root->req(); i++ ) {
590 MachReturnNode *m = root->in(i)->as_MachReturn();
591 if( m->ideal_Opcode() == Op_TailCall ) {
592 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
593 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
594 break;
595 }
596 }
597
598 // TailJumps have 2 returned values (target & ex_oop), whose masks come
599 // from the usual MachNode/MachOper mechanism. Find a sample
600 // TailJump to extract these masks and put the correct masks into
601 // the tail_jump_rms array.
602 for( i=1; i < root->req(); i++ ) {
603 MachReturnNode *m = root->in(i)->as_MachReturn();
604 if( m->ideal_Opcode() == Op_TailJump ) {
605 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
606 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
607 break;
608 }
609 }
610
611 // Input RegMask array shared by all Halts
612 uint halt_edge_cnt = TypeFunc::Parms;
613 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
614
615 // Capture the return input masks into each exit flavor
616 for( i=1; i < root->req(); i++ ) {
617 MachReturnNode *exit = root->in(i)->as_MachReturn();
618 switch( exit->ideal_Opcode() ) {
619 case Op_Return : exit->_in_rms = ret_rms; break;
620 case Op_Rethrow : exit->_in_rms = reth_rms; break;
621 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
622 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
623 case Op_Halt : exit->_in_rms = halt_rms; break;
624 default : ShouldNotReachHere();
625 }
626 }
627
628 // Next unused projection number from Start.
629 int proj_cnt = C->tf()->domain()->cnt();
630
631 // Do all the save-on-entry registers. Make projections from Start for
632 // them, and give them a use at the exit points. To the allocator, they
633 // look like incoming register arguments.
634 for( i = 0; i < _last_Mach_Reg; i++ ) {
635 if( is_save_on_entry(i) ) {
636
637 // Add the save-on-entry to the mask array
638 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
639 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
640 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
641 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
642 // Halts need the SOE registers, but only in the stack as debug info.
643 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
644 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
645
646 Node *mproj;
647
648 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
649 // into a single RegD.
650 if( (i&1) == 0 &&
651 _register_save_type[i ] == Op_RegF &&
652 _register_save_type[i+1] == Op_RegF &&
653 is_save_on_entry(i+1) ) {
654 // Add other bit for double
655 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
656 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
657 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
658 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
659 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
660 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
661 proj_cnt += 2; // Skip 2 for doubles
662 }
663 else if( (i&1) == 1 && // Else check for high half of double
664 _register_save_type[i-1] == Op_RegF &&
665 _register_save_type[i ] == Op_RegF &&
666 is_save_on_entry(i-1) ) {
667 ret_rms [ ret_edge_cnt] = RegMask::Empty;
668 reth_rms [ reth_edge_cnt] = RegMask::Empty;
669 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
670 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
671 halt_rms [ halt_edge_cnt] = RegMask::Empty;
672 mproj = C->top();
673 }
674 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
675 // into a single RegL.
676 else if( (i&1) == 0 &&
677 _register_save_type[i ] == Op_RegI &&
678 _register_save_type[i+1] == Op_RegI &&
679 is_save_on_entry(i+1) ) {
680 // Add other bit for long
681 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
682 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
683 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
684 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
685 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
686 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
687 proj_cnt += 2; // Skip 2 for longs
688 }
689 else if( (i&1) == 1 && // Else check for high half of long
690 _register_save_type[i-1] == Op_RegI &&
691 _register_save_type[i ] == Op_RegI &&
692 is_save_on_entry(i-1) ) {
693 ret_rms [ ret_edge_cnt] = RegMask::Empty;
694 reth_rms [ reth_edge_cnt] = RegMask::Empty;
695 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
696 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
697 halt_rms [ halt_edge_cnt] = RegMask::Empty;
698 mproj = C->top();
699 } else {
700 // Make a projection for it off the Start
701 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
702 }
703
704 ret_edge_cnt ++;
705 reth_edge_cnt ++;
706 tail_call_edge_cnt ++;
707 tail_jump_edge_cnt ++;
708 halt_edge_cnt ++;
709
710 // Add a use of the SOE register to all exit paths
711 for( uint j=1; j < root->req(); j++ )
712 root->in(j)->add_req(mproj);
713 } // End of if a save-on-entry register
714 } // End of for all machine registers
715 }
716
717 //------------------------------init_spill_mask--------------------------------
718 void Matcher::init_spill_mask( Node *ret ) {
719 if( idealreg2regmask[Op_RegI] ) return; // One time only init
720
721 OptoReg::c_frame_pointer = c_frame_pointer();
722 c_frame_ptr_mask = c_frame_pointer();
723 #ifdef _LP64
724 // pointers are twice as big
725 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
726 #endif
727
728 // Start at OptoReg::stack0()
729 STACK_ONLY_mask.Clear();
730 OptoReg::Name init = OptoReg::stack2reg(0);
731 // STACK_ONLY_mask is all stack bits
732 OptoReg::Name i;
733 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
734 STACK_ONLY_mask.Insert(i);
735 // Also set the "infinite stack" bit.
736 STACK_ONLY_mask.set_AllStack();
737
738 // Copy the register names over into the shared world
739 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
740 // SharedInfo::regName[i] = regName[i];
741 // Handy RegMasks per machine register
742 mreg2regmask[i].Insert(i);
743 }
744
745 // Grab the Frame Pointer
746 Node *fp = ret->in(TypeFunc::FramePtr);
747 Node *mem = ret->in(TypeFunc::Memory);
748 const TypePtr* atp = TypePtr::BOTTOM;
749 // Share frame pointer while making spill ops
750 set_shared(fp);
751
752 // Compute generic short-offset Loads
753 #ifdef _LP64
754 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
755 #endif
756 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
757 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
758 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
759 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
760 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
761 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
762 spillD != NULL && spillP != NULL, "");
763
764 // Get the ADLC notion of the right regmask, for each basic type.
765 #ifdef _LP64
766 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
767 #endif
768 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
769 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
770 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
771 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
772 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
773 }
774
775 #ifdef ASSERT
776 static void match_alias_type(Compile* C, Node* n, Node* m) {
777 if (!VerifyAliases) return; // do not go looking for trouble by default
778 const TypePtr* nat = n->adr_type();
779 const TypePtr* mat = m->adr_type();
780 int nidx = C->get_alias_index(nat);
781 int midx = C->get_alias_index(mat);
782 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
783 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
784 for (uint i = 1; i < n->req(); i++) {
785 Node* n1 = n->in(i);
786 const TypePtr* n1at = n1->adr_type();
787 if (n1at != NULL) {
788 nat = n1at;
789 nidx = C->get_alias_index(n1at);
790 }
791 }
792 }
793 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
794 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
795 switch (n->Opcode()) {
796 case Op_PrefetchRead:
797 case Op_PrefetchWrite:
798 nidx = Compile::AliasIdxRaw;
799 nat = TypeRawPtr::BOTTOM;
800 break;
801 }
802 }
803 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
804 switch (n->Opcode()) {
805 case Op_ClearArray:
806 midx = Compile::AliasIdxRaw;
807 mat = TypeRawPtr::BOTTOM;
808 break;
809 }
810 }
811 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
812 switch (n->Opcode()) {
813 case Op_Return:
814 case Op_Rethrow:
815 case Op_Halt:
816 case Op_TailCall:
817 case Op_TailJump:
818 nidx = Compile::AliasIdxBot;
819 nat = TypePtr::BOTTOM;
820 break;
821 }
822 }
823 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
824 switch (n->Opcode()) {
825 case Op_StrComp:
826 case Op_StrEquals:
827 case Op_StrIndexOf:
828 case Op_AryEq:
829 case Op_MemBarVolatile:
830 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
831 nidx = Compile::AliasIdxTop;
832 nat = NULL;
833 break;
834 }
835 }
836 if (nidx != midx) {
837 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
838 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
839 n->dump();
840 m->dump();
841 }
842 assert(C->subsume_loads() && C->must_alias(nat, midx),
843 "must not lose alias info when matching");
844 }
845 }
846 #endif
847
848
849 //------------------------------MStack-----------------------------------------
850 // State and MStack class used in xform() and find_shared() iterative methods.
851 enum Node_State { Pre_Visit, // node has to be pre-visited
852 Visit, // visit node
853 Post_Visit, // post-visit node
854 Alt_Post_Visit // alternative post-visit path
855 };
856
857 class MStack: public Node_Stack {
858 public:
859 MStack(int size) : Node_Stack(size) { }
860
861 void push(Node *n, Node_State ns) {
862 Node_Stack::push(n, (uint)ns);
863 }
864 void push(Node *n, Node_State ns, Node *parent, int indx) {
865 ++_inode_top;
866 if ((_inode_top + 1) >= _inode_max) grow();
867 _inode_top->node = parent;
868 _inode_top->indx = (uint)indx;
869 ++_inode_top;
870 _inode_top->node = n;
871 _inode_top->indx = (uint)ns;
872 }
873 Node *parent() {
874 pop();
875 return node();
876 }
877 Node_State state() const {
878 return (Node_State)index();
879 }
880 void set_state(Node_State ns) {
881 set_index((uint)ns);
882 }
883 };
884
885
886 //------------------------------xform------------------------------------------
887 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
888 // Node in new-space. Given a new-space Node, recursively walk his children.
889 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
890 Node *Matcher::xform( Node *n, int max_stack ) {
891 // Use one stack to keep both: child's node/state and parent's node/index
892 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
893 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
894
895 while (mstack.is_nonempty()) {
896 n = mstack.node(); // Leave node on stack
897 Node_State nstate = mstack.state();
898 if (nstate == Visit) {
899 mstack.set_state(Post_Visit);
900 Node *oldn = n;
901 // Old-space or new-space check
902 if (!C->node_arena()->contains(n)) {
903 // Old space!
904 Node* m;
905 if (has_new_node(n)) { // Not yet Label/Reduced
906 m = new_node(n);
907 } else {
908 if (!is_dontcare(n)) { // Matcher can match this guy
909 // Calls match special. They match alone with no children.
910 // Their children, the incoming arguments, match normally.
911 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
912 if (C->failing()) return NULL;
913 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
914 } else { // Nothing the matcher cares about
915 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
916 // Convert to machine-dependent projection
917 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
918 #ifdef ASSERT
919 _new2old_map.map(m->_idx, n);
920 #endif
921 if (m->in(0) != NULL) // m might be top
922 collect_null_checks(m, n);
923 } else { // Else just a regular 'ol guy
924 m = n->clone(); // So just clone into new-space
925 #ifdef ASSERT
926 _new2old_map.map(m->_idx, n);
927 #endif
928 // Def-Use edges will be added incrementally as Uses
929 // of this node are matched.
930 assert(m->outcnt() == 0, "no Uses of this clone yet");
931 }
932 }
933
934 set_new_node(n, m); // Map old to new
935 if (_old_node_note_array != NULL) {
936 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
937 n->_idx);
938 C->set_node_notes_at(m->_idx, nn);
939 }
940 debug_only(match_alias_type(C, n, m));
941 }
942 n = m; // n is now a new-space node
943 mstack.set_node(n);
944 }
945
946 // New space!
947 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
948
949 int i;
950 // Put precedence edges on stack first (match them last).
951 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
952 Node *m = oldn->in(i);
953 if (m == NULL) break;
954 // set -1 to call add_prec() instead of set_req() during Step1
955 mstack.push(m, Visit, n, -1);
956 }
957
958 // For constant debug info, I'd rather have unmatched constants.
959 int cnt = n->req();
960 JVMState* jvms = n->jvms();
961 int debug_cnt = jvms ? jvms->debug_start() : cnt;
962
963 // Now do only debug info. Clone constants rather than matching.
964 // Constants are represented directly in the debug info without
965 // the need for executable machine instructions.
966 // Monitor boxes are also represented directly.
967 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
968 Node *m = n->in(i); // Get input
969 int op = m->Opcode();
970 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
971 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
972 op == Op_ConF || op == Op_ConD || op == Op_ConL
973 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
974 ) {
975 m = m->clone();
976 #ifdef ASSERT
977 _new2old_map.map(m->_idx, n);
978 #endif
979 mstack.push(m, Post_Visit, n, i); // Don't need to visit
980 mstack.push(m->in(0), Visit, m, 0);
981 } else {
982 mstack.push(m, Visit, n, i);
983 }
984 }
985
986 // And now walk his children, and convert his inputs to new-space.
987 for( ; i >= 0; --i ) { // For all normal inputs do
988 Node *m = n->in(i); // Get input
989 if(m != NULL)
990 mstack.push(m, Visit, n, i);
991 }
992
993 }
994 else if (nstate == Post_Visit) {
995 // Set xformed input
996 Node *p = mstack.parent();
997 if (p != NULL) { // root doesn't have parent
998 int i = (int)mstack.index();
999 if (i >= 0)
1000 p->set_req(i, n); // required input
1001 else if (i == -1)
1002 p->add_prec(n); // precedence input
1003 else
1004 ShouldNotReachHere();
1005 }
1006 mstack.pop(); // remove processed node from stack
1007 }
1008 else {
1009 ShouldNotReachHere();
1010 }
1011 } // while (mstack.is_nonempty())
1012 return n; // Return new-space Node
1013 }
1014
1015 //------------------------------warp_outgoing_stk_arg------------------------
1016 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1017 // Convert outgoing argument location to a pre-biased stack offset
1018 if (reg->is_stack()) {
1019 OptoReg::Name warped = reg->reg2stack();
1020 // Adjust the stack slot offset to be the register number used
1021 // by the allocator.
1022 warped = OptoReg::add(begin_out_arg_area, warped);
1023 // Keep track of the largest numbered stack slot used for an arg.
1024 // Largest used slot per call-site indicates the amount of stack
1025 // that is killed by the call.
1026 if( warped >= out_arg_limit_per_call )
1027 out_arg_limit_per_call = OptoReg::add(warped,1);
1028 if (!RegMask::can_represent(warped)) {
1029 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1030 return OptoReg::Bad;
1031 }
1032 return warped;
1033 }
1034 return OptoReg::as_OptoReg(reg);
1035 }
1036
1037
1038 //------------------------------match_sfpt-------------------------------------
1039 // Helper function to match call instructions. Calls match special.
1040 // They match alone with no children. Their children, the incoming
1041 // arguments, match normally.
1042 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1043 MachSafePointNode *msfpt = NULL;
1044 MachCallNode *mcall = NULL;
1045 uint cnt;
1046 // Split out case for SafePoint vs Call
1047 CallNode *call;
1048 const TypeTuple *domain;
1049 ciMethod* method = NULL;
1050 bool is_method_handle_invoke = false; // for special kill effects
1051 if( sfpt->is_Call() ) {
1052 call = sfpt->as_Call();
1053 domain = call->tf()->domain();
1054 cnt = domain->cnt();
1055
1056 // Match just the call, nothing else
1057 MachNode *m = match_tree(call);
1058 if (C->failing()) return NULL;
1059 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1060
1061 // Copy data from the Ideal SafePoint to the machine version
1062 mcall = m->as_MachCall();
1063
1064 mcall->set_tf( call->tf());
1065 mcall->set_entry_point(call->entry_point());
1066 mcall->set_cnt( call->cnt());
1067
1068 if( mcall->is_MachCallJava() ) {
1069 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1070 const CallJavaNode *call_java = call->as_CallJava();
1071 method = call_java->method();
1072 mcall_java->_method = method;
1073 mcall_java->_bci = call_java->_bci;
1074 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1075 is_method_handle_invoke = call_java->is_method_handle_invoke();
1076 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1077 if( mcall_java->is_MachCallStaticJava() )
1078 mcall_java->as_MachCallStaticJava()->_name =
1079 call_java->as_CallStaticJava()->_name;
1080 if( mcall_java->is_MachCallDynamicJava() )
1081 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1082 call_java->as_CallDynamicJava()->_vtable_index;
1083 }
1084 else if( mcall->is_MachCallRuntime() ) {
1085 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1086 }
1087 msfpt = mcall;
1088 }
1089 // This is a non-call safepoint
1090 else {
1091 call = NULL;
1092 domain = NULL;
1093 MachNode *mn = match_tree(sfpt);
1094 if (C->failing()) return NULL;
1095 msfpt = mn->as_MachSafePoint();
1096 cnt = TypeFunc::Parms;
1097 }
1098
1099 // Advertise the correct memory effects (for anti-dependence computation).
1100 msfpt->set_adr_type(sfpt->adr_type());
1101
1102 // Allocate a private array of RegMasks. These RegMasks are not shared.
1103 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1104 // Empty them all.
1105 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1106
1107 // Do all the pre-defined non-Empty register masks
1108 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1109 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1110
1111 // Place first outgoing argument can possibly be put.
1112 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1113 assert( is_even(begin_out_arg_area), "" );
1114 // Compute max outgoing register number per call site.
1115 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1116 // Calls to C may hammer extra stack slots above and beyond any arguments.
1117 // These are usually backing store for register arguments for varargs.
1118 if( call != NULL && call->is_CallRuntime() )
1119 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1120
1121
1122 // Do the normal argument list (parameters) register masks
1123 int argcnt = cnt - TypeFunc::Parms;
1124 if( argcnt > 0 ) { // Skip it all if we have no args
1125 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1126 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1127 int i;
1128 for( i = 0; i < argcnt; i++ ) {
1129 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1130 }
1131 // V-call to pick proper calling convention
1132 call->calling_convention( sig_bt, parm_regs, argcnt );
1133
1134 #ifdef ASSERT
1135 // Sanity check users' calling convention. Really handy during
1136 // the initial porting effort. Fairly expensive otherwise.
1137 { for (int i = 0; i<argcnt; i++) {
1138 if( !parm_regs[i].first()->is_valid() &&
1139 !parm_regs[i].second()->is_valid() ) continue;
1140 VMReg reg1 = parm_regs[i].first();
1141 VMReg reg2 = parm_regs[i].second();
1142 for (int j = 0; j < i; j++) {
1143 if( !parm_regs[j].first()->is_valid() &&
1144 !parm_regs[j].second()->is_valid() ) continue;
1145 VMReg reg3 = parm_regs[j].first();
1146 VMReg reg4 = parm_regs[j].second();
1147 if( !reg1->is_valid() ) {
1148 assert( !reg2->is_valid(), "valid halvsies" );
1149 } else if( !reg3->is_valid() ) {
1150 assert( !reg4->is_valid(), "valid halvsies" );
1151 } else {
1152 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1153 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1154 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1155 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1156 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1157 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1158 }
1159 }
1160 }
1161 }
1162 #endif
1163
1164 // Visit each argument. Compute its outgoing register mask.
1165 // Return results now can have 2 bits returned.
1166 // Compute max over all outgoing arguments both per call-site
1167 // and over the entire method.
1168 for( i = 0; i < argcnt; i++ ) {
1169 // Address of incoming argument mask to fill in
1170 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1171 if( !parm_regs[i].first()->is_valid() &&
1172 !parm_regs[i].second()->is_valid() ) {
1173 continue; // Avoid Halves
1174 }
1175 // Grab first register, adjust stack slots and insert in mask.
1176 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1177 if (OptoReg::is_valid(reg1))
1178 rm->Insert( reg1 );
1179 // Grab second register (if any), adjust stack slots and insert in mask.
1180 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1181 if (OptoReg::is_valid(reg2))
1182 rm->Insert( reg2 );
1183 } // End of for all arguments
1184
1185 // Compute number of stack slots needed to restore stack in case of
1186 // Pascal-style argument popping.
1187 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1188 }
1189
1190 if (is_method_handle_invoke) {
1191 // Kill some extra stack space in case method handles want to do
1192 // a little in-place argument insertion.
1193 int regs_per_word = NOT_LP64(1) LP64_ONLY(2); // %%% make a global const!
1194 out_arg_limit_per_call += MethodHandlePushLimit * regs_per_word;
1195 // Do not update mcall->_argsize because (a) the extra space is not
1196 // pushed as arguments and (b) _argsize is dead (not used anywhere).
1197 }
1198
1199 // Compute the max stack slot killed by any call. These will not be
1200 // available for debug info, and will be used to adjust FIRST_STACK_mask
1201 // after all call sites have been visited.
1202 if( _out_arg_limit < out_arg_limit_per_call)
1203 _out_arg_limit = out_arg_limit_per_call;
1204
1205 if (mcall) {
1206 // Kill the outgoing argument area, including any non-argument holes and
1207 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1208 // Since the max-per-method covers the max-per-call-site and debug info
1209 // is excluded on the max-per-method basis, debug info cannot land in
1210 // this killed area.
1211 uint r_cnt = mcall->tf()->range()->cnt();
1212 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1213 if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) {
1214 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1215 } else {
1216 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1217 proj->_rout.Insert(OptoReg::Name(i));
1218 }
1219 if( proj->_rout.is_NotEmpty() )
1220 _proj_list.push(proj);
1221 }
1222 // Transfer the safepoint information from the call to the mcall
1223 // Move the JVMState list
1224 msfpt->set_jvms(sfpt->jvms());
1225 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1226 jvms->set_map(sfpt);
1227 }
1228
1229 // Debug inputs begin just after the last incoming parameter
1230 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1231 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1232
1233 // Move the OopMap
1234 msfpt->_oop_map = sfpt->_oop_map;
1235
1236 // Registers killed by the call are set in the local scheduling pass
1237 // of Global Code Motion.
1238 return msfpt;
1239 }
1240
1241 //---------------------------match_tree----------------------------------------
1242 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1243 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1244 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1245 // a Load's result RegMask for memoization in idealreg2regmask[]
1246 MachNode *Matcher::match_tree( const Node *n ) {
1247 assert( n->Opcode() != Op_Phi, "cannot match" );
1248 assert( !n->is_block_start(), "cannot match" );
1249 // Set the mark for all locally allocated State objects.
1250 // When this call returns, the _states_arena arena will be reset
1251 // freeing all State objects.
1252 ResourceMark rm( &_states_arena );
1253
1254 LabelRootDepth = 0;
1255
1256 // StoreNodes require their Memory input to match any LoadNodes
1257 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1258 #ifdef ASSERT
1259 Node* save_mem_node = _mem_node;
1260 _mem_node = n->is_Store() ? (Node*)n : NULL;
1261 #endif
1262 // State object for root node of match tree
1263 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1264 State *s = new (&_states_arena) State;
1265 s->_kids[0] = NULL;
1266 s->_kids[1] = NULL;
1267 s->_leaf = (Node*)n;
1268 // Label the input tree, allocating labels from top-level arena
1269 Label_Root( n, s, n->in(0), mem );
1270 if (C->failing()) return NULL;
1271
1272 // The minimum cost match for the whole tree is found at the root State
1273 uint mincost = max_juint;
1274 uint cost = max_juint;
1275 uint i;
1276 for( i = 0; i < NUM_OPERANDS; i++ ) {
1277 if( s->valid(i) && // valid entry and
1278 s->_cost[i] < cost && // low cost and
1279 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1280 cost = s->_cost[mincost=i];
1281 }
1282 if (mincost == max_juint) {
1283 #ifndef PRODUCT
1284 tty->print("No matching rule for:");
1285 s->dump();
1286 #endif
1287 Matcher::soft_match_failure();
1288 return NULL;
1289 }
1290 // Reduce input tree based upon the state labels to machine Nodes
1291 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1292 #ifdef ASSERT
1293 _old2new_map.map(n->_idx, m);
1294 _new2old_map.map(m->_idx, (Node*)n);
1295 #endif
1296
1297 // Add any Matcher-ignored edges
1298 uint cnt = n->req();
1299 uint start = 1;
1300 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1301 if( n->is_AddP() ) {
1302 assert( mem == (Node*)1, "" );
1303 start = AddPNode::Base+1;
1304 }
1305 for( i = start; i < cnt; i++ ) {
1306 if( !n->match_edge(i) ) {
1307 if( i < m->req() )
1308 m->ins_req( i, n->in(i) );
1309 else
1310 m->add_req( n->in(i) );
1311 }
1312 }
1313
1314 debug_only( _mem_node = save_mem_node; )
1315 return m;
1316 }
1317
1318
1319 //------------------------------match_into_reg---------------------------------
1320 // Choose to either match this Node in a register or part of the current
1321 // match tree. Return true for requiring a register and false for matching
1322 // as part of the current match tree.
1323 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1324
1325 const Type *t = m->bottom_type();
1326
1327 if( t->singleton() ) {
1328 // Never force constants into registers. Allow them to match as
1329 // constants or registers. Copies of the same value will share
1330 // the same register. See find_shared_node.
1331 return false;
1332 } else { // Not a constant
1333 // Stop recursion if they have different Controls.
1334 // Slot 0 of constants is not really a Control.
1335 if( control && m->in(0) && control != m->in(0) ) {
1336
1337 // Actually, we can live with the most conservative control we
1338 // find, if it post-dominates the others. This allows us to
1339 // pick up load/op/store trees where the load can float a little
1340 // above the store.
1341 Node *x = control;
1342 const uint max_scan = 6; // Arbitrary scan cutoff
1343 uint j;
1344 for( j=0; j<max_scan; j++ ) {
1345 if( x->is_Region() ) // Bail out at merge points
1346 return true;
1347 x = x->in(0);
1348 if( x == m->in(0) ) // Does 'control' post-dominate
1349 break; // m->in(0)? If so, we can use it
1350 }
1351 if( j == max_scan ) // No post-domination before scan end?
1352 return true; // Then break the match tree up
1353 }
1354 if (m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) {
1355 // These are commonly used in address expressions and can
1356 // efficiently fold into them on X64 in some cases.
1357 return false;
1358 }
1359 }
1360
1361 // Not forceable cloning. If shared, put it into a register.
1362 return shared;
1363 }
1364
1365
1366 //------------------------------Instruction Selection--------------------------
1367 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1368 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1369 // things the Matcher does not match (e.g., Memory), and things with different
1370 // Controls (hence forced into different blocks). We pass in the Control
1371 // selected for this entire State tree.
1372
1373 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1374 // Store and the Load must have identical Memories (as well as identical
1375 // pointers). Since the Matcher does not have anything for Memory (and
1376 // does not handle DAGs), I have to match the Memory input myself. If the
1377 // Tree root is a Store, I require all Loads to have the identical memory.
1378 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1379 // Since Label_Root is a recursive function, its possible that we might run
1380 // out of stack space. See bugs 6272980 & 6227033 for more info.
1381 LabelRootDepth++;
1382 if (LabelRootDepth > MaxLabelRootDepth) {
1383 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1384 return NULL;
1385 }
1386 uint care = 0; // Edges matcher cares about
1387 uint cnt = n->req();
1388 uint i = 0;
1389
1390 // Examine children for memory state
1391 // Can only subsume a child into your match-tree if that child's memory state
1392 // is not modified along the path to another input.
1393 // It is unsafe even if the other inputs are separate roots.
1394 Node *input_mem = NULL;
1395 for( i = 1; i < cnt; i++ ) {
1396 if( !n->match_edge(i) ) continue;
1397 Node *m = n->in(i); // Get ith input
1398 assert( m, "expect non-null children" );
1399 if( m->is_Load() ) {
1400 if( input_mem == NULL ) {
1401 input_mem = m->in(MemNode::Memory);
1402 } else if( input_mem != m->in(MemNode::Memory) ) {
1403 input_mem = NodeSentinel;
1404 }
1405 }
1406 }
1407
1408 for( i = 1; i < cnt; i++ ){// For my children
1409 if( !n->match_edge(i) ) continue;
1410 Node *m = n->in(i); // Get ith input
1411 // Allocate states out of a private arena
1412 State *s = new (&_states_arena) State;
1413 svec->_kids[care++] = s;
1414 assert( care <= 2, "binary only for now" );
1415
1416 // Recursively label the State tree.
1417 s->_kids[0] = NULL;
1418 s->_kids[1] = NULL;
1419 s->_leaf = m;
1420
1421 // Check for leaves of the State Tree; things that cannot be a part of
1422 // the current tree. If it finds any, that value is matched as a
1423 // register operand. If not, then the normal matching is used.
1424 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1425 //
1426 // Stop recursion if this is LoadNode and the root of this tree is a
1427 // StoreNode and the load & store have different memories.
1428 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1429 // Can NOT include the match of a subtree when its memory state
1430 // is used by any of the other subtrees
1431 (input_mem == NodeSentinel) ) {
1432 #ifndef PRODUCT
1433 // Print when we exclude matching due to different memory states at input-loads
1434 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1435 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1436 tty->print_cr("invalid input_mem");
1437 }
1438 #endif
1439 // Switch to a register-only opcode; this value must be in a register
1440 // and cannot be subsumed as part of a larger instruction.
1441 s->DFA( m->ideal_reg(), m );
1442
1443 } else {
1444 // If match tree has no control and we do, adopt it for entire tree
1445 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1446 control = m->in(0); // Pick up control
1447 // Else match as a normal part of the match tree.
1448 control = Label_Root(m,s,control,mem);
1449 if (C->failing()) return NULL;
1450 }
1451 }
1452
1453
1454 // Call DFA to match this node, and return
1455 svec->DFA( n->Opcode(), n );
1456
1457 #ifdef ASSERT
1458 uint x;
1459 for( x = 0; x < _LAST_MACH_OPER; x++ )
1460 if( svec->valid(x) )
1461 break;
1462
1463 if (x >= _LAST_MACH_OPER) {
1464 n->dump();
1465 svec->dump();
1466 assert( false, "bad AD file" );
1467 }
1468 #endif
1469 return control;
1470 }
1471
1472
1473 // Con nodes reduced using the same rule can share their MachNode
1474 // which reduces the number of copies of a constant in the final
1475 // program. The register allocator is free to split uses later to
1476 // split live ranges.
1477 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1478 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1479
1480 // See if this Con has already been reduced using this rule.
1481 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1482 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1483 if (last != NULL && rule == last->rule()) {
1484 // Don't expect control change for DecodeN
1485 if (leaf->is_DecodeN())
1486 return last;
1487 // Get the new space root.
1488 Node* xroot = new_node(C->root());
1489 if (xroot == NULL) {
1490 // This shouldn't happen give the order of matching.
1491 return NULL;
1492 }
1493
1494 // Shared constants need to have their control be root so they
1495 // can be scheduled properly.
1496 Node* control = last->in(0);
1497 if (control != xroot) {
1498 if (control == NULL || control == C->root()) {
1499 last->set_req(0, xroot);
1500 } else {
1501 assert(false, "unexpected control");
1502 return NULL;
1503 }
1504 }
1505 return last;
1506 }
1507 return NULL;
1508 }
1509
1510
1511 //------------------------------ReduceInst-------------------------------------
1512 // Reduce a State tree (with given Control) into a tree of MachNodes.
1513 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1514 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1515 // Each MachNode has a number of complicated MachOper operands; each
1516 // MachOper also covers a further tree of Ideal Nodes.
1517
1518 // The root of the Ideal match tree is always an instruction, so we enter
1519 // the recursion here. After building the MachNode, we need to recurse
1520 // the tree checking for these cases:
1521 // (1) Child is an instruction -
1522 // Build the instruction (recursively), add it as an edge.
1523 // Build a simple operand (register) to hold the result of the instruction.
1524 // (2) Child is an interior part of an instruction -
1525 // Skip over it (do nothing)
1526 // (3) Child is the start of a operand -
1527 // Build the operand, place it inside the instruction
1528 // Call ReduceOper.
1529 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1530 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1531
1532 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1533 if (shared_node != NULL) {
1534 return shared_node;
1535 }
1536
1537 // Build the object to represent this state & prepare for recursive calls
1538 MachNode *mach = s->MachNodeGenerator( rule, C );
1539 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1540 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1541 Node *leaf = s->_leaf;
1542 // Check for instruction or instruction chain rule
1543 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1544 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1545 "duplicating node that's already been matched");
1546 // Instruction
1547 mach->add_req( leaf->in(0) ); // Set initial control
1548 // Reduce interior of complex instruction
1549 ReduceInst_Interior( s, rule, mem, mach, 1 );
1550 } else {
1551 // Instruction chain rules are data-dependent on their inputs
1552 mach->add_req(0); // Set initial control to none
1553 ReduceInst_Chain_Rule( s, rule, mem, mach );
1554 }
1555
1556 // If a Memory was used, insert a Memory edge
1557 if( mem != (Node*)1 ) {
1558 mach->ins_req(MemNode::Memory,mem);
1559 #ifdef ASSERT
1560 // Verify adr type after matching memory operation
1561 const MachOper* oper = mach->memory_operand();
1562 if (oper != NULL && oper != (MachOper*)-1) {
1563 // It has a unique memory operand. Find corresponding ideal mem node.
1564 Node* m = NULL;
1565 if (leaf->is_Mem()) {
1566 m = leaf;
1567 } else {
1568 m = _mem_node;
1569 assert(m != NULL && m->is_Mem(), "expecting memory node");
1570 }
1571 const Type* mach_at = mach->adr_type();
1572 // DecodeN node consumed by an address may have different type
1573 // then its input. Don't compare types for such case.
1574 if (m->adr_type() != mach_at &&
1575 (m->in(MemNode::Address)->is_DecodeN() ||
1576 m->in(MemNode::Address)->is_AddP() &&
1577 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN() ||
1578 m->in(MemNode::Address)->is_AddP() &&
1579 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1580 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeN())) {
1581 mach_at = m->adr_type();
1582 }
1583 if (m->adr_type() != mach_at) {
1584 m->dump();
1585 tty->print_cr("mach:");
1586 mach->dump(1);
1587 }
1588 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1589 }
1590 #endif
1591 }
1592
1593 // If the _leaf is an AddP, insert the base edge
1594 if( leaf->is_AddP() )
1595 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1596
1597 uint num_proj = _proj_list.size();
1598
1599 // Perform any 1-to-many expansions required
1600 MachNode *ex = mach->Expand(s,_proj_list, mem);
1601 if( ex != mach ) {
1602 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1603 if( ex->in(1)->is_Con() )
1604 ex->in(1)->set_req(0, C->root());
1605 // Remove old node from the graph
1606 for( uint i=0; i<mach->req(); i++ ) {
1607 mach->set_req(i,NULL);
1608 }
1609 #ifdef ASSERT
1610 _new2old_map.map(ex->_idx, s->_leaf);
1611 #endif
1612 }
1613
1614 // PhaseChaitin::fixup_spills will sometimes generate spill code
1615 // via the matcher. By the time, nodes have been wired into the CFG,
1616 // and any further nodes generated by expand rules will be left hanging
1617 // in space, and will not get emitted as output code. Catch this.
1618 // Also, catch any new register allocation constraints ("projections")
1619 // generated belatedly during spill code generation.
1620 if (_allocation_started) {
1621 guarantee(ex == mach, "no expand rules during spill generation");
1622 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1623 }
1624
1625 if (leaf->is_Con() || leaf->is_DecodeN()) {
1626 // Record the con for sharing
1627 _shared_nodes.map(leaf->_idx, ex);
1628 }
1629
1630 return ex;
1631 }
1632
1633 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1634 // 'op' is what I am expecting to receive
1635 int op = _leftOp[rule];
1636 // Operand type to catch childs result
1637 // This is what my child will give me.
1638 int opnd_class_instance = s->_rule[op];
1639 // Choose between operand class or not.
1640 // This is what I will receive.
1641 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1642 // New rule for child. Chase operand classes to get the actual rule.
1643 int newrule = s->_rule[catch_op];
1644
1645 if( newrule < NUM_OPERANDS ) {
1646 // Chain from operand or operand class, may be output of shared node
1647 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1648 "Bad AD file: Instruction chain rule must chain from operand");
1649 // Insert operand into array of operands for this instruction
1650 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1651
1652 ReduceOper( s, newrule, mem, mach );
1653 } else {
1654 // Chain from the result of an instruction
1655 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1656 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1657 Node *mem1 = (Node*)1;
1658 debug_only(Node *save_mem_node = _mem_node;)
1659 mach->add_req( ReduceInst(s, newrule, mem1) );
1660 debug_only(_mem_node = save_mem_node;)
1661 }
1662 return;
1663 }
1664
1665
1666 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1667 if( s->_leaf->is_Load() ) {
1668 Node *mem2 = s->_leaf->in(MemNode::Memory);
1669 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1670 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1671 mem = mem2;
1672 }
1673 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1674 if( mach->in(0) == NULL )
1675 mach->set_req(0, s->_leaf->in(0));
1676 }
1677
1678 // Now recursively walk the state tree & add operand list.
1679 for( uint i=0; i<2; i++ ) { // binary tree
1680 State *newstate = s->_kids[i];
1681 if( newstate == NULL ) break; // Might only have 1 child
1682 // 'op' is what I am expecting to receive
1683 int op;
1684 if( i == 0 ) {
1685 op = _leftOp[rule];
1686 } else {
1687 op = _rightOp[rule];
1688 }
1689 // Operand type to catch childs result
1690 // This is what my child will give me.
1691 int opnd_class_instance = newstate->_rule[op];
1692 // Choose between operand class or not.
1693 // This is what I will receive.
1694 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1695 // New rule for child. Chase operand classes to get the actual rule.
1696 int newrule = newstate->_rule[catch_op];
1697
1698 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1699 // Operand/operandClass
1700 // Insert operand into array of operands for this instruction
1701 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1702 ReduceOper( newstate, newrule, mem, mach );
1703
1704 } else { // Child is internal operand or new instruction
1705 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1706 // internal operand --> call ReduceInst_Interior
1707 // Interior of complex instruction. Do nothing but recurse.
1708 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1709 } else {
1710 // instruction --> call build operand( ) to catch result
1711 // --> ReduceInst( newrule )
1712 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1713 Node *mem1 = (Node*)1;
1714 debug_only(Node *save_mem_node = _mem_node;)
1715 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1716 debug_only(_mem_node = save_mem_node;)
1717 }
1718 }
1719 assert( mach->_opnds[num_opnds-1], "" );
1720 }
1721 return num_opnds;
1722 }
1723
1724 // This routine walks the interior of possible complex operands.
1725 // At each point we check our children in the match tree:
1726 // (1) No children -
1727 // We are a leaf; add _leaf field as an input to the MachNode
1728 // (2) Child is an internal operand -
1729 // Skip over it ( do nothing )
1730 // (3) Child is an instruction -
1731 // Call ReduceInst recursively and
1732 // and instruction as an input to the MachNode
1733 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1734 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1735 State *kid = s->_kids[0];
1736 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1737
1738 // Leaf? And not subsumed?
1739 if( kid == NULL && !_swallowed[rule] ) {
1740 mach->add_req( s->_leaf ); // Add leaf pointer
1741 return; // Bail out
1742 }
1743
1744 if( s->_leaf->is_Load() ) {
1745 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1746 mem = s->_leaf->in(MemNode::Memory);
1747 debug_only(_mem_node = s->_leaf;)
1748 }
1749 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1750 if( !mach->in(0) )
1751 mach->set_req(0,s->_leaf->in(0));
1752 else {
1753 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1754 }
1755 }
1756
1757 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1758 int newrule;
1759 if( i == 0 )
1760 newrule = kid->_rule[_leftOp[rule]];
1761 else
1762 newrule = kid->_rule[_rightOp[rule]];
1763
1764 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1765 // Internal operand; recurse but do nothing else
1766 ReduceOper( kid, newrule, mem, mach );
1767
1768 } else { // Child is a new instruction
1769 // Reduce the instruction, and add a direct pointer from this
1770 // machine instruction to the newly reduced one.
1771 Node *mem1 = (Node*)1;
1772 debug_only(Node *save_mem_node = _mem_node;)
1773 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1774 debug_only(_mem_node = save_mem_node;)
1775 }
1776 }
1777 }
1778
1779
1780 // -------------------------------------------------------------------------
1781 // Java-Java calling convention
1782 // (what you use when Java calls Java)
1783
1784 //------------------------------find_receiver----------------------------------
1785 // For a given signature, return the OptoReg for parameter 0.
1786 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1787 VMRegPair regs;
1788 BasicType sig_bt = T_OBJECT;
1789 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1790 // Return argument 0 register. In the LP64 build pointers
1791 // take 2 registers, but the VM wants only the 'main' name.
1792 return OptoReg::as_OptoReg(regs.first());
1793 }
1794
1795 // A method-klass-holder may be passed in the inline_cache_reg
1796 // and then expanded into the inline_cache_reg and a method_oop register
1797 // defined in ad_<arch>.cpp
1798
1799
1800 //------------------------------find_shared------------------------------------
1801 // Set bits if Node is shared or otherwise a root
1802 void Matcher::find_shared( Node *n ) {
1803 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1804 MStack mstack(C->unique() * 2);
1805 // Mark nodes as address_visited if they are inputs to an address expression
1806 VectorSet address_visited(Thread::current()->resource_area());
1807 mstack.push(n, Visit); // Don't need to pre-visit root node
1808 while (mstack.is_nonempty()) {
1809 n = mstack.node(); // Leave node on stack
1810 Node_State nstate = mstack.state();
1811 uint nop = n->Opcode();
1812 if (nstate == Pre_Visit) {
1813 if (address_visited.test(n->_idx)) { // Visited in address already?
1814 // Flag as visited and shared now.
1815 set_visited(n);
1816 }
1817 if (is_visited(n)) { // Visited already?
1818 // Node is shared and has no reason to clone. Flag it as shared.
1819 // This causes it to match into a register for the sharing.
1820 set_shared(n); // Flag as shared and
1821 mstack.pop(); // remove node from stack
1822 continue;
1823 }
1824 nstate = Visit; // Not already visited; so visit now
1825 }
1826 if (nstate == Visit) {
1827 mstack.set_state(Post_Visit);
1828 set_visited(n); // Flag as visited now
1829 bool mem_op = false;
1830
1831 switch( nop ) { // Handle some opcodes special
1832 case Op_Phi: // Treat Phis as shared roots
1833 case Op_Parm:
1834 case Op_Proj: // All handled specially during matching
1835 case Op_SafePointScalarObject:
1836 set_shared(n);
1837 set_dontcare(n);
1838 break;
1839 case Op_If:
1840 case Op_CountedLoopEnd:
1841 mstack.set_state(Alt_Post_Visit); // Alternative way
1842 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1843 // with matching cmp/branch in 1 instruction. The Matcher needs the
1844 // Bool and CmpX side-by-side, because it can only get at constants
1845 // that are at the leaves of Match trees, and the Bool's condition acts
1846 // as a constant here.
1847 mstack.push(n->in(1), Visit); // Clone the Bool
1848 mstack.push(n->in(0), Pre_Visit); // Visit control input
1849 continue; // while (mstack.is_nonempty())
1850 case Op_ConvI2D: // These forms efficiently match with a prior
1851 case Op_ConvI2F: // Load but not a following Store
1852 if( n->in(1)->is_Load() && // Prior load
1853 n->outcnt() == 1 && // Not already shared
1854 n->unique_out()->is_Store() ) // Following store
1855 set_shared(n); // Force it to be a root
1856 break;
1857 case Op_ReverseBytesI:
1858 case Op_ReverseBytesL:
1859 if( n->in(1)->is_Load() && // Prior load
1860 n->outcnt() == 1 ) // Not already shared
1861 set_shared(n); // Force it to be a root
1862 break;
1863 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1864 case Op_IfFalse:
1865 case Op_IfTrue:
1866 case Op_MachProj:
1867 case Op_MergeMem:
1868 case Op_Catch:
1869 case Op_CatchProj:
1870 case Op_CProj:
1871 case Op_JumpProj:
1872 case Op_JProj:
1873 case Op_NeverBranch:
1874 set_dontcare(n);
1875 break;
1876 case Op_Jump:
1877 mstack.push(n->in(1), Visit); // Switch Value
1878 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1879 continue; // while (mstack.is_nonempty())
1880 case Op_StrComp:
1881 case Op_StrEquals:
1882 case Op_StrIndexOf:
1883 case Op_AryEq:
1884 set_shared(n); // Force result into register (it will be anyways)
1885 break;
1886 case Op_ConP: { // Convert pointers above the centerline to NUL
1887 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1888 const TypePtr* tp = tn->type()->is_ptr();
1889 if (tp->_ptr == TypePtr::AnyNull) {
1890 tn->set_type(TypePtr::NULL_PTR);
1891 }
1892 break;
1893 }
1894 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1895 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1896 const TypePtr* tp = tn->type()->make_ptr();
1897 if (tp && tp->_ptr == TypePtr::AnyNull) {
1898 tn->set_type(TypeNarrowOop::NULL_PTR);
1899 }
1900 break;
1901 }
1902 case Op_Binary: // These are introduced in the Post_Visit state.
1903 ShouldNotReachHere();
1904 break;
1905 case Op_ClearArray:
1906 case Op_SafePoint:
1907 mem_op = true;
1908 break;
1909 default:
1910 if( n->is_Store() ) {
1911 // Do match stores, despite no ideal reg
1912 mem_op = true;
1913 break;
1914 }
1915 if( n->is_Mem() ) { // Loads and LoadStores
1916 mem_op = true;
1917 // Loads must be root of match tree due to prior load conflict
1918 if( C->subsume_loads() == false )
1919 set_shared(n);
1920 }
1921 // Fall into default case
1922 if( !n->ideal_reg() )
1923 set_dontcare(n); // Unmatchable Nodes
1924 } // end_switch
1925
1926 for(int i = n->req() - 1; i >= 0; --i) { // For my children
1927 Node *m = n->in(i); // Get ith input
1928 if (m == NULL) continue; // Ignore NULLs
1929 uint mop = m->Opcode();
1930
1931 // Must clone all producers of flags, or we will not match correctly.
1932 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
1933 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
1934 // are also there, so we may match a float-branch to int-flags and
1935 // expect the allocator to haul the flags from the int-side to the
1936 // fp-side. No can do.
1937 if( _must_clone[mop] ) {
1938 mstack.push(m, Visit);
1939 continue; // for(int i = ...)
1940 }
1941
1942 if( mop == Op_AddP && m->in(AddPNode::Base)->Opcode() == Op_DecodeN ) {
1943 // Bases used in addresses must be shared but since
1944 // they are shared through a DecodeN they may appear
1945 // to have a single use so force sharing here.
1946 set_shared(m->in(AddPNode::Base)->in(1));
1947 }
1948
1949 // Clone addressing expressions as they are "free" in memory access instructions
1950 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
1951 // Some inputs for address expression are not put on stack
1952 // to avoid marking them as shared and forcing them into register
1953 // if they are used only in address expressions.
1954 // But they should be marked as shared if there are other uses
1955 // besides address expressions.
1956
1957 Node *off = m->in(AddPNode::Offset);
1958 if( off->is_Con() &&
1959 // When there are other uses besides address expressions
1960 // put it on stack and mark as shared.
1961 !is_visited(m) ) {
1962 address_visited.test_set(m->_idx); // Flag as address_visited
1963 Node *adr = m->in(AddPNode::Address);
1964
1965 // Intel, ARM and friends can handle 2 adds in addressing mode
1966 if( clone_shift_expressions && adr->is_AddP() &&
1967 // AtomicAdd is not an addressing expression.
1968 // Cheap to find it by looking for screwy base.
1969 !adr->in(AddPNode::Base)->is_top() &&
1970 // Are there other uses besides address expressions?
1971 !is_visited(adr) ) {
1972 address_visited.set(adr->_idx); // Flag as address_visited
1973 Node *shift = adr->in(AddPNode::Offset);
1974 // Check for shift by small constant as well
1975 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
1976 shift->in(2)->get_int() <= 3 &&
1977 // Are there other uses besides address expressions?
1978 !is_visited(shift) ) {
1979 address_visited.set(shift->_idx); // Flag as address_visited
1980 mstack.push(shift->in(2), Visit);
1981 Node *conv = shift->in(1);
1982 #ifdef _LP64
1983 // Allow Matcher to match the rule which bypass
1984 // ConvI2L operation for an array index on LP64
1985 // if the index value is positive.
1986 if( conv->Opcode() == Op_ConvI2L &&
1987 conv->as_Type()->type()->is_long()->_lo >= 0 &&
1988 // Are there other uses besides address expressions?
1989 !is_visited(conv) ) {
1990 address_visited.set(conv->_idx); // Flag as address_visited
1991 mstack.push(conv->in(1), Pre_Visit);
1992 } else
1993 #endif
1994 mstack.push(conv, Pre_Visit);
1995 } else {
1996 mstack.push(shift, Pre_Visit);
1997 }
1998 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
1999 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2000 } else { // Sparc, Alpha, PPC and friends
2001 mstack.push(adr, Pre_Visit);
2002 }
2003
2004 // Clone X+offset as it also folds into most addressing expressions
2005 mstack.push(off, Visit);
2006 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2007 continue; // for(int i = ...)
2008 } // if( off->is_Con() )
2009 } // if( mem_op &&
2010 mstack.push(m, Pre_Visit);
2011 } // for(int i = ...)
2012 }
2013 else if (nstate == Alt_Post_Visit) {
2014 mstack.pop(); // Remove node from stack
2015 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2016 // shared and all users of the Bool need to move the Cmp in parallel.
2017 // This leaves both the Bool and the If pointing at the Cmp. To
2018 // prevent the Matcher from trying to Match the Cmp along both paths
2019 // BoolNode::match_edge always returns a zero.
2020
2021 // We reorder the Op_If in a pre-order manner, so we can visit without
2022 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2023 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2024 }
2025 else if (nstate == Post_Visit) {
2026 mstack.pop(); // Remove node from stack
2027
2028 // Now hack a few special opcodes
2029 switch( n->Opcode() ) { // Handle some opcodes special
2030 case Op_StorePConditional:
2031 case Op_StoreIConditional:
2032 case Op_StoreLConditional:
2033 case Op_CompareAndSwapI:
2034 case Op_CompareAndSwapL:
2035 case Op_CompareAndSwapP:
2036 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2037 Node *newval = n->in(MemNode::ValueIn );
2038 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
2039 Node *pair = new (C, 3) BinaryNode( oldval, newval );
2040 n->set_req(MemNode::ValueIn,pair);
2041 n->del_req(LoadStoreNode::ExpectedIn);
2042 break;
2043 }
2044 case Op_CMoveD: // Convert trinary to binary-tree
2045 case Op_CMoveF:
2046 case Op_CMoveI:
2047 case Op_CMoveL:
2048 case Op_CMoveN:
2049 case Op_CMoveP: {
2050 // Restructure into a binary tree for Matching. It's possible that
2051 // we could move this code up next to the graph reshaping for IfNodes
2052 // or vice-versa, but I do not want to debug this for Ladybird.
2053 // 10/2/2000 CNC.
2054 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
2055 n->set_req(1,pair1);
2056 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2057 n->set_req(2,pair2);
2058 n->del_req(3);
2059 break;
2060 }
2061 case Op_StrEquals: {
2062 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2063 n->set_req(2,pair1);
2064 n->set_req(3,n->in(4));
2065 n->del_req(4);
2066 break;
2067 }
2068 case Op_StrComp:
2069 case Op_StrIndexOf: {
2070 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2071 n->set_req(2,pair1);
2072 Node *pair2 = new (C, 3) BinaryNode(n->in(4),n->in(5));
2073 n->set_req(3,pair2);
2074 n->del_req(5);
2075 n->del_req(4);
2076 break;
2077 }
2078 default:
2079 break;
2080 }
2081 }
2082 else {
2083 ShouldNotReachHere();
2084 }
2085 } // end of while (mstack.is_nonempty())
2086 }
2087
2088 #ifdef ASSERT
2089 // machine-independent root to machine-dependent root
2090 void Matcher::dump_old2new_map() {
2091 _old2new_map.dump();
2092 }
2093 #endif
2094
2095 //---------------------------collect_null_checks-------------------------------
2096 // Find null checks in the ideal graph; write a machine-specific node for
2097 // it. Used by later implicit-null-check handling. Actually collects
2098 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2099 // value being tested.
2100 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2101 Node *iff = proj->in(0);
2102 if( iff->Opcode() == Op_If ) {
2103 // During matching If's have Bool & Cmp side-by-side
2104 BoolNode *b = iff->in(1)->as_Bool();
2105 Node *cmp = iff->in(2);
2106 int opc = cmp->Opcode();
2107 if (opc != Op_CmpP && opc != Op_CmpN) return;
2108
2109 const Type* ct = cmp->in(2)->bottom_type();
2110 if (ct == TypePtr::NULL_PTR ||
2111 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2112
2113 bool push_it = false;
2114 if( proj->Opcode() == Op_IfTrue ) {
2115 extern int all_null_checks_found;
2116 all_null_checks_found++;
2117 if( b->_test._test == BoolTest::ne ) {
2118 push_it = true;
2119 }
2120 } else {
2121 assert( proj->Opcode() == Op_IfFalse, "" );
2122 if( b->_test._test == BoolTest::eq ) {
2123 push_it = true;
2124 }
2125 }
2126 if( push_it ) {
2127 _null_check_tests.push(proj);
2128 Node* val = cmp->in(1);
2129 #ifdef _LP64
2130 if (val->bottom_type()->isa_narrowoop() &&
2131 !Matcher::narrow_oop_use_complex_address()) {
2132 //
2133 // Look for DecodeN node which should be pinned to orig_proj.
2134 // On platforms (Sparc) which can not handle 2 adds
2135 // in addressing mode we have to keep a DecodeN node and
2136 // use it to do implicit NULL check in address.
2137 //
2138 // DecodeN node was pinned to non-null path (orig_proj) during
2139 // CastPP transformation in final_graph_reshaping_impl().
2140 //
2141 uint cnt = orig_proj->outcnt();
2142 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2143 Node* d = orig_proj->raw_out(i);
2144 if (d->is_DecodeN() && d->in(1) == val) {
2145 val = d;
2146 val->set_req(0, NULL); // Unpin now.
2147 // Mark this as special case to distinguish from
2148 // a regular case: CmpP(DecodeN, NULL).
2149 val = (Node*)(((intptr_t)val) | 1);
2150 break;
2151 }
2152 }
2153 }
2154 #endif
2155 _null_check_tests.push(val);
2156 }
2157 }
2158 }
2159 }
2160
2161 //---------------------------validate_null_checks------------------------------
2162 // Its possible that the value being NULL checked is not the root of a match
2163 // tree. If so, I cannot use the value in an implicit null check.
2164 void Matcher::validate_null_checks( ) {
2165 uint cnt = _null_check_tests.size();
2166 for( uint i=0; i < cnt; i+=2 ) {
2167 Node *test = _null_check_tests[i];
2168 Node *val = _null_check_tests[i+1];
2169 bool is_decoden = ((intptr_t)val) & 1;
2170 val = (Node*)(((intptr_t)val) & ~1);
2171 if (has_new_node(val)) {
2172 Node* new_val = new_node(val);
2173 if (is_decoden) {
2174 assert(val->is_DecodeN() && val->in(0) == NULL, "sanity");
2175 // Note: new_val may have a control edge if
2176 // the original ideal node DecodeN was matched before
2177 // it was unpinned in Matcher::collect_null_checks().
2178 // Unpin the mach node and mark it.
2179 new_val->set_req(0, NULL);
2180 new_val = (Node*)(((intptr_t)new_val) | 1);
2181 }
2182 // Is a match-tree root, so replace with the matched value
2183 _null_check_tests.map(i+1, new_val);
2184 } else {
2185 // Yank from candidate list
2186 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2187 _null_check_tests.map(i,_null_check_tests[--cnt]);
2188 _null_check_tests.pop();
2189 _null_check_tests.pop();
2190 i-=2;
2191 }
2192 }
2193 }
2194
2195
2196 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
2197 // acting as an Acquire and thus we don't need an Acquire here. We
2198 // retain the Node to act as a compiler ordering barrier.
2199 bool Matcher::prior_fast_lock( const Node *acq ) {
2200 Node *r = acq->in(0);
2201 if( !r->is_Region() || r->req() <= 1 ) return false;
2202 Node *proj = r->in(1);
2203 if( !proj->is_Proj() ) return false;
2204 Node *call = proj->in(0);
2205 if( !call->is_Call() || call->as_Call()->entry_point() != OptoRuntime::complete_monitor_locking_Java() )
2206 return false;
2207
2208 return true;
2209 }
2210
2211 // Used by the DFA in dfa_sparc.cpp. Check for a following FastUnLock
2212 // acting as a Release and thus we don't need a Release here. We
2213 // retain the Node to act as a compiler ordering barrier.
2214 bool Matcher::post_fast_unlock( const Node *rel ) {
2215 Compile *C = Compile::current();
2216 assert( rel->Opcode() == Op_MemBarRelease, "" );
2217 const MemBarReleaseNode *mem = (const MemBarReleaseNode*)rel;
2218 DUIterator_Fast imax, i = mem->fast_outs(imax);
2219 Node *ctrl = NULL;
2220 while( true ) {
2221 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2222 assert( ctrl->is_Proj(), "only projections here" );
2223 ProjNode *proj = (ProjNode*)ctrl;
2224 if( proj->_con == TypeFunc::Control &&
2225 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2226 break;
2227 i++;
2228 }
2229 Node *iff = NULL;
2230 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2231 Node *x = ctrl->fast_out(j);
2232 if( x->is_If() && x->req() > 1 &&
2233 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2234 iff = x;
2235 break;
2236 }
2237 }
2238 if( !iff ) return false;
2239 Node *bol = iff->in(1);
2240 // The iff might be some random subclass of If or bol might be Con-Top
2241 if (!bol->is_Bool()) return false;
2242 assert( bol->req() > 1, "" );
2243 return (bol->in(1)->Opcode() == Op_FastUnlock);
2244 }
2245
2246 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2247 // atomic instruction acting as a store_load barrier without any
2248 // intervening volatile load, and thus we don't need a barrier here.
2249 // We retain the Node to act as a compiler ordering barrier.
2250 bool Matcher::post_store_load_barrier(const Node *vmb) {
2251 Compile *C = Compile::current();
2252 assert( vmb->is_MemBar(), "" );
2253 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2254 const MemBarNode *mem = (const MemBarNode*)vmb;
2255
2256 // Get the Proj node, ctrl, that can be used to iterate forward
2257 Node *ctrl = NULL;
2258 DUIterator_Fast imax, i = mem->fast_outs(imax);
2259 while( true ) {
2260 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2261 assert( ctrl->is_Proj(), "only projections here" );
2262 ProjNode *proj = (ProjNode*)ctrl;
2263 if( proj->_con == TypeFunc::Control &&
2264 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2265 break;
2266 i++;
2267 }
2268
2269 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2270 Node *x = ctrl->fast_out(j);
2271 int xop = x->Opcode();
2272
2273 // We don't need current barrier if we see another or a lock
2274 // before seeing volatile load.
2275 //
2276 // Op_Fastunlock previously appeared in the Op_* list below.
2277 // With the advent of 1-0 lock operations we're no longer guaranteed
2278 // that a monitor exit operation contains a serializing instruction.
2279
2280 if (xop == Op_MemBarVolatile ||
2281 xop == Op_FastLock ||
2282 xop == Op_CompareAndSwapL ||
2283 xop == Op_CompareAndSwapP ||
2284 xop == Op_CompareAndSwapN ||
2285 xop == Op_CompareAndSwapI)
2286 return true;
2287
2288 if (x->is_MemBar()) {
2289 // We must retain this membar if there is an upcoming volatile
2290 // load, which will be preceded by acquire membar.
2291 if (xop == Op_MemBarAcquire)
2292 return false;
2293 // For other kinds of barriers, check by pretending we
2294 // are them, and seeing if we can be removed.
2295 else
2296 return post_store_load_barrier((const MemBarNode*)x);
2297 }
2298
2299 // Delicate code to detect case of an upcoming fastlock block
2300 if( x->is_If() && x->req() > 1 &&
2301 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2302 Node *iff = x;
2303 Node *bol = iff->in(1);
2304 // The iff might be some random subclass of If or bol might be Con-Top
2305 if (!bol->is_Bool()) return false;
2306 assert( bol->req() > 1, "" );
2307 return (bol->in(1)->Opcode() == Op_FastUnlock);
2308 }
2309 // probably not necessary to check for these
2310 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2311 return false;
2312 }
2313 return false;
2314 }
2315
2316 //=============================================================================
2317 //---------------------------State---------------------------------------------
2318 State::State(void) {
2319 #ifdef ASSERT
2320 _id = 0;
2321 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2322 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2323 //memset(_cost, -1, sizeof(_cost));
2324 //memset(_rule, -1, sizeof(_rule));
2325 #endif
2326 memset(_valid, 0, sizeof(_valid));
2327 }
2328
2329 #ifdef ASSERT
2330 State::~State() {
2331 _id = 99;
2332 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2333 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2334 memset(_cost, -3, sizeof(_cost));
2335 memset(_rule, -3, sizeof(_rule));
2336 }
2337 #endif
2338
2339 #ifndef PRODUCT
2340 //---------------------------dump----------------------------------------------
2341 void State::dump() {
2342 tty->print("\n");
2343 dump(0);
2344 }
2345
2346 void State::dump(int depth) {
2347 for( int j = 0; j < depth; j++ )
2348 tty->print(" ");
2349 tty->print("--N: ");
2350 _leaf->dump();
2351 uint i;
2352 for( i = 0; i < _LAST_MACH_OPER; i++ )
2353 // Check for valid entry
2354 if( valid(i) ) {
2355 for( int j = 0; j < depth; j++ )
2356 tty->print(" ");
2357 assert(_cost[i] != max_juint, "cost must be a valid value");
2358 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2359 tty->print_cr("%s %d %s",
2360 ruleName[i], _cost[i], ruleName[_rule[i]] );
2361 }
2362 tty->print_cr("");
2363
2364 for( i=0; i<2; i++ )
2365 if( _kids[i] )
2366 _kids[i]->dump(depth+1);
2367 }
2368 #endif