1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc_interface/collectedHeap.hpp"
34 #include "memory/barrierSet.hpp"
35 #include "memory/cardTableModRefBS.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 #define __ _masm->
41
42
43 //------------------------------------------------------------
44
45
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
47 if (opr->is_constant()) {
48 LIR_Const* constant = opr->as_constant_ptr();
49 switch (constant->type()) {
50 case T_INT: {
51 jint value = constant->as_jint();
52 return Assembler::is_simm13(value);
53 }
54
55 default:
56 return false;
57 }
58 }
59 return false;
60 }
61
62
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
64 switch (op->code()) {
65 case lir_null_check:
66 return true;
67
68
69 case lir_add:
70 case lir_ushr:
71 case lir_shr:
72 case lir_shl:
73 // integer shifts and adds are always one instruction
74 return op->result_opr()->is_single_cpu();
75
76
77 case lir_move: {
78 LIR_Op1* op1 = op->as_Op1();
79 LIR_Opr src = op1->in_opr();
80 LIR_Opr dst = op1->result_opr();
81
82 if (src == dst) {
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (dst->is_register()) {
104 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
105 return !PatchALot;
106 } else if (src->is_single_stack()) {
107 return true;
108 }
109 }
110
111 if (src->is_register()) {
112 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
113 return !PatchALot;
114 } else if (dst->is_single_stack()) {
115 return true;
116 }
117 }
118
119 if (dst->is_register() &&
120 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
121 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
122 return true;
123 }
124
125 return false;
126 }
127
128 default:
129 return false;
130 }
131 ShouldNotReachHere();
132 }
133
134
135 LIR_Opr LIR_Assembler::receiverOpr() {
136 return FrameMap::O0_oop_opr;
137 }
138
139
140 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
141 return FrameMap::I0_oop_opr;
142 }
143
144
145 LIR_Opr LIR_Assembler::osrBufferPointer() {
146 return FrameMap::I0_opr;
147 }
148
149
150 int LIR_Assembler::initial_frame_size_in_bytes() {
151 return in_bytes(frame_map()->framesize_in_bytes());
152 }
153
154
155 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
156 // we fetch the class of the receiver (O0) and compare it with the cached class.
157 // If they do not match we jump to slow case.
158 int LIR_Assembler::check_icache() {
159 int offset = __ offset();
160 __ inline_cache_check(O0, G5_inline_cache_reg);
161 return offset;
162 }
163
164
165 void LIR_Assembler::osr_entry() {
166 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
167 //
168 // 1. Create a new compiled activation.
169 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
170 // at the osr_bci; it is not initialized.
171 // 3. Jump to the continuation address in compiled code to resume execution.
172
173 // OSR entry point
174 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
175 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
176 ValueStack* entry_state = osr_entry->end()->state();
177 int number_of_locks = entry_state->locks_size();
178
179 // Create a frame for the compiled activation.
180 __ build_frame(initial_frame_size_in_bytes());
181
182 // OSR buffer is
183 //
184 // locals[nlocals-1..0]
185 // monitors[number_of_locks-1..0]
186 //
187 // locals is a direct copy of the interpreter frame so in the osr buffer
188 // so first slot in the local array is the last local from the interpreter
189 // and last slot is local[0] (receiver) from the interpreter
190 //
191 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
192 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
193 // in the interpreter frame (the method lock if a sync method)
194
195 // Initialize monitors in the compiled activation.
196 // I0: pointer to osr buffer
197 //
198 // All other registers are dead at this point and the locals will be
199 // copied into place by code emitted in the IR.
200
201 Register OSR_buf = osrBufferPointer()->as_register();
202 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
203 int monitor_offset = BytesPerWord * method()->max_locals() +
204 (2 * BytesPerWord) * (number_of_locks - 1);
205 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
206 // the OSR buffer using 2 word entries: first the lock and then
207 // the oop.
208 for (int i = 0; i < number_of_locks; i++) {
209 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
210 #ifdef ASSERT
211 // verify the interpreter's monitor has a non-null object
212 {
213 Label L;
214 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
215 __ cmp(G0, O7);
216 __ br(Assembler::notEqual, false, Assembler::pt, L);
217 __ delayed()->nop();
218 __ stop("locked object is NULL");
219 __ bind(L);
220 }
221 #endif // ASSERT
222 // Copy the lock field into the compiled activation.
223 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
224 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
225 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
226 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
227 }
228 }
229 }
230
231
232 // Optimized Library calls
233 // This is the fast version of java.lang.String.compare; it has not
234 // OSR-entry and therefore, we generate a slow version for OSR's
235 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
236 Register str0 = left->as_register();
237 Register str1 = right->as_register();
238
239 Label Ldone;
240
241 Register result = dst->as_register();
242 {
243 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
244 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
245 // Also, get string0.count-string1.count in o7 and get the condition code set
246 // Note: some instructions have been hoisted for better instruction scheduling
247
248 Register tmp0 = L0;
249 Register tmp1 = L1;
250 Register tmp2 = L2;
251
252 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
253 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
254 int count_offset = java_lang_String:: count_offset_in_bytes();
255
256 __ ld_ptr(str0, value_offset, tmp0);
257 __ ld(str0, offset_offset, tmp2);
258 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
259 __ ld(str0, count_offset, str0);
260 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
261
262 // str1 may be null
263 add_debug_info_for_null_check_here(info);
264
265 __ ld_ptr(str1, value_offset, tmp1);
266 __ add(tmp0, tmp2, tmp0);
267
268 __ ld(str1, offset_offset, tmp2);
269 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
270 __ ld(str1, count_offset, str1);
271 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
272 __ subcc(str0, str1, O7);
273 __ add(tmp1, tmp2, tmp1);
274 }
275
276 {
277 // Compute the minimum of the string lengths, scale it and store it in limit
278 Register count0 = I0;
279 Register count1 = I1;
280 Register limit = L3;
281
282 Label Lskip;
283 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
284 __ br(Assembler::greater, true, Assembler::pt, Lskip);
285 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
286 __ bind(Lskip);
287
288 // If either string is empty (or both of them) the result is the difference in lengths
289 __ cmp(limit, 0);
290 __ br(Assembler::equal, true, Assembler::pn, Ldone);
291 __ delayed()->mov(O7, result); // result is difference in lengths
292 }
293
294 {
295 // Neither string is empty
296 Label Lloop;
297
298 Register base0 = L0;
299 Register base1 = L1;
300 Register chr0 = I0;
301 Register chr1 = I1;
302 Register limit = L3;
303
304 // Shift base0 and base1 to the end of the arrays, negate limit
305 __ add(base0, limit, base0);
306 __ add(base1, limit, base1);
307 __ neg(limit); // limit = -min{string0.count, strin1.count}
308
309 __ lduh(base0, limit, chr0);
310 __ bind(Lloop);
311 __ lduh(base1, limit, chr1);
312 __ subcc(chr0, chr1, chr0);
313 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
314 assert(chr0 == result, "result must be pre-placed");
315 __ delayed()->inccc(limit, sizeof(jchar));
316 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
317 __ delayed()->lduh(base0, limit, chr0);
318 }
319
320 // If strings are equal up to min length, return the length difference.
321 __ mov(O7, result);
322
323 // Otherwise, return the difference between the first mismatched chars.
324 __ bind(Ldone);
325 }
326
327
328 // --------------------------------------------------------------------------------------------
329
330 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
331 if (!GenerateSynchronizationCode) return;
332
333 Register obj_reg = obj_opr->as_register();
334 Register lock_reg = lock_opr->as_register();
335
336 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
337 Register reg = mon_addr.base();
338 int offset = mon_addr.disp();
339 // compute pointer to BasicLock
340 if (mon_addr.is_simm13()) {
341 __ add(reg, offset, lock_reg);
342 }
343 else {
344 __ set(offset, lock_reg);
345 __ add(reg, lock_reg, lock_reg);
346 }
347 // unlock object
348 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
349 // _slow_case_stubs->append(slow_case);
350 // temporary fix: must be created after exceptionhandler, therefore as call stub
351 _slow_case_stubs->append(slow_case);
352 if (UseFastLocking) {
353 // try inlined fast unlocking first, revert to slow locking if it fails
354 // note: lock_reg points to the displaced header since the displaced header offset is 0!
355 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
356 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
357 } else {
358 // always do slow unlocking
359 // note: the slow unlocking code could be inlined here, however if we use
360 // slow unlocking, speed doesn't matter anyway and this solution is
361 // simpler and requires less duplicated code - additionally, the
362 // slow unlocking code is the same in either case which simplifies
363 // debugging
364 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
365 __ delayed()->nop();
366 }
367 // done
368 __ bind(*slow_case->continuation());
369 }
370
371
372 int LIR_Assembler::emit_exception_handler() {
373 // if the last instruction is a call (typically to do a throw which
374 // is coming at the end after block reordering) the return address
375 // must still point into the code area in order to avoid assertion
376 // failures when searching for the corresponding bci => add a nop
377 // (was bug 5/14/1999 - gri)
378 __ nop();
379
380 // generate code for exception handler
381 ciMethod* method = compilation()->method();
382
383 address handler_base = __ start_a_stub(exception_handler_size);
384
385 if (handler_base == NULL) {
386 // not enough space left for the handler
387 bailout("exception handler overflow");
388 return -1;
389 }
390
391 int offset = code_offset();
392
393 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
394 __ delayed()->nop();
395 debug_only(__ stop("should have gone to the caller");)
396 assert(code_offset() - offset <= exception_handler_size, "overflow");
397 __ end_a_stub();
398
399 return offset;
400 }
401
402
403 // Emit the code to remove the frame from the stack in the exception
404 // unwind path.
405 int LIR_Assembler::emit_unwind_handler() {
406 #ifndef PRODUCT
407 if (CommentedAssembly) {
408 _masm->block_comment("Unwind handler");
409 }
410 #endif
411
412 int offset = code_offset();
413
414 // Fetch the exception from TLS and clear out exception related thread state
415 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
416 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
417 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
418
419 __ bind(_unwind_handler_entry);
420 __ verify_not_null_oop(O0);
421 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
422 __ mov(O0, I0); // Preserve the exception
423 }
424
425 // Preform needed unlocking
426 MonitorExitStub* stub = NULL;
427 if (method()->is_synchronized()) {
428 monitor_address(0, FrameMap::I1_opr);
429 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
430 __ unlock_object(I3, I2, I1, *stub->entry());
431 __ bind(*stub->continuation());
432 }
433
434 if (compilation()->env()->dtrace_method_probes()) {
435 jobject2reg(method()->constant_encoding(), O0);
436 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
437 __ delayed()->nop();
438 }
439
440 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
441 __ mov(I0, O0); // Restore the exception
442 }
443
444 // dispatch to the unwind logic
445 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
446 __ delayed()->nop();
447
448 // Emit the slow path assembly
449 if (stub != NULL) {
450 stub->emit_code(this);
451 }
452
453 return offset;
454 }
455
456
457 int LIR_Assembler::emit_deopt_handler() {
458 // if the last instruction is a call (typically to do a throw which
459 // is coming at the end after block reordering) the return address
460 // must still point into the code area in order to avoid assertion
461 // failures when searching for the corresponding bci => add a nop
462 // (was bug 5/14/1999 - gri)
463 __ nop();
464
465 // generate code for deopt handler
466 ciMethod* method = compilation()->method();
467 address handler_base = __ start_a_stub(deopt_handler_size);
468 if (handler_base == NULL) {
469 // not enough space left for the handler
470 bailout("deopt handler overflow");
471 return -1;
472 }
473
474 int offset = code_offset();
475 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
476 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
477 __ delayed()->nop();
478 assert(code_offset() - offset <= deopt_handler_size, "overflow");
479 debug_only(__ stop("should have gone to the caller");)
480 __ end_a_stub();
481
482 return offset;
483 }
484
485
486 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
487 if (o == NULL) {
488 __ set(NULL_WORD, reg);
489 } else {
490 int oop_index = __ oop_recorder()->find_index(o);
491 RelocationHolder rspec = oop_Relocation::spec(oop_index);
492 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
493 }
494 }
495
496
497 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
498 // Allocate a new index in oop table to hold the oop once it's been patched
499 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
500 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
501
502 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
503 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
504 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
505 // NULL will be dynamically patched later and the patched value may be large. We must
506 // therefore generate the sethi/add as a placeholders
507 __ patchable_set(addrlit, reg);
508
509 patching_epilog(patch, lir_patch_normal, reg, info);
510 }
511
512
513 void LIR_Assembler::emit_op3(LIR_Op3* op) {
514 Register Rdividend = op->in_opr1()->as_register();
515 Register Rdivisor = noreg;
516 Register Rscratch = op->in_opr3()->as_register();
517 Register Rresult = op->result_opr()->as_register();
518 int divisor = -1;
519
520 if (op->in_opr2()->is_register()) {
521 Rdivisor = op->in_opr2()->as_register();
522 } else {
523 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
524 assert(Assembler::is_simm13(divisor), "can only handle simm13");
525 }
526
527 assert(Rdividend != Rscratch, "");
528 assert(Rdivisor != Rscratch, "");
529 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
530
531 if (Rdivisor == noreg && is_power_of_2(divisor)) {
532 // convert division by a power of two into some shifts and logical operations
533 if (op->code() == lir_idiv) {
534 if (divisor == 2) {
535 __ srl(Rdividend, 31, Rscratch);
536 } else {
537 __ sra(Rdividend, 31, Rscratch);
538 __ and3(Rscratch, divisor - 1, Rscratch);
539 }
540 __ add(Rdividend, Rscratch, Rscratch);
541 __ sra(Rscratch, log2_intptr(divisor), Rresult);
542 return;
543 } else {
544 if (divisor == 2) {
545 __ srl(Rdividend, 31, Rscratch);
546 } else {
547 __ sra(Rdividend, 31, Rscratch);
548 __ and3(Rscratch, divisor - 1,Rscratch);
549 }
550 __ add(Rdividend, Rscratch, Rscratch);
551 __ andn(Rscratch, divisor - 1,Rscratch);
552 __ sub(Rdividend, Rscratch, Rresult);
553 return;
554 }
555 }
556
557 __ sra(Rdividend, 31, Rscratch);
558 __ wry(Rscratch);
559 if (!VM_Version::v9_instructions_work()) {
560 // v9 doesn't require these nops
561 __ nop();
562 __ nop();
563 __ nop();
564 __ nop();
565 }
566
567 add_debug_info_for_div0_here(op->info());
568
569 if (Rdivisor != noreg) {
570 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
571 } else {
572 assert(Assembler::is_simm13(divisor), "can only handle simm13");
573 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
574 }
575
576 Label skip;
577 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
578 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
579 __ bind(skip);
580
581 if (op->code() == lir_irem) {
582 if (Rdivisor != noreg) {
583 __ smul(Rscratch, Rdivisor, Rscratch);
584 } else {
585 __ smul(Rscratch, divisor, Rscratch);
586 }
587 __ sub(Rdividend, Rscratch, Rresult);
588 }
589 }
590
591
592 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
593 #ifdef ASSERT
594 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
595 if (op->block() != NULL) _branch_target_blocks.append(op->block());
596 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
597 #endif
598 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
599
600 if (op->cond() == lir_cond_always) {
601 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
602 } else if (op->code() == lir_cond_float_branch) {
603 assert(op->ublock() != NULL, "must have unordered successor");
604 bool is_unordered = (op->ublock() == op->block());
605 Assembler::Condition acond;
606 switch (op->cond()) {
607 case lir_cond_equal: acond = Assembler::f_equal; break;
608 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
609 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
610 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
611 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
612 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
613 default : ShouldNotReachHere();
614 };
615
616 if (!VM_Version::v9_instructions_work()) {
617 __ nop();
618 }
619 __ fb( acond, false, Assembler::pn, *(op->label()));
620 } else {
621 assert (op->code() == lir_branch, "just checking");
622
623 Assembler::Condition acond;
624 switch (op->cond()) {
625 case lir_cond_equal: acond = Assembler::equal; break;
626 case lir_cond_notEqual: acond = Assembler::notEqual; break;
627 case lir_cond_less: acond = Assembler::less; break;
628 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
629 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
630 case lir_cond_greater: acond = Assembler::greater; break;
631 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
632 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
633 default: ShouldNotReachHere();
634 };
635
636 // sparc has different condition codes for testing 32-bit
637 // vs. 64-bit values. We could always test xcc is we could
638 // guarantee that 32-bit loads always sign extended but that isn't
639 // true and since sign extension isn't free, it would impose a
640 // slight cost.
641 #ifdef _LP64
642 if (op->type() == T_INT) {
643 __ br(acond, false, Assembler::pn, *(op->label()));
644 } else
645 #endif
646 __ brx(acond, false, Assembler::pn, *(op->label()));
647 }
648 // The peephole pass fills the delay slot
649 }
650
651
652 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
653 Bytecodes::Code code = op->bytecode();
654 LIR_Opr dst = op->result_opr();
655
656 switch(code) {
657 case Bytecodes::_i2l: {
658 Register rlo = dst->as_register_lo();
659 Register rhi = dst->as_register_hi();
660 Register rval = op->in_opr()->as_register();
661 #ifdef _LP64
662 __ sra(rval, 0, rlo);
663 #else
664 __ mov(rval, rlo);
665 __ sra(rval, BitsPerInt-1, rhi);
666 #endif
667 break;
668 }
669 case Bytecodes::_i2d:
670 case Bytecodes::_i2f: {
671 bool is_double = (code == Bytecodes::_i2d);
672 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
673 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
674 FloatRegister rsrc = op->in_opr()->as_float_reg();
675 if (rsrc != rdst) {
676 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
677 }
678 __ fitof(w, rdst, rdst);
679 break;
680 }
681 case Bytecodes::_f2i:{
682 FloatRegister rsrc = op->in_opr()->as_float_reg();
683 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
684 Label L;
685 // result must be 0 if value is NaN; test by comparing value to itself
686 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
687 if (!VM_Version::v9_instructions_work()) {
688 __ nop();
689 }
690 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
691 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
692 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
693 // move integer result from float register to int register
694 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
695 __ bind (L);
696 break;
697 }
698 case Bytecodes::_l2i: {
699 Register rlo = op->in_opr()->as_register_lo();
700 Register rhi = op->in_opr()->as_register_hi();
701 Register rdst = dst->as_register();
702 #ifdef _LP64
703 __ sra(rlo, 0, rdst);
704 #else
705 __ mov(rlo, rdst);
706 #endif
707 break;
708 }
709 case Bytecodes::_d2f:
710 case Bytecodes::_f2d: {
711 bool is_double = (code == Bytecodes::_f2d);
712 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
713 LIR_Opr val = op->in_opr();
714 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
715 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
716 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
717 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
718 __ ftof(vw, dw, rval, rdst);
719 break;
720 }
721 case Bytecodes::_i2s:
722 case Bytecodes::_i2b: {
723 Register rval = op->in_opr()->as_register();
724 Register rdst = dst->as_register();
725 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
726 __ sll (rval, shift, rdst);
727 __ sra (rdst, shift, rdst);
728 break;
729 }
730 case Bytecodes::_i2c: {
731 Register rval = op->in_opr()->as_register();
732 Register rdst = dst->as_register();
733 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
734 __ sll (rval, shift, rdst);
735 __ srl (rdst, shift, rdst);
736 break;
737 }
738
739 default: ShouldNotReachHere();
740 }
741 }
742
743
744 void LIR_Assembler::align_call(LIR_Code) {
745 // do nothing since all instructions are word aligned on sparc
746 }
747
748
749 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
750 __ call(op->addr(), rtype);
751 // The peephole pass fills the delay slot, add_call_info is done in
752 // LIR_Assembler::emit_delay.
753 }
754
755
756 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
757 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
758 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
759 __ relocate(rspec);
760 __ call(op->addr(), relocInfo::none);
761 // The peephole pass fills the delay slot, add_call_info is done in
762 // LIR_Assembler::emit_delay.
763 }
764
765
766 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
767 add_debug_info_for_null_check_here(op->info());
768 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
769 if (__ is_simm13(op->vtable_offset())) {
770 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
771 } else {
772 // This will generate 2 instructions
773 __ set(op->vtable_offset(), G5_method);
774 // ld_ptr, set_hi, set
775 __ ld_ptr(G3_scratch, G5_method, G5_method);
776 }
777 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
778 __ callr(G3_scratch, G0);
779 // the peephole pass fills the delay slot
780 }
781
782
783 // load with 32-bit displacement
784 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
785 int load_offset = code_offset();
786 if (Assembler::is_simm13(disp)) {
787 if (info != NULL) add_debug_info_for_null_check_here(info);
788 switch(ld_type) {
789 case T_BOOLEAN: // fall through
790 case T_BYTE : __ ldsb(s, disp, d); break;
791 case T_CHAR : __ lduh(s, disp, d); break;
792 case T_SHORT : __ ldsh(s, disp, d); break;
793 case T_INT : __ ld(s, disp, d); break;
794 case T_ADDRESS:// fall through
795 case T_ARRAY : // fall through
796 case T_OBJECT: __ ld_ptr(s, disp, d); break;
797 default : ShouldNotReachHere();
798 }
799 } else {
800 __ set(disp, O7);
801 if (info != NULL) add_debug_info_for_null_check_here(info);
802 load_offset = code_offset();
803 switch(ld_type) {
804 case T_BOOLEAN: // fall through
805 case T_BYTE : __ ldsb(s, O7, d); break;
806 case T_CHAR : __ lduh(s, O7, d); break;
807 case T_SHORT : __ ldsh(s, O7, d); break;
808 case T_INT : __ ld(s, O7, d); break;
809 case T_ADDRESS:// fall through
810 case T_ARRAY : // fall through
811 case T_OBJECT: __ ld_ptr(s, O7, d); break;
812 default : ShouldNotReachHere();
813 }
814 }
815 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
816 return load_offset;
817 }
818
819
820 // store with 32-bit displacement
821 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
822 if (Assembler::is_simm13(offset)) {
823 if (info != NULL) add_debug_info_for_null_check_here(info);
824 switch (type) {
825 case T_BOOLEAN: // fall through
826 case T_BYTE : __ stb(value, base, offset); break;
827 case T_CHAR : __ sth(value, base, offset); break;
828 case T_SHORT : __ sth(value, base, offset); break;
829 case T_INT : __ stw(value, base, offset); break;
830 case T_ADDRESS:// fall through
831 case T_ARRAY : // fall through
832 case T_OBJECT: __ st_ptr(value, base, offset); break;
833 default : ShouldNotReachHere();
834 }
835 } else {
836 __ set(offset, O7);
837 if (info != NULL) add_debug_info_for_null_check_here(info);
838 switch (type) {
839 case T_BOOLEAN: // fall through
840 case T_BYTE : __ stb(value, base, O7); break;
841 case T_CHAR : __ sth(value, base, O7); break;
842 case T_SHORT : __ sth(value, base, O7); break;
843 case T_INT : __ stw(value, base, O7); break;
844 case T_ADDRESS:// fall through
845 case T_ARRAY : //fall through
846 case T_OBJECT: __ st_ptr(value, base, O7); break;
847 default : ShouldNotReachHere();
848 }
849 }
850 // Note: Do the store before verification as the code might be patched!
851 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
852 }
853
854
855 // load float with 32-bit displacement
856 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
857 FloatRegisterImpl::Width w;
858 switch(ld_type) {
859 case T_FLOAT : w = FloatRegisterImpl::S; break;
860 case T_DOUBLE: w = FloatRegisterImpl::D; break;
861 default : ShouldNotReachHere();
862 }
863
864 if (Assembler::is_simm13(disp)) {
865 if (info != NULL) add_debug_info_for_null_check_here(info);
866 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
867 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
868 __ ldf(FloatRegisterImpl::S, s, disp , d);
869 } else {
870 __ ldf(w, s, disp, d);
871 }
872 } else {
873 __ set(disp, O7);
874 if (info != NULL) add_debug_info_for_null_check_here(info);
875 __ ldf(w, s, O7, d);
876 }
877 }
878
879
880 // store float with 32-bit displacement
881 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
882 FloatRegisterImpl::Width w;
883 switch(type) {
884 case T_FLOAT : w = FloatRegisterImpl::S; break;
885 case T_DOUBLE: w = FloatRegisterImpl::D; break;
886 default : ShouldNotReachHere();
887 }
888
889 if (Assembler::is_simm13(offset)) {
890 if (info != NULL) add_debug_info_for_null_check_here(info);
891 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
892 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
893 __ stf(FloatRegisterImpl::S, value , base, offset);
894 } else {
895 __ stf(w, value, base, offset);
896 }
897 } else {
898 __ set(offset, O7);
899 if (info != NULL) add_debug_info_for_null_check_here(info);
900 __ stf(w, value, O7, base);
901 }
902 }
903
904
905 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
906 int store_offset;
907 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
908 assert(!unaligned, "can't handle this");
909 // for offsets larger than a simm13 we setup the offset in O7
910 __ set(offset, O7);
911 store_offset = store(from_reg, base, O7, type);
912 } else {
913 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
914 store_offset = code_offset();
915 switch (type) {
916 case T_BOOLEAN: // fall through
917 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
918 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
919 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
920 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
921 case T_LONG :
922 #ifdef _LP64
923 if (unaligned || PatchALot) {
924 __ srax(from_reg->as_register_lo(), 32, O7);
925 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
926 __ stw(O7, base, offset + hi_word_offset_in_bytes);
927 } else {
928 __ stx(from_reg->as_register_lo(), base, offset);
929 }
930 #else
931 assert(Assembler::is_simm13(offset + 4), "must be");
932 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
933 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
934 #endif
935 break;
936 case T_ADDRESS:// fall through
937 case T_ARRAY : // fall through
938 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
939 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
940 case T_DOUBLE:
941 {
942 FloatRegister reg = from_reg->as_double_reg();
943 // split unaligned stores
944 if (unaligned || PatchALot) {
945 assert(Assembler::is_simm13(offset + 4), "must be");
946 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
947 __ stf(FloatRegisterImpl::S, reg, base, offset);
948 } else {
949 __ stf(FloatRegisterImpl::D, reg, base, offset);
950 }
951 break;
952 }
953 default : ShouldNotReachHere();
954 }
955 }
956 return store_offset;
957 }
958
959
960 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
961 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
962 int store_offset = code_offset();
963 switch (type) {
964 case T_BOOLEAN: // fall through
965 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
966 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
967 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
968 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
969 case T_LONG :
970 #ifdef _LP64
971 __ stx(from_reg->as_register_lo(), base, disp);
972 #else
973 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
974 __ std(from_reg->as_register_hi(), base, disp);
975 #endif
976 break;
977 case T_ADDRESS:// fall through
978 case T_ARRAY : // fall through
979 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
980 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
981 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
982 default : ShouldNotReachHere();
983 }
984 return store_offset;
985 }
986
987
988 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
989 int load_offset;
990 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
991 assert(base != O7, "destroying register");
992 assert(!unaligned, "can't handle this");
993 // for offsets larger than a simm13 we setup the offset in O7
994 __ set(offset, O7);
995 load_offset = load(base, O7, to_reg, type);
996 } else {
997 load_offset = code_offset();
998 switch(type) {
999 case T_BOOLEAN: // fall through
1000 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
1001 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
1002 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
1003 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
1004 case T_LONG :
1005 if (!unaligned) {
1006 #ifdef _LP64
1007 __ ldx(base, offset, to_reg->as_register_lo());
1008 #else
1009 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1010 "must be sequential");
1011 __ ldd(base, offset, to_reg->as_register_hi());
1012 #endif
1013 } else {
1014 #ifdef _LP64
1015 assert(base != to_reg->as_register_lo(), "can't handle this");
1016 assert(O7 != to_reg->as_register_lo(), "can't handle this");
1017 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
1018 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
1019 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
1020 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
1021 #else
1022 if (base == to_reg->as_register_lo()) {
1023 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1024 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1025 } else {
1026 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1027 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1028 }
1029 #endif
1030 }
1031 break;
1032 case T_ADDRESS:// fall through
1033 case T_ARRAY : // fall through
1034 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
1035 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
1036 case T_DOUBLE:
1037 {
1038 FloatRegister reg = to_reg->as_double_reg();
1039 // split unaligned loads
1040 if (unaligned || PatchALot) {
1041 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
1042 __ ldf(FloatRegisterImpl::S, base, offset, reg);
1043 } else {
1044 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
1045 }
1046 break;
1047 }
1048 default : ShouldNotReachHere();
1049 }
1050 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1051 }
1052 return load_offset;
1053 }
1054
1055
1056 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
1057 int load_offset = code_offset();
1058 switch(type) {
1059 case T_BOOLEAN: // fall through
1060 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1061 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1062 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1063 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1064 case T_ADDRESS:// fall through
1065 case T_ARRAY : // fall through
1066 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1067 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1068 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1069 case T_LONG :
1070 #ifdef _LP64
1071 __ ldx(base, disp, to_reg->as_register_lo());
1072 #else
1073 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1074 "must be sequential");
1075 __ ldd(base, disp, to_reg->as_register_hi());
1076 #endif
1077 break;
1078 default : ShouldNotReachHere();
1079 }
1080 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1081 return load_offset;
1082 }
1083
1084
1085 // load/store with an Address
1086 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1087 load(a.base(), a.disp() + offset, d, ld_type, info);
1088 }
1089
1090
1091 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1092 store(value, dest.base(), dest.disp() + offset, type, info);
1093 }
1094
1095
1096 // loadf/storef with an Address
1097 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1098 load(a.base(), a.disp() + offset, d, ld_type, info);
1099 }
1100
1101
1102 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1103 store(value, dest.base(), dest.disp() + offset, type, info);
1104 }
1105
1106
1107 // load/store with an Address
1108 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1109 load(as_Address(a), d, ld_type, info);
1110 }
1111
1112
1113 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1114 store(value, as_Address(dest), type, info);
1115 }
1116
1117
1118 // loadf/storef with an Address
1119 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1120 load(as_Address(a), d, ld_type, info);
1121 }
1122
1123
1124 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1125 store(value, as_Address(dest), type, info);
1126 }
1127
1128
1129 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1130 LIR_Const* c = src->as_constant_ptr();
1131 switch (c->type()) {
1132 case T_INT:
1133 case T_FLOAT:
1134 case T_ADDRESS: {
1135 Register src_reg = O7;
1136 int value = c->as_jint_bits();
1137 if (value == 0) {
1138 src_reg = G0;
1139 } else {
1140 __ set(value, O7);
1141 }
1142 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1143 __ stw(src_reg, addr.base(), addr.disp());
1144 break;
1145 }
1146 case T_OBJECT: {
1147 Register src_reg = O7;
1148 jobject2reg(c->as_jobject(), src_reg);
1149 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1150 __ st_ptr(src_reg, addr.base(), addr.disp());
1151 break;
1152 }
1153 case T_LONG:
1154 case T_DOUBLE: {
1155 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1156
1157 Register tmp = O7;
1158 int value_lo = c->as_jint_lo_bits();
1159 if (value_lo == 0) {
1160 tmp = G0;
1161 } else {
1162 __ set(value_lo, O7);
1163 }
1164 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1165 int value_hi = c->as_jint_hi_bits();
1166 if (value_hi == 0) {
1167 tmp = G0;
1168 } else {
1169 __ set(value_hi, O7);
1170 }
1171 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1172 break;
1173 }
1174 default:
1175 Unimplemented();
1176 }
1177 }
1178
1179
1180 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1181 LIR_Const* c = src->as_constant_ptr();
1182 LIR_Address* addr = dest->as_address_ptr();
1183 Register base = addr->base()->as_pointer_register();
1184
1185 if (info != NULL) {
1186 add_debug_info_for_null_check_here(info);
1187 }
1188 switch (c->type()) {
1189 case T_INT:
1190 case T_FLOAT:
1191 case T_ADDRESS: {
1192 LIR_Opr tmp = FrameMap::O7_opr;
1193 int value = c->as_jint_bits();
1194 if (value == 0) {
1195 tmp = FrameMap::G0_opr;
1196 } else if (Assembler::is_simm13(value)) {
1197 __ set(value, O7);
1198 }
1199 if (addr->index()->is_valid()) {
1200 assert(addr->disp() == 0, "must be zero");
1201 store(tmp, base, addr->index()->as_pointer_register(), type);
1202 } else {
1203 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1204 store(tmp, base, addr->disp(), type);
1205 }
1206 break;
1207 }
1208 case T_LONG:
1209 case T_DOUBLE: {
1210 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1211 assert(Assembler::is_simm13(addr->disp()) &&
1212 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1213
1214 Register tmp = O7;
1215 int value_lo = c->as_jint_lo_bits();
1216 if (value_lo == 0) {
1217 tmp = G0;
1218 } else {
1219 __ set(value_lo, O7);
1220 }
1221 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1222 int value_hi = c->as_jint_hi_bits();
1223 if (value_hi == 0) {
1224 tmp = G0;
1225 } else {
1226 __ set(value_hi, O7);
1227 }
1228 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1229 break;
1230 }
1231 case T_OBJECT: {
1232 jobject obj = c->as_jobject();
1233 LIR_Opr tmp;
1234 if (obj == NULL) {
1235 tmp = FrameMap::G0_opr;
1236 } else {
1237 tmp = FrameMap::O7_opr;
1238 jobject2reg(c->as_jobject(), O7);
1239 }
1240 // handle either reg+reg or reg+disp address
1241 if (addr->index()->is_valid()) {
1242 assert(addr->disp() == 0, "must be zero");
1243 store(tmp, base, addr->index()->as_pointer_register(), type);
1244 } else {
1245 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1246 store(tmp, base, addr->disp(), type);
1247 }
1248
1249 break;
1250 }
1251 default:
1252 Unimplemented();
1253 }
1254 }
1255
1256
1257 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1258 LIR_Const* c = src->as_constant_ptr();
1259 LIR_Opr to_reg = dest;
1260
1261 switch (c->type()) {
1262 case T_INT:
1263 case T_ADDRESS:
1264 {
1265 jint con = c->as_jint();
1266 if (to_reg->is_single_cpu()) {
1267 assert(patch_code == lir_patch_none, "no patching handled here");
1268 __ set(con, to_reg->as_register());
1269 } else {
1270 ShouldNotReachHere();
1271 assert(to_reg->is_single_fpu(), "wrong register kind");
1272
1273 __ set(con, O7);
1274 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1275 __ st(O7, temp_slot);
1276 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1277 }
1278 }
1279 break;
1280
1281 case T_LONG:
1282 {
1283 jlong con = c->as_jlong();
1284
1285 if (to_reg->is_double_cpu()) {
1286 #ifdef _LP64
1287 __ set(con, to_reg->as_register_lo());
1288 #else
1289 __ set(low(con), to_reg->as_register_lo());
1290 __ set(high(con), to_reg->as_register_hi());
1291 #endif
1292 #ifdef _LP64
1293 } else if (to_reg->is_single_cpu()) {
1294 __ set(con, to_reg->as_register());
1295 #endif
1296 } else {
1297 ShouldNotReachHere();
1298 assert(to_reg->is_double_fpu(), "wrong register kind");
1299 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1300 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1301 __ set(low(con), O7);
1302 __ st(O7, temp_slot_lo);
1303 __ set(high(con), O7);
1304 __ st(O7, temp_slot_hi);
1305 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1306 }
1307 }
1308 break;
1309
1310 case T_OBJECT:
1311 {
1312 if (patch_code == lir_patch_none) {
1313 jobject2reg(c->as_jobject(), to_reg->as_register());
1314 } else {
1315 jobject2reg_with_patching(to_reg->as_register(), info);
1316 }
1317 }
1318 break;
1319
1320 case T_FLOAT:
1321 {
1322 address const_addr = __ float_constant(c->as_jfloat());
1323 if (const_addr == NULL) {
1324 bailout("const section overflow");
1325 break;
1326 }
1327 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1328 AddressLiteral const_addrlit(const_addr, rspec);
1329 if (to_reg->is_single_fpu()) {
1330 __ patchable_sethi(const_addrlit, O7);
1331 __ relocate(rspec);
1332 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1333
1334 } else {
1335 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1336
1337 __ set(const_addrlit, O7);
1338 load(O7, 0, to_reg->as_register(), T_INT);
1339 }
1340 }
1341 break;
1342
1343 case T_DOUBLE:
1344 {
1345 address const_addr = __ double_constant(c->as_jdouble());
1346 if (const_addr == NULL) {
1347 bailout("const section overflow");
1348 break;
1349 }
1350 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1351
1352 if (to_reg->is_double_fpu()) {
1353 AddressLiteral const_addrlit(const_addr, rspec);
1354 __ patchable_sethi(const_addrlit, O7);
1355 __ relocate(rspec);
1356 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1357 } else {
1358 assert(to_reg->is_double_cpu(), "Must be a long register.");
1359 #ifdef _LP64
1360 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1361 #else
1362 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1363 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1364 #endif
1365 }
1366
1367 }
1368 break;
1369
1370 default:
1371 ShouldNotReachHere();
1372 }
1373 }
1374
1375 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1376 Register reg = addr->base()->as_register();
1377 return Address(reg, addr->disp());
1378 }
1379
1380
1381 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1382 switch (type) {
1383 case T_INT:
1384 case T_FLOAT: {
1385 Register tmp = O7;
1386 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1387 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1388 __ lduw(from.base(), from.disp(), tmp);
1389 __ stw(tmp, to.base(), to.disp());
1390 break;
1391 }
1392 case T_OBJECT: {
1393 Register tmp = O7;
1394 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1395 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1396 __ ld_ptr(from.base(), from.disp(), tmp);
1397 __ st_ptr(tmp, to.base(), to.disp());
1398 break;
1399 }
1400 case T_LONG:
1401 case T_DOUBLE: {
1402 Register tmp = O7;
1403 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1404 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1405 __ lduw(from.base(), from.disp(), tmp);
1406 __ stw(tmp, to.base(), to.disp());
1407 __ lduw(from.base(), from.disp() + 4, tmp);
1408 __ stw(tmp, to.base(), to.disp() + 4);
1409 break;
1410 }
1411
1412 default:
1413 ShouldNotReachHere();
1414 }
1415 }
1416
1417
1418 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1419 Address base = as_Address(addr);
1420 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1421 }
1422
1423
1424 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1425 Address base = as_Address(addr);
1426 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1427 }
1428
1429
1430 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1431 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1432
1433 LIR_Address* addr = src_opr->as_address_ptr();
1434 LIR_Opr to_reg = dest;
1435
1436 Register src = addr->base()->as_pointer_register();
1437 Register disp_reg = noreg;
1438 int disp_value = addr->disp();
1439 bool needs_patching = (patch_code != lir_patch_none);
1440
1441 if (addr->base()->type() == T_OBJECT) {
1442 __ verify_oop(src);
1443 }
1444
1445 PatchingStub* patch = NULL;
1446 if (needs_patching) {
1447 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1448 assert(!to_reg->is_double_cpu() ||
1449 patch_code == lir_patch_none ||
1450 patch_code == lir_patch_normal, "patching doesn't match register");
1451 }
1452
1453 if (addr->index()->is_illegal()) {
1454 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1455 if (needs_patching) {
1456 __ patchable_set(0, O7);
1457 } else {
1458 __ set(disp_value, O7);
1459 }
1460 disp_reg = O7;
1461 }
1462 } else if (unaligned || PatchALot) {
1463 __ add(src, addr->index()->as_register(), O7);
1464 src = O7;
1465 } else {
1466 disp_reg = addr->index()->as_pointer_register();
1467 assert(disp_value == 0, "can't handle 3 operand addresses");
1468 }
1469
1470 // remember the offset of the load. The patching_epilog must be done
1471 // before the call to add_debug_info, otherwise the PcDescs don't get
1472 // entered in increasing order.
1473 int offset = code_offset();
1474
1475 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1476 if (disp_reg == noreg) {
1477 offset = load(src, disp_value, to_reg, type, unaligned);
1478 } else {
1479 assert(!unaligned, "can't handle this");
1480 offset = load(src, disp_reg, to_reg, type);
1481 }
1482
1483 if (patch != NULL) {
1484 patching_epilog(patch, patch_code, src, info);
1485 }
1486
1487 if (info != NULL) add_debug_info_for_null_check(offset, info);
1488 }
1489
1490
1491 void LIR_Assembler::prefetchr(LIR_Opr src) {
1492 LIR_Address* addr = src->as_address_ptr();
1493 Address from_addr = as_Address(addr);
1494
1495 if (VM_Version::has_v9()) {
1496 __ prefetch(from_addr, Assembler::severalReads);
1497 }
1498 }
1499
1500
1501 void LIR_Assembler::prefetchw(LIR_Opr src) {
1502 LIR_Address* addr = src->as_address_ptr();
1503 Address from_addr = as_Address(addr);
1504
1505 if (VM_Version::has_v9()) {
1506 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1507 }
1508 }
1509
1510
1511 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1512 Address addr;
1513 if (src->is_single_word()) {
1514 addr = frame_map()->address_for_slot(src->single_stack_ix());
1515 } else if (src->is_double_word()) {
1516 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1517 }
1518
1519 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1520 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1521 }
1522
1523
1524 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1525 Address addr;
1526 if (dest->is_single_word()) {
1527 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1528 } else if (dest->is_double_word()) {
1529 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1530 }
1531 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1532 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1533 }
1534
1535
1536 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1537 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1538 if (from_reg->is_double_fpu()) {
1539 // double to double moves
1540 assert(to_reg->is_double_fpu(), "should match");
1541 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1542 } else {
1543 // float to float moves
1544 assert(to_reg->is_single_fpu(), "should match");
1545 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1546 }
1547 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1548 if (from_reg->is_double_cpu()) {
1549 #ifdef _LP64
1550 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1551 #else
1552 assert(to_reg->is_double_cpu() &&
1553 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1554 from_reg->as_register_lo() != to_reg->as_register_hi(),
1555 "should both be long and not overlap");
1556 // long to long moves
1557 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1558 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1559 #endif
1560 #ifdef _LP64
1561 } else if (to_reg->is_double_cpu()) {
1562 // int to int moves
1563 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1564 #endif
1565 } else {
1566 // int to int moves
1567 __ mov(from_reg->as_register(), to_reg->as_register());
1568 }
1569 } else {
1570 ShouldNotReachHere();
1571 }
1572 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1573 __ verify_oop(to_reg->as_register());
1574 }
1575 }
1576
1577
1578 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1579 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1580 bool unaligned) {
1581 LIR_Address* addr = dest->as_address_ptr();
1582
1583 Register src = addr->base()->as_pointer_register();
1584 Register disp_reg = noreg;
1585 int disp_value = addr->disp();
1586 bool needs_patching = (patch_code != lir_patch_none);
1587
1588 if (addr->base()->is_oop_register()) {
1589 __ verify_oop(src);
1590 }
1591
1592 PatchingStub* patch = NULL;
1593 if (needs_patching) {
1594 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1595 assert(!from_reg->is_double_cpu() ||
1596 patch_code == lir_patch_none ||
1597 patch_code == lir_patch_normal, "patching doesn't match register");
1598 }
1599
1600 if (addr->index()->is_illegal()) {
1601 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1602 if (needs_patching) {
1603 __ patchable_set(0, O7);
1604 } else {
1605 __ set(disp_value, O7);
1606 }
1607 disp_reg = O7;
1608 }
1609 } else if (unaligned || PatchALot) {
1610 __ add(src, addr->index()->as_register(), O7);
1611 src = O7;
1612 } else {
1613 disp_reg = addr->index()->as_pointer_register();
1614 assert(disp_value == 0, "can't handle 3 operand addresses");
1615 }
1616
1617 // remember the offset of the store. The patching_epilog must be done
1618 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1619 // entered in increasing order.
1620 int offset;
1621
1622 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1623 if (disp_reg == noreg) {
1624 offset = store(from_reg, src, disp_value, type, unaligned);
1625 } else {
1626 assert(!unaligned, "can't handle this");
1627 offset = store(from_reg, src, disp_reg, type);
1628 }
1629
1630 if (patch != NULL) {
1631 patching_epilog(patch, patch_code, src, info);
1632 }
1633
1634 if (info != NULL) add_debug_info_for_null_check(offset, info);
1635 }
1636
1637
1638 void LIR_Assembler::return_op(LIR_Opr result) {
1639 // the poll may need a register so just pick one that isn't the return register
1640 #if defined(TIERED) && !defined(_LP64)
1641 if (result->type_field() == LIR_OprDesc::long_type) {
1642 // Must move the result to G1
1643 // Must leave proper result in O0,O1 and G1 (TIERED only)
1644 __ sllx(I0, 32, G1); // Shift bits into high G1
1645 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1646 __ or3 (I1, G1, G1); // OR 64 bits into G1
1647 #ifdef ASSERT
1648 // mangle it so any problems will show up
1649 __ set(0xdeadbeef, I0);
1650 __ set(0xdeadbeef, I1);
1651 #endif
1652 }
1653 #endif // TIERED
1654 __ set((intptr_t)os::get_polling_page(), L0);
1655 __ relocate(relocInfo::poll_return_type);
1656 __ ld_ptr(L0, 0, G0);
1657 __ ret();
1658 __ delayed()->restore();
1659 }
1660
1661
1662 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1663 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1664 if (info != NULL) {
1665 add_debug_info_for_branch(info);
1666 } else {
1667 __ relocate(relocInfo::poll_type);
1668 }
1669
1670 int offset = __ offset();
1671 __ ld_ptr(tmp->as_register(), 0, G0);
1672
1673 return offset;
1674 }
1675
1676
1677 void LIR_Assembler::emit_static_call_stub() {
1678 address call_pc = __ pc();
1679 address stub = __ start_a_stub(call_stub_size);
1680 if (stub == NULL) {
1681 bailout("static call stub overflow");
1682 return;
1683 }
1684
1685 int start = __ offset();
1686 __ relocate(static_stub_Relocation::spec(call_pc));
1687
1688 __ set_oop(NULL, G5);
1689 // must be set to -1 at code generation time
1690 AddressLiteral addrlit(-1);
1691 __ jump_to(addrlit, G3);
1692 __ delayed()->nop();
1693
1694 assert(__ offset() - start <= call_stub_size, "stub too big");
1695 __ end_a_stub();
1696 }
1697
1698
1699 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1700 if (opr1->is_single_fpu()) {
1701 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1702 } else if (opr1->is_double_fpu()) {
1703 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1704 } else if (opr1->is_single_cpu()) {
1705 if (opr2->is_constant()) {
1706 switch (opr2->as_constant_ptr()->type()) {
1707 case T_INT:
1708 { jint con = opr2->as_constant_ptr()->as_jint();
1709 if (Assembler::is_simm13(con)) {
1710 __ cmp(opr1->as_register(), con);
1711 } else {
1712 __ set(con, O7);
1713 __ cmp(opr1->as_register(), O7);
1714 }
1715 }
1716 break;
1717
1718 case T_OBJECT:
1719 // there are only equal/notequal comparisions on objects
1720 { jobject con = opr2->as_constant_ptr()->as_jobject();
1721 if (con == NULL) {
1722 __ cmp(opr1->as_register(), 0);
1723 } else {
1724 jobject2reg(con, O7);
1725 __ cmp(opr1->as_register(), O7);
1726 }
1727 }
1728 break;
1729
1730 default:
1731 ShouldNotReachHere();
1732 break;
1733 }
1734 } else {
1735 if (opr2->is_address()) {
1736 LIR_Address * addr = opr2->as_address_ptr();
1737 BasicType type = addr->type();
1738 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1739 else __ ld(as_Address(addr), O7);
1740 __ cmp(opr1->as_register(), O7);
1741 } else {
1742 __ cmp(opr1->as_register(), opr2->as_register());
1743 }
1744 }
1745 } else if (opr1->is_double_cpu()) {
1746 Register xlo = opr1->as_register_lo();
1747 Register xhi = opr1->as_register_hi();
1748 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1749 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1750 #ifdef _LP64
1751 __ orcc(xhi, G0, G0);
1752 #else
1753 __ orcc(xhi, xlo, G0);
1754 #endif
1755 } else if (opr2->is_register()) {
1756 Register ylo = opr2->as_register_lo();
1757 Register yhi = opr2->as_register_hi();
1758 #ifdef _LP64
1759 __ cmp(xlo, ylo);
1760 #else
1761 __ subcc(xlo, ylo, xlo);
1762 __ subccc(xhi, yhi, xhi);
1763 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1764 __ orcc(xhi, xlo, G0);
1765 }
1766 #endif
1767 } else {
1768 ShouldNotReachHere();
1769 }
1770 } else if (opr1->is_address()) {
1771 LIR_Address * addr = opr1->as_address_ptr();
1772 BasicType type = addr->type();
1773 assert (opr2->is_constant(), "Checking");
1774 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1775 else __ ld(as_Address(addr), O7);
1776 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1777 } else {
1778 ShouldNotReachHere();
1779 }
1780 }
1781
1782
1783 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1784 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1785 bool is_unordered_less = (code == lir_ucmp_fd2i);
1786 if (left->is_single_fpu()) {
1787 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1788 } else if (left->is_double_fpu()) {
1789 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1790 } else {
1791 ShouldNotReachHere();
1792 }
1793 } else if (code == lir_cmp_l2i) {
1794 #ifdef _LP64
1795 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1796 #else
1797 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1798 right->as_register_hi(), right->as_register_lo(),
1799 dst->as_register());
1800 #endif
1801 } else {
1802 ShouldNotReachHere();
1803 }
1804 }
1805
1806
1807 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1808
1809 Assembler::Condition acond;
1810 switch (condition) {
1811 case lir_cond_equal: acond = Assembler::equal; break;
1812 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1813 case lir_cond_less: acond = Assembler::less; break;
1814 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1815 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1816 case lir_cond_greater: acond = Assembler::greater; break;
1817 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1818 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1819 default: ShouldNotReachHere();
1820 };
1821
1822 if (opr1->is_constant() && opr1->type() == T_INT) {
1823 Register dest = result->as_register();
1824 // load up first part of constant before branch
1825 // and do the rest in the delay slot.
1826 if (!Assembler::is_simm13(opr1->as_jint())) {
1827 __ sethi(opr1->as_jint(), dest);
1828 }
1829 } else if (opr1->is_constant()) {
1830 const2reg(opr1, result, lir_patch_none, NULL);
1831 } else if (opr1->is_register()) {
1832 reg2reg(opr1, result);
1833 } else if (opr1->is_stack()) {
1834 stack2reg(opr1, result, result->type());
1835 } else {
1836 ShouldNotReachHere();
1837 }
1838 Label skip;
1839 __ br(acond, false, Assembler::pt, skip);
1840 if (opr1->is_constant() && opr1->type() == T_INT) {
1841 Register dest = result->as_register();
1842 if (Assembler::is_simm13(opr1->as_jint())) {
1843 __ delayed()->or3(G0, opr1->as_jint(), dest);
1844 } else {
1845 // the sethi has been done above, so just put in the low 10 bits
1846 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1847 }
1848 } else {
1849 // can't do anything useful in the delay slot
1850 __ delayed()->nop();
1851 }
1852 if (opr2->is_constant()) {
1853 const2reg(opr2, result, lir_patch_none, NULL);
1854 } else if (opr2->is_register()) {
1855 reg2reg(opr2, result);
1856 } else if (opr2->is_stack()) {
1857 stack2reg(opr2, result, result->type());
1858 } else {
1859 ShouldNotReachHere();
1860 }
1861 __ bind(skip);
1862 }
1863
1864
1865 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1866 assert(info == NULL, "unused on this code path");
1867 assert(left->is_register(), "wrong items state");
1868 assert(dest->is_register(), "wrong items state");
1869
1870 if (right->is_register()) {
1871 if (dest->is_float_kind()) {
1872
1873 FloatRegister lreg, rreg, res;
1874 FloatRegisterImpl::Width w;
1875 if (right->is_single_fpu()) {
1876 w = FloatRegisterImpl::S;
1877 lreg = left->as_float_reg();
1878 rreg = right->as_float_reg();
1879 res = dest->as_float_reg();
1880 } else {
1881 w = FloatRegisterImpl::D;
1882 lreg = left->as_double_reg();
1883 rreg = right->as_double_reg();
1884 res = dest->as_double_reg();
1885 }
1886
1887 switch (code) {
1888 case lir_add: __ fadd(w, lreg, rreg, res); break;
1889 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1890 case lir_mul: // fall through
1891 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1892 case lir_div: // fall through
1893 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1894 default: ShouldNotReachHere();
1895 }
1896
1897 } else if (dest->is_double_cpu()) {
1898 #ifdef _LP64
1899 Register dst_lo = dest->as_register_lo();
1900 Register op1_lo = left->as_pointer_register();
1901 Register op2_lo = right->as_pointer_register();
1902
1903 switch (code) {
1904 case lir_add:
1905 __ add(op1_lo, op2_lo, dst_lo);
1906 break;
1907
1908 case lir_sub:
1909 __ sub(op1_lo, op2_lo, dst_lo);
1910 break;
1911
1912 default: ShouldNotReachHere();
1913 }
1914 #else
1915 Register op1_lo = left->as_register_lo();
1916 Register op1_hi = left->as_register_hi();
1917 Register op2_lo = right->as_register_lo();
1918 Register op2_hi = right->as_register_hi();
1919 Register dst_lo = dest->as_register_lo();
1920 Register dst_hi = dest->as_register_hi();
1921
1922 switch (code) {
1923 case lir_add:
1924 __ addcc(op1_lo, op2_lo, dst_lo);
1925 __ addc (op1_hi, op2_hi, dst_hi);
1926 break;
1927
1928 case lir_sub:
1929 __ subcc(op1_lo, op2_lo, dst_lo);
1930 __ subc (op1_hi, op2_hi, dst_hi);
1931 break;
1932
1933 default: ShouldNotReachHere();
1934 }
1935 #endif
1936 } else {
1937 assert (right->is_single_cpu(), "Just Checking");
1938
1939 Register lreg = left->as_register();
1940 Register res = dest->as_register();
1941 Register rreg = right->as_register();
1942 switch (code) {
1943 case lir_add: __ add (lreg, rreg, res); break;
1944 case lir_sub: __ sub (lreg, rreg, res); break;
1945 case lir_mul: __ mult (lreg, rreg, res); break;
1946 default: ShouldNotReachHere();
1947 }
1948 }
1949 } else {
1950 assert (right->is_constant(), "must be constant");
1951
1952 if (dest->is_single_cpu()) {
1953 Register lreg = left->as_register();
1954 Register res = dest->as_register();
1955 int simm13 = right->as_constant_ptr()->as_jint();
1956
1957 switch (code) {
1958 case lir_add: __ add (lreg, simm13, res); break;
1959 case lir_sub: __ sub (lreg, simm13, res); break;
1960 case lir_mul: __ mult (lreg, simm13, res); break;
1961 default: ShouldNotReachHere();
1962 }
1963 } else {
1964 Register lreg = left->as_pointer_register();
1965 Register res = dest->as_register_lo();
1966 long con = right->as_constant_ptr()->as_jlong();
1967 assert(Assembler::is_simm13(con), "must be simm13");
1968
1969 switch (code) {
1970 case lir_add: __ add (lreg, (int)con, res); break;
1971 case lir_sub: __ sub (lreg, (int)con, res); break;
1972 case lir_mul: __ mult (lreg, (int)con, res); break;
1973 default: ShouldNotReachHere();
1974 }
1975 }
1976 }
1977 }
1978
1979
1980 void LIR_Assembler::fpop() {
1981 // do nothing
1982 }
1983
1984
1985 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1986 switch (code) {
1987 case lir_sin:
1988 case lir_tan:
1989 case lir_cos: {
1990 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1991 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1992 break;
1993 }
1994 case lir_sqrt: {
1995 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1996 FloatRegister src_reg = value->as_double_reg();
1997 FloatRegister dst_reg = dest->as_double_reg();
1998 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1999 break;
2000 }
2001 case lir_abs: {
2002 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
2003 FloatRegister src_reg = value->as_double_reg();
2004 FloatRegister dst_reg = dest->as_double_reg();
2005 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
2006 break;
2007 }
2008 default: {
2009 ShouldNotReachHere();
2010 break;
2011 }
2012 }
2013 }
2014
2015
2016 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
2017 if (right->is_constant()) {
2018 if (dest->is_single_cpu()) {
2019 int simm13 = right->as_constant_ptr()->as_jint();
2020 switch (code) {
2021 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
2022 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
2023 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
2024 default: ShouldNotReachHere();
2025 }
2026 } else {
2027 long c = right->as_constant_ptr()->as_jlong();
2028 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
2029 int simm13 = (int)c;
2030 switch (code) {
2031 case lir_logic_and:
2032 #ifndef _LP64
2033 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
2034 #endif
2035 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
2036 break;
2037
2038 case lir_logic_or:
2039 #ifndef _LP64
2040 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
2041 #endif
2042 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
2043 break;
2044
2045 case lir_logic_xor:
2046 #ifndef _LP64
2047 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
2048 #endif
2049 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
2050 break;
2051
2052 default: ShouldNotReachHere();
2053 }
2054 }
2055 } else {
2056 assert(right->is_register(), "right should be in register");
2057
2058 if (dest->is_single_cpu()) {
2059 switch (code) {
2060 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
2061 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
2062 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
2063 default: ShouldNotReachHere();
2064 }
2065 } else {
2066 #ifdef _LP64
2067 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
2068 left->as_register_lo();
2069 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
2070 right->as_register_lo();
2071
2072 switch (code) {
2073 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2074 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2075 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2076 default: ShouldNotReachHere();
2077 }
2078 #else
2079 switch (code) {
2080 case lir_logic_and:
2081 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2082 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2083 break;
2084
2085 case lir_logic_or:
2086 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2087 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2088 break;
2089
2090 case lir_logic_xor:
2091 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2092 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2093 break;
2094
2095 default: ShouldNotReachHere();
2096 }
2097 #endif
2098 }
2099 }
2100 }
2101
2102
2103 int LIR_Assembler::shift_amount(BasicType t) {
2104 int elem_size = type2aelembytes(t);
2105 switch (elem_size) {
2106 case 1 : return 0;
2107 case 2 : return 1;
2108 case 4 : return 2;
2109 case 8 : return 3;
2110 }
2111 ShouldNotReachHere();
2112 return -1;
2113 }
2114
2115
2116 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2117 assert(exceptionOop->as_register() == Oexception, "should match");
2118 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
2119
2120 info->add_register_oop(exceptionOop);
2121
2122 // reuse the debug info from the safepoint poll for the throw op itself
2123 address pc_for_athrow = __ pc();
2124 int pc_for_athrow_offset = __ offset();
2125 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2126 __ set(pc_for_athrow, Oissuing_pc, rspec);
2127 add_call_info(pc_for_athrow_offset, info); // for exception handler
2128
2129 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2130 __ delayed()->nop();
2131 }
2132
2133
2134 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2135 assert(exceptionOop->as_register() == Oexception, "should match");
2136
2137 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
2138 __ delayed()->nop();
2139 }
2140
2141
2142 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2143 Register src = op->src()->as_register();
2144 Register dst = op->dst()->as_register();
2145 Register src_pos = op->src_pos()->as_register();
2146 Register dst_pos = op->dst_pos()->as_register();
2147 Register length = op->length()->as_register();
2148 Register tmp = op->tmp()->as_register();
2149 Register tmp2 = O7;
2150
2151 int flags = op->flags();
2152 ciArrayKlass* default_type = op->expected_type();
2153 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2154 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2155
2156 // set up the arraycopy stub information
2157 ArrayCopyStub* stub = op->stub();
2158
2159 // always do stub if no type information is available. it's ok if
2160 // the known type isn't loaded since the code sanity checks
2161 // in debug mode and the type isn't required when we know the exact type
2162 // also check that the type is an array type.
2163 // We also, for now, always call the stub if the barrier set requires a
2164 // write_ref_pre barrier (which the stub does, but none of the optimized
2165 // cases currently does).
2166 if (op->expected_type() == NULL ||
2167 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2168 __ mov(src, O0);
2169 __ mov(src_pos, O1);
2170 __ mov(dst, O2);
2171 __ mov(dst_pos, O3);
2172 __ mov(length, O4);
2173 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2174
2175 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2176 __ delayed()->nop();
2177 __ bind(*stub->continuation());
2178 return;
2179 }
2180
2181 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2182
2183 // make sure src and dst are non-null and load array length
2184 if (flags & LIR_OpArrayCopy::src_null_check) {
2185 __ tst(src);
2186 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2187 __ delayed()->nop();
2188 }
2189
2190 if (flags & LIR_OpArrayCopy::dst_null_check) {
2191 __ tst(dst);
2192 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2193 __ delayed()->nop();
2194 }
2195
2196 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2197 // test src_pos register
2198 __ tst(src_pos);
2199 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2200 __ delayed()->nop();
2201 }
2202
2203 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2204 // test dst_pos register
2205 __ tst(dst_pos);
2206 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2207 __ delayed()->nop();
2208 }
2209
2210 if (flags & LIR_OpArrayCopy::length_positive_check) {
2211 // make sure length isn't negative
2212 __ tst(length);
2213 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2214 __ delayed()->nop();
2215 }
2216
2217 if (flags & LIR_OpArrayCopy::src_range_check) {
2218 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2219 __ add(length, src_pos, tmp);
2220 __ cmp(tmp2, tmp);
2221 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2222 __ delayed()->nop();
2223 }
2224
2225 if (flags & LIR_OpArrayCopy::dst_range_check) {
2226 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2227 __ add(length, dst_pos, tmp);
2228 __ cmp(tmp2, tmp);
2229 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2230 __ delayed()->nop();
2231 }
2232
2233 if (flags & LIR_OpArrayCopy::type_check) {
2234 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2235 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2236 __ cmp(tmp, tmp2);
2237 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2238 __ delayed()->nop();
2239 }
2240
2241 #ifdef ASSERT
2242 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2243 // Sanity check the known type with the incoming class. For the
2244 // primitive case the types must match exactly with src.klass and
2245 // dst.klass each exactly matching the default type. For the
2246 // object array case, if no type check is needed then either the
2247 // dst type is exactly the expected type and the src type is a
2248 // subtype which we can't check or src is the same array as dst
2249 // but not necessarily exactly of type default_type.
2250 Label known_ok, halt;
2251 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2252 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2253 if (basic_type != T_OBJECT) {
2254 __ cmp(tmp, tmp2);
2255 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2256 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2257 __ cmp(tmp, tmp2);
2258 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2259 __ delayed()->nop();
2260 } else {
2261 __ cmp(tmp, tmp2);
2262 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2263 __ delayed()->cmp(src, dst);
2264 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2265 __ delayed()->nop();
2266 }
2267 __ bind(halt);
2268 __ stop("incorrect type information in arraycopy");
2269 __ bind(known_ok);
2270 }
2271 #endif
2272
2273 int shift = shift_amount(basic_type);
2274
2275 Register src_ptr = O0;
2276 Register dst_ptr = O1;
2277 Register len = O2;
2278
2279 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2280 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2281 if (shift == 0) {
2282 __ add(src_ptr, src_pos, src_ptr);
2283 } else {
2284 __ sll(src_pos, shift, tmp);
2285 __ add(src_ptr, tmp, src_ptr);
2286 }
2287
2288 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2289 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2290 if (shift == 0) {
2291 __ add(dst_ptr, dst_pos, dst_ptr);
2292 } else {
2293 __ sll(dst_pos, shift, tmp);
2294 __ add(dst_ptr, tmp, dst_ptr);
2295 }
2296
2297 if (basic_type != T_OBJECT) {
2298 if (shift == 0) {
2299 __ mov(length, len);
2300 } else {
2301 __ sll(length, shift, len);
2302 }
2303 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2304 } else {
2305 // oop_arraycopy takes a length in number of elements, so don't scale it.
2306 __ mov(length, len);
2307 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2308 }
2309
2310 __ bind(*stub->continuation());
2311 }
2312
2313
2314 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2315 if (dest->is_single_cpu()) {
2316 #ifdef _LP64
2317 if (left->type() == T_OBJECT) {
2318 switch (code) {
2319 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2320 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2321 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2322 default: ShouldNotReachHere();
2323 }
2324 } else
2325 #endif
2326 switch (code) {
2327 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2328 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2329 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2330 default: ShouldNotReachHere();
2331 }
2332 } else {
2333 #ifdef _LP64
2334 switch (code) {
2335 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2336 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2337 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2338 default: ShouldNotReachHere();
2339 }
2340 #else
2341 switch (code) {
2342 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2343 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2344 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2345 default: ShouldNotReachHere();
2346 }
2347 #endif
2348 }
2349 }
2350
2351
2352 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2353 #ifdef _LP64
2354 if (left->type() == T_OBJECT) {
2355 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2356 Register l = left->as_register();
2357 Register d = dest->as_register_lo();
2358 switch (code) {
2359 case lir_shl: __ sllx (l, count, d); break;
2360 case lir_shr: __ srax (l, count, d); break;
2361 case lir_ushr: __ srlx (l, count, d); break;
2362 default: ShouldNotReachHere();
2363 }
2364 return;
2365 }
2366 #endif
2367
2368 if (dest->is_single_cpu()) {
2369 count = count & 0x1F; // Java spec
2370 switch (code) {
2371 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2372 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2373 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2374 default: ShouldNotReachHere();
2375 }
2376 } else if (dest->is_double_cpu()) {
2377 count = count & 63; // Java spec
2378 switch (code) {
2379 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2380 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2381 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2382 default: ShouldNotReachHere();
2383 }
2384 } else {
2385 ShouldNotReachHere();
2386 }
2387 }
2388
2389
2390 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2391 assert(op->tmp1()->as_register() == G1 &&
2392 op->tmp2()->as_register() == G3 &&
2393 op->tmp3()->as_register() == G4 &&
2394 op->obj()->as_register() == O0 &&
2395 op->klass()->as_register() == G5, "must be");
2396 if (op->init_check()) {
2397 __ ld(op->klass()->as_register(),
2398 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2399 op->tmp1()->as_register());
2400 add_debug_info_for_null_check_here(op->stub()->info());
2401 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2402 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2403 __ delayed()->nop();
2404 }
2405 __ allocate_object(op->obj()->as_register(),
2406 op->tmp1()->as_register(),
2407 op->tmp2()->as_register(),
2408 op->tmp3()->as_register(),
2409 op->header_size(),
2410 op->object_size(),
2411 op->klass()->as_register(),
2412 *op->stub()->entry());
2413 __ bind(*op->stub()->continuation());
2414 __ verify_oop(op->obj()->as_register());
2415 }
2416
2417
2418 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2419 assert(op->tmp1()->as_register() == G1 &&
2420 op->tmp2()->as_register() == G3 &&
2421 op->tmp3()->as_register() == G4 &&
2422 op->tmp4()->as_register() == O1 &&
2423 op->klass()->as_register() == G5, "must be");
2424 if (UseSlowPath ||
2425 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2426 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2427 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2428 __ delayed()->nop();
2429 } else {
2430 __ allocate_array(op->obj()->as_register(),
2431 op->len()->as_register(),
2432 op->tmp1()->as_register(),
2433 op->tmp2()->as_register(),
2434 op->tmp3()->as_register(),
2435 arrayOopDesc::header_size(op->type()),
2436 type2aelembytes(op->type()),
2437 op->klass()->as_register(),
2438 *op->stub()->entry());
2439 }
2440 __ bind(*op->stub()->continuation());
2441 }
2442
2443
2444 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2445 ciMethodData *md, ciProfileData *data,
2446 Register recv, Register tmp1, Label* update_done) {
2447 uint i;
2448 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2449 Label next_test;
2450 // See if the receiver is receiver[n].
2451 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2452 mdo_offset_bias);
2453 __ ld_ptr(receiver_addr, tmp1);
2454 __ verify_oop(tmp1);
2455 __ cmp(recv, tmp1);
2456 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2457 __ delayed()->nop();
2458 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2459 mdo_offset_bias);
2460 __ ld_ptr(data_addr, tmp1);
2461 __ add(tmp1, DataLayout::counter_increment, tmp1);
2462 __ st_ptr(tmp1, data_addr);
2463 __ ba(false, *update_done);
2464 __ delayed()->nop();
2465 __ bind(next_test);
2466 }
2467
2468 // Didn't find receiver; find next empty slot and fill it in
2469 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2470 Label next_test;
2471 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2472 mdo_offset_bias);
2473 load(recv_addr, tmp1, T_OBJECT);
2474 __ br_notnull(tmp1, false, Assembler::pt, next_test);
2475 __ delayed()->nop();
2476 __ st_ptr(recv, recv_addr);
2477 __ set(DataLayout::counter_increment, tmp1);
2478 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2479 mdo_offset_bias);
2480 __ ba(false, *update_done);
2481 __ delayed()->nop();
2482 __ bind(next_test);
2483 }
2484 }
2485
2486
2487 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2488 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2489 md = method->method_data();
2490 if (md == NULL) {
2491 bailout("out of memory building methodDataOop");
2492 return;
2493 }
2494 data = md->bci_to_data(bci);
2495 assert(data != NULL, "need data for checkcast");
2496 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2497 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2498 // The offset is large so bias the mdo by the base of the slot so
2499 // that the ld can use simm13s to reference the slots of the data
2500 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2501 }
2502 }
2503
2504 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2505 // we always need a stub for the failure case.
2506 CodeStub* stub = op->stub();
2507 Register obj = op->object()->as_register();
2508 Register k_RInfo = op->tmp1()->as_register();
2509 Register klass_RInfo = op->tmp2()->as_register();
2510 Register dst = op->result_opr()->as_register();
2511 Register Rtmp1 = op->tmp3()->as_register();
2512 ciKlass* k = op->klass();
2513
2514
2515 if (obj == k_RInfo) {
2516 k_RInfo = klass_RInfo;
2517 klass_RInfo = obj;
2518 }
2519
2520 ciMethodData* md;
2521 ciProfileData* data;
2522 int mdo_offset_bias = 0;
2523 if (op->should_profile()) {
2524 ciMethod* method = op->profiled_method();
2525 assert(method != NULL, "Should have method");
2526 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2527
2528 Label not_null;
2529 __ br_notnull(obj, false, Assembler::pn, not_null);
2530 __ delayed()->nop();
2531 Register mdo = k_RInfo;
2532 Register data_val = Rtmp1;
2533 jobject2reg(md->constant_encoding(), mdo);
2534 if (mdo_offset_bias > 0) {
2535 __ set(mdo_offset_bias, data_val);
2536 __ add(mdo, data_val, mdo);
2537 }
2538 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2539 __ ldub(flags_addr, data_val);
2540 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2541 __ stb(data_val, flags_addr);
2542 __ ba(false, *obj_is_null);
2543 __ delayed()->nop();
2544 __ bind(not_null);
2545 } else {
2546 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2547 __ delayed()->nop();
2548 }
2549
2550 Label profile_cast_failure, profile_cast_success;
2551 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2552 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2553
2554 // patching may screw with our temporaries on sparc,
2555 // so let's do it before loading the class
2556 if (k->is_loaded()) {
2557 jobject2reg(k->constant_encoding(), k_RInfo);
2558 } else {
2559 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2560 }
2561 assert(obj != k_RInfo, "must be different");
2562
2563 // get object class
2564 // not a safepoint as obj null check happens earlier
2565 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2566 if (op->fast_check()) {
2567 assert_different_registers(klass_RInfo, k_RInfo);
2568 __ cmp(k_RInfo, klass_RInfo);
2569 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2570 __ delayed()->nop();
2571 } else {
2572 bool need_slow_path = true;
2573 if (k->is_loaded()) {
2574 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2575 need_slow_path = false;
2576 // perform the fast part of the checking logic
2577 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2578 (need_slow_path ? success_target : NULL),
2579 failure_target, NULL,
2580 RegisterOrConstant(k->super_check_offset()));
2581 } else {
2582 // perform the fast part of the checking logic
2583 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2584 failure_target, NULL);
2585 }
2586 if (need_slow_path) {
2587 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2588 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2589 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2590 __ delayed()->nop();
2591 __ cmp(G3, 0);
2592 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2593 __ delayed()->nop();
2594 // Fall through to success case
2595 }
2596 }
2597
2598 if (op->should_profile()) {
2599 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2600 assert_different_registers(obj, mdo, recv, tmp1);
2601 __ bind(profile_cast_success);
2602 jobject2reg(md->constant_encoding(), mdo);
2603 if (mdo_offset_bias > 0) {
2604 __ set(mdo_offset_bias, tmp1);
2605 __ add(mdo, tmp1, mdo);
2606 }
2607 load(Address(obj, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2608 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2609 // Jump over the failure case
2610 __ ba(false, *success);
2611 __ delayed()->nop();
2612 // Cast failure case
2613 __ bind(profile_cast_failure);
2614 jobject2reg(md->constant_encoding(), mdo);
2615 if (mdo_offset_bias > 0) {
2616 __ set(mdo_offset_bias, tmp1);
2617 __ add(mdo, tmp1, mdo);
2618 }
2619 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2620 __ ld_ptr(data_addr, tmp1);
2621 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2622 __ st_ptr(tmp1, data_addr);
2623 __ ba(false, *failure);
2624 __ delayed()->nop();
2625 }
2626 __ ba(false, *success);
2627 __ delayed()->nop();
2628 }
2629
2630 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2631 LIR_Code code = op->code();
2632 if (code == lir_store_check) {
2633 Register value = op->object()->as_register();
2634 Register array = op->array()->as_register();
2635 Register k_RInfo = op->tmp1()->as_register();
2636 Register klass_RInfo = op->tmp2()->as_register();
2637 Register Rtmp1 = op->tmp3()->as_register();
2638
2639 __ verify_oop(value);
2640 CodeStub* stub = op->stub();
2641 // check if it needs to be profiled
2642 ciMethodData* md;
2643 ciProfileData* data;
2644 int mdo_offset_bias = 0;
2645 if (op->should_profile()) {
2646 ciMethod* method = op->profiled_method();
2647 assert(method != NULL, "Should have method");
2648 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2649 }
2650 Label profile_cast_success, profile_cast_failure, done;
2651 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2652 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2653
2654 if (op->should_profile()) {
2655 Label not_null;
2656 __ br_notnull(value, false, Assembler::pn, not_null);
2657 __ delayed()->nop();
2658 Register mdo = k_RInfo;
2659 Register data_val = Rtmp1;
2660 jobject2reg(md->constant_encoding(), mdo);
2661 if (mdo_offset_bias > 0) {
2662 __ set(mdo_offset_bias, data_val);
2663 __ add(mdo, data_val, mdo);
2664 }
2665 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2666 __ ldub(flags_addr, data_val);
2667 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2668 __ stb(data_val, flags_addr);
2669 __ ba(false, done);
2670 __ delayed()->nop();
2671 __ bind(not_null);
2672 } else {
2673 __ br_null(value, false, Assembler::pn, done);
2674 __ delayed()->nop();
2675 }
2676 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2677 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2678
2679 // get instance klass
2680 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2681 // perform the fast part of the checking logic
2682 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2683
2684 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2685 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2686 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2687 __ delayed()->nop();
2688 __ cmp(G3, 0);
2689 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2690 __ delayed()->nop();
2691 // fall through to the success case
2692
2693 if (op->should_profile()) {
2694 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2695 assert_different_registers(value, mdo, recv, tmp1);
2696 __ bind(profile_cast_success);
2697 jobject2reg(md->constant_encoding(), mdo);
2698 if (mdo_offset_bias > 0) {
2699 __ set(mdo_offset_bias, tmp1);
2700 __ add(mdo, tmp1, mdo);
2701 }
2702 load(Address(value, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2703 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2704 __ ba(false, done);
2705 __ delayed()->nop();
2706 // Cast failure case
2707 __ bind(profile_cast_failure);
2708 jobject2reg(md->constant_encoding(), mdo);
2709 if (mdo_offset_bias > 0) {
2710 __ set(mdo_offset_bias, tmp1);
2711 __ add(mdo, tmp1, mdo);
2712 }
2713 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2714 __ ld_ptr(data_addr, tmp1);
2715 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2716 __ st_ptr(tmp1, data_addr);
2717 __ ba(false, *stub->entry());
2718 __ delayed()->nop();
2719 }
2720 __ bind(done);
2721 } else if (code == lir_checkcast) {
2722 Register obj = op->object()->as_register();
2723 Register dst = op->result_opr()->as_register();
2724 Label success;
2725 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2726 __ bind(success);
2727 __ mov(obj, dst);
2728 } else if (code == lir_instanceof) {
2729 Register obj = op->object()->as_register();
2730 Register dst = op->result_opr()->as_register();
2731 Label success, failure, done;
2732 emit_typecheck_helper(op, &success, &failure, &failure);
2733 __ bind(failure);
2734 __ set(0, dst);
2735 __ ba(false, done);
2736 __ delayed()->nop();
2737 __ bind(success);
2738 __ set(1, dst);
2739 __ bind(done);
2740 } else {
2741 ShouldNotReachHere();
2742 }
2743
2744 }
2745
2746
2747 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2748 if (op->code() == lir_cas_long) {
2749 assert(VM_Version::supports_cx8(), "wrong machine");
2750 Register addr = op->addr()->as_pointer_register();
2751 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2752 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2753 Register new_value_lo = op->new_value()->as_register_lo();
2754 Register new_value_hi = op->new_value()->as_register_hi();
2755 Register t1 = op->tmp1()->as_register();
2756 Register t2 = op->tmp2()->as_register();
2757 #ifdef _LP64
2758 __ mov(cmp_value_lo, t1);
2759 __ mov(new_value_lo, t2);
2760 #else
2761 // move high and low halves of long values into single registers
2762 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2763 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2764 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2765 __ sllx(new_value_hi, 32, t2);
2766 __ srl(new_value_lo, 0, new_value_lo);
2767 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2768 #endif
2769 // perform the compare and swap operation
2770 __ casx(addr, t1, t2);
2771 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2772 // overwritten with the original value in "addr" and will be equal to t1.
2773 __ cmp(t1, t2);
2774
2775 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2776 Register addr = op->addr()->as_pointer_register();
2777 Register cmp_value = op->cmp_value()->as_register();
2778 Register new_value = op->new_value()->as_register();
2779 Register t1 = op->tmp1()->as_register();
2780 Register t2 = op->tmp2()->as_register();
2781 __ mov(cmp_value, t1);
2782 __ mov(new_value, t2);
2783 #ifdef _LP64
2784 if (op->code() == lir_cas_obj) {
2785 __ casx(addr, t1, t2);
2786 } else
2787 #endif
2788 {
2789 __ cas(addr, t1, t2);
2790 }
2791 __ cmp(t1, t2);
2792 } else {
2793 Unimplemented();
2794 }
2795 }
2796
2797 void LIR_Assembler::set_24bit_FPU() {
2798 Unimplemented();
2799 }
2800
2801
2802 void LIR_Assembler::reset_FPU() {
2803 Unimplemented();
2804 }
2805
2806
2807 void LIR_Assembler::breakpoint() {
2808 __ breakpoint_trap();
2809 }
2810
2811
2812 void LIR_Assembler::push(LIR_Opr opr) {
2813 Unimplemented();
2814 }
2815
2816
2817 void LIR_Assembler::pop(LIR_Opr opr) {
2818 Unimplemented();
2819 }
2820
2821
2822 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2823 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2824 Register dst = dst_opr->as_register();
2825 Register reg = mon_addr.base();
2826 int offset = mon_addr.disp();
2827 // compute pointer to BasicLock
2828 if (mon_addr.is_simm13()) {
2829 __ add(reg, offset, dst);
2830 } else {
2831 __ set(offset, dst);
2832 __ add(dst, reg, dst);
2833 }
2834 }
2835
2836
2837 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2838 Register obj = op->obj_opr()->as_register();
2839 Register hdr = op->hdr_opr()->as_register();
2840 Register lock = op->lock_opr()->as_register();
2841
2842 // obj may not be an oop
2843 if (op->code() == lir_lock) {
2844 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2845 if (UseFastLocking) {
2846 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2847 // add debug info for NullPointerException only if one is possible
2848 if (op->info() != NULL) {
2849 add_debug_info_for_null_check_here(op->info());
2850 }
2851 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2852 } else {
2853 // always do slow locking
2854 // note: the slow locking code could be inlined here, however if we use
2855 // slow locking, speed doesn't matter anyway and this solution is
2856 // simpler and requires less duplicated code - additionally, the
2857 // slow locking code is the same in either case which simplifies
2858 // debugging
2859 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2860 __ delayed()->nop();
2861 }
2862 } else {
2863 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2864 if (UseFastLocking) {
2865 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2866 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2867 } else {
2868 // always do slow unlocking
2869 // note: the slow unlocking code could be inlined here, however if we use
2870 // slow unlocking, speed doesn't matter anyway and this solution is
2871 // simpler and requires less duplicated code - additionally, the
2872 // slow unlocking code is the same in either case which simplifies
2873 // debugging
2874 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2875 __ delayed()->nop();
2876 }
2877 }
2878 __ bind(*op->stub()->continuation());
2879 }
2880
2881
2882 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2883 ciMethod* method = op->profiled_method();
2884 int bci = op->profiled_bci();
2885
2886 // Update counter for all call types
2887 ciMethodData* md = method->method_data();
2888 if (md == NULL) {
2889 bailout("out of memory building methodDataOop");
2890 return;
2891 }
2892 ciProfileData* data = md->bci_to_data(bci);
2893 assert(data->is_CounterData(), "need CounterData for calls");
2894 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2895 Register mdo = op->mdo()->as_register();
2896 #ifdef _LP64
2897 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2898 Register tmp1 = op->tmp1()->as_register_lo();
2899 #else
2900 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2901 Register tmp1 = op->tmp1()->as_register();
2902 #endif
2903 jobject2reg(md->constant_encoding(), mdo);
2904 int mdo_offset_bias = 0;
2905 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2906 data->size_in_bytes())) {
2907 // The offset is large so bias the mdo by the base of the slot so
2908 // that the ld can use simm13s to reference the slots of the data
2909 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2910 __ set(mdo_offset_bias, O7);
2911 __ add(mdo, O7, mdo);
2912 }
2913
2914 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2915 Bytecodes::Code bc = method->java_code_at_bci(bci);
2916 // Perform additional virtual call profiling for invokevirtual and
2917 // invokeinterface bytecodes
2918 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2919 C1ProfileVirtualCalls) {
2920 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2921 Register recv = op->recv()->as_register();
2922 assert_different_registers(mdo, tmp1, recv);
2923 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2924 ciKlass* known_klass = op->known_holder();
2925 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2926 // We know the type that will be seen at this call site; we can
2927 // statically update the methodDataOop rather than needing to do
2928 // dynamic tests on the receiver type
2929
2930 // NOTE: we should probably put a lock around this search to
2931 // avoid collisions by concurrent compilations
2932 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2933 uint i;
2934 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2935 ciKlass* receiver = vc_data->receiver(i);
2936 if (known_klass->equals(receiver)) {
2937 Address data_addr(mdo, md->byte_offset_of_slot(data,
2938 VirtualCallData::receiver_count_offset(i)) -
2939 mdo_offset_bias);
2940 __ ld_ptr(data_addr, tmp1);
2941 __ add(tmp1, DataLayout::counter_increment, tmp1);
2942 __ st_ptr(tmp1, data_addr);
2943 return;
2944 }
2945 }
2946
2947 // Receiver type not found in profile data; select an empty slot
2948
2949 // Note that this is less efficient than it should be because it
2950 // always does a write to the receiver part of the
2951 // VirtualCallData rather than just the first time
2952 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2953 ciKlass* receiver = vc_data->receiver(i);
2954 if (receiver == NULL) {
2955 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2956 mdo_offset_bias);
2957 jobject2reg(known_klass->constant_encoding(), tmp1);
2958 __ st_ptr(tmp1, recv_addr);
2959 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2960 mdo_offset_bias);
2961 __ ld_ptr(data_addr, tmp1);
2962 __ add(tmp1, DataLayout::counter_increment, tmp1);
2963 __ st_ptr(tmp1, data_addr);
2964 return;
2965 }
2966 }
2967 } else {
2968 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2969 Label update_done;
2970 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2971 // Receiver did not match any saved receiver and there is no empty row for it.
2972 // Increment total counter to indicate polymorphic case.
2973 __ ld_ptr(counter_addr, tmp1);
2974 __ add(tmp1, DataLayout::counter_increment, tmp1);
2975 __ st_ptr(tmp1, counter_addr);
2976
2977 __ bind(update_done);
2978 }
2979 } else {
2980 // Static call
2981 __ ld_ptr(counter_addr, tmp1);
2982 __ add(tmp1, DataLayout::counter_increment, tmp1);
2983 __ st_ptr(tmp1, counter_addr);
2984 }
2985 }
2986
2987 void LIR_Assembler::align_backward_branch_target() {
2988 __ align(OptoLoopAlignment);
2989 }
2990
2991
2992 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2993 // make sure we are expecting a delay
2994 // this has the side effect of clearing the delay state
2995 // so we can use _masm instead of _masm->delayed() to do the
2996 // code generation.
2997 __ delayed();
2998
2999 // make sure we only emit one instruction
3000 int offset = code_offset();
3001 op->delay_op()->emit_code(this);
3002 #ifdef ASSERT
3003 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3004 op->delay_op()->print();
3005 }
3006 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3007 "only one instruction can go in a delay slot");
3008 #endif
3009
3010 // we may also be emitting the call info for the instruction
3011 // which we are the delay slot of.
3012 CodeEmitInfo* call_info = op->call_info();
3013 if (call_info) {
3014 add_call_info(code_offset(), call_info);
3015 }
3016
3017 if (VerifyStackAtCalls) {
3018 _masm->sub(FP, SP, O7);
3019 _masm->cmp(O7, initial_frame_size_in_bytes());
3020 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3021 }
3022 }
3023
3024
3025 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3026 assert(left->is_register(), "can only handle registers");
3027
3028 if (left->is_single_cpu()) {
3029 __ neg(left->as_register(), dest->as_register());
3030 } else if (left->is_single_fpu()) {
3031 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3032 } else if (left->is_double_fpu()) {
3033 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3034 } else {
3035 assert (left->is_double_cpu(), "Must be a long");
3036 Register Rlow = left->as_register_lo();
3037 Register Rhi = left->as_register_hi();
3038 #ifdef _LP64
3039 __ sub(G0, Rlow, dest->as_register_lo());
3040 #else
3041 __ subcc(G0, Rlow, dest->as_register_lo());
3042 __ subc (G0, Rhi, dest->as_register_hi());
3043 #endif
3044 }
3045 }
3046
3047
3048 void LIR_Assembler::fxch(int i) {
3049 Unimplemented();
3050 }
3051
3052 void LIR_Assembler::fld(int i) {
3053 Unimplemented();
3054 }
3055
3056 void LIR_Assembler::ffree(int i) {
3057 Unimplemented();
3058 }
3059
3060 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3061 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3062
3063 // if tmp is invalid, then the function being called doesn't destroy the thread
3064 if (tmp->is_valid()) {
3065 __ save_thread(tmp->as_register());
3066 }
3067 __ call(dest, relocInfo::runtime_call_type);
3068 __ delayed()->nop();
3069 if (info != NULL) {
3070 add_call_info_here(info);
3071 }
3072 if (tmp->is_valid()) {
3073 __ restore_thread(tmp->as_register());
3074 }
3075
3076 #ifdef ASSERT
3077 __ verify_thread();
3078 #endif // ASSERT
3079 }
3080
3081
3082 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3083 #ifdef _LP64
3084 ShouldNotReachHere();
3085 #endif
3086
3087 NEEDS_CLEANUP;
3088 if (type == T_LONG) {
3089 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3090
3091 // (extended to allow indexed as well as constant displaced for JSR-166)
3092 Register idx = noreg; // contains either constant offset or index
3093
3094 int disp = mem_addr->disp();
3095 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3096 if (!Assembler::is_simm13(disp)) {
3097 idx = O7;
3098 __ set(disp, idx);
3099 }
3100 } else {
3101 assert(disp == 0, "not both indexed and disp");
3102 idx = mem_addr->index()->as_register();
3103 }
3104
3105 int null_check_offset = -1;
3106
3107 Register base = mem_addr->base()->as_register();
3108 if (src->is_register() && dest->is_address()) {
3109 // G4 is high half, G5 is low half
3110 if (VM_Version::v9_instructions_work()) {
3111 // clear the top bits of G5, and scale up G4
3112 __ srl (src->as_register_lo(), 0, G5);
3113 __ sllx(src->as_register_hi(), 32, G4);
3114 // combine the two halves into the 64 bits of G4
3115 __ or3(G4, G5, G4);
3116 null_check_offset = __ offset();
3117 if (idx == noreg) {
3118 __ stx(G4, base, disp);
3119 } else {
3120 __ stx(G4, base, idx);
3121 }
3122 } else {
3123 __ mov (src->as_register_hi(), G4);
3124 __ mov (src->as_register_lo(), G5);
3125 null_check_offset = __ offset();
3126 if (idx == noreg) {
3127 __ std(G4, base, disp);
3128 } else {
3129 __ std(G4, base, idx);
3130 }
3131 }
3132 } else if (src->is_address() && dest->is_register()) {
3133 null_check_offset = __ offset();
3134 if (VM_Version::v9_instructions_work()) {
3135 if (idx == noreg) {
3136 __ ldx(base, disp, G5);
3137 } else {
3138 __ ldx(base, idx, G5);
3139 }
3140 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3141 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3142 } else {
3143 if (idx == noreg) {
3144 __ ldd(base, disp, G4);
3145 } else {
3146 __ ldd(base, idx, G4);
3147 }
3148 // G4 is high half, G5 is low half
3149 __ mov (G4, dest->as_register_hi());
3150 __ mov (G5, dest->as_register_lo());
3151 }
3152 } else {
3153 Unimplemented();
3154 }
3155 if (info != NULL) {
3156 add_debug_info_for_null_check(null_check_offset, info);
3157 }
3158
3159 } else {
3160 // use normal move for all other volatiles since they don't need
3161 // special handling to remain atomic.
3162 move_op(src, dest, type, lir_patch_none, info, false, false);
3163 }
3164 }
3165
3166 void LIR_Assembler::membar() {
3167 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3168 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3169 }
3170
3171 void LIR_Assembler::membar_acquire() {
3172 // no-op on TSO
3173 }
3174
3175 void LIR_Assembler::membar_release() {
3176 // no-op on TSO
3177 }
3178
3179 // Pack two sequential registers containing 32 bit values
3180 // into a single 64 bit register.
3181 // src and src->successor() are packed into dst
3182 // src and dst may be the same register.
3183 // Note: src is destroyed
3184 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3185 Register rs = src->as_register();
3186 Register rd = dst->as_register_lo();
3187 __ sllx(rs, 32, rs);
3188 __ srl(rs->successor(), 0, rs->successor());
3189 __ or3(rs, rs->successor(), rd);
3190 }
3191
3192 // Unpack a 64 bit value in a register into
3193 // two sequential registers.
3194 // src is unpacked into dst and dst->successor()
3195 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3196 Register rs = src->as_register_lo();
3197 Register rd = dst->as_register_hi();
3198 assert_different_registers(rs, rd, rd->successor());
3199 __ srlx(rs, 32, rd);
3200 __ srl (rs, 0, rd->successor());
3201 }
3202
3203
3204 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3205 LIR_Address* addr = addr_opr->as_address_ptr();
3206 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3207
3208 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3209 }
3210
3211
3212 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3213 assert(result_reg->is_register(), "check");
3214 __ mov(G2_thread, result_reg->as_register());
3215 }
3216
3217
3218 void LIR_Assembler::peephole(LIR_List* lir) {
3219 LIR_OpList* inst = lir->instructions_list();
3220 for (int i = 0; i < inst->length(); i++) {
3221 LIR_Op* op = inst->at(i);
3222 switch (op->code()) {
3223 case lir_cond_float_branch:
3224 case lir_branch: {
3225 LIR_OpBranch* branch = op->as_OpBranch();
3226 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3227 LIR_Op* delay_op = NULL;
3228 // we'd like to be able to pull following instructions into
3229 // this slot but we don't know enough to do it safely yet so
3230 // only optimize block to block control flow.
3231 if (LIRFillDelaySlots && branch->block()) {
3232 LIR_Op* prev = inst->at(i - 1);
3233 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3234 // swap previous instruction into delay slot
3235 inst->at_put(i - 1, op);
3236 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3237 #ifndef PRODUCT
3238 if (LIRTracePeephole) {
3239 tty->print_cr("delayed");
3240 inst->at(i - 1)->print();
3241 inst->at(i)->print();
3242 tty->cr();
3243 }
3244 #endif
3245 continue;
3246 }
3247 }
3248
3249 if (!delay_op) {
3250 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3251 }
3252 inst->insert_before(i + 1, delay_op);
3253 break;
3254 }
3255 case lir_static_call:
3256 case lir_virtual_call:
3257 case lir_icvirtual_call:
3258 case lir_optvirtual_call:
3259 case lir_dynamic_call: {
3260 LIR_Op* prev = inst->at(i - 1);
3261 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3262 (op->code() != lir_virtual_call ||
3263 !prev->result_opr()->is_single_cpu() ||
3264 prev->result_opr()->as_register() != O0) &&
3265 LIR_Assembler::is_single_instruction(prev)) {
3266 // Only moves without info can be put into the delay slot.
3267 // Also don't allow the setup of the receiver in the delay
3268 // slot for vtable calls.
3269 inst->at_put(i - 1, op);
3270 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3271 #ifndef PRODUCT
3272 if (LIRTracePeephole) {
3273 tty->print_cr("delayed");
3274 inst->at(i - 1)->print();
3275 inst->at(i)->print();
3276 tty->cr();
3277 }
3278 #endif
3279 } else {
3280 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3281 inst->insert_before(i + 1, delay_op);
3282 i++;
3283 }
3284
3285 #if defined(TIERED) && !defined(_LP64)
3286 // fixup the return value from G1 to O0/O1 for long returns.
3287 // It's done here instead of in LIRGenerator because there's
3288 // such a mismatch between the single reg and double reg
3289 // calling convention.
3290 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3291 if (callop->result_opr() == FrameMap::out_long_opr) {
3292 LIR_OpJavaCall* call;
3293 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3294 for (int a = 0; a < arguments->length(); a++) {
3295 arguments[a] = callop->arguments()[a];
3296 }
3297 if (op->code() == lir_virtual_call) {
3298 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3299 callop->vtable_offset(), arguments, callop->info());
3300 } else {
3301 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3302 callop->addr(), arguments, callop->info());
3303 }
3304 inst->at_put(i - 1, call);
3305 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3306 T_LONG, lir_patch_none, NULL));
3307 }
3308 #endif
3309 break;
3310 }
3311 }
3312 }
3313 }
3314
3315
3316
3317
3318 #undef __