1 /* 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "assembler_sparc.inline.hpp" 28 #include "code/icBuffer.hpp" 29 #include "gc_interface/collectedHeap.inline.hpp" 30 #include "interpreter/bytecodes.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "nativeInst_sparc.hpp" 33 #include "oops/oop.inline.hpp" 34 #include "oops/oop.inline2.hpp" 35 36 int InlineCacheBuffer::ic_stub_code_size() { 37 #ifdef _LP64 38 if (TraceJumps) return 600 * wordSize; 39 return (NativeMovConstReg::instruction_size + // sethi;add 40 NativeJump::instruction_size + // sethi; jmp; delay slot 41 (1*BytesPerInstWord) + 1); // flush + 1 extra byte 42 #else 43 if (TraceJumps) return 300 * wordSize; 44 return (2+2+ 1) * wordSize + 1; // set/jump_to/nop + 1 byte so that code_end can be set in CodeBuffer 45 #endif 46 } 47 48 void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, oop cached_oop, address entry_point) { 49 ResourceMark rm; 50 CodeBuffer code(code_begin, ic_stub_code_size()); 51 MacroAssembler* masm = new MacroAssembler(&code); 52 // note: even though the code contains an embedded oop, we do not need reloc info 53 // because 54 // (1) the oop is old (i.e., doesn't matter for scavenges) 55 // (2) these ICStubs are removed *before* a GC happens, so the roots disappear 56 assert(cached_oop == NULL || cached_oop->is_perm(), "must be old oop"); 57 AddressLiteral cached_oop_addrlit(cached_oop, relocInfo::none); 58 // Force the set to generate the fixed sequence so next_instruction_address works 59 masm->patchable_set(cached_oop_addrlit, G5_inline_cache_reg); 60 assert(G3_scratch != G5_method, "Do not clobber the method oop in the transition stub"); 61 assert(G3_scratch != G5_inline_cache_reg, "Do not clobber the inline cache register in the transition stub"); 62 AddressLiteral entry(entry_point); 63 masm->JUMP(entry, G3_scratch, 0); 64 masm->delayed()->nop(); 65 masm->flush(); 66 } 67 68 69 address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { 70 NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object 71 NativeJump* jump = nativeJump_at(move->next_instruction_address()); 72 return jump->jump_destination(); 73 } 74 75 76 oop InlineCacheBuffer::ic_buffer_cached_oop(address code_begin) { 77 NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object 78 NativeJump* jump = nativeJump_at(move->next_instruction_address()); 79 return (oop)move->data(); 80 }