src/cpu/sparc/vm/register_sparc.hpp

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   1 /*
   2  * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 






  25 // forward declaration
  26 class Address;
  27 class VMRegImpl;
  28 typedef VMRegImpl* VMReg;
  29 
  30 
  31 // Use Register as shortcut
  32 class RegisterImpl;
  33 typedef RegisterImpl* Register;
  34 
  35 
  36 inline Register as_Register(int encoding) {
  37   return (Register)(intptr_t) encoding;
  38 }
  39 
  40 // The implementation of integer registers for the SPARC architecture
  41 class RegisterImpl: public AbstractRegisterImpl {
  42  public:
  43   enum {
  44     log_set_size        = 3,                          // the number of bits to encode the set register number


 423 inline FloatRegister as_DoubleFloatRegister(int encoding);
 424 class DoubleFloatRegisterImpl {
 425  public:
 426   friend inline FloatRegister as_DoubleFloatRegister(int encoding) {
 427     assert(encoding < 32, "bad double float register encoding");
 428     return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) );
 429   }
 430 };
 431 
 432 
 433 class QuadFloatRegisterImpl;
 434 typedef QuadFloatRegisterImpl *QuadFloatRegister;
 435 
 436 class QuadFloatRegisterImpl {
 437  public:
 438   friend FloatRegister as_QuadFloatRegister(int encoding) {
 439     assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding");
 440     return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) );
 441   }
 442 };


   1 /*
   2  * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP
  26 #define CPU_SPARC_VM_REGISTER_SPARC_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_sparc.hpp"
  30 
  31 // forward declaration
  32 class Address;
  33 class VMRegImpl;
  34 typedef VMRegImpl* VMReg;
  35 
  36 
  37 // Use Register as shortcut
  38 class RegisterImpl;
  39 typedef RegisterImpl* Register;
  40 
  41 
  42 inline Register as_Register(int encoding) {
  43   return (Register)(intptr_t) encoding;
  44 }
  45 
  46 // The implementation of integer registers for the SPARC architecture
  47 class RegisterImpl: public AbstractRegisterImpl {
  48  public:
  49   enum {
  50     log_set_size        = 3,                          // the number of bits to encode the set register number


 429 inline FloatRegister as_DoubleFloatRegister(int encoding);
 430 class DoubleFloatRegisterImpl {
 431  public:
 432   friend inline FloatRegister as_DoubleFloatRegister(int encoding) {
 433     assert(encoding < 32, "bad double float register encoding");
 434     return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) );
 435   }
 436 };
 437 
 438 
 439 class QuadFloatRegisterImpl;
 440 typedef QuadFloatRegisterImpl *QuadFloatRegister;
 441 
 442 class QuadFloatRegisterImpl {
 443  public:
 444   friend FloatRegister as_QuadFloatRegister(int encoding) {
 445     assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding");
 446     return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) );
 447   }
 448 };
 449 
 450 #endif // CPU_SPARC_VM_REGISTER_SPARC_HPP