1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_x86.cpp.incl"
27
28
29 // These masks are used to provide 128-bit aligned bitmasks to the XMM
30 // instructions, to allow sign-masking or sign-bit flipping. They allow
31 // fast versions of NegF/NegD and AbsF/AbsD.
32
33 // Note: 'double' and 'long long' have 32-bits alignment on x86.
34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
36 // of 128-bits operands for SSE instructions.
37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
38 // Store the value to a 128-bits operand.
39 operand[0] = lo;
40 operand[1] = hi;
41 return operand;
42 }
43
44 // Buffer for 128-bits masks used by SSE instructions.
45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
46
47 // Static initialization during VM startup.
48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
52
53
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rax; // where the IC klass is cached
57 const Register SYNC_header = rax; // synchronization header
58 const Register SHIFT_count = rcx; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
100 if (opr->is_constant()) {
101 LIR_Const* constant = opr->as_constant_ptr();
102 switch (constant->type()) {
103 case T_INT: {
104 return true;
105 }
106
107 default:
108 return false;
109 }
110 }
111 return false;
112 }
113
114
115 LIR_Opr LIR_Assembler::receiverOpr() {
116 return FrameMap::receiver_opr;
117 }
118
119 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
120 return receiverOpr();
121 }
122
123 LIR_Opr LIR_Assembler::osrBufferPointer() {
124 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
125 }
126
127 //--------------fpu register translations-----------------------
128
129
130 address LIR_Assembler::float_constant(float f) {
131 address const_addr = __ float_constant(f);
132 if (const_addr == NULL) {
133 bailout("const section overflow");
134 return __ code()->consts()->start();
135 } else {
136 return const_addr;
137 }
138 }
139
140
141 address LIR_Assembler::double_constant(double d) {
142 address const_addr = __ double_constant(d);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 void LIR_Assembler::set_24bit_FPU() {
153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
154 }
155
156 void LIR_Assembler::reset_FPU() {
157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
158 }
159
160 void LIR_Assembler::fpop() {
161 __ fpop();
162 }
163
164 void LIR_Assembler::fxch(int i) {
165 __ fxch(i);
166 }
167
168 void LIR_Assembler::fld(int i) {
169 __ fld_s(i);
170 }
171
172 void LIR_Assembler::ffree(int i) {
173 __ ffree(i);
174 }
175
176 void LIR_Assembler::breakpoint() {
177 __ int3();
178 }
179
180 void LIR_Assembler::push(LIR_Opr opr) {
181 if (opr->is_single_cpu()) {
182 __ push_reg(opr->as_register());
183 } else if (opr->is_double_cpu()) {
184 NOT_LP64(__ push_reg(opr->as_register_hi()));
185 __ push_reg(opr->as_register_lo());
186 } else if (opr->is_stack()) {
187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
188 } else if (opr->is_constant()) {
189 LIR_Const* const_opr = opr->as_constant_ptr();
190 if (const_opr->type() == T_OBJECT) {
191 __ push_oop(const_opr->as_jobject());
192 } else if (const_opr->type() == T_INT) {
193 __ push_jint(const_opr->as_jint());
194 } else {
195 ShouldNotReachHere();
196 }
197
198 } else {
199 ShouldNotReachHere();
200 }
201 }
202
203 void LIR_Assembler::pop(LIR_Opr opr) {
204 if (opr->is_single_cpu()) {
205 __ pop_reg(opr->as_register());
206 } else {
207 ShouldNotReachHere();
208 }
209 }
210
211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
212 return addr->base()->is_illegal() && addr->index()->is_illegal();
213 }
214
215 //-------------------------------------------
216
217 Address LIR_Assembler::as_Address(LIR_Address* addr) {
218 return as_Address(addr, rscratch1);
219 }
220
221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
222 if (addr->base()->is_illegal()) {
223 assert(addr->index()->is_illegal(), "must be illegal too");
224 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
225 if (! __ reachable(laddr)) {
226 __ movptr(tmp, laddr.addr());
227 Address res(tmp, 0);
228 return res;
229 } else {
230 return __ as_Address(laddr);
231 }
232 }
233
234 Register base = addr->base()->as_pointer_register();
235
236 if (addr->index()->is_illegal()) {
237 return Address( base, addr->disp());
238 } else if (addr->index()->is_cpu_register()) {
239 Register index = addr->index()->as_pointer_register();
240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
241 } else if (addr->index()->is_constant()) {
242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
243 assert(Assembler::is_simm32(addr_offset), "must be");
244
245 return Address(base, addr_offset);
246 } else {
247 Unimplemented();
248 return Address();
249 }
250 }
251
252
253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
254 Address base = as_Address(addr);
255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
256 }
257
258
259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
260 return as_Address(addr);
261 }
262
263
264 void LIR_Assembler::osr_entry() {
265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
266 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
267 ValueStack* entry_state = osr_entry->state();
268 int number_of_locks = entry_state->locks_size();
269
270 // we jump here if osr happens with the interpreter
271 // state set up to continue at the beginning of the
272 // loop that triggered osr - in particular, we have
273 // the following registers setup:
274 //
275 // rcx: osr buffer
276 //
277
278 // build frame
279 ciMethod* m = compilation()->method();
280 __ build_frame(initial_frame_size_in_bytes());
281
282 // OSR buffer is
283 //
284 // locals[nlocals-1..0]
285 // monitors[0..number_of_locks]
286 //
287 // locals is a direct copy of the interpreter frame so in the osr buffer
288 // so first slot in the local array is the last local from the interpreter
289 // and last slot is local[0] (receiver) from the interpreter
290 //
291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
293 // in the interpreter frame (the method lock if a sync method)
294
295 // Initialize monitors in the compiled activation.
296 // rcx: pointer to osr buffer
297 //
298 // All other registers are dead at this point and the locals will be
299 // copied into place by code emitted in the IR.
300
301 Register OSR_buf = osrBufferPointer()->as_pointer_register();
302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
303 int monitor_offset = BytesPerWord * method()->max_locals() +
304 (2 * BytesPerWord) * (number_of_locks - 1);
305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
306 // the OSR buffer using 2 word entries: first the lock and then
307 // the oop.
308 for (int i = 0; i < number_of_locks; i++) {
309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
310 #ifdef ASSERT
311 // verify the interpreter's monitor has a non-null object
312 {
313 Label L;
314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
315 __ jcc(Assembler::notZero, L);
316 __ stop("locked object is NULL");
317 __ bind(L);
318 }
319 #endif
320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
323 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
324 }
325 }
326 }
327
328
329 // inline cache check; done before the frame is built.
330 int LIR_Assembler::check_icache() {
331 Register receiver = FrameMap::receiver_opr->as_register();
332 Register ic_klass = IC_Klass;
333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
334
335 if (!VerifyOops) {
336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
338 __ nop();
339 }
340 }
341 int offset = __ offset();
342 __ inline_cache_check(receiver, IC_Klass);
343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
344 if (VerifyOops) {
345 // force alignment after the cache check.
346 // It's been verified to be aligned if !VerifyOops
347 __ align(CodeEntryAlignment);
348 }
349 return offset;
350 }
351
352
353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
354 jobject o = NULL;
355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
356 __ movoop(reg, o);
357 patching_epilog(patch, lir_patch_normal, reg, info);
358 }
359
360
361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
362 if (exception->is_valid()) {
363 // preserve exception
364 // note: the monitor_exit runtime call is a leaf routine
365 // and cannot block => no GC can happen
366 // The slow case (MonitorAccessStub) uses the first two stack slots
367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
368 __ movptr (Address(rsp, 2*wordSize), exception);
369 }
370
371 Register obj_reg = obj_opr->as_register();
372 Register lock_reg = lock_opr->as_register();
373
374 // setup registers (lock_reg must be rax, for lock_object)
375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
376 Register hdr = lock_reg;
377 assert(new_hdr == SYNC_header, "wrong register");
378 lock_reg = new_hdr;
379 // compute pointer to BasicLock
380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
381 __ lea(lock_reg, lock_addr);
382 // unlock object
383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
384 // _slow_case_stubs->append(slow_case);
385 // temporary fix: must be created after exceptionhandler, therefore as call stub
386 _slow_case_stubs->append(slow_case);
387 if (UseFastLocking) {
388 // try inlined fast unlocking first, revert to slow locking if it fails
389 // note: lock_reg points to the displaced header since the displaced header offset is 0!
390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
392 } else {
393 // always do slow unlocking
394 // note: the slow unlocking code could be inlined here, however if we use
395 // slow unlocking, speed doesn't matter anyway and this solution is
396 // simpler and requires less duplicated code - additionally, the
397 // slow unlocking code is the same in either case which simplifies
398 // debugging
399 __ jmp(*slow_case->entry());
400 }
401 // done
402 __ bind(*slow_case->continuation());
403
404 if (exception->is_valid()) {
405 // restore exception
406 __ movptr (exception, Address(rsp, 2 * wordSize));
407 }
408 }
409
410 // This specifies the rsp decrement needed to build the frame
411 int LIR_Assembler::initial_frame_size_in_bytes() {
412 // if rounding, must let FrameMap know!
413
414 // The frame_map records size in slots (32bit word)
415
416 // subtract two words to account for return address and link
417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
418 }
419
420
421 int LIR_Assembler::emit_exception_handler() {
422 // if the last instruction is a call (typically to do a throw which
423 // is coming at the end after block reordering) the return address
424 // must still point into the code area in order to avoid assertion
425 // failures when searching for the corresponding bci => add a nop
426 // (was bug 5/14/1999 - gri)
427 __ nop();
428
429 // generate code for exception handler
430 address handler_base = __ start_a_stub(exception_handler_size);
431 if (handler_base == NULL) {
432 // not enough space left for the handler
433 bailout("exception handler overflow");
434 return -1;
435 }
436
437 int offset = code_offset();
438
439 // the exception oop and pc are in rax, and rdx
440 // no other registers need to be preserved, so invalidate them
441 __ invalidate_registers(false, true, true, false, true, true);
442
443 // check that there is really an exception
444 __ verify_not_null_oop(rax);
445
446 // search an exception handler (rax: exception oop, rdx: throwing pc)
447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
448
449 __ stop("should not reach here");
450
451 assert(code_offset() - offset <= exception_handler_size, "overflow");
452 __ end_a_stub();
453
454 return offset;
455 }
456
457
458 // Emit the code to remove the frame from the stack in the exception
459 // unwind path.
460 int LIR_Assembler::emit_unwind_handler() {
461 #ifndef PRODUCT
462 if (CommentedAssembly) {
463 _masm->block_comment("Unwind handler");
464 }
465 #endif
466
467 int offset = code_offset();
468
469 // Fetch the exception from TLS and clear out exception related thread state
470 __ get_thread(rsi);
471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
474
475 __ bind(_unwind_handler_entry);
476 __ verify_not_null_oop(rax);
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rsi, rax); // Preserve the exception
479 }
480
481 // Preform needed unlocking
482 MonitorExitStub* stub = NULL;
483 if (method()->is_synchronized()) {
484 monitor_address(0, FrameMap::rax_opr);
485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
486 __ unlock_object(rdi, rbx, rax, *stub->entry());
487 __ bind(*stub->continuation());
488 }
489
490 if (compilation()->env()->dtrace_method_probes()) {
491 __ movoop(Address(rsp, 0), method()->constant_encoding());
492 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
493 }
494
495 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
496 __ mov(rax, rsi); // Restore the exception
497 }
498
499 // remove the activation and dispatch to the unwind handler
500 __ remove_frame(initial_frame_size_in_bytes());
501 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
502
503 // Emit the slow path assembly
504 if (stub != NULL) {
505 stub->emit_code(this);
506 }
507
508 return offset;
509 }
510
511
512 int LIR_Assembler::emit_deopt_handler() {
513 // if the last instruction is a call (typically to do a throw which
514 // is coming at the end after block reordering) the return address
515 // must still point into the code area in order to avoid assertion
516 // failures when searching for the corresponding bci => add a nop
517 // (was bug 5/14/1999 - gri)
518 __ nop();
519
520 // generate code for exception handler
521 address handler_base = __ start_a_stub(deopt_handler_size);
522 if (handler_base == NULL) {
523 // not enough space left for the handler
524 bailout("deopt handler overflow");
525 return -1;
526 }
527
528 int offset = code_offset();
529 InternalAddress here(__ pc());
530
531 __ pushptr(here.addr());
532 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
533
534 assert(code_offset() - offset <= deopt_handler_size, "overflow");
535 __ end_a_stub();
536
537 return offset;
538 }
539
540
541 // This is the fast version of java.lang.String.compare; it has not
542 // OSR-entry and therefore, we generate a slow version for OSR's
543 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
544 __ movptr (rbx, rcx); // receiver is in rcx
545 __ movptr (rax, arg1->as_register());
546
547 // Get addresses of first characters from both Strings
548 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
549 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
550 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
551
552
553 // rbx, may be NULL
554 add_debug_info_for_null_check_here(info);
555 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
556 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
557 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
558
559 // compute minimum length (in rax) and difference of lengths (on top of stack)
560 if (VM_Version::supports_cmov()) {
561 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
562 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
563 __ mov (rcx, rbx);
564 __ subptr (rbx, rax); // subtract lengths
565 __ push (rbx); // result
566 __ cmov (Assembler::lessEqual, rax, rcx);
567 } else {
568 Label L;
569 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
570 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
571 __ mov (rax, rbx);
572 __ subptr (rbx, rcx);
573 __ push (rbx);
574 __ jcc (Assembler::lessEqual, L);
575 __ mov (rax, rcx);
576 __ bind (L);
577 }
578 // is minimum length 0?
579 Label noLoop, haveResult;
580 __ testptr (rax, rax);
581 __ jcc (Assembler::zero, noLoop);
582
583 // compare first characters
584 __ load_unsigned_short(rcx, Address(rdi, 0));
585 __ load_unsigned_short(rbx, Address(rsi, 0));
586 __ subl(rcx, rbx);
587 __ jcc(Assembler::notZero, haveResult);
588 // starting loop
589 __ decrement(rax); // we already tested index: skip one
590 __ jcc(Assembler::zero, noLoop);
591
592 // set rsi.edi to the end of the arrays (arrays have same length)
593 // negate the index
594
595 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
596 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
597 __ negptr(rax);
598
599 // compare the strings in a loop
600
601 Label loop;
602 __ align(wordSize);
603 __ bind(loop);
604 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
605 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
606 __ subl(rcx, rbx);
607 __ jcc(Assembler::notZero, haveResult);
608 __ increment(rax);
609 __ jcc(Assembler::notZero, loop);
610
611 // strings are equal up to min length
612
613 __ bind(noLoop);
614 __ pop(rax);
615 return_op(LIR_OprFact::illegalOpr);
616
617 __ bind(haveResult);
618 // leave instruction is going to discard the TOS value
619 __ mov (rax, rcx); // result of call is in rax,
620 }
621
622
623 void LIR_Assembler::return_op(LIR_Opr result) {
624 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
625 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
626 assert(result->fpu() == 0, "result must already be on TOS");
627 }
628
629 // Pop the stack before the safepoint code
630 __ remove_frame(initial_frame_size_in_bytes());
631
632 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
633
634 // Note: we do not need to round double result; float result has the right precision
635 // the poll sets the condition code, but no data registers
636 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
637 relocInfo::poll_return_type);
638
639 // NOTE: the requires that the polling page be reachable else the reloc
640 // goes to the movq that loads the address and not the faulting instruction
641 // which breaks the signal handler code
642
643 __ test32(rax, polling_page);
644
645 __ ret(0);
646 }
647
648
649 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
650 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
651 relocInfo::poll_type);
652
653 if (info != NULL) {
654 add_debug_info_for_branch(info);
655 } else {
656 ShouldNotReachHere();
657 }
658
659 int offset = __ offset();
660
661 // NOTE: the requires that the polling page be reachable else the reloc
662 // goes to the movq that loads the address and not the faulting instruction
663 // which breaks the signal handler code
664
665 __ test32(rax, polling_page);
666 return offset;
667 }
668
669
670 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
671 if (from_reg != to_reg) __ mov(to_reg, from_reg);
672 }
673
674 void LIR_Assembler::swap_reg(Register a, Register b) {
675 __ xchgptr(a, b);
676 }
677
678
679 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
680 assert(src->is_constant(), "should not call otherwise");
681 assert(dest->is_register(), "should not call otherwise");
682 LIR_Const* c = src->as_constant_ptr();
683
684 switch (c->type()) {
685 case T_INT:
686 case T_ADDRESS: {
687 assert(patch_code == lir_patch_none, "no patching handled here");
688 __ movl(dest->as_register(), c->as_jint());
689 break;
690 }
691
692 case T_LONG: {
693 assert(patch_code == lir_patch_none, "no patching handled here");
694 #ifdef _LP64
695 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
696 #else
697 __ movptr(dest->as_register_lo(), c->as_jint_lo());
698 __ movptr(dest->as_register_hi(), c->as_jint_hi());
699 #endif // _LP64
700 break;
701 }
702
703 case T_OBJECT: {
704 if (patch_code != lir_patch_none) {
705 jobject2reg_with_patching(dest->as_register(), info);
706 } else {
707 __ movoop(dest->as_register(), c->as_jobject());
708 }
709 break;
710 }
711
712 case T_FLOAT: {
713 if (dest->is_single_xmm()) {
714 if (c->is_zero_float()) {
715 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
716 } else {
717 __ movflt(dest->as_xmm_float_reg(),
718 InternalAddress(float_constant(c->as_jfloat())));
719 }
720 } else {
721 assert(dest->is_single_fpu(), "must be");
722 assert(dest->fpu_regnr() == 0, "dest must be TOS");
723 if (c->is_zero_float()) {
724 __ fldz();
725 } else if (c->is_one_float()) {
726 __ fld1();
727 } else {
728 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
729 }
730 }
731 break;
732 }
733
734 case T_DOUBLE: {
735 if (dest->is_double_xmm()) {
736 if (c->is_zero_double()) {
737 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
738 } else {
739 __ movdbl(dest->as_xmm_double_reg(),
740 InternalAddress(double_constant(c->as_jdouble())));
741 }
742 } else {
743 assert(dest->is_double_fpu(), "must be");
744 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
745 if (c->is_zero_double()) {
746 __ fldz();
747 } else if (c->is_one_double()) {
748 __ fld1();
749 } else {
750 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
751 }
752 }
753 break;
754 }
755
756 default:
757 ShouldNotReachHere();
758 }
759 }
760
761 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
762 assert(src->is_constant(), "should not call otherwise");
763 assert(dest->is_stack(), "should not call otherwise");
764 LIR_Const* c = src->as_constant_ptr();
765
766 switch (c->type()) {
767 case T_INT: // fall through
768 case T_FLOAT:
769 case T_ADDRESS:
770 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
771 break;
772
773 case T_OBJECT:
774 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
775 break;
776
777 case T_LONG: // fall through
778 case T_DOUBLE:
779 #ifdef _LP64
780 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
781 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
782 #else
783 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
784 lo_word_offset_in_bytes), c->as_jint_lo_bits());
785 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
786 hi_word_offset_in_bytes), c->as_jint_hi_bits());
787 #endif // _LP64
788 break;
789
790 default:
791 ShouldNotReachHere();
792 }
793 }
794
795 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
796 assert(src->is_constant(), "should not call otherwise");
797 assert(dest->is_address(), "should not call otherwise");
798 LIR_Const* c = src->as_constant_ptr();
799 LIR_Address* addr = dest->as_address_ptr();
800
801 int null_check_here = code_offset();
802 switch (type) {
803 case T_INT: // fall through
804 case T_FLOAT:
805 case T_ADDRESS:
806 __ movl(as_Address(addr), c->as_jint_bits());
807 break;
808
809 case T_OBJECT: // fall through
810 case T_ARRAY:
811 if (c->as_jobject() == NULL) {
812 __ movptr(as_Address(addr), NULL_WORD);
813 } else {
814 if (is_literal_address(addr)) {
815 ShouldNotReachHere();
816 __ movoop(as_Address(addr, noreg), c->as_jobject());
817 } else {
818 #ifdef _LP64
819 __ movoop(rscratch1, c->as_jobject());
820 null_check_here = code_offset();
821 __ movptr(as_Address_lo(addr), rscratch1);
822 #else
823 __ movoop(as_Address(addr), c->as_jobject());
824 #endif
825 }
826 }
827 break;
828
829 case T_LONG: // fall through
830 case T_DOUBLE:
831 #ifdef _LP64
832 if (is_literal_address(addr)) {
833 ShouldNotReachHere();
834 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
835 } else {
836 __ movptr(r10, (intptr_t)c->as_jlong_bits());
837 null_check_here = code_offset();
838 __ movptr(as_Address_lo(addr), r10);
839 }
840 #else
841 // Always reachable in 32bit so this doesn't produce useless move literal
842 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
843 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
844 #endif // _LP64
845 break;
846
847 case T_BOOLEAN: // fall through
848 case T_BYTE:
849 __ movb(as_Address(addr), c->as_jint() & 0xFF);
850 break;
851
852 case T_CHAR: // fall through
853 case T_SHORT:
854 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
855 break;
856
857 default:
858 ShouldNotReachHere();
859 };
860
861 if (info != NULL) {
862 add_debug_info_for_null_check(null_check_here, info);
863 }
864 }
865
866
867 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
868 assert(src->is_register(), "should not call otherwise");
869 assert(dest->is_register(), "should not call otherwise");
870
871 // move between cpu-registers
872 if (dest->is_single_cpu()) {
873 #ifdef _LP64
874 if (src->type() == T_LONG) {
875 // Can do LONG -> OBJECT
876 move_regs(src->as_register_lo(), dest->as_register());
877 return;
878 }
879 #endif
880 assert(src->is_single_cpu(), "must match");
881 if (src->type() == T_OBJECT) {
882 __ verify_oop(src->as_register());
883 }
884 move_regs(src->as_register(), dest->as_register());
885
886 } else if (dest->is_double_cpu()) {
887 #ifdef _LP64
888 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
889 // Surprising to me but we can see move of a long to t_object
890 __ verify_oop(src->as_register());
891 move_regs(src->as_register(), dest->as_register_lo());
892 return;
893 }
894 #endif
895 assert(src->is_double_cpu(), "must match");
896 Register f_lo = src->as_register_lo();
897 Register f_hi = src->as_register_hi();
898 Register t_lo = dest->as_register_lo();
899 Register t_hi = dest->as_register_hi();
900 #ifdef _LP64
901 assert(f_hi == f_lo, "must be same");
902 assert(t_hi == t_lo, "must be same");
903 move_regs(f_lo, t_lo);
904 #else
905 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
906
907
908 if (f_lo == t_hi && f_hi == t_lo) {
909 swap_reg(f_lo, f_hi);
910 } else if (f_hi == t_lo) {
911 assert(f_lo != t_hi, "overwriting register");
912 move_regs(f_hi, t_hi);
913 move_regs(f_lo, t_lo);
914 } else {
915 assert(f_hi != t_lo, "overwriting register");
916 move_regs(f_lo, t_lo);
917 move_regs(f_hi, t_hi);
918 }
919 #endif // LP64
920
921 // special moves from fpu-register to xmm-register
922 // necessary for method results
923 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
924 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
925 __ fld_s(Address(rsp, 0));
926 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
927 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
928 __ fld_d(Address(rsp, 0));
929 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
930 __ fstp_s(Address(rsp, 0));
931 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
932 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
933 __ fstp_d(Address(rsp, 0));
934 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
935
936 // move between xmm-registers
937 } else if (dest->is_single_xmm()) {
938 assert(src->is_single_xmm(), "must match");
939 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
940 } else if (dest->is_double_xmm()) {
941 assert(src->is_double_xmm(), "must match");
942 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
943
944 // move between fpu-registers (no instruction necessary because of fpu-stack)
945 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
946 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
947 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
948 } else {
949 ShouldNotReachHere();
950 }
951 }
952
953 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
954 assert(src->is_register(), "should not call otherwise");
955 assert(dest->is_stack(), "should not call otherwise");
956
957 if (src->is_single_cpu()) {
958 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
959 if (type == T_OBJECT || type == T_ARRAY) {
960 __ verify_oop(src->as_register());
961 __ movptr (dst, src->as_register());
962 } else {
963 __ movl (dst, src->as_register());
964 }
965
966 } else if (src->is_double_cpu()) {
967 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
968 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
969 __ movptr (dstLO, src->as_register_lo());
970 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
971
972 } else if (src->is_single_xmm()) {
973 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
974 __ movflt(dst_addr, src->as_xmm_float_reg());
975
976 } else if (src->is_double_xmm()) {
977 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
978 __ movdbl(dst_addr, src->as_xmm_double_reg());
979
980 } else if (src->is_single_fpu()) {
981 assert(src->fpu_regnr() == 0, "argument must be on TOS");
982 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
983 if (pop_fpu_stack) __ fstp_s (dst_addr);
984 else __ fst_s (dst_addr);
985
986 } else if (src->is_double_fpu()) {
987 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
988 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
989 if (pop_fpu_stack) __ fstp_d (dst_addr);
990 else __ fst_d (dst_addr);
991
992 } else {
993 ShouldNotReachHere();
994 }
995 }
996
997
998 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
999 LIR_Address* to_addr = dest->as_address_ptr();
1000 PatchingStub* patch = NULL;
1001
1002 if (type == T_ARRAY || type == T_OBJECT) {
1003 __ verify_oop(src->as_register());
1004 }
1005 if (patch_code != lir_patch_none) {
1006 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1007 Address toa = as_Address(to_addr);
1008 assert(toa.disp() != 0, "must have");
1009 }
1010 if (info != NULL) {
1011 add_debug_info_for_null_check_here(info);
1012 }
1013
1014 switch (type) {
1015 case T_FLOAT: {
1016 if (src->is_single_xmm()) {
1017 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1018 } else {
1019 assert(src->is_single_fpu(), "must be");
1020 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1021 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1022 else __ fst_s (as_Address(to_addr));
1023 }
1024 break;
1025 }
1026
1027 case T_DOUBLE: {
1028 if (src->is_double_xmm()) {
1029 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1030 } else {
1031 assert(src->is_double_fpu(), "must be");
1032 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1033 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1034 else __ fst_d (as_Address(to_addr));
1035 }
1036 break;
1037 }
1038
1039 case T_ADDRESS: // fall through
1040 case T_ARRAY: // fall through
1041 case T_OBJECT: // fall through
1042 #ifdef _LP64
1043 __ movptr(as_Address(to_addr), src->as_register());
1044 break;
1045 #endif // _LP64
1046 case T_INT:
1047 __ movl(as_Address(to_addr), src->as_register());
1048 break;
1049
1050 case T_LONG: {
1051 Register from_lo = src->as_register_lo();
1052 Register from_hi = src->as_register_hi();
1053 #ifdef _LP64
1054 __ movptr(as_Address_lo(to_addr), from_lo);
1055 #else
1056 Register base = to_addr->base()->as_register();
1057 Register index = noreg;
1058 if (to_addr->index()->is_register()) {
1059 index = to_addr->index()->as_register();
1060 }
1061 if (base == from_lo || index == from_lo) {
1062 assert(base != from_hi, "can't be");
1063 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1064 __ movl(as_Address_hi(to_addr), from_hi);
1065 if (patch != NULL) {
1066 patching_epilog(patch, lir_patch_high, base, info);
1067 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1068 patch_code = lir_patch_low;
1069 }
1070 __ movl(as_Address_lo(to_addr), from_lo);
1071 } else {
1072 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1073 __ movl(as_Address_lo(to_addr), from_lo);
1074 if (patch != NULL) {
1075 patching_epilog(patch, lir_patch_low, base, info);
1076 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1077 patch_code = lir_patch_high;
1078 }
1079 __ movl(as_Address_hi(to_addr), from_hi);
1080 }
1081 #endif // _LP64
1082 break;
1083 }
1084
1085 case T_BYTE: // fall through
1086 case T_BOOLEAN: {
1087 Register src_reg = src->as_register();
1088 Address dst_addr = as_Address(to_addr);
1089 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1090 __ movb(dst_addr, src_reg);
1091 break;
1092 }
1093
1094 case T_CHAR: // fall through
1095 case T_SHORT:
1096 __ movw(as_Address(to_addr), src->as_register());
1097 break;
1098
1099 default:
1100 ShouldNotReachHere();
1101 }
1102
1103 if (patch_code != lir_patch_none) {
1104 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1105 }
1106 }
1107
1108
1109 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1110 assert(src->is_stack(), "should not call otherwise");
1111 assert(dest->is_register(), "should not call otherwise");
1112
1113 if (dest->is_single_cpu()) {
1114 if (type == T_ARRAY || type == T_OBJECT) {
1115 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1116 __ verify_oop(dest->as_register());
1117 } else {
1118 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1119 }
1120
1121 } else if (dest->is_double_cpu()) {
1122 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1123 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1124 __ movptr(dest->as_register_lo(), src_addr_LO);
1125 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1126
1127 } else if (dest->is_single_xmm()) {
1128 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1129 __ movflt(dest->as_xmm_float_reg(), src_addr);
1130
1131 } else if (dest->is_double_xmm()) {
1132 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1133 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1134
1135 } else if (dest->is_single_fpu()) {
1136 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1137 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1138 __ fld_s(src_addr);
1139
1140 } else if (dest->is_double_fpu()) {
1141 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1142 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1143 __ fld_d(src_addr);
1144
1145 } else {
1146 ShouldNotReachHere();
1147 }
1148 }
1149
1150
1151 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1152 if (src->is_single_stack()) {
1153 if (type == T_OBJECT || type == T_ARRAY) {
1154 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1155 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1156 } else {
1157 #ifndef _LP64
1158 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1159 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1160 #else
1161 //no pushl on 64bits
1162 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1163 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1164 #endif
1165 }
1166
1167 } else if (src->is_double_stack()) {
1168 #ifdef _LP64
1169 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1170 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1171 #else
1172 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1173 // push and pop the part at src + wordSize, adding wordSize for the previous push
1174 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1175 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1176 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1177 #endif // _LP64
1178
1179 } else {
1180 ShouldNotReachHere();
1181 }
1182 }
1183
1184
1185 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1186 assert(src->is_address(), "should not call otherwise");
1187 assert(dest->is_register(), "should not call otherwise");
1188
1189 LIR_Address* addr = src->as_address_ptr();
1190 Address from_addr = as_Address(addr);
1191
1192 switch (type) {
1193 case T_BOOLEAN: // fall through
1194 case T_BYTE: // fall through
1195 case T_CHAR: // fall through
1196 case T_SHORT:
1197 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1198 // on pre P6 processors we may get partial register stalls
1199 // so blow away the value of to_rinfo before loading a
1200 // partial word into it. Do it here so that it precedes
1201 // the potential patch point below.
1202 __ xorptr(dest->as_register(), dest->as_register());
1203 }
1204 break;
1205 }
1206
1207 PatchingStub* patch = NULL;
1208 if (patch_code != lir_patch_none) {
1209 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1210 assert(from_addr.disp() != 0, "must have");
1211 }
1212 if (info != NULL) {
1213 add_debug_info_for_null_check_here(info);
1214 }
1215
1216 switch (type) {
1217 case T_FLOAT: {
1218 if (dest->is_single_xmm()) {
1219 __ movflt(dest->as_xmm_float_reg(), from_addr);
1220 } else {
1221 assert(dest->is_single_fpu(), "must be");
1222 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1223 __ fld_s(from_addr);
1224 }
1225 break;
1226 }
1227
1228 case T_DOUBLE: {
1229 if (dest->is_double_xmm()) {
1230 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1231 } else {
1232 assert(dest->is_double_fpu(), "must be");
1233 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1234 __ fld_d(from_addr);
1235 }
1236 break;
1237 }
1238
1239 case T_ADDRESS: // fall through
1240 case T_OBJECT: // fall through
1241 case T_ARRAY: // fall through
1242 #ifdef _LP64
1243 __ movptr(dest->as_register(), from_addr);
1244 break;
1245 #endif // _L64
1246 case T_INT:
1247 __ movl(dest->as_register(), from_addr);
1248 break;
1249
1250 case T_LONG: {
1251 Register to_lo = dest->as_register_lo();
1252 Register to_hi = dest->as_register_hi();
1253 #ifdef _LP64
1254 __ movptr(to_lo, as_Address_lo(addr));
1255 #else
1256 Register base = addr->base()->as_register();
1257 Register index = noreg;
1258 if (addr->index()->is_register()) {
1259 index = addr->index()->as_register();
1260 }
1261 if ((base == to_lo && index == to_hi) ||
1262 (base == to_hi && index == to_lo)) {
1263 // addresses with 2 registers are only formed as a result of
1264 // array access so this code will never have to deal with
1265 // patches or null checks.
1266 assert(info == NULL && patch == NULL, "must be");
1267 __ lea(to_hi, as_Address(addr));
1268 __ movl(to_lo, Address(to_hi, 0));
1269 __ movl(to_hi, Address(to_hi, BytesPerWord));
1270 } else if (base == to_lo || index == to_lo) {
1271 assert(base != to_hi, "can't be");
1272 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1273 __ movl(to_hi, as_Address_hi(addr));
1274 if (patch != NULL) {
1275 patching_epilog(patch, lir_patch_high, base, info);
1276 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1277 patch_code = lir_patch_low;
1278 }
1279 __ movl(to_lo, as_Address_lo(addr));
1280 } else {
1281 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1282 __ movl(to_lo, as_Address_lo(addr));
1283 if (patch != NULL) {
1284 patching_epilog(patch, lir_patch_low, base, info);
1285 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1286 patch_code = lir_patch_high;
1287 }
1288 __ movl(to_hi, as_Address_hi(addr));
1289 }
1290 #endif // _LP64
1291 break;
1292 }
1293
1294 case T_BOOLEAN: // fall through
1295 case T_BYTE: {
1296 Register dest_reg = dest->as_register();
1297 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1298 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1299 __ movsbl(dest_reg, from_addr);
1300 } else {
1301 __ movb(dest_reg, from_addr);
1302 __ shll(dest_reg, 24);
1303 __ sarl(dest_reg, 24);
1304 }
1305 break;
1306 }
1307
1308 case T_CHAR: {
1309 Register dest_reg = dest->as_register();
1310 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1311 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1312 __ movzwl(dest_reg, from_addr);
1313 } else {
1314 __ movw(dest_reg, from_addr);
1315 }
1316 break;
1317 }
1318
1319 case T_SHORT: {
1320 Register dest_reg = dest->as_register();
1321 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1322 __ movswl(dest_reg, from_addr);
1323 } else {
1324 __ movw(dest_reg, from_addr);
1325 __ shll(dest_reg, 16);
1326 __ sarl(dest_reg, 16);
1327 }
1328 break;
1329 }
1330
1331 default:
1332 ShouldNotReachHere();
1333 }
1334
1335 if (patch != NULL) {
1336 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1337 }
1338
1339 if (type == T_ARRAY || type == T_OBJECT) {
1340 __ verify_oop(dest->as_register());
1341 }
1342 }
1343
1344
1345 void LIR_Assembler::prefetchr(LIR_Opr src) {
1346 LIR_Address* addr = src->as_address_ptr();
1347 Address from_addr = as_Address(addr);
1348
1349 if (VM_Version::supports_sse()) {
1350 switch (ReadPrefetchInstr) {
1351 case 0:
1352 __ prefetchnta(from_addr); break;
1353 case 1:
1354 __ prefetcht0(from_addr); break;
1355 case 2:
1356 __ prefetcht2(from_addr); break;
1357 default:
1358 ShouldNotReachHere(); break;
1359 }
1360 } else if (VM_Version::supports_3dnow()) {
1361 __ prefetchr(from_addr);
1362 }
1363 }
1364
1365
1366 void LIR_Assembler::prefetchw(LIR_Opr src) {
1367 LIR_Address* addr = src->as_address_ptr();
1368 Address from_addr = as_Address(addr);
1369
1370 if (VM_Version::supports_sse()) {
1371 switch (AllocatePrefetchInstr) {
1372 case 0:
1373 __ prefetchnta(from_addr); break;
1374 case 1:
1375 __ prefetcht0(from_addr); break;
1376 case 2:
1377 __ prefetcht2(from_addr); break;
1378 case 3:
1379 __ prefetchw(from_addr); break;
1380 default:
1381 ShouldNotReachHere(); break;
1382 }
1383 } else if (VM_Version::supports_3dnow()) {
1384 __ prefetchw(from_addr);
1385 }
1386 }
1387
1388
1389 NEEDS_CLEANUP; // This could be static?
1390 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1391 int elem_size = type2aelembytes(type);
1392 switch (elem_size) {
1393 case 1: return Address::times_1;
1394 case 2: return Address::times_2;
1395 case 4: return Address::times_4;
1396 case 8: return Address::times_8;
1397 }
1398 ShouldNotReachHere();
1399 return Address::no_scale;
1400 }
1401
1402
1403 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1404 switch (op->code()) {
1405 case lir_idiv:
1406 case lir_irem:
1407 arithmetic_idiv(op->code(),
1408 op->in_opr1(),
1409 op->in_opr2(),
1410 op->in_opr3(),
1411 op->result_opr(),
1412 op->info());
1413 break;
1414 default: ShouldNotReachHere(); break;
1415 }
1416 }
1417
1418 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1419 #ifdef ASSERT
1420 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1421 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1422 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1423 #endif
1424
1425 if (op->cond() == lir_cond_always) {
1426 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1427 __ jmp (*(op->label()));
1428 } else {
1429 Assembler::Condition acond = Assembler::zero;
1430 if (op->code() == lir_cond_float_branch) {
1431 assert(op->ublock() != NULL, "must have unordered successor");
1432 __ jcc(Assembler::parity, *(op->ublock()->label()));
1433 switch(op->cond()) {
1434 case lir_cond_equal: acond = Assembler::equal; break;
1435 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1436 case lir_cond_less: acond = Assembler::below; break;
1437 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1438 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1439 case lir_cond_greater: acond = Assembler::above; break;
1440 default: ShouldNotReachHere();
1441 }
1442 } else {
1443 switch (op->cond()) {
1444 case lir_cond_equal: acond = Assembler::equal; break;
1445 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1446 case lir_cond_less: acond = Assembler::less; break;
1447 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1448 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1449 case lir_cond_greater: acond = Assembler::greater; break;
1450 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1451 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1452 default: ShouldNotReachHere();
1453 }
1454 }
1455 __ jcc(acond,*(op->label()));
1456 }
1457 }
1458
1459 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1460 LIR_Opr src = op->in_opr();
1461 LIR_Opr dest = op->result_opr();
1462
1463 switch (op->bytecode()) {
1464 case Bytecodes::_i2l:
1465 #ifdef _LP64
1466 __ movl2ptr(dest->as_register_lo(), src->as_register());
1467 #else
1468 move_regs(src->as_register(), dest->as_register_lo());
1469 move_regs(src->as_register(), dest->as_register_hi());
1470 __ sarl(dest->as_register_hi(), 31);
1471 #endif // LP64
1472 break;
1473
1474 case Bytecodes::_l2i:
1475 move_regs(src->as_register_lo(), dest->as_register());
1476 break;
1477
1478 case Bytecodes::_i2b:
1479 move_regs(src->as_register(), dest->as_register());
1480 __ sign_extend_byte(dest->as_register());
1481 break;
1482
1483 case Bytecodes::_i2c:
1484 move_regs(src->as_register(), dest->as_register());
1485 __ andl(dest->as_register(), 0xFFFF);
1486 break;
1487
1488 case Bytecodes::_i2s:
1489 move_regs(src->as_register(), dest->as_register());
1490 __ sign_extend_short(dest->as_register());
1491 break;
1492
1493
1494 case Bytecodes::_f2d:
1495 case Bytecodes::_d2f:
1496 if (dest->is_single_xmm()) {
1497 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1498 } else if (dest->is_double_xmm()) {
1499 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1500 } else {
1501 assert(src->fpu() == dest->fpu(), "register must be equal");
1502 // do nothing (float result is rounded later through spilling)
1503 }
1504 break;
1505
1506 case Bytecodes::_i2f:
1507 case Bytecodes::_i2d:
1508 if (dest->is_single_xmm()) {
1509 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1510 } else if (dest->is_double_xmm()) {
1511 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1512 } else {
1513 assert(dest->fpu() == 0, "result must be on TOS");
1514 __ movl(Address(rsp, 0), src->as_register());
1515 __ fild_s(Address(rsp, 0));
1516 }
1517 break;
1518
1519 case Bytecodes::_f2i:
1520 case Bytecodes::_d2i:
1521 if (src->is_single_xmm()) {
1522 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1523 } else if (src->is_double_xmm()) {
1524 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1525 } else {
1526 assert(src->fpu() == 0, "input must be on TOS");
1527 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1528 __ fist_s(Address(rsp, 0));
1529 __ movl(dest->as_register(), Address(rsp, 0));
1530 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1531 }
1532
1533 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1534 assert(op->stub() != NULL, "stub required");
1535 __ cmpl(dest->as_register(), 0x80000000);
1536 __ jcc(Assembler::equal, *op->stub()->entry());
1537 __ bind(*op->stub()->continuation());
1538 break;
1539
1540 case Bytecodes::_l2f:
1541 case Bytecodes::_l2d:
1542 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1543 assert(dest->fpu() == 0, "result must be on TOS");
1544
1545 __ movptr(Address(rsp, 0), src->as_register_lo());
1546 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1547 __ fild_d(Address(rsp, 0));
1548 // float result is rounded later through spilling
1549 break;
1550
1551 case Bytecodes::_f2l:
1552 case Bytecodes::_d2l:
1553 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1554 assert(src->fpu() == 0, "input must be on TOS");
1555 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1556
1557 // instruction sequence too long to inline it here
1558 {
1559 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1560 }
1561 break;
1562
1563 default: ShouldNotReachHere();
1564 }
1565 }
1566
1567 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1568 if (op->init_check()) {
1569 __ cmpl(Address(op->klass()->as_register(),
1570 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1571 instanceKlass::fully_initialized);
1572 add_debug_info_for_null_check_here(op->stub()->info());
1573 __ jcc(Assembler::notEqual, *op->stub()->entry());
1574 }
1575 __ allocate_object(op->obj()->as_register(),
1576 op->tmp1()->as_register(),
1577 op->tmp2()->as_register(),
1578 op->header_size(),
1579 op->object_size(),
1580 op->klass()->as_register(),
1581 *op->stub()->entry());
1582 __ bind(*op->stub()->continuation());
1583 }
1584
1585 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1586 if (UseSlowPath ||
1587 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1588 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1589 __ jmp(*op->stub()->entry());
1590 } else {
1591 Register len = op->len()->as_register();
1592 Register tmp1 = op->tmp1()->as_register();
1593 Register tmp2 = op->tmp2()->as_register();
1594 Register tmp3 = op->tmp3()->as_register();
1595 if (len == tmp1) {
1596 tmp1 = tmp3;
1597 } else if (len == tmp2) {
1598 tmp2 = tmp3;
1599 } else if (len == tmp3) {
1600 // everything is ok
1601 } else {
1602 __ mov(tmp3, len);
1603 }
1604 __ allocate_array(op->obj()->as_register(),
1605 len,
1606 tmp1,
1607 tmp2,
1608 arrayOopDesc::header_size(op->type()),
1609 array_element_size(op->type()),
1610 op->klass()->as_register(),
1611 *op->stub()->entry());
1612 }
1613 __ bind(*op->stub()->continuation());
1614 }
1615
1616 void LIR_Assembler::type_profile_helper(Register mdo,
1617 ciMethodData *md, ciProfileData *data,
1618 Register recv, Label* update_done) {
1619 uint i;
1620 for (i = 0; i < ReceiverTypeData::row_limit(); i++) {
1621 Label next_test;
1622 // See if the receiver is receiver[n].
1623 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1624 __ jccb(Assembler::notEqual, next_test);
1625 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1626 __ addptr(data_addr, DataLayout::counter_increment);
1627 __ jmp(*update_done);
1628 __ bind(next_test);
1629 }
1630
1631 // Didn't find receiver; find next empty slot and fill it in
1632 for (i = 0; i < ReceiverTypeData::row_limit(); i++) {
1633 Label next_test;
1634 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1635 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1636 __ jccb(Assembler::notEqual, next_test);
1637 __ movptr(recv_addr, recv);
1638 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1639 __ jmp(*update_done);
1640 __ bind(next_test);
1641 }
1642 }
1643
1644 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1645 // we always need a stub for the failure case.
1646 CodeStub* stub = op->stub();
1647 Register obj = op->object()->as_register();
1648 Register k_RInfo = op->tmp1()->as_register();
1649 Register klass_RInfo = op->tmp2()->as_register();
1650 Register dst = op->result_opr()->as_register();
1651 ciKlass* k = op->klass();
1652 Register Rtmp1 = noreg;
1653
1654 // check if it needs to be profiled
1655 ciMethodData* md;
1656 ciProfileData* data;
1657
1658 if (op->should_profile()) {
1659 ciMethod* method = op->profiled_method();
1660 assert(method != NULL, "Should have method");
1661 int bci = op->profiled_bci();
1662 md = method->method_data();
1663 if (md == NULL) {
1664 bailout("out of memory building methodDataOop");
1665 return;
1666 }
1667 data = md->bci_to_data(bci);
1668 assert(data != NULL, "need data for type check");
1669 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1670 }
1671 Label profile_cast_success, profile_cast_failure;
1672 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1673 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1674
1675 if (obj == k_RInfo) {
1676 k_RInfo = dst;
1677 } else if (obj == klass_RInfo) {
1678 klass_RInfo = dst;
1679 }
1680 if (k->is_loaded()) {
1681 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1682 } else {
1683 Rtmp1 = op->tmp3()->as_register();
1684 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1685 }
1686
1687 assert_different_registers(obj, k_RInfo, klass_RInfo);
1688 if (!k->is_loaded()) {
1689 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1690 } else {
1691 #ifdef _LP64
1692 __ movoop(k_RInfo, k->constant_encoding());
1693 #endif // _LP64
1694 }
1695 assert(obj != k_RInfo, "must be different");
1696
1697 __ cmpptr(obj, (int32_t)NULL_WORD);
1698 if (op->should_profile()) {
1699 Label not_null;
1700 __ jccb(Assembler::notEqual, not_null);
1701 // Object is null; update MDO and exit
1702 Register mdo = klass_RInfo;
1703 __ movoop(mdo, md->constant_encoding());
1704 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1705 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1706 __ orl(data_addr, header_bits);
1707 __ jmp(*obj_is_null);
1708 __ bind(not_null);
1709 } else {
1710 __ jcc(Assembler::equal, *obj_is_null);
1711 }
1712 __ verify_oop(obj);
1713
1714 if (op->fast_check()) {
1715 // get object class
1716 // not a safepoint as obj null check happens earlier
1717 if (k->is_loaded()) {
1718 #ifdef _LP64
1719 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1720 #else
1721 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1722 #endif // _LP64
1723 } else {
1724 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1725 }
1726 __ jcc(Assembler::notEqual, *failure_target);
1727 // successful cast, fall through to profile or jump
1728 } else {
1729 // get object class
1730 // not a safepoint as obj null check happens earlier
1731 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1732 if (k->is_loaded()) {
1733 // See if we get an immediate positive hit
1734 #ifdef _LP64
1735 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1736 #else
1737 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1738 #endif // _LP64
1739 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1740 __ jcc(Assembler::notEqual, *failure_target);
1741 // successful cast, fall through to profile or jump
1742 } else {
1743 // See if we get an immediate positive hit
1744 __ jcc(Assembler::equal, *success_target);
1745 // check for self
1746 #ifdef _LP64
1747 __ cmpptr(klass_RInfo, k_RInfo);
1748 #else
1749 __ cmpoop(klass_RInfo, k->constant_encoding());
1750 #endif // _LP64
1751 __ jcc(Assembler::equal, *success_target);
1752
1753 __ push(klass_RInfo);
1754 #ifdef _LP64
1755 __ push(k_RInfo);
1756 #else
1757 __ pushoop(k->constant_encoding());
1758 #endif // _LP64
1759 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1760 __ pop(klass_RInfo);
1761 __ pop(klass_RInfo);
1762 // result is a boolean
1763 __ cmpl(klass_RInfo, 0);
1764 __ jcc(Assembler::equal, *failure_target);
1765 // successful cast, fall through to profile or jump
1766 }
1767 } else {
1768 // perform the fast part of the checking logic
1769 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1770 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1771 __ push(klass_RInfo);
1772 __ push(k_RInfo);
1773 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1774 __ pop(klass_RInfo);
1775 __ pop(k_RInfo);
1776 // result is a boolean
1777 __ cmpl(k_RInfo, 0);
1778 __ jcc(Assembler::equal, *failure_target);
1779 // successful cast, fall through to profile or jump
1780 }
1781 }
1782 if (op->should_profile()) {
1783 Register mdo = klass_RInfo, recv = k_RInfo;
1784 __ bind(profile_cast_success);
1785 __ movoop(mdo, md->constant_encoding());
1786 __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes()));
1787 Label update_done;
1788 type_profile_helper(mdo, md, data, recv, success);
1789 __ jmp(*success);
1790
1791 __ bind(profile_cast_failure);
1792 __ movoop(mdo, md->constant_encoding());
1793 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1794 __ subptr(counter_addr, DataLayout::counter_increment);
1795 __ jmp(*failure);
1796 }
1797 __ jmp(*success);
1798 }
1799
1800
1801 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1802 LIR_Code code = op->code();
1803 if (code == lir_store_check) {
1804 Register value = op->object()->as_register();
1805 Register array = op->array()->as_register();
1806 Register k_RInfo = op->tmp1()->as_register();
1807 Register klass_RInfo = op->tmp2()->as_register();
1808 Register Rtmp1 = op->tmp3()->as_register();
1809
1810 CodeStub* stub = op->stub();
1811
1812 // check if it needs to be profiled
1813 ciMethodData* md;
1814 ciProfileData* data;
1815
1816 if (op->should_profile()) {
1817 ciMethod* method = op->profiled_method();
1818 assert(method != NULL, "Should have method");
1819 int bci = op->profiled_bci();
1820 md = method->method_data();
1821 if (md == NULL) {
1822 bailout("out of memory building methodDataOop");
1823 return;
1824 }
1825 data = md->bci_to_data(bci);
1826 assert(data != NULL, "need data for type check");
1827 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1828 }
1829 Label profile_cast_success, profile_cast_failure, done;
1830 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1831 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1832
1833 __ cmpptr(value, (int32_t)NULL_WORD);
1834 if (op->should_profile()) {
1835 Label not_null;
1836 __ jccb(Assembler::notEqual, not_null);
1837 // Object is null; update MDO and exit
1838 Register mdo = klass_RInfo;
1839 __ movoop(mdo, md->constant_encoding());
1840 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1841 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1842 __ orl(data_addr, header_bits);
1843 __ jmp(done);
1844 __ bind(not_null);
1845 } else {
1846 __ jcc(Assembler::equal, done);
1847 }
1848
1849 add_debug_info_for_null_check_here(op->info_for_exception());
1850 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1851 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1852
1853 // get instance klass
1854 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1855 // perform the fast part of the checking logic
1856 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1857 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1858 __ push(klass_RInfo);
1859 __ push(k_RInfo);
1860 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1861 __ pop(klass_RInfo);
1862 __ pop(k_RInfo);
1863 // result is a boolean
1864 __ cmpl(k_RInfo, 0);
1865 __ jcc(Assembler::equal, *failure_target);
1866 // fall through to the success case
1867
1868 if (op->should_profile()) {
1869 Register mdo = klass_RInfo, recv = k_RInfo;
1870 __ bind(profile_cast_success);
1871 __ movoop(mdo, md->constant_encoding());
1872 __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes()));
1873 Label update_done;
1874 type_profile_helper(mdo, md, data, recv, &done);
1875 __ jmpb(done);
1876
1877 __ bind(profile_cast_failure);
1878 __ movoop(mdo, md->constant_encoding());
1879 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1880 __ subptr(counter_addr, DataLayout::counter_increment);
1881 __ jmp(*stub->entry());
1882 }
1883
1884 __ bind(done);
1885 } else
1886 if (code == lir_checkcast) {
1887 Register obj = op->object()->as_register();
1888 Register dst = op->result_opr()->as_register();
1889 Label success;
1890 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1891 __ bind(success);
1892 if (dst != obj) {
1893 __ mov(dst, obj);
1894 }
1895 } else
1896 if (code == lir_instanceof) {
1897 Register obj = op->object()->as_register();
1898 Register dst = op->result_opr()->as_register();
1899 Label success, failure, done;
1900 emit_typecheck_helper(op, &success, &failure, &failure);
1901 __ bind(failure);
1902 __ xorptr(dst, dst);
1903 __ jmpb(done);
1904 __ bind(success);
1905 __ movptr(dst, 1);
1906 __ bind(done);
1907 } else {
1908 ShouldNotReachHere();
1909 }
1910
1911 }
1912
1913
1914 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1915 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1916 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1917 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1918 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1919 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1920 Register addr = op->addr()->as_register();
1921 if (os::is_MP()) {
1922 __ lock();
1923 }
1924 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1925
1926 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1927 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1928 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1929 Register newval = op->new_value()->as_register();
1930 Register cmpval = op->cmp_value()->as_register();
1931 assert(cmpval == rax, "wrong register");
1932 assert(newval != NULL, "new val must be register");
1933 assert(cmpval != newval, "cmp and new values must be in different registers");
1934 assert(cmpval != addr, "cmp and addr must be in different registers");
1935 assert(newval != addr, "new value and addr must be in different registers");
1936 if (os::is_MP()) {
1937 __ lock();
1938 }
1939 if ( op->code() == lir_cas_obj) {
1940 __ cmpxchgptr(newval, Address(addr, 0));
1941 } else if (op->code() == lir_cas_int) {
1942 __ cmpxchgl(newval, Address(addr, 0));
1943 } else {
1944 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1945 }
1946 #ifdef _LP64
1947 } else if (op->code() == lir_cas_long) {
1948 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1949 Register newval = op->new_value()->as_register_lo();
1950 Register cmpval = op->cmp_value()->as_register_lo();
1951 assert(cmpval == rax, "wrong register");
1952 assert(newval != NULL, "new val must be register");
1953 assert(cmpval != newval, "cmp and new values must be in different registers");
1954 assert(cmpval != addr, "cmp and addr must be in different registers");
1955 assert(newval != addr, "new value and addr must be in different registers");
1956 if (os::is_MP()) {
1957 __ lock();
1958 }
1959 __ cmpxchgq(newval, Address(addr, 0));
1960 #endif // _LP64
1961 } else {
1962 Unimplemented();
1963 }
1964 }
1965
1966 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1967 Assembler::Condition acond, ncond;
1968 switch (condition) {
1969 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1970 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1971 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1972 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1973 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1974 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1975 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1976 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1977 default: ShouldNotReachHere();
1978 }
1979
1980 if (opr1->is_cpu_register()) {
1981 reg2reg(opr1, result);
1982 } else if (opr1->is_stack()) {
1983 stack2reg(opr1, result, result->type());
1984 } else if (opr1->is_constant()) {
1985 const2reg(opr1, result, lir_patch_none, NULL);
1986 } else {
1987 ShouldNotReachHere();
1988 }
1989
1990 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1991 // optimized version that does not require a branch
1992 if (opr2->is_single_cpu()) {
1993 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1994 __ cmov(ncond, result->as_register(), opr2->as_register());
1995 } else if (opr2->is_double_cpu()) {
1996 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1997 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1998 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1999 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2000 } else if (opr2->is_single_stack()) {
2001 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2002 } else if (opr2->is_double_stack()) {
2003 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2004 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2005 } else {
2006 ShouldNotReachHere();
2007 }
2008
2009 } else {
2010 Label skip;
2011 __ jcc (acond, skip);
2012 if (opr2->is_cpu_register()) {
2013 reg2reg(opr2, result);
2014 } else if (opr2->is_stack()) {
2015 stack2reg(opr2, result, result->type());
2016 } else if (opr2->is_constant()) {
2017 const2reg(opr2, result, lir_patch_none, NULL);
2018 } else {
2019 ShouldNotReachHere();
2020 }
2021 __ bind(skip);
2022 }
2023 }
2024
2025
2026 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2027 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2028
2029 if (left->is_single_cpu()) {
2030 assert(left == dest, "left and dest must be equal");
2031 Register lreg = left->as_register();
2032
2033 if (right->is_single_cpu()) {
2034 // cpu register - cpu register
2035 Register rreg = right->as_register();
2036 switch (code) {
2037 case lir_add: __ addl (lreg, rreg); break;
2038 case lir_sub: __ subl (lreg, rreg); break;
2039 case lir_mul: __ imull(lreg, rreg); break;
2040 default: ShouldNotReachHere();
2041 }
2042
2043 } else if (right->is_stack()) {
2044 // cpu register - stack
2045 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2046 switch (code) {
2047 case lir_add: __ addl(lreg, raddr); break;
2048 case lir_sub: __ subl(lreg, raddr); break;
2049 default: ShouldNotReachHere();
2050 }
2051
2052 } else if (right->is_constant()) {
2053 // cpu register - constant
2054 jint c = right->as_constant_ptr()->as_jint();
2055 switch (code) {
2056 case lir_add: {
2057 __ incrementl(lreg, c);
2058 break;
2059 }
2060 case lir_sub: {
2061 __ decrementl(lreg, c);
2062 break;
2063 }
2064 default: ShouldNotReachHere();
2065 }
2066
2067 } else {
2068 ShouldNotReachHere();
2069 }
2070
2071 } else if (left->is_double_cpu()) {
2072 assert(left == dest, "left and dest must be equal");
2073 Register lreg_lo = left->as_register_lo();
2074 Register lreg_hi = left->as_register_hi();
2075
2076 if (right->is_double_cpu()) {
2077 // cpu register - cpu register
2078 Register rreg_lo = right->as_register_lo();
2079 Register rreg_hi = right->as_register_hi();
2080 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2081 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2082 switch (code) {
2083 case lir_add:
2084 __ addptr(lreg_lo, rreg_lo);
2085 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2086 break;
2087 case lir_sub:
2088 __ subptr(lreg_lo, rreg_lo);
2089 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2090 break;
2091 case lir_mul:
2092 #ifdef _LP64
2093 __ imulq(lreg_lo, rreg_lo);
2094 #else
2095 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2096 __ imull(lreg_hi, rreg_lo);
2097 __ imull(rreg_hi, lreg_lo);
2098 __ addl (rreg_hi, lreg_hi);
2099 __ mull (rreg_lo);
2100 __ addl (lreg_hi, rreg_hi);
2101 #endif // _LP64
2102 break;
2103 default:
2104 ShouldNotReachHere();
2105 }
2106
2107 } else if (right->is_constant()) {
2108 // cpu register - constant
2109 #ifdef _LP64
2110 jlong c = right->as_constant_ptr()->as_jlong_bits();
2111 __ movptr(r10, (intptr_t) c);
2112 switch (code) {
2113 case lir_add:
2114 __ addptr(lreg_lo, r10);
2115 break;
2116 case lir_sub:
2117 __ subptr(lreg_lo, r10);
2118 break;
2119 default:
2120 ShouldNotReachHere();
2121 }
2122 #else
2123 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2124 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2125 switch (code) {
2126 case lir_add:
2127 __ addptr(lreg_lo, c_lo);
2128 __ adcl(lreg_hi, c_hi);
2129 break;
2130 case lir_sub:
2131 __ subptr(lreg_lo, c_lo);
2132 __ sbbl(lreg_hi, c_hi);
2133 break;
2134 default:
2135 ShouldNotReachHere();
2136 }
2137 #endif // _LP64
2138
2139 } else {
2140 ShouldNotReachHere();
2141 }
2142
2143 } else if (left->is_single_xmm()) {
2144 assert(left == dest, "left and dest must be equal");
2145 XMMRegister lreg = left->as_xmm_float_reg();
2146
2147 if (right->is_single_xmm()) {
2148 XMMRegister rreg = right->as_xmm_float_reg();
2149 switch (code) {
2150 case lir_add: __ addss(lreg, rreg); break;
2151 case lir_sub: __ subss(lreg, rreg); break;
2152 case lir_mul_strictfp: // fall through
2153 case lir_mul: __ mulss(lreg, rreg); break;
2154 case lir_div_strictfp: // fall through
2155 case lir_div: __ divss(lreg, rreg); break;
2156 default: ShouldNotReachHere();
2157 }
2158 } else {
2159 Address raddr;
2160 if (right->is_single_stack()) {
2161 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2162 } else if (right->is_constant()) {
2163 // hack for now
2164 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2165 } else {
2166 ShouldNotReachHere();
2167 }
2168 switch (code) {
2169 case lir_add: __ addss(lreg, raddr); break;
2170 case lir_sub: __ subss(lreg, raddr); break;
2171 case lir_mul_strictfp: // fall through
2172 case lir_mul: __ mulss(lreg, raddr); break;
2173 case lir_div_strictfp: // fall through
2174 case lir_div: __ divss(lreg, raddr); break;
2175 default: ShouldNotReachHere();
2176 }
2177 }
2178
2179 } else if (left->is_double_xmm()) {
2180 assert(left == dest, "left and dest must be equal");
2181
2182 XMMRegister lreg = left->as_xmm_double_reg();
2183 if (right->is_double_xmm()) {
2184 XMMRegister rreg = right->as_xmm_double_reg();
2185 switch (code) {
2186 case lir_add: __ addsd(lreg, rreg); break;
2187 case lir_sub: __ subsd(lreg, rreg); break;
2188 case lir_mul_strictfp: // fall through
2189 case lir_mul: __ mulsd(lreg, rreg); break;
2190 case lir_div_strictfp: // fall through
2191 case lir_div: __ divsd(lreg, rreg); break;
2192 default: ShouldNotReachHere();
2193 }
2194 } else {
2195 Address raddr;
2196 if (right->is_double_stack()) {
2197 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2198 } else if (right->is_constant()) {
2199 // hack for now
2200 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2201 } else {
2202 ShouldNotReachHere();
2203 }
2204 switch (code) {
2205 case lir_add: __ addsd(lreg, raddr); break;
2206 case lir_sub: __ subsd(lreg, raddr); break;
2207 case lir_mul_strictfp: // fall through
2208 case lir_mul: __ mulsd(lreg, raddr); break;
2209 case lir_div_strictfp: // fall through
2210 case lir_div: __ divsd(lreg, raddr); break;
2211 default: ShouldNotReachHere();
2212 }
2213 }
2214
2215 } else if (left->is_single_fpu()) {
2216 assert(dest->is_single_fpu(), "fpu stack allocation required");
2217
2218 if (right->is_single_fpu()) {
2219 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2220
2221 } else {
2222 assert(left->fpu_regnr() == 0, "left must be on TOS");
2223 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2224
2225 Address raddr;
2226 if (right->is_single_stack()) {
2227 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2228 } else if (right->is_constant()) {
2229 address const_addr = float_constant(right->as_jfloat());
2230 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2231 // hack for now
2232 raddr = __ as_Address(InternalAddress(const_addr));
2233 } else {
2234 ShouldNotReachHere();
2235 }
2236
2237 switch (code) {
2238 case lir_add: __ fadd_s(raddr); break;
2239 case lir_sub: __ fsub_s(raddr); break;
2240 case lir_mul_strictfp: // fall through
2241 case lir_mul: __ fmul_s(raddr); break;
2242 case lir_div_strictfp: // fall through
2243 case lir_div: __ fdiv_s(raddr); break;
2244 default: ShouldNotReachHere();
2245 }
2246 }
2247
2248 } else if (left->is_double_fpu()) {
2249 assert(dest->is_double_fpu(), "fpu stack allocation required");
2250
2251 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2252 // Double values require special handling for strictfp mul/div on x86
2253 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2254 __ fmulp(left->fpu_regnrLo() + 1);
2255 }
2256
2257 if (right->is_double_fpu()) {
2258 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2259
2260 } else {
2261 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2262 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2263
2264 Address raddr;
2265 if (right->is_double_stack()) {
2266 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2267 } else if (right->is_constant()) {
2268 // hack for now
2269 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2270 } else {
2271 ShouldNotReachHere();
2272 }
2273
2274 switch (code) {
2275 case lir_add: __ fadd_d(raddr); break;
2276 case lir_sub: __ fsub_d(raddr); break;
2277 case lir_mul_strictfp: // fall through
2278 case lir_mul: __ fmul_d(raddr); break;
2279 case lir_div_strictfp: // fall through
2280 case lir_div: __ fdiv_d(raddr); break;
2281 default: ShouldNotReachHere();
2282 }
2283 }
2284
2285 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2286 // Double values require special handling for strictfp mul/div on x86
2287 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2288 __ fmulp(dest->fpu_regnrLo() + 1);
2289 }
2290
2291 } else if (left->is_single_stack() || left->is_address()) {
2292 assert(left == dest, "left and dest must be equal");
2293
2294 Address laddr;
2295 if (left->is_single_stack()) {
2296 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2297 } else if (left->is_address()) {
2298 laddr = as_Address(left->as_address_ptr());
2299 } else {
2300 ShouldNotReachHere();
2301 }
2302
2303 if (right->is_single_cpu()) {
2304 Register rreg = right->as_register();
2305 switch (code) {
2306 case lir_add: __ addl(laddr, rreg); break;
2307 case lir_sub: __ subl(laddr, rreg); break;
2308 default: ShouldNotReachHere();
2309 }
2310 } else if (right->is_constant()) {
2311 jint c = right->as_constant_ptr()->as_jint();
2312 switch (code) {
2313 case lir_add: {
2314 __ incrementl(laddr, c);
2315 break;
2316 }
2317 case lir_sub: {
2318 __ decrementl(laddr, c);
2319 break;
2320 }
2321 default: ShouldNotReachHere();
2322 }
2323 } else {
2324 ShouldNotReachHere();
2325 }
2326
2327 } else {
2328 ShouldNotReachHere();
2329 }
2330 }
2331
2332 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2333 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2334 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2335 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2336
2337 bool left_is_tos = (left_index == 0);
2338 bool dest_is_tos = (dest_index == 0);
2339 int non_tos_index = (left_is_tos ? right_index : left_index);
2340
2341 switch (code) {
2342 case lir_add:
2343 if (pop_fpu_stack) __ faddp(non_tos_index);
2344 else if (dest_is_tos) __ fadd (non_tos_index);
2345 else __ fadda(non_tos_index);
2346 break;
2347
2348 case lir_sub:
2349 if (left_is_tos) {
2350 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2351 else if (dest_is_tos) __ fsub (non_tos_index);
2352 else __ fsubra(non_tos_index);
2353 } else {
2354 if (pop_fpu_stack) __ fsubp (non_tos_index);
2355 else if (dest_is_tos) __ fsubr (non_tos_index);
2356 else __ fsuba (non_tos_index);
2357 }
2358 break;
2359
2360 case lir_mul_strictfp: // fall through
2361 case lir_mul:
2362 if (pop_fpu_stack) __ fmulp(non_tos_index);
2363 else if (dest_is_tos) __ fmul (non_tos_index);
2364 else __ fmula(non_tos_index);
2365 break;
2366
2367 case lir_div_strictfp: // fall through
2368 case lir_div:
2369 if (left_is_tos) {
2370 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2371 else if (dest_is_tos) __ fdiv (non_tos_index);
2372 else __ fdivra(non_tos_index);
2373 } else {
2374 if (pop_fpu_stack) __ fdivp (non_tos_index);
2375 else if (dest_is_tos) __ fdivr (non_tos_index);
2376 else __ fdiva (non_tos_index);
2377 }
2378 break;
2379
2380 case lir_rem:
2381 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2382 __ fremr(noreg);
2383 break;
2384
2385 default:
2386 ShouldNotReachHere();
2387 }
2388 }
2389
2390
2391 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2392 if (value->is_double_xmm()) {
2393 switch(code) {
2394 case lir_abs :
2395 {
2396 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2397 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2398 }
2399 __ andpd(dest->as_xmm_double_reg(),
2400 ExternalAddress((address)double_signmask_pool));
2401 }
2402 break;
2403
2404 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2405 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2406 default : ShouldNotReachHere();
2407 }
2408
2409 } else if (value->is_double_fpu()) {
2410 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2411 switch(code) {
2412 case lir_log : __ flog() ; break;
2413 case lir_log10 : __ flog10() ; break;
2414 case lir_abs : __ fabs() ; break;
2415 case lir_sqrt : __ fsqrt(); break;
2416 case lir_sin :
2417 // Should consider not saving rbx, if not necessary
2418 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2419 break;
2420 case lir_cos :
2421 // Should consider not saving rbx, if not necessary
2422 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2423 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2424 break;
2425 case lir_tan :
2426 // Should consider not saving rbx, if not necessary
2427 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2428 break;
2429 default : ShouldNotReachHere();
2430 }
2431 } else {
2432 Unimplemented();
2433 }
2434 }
2435
2436 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2437 // assert(left->destroys_register(), "check");
2438 if (left->is_single_cpu()) {
2439 Register reg = left->as_register();
2440 if (right->is_constant()) {
2441 int val = right->as_constant_ptr()->as_jint();
2442 switch (code) {
2443 case lir_logic_and: __ andl (reg, val); break;
2444 case lir_logic_or: __ orl (reg, val); break;
2445 case lir_logic_xor: __ xorl (reg, val); break;
2446 default: ShouldNotReachHere();
2447 }
2448 } else if (right->is_stack()) {
2449 // added support for stack operands
2450 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2451 switch (code) {
2452 case lir_logic_and: __ andl (reg, raddr); break;
2453 case lir_logic_or: __ orl (reg, raddr); break;
2454 case lir_logic_xor: __ xorl (reg, raddr); break;
2455 default: ShouldNotReachHere();
2456 }
2457 } else {
2458 Register rright = right->as_register();
2459 switch (code) {
2460 case lir_logic_and: __ andptr (reg, rright); break;
2461 case lir_logic_or : __ orptr (reg, rright); break;
2462 case lir_logic_xor: __ xorptr (reg, rright); break;
2463 default: ShouldNotReachHere();
2464 }
2465 }
2466 move_regs(reg, dst->as_register());
2467 } else {
2468 Register l_lo = left->as_register_lo();
2469 Register l_hi = left->as_register_hi();
2470 if (right->is_constant()) {
2471 #ifdef _LP64
2472 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2473 switch (code) {
2474 case lir_logic_and:
2475 __ andq(l_lo, rscratch1);
2476 break;
2477 case lir_logic_or:
2478 __ orq(l_lo, rscratch1);
2479 break;
2480 case lir_logic_xor:
2481 __ xorq(l_lo, rscratch1);
2482 break;
2483 default: ShouldNotReachHere();
2484 }
2485 #else
2486 int r_lo = right->as_constant_ptr()->as_jint_lo();
2487 int r_hi = right->as_constant_ptr()->as_jint_hi();
2488 switch (code) {
2489 case lir_logic_and:
2490 __ andl(l_lo, r_lo);
2491 __ andl(l_hi, r_hi);
2492 break;
2493 case lir_logic_or:
2494 __ orl(l_lo, r_lo);
2495 __ orl(l_hi, r_hi);
2496 break;
2497 case lir_logic_xor:
2498 __ xorl(l_lo, r_lo);
2499 __ xorl(l_hi, r_hi);
2500 break;
2501 default: ShouldNotReachHere();
2502 }
2503 #endif // _LP64
2504 } else {
2505 #ifdef _LP64
2506 Register r_lo;
2507 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2508 r_lo = right->as_register();
2509 } else {
2510 r_lo = right->as_register_lo();
2511 }
2512 #else
2513 Register r_lo = right->as_register_lo();
2514 Register r_hi = right->as_register_hi();
2515 assert(l_lo != r_hi, "overwriting registers");
2516 #endif
2517 switch (code) {
2518 case lir_logic_and:
2519 __ andptr(l_lo, r_lo);
2520 NOT_LP64(__ andptr(l_hi, r_hi);)
2521 break;
2522 case lir_logic_or:
2523 __ orptr(l_lo, r_lo);
2524 NOT_LP64(__ orptr(l_hi, r_hi);)
2525 break;
2526 case lir_logic_xor:
2527 __ xorptr(l_lo, r_lo);
2528 NOT_LP64(__ xorptr(l_hi, r_hi);)
2529 break;
2530 default: ShouldNotReachHere();
2531 }
2532 }
2533
2534 Register dst_lo = dst->as_register_lo();
2535 Register dst_hi = dst->as_register_hi();
2536
2537 #ifdef _LP64
2538 move_regs(l_lo, dst_lo);
2539 #else
2540 if (dst_lo == l_hi) {
2541 assert(dst_hi != l_lo, "overwriting registers");
2542 move_regs(l_hi, dst_hi);
2543 move_regs(l_lo, dst_lo);
2544 } else {
2545 assert(dst_lo != l_hi, "overwriting registers");
2546 move_regs(l_lo, dst_lo);
2547 move_regs(l_hi, dst_hi);
2548 }
2549 #endif // _LP64
2550 }
2551 }
2552
2553
2554 // we assume that rax, and rdx can be overwritten
2555 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2556
2557 assert(left->is_single_cpu(), "left must be register");
2558 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2559 assert(result->is_single_cpu(), "result must be register");
2560
2561 // assert(left->destroys_register(), "check");
2562 // assert(right->destroys_register(), "check");
2563
2564 Register lreg = left->as_register();
2565 Register dreg = result->as_register();
2566
2567 if (right->is_constant()) {
2568 int divisor = right->as_constant_ptr()->as_jint();
2569 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2570 if (code == lir_idiv) {
2571 assert(lreg == rax, "must be rax,");
2572 assert(temp->as_register() == rdx, "tmp register must be rdx");
2573 __ cdql(); // sign extend into rdx:rax
2574 if (divisor == 2) {
2575 __ subl(lreg, rdx);
2576 } else {
2577 __ andl(rdx, divisor - 1);
2578 __ addl(lreg, rdx);
2579 }
2580 __ sarl(lreg, log2_intptr(divisor));
2581 move_regs(lreg, dreg);
2582 } else if (code == lir_irem) {
2583 Label done;
2584 __ mov(dreg, lreg);
2585 __ andl(dreg, 0x80000000 | (divisor - 1));
2586 __ jcc(Assembler::positive, done);
2587 __ decrement(dreg);
2588 __ orl(dreg, ~(divisor - 1));
2589 __ increment(dreg);
2590 __ bind(done);
2591 } else {
2592 ShouldNotReachHere();
2593 }
2594 } else {
2595 Register rreg = right->as_register();
2596 assert(lreg == rax, "left register must be rax,");
2597 assert(rreg != rdx, "right register must not be rdx");
2598 assert(temp->as_register() == rdx, "tmp register must be rdx");
2599
2600 move_regs(lreg, rax);
2601
2602 int idivl_offset = __ corrected_idivl(rreg);
2603 add_debug_info_for_div0(idivl_offset, info);
2604 if (code == lir_irem) {
2605 move_regs(rdx, dreg); // result is in rdx
2606 } else {
2607 move_regs(rax, dreg);
2608 }
2609 }
2610 }
2611
2612
2613 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2614 if (opr1->is_single_cpu()) {
2615 Register reg1 = opr1->as_register();
2616 if (opr2->is_single_cpu()) {
2617 // cpu register - cpu register
2618 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2619 __ cmpptr(reg1, opr2->as_register());
2620 } else {
2621 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2622 __ cmpl(reg1, opr2->as_register());
2623 }
2624 } else if (opr2->is_stack()) {
2625 // cpu register - stack
2626 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2627 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2628 } else {
2629 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2630 }
2631 } else if (opr2->is_constant()) {
2632 // cpu register - constant
2633 LIR_Const* c = opr2->as_constant_ptr();
2634 if (c->type() == T_INT) {
2635 __ cmpl(reg1, c->as_jint());
2636 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2637 // In 64bit oops are single register
2638 jobject o = c->as_jobject();
2639 if (o == NULL) {
2640 __ cmpptr(reg1, (int32_t)NULL_WORD);
2641 } else {
2642 #ifdef _LP64
2643 __ movoop(rscratch1, o);
2644 __ cmpptr(reg1, rscratch1);
2645 #else
2646 __ cmpoop(reg1, c->as_jobject());
2647 #endif // _LP64
2648 }
2649 } else {
2650 ShouldNotReachHere();
2651 }
2652 // cpu register - address
2653 } else if (opr2->is_address()) {
2654 if (op->info() != NULL) {
2655 add_debug_info_for_null_check_here(op->info());
2656 }
2657 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2658 } else {
2659 ShouldNotReachHere();
2660 }
2661
2662 } else if(opr1->is_double_cpu()) {
2663 Register xlo = opr1->as_register_lo();
2664 Register xhi = opr1->as_register_hi();
2665 if (opr2->is_double_cpu()) {
2666 #ifdef _LP64
2667 __ cmpptr(xlo, opr2->as_register_lo());
2668 #else
2669 // cpu register - cpu register
2670 Register ylo = opr2->as_register_lo();
2671 Register yhi = opr2->as_register_hi();
2672 __ subl(xlo, ylo);
2673 __ sbbl(xhi, yhi);
2674 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2675 __ orl(xhi, xlo);
2676 }
2677 #endif // _LP64
2678 } else if (opr2->is_constant()) {
2679 // cpu register - constant 0
2680 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2681 #ifdef _LP64
2682 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2683 #else
2684 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2685 __ orl(xhi, xlo);
2686 #endif // _LP64
2687 } else {
2688 ShouldNotReachHere();
2689 }
2690
2691 } else if (opr1->is_single_xmm()) {
2692 XMMRegister reg1 = opr1->as_xmm_float_reg();
2693 if (opr2->is_single_xmm()) {
2694 // xmm register - xmm register
2695 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2696 } else if (opr2->is_stack()) {
2697 // xmm register - stack
2698 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2699 } else if (opr2->is_constant()) {
2700 // xmm register - constant
2701 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2702 } else if (opr2->is_address()) {
2703 // xmm register - address
2704 if (op->info() != NULL) {
2705 add_debug_info_for_null_check_here(op->info());
2706 }
2707 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2708 } else {
2709 ShouldNotReachHere();
2710 }
2711
2712 } else if (opr1->is_double_xmm()) {
2713 XMMRegister reg1 = opr1->as_xmm_double_reg();
2714 if (opr2->is_double_xmm()) {
2715 // xmm register - xmm register
2716 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2717 } else if (opr2->is_stack()) {
2718 // xmm register - stack
2719 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2720 } else if (opr2->is_constant()) {
2721 // xmm register - constant
2722 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2723 } else if (opr2->is_address()) {
2724 // xmm register - address
2725 if (op->info() != NULL) {
2726 add_debug_info_for_null_check_here(op->info());
2727 }
2728 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2729 } else {
2730 ShouldNotReachHere();
2731 }
2732
2733 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2734 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2735 assert(opr2->is_fpu_register(), "both must be registers");
2736 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2737
2738 } else if (opr1->is_address() && opr2->is_constant()) {
2739 LIR_Const* c = opr2->as_constant_ptr();
2740 #ifdef _LP64
2741 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2742 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2743 __ movoop(rscratch1, c->as_jobject());
2744 }
2745 #endif // LP64
2746 if (op->info() != NULL) {
2747 add_debug_info_for_null_check_here(op->info());
2748 }
2749 // special case: address - constant
2750 LIR_Address* addr = opr1->as_address_ptr();
2751 if (c->type() == T_INT) {
2752 __ cmpl(as_Address(addr), c->as_jint());
2753 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2754 #ifdef _LP64
2755 // %%% Make this explode if addr isn't reachable until we figure out a
2756 // better strategy by giving noreg as the temp for as_Address
2757 __ cmpptr(rscratch1, as_Address(addr, noreg));
2758 #else
2759 __ cmpoop(as_Address(addr), c->as_jobject());
2760 #endif // _LP64
2761 } else {
2762 ShouldNotReachHere();
2763 }
2764
2765 } else {
2766 ShouldNotReachHere();
2767 }
2768 }
2769
2770 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2771 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2772 if (left->is_single_xmm()) {
2773 assert(right->is_single_xmm(), "must match");
2774 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2775 } else if (left->is_double_xmm()) {
2776 assert(right->is_double_xmm(), "must match");
2777 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2778
2779 } else {
2780 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2781 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2782
2783 assert(left->fpu() == 0, "left must be on TOS");
2784 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2785 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2786 }
2787 } else {
2788 assert(code == lir_cmp_l2i, "check");
2789 #ifdef _LP64
2790 Label done;
2791 Register dest = dst->as_register();
2792 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2793 __ movl(dest, -1);
2794 __ jccb(Assembler::less, done);
2795 __ set_byte_if_not_zero(dest);
2796 __ movzbl(dest, dest);
2797 __ bind(done);
2798 #else
2799 __ lcmp2int(left->as_register_hi(),
2800 left->as_register_lo(),
2801 right->as_register_hi(),
2802 right->as_register_lo());
2803 move_regs(left->as_register_hi(), dst->as_register());
2804 #endif // _LP64
2805 }
2806 }
2807
2808
2809 void LIR_Assembler::align_call(LIR_Code code) {
2810 if (os::is_MP()) {
2811 // make sure that the displacement word of the call ends up word aligned
2812 int offset = __ offset();
2813 switch (code) {
2814 case lir_static_call:
2815 case lir_optvirtual_call:
2816 case lir_dynamic_call:
2817 offset += NativeCall::displacement_offset;
2818 break;
2819 case lir_icvirtual_call:
2820 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2821 break;
2822 case lir_virtual_call: // currently, sparc-specific for niagara
2823 default: ShouldNotReachHere();
2824 }
2825 while (offset++ % BytesPerWord != 0) {
2826 __ nop();
2827 }
2828 }
2829 }
2830
2831
2832 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2833 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2834 "must be aligned");
2835 __ call(AddressLiteral(op->addr(), rtype));
2836 add_call_info(code_offset(), op->info());
2837 }
2838
2839
2840 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2841 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2842 __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2843 assert(!os::is_MP() ||
2844 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2845 "must be aligned");
2846 __ call(AddressLiteral(op->addr(), rh));
2847 add_call_info(code_offset(), op->info());
2848 }
2849
2850
2851 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2852 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2853 ShouldNotReachHere();
2854 }
2855
2856
2857 void LIR_Assembler::emit_static_call_stub() {
2858 address call_pc = __ pc();
2859 address stub = __ start_a_stub(call_stub_size);
2860 if (stub == NULL) {
2861 bailout("static call stub overflow");
2862 return;
2863 }
2864
2865 int start = __ offset();
2866 if (os::is_MP()) {
2867 // make sure that the displacement word of the call ends up word aligned
2868 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2869 while (offset++ % BytesPerWord != 0) {
2870 __ nop();
2871 }
2872 }
2873 __ relocate(static_stub_Relocation::spec(call_pc));
2874 __ movoop(rbx, (jobject)NULL);
2875 // must be set to -1 at code generation time
2876 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2877 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2878 __ jump(RuntimeAddress(__ pc()));
2879
2880 assert(__ offset() - start <= call_stub_size, "stub too big");
2881 __ end_a_stub();
2882 }
2883
2884
2885 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2886 assert(exceptionOop->as_register() == rax, "must match");
2887 assert(exceptionPC->as_register() == rdx, "must match");
2888
2889 // exception object is not added to oop map by LinearScan
2890 // (LinearScan assumes that no oops are in fixed registers)
2891 info->add_register_oop(exceptionOop);
2892 Runtime1::StubID unwind_id;
2893
2894 // get current pc information
2895 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2896 int pc_for_athrow_offset = __ offset();
2897 InternalAddress pc_for_athrow(__ pc());
2898 __ lea(exceptionPC->as_register(), pc_for_athrow);
2899 add_call_info(pc_for_athrow_offset, info); // for exception handler
2900
2901 __ verify_not_null_oop(rax);
2902 // search an exception handler (rax: exception oop, rdx: throwing pc)
2903 if (compilation()->has_fpu_code()) {
2904 unwind_id = Runtime1::handle_exception_id;
2905 } else {
2906 unwind_id = Runtime1::handle_exception_nofpu_id;
2907 }
2908 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2909
2910 // enough room for two byte trap
2911 __ nop();
2912 }
2913
2914
2915 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2916 assert(exceptionOop->as_register() == rax, "must match");
2917
2918 __ jmp(_unwind_handler_entry);
2919 }
2920
2921
2922 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2923
2924 // optimized version for linear scan:
2925 // * count must be already in ECX (guaranteed by LinearScan)
2926 // * left and dest must be equal
2927 // * tmp must be unused
2928 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2929 assert(left == dest, "left and dest must be equal");
2930 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2931
2932 if (left->is_single_cpu()) {
2933 Register value = left->as_register();
2934 assert(value != SHIFT_count, "left cannot be ECX");
2935
2936 switch (code) {
2937 case lir_shl: __ shll(value); break;
2938 case lir_shr: __ sarl(value); break;
2939 case lir_ushr: __ shrl(value); break;
2940 default: ShouldNotReachHere();
2941 }
2942 } else if (left->is_double_cpu()) {
2943 Register lo = left->as_register_lo();
2944 Register hi = left->as_register_hi();
2945 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2946 #ifdef _LP64
2947 switch (code) {
2948 case lir_shl: __ shlptr(lo); break;
2949 case lir_shr: __ sarptr(lo); break;
2950 case lir_ushr: __ shrptr(lo); break;
2951 default: ShouldNotReachHere();
2952 }
2953 #else
2954
2955 switch (code) {
2956 case lir_shl: __ lshl(hi, lo); break;
2957 case lir_shr: __ lshr(hi, lo, true); break;
2958 case lir_ushr: __ lshr(hi, lo, false); break;
2959 default: ShouldNotReachHere();
2960 }
2961 #endif // LP64
2962 } else {
2963 ShouldNotReachHere();
2964 }
2965 }
2966
2967
2968 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2969 if (dest->is_single_cpu()) {
2970 // first move left into dest so that left is not destroyed by the shift
2971 Register value = dest->as_register();
2972 count = count & 0x1F; // Java spec
2973
2974 move_regs(left->as_register(), value);
2975 switch (code) {
2976 case lir_shl: __ shll(value, count); break;
2977 case lir_shr: __ sarl(value, count); break;
2978 case lir_ushr: __ shrl(value, count); break;
2979 default: ShouldNotReachHere();
2980 }
2981 } else if (dest->is_double_cpu()) {
2982 #ifndef _LP64
2983 Unimplemented();
2984 #else
2985 // first move left into dest so that left is not destroyed by the shift
2986 Register value = dest->as_register_lo();
2987 count = count & 0x1F; // Java spec
2988
2989 move_regs(left->as_register_lo(), value);
2990 switch (code) {
2991 case lir_shl: __ shlptr(value, count); break;
2992 case lir_shr: __ sarptr(value, count); break;
2993 case lir_ushr: __ shrptr(value, count); break;
2994 default: ShouldNotReachHere();
2995 }
2996 #endif // _LP64
2997 } else {
2998 ShouldNotReachHere();
2999 }
3000 }
3001
3002
3003 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3004 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3005 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3006 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3007 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3008 }
3009
3010
3011 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3012 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3013 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3014 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3015 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3016 }
3017
3018
3019 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3020 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3021 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3022 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3023 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3024 }
3025
3026
3027 // This code replaces a call to arraycopy; no exception may
3028 // be thrown in this code, they must be thrown in the System.arraycopy
3029 // activation frame; we could save some checks if this would not be the case
3030 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3031 ciArrayKlass* default_type = op->expected_type();
3032 Register src = op->src()->as_register();
3033 Register dst = op->dst()->as_register();
3034 Register src_pos = op->src_pos()->as_register();
3035 Register dst_pos = op->dst_pos()->as_register();
3036 Register length = op->length()->as_register();
3037 Register tmp = op->tmp()->as_register();
3038
3039 CodeStub* stub = op->stub();
3040 int flags = op->flags();
3041 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3042 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3043
3044 // if we don't know anything or it's an object array, just go through the generic arraycopy
3045 if (default_type == NULL) {
3046 Label done;
3047 // save outgoing arguments on stack in case call to System.arraycopy is needed
3048 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3049 // for interpreter calling conventions. Now we have to do it in new style conventions.
3050 // For the moment until C1 gets the new register allocator I just force all the
3051 // args to the right place (except the register args) and then on the back side
3052 // reload the register args properly if we go slow path. Yuck
3053
3054 // These are proper for the calling convention
3055
3056 store_parameter(length, 2);
3057 store_parameter(dst_pos, 1);
3058 store_parameter(dst, 0);
3059
3060 // these are just temporary placements until we need to reload
3061 store_parameter(src_pos, 3);
3062 store_parameter(src, 4);
3063 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3064
3065 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3066
3067 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3068 #ifdef _LP64
3069 // The arguments are in java calling convention so we can trivially shift them to C
3070 // convention
3071 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3072 __ mov(c_rarg0, j_rarg0);
3073 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3074 __ mov(c_rarg1, j_rarg1);
3075 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3076 __ mov(c_rarg2, j_rarg2);
3077 assert_different_registers(c_rarg3, j_rarg4);
3078 __ mov(c_rarg3, j_rarg3);
3079 #ifdef _WIN64
3080 // Allocate abi space for args but be sure to keep stack aligned
3081 __ subptr(rsp, 6*wordSize);
3082 store_parameter(j_rarg4, 4);
3083 __ call(RuntimeAddress(entry));
3084 __ addptr(rsp, 6*wordSize);
3085 #else
3086 __ mov(c_rarg4, j_rarg4);
3087 __ call(RuntimeAddress(entry));
3088 #endif // _WIN64
3089 #else
3090 __ push(length);
3091 __ push(dst_pos);
3092 __ push(dst);
3093 __ push(src_pos);
3094 __ push(src);
3095 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3096
3097 #endif // _LP64
3098
3099 __ cmpl(rax, 0);
3100 __ jcc(Assembler::equal, *stub->continuation());
3101
3102 // Reload values from the stack so they are where the stub
3103 // expects them.
3104 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3105 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3106 __ movptr (length, Address(rsp, 2*BytesPerWord));
3107 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3108 __ movptr (src, Address(rsp, 4*BytesPerWord));
3109 __ jmp(*stub->entry());
3110
3111 __ bind(*stub->continuation());
3112 return;
3113 }
3114
3115 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3116
3117 int elem_size = type2aelembytes(basic_type);
3118 int shift_amount;
3119 Address::ScaleFactor scale;
3120
3121 switch (elem_size) {
3122 case 1 :
3123 shift_amount = 0;
3124 scale = Address::times_1;
3125 break;
3126 case 2 :
3127 shift_amount = 1;
3128 scale = Address::times_2;
3129 break;
3130 case 4 :
3131 shift_amount = 2;
3132 scale = Address::times_4;
3133 break;
3134 case 8 :
3135 shift_amount = 3;
3136 scale = Address::times_8;
3137 break;
3138 default:
3139 ShouldNotReachHere();
3140 }
3141
3142 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3143 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3144 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3145 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3146
3147 // length and pos's are all sign extended at this point on 64bit
3148
3149 // test for NULL
3150 if (flags & LIR_OpArrayCopy::src_null_check) {
3151 __ testptr(src, src);
3152 __ jcc(Assembler::zero, *stub->entry());
3153 }
3154 if (flags & LIR_OpArrayCopy::dst_null_check) {
3155 __ testptr(dst, dst);
3156 __ jcc(Assembler::zero, *stub->entry());
3157 }
3158
3159 // check if negative
3160 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3161 __ testl(src_pos, src_pos);
3162 __ jcc(Assembler::less, *stub->entry());
3163 }
3164 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3165 __ testl(dst_pos, dst_pos);
3166 __ jcc(Assembler::less, *stub->entry());
3167 }
3168 if (flags & LIR_OpArrayCopy::length_positive_check) {
3169 __ testl(length, length);
3170 __ jcc(Assembler::less, *stub->entry());
3171 }
3172
3173 if (flags & LIR_OpArrayCopy::src_range_check) {
3174 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3175 __ cmpl(tmp, src_length_addr);
3176 __ jcc(Assembler::above, *stub->entry());
3177 }
3178 if (flags & LIR_OpArrayCopy::dst_range_check) {
3179 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3180 __ cmpl(tmp, dst_length_addr);
3181 __ jcc(Assembler::above, *stub->entry());
3182 }
3183
3184 if (flags & LIR_OpArrayCopy::type_check) {
3185 __ movptr(tmp, src_klass_addr);
3186 __ cmpptr(tmp, dst_klass_addr);
3187 __ jcc(Assembler::notEqual, *stub->entry());
3188 }
3189
3190 #ifdef ASSERT
3191 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3192 // Sanity check the known type with the incoming class. For the
3193 // primitive case the types must match exactly with src.klass and
3194 // dst.klass each exactly matching the default type. For the
3195 // object array case, if no type check is needed then either the
3196 // dst type is exactly the expected type and the src type is a
3197 // subtype which we can't check or src is the same array as dst
3198 // but not necessarily exactly of type default_type.
3199 Label known_ok, halt;
3200 __ movoop(tmp, default_type->constant_encoding());
3201 if (basic_type != T_OBJECT) {
3202 __ cmpptr(tmp, dst_klass_addr);
3203 __ jcc(Assembler::notEqual, halt);
3204 __ cmpptr(tmp, src_klass_addr);
3205 __ jcc(Assembler::equal, known_ok);
3206 } else {
3207 __ cmpptr(tmp, dst_klass_addr);
3208 __ jcc(Assembler::equal, known_ok);
3209 __ cmpptr(src, dst);
3210 __ jcc(Assembler::equal, known_ok);
3211 }
3212 __ bind(halt);
3213 __ stop("incorrect type information in arraycopy");
3214 __ bind(known_ok);
3215 }
3216 #endif
3217
3218 if (shift_amount > 0 && basic_type != T_OBJECT) {
3219 __ shlptr(length, shift_amount);
3220 }
3221
3222 #ifdef _LP64
3223 assert_different_registers(c_rarg0, dst, dst_pos, length);
3224 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3225 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3226 assert_different_registers(c_rarg1, length);
3227 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3228 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3229 __ mov(c_rarg2, length);
3230
3231 #else
3232 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3233 store_parameter(tmp, 0);
3234 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3235 store_parameter(tmp, 1);
3236 store_parameter(length, 2);
3237 #endif // _LP64
3238 if (basic_type == T_OBJECT) {
3239 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3240 } else {
3241 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3242 }
3243
3244 __ bind(*stub->continuation());
3245 }
3246
3247
3248 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3249 Register obj = op->obj_opr()->as_register(); // may not be an oop
3250 Register hdr = op->hdr_opr()->as_register();
3251 Register lock = op->lock_opr()->as_register();
3252 if (!UseFastLocking) {
3253 __ jmp(*op->stub()->entry());
3254 } else if (op->code() == lir_lock) {
3255 Register scratch = noreg;
3256 if (UseBiasedLocking) {
3257 scratch = op->scratch_opr()->as_register();
3258 }
3259 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3260 // add debug info for NullPointerException only if one is possible
3261 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3262 if (op->info() != NULL) {
3263 add_debug_info_for_null_check(null_check_offset, op->info());
3264 }
3265 // done
3266 } else if (op->code() == lir_unlock) {
3267 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3268 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3269 } else {
3270 Unimplemented();
3271 }
3272 __ bind(*op->stub()->continuation());
3273 }
3274
3275
3276 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3277 ciMethod* method = op->profiled_method();
3278 int bci = op->profiled_bci();
3279
3280 // Update counter for all call types
3281 ciMethodData* md = method->method_data();
3282 if (md == NULL) {
3283 bailout("out of memory building methodDataOop");
3284 return;
3285 }
3286 ciProfileData* data = md->bci_to_data(bci);
3287 assert(data->is_CounterData(), "need CounterData for calls");
3288 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3289 Register mdo = op->mdo()->as_register();
3290 __ movoop(mdo, md->constant_encoding());
3291 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3292 Bytecodes::Code bc = method->java_code_at_bci(bci);
3293 // Perform additional virtual call profiling for invokevirtual and
3294 // invokeinterface bytecodes
3295 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3296 C1ProfileVirtualCalls) {
3297 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3298 Register recv = op->recv()->as_register();
3299 assert_different_registers(mdo, recv);
3300 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3301 ciKlass* known_klass = op->known_holder();
3302 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3303 // We know the type that will be seen at this call site; we can
3304 // statically update the methodDataOop rather than needing to do
3305 // dynamic tests on the receiver type
3306
3307 // NOTE: we should probably put a lock around this search to
3308 // avoid collisions by concurrent compilations
3309 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3310 uint i;
3311 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3312 ciKlass* receiver = vc_data->receiver(i);
3313 if (known_klass->equals(receiver)) {
3314 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3315 __ addptr(data_addr, DataLayout::counter_increment);
3316 return;
3317 }
3318 }
3319
3320 // Receiver type not found in profile data; select an empty slot
3321
3322 // Note that this is less efficient than it should be because it
3323 // always does a write to the receiver part of the
3324 // VirtualCallData rather than just the first time
3325 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3326 ciKlass* receiver = vc_data->receiver(i);
3327 if (receiver == NULL) {
3328 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3329 __ movoop(recv_addr, known_klass->constant_encoding());
3330 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3331 __ addptr(data_addr, DataLayout::counter_increment);
3332 return;
3333 }
3334 }
3335 } else {
3336 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3337 Label update_done;
3338 type_profile_helper(mdo, md, data, recv, &update_done);
3339 // Receiver did not match any saved receiver and there is no empty row for it.
3340 // Increment total counter to indicate polymorphic case.
3341 __ addptr(counter_addr, DataLayout::counter_increment);
3342
3343 __ bind(update_done);
3344 }
3345 } else {
3346 // Static call
3347 __ addptr(counter_addr, DataLayout::counter_increment);
3348 }
3349 }
3350
3351 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3352 Unimplemented();
3353 }
3354
3355
3356 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3357 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3358 }
3359
3360
3361 void LIR_Assembler::align_backward_branch_target() {
3362 __ align(BytesPerWord);
3363 }
3364
3365
3366 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3367 if (left->is_single_cpu()) {
3368 __ negl(left->as_register());
3369 move_regs(left->as_register(), dest->as_register());
3370
3371 } else if (left->is_double_cpu()) {
3372 Register lo = left->as_register_lo();
3373 #ifdef _LP64
3374 Register dst = dest->as_register_lo();
3375 __ movptr(dst, lo);
3376 __ negptr(dst);
3377 #else
3378 Register hi = left->as_register_hi();
3379 __ lneg(hi, lo);
3380 if (dest->as_register_lo() == hi) {
3381 assert(dest->as_register_hi() != lo, "destroying register");
3382 move_regs(hi, dest->as_register_hi());
3383 move_regs(lo, dest->as_register_lo());
3384 } else {
3385 move_regs(lo, dest->as_register_lo());
3386 move_regs(hi, dest->as_register_hi());
3387 }
3388 #endif // _LP64
3389
3390 } else if (dest->is_single_xmm()) {
3391 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3392 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3393 }
3394 __ xorps(dest->as_xmm_float_reg(),
3395 ExternalAddress((address)float_signflip_pool));
3396
3397 } else if (dest->is_double_xmm()) {
3398 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3399 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3400 }
3401 __ xorpd(dest->as_xmm_double_reg(),
3402 ExternalAddress((address)double_signflip_pool));
3403
3404 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3405 assert(left->fpu() == 0, "arg must be on TOS");
3406 assert(dest->fpu() == 0, "dest must be TOS");
3407 __ fchs();
3408
3409 } else {
3410 ShouldNotReachHere();
3411 }
3412 }
3413
3414
3415 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3416 assert(addr->is_address() && dest->is_register(), "check");
3417 Register reg;
3418 reg = dest->as_pointer_register();
3419 __ lea(reg, as_Address(addr->as_address_ptr()));
3420 }
3421
3422
3423
3424 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3425 assert(!tmp->is_valid(), "don't need temporary");
3426 __ call(RuntimeAddress(dest));
3427 if (info != NULL) {
3428 add_call_info_here(info);
3429 }
3430 }
3431
3432
3433 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3434 assert(type == T_LONG, "only for volatile long fields");
3435
3436 if (info != NULL) {
3437 add_debug_info_for_null_check_here(info);
3438 }
3439
3440 if (src->is_double_xmm()) {
3441 if (dest->is_double_cpu()) {
3442 #ifdef _LP64
3443 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3444 #else
3445 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3446 __ psrlq(src->as_xmm_double_reg(), 32);
3447 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3448 #endif // _LP64
3449 } else if (dest->is_double_stack()) {
3450 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3451 } else if (dest->is_address()) {
3452 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3453 } else {
3454 ShouldNotReachHere();
3455 }
3456
3457 } else if (dest->is_double_xmm()) {
3458 if (src->is_double_stack()) {
3459 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3460 } else if (src->is_address()) {
3461 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3462 } else {
3463 ShouldNotReachHere();
3464 }
3465
3466 } else if (src->is_double_fpu()) {
3467 assert(src->fpu_regnrLo() == 0, "must be TOS");
3468 if (dest->is_double_stack()) {
3469 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3470 } else if (dest->is_address()) {
3471 __ fistp_d(as_Address(dest->as_address_ptr()));
3472 } else {
3473 ShouldNotReachHere();
3474 }
3475
3476 } else if (dest->is_double_fpu()) {
3477 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3478 if (src->is_double_stack()) {
3479 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3480 } else if (src->is_address()) {
3481 __ fild_d(as_Address(src->as_address_ptr()));
3482 } else {
3483 ShouldNotReachHere();
3484 }
3485 } else {
3486 ShouldNotReachHere();
3487 }
3488 }
3489
3490
3491 void LIR_Assembler::membar() {
3492 // QQQ sparc TSO uses this,
3493 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3494 }
3495
3496 void LIR_Assembler::membar_acquire() {
3497 // No x86 machines currently require load fences
3498 // __ load_fence();
3499 }
3500
3501 void LIR_Assembler::membar_release() {
3502 // No x86 machines currently require store fences
3503 // __ store_fence();
3504 }
3505
3506 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3507 assert(result_reg->is_register(), "check");
3508 #ifdef _LP64
3509 // __ get_thread(result_reg->as_register_lo());
3510 __ mov(result_reg->as_register(), r15_thread);
3511 #else
3512 __ get_thread(result_reg->as_register());
3513 #endif // _LP64
3514 }
3515
3516
3517 void LIR_Assembler::peephole(LIR_List*) {
3518 // do nothing for now
3519 }
3520
3521
3522 #undef __