1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc_interface/collectedHeap.hpp"
34 #include "memory/barrierSet.hpp"
35 #include "memory/cardTableModRefBS.hpp"
36 #include "nativeInst_x86.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40
41 // These masks are used to provide 128-bit aligned bitmasks to the XMM
42 // instructions, to allow sign-masking or sign-bit flipping. They allow
43 // fast versions of NegF/NegD and AbsF/AbsD.
44
45 // Note: 'double' and 'long long' have 32-bits alignment on x86.
46 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
47 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
48 // of 128-bits operands for SSE instructions.
49 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
50 // Store the value to a 128-bits operand.
51 operand[0] = lo;
52 operand[1] = hi;
53 return operand;
54 }
55
56 // Buffer for 128-bits masks used by SSE instructions.
57 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
58
59 // Static initialization during VM startup.
60 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
61 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
62 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
63 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
64
65
66
67 NEEDS_CLEANUP // remove this definitions ?
68 const Register IC_Klass = rax; // where the IC klass is cached
69 const Register SYNC_header = rax; // synchronization header
70 const Register SHIFT_count = rcx; // where count for shift operations must be
71
72 #define __ _masm->
73
74
75 static void select_different_registers(Register preserve,
76 Register extra,
77 Register &tmp1,
78 Register &tmp2) {
79 if (tmp1 == preserve) {
80 assert_different_registers(tmp1, tmp2, extra);
81 tmp1 = extra;
82 } else if (tmp2 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp2 = extra;
85 }
86 assert_different_registers(preserve, tmp1, tmp2);
87 }
88
89
90
91 static void select_different_registers(Register preserve,
92 Register extra,
93 Register &tmp1,
94 Register &tmp2,
95 Register &tmp3) {
96 if (tmp1 == preserve) {
97 assert_different_registers(tmp1, tmp2, tmp3, extra);
98 tmp1 = extra;
99 } else if (tmp2 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp2 = extra;
102 } else if (tmp3 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp3 = extra;
105 }
106 assert_different_registers(preserve, tmp1, tmp2, tmp3);
107 }
108
109
110
111 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
112 if (opr->is_constant()) {
113 LIR_Const* constant = opr->as_constant_ptr();
114 switch (constant->type()) {
115 case T_INT: {
116 return true;
117 }
118
119 default:
120 return false;
121 }
122 }
123 return false;
124 }
125
126
127 LIR_Opr LIR_Assembler::receiverOpr() {
128 return FrameMap::receiver_opr;
129 }
130
131 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
132 return receiverOpr();
133 }
134
135 LIR_Opr LIR_Assembler::osrBufferPointer() {
136 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
137 }
138
139 //--------------fpu register translations-----------------------
140
141
142 address LIR_Assembler::float_constant(float f) {
143 address const_addr = __ float_constant(f);
144 if (const_addr == NULL) {
145 bailout("const section overflow");
146 return __ code()->consts()->start();
147 } else {
148 return const_addr;
149 }
150 }
151
152
153 address LIR_Assembler::double_constant(double d) {
154 address const_addr = __ double_constant(d);
155 if (const_addr == NULL) {
156 bailout("const section overflow");
157 return __ code()->consts()->start();
158 } else {
159 return const_addr;
160 }
161 }
162
163
164 void LIR_Assembler::set_24bit_FPU() {
165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
166 }
167
168 void LIR_Assembler::reset_FPU() {
169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
170 }
171
172 void LIR_Assembler::fpop() {
173 __ fpop();
174 }
175
176 void LIR_Assembler::fxch(int i) {
177 __ fxch(i);
178 }
179
180 void LIR_Assembler::fld(int i) {
181 __ fld_s(i);
182 }
183
184 void LIR_Assembler::ffree(int i) {
185 __ ffree(i);
186 }
187
188 void LIR_Assembler::breakpoint() {
189 __ int3();
190 }
191
192 void LIR_Assembler::push(LIR_Opr opr) {
193 if (opr->is_single_cpu()) {
194 __ push_reg(opr->as_register());
195 } else if (opr->is_double_cpu()) {
196 NOT_LP64(__ push_reg(opr->as_register_hi()));
197 __ push_reg(opr->as_register_lo());
198 } else if (opr->is_stack()) {
199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
200 } else if (opr->is_constant()) {
201 LIR_Const* const_opr = opr->as_constant_ptr();
202 if (const_opr->type() == T_OBJECT) {
203 __ push_oop(const_opr->as_jobject());
204 } else if (const_opr->type() == T_INT) {
205 __ push_jint(const_opr->as_jint());
206 } else {
207 ShouldNotReachHere();
208 }
209
210 } else {
211 ShouldNotReachHere();
212 }
213 }
214
215 void LIR_Assembler::pop(LIR_Opr opr) {
216 if (opr->is_single_cpu()) {
217 __ pop_reg(opr->as_register());
218 } else {
219 ShouldNotReachHere();
220 }
221 }
222
223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
224 return addr->base()->is_illegal() && addr->index()->is_illegal();
225 }
226
227 //-------------------------------------------
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr) {
230 return as_Address(addr, rscratch1);
231 }
232
233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
234 if (addr->base()->is_illegal()) {
235 assert(addr->index()->is_illegal(), "must be illegal too");
236 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
237 if (! __ reachable(laddr)) {
238 __ movptr(tmp, laddr.addr());
239 Address res(tmp, 0);
240 return res;
241 } else {
242 return __ as_Address(laddr);
243 }
244 }
245
246 Register base = addr->base()->as_pointer_register();
247
248 if (addr->index()->is_illegal()) {
249 return Address( base, addr->disp());
250 } else if (addr->index()->is_cpu_register()) {
251 Register index = addr->index()->as_pointer_register();
252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
253 } else if (addr->index()->is_constant()) {
254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
255 assert(Assembler::is_simm32(addr_offset), "must be");
256
257 return Address(base, addr_offset);
258 } else {
259 Unimplemented();
260 return Address();
261 }
262 }
263
264
265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
266 Address base = as_Address(addr);
267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
268 }
269
270
271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
272 return as_Address(addr);
273 }
274
275
276 void LIR_Assembler::osr_entry() {
277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
278 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
279 ValueStack* entry_state = osr_entry->state();
280 int number_of_locks = entry_state->locks_size();
281
282 // we jump here if osr happens with the interpreter
283 // state set up to continue at the beginning of the
284 // loop that triggered osr - in particular, we have
285 // the following registers setup:
286 //
287 // rcx: osr buffer
288 //
289
290 // build frame
291 ciMethod* m = compilation()->method();
292 __ build_frame(initial_frame_size_in_bytes());
293
294 // OSR buffer is
295 //
296 // locals[nlocals-1..0]
297 // monitors[0..number_of_locks]
298 //
299 // locals is a direct copy of the interpreter frame so in the osr buffer
300 // so first slot in the local array is the last local from the interpreter
301 // and last slot is local[0] (receiver) from the interpreter
302 //
303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
305 // in the interpreter frame (the method lock if a sync method)
306
307 // Initialize monitors in the compiled activation.
308 // rcx: pointer to osr buffer
309 //
310 // All other registers are dead at this point and the locals will be
311 // copied into place by code emitted in the IR.
312
313 Register OSR_buf = osrBufferPointer()->as_pointer_register();
314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
315 int monitor_offset = BytesPerWord * method()->max_locals() +
316 (2 * BytesPerWord) * (number_of_locks - 1);
317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
318 // the OSR buffer using 2 word entries: first the lock and then
319 // the oop.
320 for (int i = 0; i < number_of_locks; i++) {
321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
322 #ifdef ASSERT
323 // verify the interpreter's monitor has a non-null object
324 {
325 Label L;
326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
327 __ jcc(Assembler::notZero, L);
328 __ stop("locked object is NULL");
329 __ bind(L);
330 }
331 #endif
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
335 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
336 }
337 }
338 }
339
340
341 // inline cache check; done before the frame is built.
342 int LIR_Assembler::check_icache() {
343 Register receiver = FrameMap::receiver_opr->as_register();
344 Register ic_klass = IC_Klass;
345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
346
347 if (!VerifyOops) {
348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
349 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
350 __ nop();
351 }
352 }
353 int offset = __ offset();
354 __ inline_cache_check(receiver, IC_Klass);
355 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
356 if (VerifyOops) {
357 // force alignment after the cache check.
358 // It's been verified to be aligned if !VerifyOops
359 __ align(CodeEntryAlignment);
360 }
361 return offset;
362 }
363
364
365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
366 jobject o = NULL;
367 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
368 __ movoop(reg, o);
369 patching_epilog(patch, lir_patch_normal, reg, info);
370 }
371
372
373 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
374 if (exception->is_valid()) {
375 // preserve exception
376 // note: the monitor_exit runtime call is a leaf routine
377 // and cannot block => no GC can happen
378 // The slow case (MonitorAccessStub) uses the first two stack slots
379 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
380 __ movptr (Address(rsp, 2*wordSize), exception);
381 }
382
383 Register obj_reg = obj_opr->as_register();
384 Register lock_reg = lock_opr->as_register();
385
386 // setup registers (lock_reg must be rax, for lock_object)
387 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
388 Register hdr = lock_reg;
389 assert(new_hdr == SYNC_header, "wrong register");
390 lock_reg = new_hdr;
391 // compute pointer to BasicLock
392 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
393 __ lea(lock_reg, lock_addr);
394 // unlock object
395 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
396 // _slow_case_stubs->append(slow_case);
397 // temporary fix: must be created after exceptionhandler, therefore as call stub
398 _slow_case_stubs->append(slow_case);
399 if (UseFastLocking) {
400 // try inlined fast unlocking first, revert to slow locking if it fails
401 // note: lock_reg points to the displaced header since the displaced header offset is 0!
402 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
403 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
404 } else {
405 // always do slow unlocking
406 // note: the slow unlocking code could be inlined here, however if we use
407 // slow unlocking, speed doesn't matter anyway and this solution is
408 // simpler and requires less duplicated code - additionally, the
409 // slow unlocking code is the same in either case which simplifies
410 // debugging
411 __ jmp(*slow_case->entry());
412 }
413 // done
414 __ bind(*slow_case->continuation());
415
416 if (exception->is_valid()) {
417 // restore exception
418 __ movptr (exception, Address(rsp, 2 * wordSize));
419 }
420 }
421
422 // This specifies the rsp decrement needed to build the frame
423 int LIR_Assembler::initial_frame_size_in_bytes() {
424 // if rounding, must let FrameMap know!
425
426 // The frame_map records size in slots (32bit word)
427
428 // subtract two words to account for return address and link
429 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
430 }
431
432
433 int LIR_Assembler::emit_exception_handler() {
434 // if the last instruction is a call (typically to do a throw which
435 // is coming at the end after block reordering) the return address
436 // must still point into the code area in order to avoid assertion
437 // failures when searching for the corresponding bci => add a nop
438 // (was bug 5/14/1999 - gri)
439 __ nop();
440
441 // generate code for exception handler
442 address handler_base = __ start_a_stub(exception_handler_size);
443 if (handler_base == NULL) {
444 // not enough space left for the handler
445 bailout("exception handler overflow");
446 return -1;
447 }
448
449 int offset = code_offset();
450
451 // the exception oop and pc are in rax, and rdx
452 // no other registers need to be preserved, so invalidate them
453 __ invalidate_registers(false, true, true, false, true, true);
454
455 // check that there is really an exception
456 __ verify_not_null_oop(rax);
457
458 // search an exception handler (rax: exception oop, rdx: throwing pc)
459 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
460
461 __ stop("should not reach here");
462
463 assert(code_offset() - offset <= exception_handler_size, "overflow");
464 __ end_a_stub();
465
466 return offset;
467 }
468
469
470 // Emit the code to remove the frame from the stack in the exception
471 // unwind path.
472 int LIR_Assembler::emit_unwind_handler() {
473 #ifndef PRODUCT
474 if (CommentedAssembly) {
475 _masm->block_comment("Unwind handler");
476 }
477 #endif
478
479 int offset = code_offset();
480
481 // Fetch the exception from TLS and clear out exception related thread state
482 __ get_thread(rsi);
483 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
484 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
485 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
486
487 __ bind(_unwind_handler_entry);
488 __ verify_not_null_oop(rax);
489 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
490 __ mov(rsi, rax); // Preserve the exception
491 }
492
493 // Preform needed unlocking
494 MonitorExitStub* stub = NULL;
495 if (method()->is_synchronized()) {
496 monitor_address(0, FrameMap::rax_opr);
497 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
498 __ unlock_object(rdi, rbx, rax, *stub->entry());
499 __ bind(*stub->continuation());
500 }
501
502 if (compilation()->env()->dtrace_method_probes()) {
503 __ movoop(Address(rsp, 0), method()->constant_encoding());
504 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
505 }
506
507 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
508 __ mov(rax, rsi); // Restore the exception
509 }
510
511 // remove the activation and dispatch to the unwind handler
512 __ remove_frame(initial_frame_size_in_bytes());
513 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
514
515 // Emit the slow path assembly
516 if (stub != NULL) {
517 stub->emit_code(this);
518 }
519
520 return offset;
521 }
522
523
524 int LIR_Assembler::emit_deopt_handler() {
525 // if the last instruction is a call (typically to do a throw which
526 // is coming at the end after block reordering) the return address
527 // must still point into the code area in order to avoid assertion
528 // failures when searching for the corresponding bci => add a nop
529 // (was bug 5/14/1999 - gri)
530 __ nop();
531
532 // generate code for exception handler
533 address handler_base = __ start_a_stub(deopt_handler_size);
534 if (handler_base == NULL) {
535 // not enough space left for the handler
536 bailout("deopt handler overflow");
537 return -1;
538 }
539
540 int offset = code_offset();
541 InternalAddress here(__ pc());
542
543 __ pushptr(here.addr());
544 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
545
546 assert(code_offset() - offset <= deopt_handler_size, "overflow");
547 __ end_a_stub();
548
549 return offset;
550 }
551
552
553 // This is the fast version of java.lang.String.compare; it has not
554 // OSR-entry and therefore, we generate a slow version for OSR's
555 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
556 __ movptr (rbx, rcx); // receiver is in rcx
557 __ movptr (rax, arg1->as_register());
558
559 // Get addresses of first characters from both Strings
560 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
561 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
562 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
563
564
565 // rbx, may be NULL
566 add_debug_info_for_null_check_here(info);
567 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
568 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
569 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
570
571 // compute minimum length (in rax) and difference of lengths (on top of stack)
572 if (VM_Version::supports_cmov()) {
573 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
574 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
575 __ mov (rcx, rbx);
576 __ subptr (rbx, rax); // subtract lengths
577 __ push (rbx); // result
578 __ cmov (Assembler::lessEqual, rax, rcx);
579 } else {
580 Label L;
581 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
582 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
583 __ mov (rax, rbx);
584 __ subptr (rbx, rcx);
585 __ push (rbx);
586 __ jcc (Assembler::lessEqual, L);
587 __ mov (rax, rcx);
588 __ bind (L);
589 }
590 // is minimum length 0?
591 Label noLoop, haveResult;
592 __ testptr (rax, rax);
593 __ jcc (Assembler::zero, noLoop);
594
595 // compare first characters
596 __ load_unsigned_short(rcx, Address(rdi, 0));
597 __ load_unsigned_short(rbx, Address(rsi, 0));
598 __ subl(rcx, rbx);
599 __ jcc(Assembler::notZero, haveResult);
600 // starting loop
601 __ decrement(rax); // we already tested index: skip one
602 __ jcc(Assembler::zero, noLoop);
603
604 // set rsi.edi to the end of the arrays (arrays have same length)
605 // negate the index
606
607 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
608 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
609 __ negptr(rax);
610
611 // compare the strings in a loop
612
613 Label loop;
614 __ align(wordSize);
615 __ bind(loop);
616 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
617 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
618 __ subl(rcx, rbx);
619 __ jcc(Assembler::notZero, haveResult);
620 __ increment(rax);
621 __ jcc(Assembler::notZero, loop);
622
623 // strings are equal up to min length
624
625 __ bind(noLoop);
626 __ pop(rax);
627 return_op(LIR_OprFact::illegalOpr);
628
629 __ bind(haveResult);
630 // leave instruction is going to discard the TOS value
631 __ mov (rax, rcx); // result of call is in rax,
632 }
633
634
635 void LIR_Assembler::return_op(LIR_Opr result) {
636 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
637 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
638 assert(result->fpu() == 0, "result must already be on TOS");
639 }
640
641 // Pop the stack before the safepoint code
642 __ remove_frame(initial_frame_size_in_bytes());
643
644 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
645
646 // Note: we do not need to round double result; float result has the right precision
647 // the poll sets the condition code, but no data registers
648 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
649 relocInfo::poll_return_type);
650
651 // NOTE: the requires that the polling page be reachable else the reloc
652 // goes to the movq that loads the address and not the faulting instruction
653 // which breaks the signal handler code
654
655 __ test32(rax, polling_page);
656
657 __ ret(0);
658 }
659
660
661 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
662 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
663 relocInfo::poll_type);
664
665 if (info != NULL) {
666 add_debug_info_for_branch(info);
667 } else {
668 ShouldNotReachHere();
669 }
670
671 int offset = __ offset();
672
673 // NOTE: the requires that the polling page be reachable else the reloc
674 // goes to the movq that loads the address and not the faulting instruction
675 // which breaks the signal handler code
676
677 __ test32(rax, polling_page);
678 return offset;
679 }
680
681
682 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
683 if (from_reg != to_reg) __ mov(to_reg, from_reg);
684 }
685
686 void LIR_Assembler::swap_reg(Register a, Register b) {
687 __ xchgptr(a, b);
688 }
689
690
691 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
692 assert(src->is_constant(), "should not call otherwise");
693 assert(dest->is_register(), "should not call otherwise");
694 LIR_Const* c = src->as_constant_ptr();
695
696 switch (c->type()) {
697 case T_INT:
698 case T_ADDRESS: {
699 assert(patch_code == lir_patch_none, "no patching handled here");
700 __ movl(dest->as_register(), c->as_jint());
701 break;
702 }
703
704 case T_LONG: {
705 assert(patch_code == lir_patch_none, "no patching handled here");
706 #ifdef _LP64
707 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
708 #else
709 __ movptr(dest->as_register_lo(), c->as_jint_lo());
710 __ movptr(dest->as_register_hi(), c->as_jint_hi());
711 #endif // _LP64
712 break;
713 }
714
715 case T_OBJECT: {
716 if (patch_code != lir_patch_none) {
717 jobject2reg_with_patching(dest->as_register(), info);
718 } else {
719 __ movoop(dest->as_register(), c->as_jobject());
720 }
721 break;
722 }
723
724 case T_FLOAT: {
725 if (dest->is_single_xmm()) {
726 if (c->is_zero_float()) {
727 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
728 } else {
729 __ movflt(dest->as_xmm_float_reg(),
730 InternalAddress(float_constant(c->as_jfloat())));
731 }
732 } else {
733 assert(dest->is_single_fpu(), "must be");
734 assert(dest->fpu_regnr() == 0, "dest must be TOS");
735 if (c->is_zero_float()) {
736 __ fldz();
737 } else if (c->is_one_float()) {
738 __ fld1();
739 } else {
740 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
741 }
742 }
743 break;
744 }
745
746 case T_DOUBLE: {
747 if (dest->is_double_xmm()) {
748 if (c->is_zero_double()) {
749 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
750 } else {
751 __ movdbl(dest->as_xmm_double_reg(),
752 InternalAddress(double_constant(c->as_jdouble())));
753 }
754 } else {
755 assert(dest->is_double_fpu(), "must be");
756 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
757 if (c->is_zero_double()) {
758 __ fldz();
759 } else if (c->is_one_double()) {
760 __ fld1();
761 } else {
762 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
763 }
764 }
765 break;
766 }
767
768 default:
769 ShouldNotReachHere();
770 }
771 }
772
773 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
774 assert(src->is_constant(), "should not call otherwise");
775 assert(dest->is_stack(), "should not call otherwise");
776 LIR_Const* c = src->as_constant_ptr();
777
778 switch (c->type()) {
779 case T_INT: // fall through
780 case T_FLOAT:
781 case T_ADDRESS:
782 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
783 break;
784
785 case T_OBJECT:
786 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
787 break;
788
789 case T_LONG: // fall through
790 case T_DOUBLE:
791 #ifdef _LP64
792 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
793 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
794 #else
795 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
796 lo_word_offset_in_bytes), c->as_jint_lo_bits());
797 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
798 hi_word_offset_in_bytes), c->as_jint_hi_bits());
799 #endif // _LP64
800 break;
801
802 default:
803 ShouldNotReachHere();
804 }
805 }
806
807 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
808 assert(src->is_constant(), "should not call otherwise");
809 assert(dest->is_address(), "should not call otherwise");
810 LIR_Const* c = src->as_constant_ptr();
811 LIR_Address* addr = dest->as_address_ptr();
812
813 int null_check_here = code_offset();
814 switch (type) {
815 case T_INT: // fall through
816 case T_FLOAT:
817 case T_ADDRESS:
818 __ movl(as_Address(addr), c->as_jint_bits());
819 break;
820
821 case T_OBJECT: // fall through
822 case T_ARRAY:
823 if (c->as_jobject() == NULL) {
824 __ movptr(as_Address(addr), NULL_WORD);
825 } else {
826 if (is_literal_address(addr)) {
827 ShouldNotReachHere();
828 __ movoop(as_Address(addr, noreg), c->as_jobject());
829 } else {
830 #ifdef _LP64
831 __ movoop(rscratch1, c->as_jobject());
832 null_check_here = code_offset();
833 __ movptr(as_Address_lo(addr), rscratch1);
834 #else
835 __ movoop(as_Address(addr), c->as_jobject());
836 #endif
837 }
838 }
839 break;
840
841 case T_LONG: // fall through
842 case T_DOUBLE:
843 #ifdef _LP64
844 if (is_literal_address(addr)) {
845 ShouldNotReachHere();
846 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
847 } else {
848 __ movptr(r10, (intptr_t)c->as_jlong_bits());
849 null_check_here = code_offset();
850 __ movptr(as_Address_lo(addr), r10);
851 }
852 #else
853 // Always reachable in 32bit so this doesn't produce useless move literal
854 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
855 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
856 #endif // _LP64
857 break;
858
859 case T_BOOLEAN: // fall through
860 case T_BYTE:
861 __ movb(as_Address(addr), c->as_jint() & 0xFF);
862 break;
863
864 case T_CHAR: // fall through
865 case T_SHORT:
866 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
867 break;
868
869 default:
870 ShouldNotReachHere();
871 };
872
873 if (info != NULL) {
874 add_debug_info_for_null_check(null_check_here, info);
875 }
876 }
877
878
879 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
880 assert(src->is_register(), "should not call otherwise");
881 assert(dest->is_register(), "should not call otherwise");
882
883 // move between cpu-registers
884 if (dest->is_single_cpu()) {
885 #ifdef _LP64
886 if (src->type() == T_LONG) {
887 // Can do LONG -> OBJECT
888 move_regs(src->as_register_lo(), dest->as_register());
889 return;
890 }
891 #endif
892 assert(src->is_single_cpu(), "must match");
893 if (src->type() == T_OBJECT) {
894 __ verify_oop(src->as_register());
895 }
896 move_regs(src->as_register(), dest->as_register());
897
898 } else if (dest->is_double_cpu()) {
899 #ifdef _LP64
900 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
901 // Surprising to me but we can see move of a long to t_object
902 __ verify_oop(src->as_register());
903 move_regs(src->as_register(), dest->as_register_lo());
904 return;
905 }
906 #endif
907 assert(src->is_double_cpu(), "must match");
908 Register f_lo = src->as_register_lo();
909 Register f_hi = src->as_register_hi();
910 Register t_lo = dest->as_register_lo();
911 Register t_hi = dest->as_register_hi();
912 #ifdef _LP64
913 assert(f_hi == f_lo, "must be same");
914 assert(t_hi == t_lo, "must be same");
915 move_regs(f_lo, t_lo);
916 #else
917 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
918
919
920 if (f_lo == t_hi && f_hi == t_lo) {
921 swap_reg(f_lo, f_hi);
922 } else if (f_hi == t_lo) {
923 assert(f_lo != t_hi, "overwriting register");
924 move_regs(f_hi, t_hi);
925 move_regs(f_lo, t_lo);
926 } else {
927 assert(f_hi != t_lo, "overwriting register");
928 move_regs(f_lo, t_lo);
929 move_regs(f_hi, t_hi);
930 }
931 #endif // LP64
932
933 // special moves from fpu-register to xmm-register
934 // necessary for method results
935 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
936 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
937 __ fld_s(Address(rsp, 0));
938 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
939 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
940 __ fld_d(Address(rsp, 0));
941 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
942 __ fstp_s(Address(rsp, 0));
943 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
944 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
945 __ fstp_d(Address(rsp, 0));
946 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
947
948 // move between xmm-registers
949 } else if (dest->is_single_xmm()) {
950 assert(src->is_single_xmm(), "must match");
951 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
952 } else if (dest->is_double_xmm()) {
953 assert(src->is_double_xmm(), "must match");
954 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
955
956 // move between fpu-registers (no instruction necessary because of fpu-stack)
957 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
958 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
959 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
960 } else {
961 ShouldNotReachHere();
962 }
963 }
964
965 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
966 assert(src->is_register(), "should not call otherwise");
967 assert(dest->is_stack(), "should not call otherwise");
968
969 if (src->is_single_cpu()) {
970 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
971 if (type == T_OBJECT || type == T_ARRAY) {
972 __ verify_oop(src->as_register());
973 __ movptr (dst, src->as_register());
974 } else {
975 __ movl (dst, src->as_register());
976 }
977
978 } else if (src->is_double_cpu()) {
979 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
980 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
981 __ movptr (dstLO, src->as_register_lo());
982 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
983
984 } else if (src->is_single_xmm()) {
985 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
986 __ movflt(dst_addr, src->as_xmm_float_reg());
987
988 } else if (src->is_double_xmm()) {
989 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
990 __ movdbl(dst_addr, src->as_xmm_double_reg());
991
992 } else if (src->is_single_fpu()) {
993 assert(src->fpu_regnr() == 0, "argument must be on TOS");
994 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
995 if (pop_fpu_stack) __ fstp_s (dst_addr);
996 else __ fst_s (dst_addr);
997
998 } else if (src->is_double_fpu()) {
999 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1000 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1001 if (pop_fpu_stack) __ fstp_d (dst_addr);
1002 else __ fst_d (dst_addr);
1003
1004 } else {
1005 ShouldNotReachHere();
1006 }
1007 }
1008
1009
1010 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
1011 LIR_Address* to_addr = dest->as_address_ptr();
1012 PatchingStub* patch = NULL;
1013
1014 if (type == T_ARRAY || type == T_OBJECT) {
1015 __ verify_oop(src->as_register());
1016 }
1017 if (patch_code != lir_patch_none) {
1018 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1019 Address toa = as_Address(to_addr);
1020 assert(toa.disp() != 0, "must have");
1021 }
1022 if (info != NULL) {
1023 add_debug_info_for_null_check_here(info);
1024 }
1025
1026 switch (type) {
1027 case T_FLOAT: {
1028 if (src->is_single_xmm()) {
1029 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1030 } else {
1031 assert(src->is_single_fpu(), "must be");
1032 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1033 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1034 else __ fst_s (as_Address(to_addr));
1035 }
1036 break;
1037 }
1038
1039 case T_DOUBLE: {
1040 if (src->is_double_xmm()) {
1041 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1042 } else {
1043 assert(src->is_double_fpu(), "must be");
1044 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1045 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1046 else __ fst_d (as_Address(to_addr));
1047 }
1048 break;
1049 }
1050
1051 case T_ADDRESS: // fall through
1052 case T_ARRAY: // fall through
1053 case T_OBJECT: // fall through
1054 #ifdef _LP64
1055 __ movptr(as_Address(to_addr), src->as_register());
1056 break;
1057 #endif // _LP64
1058 case T_INT:
1059 __ movl(as_Address(to_addr), src->as_register());
1060 break;
1061
1062 case T_LONG: {
1063 Register from_lo = src->as_register_lo();
1064 Register from_hi = src->as_register_hi();
1065 #ifdef _LP64
1066 __ movptr(as_Address_lo(to_addr), from_lo);
1067 #else
1068 Register base = to_addr->base()->as_register();
1069 Register index = noreg;
1070 if (to_addr->index()->is_register()) {
1071 index = to_addr->index()->as_register();
1072 }
1073 if (base == from_lo || index == from_lo) {
1074 assert(base != from_hi, "can't be");
1075 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1076 __ movl(as_Address_hi(to_addr), from_hi);
1077 if (patch != NULL) {
1078 patching_epilog(patch, lir_patch_high, base, info);
1079 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1080 patch_code = lir_patch_low;
1081 }
1082 __ movl(as_Address_lo(to_addr), from_lo);
1083 } else {
1084 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1085 __ movl(as_Address_lo(to_addr), from_lo);
1086 if (patch != NULL) {
1087 patching_epilog(patch, lir_patch_low, base, info);
1088 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1089 patch_code = lir_patch_high;
1090 }
1091 __ movl(as_Address_hi(to_addr), from_hi);
1092 }
1093 #endif // _LP64
1094 break;
1095 }
1096
1097 case T_BYTE: // fall through
1098 case T_BOOLEAN: {
1099 Register src_reg = src->as_register();
1100 Address dst_addr = as_Address(to_addr);
1101 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1102 __ movb(dst_addr, src_reg);
1103 break;
1104 }
1105
1106 case T_CHAR: // fall through
1107 case T_SHORT:
1108 __ movw(as_Address(to_addr), src->as_register());
1109 break;
1110
1111 default:
1112 ShouldNotReachHere();
1113 }
1114
1115 if (patch_code != lir_patch_none) {
1116 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1117 }
1118 }
1119
1120
1121 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1122 assert(src->is_stack(), "should not call otherwise");
1123 assert(dest->is_register(), "should not call otherwise");
1124
1125 if (dest->is_single_cpu()) {
1126 if (type == T_ARRAY || type == T_OBJECT) {
1127 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1128 __ verify_oop(dest->as_register());
1129 } else {
1130 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1131 }
1132
1133 } else if (dest->is_double_cpu()) {
1134 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1135 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1136 __ movptr(dest->as_register_lo(), src_addr_LO);
1137 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1138
1139 } else if (dest->is_single_xmm()) {
1140 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1141 __ movflt(dest->as_xmm_float_reg(), src_addr);
1142
1143 } else if (dest->is_double_xmm()) {
1144 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1145 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1146
1147 } else if (dest->is_single_fpu()) {
1148 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1149 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1150 __ fld_s(src_addr);
1151
1152 } else if (dest->is_double_fpu()) {
1153 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1154 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1155 __ fld_d(src_addr);
1156
1157 } else {
1158 ShouldNotReachHere();
1159 }
1160 }
1161
1162
1163 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1164 if (src->is_single_stack()) {
1165 if (type == T_OBJECT || type == T_ARRAY) {
1166 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1167 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1168 } else {
1169 #ifndef _LP64
1170 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1171 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1172 #else
1173 //no pushl on 64bits
1174 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1175 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1176 #endif
1177 }
1178
1179 } else if (src->is_double_stack()) {
1180 #ifdef _LP64
1181 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1182 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1183 #else
1184 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1185 // push and pop the part at src + wordSize, adding wordSize for the previous push
1186 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1187 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1188 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1189 #endif // _LP64
1190
1191 } else {
1192 ShouldNotReachHere();
1193 }
1194 }
1195
1196
1197 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1198 assert(src->is_address(), "should not call otherwise");
1199 assert(dest->is_register(), "should not call otherwise");
1200
1201 LIR_Address* addr = src->as_address_ptr();
1202 Address from_addr = as_Address(addr);
1203
1204 switch (type) {
1205 case T_BOOLEAN: // fall through
1206 case T_BYTE: // fall through
1207 case T_CHAR: // fall through
1208 case T_SHORT:
1209 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1210 // on pre P6 processors we may get partial register stalls
1211 // so blow away the value of to_rinfo before loading a
1212 // partial word into it. Do it here so that it precedes
1213 // the potential patch point below.
1214 __ xorptr(dest->as_register(), dest->as_register());
1215 }
1216 break;
1217 }
1218
1219 PatchingStub* patch = NULL;
1220 if (patch_code != lir_patch_none) {
1221 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1222 assert(from_addr.disp() != 0, "must have");
1223 }
1224 if (info != NULL) {
1225 add_debug_info_for_null_check_here(info);
1226 }
1227
1228 switch (type) {
1229 case T_FLOAT: {
1230 if (dest->is_single_xmm()) {
1231 __ movflt(dest->as_xmm_float_reg(), from_addr);
1232 } else {
1233 assert(dest->is_single_fpu(), "must be");
1234 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1235 __ fld_s(from_addr);
1236 }
1237 break;
1238 }
1239
1240 case T_DOUBLE: {
1241 if (dest->is_double_xmm()) {
1242 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1243 } else {
1244 assert(dest->is_double_fpu(), "must be");
1245 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1246 __ fld_d(from_addr);
1247 }
1248 break;
1249 }
1250
1251 case T_ADDRESS: // fall through
1252 case T_OBJECT: // fall through
1253 case T_ARRAY: // fall through
1254 #ifdef _LP64
1255 __ movptr(dest->as_register(), from_addr);
1256 break;
1257 #endif // _L64
1258 case T_INT:
1259 __ movl(dest->as_register(), from_addr);
1260 break;
1261
1262 case T_LONG: {
1263 Register to_lo = dest->as_register_lo();
1264 Register to_hi = dest->as_register_hi();
1265 #ifdef _LP64
1266 __ movptr(to_lo, as_Address_lo(addr));
1267 #else
1268 Register base = addr->base()->as_register();
1269 Register index = noreg;
1270 if (addr->index()->is_register()) {
1271 index = addr->index()->as_register();
1272 }
1273 if ((base == to_lo && index == to_hi) ||
1274 (base == to_hi && index == to_lo)) {
1275 // addresses with 2 registers are only formed as a result of
1276 // array access so this code will never have to deal with
1277 // patches or null checks.
1278 assert(info == NULL && patch == NULL, "must be");
1279 __ lea(to_hi, as_Address(addr));
1280 __ movl(to_lo, Address(to_hi, 0));
1281 __ movl(to_hi, Address(to_hi, BytesPerWord));
1282 } else if (base == to_lo || index == to_lo) {
1283 assert(base != to_hi, "can't be");
1284 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1285 __ movl(to_hi, as_Address_hi(addr));
1286 if (patch != NULL) {
1287 patching_epilog(patch, lir_patch_high, base, info);
1288 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1289 patch_code = lir_patch_low;
1290 }
1291 __ movl(to_lo, as_Address_lo(addr));
1292 } else {
1293 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1294 __ movl(to_lo, as_Address_lo(addr));
1295 if (patch != NULL) {
1296 patching_epilog(patch, lir_patch_low, base, info);
1297 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1298 patch_code = lir_patch_high;
1299 }
1300 __ movl(to_hi, as_Address_hi(addr));
1301 }
1302 #endif // _LP64
1303 break;
1304 }
1305
1306 case T_BOOLEAN: // fall through
1307 case T_BYTE: {
1308 Register dest_reg = dest->as_register();
1309 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1310 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1311 __ movsbl(dest_reg, from_addr);
1312 } else {
1313 __ movb(dest_reg, from_addr);
1314 __ shll(dest_reg, 24);
1315 __ sarl(dest_reg, 24);
1316 }
1317 break;
1318 }
1319
1320 case T_CHAR: {
1321 Register dest_reg = dest->as_register();
1322 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1324 __ movzwl(dest_reg, from_addr);
1325 } else {
1326 __ movw(dest_reg, from_addr);
1327 }
1328 break;
1329 }
1330
1331 case T_SHORT: {
1332 Register dest_reg = dest->as_register();
1333 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1334 __ movswl(dest_reg, from_addr);
1335 } else {
1336 __ movw(dest_reg, from_addr);
1337 __ shll(dest_reg, 16);
1338 __ sarl(dest_reg, 16);
1339 }
1340 break;
1341 }
1342
1343 default:
1344 ShouldNotReachHere();
1345 }
1346
1347 if (patch != NULL) {
1348 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1349 }
1350
1351 if (type == T_ARRAY || type == T_OBJECT) {
1352 __ verify_oop(dest->as_register());
1353 }
1354 }
1355
1356
1357 void LIR_Assembler::prefetchr(LIR_Opr src) {
1358 LIR_Address* addr = src->as_address_ptr();
1359 Address from_addr = as_Address(addr);
1360
1361 if (VM_Version::supports_sse()) {
1362 switch (ReadPrefetchInstr) {
1363 case 0:
1364 __ prefetchnta(from_addr); break;
1365 case 1:
1366 __ prefetcht0(from_addr); break;
1367 case 2:
1368 __ prefetcht2(from_addr); break;
1369 default:
1370 ShouldNotReachHere(); break;
1371 }
1372 } else if (VM_Version::supports_3dnow()) {
1373 __ prefetchr(from_addr);
1374 }
1375 }
1376
1377
1378 void LIR_Assembler::prefetchw(LIR_Opr src) {
1379 LIR_Address* addr = src->as_address_ptr();
1380 Address from_addr = as_Address(addr);
1381
1382 if (VM_Version::supports_sse()) {
1383 switch (AllocatePrefetchInstr) {
1384 case 0:
1385 __ prefetchnta(from_addr); break;
1386 case 1:
1387 __ prefetcht0(from_addr); break;
1388 case 2:
1389 __ prefetcht2(from_addr); break;
1390 case 3:
1391 __ prefetchw(from_addr); break;
1392 default:
1393 ShouldNotReachHere(); break;
1394 }
1395 } else if (VM_Version::supports_3dnow()) {
1396 __ prefetchw(from_addr);
1397 }
1398 }
1399
1400
1401 NEEDS_CLEANUP; // This could be static?
1402 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1403 int elem_size = type2aelembytes(type);
1404 switch (elem_size) {
1405 case 1: return Address::times_1;
1406 case 2: return Address::times_2;
1407 case 4: return Address::times_4;
1408 case 8: return Address::times_8;
1409 }
1410 ShouldNotReachHere();
1411 return Address::no_scale;
1412 }
1413
1414
1415 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1416 switch (op->code()) {
1417 case lir_idiv:
1418 case lir_irem:
1419 arithmetic_idiv(op->code(),
1420 op->in_opr1(),
1421 op->in_opr2(),
1422 op->in_opr3(),
1423 op->result_opr(),
1424 op->info());
1425 break;
1426 default: ShouldNotReachHere(); break;
1427 }
1428 }
1429
1430 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1431 #ifdef ASSERT
1432 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1433 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1434 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1435 #endif
1436
1437 if (op->cond() == lir_cond_always) {
1438 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1439 __ jmp (*(op->label()));
1440 } else {
1441 Assembler::Condition acond = Assembler::zero;
1442 if (op->code() == lir_cond_float_branch) {
1443 assert(op->ublock() != NULL, "must have unordered successor");
1444 __ jcc(Assembler::parity, *(op->ublock()->label()));
1445 switch(op->cond()) {
1446 case lir_cond_equal: acond = Assembler::equal; break;
1447 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1448 case lir_cond_less: acond = Assembler::below; break;
1449 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1450 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1451 case lir_cond_greater: acond = Assembler::above; break;
1452 default: ShouldNotReachHere();
1453 }
1454 } else {
1455 switch (op->cond()) {
1456 case lir_cond_equal: acond = Assembler::equal; break;
1457 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1458 case lir_cond_less: acond = Assembler::less; break;
1459 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1460 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1461 case lir_cond_greater: acond = Assembler::greater; break;
1462 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1463 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1464 default: ShouldNotReachHere();
1465 }
1466 }
1467 __ jcc(acond,*(op->label()));
1468 }
1469 }
1470
1471 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1472 LIR_Opr src = op->in_opr();
1473 LIR_Opr dest = op->result_opr();
1474
1475 switch (op->bytecode()) {
1476 case Bytecodes::_i2l:
1477 #ifdef _LP64
1478 __ movl2ptr(dest->as_register_lo(), src->as_register());
1479 #else
1480 move_regs(src->as_register(), dest->as_register_lo());
1481 move_regs(src->as_register(), dest->as_register_hi());
1482 __ sarl(dest->as_register_hi(), 31);
1483 #endif // LP64
1484 break;
1485
1486 case Bytecodes::_l2i:
1487 move_regs(src->as_register_lo(), dest->as_register());
1488 break;
1489
1490 case Bytecodes::_i2b:
1491 move_regs(src->as_register(), dest->as_register());
1492 __ sign_extend_byte(dest->as_register());
1493 break;
1494
1495 case Bytecodes::_i2c:
1496 move_regs(src->as_register(), dest->as_register());
1497 __ andl(dest->as_register(), 0xFFFF);
1498 break;
1499
1500 case Bytecodes::_i2s:
1501 move_regs(src->as_register(), dest->as_register());
1502 __ sign_extend_short(dest->as_register());
1503 break;
1504
1505
1506 case Bytecodes::_f2d:
1507 case Bytecodes::_d2f:
1508 if (dest->is_single_xmm()) {
1509 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1510 } else if (dest->is_double_xmm()) {
1511 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1512 } else {
1513 assert(src->fpu() == dest->fpu(), "register must be equal");
1514 // do nothing (float result is rounded later through spilling)
1515 }
1516 break;
1517
1518 case Bytecodes::_i2f:
1519 case Bytecodes::_i2d:
1520 if (dest->is_single_xmm()) {
1521 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1522 } else if (dest->is_double_xmm()) {
1523 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1524 } else {
1525 assert(dest->fpu() == 0, "result must be on TOS");
1526 __ movl(Address(rsp, 0), src->as_register());
1527 __ fild_s(Address(rsp, 0));
1528 }
1529 break;
1530
1531 case Bytecodes::_f2i:
1532 case Bytecodes::_d2i:
1533 if (src->is_single_xmm()) {
1534 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1535 } else if (src->is_double_xmm()) {
1536 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1537 } else {
1538 assert(src->fpu() == 0, "input must be on TOS");
1539 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1540 __ fist_s(Address(rsp, 0));
1541 __ movl(dest->as_register(), Address(rsp, 0));
1542 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1543 }
1544
1545 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1546 assert(op->stub() != NULL, "stub required");
1547 __ cmpl(dest->as_register(), 0x80000000);
1548 __ jcc(Assembler::equal, *op->stub()->entry());
1549 __ bind(*op->stub()->continuation());
1550 break;
1551
1552 case Bytecodes::_l2f:
1553 case Bytecodes::_l2d:
1554 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1555 assert(dest->fpu() == 0, "result must be on TOS");
1556
1557 __ movptr(Address(rsp, 0), src->as_register_lo());
1558 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1559 __ fild_d(Address(rsp, 0));
1560 // float result is rounded later through spilling
1561 break;
1562
1563 case Bytecodes::_f2l:
1564 case Bytecodes::_d2l:
1565 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1566 assert(src->fpu() == 0, "input must be on TOS");
1567 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1568
1569 // instruction sequence too long to inline it here
1570 {
1571 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1572 }
1573 break;
1574
1575 default: ShouldNotReachHere();
1576 }
1577 }
1578
1579 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1580 if (op->init_check()) {
1581 __ cmpl(Address(op->klass()->as_register(),
1582 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1583 instanceKlass::fully_initialized);
1584 add_debug_info_for_null_check_here(op->stub()->info());
1585 __ jcc(Assembler::notEqual, *op->stub()->entry());
1586 }
1587 __ allocate_object(op->obj()->as_register(),
1588 op->tmp1()->as_register(),
1589 op->tmp2()->as_register(),
1590 op->header_size(),
1591 op->object_size(),
1592 op->klass()->as_register(),
1593 *op->stub()->entry());
1594 __ bind(*op->stub()->continuation());
1595 }
1596
1597 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1598 if (UseSlowPath ||
1599 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1600 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1601 __ jmp(*op->stub()->entry());
1602 } else {
1603 Register len = op->len()->as_register();
1604 Register tmp1 = op->tmp1()->as_register();
1605 Register tmp2 = op->tmp2()->as_register();
1606 Register tmp3 = op->tmp3()->as_register();
1607 if (len == tmp1) {
1608 tmp1 = tmp3;
1609 } else if (len == tmp2) {
1610 tmp2 = tmp3;
1611 } else if (len == tmp3) {
1612 // everything is ok
1613 } else {
1614 __ mov(tmp3, len);
1615 }
1616 __ allocate_array(op->obj()->as_register(),
1617 len,
1618 tmp1,
1619 tmp2,
1620 arrayOopDesc::header_size(op->type()),
1621 array_element_size(op->type()),
1622 op->klass()->as_register(),
1623 *op->stub()->entry());
1624 }
1625 __ bind(*op->stub()->continuation());
1626 }
1627
1628 void LIR_Assembler::type_profile_helper(Register mdo,
1629 ciMethodData *md, ciProfileData *data,
1630 Register recv, Label* update_done) {
1631 uint i;
1632 for (i = 0; i < ReceiverTypeData::row_limit(); i++) {
1633 Label next_test;
1634 // See if the receiver is receiver[n].
1635 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1636 __ jccb(Assembler::notEqual, next_test);
1637 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1638 __ addptr(data_addr, DataLayout::counter_increment);
1639 __ jmp(*update_done);
1640 __ bind(next_test);
1641 }
1642
1643 // Didn't find receiver; find next empty slot and fill it in
1644 for (i = 0; i < ReceiverTypeData::row_limit(); i++) {
1645 Label next_test;
1646 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1647 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1648 __ jccb(Assembler::notEqual, next_test);
1649 __ movptr(recv_addr, recv);
1650 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1651 __ jmp(*update_done);
1652 __ bind(next_test);
1653 }
1654 }
1655
1656 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1657 // we always need a stub for the failure case.
1658 CodeStub* stub = op->stub();
1659 Register obj = op->object()->as_register();
1660 Register k_RInfo = op->tmp1()->as_register();
1661 Register klass_RInfo = op->tmp2()->as_register();
1662 Register dst = op->result_opr()->as_register();
1663 ciKlass* k = op->klass();
1664 Register Rtmp1 = noreg;
1665
1666 // check if it needs to be profiled
1667 ciMethodData* md;
1668 ciProfileData* data;
1669
1670 if (op->should_profile()) {
1671 ciMethod* method = op->profiled_method();
1672 assert(method != NULL, "Should have method");
1673 int bci = op->profiled_bci();
1674 md = method->method_data();
1675 if (md == NULL) {
1676 bailout("out of memory building methodDataOop");
1677 return;
1678 }
1679 data = md->bci_to_data(bci);
1680 assert(data != NULL, "need data for type check");
1681 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1682 }
1683 Label profile_cast_success, profile_cast_failure;
1684 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1685 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1686
1687 if (obj == k_RInfo) {
1688 k_RInfo = dst;
1689 } else if (obj == klass_RInfo) {
1690 klass_RInfo = dst;
1691 }
1692 if (k->is_loaded()) {
1693 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1694 } else {
1695 Rtmp1 = op->tmp3()->as_register();
1696 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1697 }
1698
1699 assert_different_registers(obj, k_RInfo, klass_RInfo);
1700 if (!k->is_loaded()) {
1701 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1702 } else {
1703 #ifdef _LP64
1704 __ movoop(k_RInfo, k->constant_encoding());
1705 #endif // _LP64
1706 }
1707 assert(obj != k_RInfo, "must be different");
1708
1709 __ cmpptr(obj, (int32_t)NULL_WORD);
1710 if (op->should_profile()) {
1711 Label not_null;
1712 __ jccb(Assembler::notEqual, not_null);
1713 // Object is null; update MDO and exit
1714 Register mdo = klass_RInfo;
1715 __ movoop(mdo, md->constant_encoding());
1716 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1717 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1718 __ orl(data_addr, header_bits);
1719 __ jmp(*obj_is_null);
1720 __ bind(not_null);
1721 } else {
1722 __ jcc(Assembler::equal, *obj_is_null);
1723 }
1724 __ verify_oop(obj);
1725
1726 if (op->fast_check()) {
1727 // get object class
1728 // not a safepoint as obj null check happens earlier
1729 if (k->is_loaded()) {
1730 #ifdef _LP64
1731 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1732 #else
1733 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1734 #endif // _LP64
1735 } else {
1736 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1737 }
1738 __ jcc(Assembler::notEqual, *failure_target);
1739 // successful cast, fall through to profile or jump
1740 } else {
1741 // get object class
1742 // not a safepoint as obj null check happens earlier
1743 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1744 if (k->is_loaded()) {
1745 // See if we get an immediate positive hit
1746 #ifdef _LP64
1747 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1748 #else
1749 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1750 #endif // _LP64
1751 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1752 __ jcc(Assembler::notEqual, *failure_target);
1753 // successful cast, fall through to profile or jump
1754 } else {
1755 // See if we get an immediate positive hit
1756 __ jcc(Assembler::equal, *success_target);
1757 // check for self
1758 #ifdef _LP64
1759 __ cmpptr(klass_RInfo, k_RInfo);
1760 #else
1761 __ cmpoop(klass_RInfo, k->constant_encoding());
1762 #endif // _LP64
1763 __ jcc(Assembler::equal, *success_target);
1764
1765 __ push(klass_RInfo);
1766 #ifdef _LP64
1767 __ push(k_RInfo);
1768 #else
1769 __ pushoop(k->constant_encoding());
1770 #endif // _LP64
1771 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1772 __ pop(klass_RInfo);
1773 __ pop(klass_RInfo);
1774 // result is a boolean
1775 __ cmpl(klass_RInfo, 0);
1776 __ jcc(Assembler::equal, *failure_target);
1777 // successful cast, fall through to profile or jump
1778 }
1779 } else {
1780 // perform the fast part of the checking logic
1781 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1782 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1783 __ push(klass_RInfo);
1784 __ push(k_RInfo);
1785 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1786 __ pop(klass_RInfo);
1787 __ pop(k_RInfo);
1788 // result is a boolean
1789 __ cmpl(k_RInfo, 0);
1790 __ jcc(Assembler::equal, *failure_target);
1791 // successful cast, fall through to profile or jump
1792 }
1793 }
1794 if (op->should_profile()) {
1795 Register mdo = klass_RInfo, recv = k_RInfo;
1796 __ bind(profile_cast_success);
1797 __ movoop(mdo, md->constant_encoding());
1798 __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes()));
1799 Label update_done;
1800 type_profile_helper(mdo, md, data, recv, success);
1801 __ jmp(*success);
1802
1803 __ bind(profile_cast_failure);
1804 __ movoop(mdo, md->constant_encoding());
1805 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1806 __ subptr(counter_addr, DataLayout::counter_increment);
1807 __ jmp(*failure);
1808 }
1809 __ jmp(*success);
1810 }
1811
1812
1813 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1814 LIR_Code code = op->code();
1815 if (code == lir_store_check) {
1816 Register value = op->object()->as_register();
1817 Register array = op->array()->as_register();
1818 Register k_RInfo = op->tmp1()->as_register();
1819 Register klass_RInfo = op->tmp2()->as_register();
1820 Register Rtmp1 = op->tmp3()->as_register();
1821
1822 CodeStub* stub = op->stub();
1823
1824 // check if it needs to be profiled
1825 ciMethodData* md;
1826 ciProfileData* data;
1827
1828 if (op->should_profile()) {
1829 ciMethod* method = op->profiled_method();
1830 assert(method != NULL, "Should have method");
1831 int bci = op->profiled_bci();
1832 md = method->method_data();
1833 if (md == NULL) {
1834 bailout("out of memory building methodDataOop");
1835 return;
1836 }
1837 data = md->bci_to_data(bci);
1838 assert(data != NULL, "need data for type check");
1839 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1840 }
1841 Label profile_cast_success, profile_cast_failure, done;
1842 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1843 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1844
1845 __ cmpptr(value, (int32_t)NULL_WORD);
1846 if (op->should_profile()) {
1847 Label not_null;
1848 __ jccb(Assembler::notEqual, not_null);
1849 // Object is null; update MDO and exit
1850 Register mdo = klass_RInfo;
1851 __ movoop(mdo, md->constant_encoding());
1852 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1853 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1854 __ orl(data_addr, header_bits);
1855 __ jmp(done);
1856 __ bind(not_null);
1857 } else {
1858 __ jcc(Assembler::equal, done);
1859 }
1860
1861 add_debug_info_for_null_check_here(op->info_for_exception());
1862 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1863 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1864
1865 // get instance klass
1866 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1867 // perform the fast part of the checking logic
1868 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1869 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1870 __ push(klass_RInfo);
1871 __ push(k_RInfo);
1872 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1873 __ pop(klass_RInfo);
1874 __ pop(k_RInfo);
1875 // result is a boolean
1876 __ cmpl(k_RInfo, 0);
1877 __ jcc(Assembler::equal, *failure_target);
1878 // fall through to the success case
1879
1880 if (op->should_profile()) {
1881 Register mdo = klass_RInfo, recv = k_RInfo;
1882 __ bind(profile_cast_success);
1883 __ movoop(mdo, md->constant_encoding());
1884 __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes()));
1885 Label update_done;
1886 type_profile_helper(mdo, md, data, recv, &done);
1887 __ jmpb(done);
1888
1889 __ bind(profile_cast_failure);
1890 __ movoop(mdo, md->constant_encoding());
1891 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1892 __ subptr(counter_addr, DataLayout::counter_increment);
1893 __ jmp(*stub->entry());
1894 }
1895
1896 __ bind(done);
1897 } else
1898 if (code == lir_checkcast) {
1899 Register obj = op->object()->as_register();
1900 Register dst = op->result_opr()->as_register();
1901 Label success;
1902 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1903 __ bind(success);
1904 if (dst != obj) {
1905 __ mov(dst, obj);
1906 }
1907 } else
1908 if (code == lir_instanceof) {
1909 Register obj = op->object()->as_register();
1910 Register dst = op->result_opr()->as_register();
1911 Label success, failure, done;
1912 emit_typecheck_helper(op, &success, &failure, &failure);
1913 __ bind(failure);
1914 __ xorptr(dst, dst);
1915 __ jmpb(done);
1916 __ bind(success);
1917 __ movptr(dst, 1);
1918 __ bind(done);
1919 } else {
1920 ShouldNotReachHere();
1921 }
1922
1923 }
1924
1925
1926 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1927 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1928 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1929 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1930 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1931 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1932 Register addr = op->addr()->as_register();
1933 if (os::is_MP()) {
1934 __ lock();
1935 }
1936 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1937
1938 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1939 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1940 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1941 Register newval = op->new_value()->as_register();
1942 Register cmpval = op->cmp_value()->as_register();
1943 assert(cmpval == rax, "wrong register");
1944 assert(newval != NULL, "new val must be register");
1945 assert(cmpval != newval, "cmp and new values must be in different registers");
1946 assert(cmpval != addr, "cmp and addr must be in different registers");
1947 assert(newval != addr, "new value and addr must be in different registers");
1948 if (os::is_MP()) {
1949 __ lock();
1950 }
1951 if ( op->code() == lir_cas_obj) {
1952 __ cmpxchgptr(newval, Address(addr, 0));
1953 } else if (op->code() == lir_cas_int) {
1954 __ cmpxchgl(newval, Address(addr, 0));
1955 } else {
1956 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1957 }
1958 #ifdef _LP64
1959 } else if (op->code() == lir_cas_long) {
1960 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1961 Register newval = op->new_value()->as_register_lo();
1962 Register cmpval = op->cmp_value()->as_register_lo();
1963 assert(cmpval == rax, "wrong register");
1964 assert(newval != NULL, "new val must be register");
1965 assert(cmpval != newval, "cmp and new values must be in different registers");
1966 assert(cmpval != addr, "cmp and addr must be in different registers");
1967 assert(newval != addr, "new value and addr must be in different registers");
1968 if (os::is_MP()) {
1969 __ lock();
1970 }
1971 __ cmpxchgq(newval, Address(addr, 0));
1972 #endif // _LP64
1973 } else {
1974 Unimplemented();
1975 }
1976 }
1977
1978 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1979 Assembler::Condition acond, ncond;
1980 switch (condition) {
1981 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1982 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1983 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1984 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1985 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1986 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1987 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1988 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1989 default: ShouldNotReachHere();
1990 }
1991
1992 if (opr1->is_cpu_register()) {
1993 reg2reg(opr1, result);
1994 } else if (opr1->is_stack()) {
1995 stack2reg(opr1, result, result->type());
1996 } else if (opr1->is_constant()) {
1997 const2reg(opr1, result, lir_patch_none, NULL);
1998 } else {
1999 ShouldNotReachHere();
2000 }
2001
2002 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2003 // optimized version that does not require a branch
2004 if (opr2->is_single_cpu()) {
2005 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2006 __ cmov(ncond, result->as_register(), opr2->as_register());
2007 } else if (opr2->is_double_cpu()) {
2008 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2009 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2010 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2011 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2012 } else if (opr2->is_single_stack()) {
2013 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2014 } else if (opr2->is_double_stack()) {
2015 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2016 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2017 } else {
2018 ShouldNotReachHere();
2019 }
2020
2021 } else {
2022 Label skip;
2023 __ jcc (acond, skip);
2024 if (opr2->is_cpu_register()) {
2025 reg2reg(opr2, result);
2026 } else if (opr2->is_stack()) {
2027 stack2reg(opr2, result, result->type());
2028 } else if (opr2->is_constant()) {
2029 const2reg(opr2, result, lir_patch_none, NULL);
2030 } else {
2031 ShouldNotReachHere();
2032 }
2033 __ bind(skip);
2034 }
2035 }
2036
2037
2038 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2039 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2040
2041 if (left->is_single_cpu()) {
2042 assert(left == dest, "left and dest must be equal");
2043 Register lreg = left->as_register();
2044
2045 if (right->is_single_cpu()) {
2046 // cpu register - cpu register
2047 Register rreg = right->as_register();
2048 switch (code) {
2049 case lir_add: __ addl (lreg, rreg); break;
2050 case lir_sub: __ subl (lreg, rreg); break;
2051 case lir_mul: __ imull(lreg, rreg); break;
2052 default: ShouldNotReachHere();
2053 }
2054
2055 } else if (right->is_stack()) {
2056 // cpu register - stack
2057 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2058 switch (code) {
2059 case lir_add: __ addl(lreg, raddr); break;
2060 case lir_sub: __ subl(lreg, raddr); break;
2061 default: ShouldNotReachHere();
2062 }
2063
2064 } else if (right->is_constant()) {
2065 // cpu register - constant
2066 jint c = right->as_constant_ptr()->as_jint();
2067 switch (code) {
2068 case lir_add: {
2069 __ incrementl(lreg, c);
2070 break;
2071 }
2072 case lir_sub: {
2073 __ decrementl(lreg, c);
2074 break;
2075 }
2076 default: ShouldNotReachHere();
2077 }
2078
2079 } else {
2080 ShouldNotReachHere();
2081 }
2082
2083 } else if (left->is_double_cpu()) {
2084 assert(left == dest, "left and dest must be equal");
2085 Register lreg_lo = left->as_register_lo();
2086 Register lreg_hi = left->as_register_hi();
2087
2088 if (right->is_double_cpu()) {
2089 // cpu register - cpu register
2090 Register rreg_lo = right->as_register_lo();
2091 Register rreg_hi = right->as_register_hi();
2092 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2093 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2094 switch (code) {
2095 case lir_add:
2096 __ addptr(lreg_lo, rreg_lo);
2097 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2098 break;
2099 case lir_sub:
2100 __ subptr(lreg_lo, rreg_lo);
2101 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2102 break;
2103 case lir_mul:
2104 #ifdef _LP64
2105 __ imulq(lreg_lo, rreg_lo);
2106 #else
2107 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2108 __ imull(lreg_hi, rreg_lo);
2109 __ imull(rreg_hi, lreg_lo);
2110 __ addl (rreg_hi, lreg_hi);
2111 __ mull (rreg_lo);
2112 __ addl (lreg_hi, rreg_hi);
2113 #endif // _LP64
2114 break;
2115 default:
2116 ShouldNotReachHere();
2117 }
2118
2119 } else if (right->is_constant()) {
2120 // cpu register - constant
2121 #ifdef _LP64
2122 jlong c = right->as_constant_ptr()->as_jlong_bits();
2123 __ movptr(r10, (intptr_t) c);
2124 switch (code) {
2125 case lir_add:
2126 __ addptr(lreg_lo, r10);
2127 break;
2128 case lir_sub:
2129 __ subptr(lreg_lo, r10);
2130 break;
2131 default:
2132 ShouldNotReachHere();
2133 }
2134 #else
2135 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2136 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2137 switch (code) {
2138 case lir_add:
2139 __ addptr(lreg_lo, c_lo);
2140 __ adcl(lreg_hi, c_hi);
2141 break;
2142 case lir_sub:
2143 __ subptr(lreg_lo, c_lo);
2144 __ sbbl(lreg_hi, c_hi);
2145 break;
2146 default:
2147 ShouldNotReachHere();
2148 }
2149 #endif // _LP64
2150
2151 } else {
2152 ShouldNotReachHere();
2153 }
2154
2155 } else if (left->is_single_xmm()) {
2156 assert(left == dest, "left and dest must be equal");
2157 XMMRegister lreg = left->as_xmm_float_reg();
2158
2159 if (right->is_single_xmm()) {
2160 XMMRegister rreg = right->as_xmm_float_reg();
2161 switch (code) {
2162 case lir_add: __ addss(lreg, rreg); break;
2163 case lir_sub: __ subss(lreg, rreg); break;
2164 case lir_mul_strictfp: // fall through
2165 case lir_mul: __ mulss(lreg, rreg); break;
2166 case lir_div_strictfp: // fall through
2167 case lir_div: __ divss(lreg, rreg); break;
2168 default: ShouldNotReachHere();
2169 }
2170 } else {
2171 Address raddr;
2172 if (right->is_single_stack()) {
2173 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2174 } else if (right->is_constant()) {
2175 // hack for now
2176 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2177 } else {
2178 ShouldNotReachHere();
2179 }
2180 switch (code) {
2181 case lir_add: __ addss(lreg, raddr); break;
2182 case lir_sub: __ subss(lreg, raddr); break;
2183 case lir_mul_strictfp: // fall through
2184 case lir_mul: __ mulss(lreg, raddr); break;
2185 case lir_div_strictfp: // fall through
2186 case lir_div: __ divss(lreg, raddr); break;
2187 default: ShouldNotReachHere();
2188 }
2189 }
2190
2191 } else if (left->is_double_xmm()) {
2192 assert(left == dest, "left and dest must be equal");
2193
2194 XMMRegister lreg = left->as_xmm_double_reg();
2195 if (right->is_double_xmm()) {
2196 XMMRegister rreg = right->as_xmm_double_reg();
2197 switch (code) {
2198 case lir_add: __ addsd(lreg, rreg); break;
2199 case lir_sub: __ subsd(lreg, rreg); break;
2200 case lir_mul_strictfp: // fall through
2201 case lir_mul: __ mulsd(lreg, rreg); break;
2202 case lir_div_strictfp: // fall through
2203 case lir_div: __ divsd(lreg, rreg); break;
2204 default: ShouldNotReachHere();
2205 }
2206 } else {
2207 Address raddr;
2208 if (right->is_double_stack()) {
2209 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2210 } else if (right->is_constant()) {
2211 // hack for now
2212 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2213 } else {
2214 ShouldNotReachHere();
2215 }
2216 switch (code) {
2217 case lir_add: __ addsd(lreg, raddr); break;
2218 case lir_sub: __ subsd(lreg, raddr); break;
2219 case lir_mul_strictfp: // fall through
2220 case lir_mul: __ mulsd(lreg, raddr); break;
2221 case lir_div_strictfp: // fall through
2222 case lir_div: __ divsd(lreg, raddr); break;
2223 default: ShouldNotReachHere();
2224 }
2225 }
2226
2227 } else if (left->is_single_fpu()) {
2228 assert(dest->is_single_fpu(), "fpu stack allocation required");
2229
2230 if (right->is_single_fpu()) {
2231 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2232
2233 } else {
2234 assert(left->fpu_regnr() == 0, "left must be on TOS");
2235 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2236
2237 Address raddr;
2238 if (right->is_single_stack()) {
2239 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2240 } else if (right->is_constant()) {
2241 address const_addr = float_constant(right->as_jfloat());
2242 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2243 // hack for now
2244 raddr = __ as_Address(InternalAddress(const_addr));
2245 } else {
2246 ShouldNotReachHere();
2247 }
2248
2249 switch (code) {
2250 case lir_add: __ fadd_s(raddr); break;
2251 case lir_sub: __ fsub_s(raddr); break;
2252 case lir_mul_strictfp: // fall through
2253 case lir_mul: __ fmul_s(raddr); break;
2254 case lir_div_strictfp: // fall through
2255 case lir_div: __ fdiv_s(raddr); break;
2256 default: ShouldNotReachHere();
2257 }
2258 }
2259
2260 } else if (left->is_double_fpu()) {
2261 assert(dest->is_double_fpu(), "fpu stack allocation required");
2262
2263 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2264 // Double values require special handling for strictfp mul/div on x86
2265 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2266 __ fmulp(left->fpu_regnrLo() + 1);
2267 }
2268
2269 if (right->is_double_fpu()) {
2270 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2271
2272 } else {
2273 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2274 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2275
2276 Address raddr;
2277 if (right->is_double_stack()) {
2278 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2279 } else if (right->is_constant()) {
2280 // hack for now
2281 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2282 } else {
2283 ShouldNotReachHere();
2284 }
2285
2286 switch (code) {
2287 case lir_add: __ fadd_d(raddr); break;
2288 case lir_sub: __ fsub_d(raddr); break;
2289 case lir_mul_strictfp: // fall through
2290 case lir_mul: __ fmul_d(raddr); break;
2291 case lir_div_strictfp: // fall through
2292 case lir_div: __ fdiv_d(raddr); break;
2293 default: ShouldNotReachHere();
2294 }
2295 }
2296
2297 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2298 // Double values require special handling for strictfp mul/div on x86
2299 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2300 __ fmulp(dest->fpu_regnrLo() + 1);
2301 }
2302
2303 } else if (left->is_single_stack() || left->is_address()) {
2304 assert(left == dest, "left and dest must be equal");
2305
2306 Address laddr;
2307 if (left->is_single_stack()) {
2308 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2309 } else if (left->is_address()) {
2310 laddr = as_Address(left->as_address_ptr());
2311 } else {
2312 ShouldNotReachHere();
2313 }
2314
2315 if (right->is_single_cpu()) {
2316 Register rreg = right->as_register();
2317 switch (code) {
2318 case lir_add: __ addl(laddr, rreg); break;
2319 case lir_sub: __ subl(laddr, rreg); break;
2320 default: ShouldNotReachHere();
2321 }
2322 } else if (right->is_constant()) {
2323 jint c = right->as_constant_ptr()->as_jint();
2324 switch (code) {
2325 case lir_add: {
2326 __ incrementl(laddr, c);
2327 break;
2328 }
2329 case lir_sub: {
2330 __ decrementl(laddr, c);
2331 break;
2332 }
2333 default: ShouldNotReachHere();
2334 }
2335 } else {
2336 ShouldNotReachHere();
2337 }
2338
2339 } else {
2340 ShouldNotReachHere();
2341 }
2342 }
2343
2344 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2345 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2346 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2347 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2348
2349 bool left_is_tos = (left_index == 0);
2350 bool dest_is_tos = (dest_index == 0);
2351 int non_tos_index = (left_is_tos ? right_index : left_index);
2352
2353 switch (code) {
2354 case lir_add:
2355 if (pop_fpu_stack) __ faddp(non_tos_index);
2356 else if (dest_is_tos) __ fadd (non_tos_index);
2357 else __ fadda(non_tos_index);
2358 break;
2359
2360 case lir_sub:
2361 if (left_is_tos) {
2362 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2363 else if (dest_is_tos) __ fsub (non_tos_index);
2364 else __ fsubra(non_tos_index);
2365 } else {
2366 if (pop_fpu_stack) __ fsubp (non_tos_index);
2367 else if (dest_is_tos) __ fsubr (non_tos_index);
2368 else __ fsuba (non_tos_index);
2369 }
2370 break;
2371
2372 case lir_mul_strictfp: // fall through
2373 case lir_mul:
2374 if (pop_fpu_stack) __ fmulp(non_tos_index);
2375 else if (dest_is_tos) __ fmul (non_tos_index);
2376 else __ fmula(non_tos_index);
2377 break;
2378
2379 case lir_div_strictfp: // fall through
2380 case lir_div:
2381 if (left_is_tos) {
2382 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2383 else if (dest_is_tos) __ fdiv (non_tos_index);
2384 else __ fdivra(non_tos_index);
2385 } else {
2386 if (pop_fpu_stack) __ fdivp (non_tos_index);
2387 else if (dest_is_tos) __ fdivr (non_tos_index);
2388 else __ fdiva (non_tos_index);
2389 }
2390 break;
2391
2392 case lir_rem:
2393 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2394 __ fremr(noreg);
2395 break;
2396
2397 default:
2398 ShouldNotReachHere();
2399 }
2400 }
2401
2402
2403 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2404 if (value->is_double_xmm()) {
2405 switch(code) {
2406 case lir_abs :
2407 {
2408 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2409 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2410 }
2411 __ andpd(dest->as_xmm_double_reg(),
2412 ExternalAddress((address)double_signmask_pool));
2413 }
2414 break;
2415
2416 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2417 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2418 default : ShouldNotReachHere();
2419 }
2420
2421 } else if (value->is_double_fpu()) {
2422 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2423 switch(code) {
2424 case lir_log : __ flog() ; break;
2425 case lir_log10 : __ flog10() ; break;
2426 case lir_abs : __ fabs() ; break;
2427 case lir_sqrt : __ fsqrt(); break;
2428 case lir_sin :
2429 // Should consider not saving rbx, if not necessary
2430 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2431 break;
2432 case lir_cos :
2433 // Should consider not saving rbx, if not necessary
2434 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2435 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2436 break;
2437 case lir_tan :
2438 // Should consider not saving rbx, if not necessary
2439 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2440 break;
2441 default : ShouldNotReachHere();
2442 }
2443 } else {
2444 Unimplemented();
2445 }
2446 }
2447
2448 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2449 // assert(left->destroys_register(), "check");
2450 if (left->is_single_cpu()) {
2451 Register reg = left->as_register();
2452 if (right->is_constant()) {
2453 int val = right->as_constant_ptr()->as_jint();
2454 switch (code) {
2455 case lir_logic_and: __ andl (reg, val); break;
2456 case lir_logic_or: __ orl (reg, val); break;
2457 case lir_logic_xor: __ xorl (reg, val); break;
2458 default: ShouldNotReachHere();
2459 }
2460 } else if (right->is_stack()) {
2461 // added support for stack operands
2462 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2463 switch (code) {
2464 case lir_logic_and: __ andl (reg, raddr); break;
2465 case lir_logic_or: __ orl (reg, raddr); break;
2466 case lir_logic_xor: __ xorl (reg, raddr); break;
2467 default: ShouldNotReachHere();
2468 }
2469 } else {
2470 Register rright = right->as_register();
2471 switch (code) {
2472 case lir_logic_and: __ andptr (reg, rright); break;
2473 case lir_logic_or : __ orptr (reg, rright); break;
2474 case lir_logic_xor: __ xorptr (reg, rright); break;
2475 default: ShouldNotReachHere();
2476 }
2477 }
2478 move_regs(reg, dst->as_register());
2479 } else {
2480 Register l_lo = left->as_register_lo();
2481 Register l_hi = left->as_register_hi();
2482 if (right->is_constant()) {
2483 #ifdef _LP64
2484 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2485 switch (code) {
2486 case lir_logic_and:
2487 __ andq(l_lo, rscratch1);
2488 break;
2489 case lir_logic_or:
2490 __ orq(l_lo, rscratch1);
2491 break;
2492 case lir_logic_xor:
2493 __ xorq(l_lo, rscratch1);
2494 break;
2495 default: ShouldNotReachHere();
2496 }
2497 #else
2498 int r_lo = right->as_constant_ptr()->as_jint_lo();
2499 int r_hi = right->as_constant_ptr()->as_jint_hi();
2500 switch (code) {
2501 case lir_logic_and:
2502 __ andl(l_lo, r_lo);
2503 __ andl(l_hi, r_hi);
2504 break;
2505 case lir_logic_or:
2506 __ orl(l_lo, r_lo);
2507 __ orl(l_hi, r_hi);
2508 break;
2509 case lir_logic_xor:
2510 __ xorl(l_lo, r_lo);
2511 __ xorl(l_hi, r_hi);
2512 break;
2513 default: ShouldNotReachHere();
2514 }
2515 #endif // _LP64
2516 } else {
2517 #ifdef _LP64
2518 Register r_lo;
2519 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2520 r_lo = right->as_register();
2521 } else {
2522 r_lo = right->as_register_lo();
2523 }
2524 #else
2525 Register r_lo = right->as_register_lo();
2526 Register r_hi = right->as_register_hi();
2527 assert(l_lo != r_hi, "overwriting registers");
2528 #endif
2529 switch (code) {
2530 case lir_logic_and:
2531 __ andptr(l_lo, r_lo);
2532 NOT_LP64(__ andptr(l_hi, r_hi);)
2533 break;
2534 case lir_logic_or:
2535 __ orptr(l_lo, r_lo);
2536 NOT_LP64(__ orptr(l_hi, r_hi);)
2537 break;
2538 case lir_logic_xor:
2539 __ xorptr(l_lo, r_lo);
2540 NOT_LP64(__ xorptr(l_hi, r_hi);)
2541 break;
2542 default: ShouldNotReachHere();
2543 }
2544 }
2545
2546 Register dst_lo = dst->as_register_lo();
2547 Register dst_hi = dst->as_register_hi();
2548
2549 #ifdef _LP64
2550 move_regs(l_lo, dst_lo);
2551 #else
2552 if (dst_lo == l_hi) {
2553 assert(dst_hi != l_lo, "overwriting registers");
2554 move_regs(l_hi, dst_hi);
2555 move_regs(l_lo, dst_lo);
2556 } else {
2557 assert(dst_lo != l_hi, "overwriting registers");
2558 move_regs(l_lo, dst_lo);
2559 move_regs(l_hi, dst_hi);
2560 }
2561 #endif // _LP64
2562 }
2563 }
2564
2565
2566 // we assume that rax, and rdx can be overwritten
2567 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2568
2569 assert(left->is_single_cpu(), "left must be register");
2570 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2571 assert(result->is_single_cpu(), "result must be register");
2572
2573 // assert(left->destroys_register(), "check");
2574 // assert(right->destroys_register(), "check");
2575
2576 Register lreg = left->as_register();
2577 Register dreg = result->as_register();
2578
2579 if (right->is_constant()) {
2580 int divisor = right->as_constant_ptr()->as_jint();
2581 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2582 if (code == lir_idiv) {
2583 assert(lreg == rax, "must be rax,");
2584 assert(temp->as_register() == rdx, "tmp register must be rdx");
2585 __ cdql(); // sign extend into rdx:rax
2586 if (divisor == 2) {
2587 __ subl(lreg, rdx);
2588 } else {
2589 __ andl(rdx, divisor - 1);
2590 __ addl(lreg, rdx);
2591 }
2592 __ sarl(lreg, log2_intptr(divisor));
2593 move_regs(lreg, dreg);
2594 } else if (code == lir_irem) {
2595 Label done;
2596 __ mov(dreg, lreg);
2597 __ andl(dreg, 0x80000000 | (divisor - 1));
2598 __ jcc(Assembler::positive, done);
2599 __ decrement(dreg);
2600 __ orl(dreg, ~(divisor - 1));
2601 __ increment(dreg);
2602 __ bind(done);
2603 } else {
2604 ShouldNotReachHere();
2605 }
2606 } else {
2607 Register rreg = right->as_register();
2608 assert(lreg == rax, "left register must be rax,");
2609 assert(rreg != rdx, "right register must not be rdx");
2610 assert(temp->as_register() == rdx, "tmp register must be rdx");
2611
2612 move_regs(lreg, rax);
2613
2614 int idivl_offset = __ corrected_idivl(rreg);
2615 add_debug_info_for_div0(idivl_offset, info);
2616 if (code == lir_irem) {
2617 move_regs(rdx, dreg); // result is in rdx
2618 } else {
2619 move_regs(rax, dreg);
2620 }
2621 }
2622 }
2623
2624
2625 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2626 if (opr1->is_single_cpu()) {
2627 Register reg1 = opr1->as_register();
2628 if (opr2->is_single_cpu()) {
2629 // cpu register - cpu register
2630 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2631 __ cmpptr(reg1, opr2->as_register());
2632 } else {
2633 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2634 __ cmpl(reg1, opr2->as_register());
2635 }
2636 } else if (opr2->is_stack()) {
2637 // cpu register - stack
2638 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2639 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2640 } else {
2641 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2642 }
2643 } else if (opr2->is_constant()) {
2644 // cpu register - constant
2645 LIR_Const* c = opr2->as_constant_ptr();
2646 if (c->type() == T_INT) {
2647 __ cmpl(reg1, c->as_jint());
2648 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2649 // In 64bit oops are single register
2650 jobject o = c->as_jobject();
2651 if (o == NULL) {
2652 __ cmpptr(reg1, (int32_t)NULL_WORD);
2653 } else {
2654 #ifdef _LP64
2655 __ movoop(rscratch1, o);
2656 __ cmpptr(reg1, rscratch1);
2657 #else
2658 __ cmpoop(reg1, c->as_jobject());
2659 #endif // _LP64
2660 }
2661 } else {
2662 ShouldNotReachHere();
2663 }
2664 // cpu register - address
2665 } else if (opr2->is_address()) {
2666 if (op->info() != NULL) {
2667 add_debug_info_for_null_check_here(op->info());
2668 }
2669 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2670 } else {
2671 ShouldNotReachHere();
2672 }
2673
2674 } else if(opr1->is_double_cpu()) {
2675 Register xlo = opr1->as_register_lo();
2676 Register xhi = opr1->as_register_hi();
2677 if (opr2->is_double_cpu()) {
2678 #ifdef _LP64
2679 __ cmpptr(xlo, opr2->as_register_lo());
2680 #else
2681 // cpu register - cpu register
2682 Register ylo = opr2->as_register_lo();
2683 Register yhi = opr2->as_register_hi();
2684 __ subl(xlo, ylo);
2685 __ sbbl(xhi, yhi);
2686 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2687 __ orl(xhi, xlo);
2688 }
2689 #endif // _LP64
2690 } else if (opr2->is_constant()) {
2691 // cpu register - constant 0
2692 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2693 #ifdef _LP64
2694 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2695 #else
2696 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2697 __ orl(xhi, xlo);
2698 #endif // _LP64
2699 } else {
2700 ShouldNotReachHere();
2701 }
2702
2703 } else if (opr1->is_single_xmm()) {
2704 XMMRegister reg1 = opr1->as_xmm_float_reg();
2705 if (opr2->is_single_xmm()) {
2706 // xmm register - xmm register
2707 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2708 } else if (opr2->is_stack()) {
2709 // xmm register - stack
2710 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2711 } else if (opr2->is_constant()) {
2712 // xmm register - constant
2713 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2714 } else if (opr2->is_address()) {
2715 // xmm register - address
2716 if (op->info() != NULL) {
2717 add_debug_info_for_null_check_here(op->info());
2718 }
2719 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2720 } else {
2721 ShouldNotReachHere();
2722 }
2723
2724 } else if (opr1->is_double_xmm()) {
2725 XMMRegister reg1 = opr1->as_xmm_double_reg();
2726 if (opr2->is_double_xmm()) {
2727 // xmm register - xmm register
2728 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2729 } else if (opr2->is_stack()) {
2730 // xmm register - stack
2731 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2732 } else if (opr2->is_constant()) {
2733 // xmm register - constant
2734 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2735 } else if (opr2->is_address()) {
2736 // xmm register - address
2737 if (op->info() != NULL) {
2738 add_debug_info_for_null_check_here(op->info());
2739 }
2740 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2741 } else {
2742 ShouldNotReachHere();
2743 }
2744
2745 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2746 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2747 assert(opr2->is_fpu_register(), "both must be registers");
2748 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2749
2750 } else if (opr1->is_address() && opr2->is_constant()) {
2751 LIR_Const* c = opr2->as_constant_ptr();
2752 #ifdef _LP64
2753 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2754 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2755 __ movoop(rscratch1, c->as_jobject());
2756 }
2757 #endif // LP64
2758 if (op->info() != NULL) {
2759 add_debug_info_for_null_check_here(op->info());
2760 }
2761 // special case: address - constant
2762 LIR_Address* addr = opr1->as_address_ptr();
2763 if (c->type() == T_INT) {
2764 __ cmpl(as_Address(addr), c->as_jint());
2765 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2766 #ifdef _LP64
2767 // %%% Make this explode if addr isn't reachable until we figure out a
2768 // better strategy by giving noreg as the temp for as_Address
2769 __ cmpptr(rscratch1, as_Address(addr, noreg));
2770 #else
2771 __ cmpoop(as_Address(addr), c->as_jobject());
2772 #endif // _LP64
2773 } else {
2774 ShouldNotReachHere();
2775 }
2776
2777 } else {
2778 ShouldNotReachHere();
2779 }
2780 }
2781
2782 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2783 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2784 if (left->is_single_xmm()) {
2785 assert(right->is_single_xmm(), "must match");
2786 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2787 } else if (left->is_double_xmm()) {
2788 assert(right->is_double_xmm(), "must match");
2789 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2790
2791 } else {
2792 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2793 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2794
2795 assert(left->fpu() == 0, "left must be on TOS");
2796 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2797 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2798 }
2799 } else {
2800 assert(code == lir_cmp_l2i, "check");
2801 #ifdef _LP64
2802 Label done;
2803 Register dest = dst->as_register();
2804 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2805 __ movl(dest, -1);
2806 __ jccb(Assembler::less, done);
2807 __ set_byte_if_not_zero(dest);
2808 __ movzbl(dest, dest);
2809 __ bind(done);
2810 #else
2811 __ lcmp2int(left->as_register_hi(),
2812 left->as_register_lo(),
2813 right->as_register_hi(),
2814 right->as_register_lo());
2815 move_regs(left->as_register_hi(), dst->as_register());
2816 #endif // _LP64
2817 }
2818 }
2819
2820
2821 void LIR_Assembler::align_call(LIR_Code code) {
2822 if (os::is_MP()) {
2823 // make sure that the displacement word of the call ends up word aligned
2824 int offset = __ offset();
2825 switch (code) {
2826 case lir_static_call:
2827 case lir_optvirtual_call:
2828 case lir_dynamic_call:
2829 offset += NativeCall::displacement_offset;
2830 break;
2831 case lir_icvirtual_call:
2832 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2833 break;
2834 case lir_virtual_call: // currently, sparc-specific for niagara
2835 default: ShouldNotReachHere();
2836 }
2837 while (offset++ % BytesPerWord != 0) {
2838 __ nop();
2839 }
2840 }
2841 }
2842
2843
2844 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2845 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2846 "must be aligned");
2847 __ call(AddressLiteral(op->addr(), rtype));
2848 add_call_info(code_offset(), op->info());
2849 }
2850
2851
2852 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2853 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2854 __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2855 assert(!os::is_MP() ||
2856 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2857 "must be aligned");
2858 __ call(AddressLiteral(op->addr(), rh));
2859 add_call_info(code_offset(), op->info());
2860 }
2861
2862
2863 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2864 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2865 ShouldNotReachHere();
2866 }
2867
2868
2869 void LIR_Assembler::emit_static_call_stub() {
2870 address call_pc = __ pc();
2871 address stub = __ start_a_stub(call_stub_size);
2872 if (stub == NULL) {
2873 bailout("static call stub overflow");
2874 return;
2875 }
2876
2877 int start = __ offset();
2878 if (os::is_MP()) {
2879 // make sure that the displacement word of the call ends up word aligned
2880 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2881 while (offset++ % BytesPerWord != 0) {
2882 __ nop();
2883 }
2884 }
2885 __ relocate(static_stub_Relocation::spec(call_pc));
2886 __ movoop(rbx, (jobject)NULL);
2887 // must be set to -1 at code generation time
2888 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2889 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2890 __ jump(RuntimeAddress(__ pc()));
2891
2892 assert(__ offset() - start <= call_stub_size, "stub too big");
2893 __ end_a_stub();
2894 }
2895
2896
2897 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2898 assert(exceptionOop->as_register() == rax, "must match");
2899 assert(exceptionPC->as_register() == rdx, "must match");
2900
2901 // exception object is not added to oop map by LinearScan
2902 // (LinearScan assumes that no oops are in fixed registers)
2903 info->add_register_oop(exceptionOop);
2904 Runtime1::StubID unwind_id;
2905
2906 // get current pc information
2907 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2908 int pc_for_athrow_offset = __ offset();
2909 InternalAddress pc_for_athrow(__ pc());
2910 __ lea(exceptionPC->as_register(), pc_for_athrow);
2911 add_call_info(pc_for_athrow_offset, info); // for exception handler
2912
2913 __ verify_not_null_oop(rax);
2914 // search an exception handler (rax: exception oop, rdx: throwing pc)
2915 if (compilation()->has_fpu_code()) {
2916 unwind_id = Runtime1::handle_exception_id;
2917 } else {
2918 unwind_id = Runtime1::handle_exception_nofpu_id;
2919 }
2920 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2921
2922 // enough room for two byte trap
2923 __ nop();
2924 }
2925
2926
2927 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2928 assert(exceptionOop->as_register() == rax, "must match");
2929
2930 __ jmp(_unwind_handler_entry);
2931 }
2932
2933
2934 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2935
2936 // optimized version for linear scan:
2937 // * count must be already in ECX (guaranteed by LinearScan)
2938 // * left and dest must be equal
2939 // * tmp must be unused
2940 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2941 assert(left == dest, "left and dest must be equal");
2942 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2943
2944 if (left->is_single_cpu()) {
2945 Register value = left->as_register();
2946 assert(value != SHIFT_count, "left cannot be ECX");
2947
2948 switch (code) {
2949 case lir_shl: __ shll(value); break;
2950 case lir_shr: __ sarl(value); break;
2951 case lir_ushr: __ shrl(value); break;
2952 default: ShouldNotReachHere();
2953 }
2954 } else if (left->is_double_cpu()) {
2955 Register lo = left->as_register_lo();
2956 Register hi = left->as_register_hi();
2957 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2958 #ifdef _LP64
2959 switch (code) {
2960 case lir_shl: __ shlptr(lo); break;
2961 case lir_shr: __ sarptr(lo); break;
2962 case lir_ushr: __ shrptr(lo); break;
2963 default: ShouldNotReachHere();
2964 }
2965 #else
2966
2967 switch (code) {
2968 case lir_shl: __ lshl(hi, lo); break;
2969 case lir_shr: __ lshr(hi, lo, true); break;
2970 case lir_ushr: __ lshr(hi, lo, false); break;
2971 default: ShouldNotReachHere();
2972 }
2973 #endif // LP64
2974 } else {
2975 ShouldNotReachHere();
2976 }
2977 }
2978
2979
2980 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2981 if (dest->is_single_cpu()) {
2982 // first move left into dest so that left is not destroyed by the shift
2983 Register value = dest->as_register();
2984 count = count & 0x1F; // Java spec
2985
2986 move_regs(left->as_register(), value);
2987 switch (code) {
2988 case lir_shl: __ shll(value, count); break;
2989 case lir_shr: __ sarl(value, count); break;
2990 case lir_ushr: __ shrl(value, count); break;
2991 default: ShouldNotReachHere();
2992 }
2993 } else if (dest->is_double_cpu()) {
2994 #ifndef _LP64
2995 Unimplemented();
2996 #else
2997 // first move left into dest so that left is not destroyed by the shift
2998 Register value = dest->as_register_lo();
2999 count = count & 0x1F; // Java spec
3000
3001 move_regs(left->as_register_lo(), value);
3002 switch (code) {
3003 case lir_shl: __ shlptr(value, count); break;
3004 case lir_shr: __ sarptr(value, count); break;
3005 case lir_ushr: __ shrptr(value, count); break;
3006 default: ShouldNotReachHere();
3007 }
3008 #endif // _LP64
3009 } else {
3010 ShouldNotReachHere();
3011 }
3012 }
3013
3014
3015 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3016 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3017 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3018 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3019 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3020 }
3021
3022
3023 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3024 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3025 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3026 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3027 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3028 }
3029
3030
3031 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3032 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3033 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3034 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3035 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3036 }
3037
3038
3039 // This code replaces a call to arraycopy; no exception may
3040 // be thrown in this code, they must be thrown in the System.arraycopy
3041 // activation frame; we could save some checks if this would not be the case
3042 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3043 ciArrayKlass* default_type = op->expected_type();
3044 Register src = op->src()->as_register();
3045 Register dst = op->dst()->as_register();
3046 Register src_pos = op->src_pos()->as_register();
3047 Register dst_pos = op->dst_pos()->as_register();
3048 Register length = op->length()->as_register();
3049 Register tmp = op->tmp()->as_register();
3050
3051 CodeStub* stub = op->stub();
3052 int flags = op->flags();
3053 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3054 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3055
3056 // if we don't know anything or it's an object array, just go through the generic arraycopy
3057 if (default_type == NULL) {
3058 Label done;
3059 // save outgoing arguments on stack in case call to System.arraycopy is needed
3060 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3061 // for interpreter calling conventions. Now we have to do it in new style conventions.
3062 // For the moment until C1 gets the new register allocator I just force all the
3063 // args to the right place (except the register args) and then on the back side
3064 // reload the register args properly if we go slow path. Yuck
3065
3066 // These are proper for the calling convention
3067
3068 store_parameter(length, 2);
3069 store_parameter(dst_pos, 1);
3070 store_parameter(dst, 0);
3071
3072 // these are just temporary placements until we need to reload
3073 store_parameter(src_pos, 3);
3074 store_parameter(src, 4);
3075 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3076
3077 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3078
3079 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3080 #ifdef _LP64
3081 // The arguments are in java calling convention so we can trivially shift them to C
3082 // convention
3083 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3084 __ mov(c_rarg0, j_rarg0);
3085 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3086 __ mov(c_rarg1, j_rarg1);
3087 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3088 __ mov(c_rarg2, j_rarg2);
3089 assert_different_registers(c_rarg3, j_rarg4);
3090 __ mov(c_rarg3, j_rarg3);
3091 #ifdef _WIN64
3092 // Allocate abi space for args but be sure to keep stack aligned
3093 __ subptr(rsp, 6*wordSize);
3094 store_parameter(j_rarg4, 4);
3095 __ call(RuntimeAddress(entry));
3096 __ addptr(rsp, 6*wordSize);
3097 #else
3098 __ mov(c_rarg4, j_rarg4);
3099 __ call(RuntimeAddress(entry));
3100 #endif // _WIN64
3101 #else
3102 __ push(length);
3103 __ push(dst_pos);
3104 __ push(dst);
3105 __ push(src_pos);
3106 __ push(src);
3107 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3108
3109 #endif // _LP64
3110
3111 __ cmpl(rax, 0);
3112 __ jcc(Assembler::equal, *stub->continuation());
3113
3114 // Reload values from the stack so they are where the stub
3115 // expects them.
3116 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3117 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3118 __ movptr (length, Address(rsp, 2*BytesPerWord));
3119 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3120 __ movptr (src, Address(rsp, 4*BytesPerWord));
3121 __ jmp(*stub->entry());
3122
3123 __ bind(*stub->continuation());
3124 return;
3125 }
3126
3127 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3128
3129 int elem_size = type2aelembytes(basic_type);
3130 int shift_amount;
3131 Address::ScaleFactor scale;
3132
3133 switch (elem_size) {
3134 case 1 :
3135 shift_amount = 0;
3136 scale = Address::times_1;
3137 break;
3138 case 2 :
3139 shift_amount = 1;
3140 scale = Address::times_2;
3141 break;
3142 case 4 :
3143 shift_amount = 2;
3144 scale = Address::times_4;
3145 break;
3146 case 8 :
3147 shift_amount = 3;
3148 scale = Address::times_8;
3149 break;
3150 default:
3151 ShouldNotReachHere();
3152 }
3153
3154 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3155 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3156 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3157 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3158
3159 // length and pos's are all sign extended at this point on 64bit
3160
3161 // test for NULL
3162 if (flags & LIR_OpArrayCopy::src_null_check) {
3163 __ testptr(src, src);
3164 __ jcc(Assembler::zero, *stub->entry());
3165 }
3166 if (flags & LIR_OpArrayCopy::dst_null_check) {
3167 __ testptr(dst, dst);
3168 __ jcc(Assembler::zero, *stub->entry());
3169 }
3170
3171 // check if negative
3172 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3173 __ testl(src_pos, src_pos);
3174 __ jcc(Assembler::less, *stub->entry());
3175 }
3176 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3177 __ testl(dst_pos, dst_pos);
3178 __ jcc(Assembler::less, *stub->entry());
3179 }
3180 if (flags & LIR_OpArrayCopy::length_positive_check) {
3181 __ testl(length, length);
3182 __ jcc(Assembler::less, *stub->entry());
3183 }
3184
3185 if (flags & LIR_OpArrayCopy::src_range_check) {
3186 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3187 __ cmpl(tmp, src_length_addr);
3188 __ jcc(Assembler::above, *stub->entry());
3189 }
3190 if (flags & LIR_OpArrayCopy::dst_range_check) {
3191 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3192 __ cmpl(tmp, dst_length_addr);
3193 __ jcc(Assembler::above, *stub->entry());
3194 }
3195
3196 if (flags & LIR_OpArrayCopy::type_check) {
3197 __ movptr(tmp, src_klass_addr);
3198 __ cmpptr(tmp, dst_klass_addr);
3199 __ jcc(Assembler::notEqual, *stub->entry());
3200 }
3201
3202 #ifdef ASSERT
3203 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3204 // Sanity check the known type with the incoming class. For the
3205 // primitive case the types must match exactly with src.klass and
3206 // dst.klass each exactly matching the default type. For the
3207 // object array case, if no type check is needed then either the
3208 // dst type is exactly the expected type and the src type is a
3209 // subtype which we can't check or src is the same array as dst
3210 // but not necessarily exactly of type default_type.
3211 Label known_ok, halt;
3212 __ movoop(tmp, default_type->constant_encoding());
3213 if (basic_type != T_OBJECT) {
3214 __ cmpptr(tmp, dst_klass_addr);
3215 __ jcc(Assembler::notEqual, halt);
3216 __ cmpptr(tmp, src_klass_addr);
3217 __ jcc(Assembler::equal, known_ok);
3218 } else {
3219 __ cmpptr(tmp, dst_klass_addr);
3220 __ jcc(Assembler::equal, known_ok);
3221 __ cmpptr(src, dst);
3222 __ jcc(Assembler::equal, known_ok);
3223 }
3224 __ bind(halt);
3225 __ stop("incorrect type information in arraycopy");
3226 __ bind(known_ok);
3227 }
3228 #endif
3229
3230 if (shift_amount > 0 && basic_type != T_OBJECT) {
3231 __ shlptr(length, shift_amount);
3232 }
3233
3234 #ifdef _LP64
3235 assert_different_registers(c_rarg0, dst, dst_pos, length);
3236 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3237 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3238 assert_different_registers(c_rarg1, length);
3239 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3240 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3241 __ mov(c_rarg2, length);
3242
3243 #else
3244 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3245 store_parameter(tmp, 0);
3246 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3247 store_parameter(tmp, 1);
3248 store_parameter(length, 2);
3249 #endif // _LP64
3250 if (basic_type == T_OBJECT) {
3251 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3252 } else {
3253 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3254 }
3255
3256 __ bind(*stub->continuation());
3257 }
3258
3259
3260 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3261 Register obj = op->obj_opr()->as_register(); // may not be an oop
3262 Register hdr = op->hdr_opr()->as_register();
3263 Register lock = op->lock_opr()->as_register();
3264 if (!UseFastLocking) {
3265 __ jmp(*op->stub()->entry());
3266 } else if (op->code() == lir_lock) {
3267 Register scratch = noreg;
3268 if (UseBiasedLocking) {
3269 scratch = op->scratch_opr()->as_register();
3270 }
3271 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3272 // add debug info for NullPointerException only if one is possible
3273 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3274 if (op->info() != NULL) {
3275 add_debug_info_for_null_check(null_check_offset, op->info());
3276 }
3277 // done
3278 } else if (op->code() == lir_unlock) {
3279 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3280 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3281 } else {
3282 Unimplemented();
3283 }
3284 __ bind(*op->stub()->continuation());
3285 }
3286
3287
3288 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3289 ciMethod* method = op->profiled_method();
3290 int bci = op->profiled_bci();
3291
3292 // Update counter for all call types
3293 ciMethodData* md = method->method_data();
3294 if (md == NULL) {
3295 bailout("out of memory building methodDataOop");
3296 return;
3297 }
3298 ciProfileData* data = md->bci_to_data(bci);
3299 assert(data->is_CounterData(), "need CounterData for calls");
3300 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3301 Register mdo = op->mdo()->as_register();
3302 __ movoop(mdo, md->constant_encoding());
3303 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3304 Bytecodes::Code bc = method->java_code_at_bci(bci);
3305 // Perform additional virtual call profiling for invokevirtual and
3306 // invokeinterface bytecodes
3307 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3308 C1ProfileVirtualCalls) {
3309 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3310 Register recv = op->recv()->as_register();
3311 assert_different_registers(mdo, recv);
3312 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3313 ciKlass* known_klass = op->known_holder();
3314 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3315 // We know the type that will be seen at this call site; we can
3316 // statically update the methodDataOop rather than needing to do
3317 // dynamic tests on the receiver type
3318
3319 // NOTE: we should probably put a lock around this search to
3320 // avoid collisions by concurrent compilations
3321 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3322 uint i;
3323 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3324 ciKlass* receiver = vc_data->receiver(i);
3325 if (known_klass->equals(receiver)) {
3326 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3327 __ addptr(data_addr, DataLayout::counter_increment);
3328 return;
3329 }
3330 }
3331
3332 // Receiver type not found in profile data; select an empty slot
3333
3334 // Note that this is less efficient than it should be because it
3335 // always does a write to the receiver part of the
3336 // VirtualCallData rather than just the first time
3337 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3338 ciKlass* receiver = vc_data->receiver(i);
3339 if (receiver == NULL) {
3340 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3341 __ movoop(recv_addr, known_klass->constant_encoding());
3342 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3343 __ addptr(data_addr, DataLayout::counter_increment);
3344 return;
3345 }
3346 }
3347 } else {
3348 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3349 Label update_done;
3350 type_profile_helper(mdo, md, data, recv, &update_done);
3351 // Receiver did not match any saved receiver and there is no empty row for it.
3352 // Increment total counter to indicate polymorphic case.
3353 __ addptr(counter_addr, DataLayout::counter_increment);
3354
3355 __ bind(update_done);
3356 }
3357 } else {
3358 // Static call
3359 __ addptr(counter_addr, DataLayout::counter_increment);
3360 }
3361 }
3362
3363 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3364 Unimplemented();
3365 }
3366
3367
3368 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3369 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3370 }
3371
3372
3373 void LIR_Assembler::align_backward_branch_target() {
3374 __ align(BytesPerWord);
3375 }
3376
3377
3378 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3379 if (left->is_single_cpu()) {
3380 __ negl(left->as_register());
3381 move_regs(left->as_register(), dest->as_register());
3382
3383 } else if (left->is_double_cpu()) {
3384 Register lo = left->as_register_lo();
3385 #ifdef _LP64
3386 Register dst = dest->as_register_lo();
3387 __ movptr(dst, lo);
3388 __ negptr(dst);
3389 #else
3390 Register hi = left->as_register_hi();
3391 __ lneg(hi, lo);
3392 if (dest->as_register_lo() == hi) {
3393 assert(dest->as_register_hi() != lo, "destroying register");
3394 move_regs(hi, dest->as_register_hi());
3395 move_regs(lo, dest->as_register_lo());
3396 } else {
3397 move_regs(lo, dest->as_register_lo());
3398 move_regs(hi, dest->as_register_hi());
3399 }
3400 #endif // _LP64
3401
3402 } else if (dest->is_single_xmm()) {
3403 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3404 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3405 }
3406 __ xorps(dest->as_xmm_float_reg(),
3407 ExternalAddress((address)float_signflip_pool));
3408
3409 } else if (dest->is_double_xmm()) {
3410 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3411 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3412 }
3413 __ xorpd(dest->as_xmm_double_reg(),
3414 ExternalAddress((address)double_signflip_pool));
3415
3416 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3417 assert(left->fpu() == 0, "arg must be on TOS");
3418 assert(dest->fpu() == 0, "dest must be TOS");
3419 __ fchs();
3420
3421 } else {
3422 ShouldNotReachHere();
3423 }
3424 }
3425
3426
3427 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3428 assert(addr->is_address() && dest->is_register(), "check");
3429 Register reg;
3430 reg = dest->as_pointer_register();
3431 __ lea(reg, as_Address(addr->as_address_ptr()));
3432 }
3433
3434
3435
3436 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3437 assert(!tmp->is_valid(), "don't need temporary");
3438 __ call(RuntimeAddress(dest));
3439 if (info != NULL) {
3440 add_call_info_here(info);
3441 }
3442 }
3443
3444
3445 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3446 assert(type == T_LONG, "only for volatile long fields");
3447
3448 if (info != NULL) {
3449 add_debug_info_for_null_check_here(info);
3450 }
3451
3452 if (src->is_double_xmm()) {
3453 if (dest->is_double_cpu()) {
3454 #ifdef _LP64
3455 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3456 #else
3457 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3458 __ psrlq(src->as_xmm_double_reg(), 32);
3459 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3460 #endif // _LP64
3461 } else if (dest->is_double_stack()) {
3462 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3463 } else if (dest->is_address()) {
3464 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3465 } else {
3466 ShouldNotReachHere();
3467 }
3468
3469 } else if (dest->is_double_xmm()) {
3470 if (src->is_double_stack()) {
3471 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3472 } else if (src->is_address()) {
3473 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3474 } else {
3475 ShouldNotReachHere();
3476 }
3477
3478 } else if (src->is_double_fpu()) {
3479 assert(src->fpu_regnrLo() == 0, "must be TOS");
3480 if (dest->is_double_stack()) {
3481 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3482 } else if (dest->is_address()) {
3483 __ fistp_d(as_Address(dest->as_address_ptr()));
3484 } else {
3485 ShouldNotReachHere();
3486 }
3487
3488 } else if (dest->is_double_fpu()) {
3489 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3490 if (src->is_double_stack()) {
3491 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3492 } else if (src->is_address()) {
3493 __ fild_d(as_Address(src->as_address_ptr()));
3494 } else {
3495 ShouldNotReachHere();
3496 }
3497 } else {
3498 ShouldNotReachHere();
3499 }
3500 }
3501
3502
3503 void LIR_Assembler::membar() {
3504 // QQQ sparc TSO uses this,
3505 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3506 }
3507
3508 void LIR_Assembler::membar_acquire() {
3509 // No x86 machines currently require load fences
3510 // __ load_fence();
3511 }
3512
3513 void LIR_Assembler::membar_release() {
3514 // No x86 machines currently require store fences
3515 // __ store_fence();
3516 }
3517
3518 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3519 assert(result_reg->is_register(), "check");
3520 #ifdef _LP64
3521 // __ get_thread(result_reg->as_register_lo());
3522 __ mov(result_reg->as_register(), r15_thread);
3523 #else
3524 __ get_thread(result_reg->as_register());
3525 #endif // _LP64
3526 }
3527
3528
3529 void LIR_Assembler::peephole(LIR_List*) {
3530 // do nothing for now
3531 }
3532
3533
3534 #undef __