1 /*
2 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP
26 #define OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP
27
28 #include "runtime/orderAccess.hpp"
29
30 // Implementation of class OrderAccess.
31
32 inline void OrderAccess::loadload() { acquire(); }
33 inline void OrderAccess::storestore() { release(); }
34 inline void OrderAccess::loadstore() { acquire(); }
35 inline void OrderAccess::storeload() { fence(); }
36
37 inline void OrderAccess::acquire() {
38 volatile intptr_t local_dummy;
39 #ifdef AMD64
40 __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
41 #else
42 __asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
43 #endif // AMD64
44 }
45
46 inline void OrderAccess::release() {
47 // Avoid hitting the same cache-line from
48 // different threads.
49 volatile jint local_dummy = 0;
50 }
51
52 inline void OrderAccess::fence() {
53 if (os::is_MP()) {
54 // always use locked addl since mfence is sometimes expensive
55 #ifdef AMD64
56 __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
57 #else
58 __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
59 #endif
60 }
61 }
62
63 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
64 inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
65 inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
66 inline jlong OrderAccess::load_acquire(volatile jlong* p) { return *p; }
67 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
68 inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
69 inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
70 inline julong OrderAccess::load_acquire(volatile julong* p) { return *p; }
71 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
72 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; }
73
74 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
75 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
76 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
77
78 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
79 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
80 inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
81 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { *p = v; }
82 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
83 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
84 inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
85 inline void OrderAccess::release_store(volatile julong* p, julong v) { *p = v; }
86 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
87 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; }
88
89 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
90 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
91
92 inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
93 __asm__ volatile ( "xchgb (%2),%0"
94 : "=r" (v)
95 : "0" (v), "r" (p)
96 : "memory");
97 }
98 inline void OrderAccess::store_fence(jshort* p, jshort v) {
99 __asm__ volatile ( "xchgw (%2),%0"
100 : "=r" (v)
101 : "0" (v), "r" (p)
102 : "memory");
103 }
104 inline void OrderAccess::store_fence(jint* p, jint v) {
105 __asm__ volatile ( "xchgl (%2),%0"
106 : "=r" (v)
107 : "0" (v), "r" (p)
108 : "memory");
109 }
110
111 inline void OrderAccess::store_fence(jlong* p, jlong v) {
112 #ifdef AMD64
113 __asm__ __volatile__ ("xchgq (%2), %0"
114 : "=r" (v)
115 : "0" (v), "r" (p)
116 : "memory");
117 #else
118 *p = v; fence();
119 #endif // AMD64
120 }
121
122 // AMD64 copied the bodies for the the signed version. 32bit did this. As long as the
123 // compiler does the inlining this is simpler.
124 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
125 inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
126 inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
127 inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
128 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
129 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
130
131 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
132 #ifdef AMD64
133 __asm__ __volatile__ ("xchgq (%2), %0"
134 : "=r" (v)
135 : "0" (v), "r" (p)
136 : "memory");
137 #else
138 store_fence((jint*)p, (jint)v);
139 #endif // AMD64
140 }
141
142 inline void OrderAccess::store_ptr_fence(void** p, void* v) {
143 #ifdef AMD64
144 __asm__ __volatile__ ("xchgq (%2), %0"
145 : "=r" (v)
146 : "0" (v), "r" (p)
147 : "memory");
148 #else
149 store_fence((jint*)p, (jint)v);
150 #endif // AMD64
151 }
152
153 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
154 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
155 __asm__ volatile ( "xchgb (%2),%0"
156 : "=r" (v)
157 : "0" (v), "r" (p)
158 : "memory");
159 }
160 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
161 __asm__ volatile ( "xchgw (%2),%0"
162 : "=r" (v)
163 : "0" (v), "r" (p)
164 : "memory");
165 }
166 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
167 __asm__ volatile ( "xchgl (%2),%0"
168 : "=r" (v)
169 : "0" (v), "r" (p)
170 : "memory");
171 }
172
173 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) {
174 #ifdef AMD64
175 __asm__ __volatile__ ( "xchgq (%2), %0"
176 : "=r" (v)
177 : "0" (v), "r" (p)
178 : "memory");
179 #else
180 *p = v; fence();
181 #endif // AMD64
182 }
183
184 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
185 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
186 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
187 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
188
189 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
190 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); }
191
192 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
193 #ifdef AMD64
194 __asm__ __volatile__ ( "xchgq (%2), %0"
195 : "=r" (v)
196 : "0" (v), "r" (p)
197 : "memory");
198 #else
199 release_store_fence((volatile jint*)p, (jint)v);
200 #endif // AMD64
201 }
202 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
203 #ifdef AMD64
204 __asm__ __volatile__ ( "xchgq (%2), %0"
205 : "=r" (v)
206 : "0" (v), "r" (p)
207 : "memory");
208 #else
209 release_store_fence((volatile jint*)p, (jint)v);
210 #endif // AMD64
211 }
212
213 #endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP