5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 // Implementation of class OrderAccess.
26
27 inline void OrderAccess::loadload() { acquire(); }
28 inline void OrderAccess::storestore() { release(); }
29 inline void OrderAccess::loadstore() { acquire(); }
30 inline void OrderAccess::storeload() { fence(); }
31
32 inline void OrderAccess::acquire() {
33 volatile intptr_t local_dummy;
34 #ifdef AMD64
35 __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
36 #else
37 __asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
38 #endif // AMD64
39 }
40
41 inline void OrderAccess::release() {
42 // Avoid hitting the same cache-line from
43 // different threads.
44 volatile jint local_dummy = 0;
187 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
188 #ifdef AMD64
189 __asm__ __volatile__ ( "xchgq (%2), %0"
190 : "=r" (v)
191 : "0" (v), "r" (p)
192 : "memory");
193 #else
194 release_store_fence((volatile jint*)p, (jint)v);
195 #endif // AMD64
196 }
197 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
198 #ifdef AMD64
199 __asm__ __volatile__ ( "xchgq (%2), %0"
200 : "=r" (v)
201 : "0" (v), "r" (p)
202 : "memory");
203 #else
204 release_store_fence((volatile jint*)p, (jint)v);
205 #endif // AMD64
206 }
|
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP
26 #define OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP
27
28 #include "runtime/orderAccess.hpp"
29
30 // Implementation of class OrderAccess.
31
32 inline void OrderAccess::loadload() { acquire(); }
33 inline void OrderAccess::storestore() { release(); }
34 inline void OrderAccess::loadstore() { acquire(); }
35 inline void OrderAccess::storeload() { fence(); }
36
37 inline void OrderAccess::acquire() {
38 volatile intptr_t local_dummy;
39 #ifdef AMD64
40 __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
41 #else
42 __asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
43 #endif // AMD64
44 }
45
46 inline void OrderAccess::release() {
47 // Avoid hitting the same cache-line from
48 // different threads.
49 volatile jint local_dummy = 0;
192 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
193 #ifdef AMD64
194 __asm__ __volatile__ ( "xchgq (%2), %0"
195 : "=r" (v)
196 : "0" (v), "r" (p)
197 : "memory");
198 #else
199 release_store_fence((volatile jint*)p, (jint)v);
200 #endif // AMD64
201 }
202 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
203 #ifdef AMD64
204 __asm__ __volatile__ ( "xchgq (%2), %0"
205 : "=r" (v)
206 : "0" (v), "r" (p)
207 : "memory");
208 #else
209 release_store_fence((volatile jint*)p, (jint)v);
210 #endif // AMD64
211 }
212
213 #endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP
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