1 /* 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 # include "incls/_precompiled.incl" 26 # include "incls/_c1_LIR.cpp.incl" 27 28 Register LIR_OprDesc::as_register() const { 29 return FrameMap::cpu_rnr2reg(cpu_regnr()); 30 } 31 32 Register LIR_OprDesc::as_register_lo() const { 33 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 34 } 35 36 Register LIR_OprDesc::as_register_hi() const { 37 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 38 } 39 40 #if defined(X86) 41 42 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 43 return FrameMap::nr2xmmreg(xmm_regnr()); 44 } 45 46 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 47 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 48 return FrameMap::nr2xmmreg(xmm_regnrLo()); 49 } 50 51 #endif // X86 52 53 #if defined(SPARC) || defined(PPC) 54 55 FloatRegister LIR_OprDesc::as_float_reg() const { 56 return FrameMap::nr2floatreg(fpu_regnr()); 57 } 58 59 FloatRegister LIR_OprDesc::as_double_reg() const { 60 return FrameMap::nr2floatreg(fpu_regnrHi()); 61 } 62 63 #endif 64 65 #ifdef ARM 66 67 FloatRegister LIR_OprDesc::as_float_reg() const { 68 return as_FloatRegister(fpu_regnr()); 69 } 70 71 FloatRegister LIR_OprDesc::as_double_reg() const { 72 return as_FloatRegister(fpu_regnrLo()); 73 } 74 75 #endif 76 77 78 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 79 80 LIR_Opr LIR_OprFact::value_type(ValueType* type) { 81 ValueTag tag = type->tag(); 82 switch (tag) { 83 case objectTag : { 84 ClassConstant* c = type->as_ClassConstant(); 85 if (c != NULL && !c->value()->is_loaded()) { 86 return LIR_OprFact::oopConst(NULL); 87 } else { 88 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 89 } 90 } 91 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 92 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 93 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 94 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 95 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 96 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 97 } 98 } 99 100 101 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 102 switch (type->tag()) { 103 case objectTag: return LIR_OprFact::oopConst(NULL); 104 case addressTag:return LIR_OprFact::addressConst(0); 105 case intTag: return LIR_OprFact::intConst(0); 106 case floatTag: return LIR_OprFact::floatConst(0.0); 107 case longTag: return LIR_OprFact::longConst(0); 108 case doubleTag: return LIR_OprFact::doubleConst(0.0); 109 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 110 } 111 return illegalOpr; 112 } 113 114 115 116 //--------------------------------------------------- 117 118 119 LIR_Address::Scale LIR_Address::scale(BasicType type) { 120 int elem_size = type2aelembytes(type); 121 switch (elem_size) { 122 case 1: return LIR_Address::times_1; 123 case 2: return LIR_Address::times_2; 124 case 4: return LIR_Address::times_4; 125 case 8: return LIR_Address::times_8; 126 } 127 ShouldNotReachHere(); 128 return LIR_Address::times_1; 129 } 130 131 132 #ifndef PRODUCT 133 void LIR_Address::verify() const { 134 #if defined(SPARC) || defined(PPC) 135 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 136 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 137 #endif 138 #ifdef ARM 139 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 140 assert(-4096 < disp() && disp() < 4096, "architecture constraint"); 141 #endif 142 #ifdef _LP64 143 assert(base()->is_cpu_register(), "wrong base operand"); 144 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 145 assert(base()->type() == T_OBJECT || base()->type() == T_LONG, 146 "wrong type for addresses"); 147 #else 148 assert(base()->is_single_cpu(), "wrong base operand"); 149 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 150 assert(base()->type() == T_OBJECT || base()->type() == T_INT, 151 "wrong type for addresses"); 152 #endif 153 } 154 #endif 155 156 157 //--------------------------------------------------- 158 159 char LIR_OprDesc::type_char(BasicType t) { 160 switch (t) { 161 case T_ARRAY: 162 t = T_OBJECT; 163 case T_BOOLEAN: 164 case T_CHAR: 165 case T_FLOAT: 166 case T_DOUBLE: 167 case T_BYTE: 168 case T_SHORT: 169 case T_INT: 170 case T_LONG: 171 case T_OBJECT: 172 case T_ADDRESS: 173 case T_VOID: 174 return ::type2char(t); 175 176 case T_ILLEGAL: 177 return '?'; 178 179 default: 180 ShouldNotReachHere(); 181 return '?'; 182 } 183 } 184 185 #ifndef PRODUCT 186 void LIR_OprDesc::validate_type() const { 187 188 #ifdef ASSERT 189 if (!is_pointer() && !is_illegal()) { 190 switch (as_BasicType(type_field())) { 191 case T_LONG: 192 assert((kind_field() == cpu_register || kind_field() == stack_value) && 193 size_field() == double_size, "must match"); 194 break; 195 case T_FLOAT: 196 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 197 assert((kind_field() == fpu_register || kind_field() == stack_value 198 ARM_ONLY(|| kind_field() == cpu_register) 199 PPC_ONLY(|| kind_field() == cpu_register) ) && 200 size_field() == single_size, "must match"); 201 break; 202 case T_DOUBLE: 203 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 204 assert((kind_field() == fpu_register || kind_field() == stack_value 205 ARM_ONLY(|| kind_field() == cpu_register) 206 PPC_ONLY(|| kind_field() == cpu_register) ) && 207 size_field() == double_size, "must match"); 208 break; 209 case T_BOOLEAN: 210 case T_CHAR: 211 case T_BYTE: 212 case T_SHORT: 213 case T_INT: 214 case T_OBJECT: 215 case T_ARRAY: 216 assert((kind_field() == cpu_register || kind_field() == stack_value) && 217 size_field() == single_size, "must match"); 218 break; 219 220 case T_ILLEGAL: 221 // XXX TKR also means unknown right now 222 // assert(is_illegal(), "must match"); 223 break; 224 225 default: 226 ShouldNotReachHere(); 227 } 228 } 229 #endif 230 231 } 232 #endif // PRODUCT 233 234 235 bool LIR_OprDesc::is_oop() const { 236 if (is_pointer()) { 237 return pointer()->is_oop_pointer(); 238 } else { 239 OprType t= type_field(); 240 assert(t != unknown_type, "not set"); 241 return t == object_type; 242 } 243 } 244 245 246 247 void LIR_Op2::verify() const { 248 #ifdef ASSERT 249 switch (code()) { 250 case lir_cmove: 251 break; 252 253 default: 254 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 255 "can't produce oops from arith"); 256 } 257 258 if (TwoOperandLIRForm) { 259 switch (code()) { 260 case lir_add: 261 case lir_sub: 262 case lir_mul: 263 case lir_mul_strictfp: 264 case lir_div: 265 case lir_div_strictfp: 266 case lir_rem: 267 case lir_logic_and: 268 case lir_logic_or: 269 case lir_logic_xor: 270 case lir_shl: 271 case lir_shr: 272 assert(in_opr1() == result_opr(), "opr1 and result must match"); 273 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 274 break; 275 276 // special handling for lir_ushr because of write barriers 277 case lir_ushr: 278 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 279 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 280 break; 281 282 } 283 } 284 #endif 285 } 286 287 288 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 289 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 290 , _cond(cond) 291 , _type(type) 292 , _label(block->label()) 293 , _block(block) 294 , _ublock(NULL) 295 , _stub(NULL) { 296 } 297 298 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 299 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 300 , _cond(cond) 301 , _type(type) 302 , _label(stub->entry()) 303 , _block(NULL) 304 , _ublock(NULL) 305 , _stub(stub) { 306 } 307 308 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 309 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 310 , _cond(cond) 311 , _type(type) 312 , _label(block->label()) 313 , _block(block) 314 , _ublock(ublock) 315 , _stub(NULL) 316 { 317 } 318 319 void LIR_OpBranch::change_block(BlockBegin* b) { 320 assert(_block != NULL, "must have old block"); 321 assert(_block->label() == label(), "must be equal"); 322 323 _block = b; 324 _label = b->label(); 325 } 326 327 void LIR_OpBranch::change_ublock(BlockBegin* b) { 328 assert(_ublock != NULL, "must have old block"); 329 _ublock = b; 330 } 331 332 void LIR_OpBranch::negate_cond() { 333 switch (_cond) { 334 case lir_cond_equal: _cond = lir_cond_notEqual; break; 335 case lir_cond_notEqual: _cond = lir_cond_equal; break; 336 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 337 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 338 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 339 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 340 default: ShouldNotReachHere(); 341 } 342 } 343 344 345 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 346 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 347 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 348 CodeStub* stub) 349 350 : LIR_Op(code, result, NULL) 351 , _object(object) 352 , _array(LIR_OprFact::illegalOpr) 353 , _klass(klass) 354 , _tmp1(tmp1) 355 , _tmp2(tmp2) 356 , _tmp3(tmp3) 357 , _fast_check(fast_check) 358 , _stub(stub) 359 , _info_for_patch(info_for_patch) 360 , _info_for_exception(info_for_exception) 361 , _profiled_method(NULL) 362 , _profiled_bci(-1) 363 , _should_profile(false) 364 { 365 if (code == lir_checkcast) { 366 assert(info_for_exception != NULL, "checkcast throws exceptions"); 367 } else if (code == lir_instanceof) { 368 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 369 } else { 370 ShouldNotReachHere(); 371 } 372 } 373 374 375 376 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) 377 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 378 , _object(object) 379 , _array(array) 380 , _klass(NULL) 381 , _tmp1(tmp1) 382 , _tmp2(tmp2) 383 , _tmp3(tmp3) 384 , _fast_check(false) 385 , _stub(NULL) 386 , _info_for_patch(NULL) 387 , _info_for_exception(info_for_exception) 388 , _profiled_method(NULL) 389 , _profiled_bci(-1) 390 , _should_profile(false) 391 { 392 if (code == lir_store_check) { 393 _stub = new ArrayStoreExceptionStub(info_for_exception); 394 assert(info_for_exception != NULL, "store_check throws exceptions"); 395 } else { 396 ShouldNotReachHere(); 397 } 398 } 399 400 401 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 402 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 403 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 404 , _tmp(tmp) 405 , _src(src) 406 , _src_pos(src_pos) 407 , _dst(dst) 408 , _dst_pos(dst_pos) 409 , _flags(flags) 410 , _expected_type(expected_type) 411 , _length(length) { 412 _stub = new ArrayCopyStub(this); 413 } 414 415 416 //-------------------verify-------------------------- 417 418 void LIR_Op1::verify() const { 419 switch(code()) { 420 case lir_move: 421 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 422 break; 423 case lir_null_check: 424 assert(in_opr()->is_register(), "must be"); 425 break; 426 case lir_return: 427 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 428 break; 429 } 430 } 431 432 void LIR_OpRTCall::verify() const { 433 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 434 } 435 436 //-------------------visits-------------------------- 437 438 // complete rework of LIR instruction visitor. 439 // The virtual calls for each instruction type is replaced by a big 440 // switch that adds the operands for each instruction 441 442 void LIR_OpVisitState::visit(LIR_Op* op) { 443 // copy information from the LIR_Op 444 reset(); 445 set_op(op); 446 447 switch (op->code()) { 448 449 // LIR_Op0 450 case lir_word_align: // result and info always invalid 451 case lir_backwardbranch_target: // result and info always invalid 452 case lir_build_frame: // result and info always invalid 453 case lir_fpop_raw: // result and info always invalid 454 case lir_24bit_FPU: // result and info always invalid 455 case lir_reset_FPU: // result and info always invalid 456 case lir_breakpoint: // result and info always invalid 457 case lir_membar: // result and info always invalid 458 case lir_membar_acquire: // result and info always invalid 459 case lir_membar_release: // result and info always invalid 460 { 461 assert(op->as_Op0() != NULL, "must be"); 462 assert(op->_info == NULL, "info not used by this instruction"); 463 assert(op->_result->is_illegal(), "not used"); 464 break; 465 } 466 467 case lir_nop: // may have info, result always invalid 468 case lir_std_entry: // may have result, info always invalid 469 case lir_osr_entry: // may have result, info always invalid 470 case lir_get_thread: // may have result, info always invalid 471 { 472 assert(op->as_Op0() != NULL, "must be"); 473 if (op->_info != NULL) do_info(op->_info); 474 if (op->_result->is_valid()) do_output(op->_result); 475 break; 476 } 477 478 479 // LIR_OpLabel 480 case lir_label: // result and info always invalid 481 { 482 assert(op->as_OpLabel() != NULL, "must be"); 483 assert(op->_info == NULL, "info not used by this instruction"); 484 assert(op->_result->is_illegal(), "not used"); 485 break; 486 } 487 488 489 // LIR_Op1 490 case lir_fxch: // input always valid, result and info always invalid 491 case lir_fld: // input always valid, result and info always invalid 492 case lir_ffree: // input always valid, result and info always invalid 493 case lir_push: // input always valid, result and info always invalid 494 case lir_pop: // input always valid, result and info always invalid 495 case lir_return: // input always valid, result and info always invalid 496 case lir_leal: // input and result always valid, info always invalid 497 case lir_neg: // input and result always valid, info always invalid 498 case lir_monaddr: // input and result always valid, info always invalid 499 case lir_null_check: // input and info always valid, result always invalid 500 case lir_move: // input and result always valid, may have info 501 case lir_pack64: // input and result always valid 502 case lir_unpack64: // input and result always valid 503 case lir_prefetchr: // input always valid, result and info always invalid 504 case lir_prefetchw: // input always valid, result and info always invalid 505 { 506 assert(op->as_Op1() != NULL, "must be"); 507 LIR_Op1* op1 = (LIR_Op1*)op; 508 509 if (op1->_info) do_info(op1->_info); 510 if (op1->_opr->is_valid()) do_input(op1->_opr); 511 if (op1->_result->is_valid()) do_output(op1->_result); 512 513 break; 514 } 515 516 case lir_safepoint: 517 { 518 assert(op->as_Op1() != NULL, "must be"); 519 LIR_Op1* op1 = (LIR_Op1*)op; 520 521 assert(op1->_info != NULL, ""); do_info(op1->_info); 522 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 523 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 524 525 break; 526 } 527 528 // LIR_OpConvert; 529 case lir_convert: // input and result always valid, info always invalid 530 { 531 assert(op->as_OpConvert() != NULL, "must be"); 532 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 533 534 assert(opConvert->_info == NULL, "must be"); 535 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 536 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 537 #ifdef PPC 538 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); 539 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); 540 #endif 541 do_stub(opConvert->_stub); 542 543 break; 544 } 545 546 // LIR_OpBranch; 547 case lir_branch: // may have info, input and result register always invalid 548 case lir_cond_float_branch: // may have info, input and result register always invalid 549 { 550 assert(op->as_OpBranch() != NULL, "must be"); 551 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 552 553 if (opBranch->_info != NULL) do_info(opBranch->_info); 554 assert(opBranch->_result->is_illegal(), "not used"); 555 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 556 557 break; 558 } 559 560 561 // LIR_OpAllocObj 562 case lir_alloc_object: 563 { 564 assert(op->as_OpAllocObj() != NULL, "must be"); 565 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 566 567 if (opAllocObj->_info) do_info(opAllocObj->_info); 568 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); 569 do_temp(opAllocObj->_opr); 570 } 571 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 572 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 573 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 574 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 575 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 576 do_stub(opAllocObj->_stub); 577 break; 578 } 579 580 581 // LIR_OpRoundFP; 582 case lir_roundfp: { 583 assert(op->as_OpRoundFP() != NULL, "must be"); 584 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 585 586 assert(op->_info == NULL, "info not used by this instruction"); 587 assert(opRoundFP->_tmp->is_illegal(), "not used"); 588 do_input(opRoundFP->_opr); 589 do_output(opRoundFP->_result); 590 591 break; 592 } 593 594 595 // LIR_Op2 596 case lir_cmp: 597 case lir_cmp_l2i: 598 case lir_ucmp_fd2i: 599 case lir_cmp_fd2i: 600 case lir_add: 601 case lir_sub: 602 case lir_mul: 603 case lir_div: 604 case lir_rem: 605 case lir_sqrt: 606 case lir_abs: 607 case lir_logic_and: 608 case lir_logic_or: 609 case lir_logic_xor: 610 case lir_shl: 611 case lir_shr: 612 case lir_ushr: 613 { 614 assert(op->as_Op2() != NULL, "must be"); 615 LIR_Op2* op2 = (LIR_Op2*)op; 616 617 if (op2->_info) do_info(op2->_info); 618 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 619 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 620 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); 621 if (op2->_result->is_valid()) do_output(op2->_result); 622 623 break; 624 } 625 626 // special handling for cmove: right input operand must not be equal 627 // to the result operand, otherwise the backend fails 628 case lir_cmove: 629 { 630 assert(op->as_Op2() != NULL, "must be"); 631 LIR_Op2* op2 = (LIR_Op2*)op; 632 633 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used"); 634 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 635 636 do_input(op2->_opr1); 637 do_input(op2->_opr2); 638 do_temp(op2->_opr2); 639 do_output(op2->_result); 640 641 break; 642 } 643 644 // vspecial handling for strict operations: register input operands 645 // as temp to guarantee that they do not overlap with other 646 // registers 647 case lir_mul_strictfp: 648 case lir_div_strictfp: 649 { 650 assert(op->as_Op2() != NULL, "must be"); 651 LIR_Op2* op2 = (LIR_Op2*)op; 652 653 assert(op2->_info == NULL, "not used"); 654 assert(op2->_opr1->is_valid(), "used"); 655 assert(op2->_opr2->is_valid(), "used"); 656 assert(op2->_result->is_valid(), "used"); 657 658 do_input(op2->_opr1); do_temp(op2->_opr1); 659 do_input(op2->_opr2); do_temp(op2->_opr2); 660 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); 661 do_output(op2->_result); 662 663 break; 664 } 665 666 case lir_throw: { 667 assert(op->as_Op2() != NULL, "must be"); 668 LIR_Op2* op2 = (LIR_Op2*)op; 669 670 if (op2->_info) do_info(op2->_info); 671 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 672 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 673 assert(op2->_result->is_illegal(), "no result"); 674 675 break; 676 } 677 678 case lir_unwind: { 679 assert(op->as_Op1() != NULL, "must be"); 680 LIR_Op1* op1 = (LIR_Op1*)op; 681 682 assert(op1->_info == NULL, "no info"); 683 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 684 assert(op1->_result->is_illegal(), "no result"); 685 686 break; 687 } 688 689 690 case lir_tan: 691 case lir_sin: 692 case lir_cos: 693 case lir_log: 694 case lir_log10: { 695 assert(op->as_Op2() != NULL, "must be"); 696 LIR_Op2* op2 = (LIR_Op2*)op; 697 698 // On x86 tan/sin/cos need two temporary fpu stack slots and 699 // log/log10 need one so handle opr2 and tmp as temp inputs. 700 // Register input operand as temp to guarantee that it doesn't 701 // overlap with the input. 702 assert(op2->_info == NULL, "not used"); 703 assert(op2->_opr1->is_valid(), "used"); 704 do_input(op2->_opr1); do_temp(op2->_opr1); 705 706 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 707 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); 708 if (op2->_result->is_valid()) do_output(op2->_result); 709 710 break; 711 } 712 713 714 // LIR_Op3 715 case lir_idiv: 716 case lir_irem: { 717 assert(op->as_Op3() != NULL, "must be"); 718 LIR_Op3* op3= (LIR_Op3*)op; 719 720 if (op3->_info) do_info(op3->_info); 721 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 722 723 // second operand is input and temp, so ensure that second operand 724 // and third operand get not the same register 725 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 726 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 727 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 728 729 if (op3->_result->is_valid()) do_output(op3->_result); 730 731 break; 732 } 733 734 735 // LIR_OpJavaCall 736 case lir_static_call: 737 case lir_optvirtual_call: 738 case lir_icvirtual_call: 739 case lir_virtual_call: 740 case lir_dynamic_call: { 741 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 742 assert(opJavaCall != NULL, "must be"); 743 744 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 745 746 // only visit register parameters 747 int n = opJavaCall->_arguments->length(); 748 for (int i = 0; i < n; i++) { 749 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 750 do_input(*opJavaCall->_arguments->adr_at(i)); 751 } 752 } 753 754 if (opJavaCall->_info) do_info(opJavaCall->_info); 755 if (opJavaCall->is_method_handle_invoke()) { 756 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); 757 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); 758 } 759 do_call(); 760 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 761 762 break; 763 } 764 765 766 // LIR_OpRTCall 767 case lir_rtcall: { 768 assert(op->as_OpRTCall() != NULL, "must be"); 769 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 770 771 // only visit register parameters 772 int n = opRTCall->_arguments->length(); 773 for (int i = 0; i < n; i++) { 774 if (!opRTCall->_arguments->at(i)->is_pointer()) { 775 do_input(*opRTCall->_arguments->adr_at(i)); 776 } 777 } 778 if (opRTCall->_info) do_info(opRTCall->_info); 779 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 780 do_call(); 781 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 782 783 break; 784 } 785 786 787 // LIR_OpArrayCopy 788 case lir_arraycopy: { 789 assert(op->as_OpArrayCopy() != NULL, "must be"); 790 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 791 792 assert(opArrayCopy->_result->is_illegal(), "unused"); 793 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 794 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 795 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 796 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 797 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 798 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 799 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 800 801 // the implementation of arraycopy always has a call into the runtime 802 do_call(); 803 804 break; 805 } 806 807 808 // LIR_OpLock 809 case lir_lock: 810 case lir_unlock: { 811 assert(op->as_OpLock() != NULL, "must be"); 812 LIR_OpLock* opLock = (LIR_OpLock*)op; 813 814 if (opLock->_info) do_info(opLock->_info); 815 816 // TODO: check if these operands really have to be temp 817 // (or if input is sufficient). This may have influence on the oop map! 818 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 819 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 820 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 821 822 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 823 assert(opLock->_result->is_illegal(), "unused"); 824 825 do_stub(opLock->_stub); 826 827 break; 828 } 829 830 831 // LIR_OpDelay 832 case lir_delay_slot: { 833 assert(op->as_OpDelay() != NULL, "must be"); 834 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 835 836 visit(opDelay->delay_op()); 837 break; 838 } 839 840 // LIR_OpTypeCheck 841 case lir_instanceof: 842 case lir_checkcast: 843 case lir_store_check: { 844 assert(op->as_OpTypeCheck() != NULL, "must be"); 845 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 846 847 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 848 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 849 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 850 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 851 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 852 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 853 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 854 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 855 do_stub(opTypeCheck->_stub); 856 break; 857 } 858 859 // LIR_OpCompareAndSwap 860 case lir_cas_long: 861 case lir_cas_obj: 862 case lir_cas_int: { 863 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 864 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 865 866 assert(opCompareAndSwap->_addr->is_valid(), "used"); 867 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); 868 assert(opCompareAndSwap->_new_value->is_valid(), "used"); 869 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 870 do_input(opCompareAndSwap->_addr); 871 do_temp(opCompareAndSwap->_addr); 872 do_input(opCompareAndSwap->_cmp_value); 873 do_temp(opCompareAndSwap->_cmp_value); 874 do_input(opCompareAndSwap->_new_value); 875 do_temp(opCompareAndSwap->_new_value); 876 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 877 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 878 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 879 880 break; 881 } 882 883 884 // LIR_OpAllocArray; 885 case lir_alloc_array: { 886 assert(op->as_OpAllocArray() != NULL, "must be"); 887 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 888 889 if (opAllocArray->_info) do_info(opAllocArray->_info); 890 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 891 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 892 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 893 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 894 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 895 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 896 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 897 do_stub(opAllocArray->_stub); 898 break; 899 } 900 901 // LIR_OpProfileCall: 902 case lir_profile_call: { 903 assert(op->as_OpProfileCall() != NULL, "must be"); 904 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 905 906 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 907 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 908 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 909 break; 910 } 911 default: 912 ShouldNotReachHere(); 913 } 914 } 915 916 917 void LIR_OpVisitState::do_stub(CodeStub* stub) { 918 if (stub != NULL) { 919 stub->visit(this); 920 } 921 } 922 923 XHandlers* LIR_OpVisitState::all_xhandler() { 924 XHandlers* result = NULL; 925 926 int i; 927 for (i = 0; i < info_count(); i++) { 928 if (info_at(i)->exception_handlers() != NULL) { 929 result = info_at(i)->exception_handlers(); 930 break; 931 } 932 } 933 934 #ifdef ASSERT 935 for (i = 0; i < info_count(); i++) { 936 assert(info_at(i)->exception_handlers() == NULL || 937 info_at(i)->exception_handlers() == result, 938 "only one xhandler list allowed per LIR-operation"); 939 } 940 #endif 941 942 if (result != NULL) { 943 return result; 944 } else { 945 return new XHandlers(); 946 } 947 948 return result; 949 } 950 951 952 #ifdef ASSERT 953 bool LIR_OpVisitState::no_operands(LIR_Op* op) { 954 visit(op); 955 956 return opr_count(inputMode) == 0 && 957 opr_count(outputMode) == 0 && 958 opr_count(tempMode) == 0 && 959 info_count() == 0 && 960 !has_call() && 961 !has_slow_case(); 962 } 963 #endif 964 965 //--------------------------------------------------- 966 967 968 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 969 masm->emit_call(this); 970 } 971 972 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 973 masm->emit_rtcall(this); 974 } 975 976 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 977 masm->emit_opLabel(this); 978 } 979 980 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 981 masm->emit_arraycopy(this); 982 masm->emit_code_stub(stub()); 983 } 984 985 void LIR_Op0::emit_code(LIR_Assembler* masm) { 986 masm->emit_op0(this); 987 } 988 989 void LIR_Op1::emit_code(LIR_Assembler* masm) { 990 masm->emit_op1(this); 991 } 992 993 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 994 masm->emit_alloc_obj(this); 995 masm->emit_code_stub(stub()); 996 } 997 998 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 999 masm->emit_opBranch(this); 1000 if (stub()) { 1001 masm->emit_code_stub(stub()); 1002 } 1003 } 1004 1005 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 1006 masm->emit_opConvert(this); 1007 if (stub() != NULL) { 1008 masm->emit_code_stub(stub()); 1009 } 1010 } 1011 1012 void LIR_Op2::emit_code(LIR_Assembler* masm) { 1013 masm->emit_op2(this); 1014 } 1015 1016 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 1017 masm->emit_alloc_array(this); 1018 masm->emit_code_stub(stub()); 1019 } 1020 1021 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 1022 masm->emit_opTypeCheck(this); 1023 if (stub()) { 1024 masm->emit_code_stub(stub()); 1025 } 1026 } 1027 1028 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 1029 masm->emit_compare_and_swap(this); 1030 } 1031 1032 void LIR_Op3::emit_code(LIR_Assembler* masm) { 1033 masm->emit_op3(this); 1034 } 1035 1036 void LIR_OpLock::emit_code(LIR_Assembler* masm) { 1037 masm->emit_lock(this); 1038 if (stub()) { 1039 masm->emit_code_stub(stub()); 1040 } 1041 } 1042 1043 1044 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1045 masm->emit_delay(this); 1046 } 1047 1048 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1049 masm->emit_profile_call(this); 1050 } 1051 1052 // LIR_List 1053 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1054 : _operations(8) 1055 , _compilation(compilation) 1056 #ifndef PRODUCT 1057 , _block(block) 1058 #endif 1059 #ifdef ASSERT 1060 , _file(NULL) 1061 , _line(0) 1062 #endif 1063 { } 1064 1065 1066 #ifdef ASSERT 1067 void LIR_List::set_file_and_line(const char * file, int line) { 1068 const char * f = strrchr(file, '/'); 1069 if (f == NULL) f = strrchr(file, '\\'); 1070 if (f == NULL) { 1071 f = file; 1072 } else { 1073 f++; 1074 } 1075 _file = f; 1076 _line = line; 1077 } 1078 #endif 1079 1080 1081 void LIR_List::append(LIR_InsertionBuffer* buffer) { 1082 assert(this == buffer->lir_list(), "wrong lir list"); 1083 const int n = _operations.length(); 1084 1085 if (buffer->number_of_ops() > 0) { 1086 // increase size of instructions list 1087 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1088 // insert ops from buffer into instructions list 1089 int op_index = buffer->number_of_ops() - 1; 1090 int ip_index = buffer->number_of_insertion_points() - 1; 1091 int from_index = n - 1; 1092 int to_index = _operations.length() - 1; 1093 for (; ip_index >= 0; ip_index --) { 1094 int index = buffer->index_at(ip_index); 1095 // make room after insertion point 1096 while (index < from_index) { 1097 _operations.at_put(to_index --, _operations.at(from_index --)); 1098 } 1099 // insert ops from buffer 1100 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1101 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1102 } 1103 } 1104 } 1105 1106 buffer->finish(); 1107 } 1108 1109 1110 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1111 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1112 } 1113 1114 1115 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1116 append(new LIR_Op1( 1117 lir_move, 1118 LIR_OprFact::address(addr), 1119 src, 1120 addr->type(), 1121 patch_code, 1122 info)); 1123 } 1124 1125 1126 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1127 append(new LIR_Op1( 1128 lir_move, 1129 LIR_OprFact::address(address), 1130 dst, 1131 address->type(), 1132 patch_code, 1133 info, lir_move_volatile)); 1134 } 1135 1136 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1137 append(new LIR_Op1( 1138 lir_move, 1139 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1140 dst, 1141 type, 1142 patch_code, 1143 info, lir_move_volatile)); 1144 } 1145 1146 1147 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { 1148 append(new LIR_Op1( 1149 is_store ? lir_prefetchw : lir_prefetchr, 1150 LIR_OprFact::address(addr))); 1151 } 1152 1153 1154 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1155 append(new LIR_Op1( 1156 lir_move, 1157 LIR_OprFact::intConst(v), 1158 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1159 type, 1160 patch_code, 1161 info)); 1162 } 1163 1164 1165 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1166 append(new LIR_Op1( 1167 lir_move, 1168 LIR_OprFact::oopConst(o), 1169 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1170 type, 1171 patch_code, 1172 info)); 1173 } 1174 1175 1176 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1177 append(new LIR_Op1( 1178 lir_move, 1179 src, 1180 LIR_OprFact::address(addr), 1181 addr->type(), 1182 patch_code, 1183 info)); 1184 } 1185 1186 1187 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1188 append(new LIR_Op1( 1189 lir_move, 1190 src, 1191 LIR_OprFact::address(addr), 1192 addr->type(), 1193 patch_code, 1194 info, 1195 lir_move_volatile)); 1196 } 1197 1198 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1199 append(new LIR_Op1( 1200 lir_move, 1201 src, 1202 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1203 type, 1204 patch_code, 1205 info, lir_move_volatile)); 1206 } 1207 1208 1209 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1210 append(new LIR_Op3( 1211 lir_idiv, 1212 left, 1213 right, 1214 tmp, 1215 res, 1216 info)); 1217 } 1218 1219 1220 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1221 append(new LIR_Op3( 1222 lir_idiv, 1223 left, 1224 LIR_OprFact::intConst(right), 1225 tmp, 1226 res, 1227 info)); 1228 } 1229 1230 1231 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1232 append(new LIR_Op3( 1233 lir_irem, 1234 left, 1235 right, 1236 tmp, 1237 res, 1238 info)); 1239 } 1240 1241 1242 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1243 append(new LIR_Op3( 1244 lir_irem, 1245 left, 1246 LIR_OprFact::intConst(right), 1247 tmp, 1248 res, 1249 info)); 1250 } 1251 1252 1253 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1254 append(new LIR_Op2( 1255 lir_cmp, 1256 condition, 1257 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1258 LIR_OprFact::intConst(c), 1259 info)); 1260 } 1261 1262 1263 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1264 append(new LIR_Op2( 1265 lir_cmp, 1266 condition, 1267 reg, 1268 LIR_OprFact::address(addr), 1269 info)); 1270 } 1271 1272 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1273 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1274 append(new LIR_OpAllocObj( 1275 klass, 1276 dst, 1277 t1, 1278 t2, 1279 t3, 1280 t4, 1281 header_size, 1282 object_size, 1283 init_check, 1284 stub)); 1285 } 1286 1287 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1288 append(new LIR_OpAllocArray( 1289 klass, 1290 len, 1291 dst, 1292 t1, 1293 t2, 1294 t3, 1295 t4, 1296 type, 1297 stub)); 1298 } 1299 1300 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1301 append(new LIR_Op2( 1302 lir_shl, 1303 value, 1304 count, 1305 dst, 1306 tmp)); 1307 } 1308 1309 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1310 append(new LIR_Op2( 1311 lir_shr, 1312 value, 1313 count, 1314 dst, 1315 tmp)); 1316 } 1317 1318 1319 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1320 append(new LIR_Op2( 1321 lir_ushr, 1322 value, 1323 count, 1324 dst, 1325 tmp)); 1326 } 1327 1328 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1329 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1330 left, 1331 right, 1332 dst)); 1333 } 1334 1335 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1336 append(new LIR_OpLock( 1337 lir_lock, 1338 hdr, 1339 obj, 1340 lock, 1341 scratch, 1342 stub, 1343 info)); 1344 } 1345 1346 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { 1347 append(new LIR_OpLock( 1348 lir_unlock, 1349 hdr, 1350 obj, 1351 lock, 1352 scratch, 1353 stub, 1354 NULL)); 1355 } 1356 1357 1358 void check_LIR() { 1359 // cannot do the proper checking as PRODUCT and other modes return different results 1360 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1361 } 1362 1363 1364 1365 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1366 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1367 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1368 ciMethod* profiled_method, int profiled_bci) { 1369 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1370 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); 1371 if (profiled_method != NULL) { 1372 c->set_profiled_method(profiled_method); 1373 c->set_profiled_bci(profiled_bci); 1374 c->set_should_profile(true); 1375 } 1376 append(c); 1377 } 1378 1379 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { 1380 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); 1381 if (profiled_method != NULL) { 1382 c->set_profiled_method(profiled_method); 1383 c->set_profiled_bci(profiled_bci); 1384 c->set_should_profile(true); 1385 } 1386 append(c); 1387 } 1388 1389 1390 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) { 1391 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception)); 1392 } 1393 1394 1395 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1396 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1397 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1398 } 1399 1400 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1401 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1402 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); 1403 } 1404 1405 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1406 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1407 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1408 } 1409 1410 1411 #ifdef PRODUCT 1412 1413 void print_LIR(BlockList* blocks) { 1414 } 1415 1416 #else 1417 // LIR_OprDesc 1418 void LIR_OprDesc::print() const { 1419 print(tty); 1420 } 1421 1422 void LIR_OprDesc::print(outputStream* out) const { 1423 if (is_illegal()) { 1424 return; 1425 } 1426 1427 out->print("["); 1428 if (is_pointer()) { 1429 pointer()->print_value_on(out); 1430 } else if (is_single_stack()) { 1431 out->print("stack:%d", single_stack_ix()); 1432 } else if (is_double_stack()) { 1433 out->print("dbl_stack:%d",double_stack_ix()); 1434 } else if (is_virtual()) { 1435 out->print("R%d", vreg_number()); 1436 } else if (is_single_cpu()) { 1437 out->print(as_register()->name()); 1438 } else if (is_double_cpu()) { 1439 out->print(as_register_hi()->name()); 1440 out->print(as_register_lo()->name()); 1441 #if defined(X86) 1442 } else if (is_single_xmm()) { 1443 out->print(as_xmm_float_reg()->name()); 1444 } else if (is_double_xmm()) { 1445 out->print(as_xmm_double_reg()->name()); 1446 } else if (is_single_fpu()) { 1447 out->print("fpu%d", fpu_regnr()); 1448 } else if (is_double_fpu()) { 1449 out->print("fpu%d", fpu_regnrLo()); 1450 #elif defined(ARM) 1451 } else if (is_single_fpu()) { 1452 out->print("s%d", fpu_regnr()); 1453 } else if (is_double_fpu()) { 1454 out->print("d%d", fpu_regnrLo() >> 1); 1455 #else 1456 } else if (is_single_fpu()) { 1457 out->print(as_float_reg()->name()); 1458 } else if (is_double_fpu()) { 1459 out->print(as_double_reg()->name()); 1460 #endif 1461 1462 } else if (is_illegal()) { 1463 out->print("-"); 1464 } else { 1465 out->print("Unknown Operand"); 1466 } 1467 if (!is_illegal()) { 1468 out->print("|%c", type_char()); 1469 } 1470 if (is_register() && is_last_use()) { 1471 out->print("(last_use)"); 1472 } 1473 out->print("]"); 1474 } 1475 1476 1477 // LIR_Address 1478 void LIR_Const::print_value_on(outputStream* out) const { 1479 switch (type()) { 1480 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1481 case T_INT: out->print("int:%d", as_jint()); break; 1482 case T_LONG: out->print("lng:%lld", as_jlong()); break; 1483 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1484 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1485 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break; 1486 default: out->print("%3d:0x%x",type(), as_jdouble()); break; 1487 } 1488 } 1489 1490 // LIR_Address 1491 void LIR_Address::print_value_on(outputStream* out) const { 1492 out->print("Base:"); _base->print(out); 1493 if (!_index->is_illegal()) { 1494 out->print(" Index:"); _index->print(out); 1495 switch (scale()) { 1496 case times_1: break; 1497 case times_2: out->print(" * 2"); break; 1498 case times_4: out->print(" * 4"); break; 1499 case times_8: out->print(" * 8"); break; 1500 } 1501 } 1502 out->print(" Disp: %d", _disp); 1503 } 1504 1505 // debug output of block header without InstructionPrinter 1506 // (because phi functions are not necessary for LIR) 1507 static void print_block(BlockBegin* x) { 1508 // print block id 1509 BlockEnd* end = x->end(); 1510 tty->print("B%d ", x->block_id()); 1511 1512 // print flags 1513 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1514 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1515 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1516 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1517 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1518 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1519 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1520 1521 // print block bci range 1522 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->bci())); 1523 1524 // print predecessors and successors 1525 if (x->number_of_preds() > 0) { 1526 tty->print("preds: "); 1527 for (int i = 0; i < x->number_of_preds(); i ++) { 1528 tty->print("B%d ", x->pred_at(i)->block_id()); 1529 } 1530 } 1531 1532 if (x->number_of_sux() > 0) { 1533 tty->print("sux: "); 1534 for (int i = 0; i < x->number_of_sux(); i ++) { 1535 tty->print("B%d ", x->sux_at(i)->block_id()); 1536 } 1537 } 1538 1539 // print exception handlers 1540 if (x->number_of_exception_handlers() > 0) { 1541 tty->print("xhandler: "); 1542 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1543 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1544 } 1545 } 1546 1547 tty->cr(); 1548 } 1549 1550 void print_LIR(BlockList* blocks) { 1551 tty->print_cr("LIR:"); 1552 int i; 1553 for (i = 0; i < blocks->length(); i++) { 1554 BlockBegin* bb = blocks->at(i); 1555 print_block(bb); 1556 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1557 bb->lir()->print_instructions(); 1558 } 1559 } 1560 1561 void LIR_List::print_instructions() { 1562 for (int i = 0; i < _operations.length(); i++) { 1563 _operations.at(i)->print(); tty->cr(); 1564 } 1565 tty->cr(); 1566 } 1567 1568 // LIR_Ops printing routines 1569 // LIR_Op 1570 void LIR_Op::print_on(outputStream* out) const { 1571 if (id() != -1 || PrintCFGToFile) { 1572 out->print("%4d ", id()); 1573 } else { 1574 out->print(" "); 1575 } 1576 out->print(name()); out->print(" "); 1577 print_instr(out); 1578 if (info() != NULL) out->print(" [bci:%d]", info()->bci()); 1579 #ifdef ASSERT 1580 if (Verbose && _file != NULL) { 1581 out->print(" (%s:%d)", _file, _line); 1582 } 1583 #endif 1584 } 1585 1586 const char * LIR_Op::name() const { 1587 const char* s = NULL; 1588 switch(code()) { 1589 // LIR_Op0 1590 case lir_membar: s = "membar"; break; 1591 case lir_membar_acquire: s = "membar_acquire"; break; 1592 case lir_membar_release: s = "membar_release"; break; 1593 case lir_word_align: s = "word_align"; break; 1594 case lir_label: s = "label"; break; 1595 case lir_nop: s = "nop"; break; 1596 case lir_backwardbranch_target: s = "backbranch"; break; 1597 case lir_std_entry: s = "std_entry"; break; 1598 case lir_osr_entry: s = "osr_entry"; break; 1599 case lir_build_frame: s = "build_frm"; break; 1600 case lir_fpop_raw: s = "fpop_raw"; break; 1601 case lir_24bit_FPU: s = "24bit_FPU"; break; 1602 case lir_reset_FPU: s = "reset_FPU"; break; 1603 case lir_breakpoint: s = "breakpoint"; break; 1604 case lir_get_thread: s = "get_thread"; break; 1605 // LIR_Op1 1606 case lir_fxch: s = "fxch"; break; 1607 case lir_fld: s = "fld"; break; 1608 case lir_ffree: s = "ffree"; break; 1609 case lir_push: s = "push"; break; 1610 case lir_pop: s = "pop"; break; 1611 case lir_null_check: s = "null_check"; break; 1612 case lir_return: s = "return"; break; 1613 case lir_safepoint: s = "safepoint"; break; 1614 case lir_neg: s = "neg"; break; 1615 case lir_leal: s = "leal"; break; 1616 case lir_branch: s = "branch"; break; 1617 case lir_cond_float_branch: s = "flt_cond_br"; break; 1618 case lir_move: s = "move"; break; 1619 case lir_roundfp: s = "roundfp"; break; 1620 case lir_rtcall: s = "rtcall"; break; 1621 case lir_throw: s = "throw"; break; 1622 case lir_unwind: s = "unwind"; break; 1623 case lir_convert: s = "convert"; break; 1624 case lir_alloc_object: s = "alloc_obj"; break; 1625 case lir_monaddr: s = "mon_addr"; break; 1626 case lir_pack64: s = "pack64"; break; 1627 case lir_unpack64: s = "unpack64"; break; 1628 // LIR_Op2 1629 case lir_cmp: s = "cmp"; break; 1630 case lir_cmp_l2i: s = "cmp_l2i"; break; 1631 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1632 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1633 case lir_cmove: s = "cmove"; break; 1634 case lir_add: s = "add"; break; 1635 case lir_sub: s = "sub"; break; 1636 case lir_mul: s = "mul"; break; 1637 case lir_mul_strictfp: s = "mul_strictfp"; break; 1638 case lir_div: s = "div"; break; 1639 case lir_div_strictfp: s = "div_strictfp"; break; 1640 case lir_rem: s = "rem"; break; 1641 case lir_abs: s = "abs"; break; 1642 case lir_sqrt: s = "sqrt"; break; 1643 case lir_sin: s = "sin"; break; 1644 case lir_cos: s = "cos"; break; 1645 case lir_tan: s = "tan"; break; 1646 case lir_log: s = "log"; break; 1647 case lir_log10: s = "log10"; break; 1648 case lir_logic_and: s = "logic_and"; break; 1649 case lir_logic_or: s = "logic_or"; break; 1650 case lir_logic_xor: s = "logic_xor"; break; 1651 case lir_shl: s = "shift_left"; break; 1652 case lir_shr: s = "shift_right"; break; 1653 case lir_ushr: s = "ushift_right"; break; 1654 case lir_alloc_array: s = "alloc_array"; break; 1655 // LIR_Op3 1656 case lir_idiv: s = "idiv"; break; 1657 case lir_irem: s = "irem"; break; 1658 // LIR_OpJavaCall 1659 case lir_static_call: s = "static"; break; 1660 case lir_optvirtual_call: s = "optvirtual"; break; 1661 case lir_icvirtual_call: s = "icvirtual"; break; 1662 case lir_virtual_call: s = "virtual"; break; 1663 case lir_dynamic_call: s = "dynamic"; break; 1664 // LIR_OpArrayCopy 1665 case lir_arraycopy: s = "arraycopy"; break; 1666 // LIR_OpLock 1667 case lir_lock: s = "lock"; break; 1668 case lir_unlock: s = "unlock"; break; 1669 // LIR_OpDelay 1670 case lir_delay_slot: s = "delay"; break; 1671 // LIR_OpTypeCheck 1672 case lir_instanceof: s = "instanceof"; break; 1673 case lir_checkcast: s = "checkcast"; break; 1674 case lir_store_check: s = "store_check"; break; 1675 // LIR_OpCompareAndSwap 1676 case lir_cas_long: s = "cas_long"; break; 1677 case lir_cas_obj: s = "cas_obj"; break; 1678 case lir_cas_int: s = "cas_int"; break; 1679 // LIR_OpProfileCall 1680 case lir_profile_call: s = "profile_call"; break; 1681 case lir_none: ShouldNotReachHere();break; 1682 default: s = "illegal_op"; break; 1683 } 1684 return s; 1685 } 1686 1687 // LIR_OpJavaCall 1688 void LIR_OpJavaCall::print_instr(outputStream* out) const { 1689 out->print("call: "); 1690 out->print("[addr: 0x%x]", address()); 1691 if (receiver()->is_valid()) { 1692 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1693 } 1694 if (result_opr()->is_valid()) { 1695 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1696 } 1697 } 1698 1699 // LIR_OpLabel 1700 void LIR_OpLabel::print_instr(outputStream* out) const { 1701 out->print("[label:0x%x]", _label); 1702 } 1703 1704 // LIR_OpArrayCopy 1705 void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1706 src()->print(out); out->print(" "); 1707 src_pos()->print(out); out->print(" "); 1708 dst()->print(out); out->print(" "); 1709 dst_pos()->print(out); out->print(" "); 1710 length()->print(out); out->print(" "); 1711 tmp()->print(out); out->print(" "); 1712 } 1713 1714 // LIR_OpCompareAndSwap 1715 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1716 addr()->print(out); out->print(" "); 1717 cmp_value()->print(out); out->print(" "); 1718 new_value()->print(out); out->print(" "); 1719 tmp1()->print(out); out->print(" "); 1720 tmp2()->print(out); out->print(" "); 1721 1722 } 1723 1724 // LIR_Op0 1725 void LIR_Op0::print_instr(outputStream* out) const { 1726 result_opr()->print(out); 1727 } 1728 1729 // LIR_Op1 1730 const char * LIR_Op1::name() const { 1731 if (code() == lir_move) { 1732 switch (move_kind()) { 1733 case lir_move_normal: 1734 return "move"; 1735 case lir_move_unaligned: 1736 return "unaligned move"; 1737 case lir_move_volatile: 1738 return "volatile_move"; 1739 default: 1740 ShouldNotReachHere(); 1741 return "illegal_op"; 1742 } 1743 } else { 1744 return LIR_Op::name(); 1745 } 1746 } 1747 1748 1749 void LIR_Op1::print_instr(outputStream* out) const { 1750 _opr->print(out); out->print(" "); 1751 result_opr()->print(out); out->print(" "); 1752 print_patch_code(out, patch_code()); 1753 } 1754 1755 1756 // LIR_Op1 1757 void LIR_OpRTCall::print_instr(outputStream* out) const { 1758 intx a = (intx)addr(); 1759 out->print(Runtime1::name_for_address(addr())); 1760 out->print(" "); 1761 tmp()->print(out); 1762 } 1763 1764 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1765 switch(code) { 1766 case lir_patch_none: break; 1767 case lir_patch_low: out->print("[patch_low]"); break; 1768 case lir_patch_high: out->print("[patch_high]"); break; 1769 case lir_patch_normal: out->print("[patch_normal]"); break; 1770 default: ShouldNotReachHere(); 1771 } 1772 } 1773 1774 // LIR_OpBranch 1775 void LIR_OpBranch::print_instr(outputStream* out) const { 1776 print_condition(out, cond()); out->print(" "); 1777 if (block() != NULL) { 1778 out->print("[B%d] ", block()->block_id()); 1779 } else if (stub() != NULL) { 1780 out->print("["); 1781 stub()->print_name(out); 1782 out->print(": 0x%x]", stub()); 1783 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->bci()); 1784 } else { 1785 out->print("[label:0x%x] ", label()); 1786 } 1787 if (ublock() != NULL) { 1788 out->print("unordered: [B%d] ", ublock()->block_id()); 1789 } 1790 } 1791 1792 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1793 switch(cond) { 1794 case lir_cond_equal: out->print("[EQ]"); break; 1795 case lir_cond_notEqual: out->print("[NE]"); break; 1796 case lir_cond_less: out->print("[LT]"); break; 1797 case lir_cond_lessEqual: out->print("[LE]"); break; 1798 case lir_cond_greaterEqual: out->print("[GE]"); break; 1799 case lir_cond_greater: out->print("[GT]"); break; 1800 case lir_cond_belowEqual: out->print("[BE]"); break; 1801 case lir_cond_aboveEqual: out->print("[AE]"); break; 1802 case lir_cond_always: out->print("[AL]"); break; 1803 default: out->print("[%d]",cond); break; 1804 } 1805 } 1806 1807 // LIR_OpConvert 1808 void LIR_OpConvert::print_instr(outputStream* out) const { 1809 print_bytecode(out, bytecode()); 1810 in_opr()->print(out); out->print(" "); 1811 result_opr()->print(out); out->print(" "); 1812 #ifdef PPC 1813 if(tmp1()->is_valid()) { 1814 tmp1()->print(out); out->print(" "); 1815 tmp2()->print(out); out->print(" "); 1816 } 1817 #endif 1818 } 1819 1820 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1821 switch(code) { 1822 case Bytecodes::_d2f: out->print("[d2f] "); break; 1823 case Bytecodes::_d2i: out->print("[d2i] "); break; 1824 case Bytecodes::_d2l: out->print("[d2l] "); break; 1825 case Bytecodes::_f2d: out->print("[f2d] "); break; 1826 case Bytecodes::_f2i: out->print("[f2i] "); break; 1827 case Bytecodes::_f2l: out->print("[f2l] "); break; 1828 case Bytecodes::_i2b: out->print("[i2b] "); break; 1829 case Bytecodes::_i2c: out->print("[i2c] "); break; 1830 case Bytecodes::_i2d: out->print("[i2d] "); break; 1831 case Bytecodes::_i2f: out->print("[i2f] "); break; 1832 case Bytecodes::_i2l: out->print("[i2l] "); break; 1833 case Bytecodes::_i2s: out->print("[i2s] "); break; 1834 case Bytecodes::_l2i: out->print("[l2i] "); break; 1835 case Bytecodes::_l2f: out->print("[l2f] "); break; 1836 case Bytecodes::_l2d: out->print("[l2d] "); break; 1837 default: 1838 out->print("[?%d]",code); 1839 break; 1840 } 1841 } 1842 1843 void LIR_OpAllocObj::print_instr(outputStream* out) const { 1844 klass()->print(out); out->print(" "); 1845 obj()->print(out); out->print(" "); 1846 tmp1()->print(out); out->print(" "); 1847 tmp2()->print(out); out->print(" "); 1848 tmp3()->print(out); out->print(" "); 1849 tmp4()->print(out); out->print(" "); 1850 out->print("[hdr:%d]", header_size()); out->print(" "); 1851 out->print("[obj:%d]", object_size()); out->print(" "); 1852 out->print("[lbl:0x%x]", stub()->entry()); 1853 } 1854 1855 void LIR_OpRoundFP::print_instr(outputStream* out) const { 1856 _opr->print(out); out->print(" "); 1857 tmp()->print(out); out->print(" "); 1858 result_opr()->print(out); out->print(" "); 1859 } 1860 1861 // LIR_Op2 1862 void LIR_Op2::print_instr(outputStream* out) const { 1863 if (code() == lir_cmove) { 1864 print_condition(out, condition()); out->print(" "); 1865 } 1866 in_opr1()->print(out); out->print(" "); 1867 in_opr2()->print(out); out->print(" "); 1868 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); } 1869 result_opr()->print(out); 1870 } 1871 1872 void LIR_OpAllocArray::print_instr(outputStream* out) const { 1873 klass()->print(out); out->print(" "); 1874 len()->print(out); out->print(" "); 1875 obj()->print(out); out->print(" "); 1876 tmp1()->print(out); out->print(" "); 1877 tmp2()->print(out); out->print(" "); 1878 tmp3()->print(out); out->print(" "); 1879 tmp4()->print(out); out->print(" "); 1880 out->print("[type:0x%x]", type()); out->print(" "); 1881 out->print("[label:0x%x]", stub()->entry()); 1882 } 1883 1884 1885 void LIR_OpTypeCheck::print_instr(outputStream* out) const { 1886 object()->print(out); out->print(" "); 1887 if (code() == lir_store_check) { 1888 array()->print(out); out->print(" "); 1889 } 1890 if (code() != lir_store_check) { 1891 klass()->print_name_on(out); out->print(" "); 1892 if (fast_check()) out->print("fast_check "); 1893 } 1894 tmp1()->print(out); out->print(" "); 1895 tmp2()->print(out); out->print(" "); 1896 tmp3()->print(out); out->print(" "); 1897 result_opr()->print(out); out->print(" "); 1898 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->bci()); 1899 } 1900 1901 1902 // LIR_Op3 1903 void LIR_Op3::print_instr(outputStream* out) const { 1904 in_opr1()->print(out); out->print(" "); 1905 in_opr2()->print(out); out->print(" "); 1906 in_opr3()->print(out); out->print(" "); 1907 result_opr()->print(out); 1908 } 1909 1910 1911 void LIR_OpLock::print_instr(outputStream* out) const { 1912 hdr_opr()->print(out); out->print(" "); 1913 obj_opr()->print(out); out->print(" "); 1914 lock_opr()->print(out); out->print(" "); 1915 if (_scratch->is_valid()) { 1916 _scratch->print(out); out->print(" "); 1917 } 1918 out->print("[lbl:0x%x]", stub()->entry()); 1919 } 1920 1921 1922 void LIR_OpDelay::print_instr(outputStream* out) const { 1923 _op->print_on(out); 1924 } 1925 1926 1927 // LIR_OpProfileCall 1928 void LIR_OpProfileCall::print_instr(outputStream* out) const { 1929 profiled_method()->name()->print_symbol_on(out); 1930 out->print("."); 1931 profiled_method()->holder()->name()->print_symbol_on(out); 1932 out->print(" @ %d ", profiled_bci()); 1933 mdo()->print(out); out->print(" "); 1934 recv()->print(out); out->print(" "); 1935 tmp1()->print(out); out->print(" "); 1936 } 1937 1938 #endif // PRODUCT 1939 1940 // Implementation of LIR_InsertionBuffer 1941 1942 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 1943 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 1944 1945 int i = number_of_insertion_points() - 1; 1946 if (i < 0 || index_at(i) < index) { 1947 append_new(index, 1); 1948 } else { 1949 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 1950 assert(count_at(i) > 0, "check"); 1951 set_count_at(i, count_at(i) + 1); 1952 } 1953 _ops.push(op); 1954 1955 DEBUG_ONLY(verify()); 1956 } 1957 1958 #ifdef ASSERT 1959 void LIR_InsertionBuffer::verify() { 1960 int sum = 0; 1961 int prev_idx = -1; 1962 1963 for (int i = 0; i < number_of_insertion_points(); i++) { 1964 assert(prev_idx < index_at(i), "index must be ordered ascending"); 1965 sum += count_at(i); 1966 } 1967 assert(sum == number_of_ops(), "wrong total sum"); 1968 } 1969 #endif