1 /*
2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CFGPrinter.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_FrameMap.hpp"
30 #include "c1/c1_IR.hpp"
31 #include "c1/c1_LIRGenerator.hpp"
32 #include "c1/c1_LinearScan.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "utilities/bitMap.inline.hpp"
35 #ifdef TARGET_ARCH_x86
36 # include "vmreg_x86.inline.hpp"
37 #endif
38 #ifdef TARGET_ARCH_sparc
39 # include "vmreg_sparc.inline.hpp"
40 #endif
41 #ifdef TARGET_ARCH_zero
42 # include "vmreg_zero.inline.hpp"
43 #endif
44
45
46 #ifndef PRODUCT
47
48 static LinearScanStatistic _stat_before_alloc;
49 static LinearScanStatistic _stat_after_asign;
50 static LinearScanStatistic _stat_final;
51
52 static LinearScanTimers _total_timer;
53
54 // helper macro for short definition of timer
55 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
56
57 // helper macro for short definition of trace-output inside code
58 #define TRACE_LINEAR_SCAN(level, code) \
59 if (TraceLinearScanLevel >= level) { \
60 code; \
61 }
62
63 #else
64
65 #define TIME_LINEAR_SCAN(timer_name)
66 #define TRACE_LINEAR_SCAN(level, code)
67
68 #endif
69
70 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
71 #ifdef _LP64
72 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 1, -1};
73 #else
74 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1};
75 #endif
76
77
78 // Implementation of LinearScan
79
80 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
81 : _compilation(ir->compilation())
82 , _ir(ir)
83 , _gen(gen)
84 , _frame_map(frame_map)
85 , _num_virtual_regs(gen->max_virtual_register_number())
86 , _has_fpu_registers(false)
87 , _num_calls(-1)
88 , _max_spills(0)
89 , _unused_spill_slot(-1)
90 , _intervals(0) // initialized later with correct length
91 , _new_intervals_from_allocation(new IntervalList())
92 , _sorted_intervals(NULL)
93 , _lir_ops(0) // initialized later with correct length
94 , _block_of_op(0) // initialized later with correct length
95 , _has_info(0)
96 , _has_call(0)
97 , _scope_value_cache(0) // initialized later with correct length
98 , _interval_in_loop(0, 0) // initialized later with correct length
99 , _cached_blocks(*ir->linear_scan_order())
100 #ifdef X86
101 , _fpu_stack_allocator(NULL)
102 #endif
103 {
104 assert(this->ir() != NULL, "check if valid");
105 assert(this->compilation() != NULL, "check if valid");
106 assert(this->gen() != NULL, "check if valid");
107 assert(this->frame_map() != NULL, "check if valid");
108 }
109
110
111 // ********** functions for converting LIR-Operands to register numbers
112 //
113 // Emulate a flat register file comprising physical integer registers,
114 // physical floating-point registers and virtual registers, in that order.
115 // Virtual registers already have appropriate numbers, since V0 is
116 // the number of physical registers.
117 // Returns -1 for hi word if opr is a single word operand.
118 //
119 // Note: the inverse operation (calculating an operand for register numbers)
120 // is done in calc_operand_for_interval()
121
122 int LinearScan::reg_num(LIR_Opr opr) {
123 assert(opr->is_register(), "should not call this otherwise");
124
125 if (opr->is_virtual_register()) {
126 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
127 return opr->vreg_number();
128 } else if (opr->is_single_cpu()) {
129 return opr->cpu_regnr();
130 } else if (opr->is_double_cpu()) {
131 return opr->cpu_regnrLo();
132 #ifdef X86
133 } else if (opr->is_single_xmm()) {
134 return opr->fpu_regnr() + pd_first_xmm_reg;
135 } else if (opr->is_double_xmm()) {
136 return opr->fpu_regnrLo() + pd_first_xmm_reg;
137 #endif
138 } else if (opr->is_single_fpu()) {
139 return opr->fpu_regnr() + pd_first_fpu_reg;
140 } else if (opr->is_double_fpu()) {
141 return opr->fpu_regnrLo() + pd_first_fpu_reg;
142 } else {
143 ShouldNotReachHere();
144 return -1;
145 }
146 }
147
148 int LinearScan::reg_numHi(LIR_Opr opr) {
149 assert(opr->is_register(), "should not call this otherwise");
150
151 if (opr->is_virtual_register()) {
152 return -1;
153 } else if (opr->is_single_cpu()) {
154 return -1;
155 } else if (opr->is_double_cpu()) {
156 return opr->cpu_regnrHi();
157 #ifdef X86
158 } else if (opr->is_single_xmm()) {
159 return -1;
160 } else if (opr->is_double_xmm()) {
161 return -1;
162 #endif
163 } else if (opr->is_single_fpu()) {
164 return -1;
165 } else if (opr->is_double_fpu()) {
166 return opr->fpu_regnrHi() + pd_first_fpu_reg;
167 } else {
168 ShouldNotReachHere();
169 return -1;
170 }
171 }
172
173
174 // ********** functions for classification of intervals
175
176 bool LinearScan::is_precolored_interval(const Interval* i) {
177 return i->reg_num() < LinearScan::nof_regs;
178 }
179
180 bool LinearScan::is_virtual_interval(const Interval* i) {
181 return i->reg_num() >= LIR_OprDesc::vreg_base;
182 }
183
184 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
185 return i->reg_num() < LinearScan::nof_cpu_regs;
186 }
187
188 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
189 #if defined(__SOFTFP__) || defined(E500V2)
190 return i->reg_num() >= LIR_OprDesc::vreg_base;
191 #else
192 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
193 #endif // __SOFTFP__ or E500V2
194 }
195
196 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
197 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
198 }
199
200 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
201 #if defined(__SOFTFP__) || defined(E500V2)
202 return false;
203 #else
204 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
205 #endif // __SOFTFP__ or E500V2
206 }
207
208 bool LinearScan::is_in_fpu_register(const Interval* i) {
209 // fixed intervals not needed for FPU stack allocation
210 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
211 }
212
213 bool LinearScan::is_oop_interval(const Interval* i) {
214 // fixed intervals never contain oops
215 return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
216 }
217
218
219 // ********** General helper functions
220
221 // compute next unused stack index that can be used for spilling
222 int LinearScan::allocate_spill_slot(bool double_word) {
223 int spill_slot;
224 if (double_word) {
225 if ((_max_spills & 1) == 1) {
226 // alignment of double-word values
227 // the hole because of the alignment is filled with the next single-word value
228 assert(_unused_spill_slot == -1, "wasting a spill slot");
229 _unused_spill_slot = _max_spills;
230 _max_spills++;
231 }
232 spill_slot = _max_spills;
233 _max_spills += 2;
234
235 } else if (_unused_spill_slot != -1) {
236 // re-use hole that was the result of a previous double-word alignment
237 spill_slot = _unused_spill_slot;
238 _unused_spill_slot = -1;
239
240 } else {
241 spill_slot = _max_spills;
242 _max_spills++;
243 }
244
245 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
246
247 // the class OopMapValue uses only 11 bits for storing the name of the
248 // oop location. So a stack slot bigger than 2^11 leads to an overflow
249 // that is not reported in product builds. Prevent this by checking the
250 // spill slot here (altough this value and the later used location name
251 // are slightly different)
252 if (result > 2000) {
253 bailout("too many stack slots used");
254 }
255
256 return result;
257 }
258
259 void LinearScan::assign_spill_slot(Interval* it) {
260 // assign the canonical spill slot of the parent (if a part of the interval
261 // is already spilled) or allocate a new spill slot
262 if (it->canonical_spill_slot() >= 0) {
263 it->assign_reg(it->canonical_spill_slot());
264 } else {
265 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
266 it->set_canonical_spill_slot(spill);
267 it->assign_reg(spill);
268 }
269 }
270
271 void LinearScan::propagate_spill_slots() {
272 if (!frame_map()->finalize_frame(max_spills())) {
273 bailout("frame too large");
274 }
275 }
276
277 // create a new interval with a predefined reg_num
278 // (only used for parent intervals that are created during the building phase)
279 Interval* LinearScan::create_interval(int reg_num) {
280 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
281
282 Interval* interval = new Interval(reg_num);
283 _intervals.at_put(reg_num, interval);
284
285 // assign register number for precolored intervals
286 if (reg_num < LIR_OprDesc::vreg_base) {
287 interval->assign_reg(reg_num);
288 }
289 return interval;
290 }
291
292 // assign a new reg_num to the interval and append it to the list of intervals
293 // (only used for child intervals that are created during register allocation)
294 void LinearScan::append_interval(Interval* it) {
295 it->set_reg_num(_intervals.length());
296 _intervals.append(it);
297 _new_intervals_from_allocation->append(it);
298 }
299
300 // copy the vreg-flags if an interval is split
301 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
302 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
303 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
304 }
305 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
306 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
307 }
308
309 // Note: do not copy the must_start_in_memory flag because it is not necessary for child
310 // intervals (only the very beginning of the interval must be in memory)
311 }
312
313
314 // ********** spill move optimization
315 // eliminate moves from register to stack if stack slot is known to be correct
316
317 // called during building of intervals
318 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
319 assert(interval->is_split_parent(), "can only be called for split parents");
320
321 switch (interval->spill_state()) {
322 case noDefinitionFound:
323 assert(interval->spill_definition_pos() == -1, "must no be set before");
324 interval->set_spill_definition_pos(def_pos);
325 interval->set_spill_state(oneDefinitionFound);
326 break;
327
328 case oneDefinitionFound:
329 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
330 if (def_pos < interval->spill_definition_pos() - 2) {
331 // second definition found, so no spill optimization possible for this interval
332 interval->set_spill_state(noOptimization);
333 } else {
334 // two consecutive definitions (because of two-operand LIR form)
335 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
336 }
337 break;
338
339 case noOptimization:
340 // nothing to do
341 break;
342
343 default:
344 assert(false, "other states not allowed at this time");
345 }
346 }
347
348 // called during register allocation
349 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
350 switch (interval->spill_state()) {
351 case oneDefinitionFound: {
352 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
353 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
354
355 if (def_loop_depth < spill_loop_depth) {
356 // the loop depth of the spilling position is higher then the loop depth
357 // at the definition of the interval -> move write to memory out of loop
358 // by storing at definitin of the interval
359 interval->set_spill_state(storeAtDefinition);
360 } else {
361 // the interval is currently spilled only once, so for now there is no
362 // reason to store the interval at the definition
363 interval->set_spill_state(oneMoveInserted);
364 }
365 break;
366 }
367
368 case oneMoveInserted: {
369 // the interval is spilled more then once, so it is better to store it to
370 // memory at the definition
371 interval->set_spill_state(storeAtDefinition);
372 break;
373 }
374
375 case storeAtDefinition:
376 case startInMemory:
377 case noOptimization:
378 case noDefinitionFound:
379 // nothing to do
380 break;
381
382 default:
383 assert(false, "other states not allowed at this time");
384 }
385 }
386
387
388 bool LinearScan::must_store_at_definition(const Interval* i) {
389 return i->is_split_parent() && i->spill_state() == storeAtDefinition;
390 }
391
392 // called once before asignment of register numbers
393 void LinearScan::eliminate_spill_moves() {
394 TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
395 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
396
397 // collect all intervals that must be stored after their definion.
398 // the list is sorted by Interval::spill_definition_pos
399 Interval* interval;
400 Interval* temp_list;
401 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
402
403 #ifdef ASSERT
404 Interval* prev = NULL;
405 Interval* temp = interval;
406 while (temp != Interval::end()) {
407 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
408 if (prev != NULL) {
409 assert(temp->from() >= prev->from(), "intervals not sorted");
410 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
411 }
412
413 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
414 assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
415 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
416
417 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
418
419 temp = temp->next();
420 }
421 #endif
422
423 LIR_InsertionBuffer insertion_buffer;
424 int num_blocks = block_count();
425 for (int i = 0; i < num_blocks; i++) {
426 BlockBegin* block = block_at(i);
427 LIR_OpList* instructions = block->lir()->instructions_list();
428 int num_inst = instructions->length();
429 bool has_new = false;
430
431 // iterate all instructions of the block. skip the first because it is always a label
432 for (int j = 1; j < num_inst; j++) {
433 LIR_Op* op = instructions->at(j);
434 int op_id = op->id();
435
436 if (op_id == -1) {
437 // remove move from register to stack if the stack slot is guaranteed to be correct.
438 // only moves that have been inserted by LinearScan can be removed.
439 assert(op->code() == lir_move, "only moves can have a op_id of -1");
440 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
441 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
442
443 LIR_Op1* op1 = (LIR_Op1*)op;
444 Interval* interval = interval_at(op1->result_opr()->vreg_number());
445
446 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
447 // move target is a stack slot that is always correct, so eliminate instruction
448 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
449 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
450 }
451
452 } else {
453 // insert move from register to stack just after the beginning of the interval
454 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
455 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
456
457 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
458 if (!has_new) {
459 // prepare insertion buffer (appended when all instructions of the block are processed)
460 insertion_buffer.init(block->lir());
461 has_new = true;
462 }
463
464 LIR_Opr from_opr = operand_for_interval(interval);
465 LIR_Opr to_opr = canonical_spill_opr(interval);
466 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
467 assert(to_opr->is_stack(), "to operand must be a stack slot");
468
469 insertion_buffer.move(j, from_opr, to_opr);
470 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
471
472 interval = interval->next();
473 }
474 }
475 } // end of instruction iteration
476
477 if (has_new) {
478 block->lir()->append(&insertion_buffer);
479 }
480 } // end of block iteration
481
482 assert(interval == Interval::end(), "missed an interval");
483 }
484
485
486 // ********** Phase 1: number all instructions in all blocks
487 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
488
489 void LinearScan::number_instructions() {
490 {
491 // dummy-timer to measure the cost of the timer itself
492 // (this time is then subtracted from all other timers to get the real value)
493 TIME_LINEAR_SCAN(timer_do_nothing);
494 }
495 TIME_LINEAR_SCAN(timer_number_instructions);
496
497 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
498 int num_blocks = block_count();
499 int num_instructions = 0;
500 int i;
501 for (i = 0; i < num_blocks; i++) {
502 num_instructions += block_at(i)->lir()->instructions_list()->length();
503 }
504
505 // initialize with correct length
506 _lir_ops = LIR_OpArray(num_instructions);
507 _block_of_op = BlockBeginArray(num_instructions);
508
509 int op_id = 0;
510 int idx = 0;
511
512 for (i = 0; i < num_blocks; i++) {
513 BlockBegin* block = block_at(i);
514 block->set_first_lir_instruction_id(op_id);
515 LIR_OpList* instructions = block->lir()->instructions_list();
516
517 int num_inst = instructions->length();
518 for (int j = 0; j < num_inst; j++) {
519 LIR_Op* op = instructions->at(j);
520 op->set_id(op_id);
521
522 _lir_ops.at_put(idx, op);
523 _block_of_op.at_put(idx, block);
524 assert(lir_op_with_id(op_id) == op, "must match");
525
526 idx++;
527 op_id += 2; // numbering of lir_ops by two
528 }
529 block->set_last_lir_instruction_id(op_id - 2);
530 }
531 assert(idx == num_instructions, "must match");
532 assert(idx * 2 == op_id, "must match");
533
534 _has_call = BitMap(num_instructions); _has_call.clear();
535 _has_info = BitMap(num_instructions); _has_info.clear();
536 }
537
538
539 // ********** Phase 2: compute local live sets separately for each block
540 // (sets live_gen and live_kill for each block)
541
542 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
543 LIR_Opr opr = value->operand();
544 Constant* con = value->as_Constant();
545
546 // check some asumptions about debug information
547 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
548 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
549 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
550
551 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
552 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
553 int reg = opr->vreg_number();
554 if (!live_kill.at(reg)) {
555 live_gen.set_bit(reg);
556 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
557 }
558 }
559 }
560
561
562 void LinearScan::compute_local_live_sets() {
563 TIME_LINEAR_SCAN(timer_compute_local_live_sets);
564
565 int num_blocks = block_count();
566 int live_size = live_set_size();
567 bool local_has_fpu_registers = false;
568 int local_num_calls = 0;
569 LIR_OpVisitState visitor;
570
571 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
572 local_interval_in_loop.clear();
573
574 // iterate all blocks
575 for (int i = 0; i < num_blocks; i++) {
576 BlockBegin* block = block_at(i);
577
578 BitMap live_gen(live_size); live_gen.clear();
579 BitMap live_kill(live_size); live_kill.clear();
580
581 if (block->is_set(BlockBegin::exception_entry_flag)) {
582 // Phi functions at the begin of an exception handler are
583 // implicitly defined (= killed) at the beginning of the block.
584 for_each_phi_fun(block, phi,
585 live_kill.set_bit(phi->operand()->vreg_number())
586 );
587 }
588
589 LIR_OpList* instructions = block->lir()->instructions_list();
590 int num_inst = instructions->length();
591
592 // iterate all instructions of the block. skip the first because it is always a label
593 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
594 for (int j = 1; j < num_inst; j++) {
595 LIR_Op* op = instructions->at(j);
596
597 // visit operation to collect all operands
598 visitor.visit(op);
599
600 if (visitor.has_call()) {
601 _has_call.set_bit(op->id() >> 1);
602 local_num_calls++;
603 }
604 if (visitor.info_count() > 0) {
605 _has_info.set_bit(op->id() >> 1);
606 }
607
608 // iterate input operands of instruction
609 int k, n, reg;
610 n = visitor.opr_count(LIR_OpVisitState::inputMode);
611 for (k = 0; k < n; k++) {
612 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
613 assert(opr->is_register(), "visitor should only return register operands");
614
615 if (opr->is_virtual_register()) {
616 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
617 reg = opr->vreg_number();
618 if (!live_kill.at(reg)) {
619 live_gen.set_bit(reg);
620 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
621 }
622 if (block->loop_index() >= 0) {
623 local_interval_in_loop.set_bit(reg, block->loop_index());
624 }
625 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
626 }
627
628 #ifdef ASSERT
629 // fixed intervals are never live at block boundaries, so
630 // they need not be processed in live sets.
631 // this is checked by these assertions to be sure about it.
632 // the entry block may have incoming values in registers, which is ok.
633 if (!opr->is_virtual_register() && block != ir()->start()) {
634 reg = reg_num(opr);
635 if (is_processed_reg_num(reg)) {
636 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
637 }
638 reg = reg_numHi(opr);
639 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
640 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
641 }
642 }
643 #endif
644 }
645
646 // Add uses of live locals from interpreter's point of view for proper debug information generation
647 n = visitor.info_count();
648 for (k = 0; k < n; k++) {
649 CodeEmitInfo* info = visitor.info_at(k);
650 ValueStack* stack = info->stack();
651 for_each_state_value(stack, value,
652 set_live_gen_kill(value, op, live_gen, live_kill)
653 );
654 }
655
656 // iterate temp operands of instruction
657 n = visitor.opr_count(LIR_OpVisitState::tempMode);
658 for (k = 0; k < n; k++) {
659 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
660 assert(opr->is_register(), "visitor should only return register operands");
661
662 if (opr->is_virtual_register()) {
663 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
664 reg = opr->vreg_number();
665 live_kill.set_bit(reg);
666 if (block->loop_index() >= 0) {
667 local_interval_in_loop.set_bit(reg, block->loop_index());
668 }
669 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
670 }
671
672 #ifdef ASSERT
673 // fixed intervals are never live at block boundaries, so
674 // they need not be processed in live sets
675 // process them only in debug mode so that this can be checked
676 if (!opr->is_virtual_register()) {
677 reg = reg_num(opr);
678 if (is_processed_reg_num(reg)) {
679 live_kill.set_bit(reg_num(opr));
680 }
681 reg = reg_numHi(opr);
682 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
683 live_kill.set_bit(reg);
684 }
685 }
686 #endif
687 }
688
689 // iterate output operands of instruction
690 n = visitor.opr_count(LIR_OpVisitState::outputMode);
691 for (k = 0; k < n; k++) {
692 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
693 assert(opr->is_register(), "visitor should only return register operands");
694
695 if (opr->is_virtual_register()) {
696 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
697 reg = opr->vreg_number();
698 live_kill.set_bit(reg);
699 if (block->loop_index() >= 0) {
700 local_interval_in_loop.set_bit(reg, block->loop_index());
701 }
702 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
703 }
704
705 #ifdef ASSERT
706 // fixed intervals are never live at block boundaries, so
707 // they need not be processed in live sets
708 // process them only in debug mode so that this can be checked
709 if (!opr->is_virtual_register()) {
710 reg = reg_num(opr);
711 if (is_processed_reg_num(reg)) {
712 live_kill.set_bit(reg_num(opr));
713 }
714 reg = reg_numHi(opr);
715 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
716 live_kill.set_bit(reg);
717 }
718 }
719 #endif
720 }
721 } // end of instruction iteration
722
723 block->set_live_gen (live_gen);
724 block->set_live_kill(live_kill);
725 block->set_live_in (BitMap(live_size)); block->live_in().clear();
726 block->set_live_out (BitMap(live_size)); block->live_out().clear();
727
728 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
729 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
730 } // end of block iteration
731
732 // propagate local calculated information into LinearScan object
733 _has_fpu_registers = local_has_fpu_registers;
734 compilation()->set_has_fpu_code(local_has_fpu_registers);
735
736 _num_calls = local_num_calls;
737 _interval_in_loop = local_interval_in_loop;
738 }
739
740
741 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
742 // (sets live_in and live_out for each block)
743
744 void LinearScan::compute_global_live_sets() {
745 TIME_LINEAR_SCAN(timer_compute_global_live_sets);
746
747 int num_blocks = block_count();
748 bool change_occurred;
749 bool change_occurred_in_block;
750 int iteration_count = 0;
751 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
752
753 // Perform a backward dataflow analysis to compute live_out and live_in for each block.
754 // The loop is executed until a fixpoint is reached (no changes in an iteration)
755 // Exception handlers must be processed because not all live values are
756 // present in the state array, e.g. because of global value numbering
757 do {
758 change_occurred = false;
759
760 // iterate all blocks in reverse order
761 for (int i = num_blocks - 1; i >= 0; i--) {
762 BlockBegin* block = block_at(i);
763
764 change_occurred_in_block = false;
765
766 // live_out(block) is the union of live_in(sux), for successors sux of block
767 int n = block->number_of_sux();
768 int e = block->number_of_exception_handlers();
769 if (n + e > 0) {
770 // block has successors
771 if (n > 0) {
772 live_out.set_from(block->sux_at(0)->live_in());
773 for (int j = 1; j < n; j++) {
774 live_out.set_union(block->sux_at(j)->live_in());
775 }
776 } else {
777 live_out.clear();
778 }
779 for (int j = 0; j < e; j++) {
780 live_out.set_union(block->exception_handler_at(j)->live_in());
781 }
782
783 if (!block->live_out().is_same(live_out)) {
784 // A change occurred. Swap the old and new live out sets to avoid copying.
785 BitMap temp = block->live_out();
786 block->set_live_out(live_out);
787 live_out = temp;
788
789 change_occurred = true;
790 change_occurred_in_block = true;
791 }
792 }
793
794 if (iteration_count == 0 || change_occurred_in_block) {
795 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
796 // note: live_in has to be computed only in first iteration or if live_out has changed!
797 BitMap live_in = block->live_in();
798 live_in.set_from(block->live_out());
799 live_in.set_difference(block->live_kill());
800 live_in.set_union(block->live_gen());
801 }
802
803 #ifndef PRODUCT
804 if (TraceLinearScanLevel >= 4) {
805 char c = ' ';
806 if (iteration_count == 0 || change_occurred_in_block) {
807 c = '*';
808 }
809 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
810 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
811 }
812 #endif
813 }
814 iteration_count++;
815
816 if (change_occurred && iteration_count > 50) {
817 BAILOUT("too many iterations in compute_global_live_sets");
818 }
819 } while (change_occurred);
820
821
822 #ifdef ASSERT
823 // check that fixed intervals are not live at block boundaries
824 // (live set must be empty at fixed intervals)
825 for (int i = 0; i < num_blocks; i++) {
826 BlockBegin* block = block_at(i);
827 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
828 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty");
829 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
830 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
831 }
832 }
833 #endif
834
835 // check that the live_in set of the first block is empty
836 BitMap live_in_args(ir()->start()->live_in().size());
837 live_in_args.clear();
838 if (!ir()->start()->live_in().is_same(live_in_args)) {
839 #ifdef ASSERT
840 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
841 tty->print_cr("affected registers:");
842 print_bitmap(ir()->start()->live_in());
843
844 // print some additional information to simplify debugging
845 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
846 if (ir()->start()->live_in().at(i)) {
847 Instruction* instr = gen()->instruction_for_vreg(i);
848 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
849
850 for (int j = 0; j < num_blocks; j++) {
851 BlockBegin* block = block_at(j);
852 if (block->live_gen().at(i)) {
853 tty->print_cr(" used in block B%d", block->block_id());
854 }
855 if (block->live_kill().at(i)) {
856 tty->print_cr(" defined in block B%d", block->block_id());
857 }
858 }
859 }
860 }
861
862 #endif
863 // when this fails, virtual registers are used before they are defined.
864 assert(false, "live_in set of first block must be empty");
865 // bailout of if this occurs in product mode.
866 bailout("live_in set of first block not empty");
867 }
868 }
869
870
871 // ********** Phase 4: build intervals
872 // (fills the list _intervals)
873
874 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
875 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
876 LIR_Opr opr = value->operand();
877 Constant* con = value->as_Constant();
878
879 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
880 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
881 add_use(opr, from, to, use_kind);
882 }
883 }
884
885
886 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
887 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
888 assert(opr->is_register(), "should not be called otherwise");
889
890 if (opr->is_virtual_register()) {
891 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
892 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
893
894 } else {
895 int reg = reg_num(opr);
896 if (is_processed_reg_num(reg)) {
897 add_def(reg, def_pos, use_kind, opr->type_register());
898 }
899 reg = reg_numHi(opr);
900 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
901 add_def(reg, def_pos, use_kind, opr->type_register());
902 }
903 }
904 }
905
906 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
907 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
908 assert(opr->is_register(), "should not be called otherwise");
909
910 if (opr->is_virtual_register()) {
911 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
912 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
913
914 } else {
915 int reg = reg_num(opr);
916 if (is_processed_reg_num(reg)) {
917 add_use(reg, from, to, use_kind, opr->type_register());
918 }
919 reg = reg_numHi(opr);
920 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
921 add_use(reg, from, to, use_kind, opr->type_register());
922 }
923 }
924 }
925
926 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
927 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
928 assert(opr->is_register(), "should not be called otherwise");
929
930 if (opr->is_virtual_register()) {
931 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
932 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
933
934 } else {
935 int reg = reg_num(opr);
936 if (is_processed_reg_num(reg)) {
937 add_temp(reg, temp_pos, use_kind, opr->type_register());
938 }
939 reg = reg_numHi(opr);
940 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
941 add_temp(reg, temp_pos, use_kind, opr->type_register());
942 }
943 }
944 }
945
946
947 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
948 Interval* interval = interval_at(reg_num);
949 if (interval != NULL) {
950 assert(interval->reg_num() == reg_num, "wrong interval");
951
952 if (type != T_ILLEGAL) {
953 interval->set_type(type);
954 }
955
956 Range* r = interval->first();
957 if (r->from() <= def_pos) {
958 // Update the starting point (when a range is first created for a use, its
959 // start is the beginning of the current block until a def is encountered.)
960 r->set_from(def_pos);
961 interval->add_use_pos(def_pos, use_kind);
962
963 } else {
964 // Dead value - make vacuous interval
965 // also add use_kind for dead intervals
966 interval->add_range(def_pos, def_pos + 1);
967 interval->add_use_pos(def_pos, use_kind);
968 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
969 }
970
971 } else {
972 // Dead value - make vacuous interval
973 // also add use_kind for dead intervals
974 interval = create_interval(reg_num);
975 if (type != T_ILLEGAL) {
976 interval->set_type(type);
977 }
978
979 interval->add_range(def_pos, def_pos + 1);
980 interval->add_use_pos(def_pos, use_kind);
981 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
982 }
983
984 change_spill_definition_pos(interval, def_pos);
985 if (use_kind == noUse && interval->spill_state() <= startInMemory) {
986 // detection of method-parameters and roundfp-results
987 // TODO: move this directly to position where use-kind is computed
988 interval->set_spill_state(startInMemory);
989 }
990 }
991
992 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
993 Interval* interval = interval_at(reg_num);
994 if (interval == NULL) {
995 interval = create_interval(reg_num);
996 }
997 assert(interval->reg_num() == reg_num, "wrong interval");
998
999 if (type != T_ILLEGAL) {
1000 interval->set_type(type);
1001 }
1002
1003 interval->add_range(from, to);
1004 interval->add_use_pos(to, use_kind);
1005 }
1006
1007 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1008 Interval* interval = interval_at(reg_num);
1009 if (interval == NULL) {
1010 interval = create_interval(reg_num);
1011 }
1012 assert(interval->reg_num() == reg_num, "wrong interval");
1013
1014 if (type != T_ILLEGAL) {
1015 interval->set_type(type);
1016 }
1017
1018 interval->add_range(temp_pos, temp_pos + 1);
1019 interval->add_use_pos(temp_pos, use_kind);
1020 }
1021
1022
1023 // the results of this functions are used for optimizing spilling and reloading
1024 // if the functions return shouldHaveRegister and the interval is spilled,
1025 // it is not reloaded to a register.
1026 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1027 if (op->code() == lir_move) {
1028 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1029 LIR_Op1* move = (LIR_Op1*)op;
1030 LIR_Opr res = move->result_opr();
1031 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1032
1033 if (result_in_memory) {
1034 // Begin of an interval with must_start_in_memory set.
1035 // This interval will always get a stack slot first, so return noUse.
1036 return noUse;
1037
1038 } else if (move->in_opr()->is_stack()) {
1039 // method argument (condition must be equal to handle_method_arguments)
1040 return noUse;
1041
1042 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1043 // Move from register to register
1044 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1045 // special handling of phi-function moves inside osr-entry blocks
1046 // input operand must have a register instead of output operand (leads to better register allocation)
1047 return shouldHaveRegister;
1048 }
1049 }
1050 }
1051
1052 if (opr->is_virtual() &&
1053 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1054 // result is a stack-slot, so prevent immediate reloading
1055 return noUse;
1056 }
1057
1058 // all other operands require a register
1059 return mustHaveRegister;
1060 }
1061
1062 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1063 if (op->code() == lir_move) {
1064 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1065 LIR_Op1* move = (LIR_Op1*)op;
1066 LIR_Opr res = move->result_opr();
1067 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1068
1069 if (result_in_memory) {
1070 // Move to an interval with must_start_in_memory set.
1071 // To avoid moves from stack to stack (not allowed) force the input operand to a register
1072 return mustHaveRegister;
1073
1074 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1075 // Move from register to register
1076 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1077 // special handling of phi-function moves inside osr-entry blocks
1078 // input operand must have a register instead of output operand (leads to better register allocation)
1079 return mustHaveRegister;
1080 }
1081
1082 // The input operand is not forced to a register (moves from stack to register are allowed),
1083 // but it is faster if the input operand is in a register
1084 return shouldHaveRegister;
1085 }
1086 }
1087
1088
1089 #ifdef X86
1090 if (op->code() == lir_cmove) {
1091 // conditional moves can handle stack operands
1092 assert(op->result_opr()->is_register(), "result must always be in a register");
1093 return shouldHaveRegister;
1094 }
1095
1096 // optimizations for second input operand of arithmehtic operations on Intel
1097 // this operand is allowed to be on the stack in some cases
1098 BasicType opr_type = opr->type_register();
1099 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1100 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1101 // SSE float instruction (T_DOUBLE only supported with SSE2)
1102 switch (op->code()) {
1103 case lir_cmp:
1104 case lir_add:
1105 case lir_sub:
1106 case lir_mul:
1107 case lir_div:
1108 {
1109 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1110 LIR_Op2* op2 = (LIR_Op2*)op;
1111 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1112 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1113 return shouldHaveRegister;
1114 }
1115 }
1116 }
1117 } else {
1118 // FPU stack float instruction
1119 switch (op->code()) {
1120 case lir_add:
1121 case lir_sub:
1122 case lir_mul:
1123 case lir_div:
1124 {
1125 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1126 LIR_Op2* op2 = (LIR_Op2*)op;
1127 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1128 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1129 return shouldHaveRegister;
1130 }
1131 }
1132 }
1133 }
1134
1135 } else if (opr_type != T_LONG) {
1136 // integer instruction (note: long operands must always be in register)
1137 switch (op->code()) {
1138 case lir_cmp:
1139 case lir_add:
1140 case lir_sub:
1141 case lir_logic_and:
1142 case lir_logic_or:
1143 case lir_logic_xor:
1144 {
1145 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1146 LIR_Op2* op2 = (LIR_Op2*)op;
1147 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149 return shouldHaveRegister;
1150 }
1151 }
1152 }
1153 }
1154 #endif // X86
1155
1156 // all other operands require a register
1157 return mustHaveRegister;
1158 }
1159
1160
1161 void LinearScan::handle_method_arguments(LIR_Op* op) {
1162 // special handling for method arguments (moves from stack to virtual register):
1163 // the interval gets no register assigned, but the stack slot.
1164 // it is split before the first use by the register allocator.
1165
1166 if (op->code() == lir_move) {
1167 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1168 LIR_Op1* move = (LIR_Op1*)op;
1169
1170 if (move->in_opr()->is_stack()) {
1171 #ifdef ASSERT
1172 int arg_size = compilation()->method()->arg_size();
1173 LIR_Opr o = move->in_opr();
1174 if (o->is_single_stack()) {
1175 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1176 } else if (o->is_double_stack()) {
1177 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1178 } else {
1179 ShouldNotReachHere();
1180 }
1181
1182 assert(move->id() > 0, "invalid id");
1183 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1184 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1185
1186 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1187 #endif
1188
1189 Interval* interval = interval_at(reg_num(move->result_opr()));
1190
1191 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1192 interval->set_canonical_spill_slot(stack_slot);
1193 interval->assign_reg(stack_slot);
1194 }
1195 }
1196 }
1197
1198 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1199 // special handling for doubleword move from memory to register:
1200 // in this case the registers of the input address and the result
1201 // registers must not overlap -> add a temp range for the input registers
1202 if (op->code() == lir_move) {
1203 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1204 LIR_Op1* move = (LIR_Op1*)op;
1205
1206 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1207 LIR_Address* address = move->in_opr()->as_address_ptr();
1208 if (address != NULL) {
1209 if (address->base()->is_valid()) {
1210 add_temp(address->base(), op->id(), noUse);
1211 }
1212 if (address->index()->is_valid()) {
1213 add_temp(address->index(), op->id(), noUse);
1214 }
1215 }
1216 }
1217 }
1218 }
1219
1220 void LinearScan::add_register_hints(LIR_Op* op) {
1221 switch (op->code()) {
1222 case lir_move: // fall through
1223 case lir_convert: {
1224 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1225 LIR_Op1* move = (LIR_Op1*)op;
1226
1227 LIR_Opr move_from = move->in_opr();
1228 LIR_Opr move_to = move->result_opr();
1229
1230 if (move_to->is_register() && move_from->is_register()) {
1231 Interval* from = interval_at(reg_num(move_from));
1232 Interval* to = interval_at(reg_num(move_to));
1233 if (from != NULL && to != NULL) {
1234 to->set_register_hint(from);
1235 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1236 }
1237 }
1238 break;
1239 }
1240 case lir_cmove: {
1241 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1242 LIR_Op2* cmove = (LIR_Op2*)op;
1243
1244 LIR_Opr move_from = cmove->in_opr1();
1245 LIR_Opr move_to = cmove->result_opr();
1246
1247 if (move_to->is_register() && move_from->is_register()) {
1248 Interval* from = interval_at(reg_num(move_from));
1249 Interval* to = interval_at(reg_num(move_to));
1250 if (from != NULL && to != NULL) {
1251 to->set_register_hint(from);
1252 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1253 }
1254 }
1255 break;
1256 }
1257 }
1258 }
1259
1260
1261 void LinearScan::build_intervals() {
1262 TIME_LINEAR_SCAN(timer_build_intervals);
1263
1264 // initialize interval list with expected number of intervals
1265 // (32 is added to have some space for split children without having to resize the list)
1266 _intervals = IntervalList(num_virtual_regs() + 32);
1267 // initialize all slots that are used by build_intervals
1268 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1269
1270 // create a list with all caller-save registers (cpu, fpu, xmm)
1271 // when an instruction is a call, a temp range is created for all these registers
1272 int num_caller_save_registers = 0;
1273 int caller_save_registers[LinearScan::nof_regs];
1274
1275 int i;
1276 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs; i++) {
1277 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1278 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1279 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1280 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1281 }
1282
1283 // temp ranges for fpu registers are only created when the method has
1284 // virtual fpu operands. Otherwise no allocation for fpu registers is
1285 // perfomed and so the temp ranges would be useless
1286 if (has_fpu_registers()) {
1287 #ifdef X86
1288 if (UseSSE < 2) {
1289 #endif
1290 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1291 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1292 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1293 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1294 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1295 }
1296 #ifdef X86
1297 }
1298 if (UseSSE > 0) {
1299 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
1300 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1301 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1302 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1303 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1304 }
1305 }
1306 #endif
1307 }
1308 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1309
1310
1311 LIR_OpVisitState visitor;
1312
1313 // iterate all blocks in reverse order
1314 for (i = block_count() - 1; i >= 0; i--) {
1315 BlockBegin* block = block_at(i);
1316 LIR_OpList* instructions = block->lir()->instructions_list();
1317 int block_from = block->first_lir_instruction_id();
1318 int block_to = block->last_lir_instruction_id();
1319
1320 assert(block_from == instructions->at(0)->id(), "must be");
1321 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be");
1322
1323 // Update intervals for registers live at the end of this block;
1324 BitMap live = block->live_out();
1325 int size = (int)live.size();
1326 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1327 assert(live.at(number), "should not stop here otherwise");
1328 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1329 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1330
1331 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1332
1333 // add special use positions for loop-end blocks when the
1334 // interval is used anywhere inside this loop. It's possible
1335 // that the block was part of a non-natural loop, so it might
1336 // have an invalid loop index.
1337 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1338 block->loop_index() != -1 &&
1339 is_interval_in_loop(number, block->loop_index())) {
1340 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1341 }
1342 }
1343
1344 // iterate all instructions of the block in reverse order.
1345 // skip the first instruction because it is always a label
1346 // definitions of intervals are processed before uses
1347 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1348 for (int j = instructions->length() - 1; j >= 1; j--) {
1349 LIR_Op* op = instructions->at(j);
1350 int op_id = op->id();
1351
1352 // visit operation to collect all operands
1353 visitor.visit(op);
1354
1355 // add a temp range for each register if operation destroys caller-save registers
1356 if (visitor.has_call()) {
1357 for (int k = 0; k < num_caller_save_registers; k++) {
1358 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1359 }
1360 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1361 }
1362
1363 // Add any platform dependent temps
1364 pd_add_temps(op);
1365
1366 // visit definitions (output and temp operands)
1367 int k, n;
1368 n = visitor.opr_count(LIR_OpVisitState::outputMode);
1369 for (k = 0; k < n; k++) {
1370 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1371 assert(opr->is_register(), "visitor should only return register operands");
1372 add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1373 }
1374
1375 n = visitor.opr_count(LIR_OpVisitState::tempMode);
1376 for (k = 0; k < n; k++) {
1377 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1378 assert(opr->is_register(), "visitor should only return register operands");
1379 add_temp(opr, op_id, mustHaveRegister);
1380 }
1381
1382 // visit uses (input operands)
1383 n = visitor.opr_count(LIR_OpVisitState::inputMode);
1384 for (k = 0; k < n; k++) {
1385 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1386 assert(opr->is_register(), "visitor should only return register operands");
1387 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1388 }
1389
1390 // Add uses of live locals from interpreter's point of view for proper
1391 // debug information generation
1392 // Treat these operands as temp values (if the life range is extended
1393 // to a call site, the value would be in a register at the call otherwise)
1394 n = visitor.info_count();
1395 for (k = 0; k < n; k++) {
1396 CodeEmitInfo* info = visitor.info_at(k);
1397 ValueStack* stack = info->stack();
1398 for_each_state_value(stack, value,
1399 add_use(value, block_from, op_id + 1, noUse);
1400 );
1401 }
1402
1403 // special steps for some instructions (especially moves)
1404 handle_method_arguments(op);
1405 handle_doubleword_moves(op);
1406 add_register_hints(op);
1407
1408 } // end of instruction iteration
1409 } // end of block iteration
1410
1411
1412 // add the range [0, 1[ to all fixed intervals
1413 // -> the register allocator need not handle unhandled fixed intervals
1414 for (int n = 0; n < LinearScan::nof_regs; n++) {
1415 Interval* interval = interval_at(n);
1416 if (interval != NULL) {
1417 interval->add_range(0, 1);
1418 }
1419 }
1420 }
1421
1422
1423 // ********** Phase 5: actual register allocation
1424
1425 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1426 if (*a != NULL) {
1427 if (*b != NULL) {
1428 return (*a)->from() - (*b)->from();
1429 } else {
1430 return -1;
1431 }
1432 } else {
1433 if (*b != NULL) {
1434 return 1;
1435 } else {
1436 return 0;
1437 }
1438 }
1439 }
1440
1441 #ifndef PRODUCT
1442 bool LinearScan::is_sorted(IntervalArray* intervals) {
1443 int from = -1;
1444 int i, j;
1445 for (i = 0; i < intervals->length(); i ++) {
1446 Interval* it = intervals->at(i);
1447 if (it != NULL) {
1448 if (from > it->from()) {
1449 assert(false, "");
1450 return false;
1451 }
1452 from = it->from();
1453 }
1454 }
1455
1456 // check in both directions if sorted list and unsorted list contain same intervals
1457 for (i = 0; i < interval_count(); i++) {
1458 if (interval_at(i) != NULL) {
1459 int num_found = 0;
1460 for (j = 0; j < intervals->length(); j++) {
1461 if (interval_at(i) == intervals->at(j)) {
1462 num_found++;
1463 }
1464 }
1465 assert(num_found == 1, "lists do not contain same intervals");
1466 }
1467 }
1468 for (j = 0; j < intervals->length(); j++) {
1469 int num_found = 0;
1470 for (i = 0; i < interval_count(); i++) {
1471 if (interval_at(i) == intervals->at(j)) {
1472 num_found++;
1473 }
1474 }
1475 assert(num_found == 1, "lists do not contain same intervals");
1476 }
1477
1478 return true;
1479 }
1480 #endif
1481
1482 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1483 if (*prev != NULL) {
1484 (*prev)->set_next(interval);
1485 } else {
1486 *first = interval;
1487 }
1488 *prev = interval;
1489 }
1490
1491 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1492 assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1493
1494 *list1 = *list2 = Interval::end();
1495
1496 Interval* list1_prev = NULL;
1497 Interval* list2_prev = NULL;
1498 Interval* v;
1499
1500 const int n = _sorted_intervals->length();
1501 for (int i = 0; i < n; i++) {
1502 v = _sorted_intervals->at(i);
1503 if (v == NULL) continue;
1504
1505 if (is_list1(v)) {
1506 add_to_list(list1, &list1_prev, v);
1507 } else if (is_list2 == NULL || is_list2(v)) {
1508 add_to_list(list2, &list2_prev, v);
1509 }
1510 }
1511
1512 if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1513 if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1514
1515 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1516 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1517 }
1518
1519
1520 void LinearScan::sort_intervals_before_allocation() {
1521 TIME_LINEAR_SCAN(timer_sort_intervals_before);
1522
1523 IntervalList* unsorted_list = &_intervals;
1524 int unsorted_len = unsorted_list->length();
1525 int sorted_len = 0;
1526 int unsorted_idx;
1527 int sorted_idx = 0;
1528 int sorted_from_max = -1;
1529
1530 // calc number of items for sorted list (sorted list must not contain NULL values)
1531 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1532 if (unsorted_list->at(unsorted_idx) != NULL) {
1533 sorted_len++;
1534 }
1535 }
1536 IntervalArray* sorted_list = new IntervalArray(sorted_len);
1537
1538 // special sorting algorithm: the original interval-list is almost sorted,
1539 // only some intervals are swapped. So this is much faster than a complete QuickSort
1540 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1541 Interval* cur_interval = unsorted_list->at(unsorted_idx);
1542
1543 if (cur_interval != NULL) {
1544 int cur_from = cur_interval->from();
1545
1546 if (sorted_from_max <= cur_from) {
1547 sorted_list->at_put(sorted_idx++, cur_interval);
1548 sorted_from_max = cur_interval->from();
1549 } else {
1550 // the asumption that the intervals are already sorted failed,
1551 // so this interval must be sorted in manually
1552 int j;
1553 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1554 sorted_list->at_put(j + 1, sorted_list->at(j));
1555 }
1556 sorted_list->at_put(j + 1, cur_interval);
1557 sorted_idx++;
1558 }
1559 }
1560 }
1561 _sorted_intervals = sorted_list;
1562 }
1563
1564 void LinearScan::sort_intervals_after_allocation() {
1565 TIME_LINEAR_SCAN(timer_sort_intervals_after);
1566
1567 IntervalArray* old_list = _sorted_intervals;
1568 IntervalList* new_list = _new_intervals_from_allocation;
1569 int old_len = old_list->length();
1570 int new_len = new_list->length();
1571
1572 if (new_len == 0) {
1573 // no intervals have been added during allocation, so sorted list is already up to date
1574 return;
1575 }
1576
1577 // conventional sort-algorithm for new intervals
1578 new_list->sort(interval_cmp);
1579
1580 // merge old and new list (both already sorted) into one combined list
1581 IntervalArray* combined_list = new IntervalArray(old_len + new_len);
1582 int old_idx = 0;
1583 int new_idx = 0;
1584
1585 while (old_idx + new_idx < old_len + new_len) {
1586 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1587 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1588 old_idx++;
1589 } else {
1590 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1591 new_idx++;
1592 }
1593 }
1594
1595 _sorted_intervals = combined_list;
1596 }
1597
1598
1599 void LinearScan::allocate_registers() {
1600 TIME_LINEAR_SCAN(timer_allocate_registers);
1601
1602 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1603 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1604
1605 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
1606 if (has_fpu_registers()) {
1607 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
1608 #ifdef ASSERT
1609 } else {
1610 // fpu register allocation is omitted because no virtual fpu registers are present
1611 // just check this again...
1612 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
1613 assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1614 #endif
1615 }
1616
1617 // allocate cpu registers
1618 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1619 cpu_lsw.walk();
1620 cpu_lsw.finish_allocation();
1621
1622 if (has_fpu_registers()) {
1623 // allocate fpu registers
1624 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1625 fpu_lsw.walk();
1626 fpu_lsw.finish_allocation();
1627 }
1628 }
1629
1630
1631 // ********** Phase 6: resolve data flow
1632 // (insert moves at edges between blocks if intervals have been split)
1633
1634 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1635 // instead of returning NULL
1636 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1637 Interval* result = interval->split_child_at_op_id(op_id, mode);
1638 if (result != NULL) {
1639 return result;
1640 }
1641
1642 assert(false, "must find an interval, but do a clean bailout in product mode");
1643 result = new Interval(LIR_OprDesc::vreg_base);
1644 result->assign_reg(0);
1645 result->set_type(T_INT);
1646 BAILOUT_("LinearScan: interval is NULL", result);
1647 }
1648
1649
1650 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1651 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1652 assert(interval_at(reg_num) != NULL, "no interval found");
1653
1654 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1655 }
1656
1657 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1658 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1659 assert(interval_at(reg_num) != NULL, "no interval found");
1660
1661 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1662 }
1663
1664 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1665 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1666 assert(interval_at(reg_num) != NULL, "no interval found");
1667
1668 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1669 }
1670
1671
1672 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1673 DEBUG_ONLY(move_resolver.check_empty());
1674
1675 const int num_regs = num_virtual_regs();
1676 const int size = live_set_size();
1677 const BitMap live_at_edge = to_block->live_in();
1678
1679 // visit all registers where the live_at_edge bit is set
1680 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1681 assert(r < num_regs, "live information set for not exisiting interval");
1682 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1683
1684 Interval* from_interval = interval_at_block_end(from_block, r);
1685 Interval* to_interval = interval_at_block_begin(to_block, r);
1686
1687 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1688 // need to insert move instruction
1689 move_resolver.add_mapping(from_interval, to_interval);
1690 }
1691 }
1692 }
1693
1694
1695 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1696 if (from_block->number_of_sux() <= 1) {
1697 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1698
1699 LIR_OpList* instructions = from_block->lir()->instructions_list();
1700 LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1701 if (branch != NULL) {
1702 // insert moves before branch
1703 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1704 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1705 } else {
1706 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1707 }
1708
1709 } else {
1710 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1711 #ifdef ASSERT
1712 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1713
1714 // because the number of predecessor edges matches the number of
1715 // successor edges, blocks which are reached by switch statements
1716 // may have be more than one predecessor but it will be guaranteed
1717 // that all predecessors will be the same.
1718 for (int i = 0; i < to_block->number_of_preds(); i++) {
1719 assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1720 }
1721 #endif
1722
1723 move_resolver.set_insert_position(to_block->lir(), 0);
1724 }
1725 }
1726
1727
1728 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1729 void LinearScan::resolve_data_flow() {
1730 TIME_LINEAR_SCAN(timer_resolve_data_flow);
1731
1732 int num_blocks = block_count();
1733 MoveResolver move_resolver(this);
1734 BitMap block_completed(num_blocks); block_completed.clear();
1735 BitMap already_resolved(num_blocks); already_resolved.clear();
1736
1737 int i;
1738 for (i = 0; i < num_blocks; i++) {
1739 BlockBegin* block = block_at(i);
1740
1741 // check if block has only one predecessor and only one successor
1742 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1743 LIR_OpList* instructions = block->lir()->instructions_list();
1744 assert(instructions->at(0)->code() == lir_label, "block must start with label");
1745 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1746 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1747
1748 // check if block is empty (only label and branch)
1749 if (instructions->length() == 2) {
1750 BlockBegin* pred = block->pred_at(0);
1751 BlockBegin* sux = block->sux_at(0);
1752
1753 // prevent optimization of two consecutive blocks
1754 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1755 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1756 block_completed.set_bit(block->linear_scan_number());
1757
1758 // directly resolve between pred and sux (without looking at the empty block between)
1759 resolve_collect_mappings(pred, sux, move_resolver);
1760 if (move_resolver.has_mappings()) {
1761 move_resolver.set_insert_position(block->lir(), 0);
1762 move_resolver.resolve_and_append_moves();
1763 }
1764 }
1765 }
1766 }
1767 }
1768
1769
1770 for (i = 0; i < num_blocks; i++) {
1771 if (!block_completed.at(i)) {
1772 BlockBegin* from_block = block_at(i);
1773 already_resolved.set_from(block_completed);
1774
1775 int num_sux = from_block->number_of_sux();
1776 for (int s = 0; s < num_sux; s++) {
1777 BlockBegin* to_block = from_block->sux_at(s);
1778
1779 // check for duplicate edges between the same blocks (can happen with switch blocks)
1780 if (!already_resolved.at(to_block->linear_scan_number())) {
1781 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1782 already_resolved.set_bit(to_block->linear_scan_number());
1783
1784 // collect all intervals that have been split between from_block and to_block
1785 resolve_collect_mappings(from_block, to_block, move_resolver);
1786 if (move_resolver.has_mappings()) {
1787 resolve_find_insert_pos(from_block, to_block, move_resolver);
1788 move_resolver.resolve_and_append_moves();
1789 }
1790 }
1791 }
1792 }
1793 }
1794 }
1795
1796
1797 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1798 if (interval_at(reg_num) == NULL) {
1799 // if a phi function is never used, no interval is created -> ignore this
1800 return;
1801 }
1802
1803 Interval* interval = interval_at_block_begin(block, reg_num);
1804 int reg = interval->assigned_reg();
1805 int regHi = interval->assigned_regHi();
1806
1807 if ((reg < nof_regs && interval->always_in_memory()) ||
1808 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1809 // the interval is split to get a short range that is located on the stack
1810 // in the following two cases:
1811 // * the interval started in memory (e.g. method parameter), but is currently in a register
1812 // this is an optimization for exception handling that reduces the number of moves that
1813 // are necessary for resolving the states when an exception uses this exception handler
1814 // * the interval would be on the fpu stack at the begin of the exception handler
1815 // this is not allowed because of the complicated fpu stack handling on Intel
1816
1817 // range that will be spilled to memory
1818 int from_op_id = block->first_lir_instruction_id();
1819 int to_op_id = from_op_id + 1; // short live range of length 1
1820 assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1821 "no split allowed between exception entry and first instruction");
1822
1823 if (interval->from() != from_op_id) {
1824 // the part before from_op_id is unchanged
1825 interval = interval->split(from_op_id);
1826 interval->assign_reg(reg, regHi);
1827 append_interval(interval);
1828 }
1829 assert(interval->from() == from_op_id, "must be true now");
1830
1831 Interval* spilled_part = interval;
1832 if (interval->to() != to_op_id) {
1833 // the part after to_op_id is unchanged
1834 spilled_part = interval->split_from_start(to_op_id);
1835 append_interval(spilled_part);
1836 move_resolver.add_mapping(spilled_part, interval);
1837 }
1838 assign_spill_slot(spilled_part);
1839
1840 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1841 }
1842 }
1843
1844 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1845 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1846 DEBUG_ONLY(move_resolver.check_empty());
1847
1848 // visit all registers where the live_in bit is set
1849 int size = live_set_size();
1850 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1851 resolve_exception_entry(block, r, move_resolver);
1852 }
1853
1854 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1855 for_each_phi_fun(block, phi,
1856 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1857 );
1858
1859 if (move_resolver.has_mappings()) {
1860 // insert moves after first instruction
1861 move_resolver.set_insert_position(block->lir(), 1);
1862 move_resolver.resolve_and_append_moves();
1863 }
1864 }
1865
1866
1867 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1868 if (interval_at(reg_num) == NULL) {
1869 // if a phi function is never used, no interval is created -> ignore this
1870 return;
1871 }
1872
1873 // the computation of to_interval is equal to resolve_collect_mappings,
1874 // but from_interval is more complicated because of phi functions
1875 BlockBegin* to_block = handler->entry_block();
1876 Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1877
1878 if (phi != NULL) {
1879 // phi function of the exception entry block
1880 // no moves are created for this phi function in the LIR_Generator, so the
1881 // interval at the throwing instruction must be searched using the operands
1882 // of the phi function
1883 Value from_value = phi->operand_at(handler->phi_operand());
1884
1885 // with phi functions it can happen that the same from_value is used in
1886 // multiple mappings, so notify move-resolver that this is allowed
1887 move_resolver.set_multiple_reads_allowed();
1888
1889 Constant* con = from_value->as_Constant();
1890 if (con != NULL && !con->is_pinned()) {
1891 // unpinned constants may have no register, so add mapping from constant to interval
1892 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1893 } else {
1894 // search split child at the throwing op_id
1895 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1896 move_resolver.add_mapping(from_interval, to_interval);
1897 }
1898
1899 } else {
1900 // no phi function, so use reg_num also for from_interval
1901 // search split child at the throwing op_id
1902 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1903 if (from_interval != to_interval) {
1904 // optimization to reduce number of moves: when to_interval is on stack and
1905 // the stack slot is known to be always correct, then no move is necessary
1906 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1907 move_resolver.add_mapping(from_interval, to_interval);
1908 }
1909 }
1910 }
1911 }
1912
1913 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1914 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1915
1916 DEBUG_ONLY(move_resolver.check_empty());
1917 assert(handler->lir_op_id() == -1, "already processed this xhandler");
1918 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1919 assert(handler->entry_code() == NULL, "code already present");
1920
1921 // visit all registers where the live_in bit is set
1922 BlockBegin* block = handler->entry_block();
1923 int size = live_set_size();
1924 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1925 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1926 }
1927
1928 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1929 for_each_phi_fun(block, phi,
1930 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1931 );
1932
1933 if (move_resolver.has_mappings()) {
1934 LIR_List* entry_code = new LIR_List(compilation());
1935 move_resolver.set_insert_position(entry_code, 0);
1936 move_resolver.resolve_and_append_moves();
1937
1938 entry_code->jump(handler->entry_block());
1939 handler->set_entry_code(entry_code);
1940 }
1941 }
1942
1943
1944 void LinearScan::resolve_exception_handlers() {
1945 MoveResolver move_resolver(this);
1946 LIR_OpVisitState visitor;
1947 int num_blocks = block_count();
1948
1949 int i;
1950 for (i = 0; i < num_blocks; i++) {
1951 BlockBegin* block = block_at(i);
1952 if (block->is_set(BlockBegin::exception_entry_flag)) {
1953 resolve_exception_entry(block, move_resolver);
1954 }
1955 }
1956
1957 for (i = 0; i < num_blocks; i++) {
1958 BlockBegin* block = block_at(i);
1959 LIR_List* ops = block->lir();
1960 int num_ops = ops->length();
1961
1962 // iterate all instructions of the block. skip the first because it is always a label
1963 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
1964 for (int j = 1; j < num_ops; j++) {
1965 LIR_Op* op = ops->at(j);
1966 int op_id = op->id();
1967
1968 if (op_id != -1 && has_info(op_id)) {
1969 // visit operation to collect all operands
1970 visitor.visit(op);
1971 assert(visitor.info_count() > 0, "should not visit otherwise");
1972
1973 XHandlers* xhandlers = visitor.all_xhandler();
1974 int n = xhandlers->length();
1975 for (int k = 0; k < n; k++) {
1976 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
1977 }
1978
1979 #ifdef ASSERT
1980 } else {
1981 visitor.visit(op);
1982 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
1983 #endif
1984 }
1985 }
1986 }
1987 }
1988
1989
1990 // ********** Phase 7: assign register numbers back to LIR
1991 // (includes computation of debug information and oop maps)
1992
1993 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
1994 VMReg reg = interval->cached_vm_reg();
1995 if (!reg->is_valid() ) {
1996 reg = vm_reg_for_operand(operand_for_interval(interval));
1997 interval->set_cached_vm_reg(reg);
1998 }
1999 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2000 return reg;
2001 }
2002
2003 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2004 assert(opr->is_oop(), "currently only implemented for oop operands");
2005 return frame_map()->regname(opr);
2006 }
2007
2008
2009 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2010 LIR_Opr opr = interval->cached_opr();
2011 if (opr->is_illegal()) {
2012 opr = calc_operand_for_interval(interval);
2013 interval->set_cached_opr(opr);
2014 }
2015
2016 assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2017 return opr;
2018 }
2019
2020 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2021 int assigned_reg = interval->assigned_reg();
2022 BasicType type = interval->type();
2023
2024 if (assigned_reg >= nof_regs) {
2025 // stack slot
2026 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2027 return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2028
2029 } else {
2030 // register
2031 switch (type) {
2032 case T_OBJECT: {
2033 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2034 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2035 return LIR_OprFact::single_cpu_oop(assigned_reg);
2036 }
2037
2038 #ifdef __SOFTFP__
2039 case T_FLOAT: // fall through
2040 #endif // __SOFTFP__
2041 case T_INT: {
2042 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2043 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2044 return LIR_OprFact::single_cpu(assigned_reg);
2045 }
2046
2047 #ifdef __SOFTFP__
2048 case T_DOUBLE: // fall through
2049 #endif // __SOFTFP__
2050 case T_LONG: {
2051 int assigned_regHi = interval->assigned_regHi();
2052 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2053 assert(num_physical_regs(T_LONG) == 1 ||
2054 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2055
2056 assert(assigned_reg != assigned_regHi, "invalid allocation");
2057 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2058 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2059 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2060 if (requires_adjacent_regs(T_LONG)) {
2061 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2062 }
2063
2064 #ifdef _LP64
2065 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2066 #else
2067 #if defined(SPARC) || defined(PPC)
2068 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2069 #else
2070 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2071 #endif // SPARC
2072 #endif // LP64
2073 }
2074
2075 #ifndef __SOFTFP__
2076 case T_FLOAT: {
2077 #ifdef X86
2078 if (UseSSE >= 1) {
2079 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2080 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2081 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2082 }
2083 #endif
2084
2085 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2086 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2087 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2088 }
2089
2090 case T_DOUBLE: {
2091 #ifdef X86
2092 if (UseSSE >= 2) {
2093 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2094 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2095 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2096 }
2097 #endif
2098
2099 #ifdef SPARC
2100 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2101 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2102 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2103 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2104 #elif defined(ARM)
2105 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2106 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2107 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2108 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2109 #else
2110 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2111 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2112 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2113 #endif
2114 return result;
2115 }
2116 #endif // __SOFTFP__
2117
2118 default: {
2119 ShouldNotReachHere();
2120 return LIR_OprFact::illegalOpr;
2121 }
2122 }
2123 }
2124 }
2125
2126 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2127 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2128 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2129 }
2130
2131 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2132 assert(opr->is_virtual(), "should not call this otherwise");
2133
2134 Interval* interval = interval_at(opr->vreg_number());
2135 assert(interval != NULL, "interval must exist");
2136
2137 if (op_id != -1) {
2138 #ifdef ASSERT
2139 BlockBegin* block = block_of_op_with_id(op_id);
2140 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2141 // check if spill moves could have been appended at the end of this block, but
2142 // before the branch instruction. So the split child information for this branch would
2143 // be incorrect.
2144 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2145 if (branch != NULL) {
2146 if (block->live_out().at(opr->vreg_number())) {
2147 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2148 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2149 }
2150 }
2151 }
2152 #endif
2153
2154 // operands are not changed when an interval is split during allocation,
2155 // so search the right interval here
2156 interval = split_child_at_op_id(interval, op_id, mode);
2157 }
2158
2159 LIR_Opr res = operand_for_interval(interval);
2160
2161 #ifdef X86
2162 // new semantic for is_last_use: not only set on definite end of interval,
2163 // but also before hole
2164 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2165 // last use information is completely correct
2166 // information is only needed for fpu stack allocation
2167 if (res->is_fpu_register()) {
2168 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2169 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2170 res = res->make_last_use();
2171 }
2172 }
2173 #endif
2174
2175 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2176
2177 return res;
2178 }
2179
2180
2181 #ifdef ASSERT
2182 // some methods used to check correctness of debug information
2183
2184 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2185 if (values == NULL) {
2186 return;
2187 }
2188
2189 for (int i = 0; i < values->length(); i++) {
2190 ScopeValue* value = values->at(i);
2191
2192 if (value->is_location()) {
2193 Location location = ((LocationValue*)value)->location();
2194 assert(location.where() == Location::on_stack, "value is in register");
2195 }
2196 }
2197 }
2198
2199 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2200 if (values == NULL) {
2201 return;
2202 }
2203
2204 for (int i = 0; i < values->length(); i++) {
2205 MonitorValue* value = values->at(i);
2206
2207 if (value->owner()->is_location()) {
2208 Location location = ((LocationValue*)value->owner())->location();
2209 assert(location.where() == Location::on_stack, "owner is in register");
2210 }
2211 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2212 }
2213 }
2214
2215 void assert_equal(Location l1, Location l2) {
2216 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2217 }
2218
2219 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2220 if (v1->is_location()) {
2221 assert(v2->is_location(), "");
2222 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2223 } else if (v1->is_constant_int()) {
2224 assert(v2->is_constant_int(), "");
2225 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2226 } else if (v1->is_constant_double()) {
2227 assert(v2->is_constant_double(), "");
2228 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2229 } else if (v1->is_constant_long()) {
2230 assert(v2->is_constant_long(), "");
2231 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2232 } else if (v1->is_constant_oop()) {
2233 assert(v2->is_constant_oop(), "");
2234 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2235 } else {
2236 ShouldNotReachHere();
2237 }
2238 }
2239
2240 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2241 assert_equal(m1->owner(), m2->owner());
2242 assert_equal(m1->basic_lock(), m2->basic_lock());
2243 }
2244
2245 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2246 assert(d1->scope() == d2->scope(), "not equal");
2247 assert(d1->bci() == d2->bci(), "not equal");
2248
2249 if (d1->locals() != NULL) {
2250 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2251 assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2252 for (int i = 0; i < d1->locals()->length(); i++) {
2253 assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2254 }
2255 } else {
2256 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2257 }
2258
2259 if (d1->expressions() != NULL) {
2260 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2261 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2262 for (int i = 0; i < d1->expressions()->length(); i++) {
2263 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2264 }
2265 } else {
2266 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2267 }
2268
2269 if (d1->monitors() != NULL) {
2270 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2271 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2272 for (int i = 0; i < d1->monitors()->length(); i++) {
2273 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2274 }
2275 } else {
2276 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2277 }
2278
2279 if (d1->caller() != NULL) {
2280 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2281 assert_equal(d1->caller(), d2->caller());
2282 } else {
2283 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2284 }
2285 }
2286
2287 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2288 if (info->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2289 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->bci());
2290 switch (code) {
2291 case Bytecodes::_ifnull : // fall through
2292 case Bytecodes::_ifnonnull : // fall through
2293 case Bytecodes::_ifeq : // fall through
2294 case Bytecodes::_ifne : // fall through
2295 case Bytecodes::_iflt : // fall through
2296 case Bytecodes::_ifge : // fall through
2297 case Bytecodes::_ifgt : // fall through
2298 case Bytecodes::_ifle : // fall through
2299 case Bytecodes::_if_icmpeq : // fall through
2300 case Bytecodes::_if_icmpne : // fall through
2301 case Bytecodes::_if_icmplt : // fall through
2302 case Bytecodes::_if_icmpge : // fall through
2303 case Bytecodes::_if_icmpgt : // fall through
2304 case Bytecodes::_if_icmple : // fall through
2305 case Bytecodes::_if_acmpeq : // fall through
2306 case Bytecodes::_if_acmpne :
2307 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2308 break;
2309 }
2310 }
2311 }
2312
2313 #endif // ASSERT
2314
2315
2316 IntervalWalker* LinearScan::init_compute_oop_maps() {
2317 // setup lists of potential oops for walking
2318 Interval* oop_intervals;
2319 Interval* non_oop_intervals;
2320
2321 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2322
2323 // intervals that have no oops inside need not to be processed
2324 // to ensure a walking until the last instruction id, add a dummy interval
2325 // with a high operation id
2326 non_oop_intervals = new Interval(any_reg);
2327 non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2328
2329 return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2330 }
2331
2332
2333 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2334 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2335
2336 // walk before the current operation -> intervals that start at
2337 // the operation (= output operands of the operation) are not
2338 // included in the oop map
2339 iw->walk_before(op->id());
2340
2341 int frame_size = frame_map()->framesize();
2342 int arg_count = frame_map()->oop_map_arg_count();
2343 OopMap* map = new OopMap(frame_size, arg_count);
2344
2345 // Check if this is a patch site.
2346 bool is_patch_info = false;
2347 if (op->code() == lir_move) {
2348 assert(!is_call_site, "move must not be a call site");
2349 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2350 LIR_Op1* move = (LIR_Op1*)op;
2351
2352 is_patch_info = move->patch_code() != lir_patch_none;
2353 }
2354
2355 // Iterate through active intervals
2356 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2357 int assigned_reg = interval->assigned_reg();
2358
2359 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2360 assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2361 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2362
2363 // Check if this range covers the instruction. Intervals that
2364 // start or end at the current operation are not included in the
2365 // oop map, except in the case of patching moves. For patching
2366 // moves, any intervals which end at this instruction are included
2367 // in the oop map since we may safepoint while doing the patch
2368 // before we've consumed the inputs.
2369 if (is_patch_info || op->id() < interval->current_to()) {
2370
2371 // caller-save registers must not be included into oop-maps at calls
2372 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2373
2374 VMReg name = vm_reg_for_interval(interval);
2375 map->set_oop(name);
2376
2377 // Spill optimization: when the stack value is guaranteed to be always correct,
2378 // then it must be added to the oop map even if the interval is currently in a register
2379 if (interval->always_in_memory() &&
2380 op->id() > interval->spill_definition_pos() &&
2381 interval->assigned_reg() != interval->canonical_spill_slot()) {
2382 assert(interval->spill_definition_pos() > 0, "position not set correctly");
2383 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2384 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2385
2386 map->set_oop(frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2387 }
2388 }
2389 }
2390
2391 // add oops from lock stack
2392 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2393 int locks_count = info->stack()->locks_size();
2394 for (int i = 0; i < locks_count; i++) {
2395 map->set_oop(frame_map()->monitor_object_regname(i));
2396 }
2397
2398 return map;
2399 }
2400
2401
2402 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2403 assert(visitor.info_count() > 0, "no oop map needed");
2404
2405 // compute oop_map only for first CodeEmitInfo
2406 // because it is (in most cases) equal for all other infos of the same operation
2407 CodeEmitInfo* first_info = visitor.info_at(0);
2408 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2409
2410 for (int i = 0; i < visitor.info_count(); i++) {
2411 CodeEmitInfo* info = visitor.info_at(i);
2412 OopMap* oop_map = first_oop_map;
2413
2414 if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2415 // this info has a different number of locks then the precomputed oop map
2416 // (possible for lock and unlock instructions) -> compute oop map with
2417 // correct lock information
2418 oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2419 }
2420
2421 if (info->_oop_map == NULL) {
2422 info->_oop_map = oop_map;
2423 } else {
2424 // a CodeEmitInfo can not be shared between different LIR-instructions
2425 // because interval splitting can occur anywhere between two instructions
2426 // and so the oop maps must be different
2427 // -> check if the already set oop_map is exactly the one calculated for this operation
2428 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2429 }
2430 }
2431 }
2432
2433
2434 // frequently used constants
2435 ConstantOopWriteValue LinearScan::_oop_null_scope_value = ConstantOopWriteValue(NULL);
2436 ConstantIntValue LinearScan::_int_m1_scope_value = ConstantIntValue(-1);
2437 ConstantIntValue LinearScan::_int_0_scope_value = ConstantIntValue(0);
2438 ConstantIntValue LinearScan::_int_1_scope_value = ConstantIntValue(1);
2439 ConstantIntValue LinearScan::_int_2_scope_value = ConstantIntValue(2);
2440 LocationValue _illegal_value = LocationValue(Location());
2441
2442 void LinearScan::init_compute_debug_info() {
2443 // cache for frequently used scope values
2444 // (cpu registers and stack slots)
2445 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
2446 }
2447
2448 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2449 Location loc;
2450 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2451 bailout("too large frame");
2452 }
2453 ScopeValue* object_scope_value = new LocationValue(loc);
2454
2455 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2456 bailout("too large frame");
2457 }
2458 return new MonitorValue(object_scope_value, loc);
2459 }
2460
2461 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2462 Location loc;
2463 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2464 bailout("too large frame");
2465 }
2466 return new LocationValue(loc);
2467 }
2468
2469
2470 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2471 assert(opr->is_constant(), "should not be called otherwise");
2472
2473 LIR_Const* c = opr->as_constant_ptr();
2474 BasicType t = c->type();
2475 switch (t) {
2476 case T_OBJECT: {
2477 jobject value = c->as_jobject();
2478 if (value == NULL) {
2479 scope_values->append(&_oop_null_scope_value);
2480 } else {
2481 scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2482 }
2483 return 1;
2484 }
2485
2486 case T_INT: // fall through
2487 case T_FLOAT: {
2488 int value = c->as_jint_bits();
2489 switch (value) {
2490 case -1: scope_values->append(&_int_m1_scope_value); break;
2491 case 0: scope_values->append(&_int_0_scope_value); break;
2492 case 1: scope_values->append(&_int_1_scope_value); break;
2493 case 2: scope_values->append(&_int_2_scope_value); break;
2494 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2495 }
2496 return 1;
2497 }
2498
2499 case T_LONG: // fall through
2500 case T_DOUBLE: {
2501 #ifdef _LP64
2502 scope_values->append(&_int_0_scope_value);
2503 scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2504 #else
2505 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2506 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2507 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2508 } else {
2509 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2510 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2511 }
2512 #endif
2513 return 2;
2514 }
2515
2516 case T_ADDRESS: {
2517 #ifdef _LP64
2518 scope_values->append(new ConstantLongValue(c->as_jint()));
2519 #else
2520 scope_values->append(new ConstantIntValue(c->as_jint()));
2521 #endif
2522 return 1;
2523 }
2524
2525 default:
2526 ShouldNotReachHere();
2527 return -1;
2528 }
2529 }
2530
2531 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2532 if (opr->is_single_stack()) {
2533 int stack_idx = opr->single_stack_ix();
2534 bool is_oop = opr->is_oop_register();
2535 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2536
2537 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2538 if (sv == NULL) {
2539 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2540 sv = location_for_name(stack_idx, loc_type);
2541 _scope_value_cache.at_put(cache_idx, sv);
2542 }
2543
2544 // check if cached value is correct
2545 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2546
2547 scope_values->append(sv);
2548 return 1;
2549
2550 } else if (opr->is_single_cpu()) {
2551 bool is_oop = opr->is_oop_register();
2552 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2553 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2554
2555 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2556 if (sv == NULL) {
2557 Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2558 VMReg rname = frame_map()->regname(opr);
2559 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2560 _scope_value_cache.at_put(cache_idx, sv);
2561 }
2562
2563 // check if cached value is correct
2564 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2565
2566 scope_values->append(sv);
2567 return 1;
2568
2569 #ifdef X86
2570 } else if (opr->is_single_xmm()) {
2571 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2572 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2573
2574 scope_values->append(sv);
2575 return 1;
2576 #endif
2577
2578 } else if (opr->is_single_fpu()) {
2579 #ifdef X86
2580 // the exact location of fpu stack values is only known
2581 // during fpu stack allocation, so the stack allocator object
2582 // must be present
2583 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2584 assert(_fpu_stack_allocator != NULL, "must be present");
2585 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2586 #endif
2587
2588 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2589 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2590 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2591
2592 scope_values->append(sv);
2593 return 1;
2594
2595 } else {
2596 // double-size operands
2597
2598 ScopeValue* first;
2599 ScopeValue* second;
2600
2601 if (opr->is_double_stack()) {
2602 #ifdef _LP64
2603 Location loc1;
2604 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2605 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2606 bailout("too large frame");
2607 }
2608 // Does this reverse on x86 vs. sparc?
2609 first = new LocationValue(loc1);
2610 second = &_int_0_scope_value;
2611 #else
2612 Location loc1, loc2;
2613 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2614 bailout("too large frame");
2615 }
2616 first = new LocationValue(loc1);
2617 second = new LocationValue(loc2);
2618 #endif // _LP64
2619
2620 } else if (opr->is_double_cpu()) {
2621 #ifdef _LP64
2622 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2623 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2624 second = &_int_0_scope_value;
2625 #else
2626 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2627 VMReg rname_second = opr->as_register_hi()->as_VMReg();
2628
2629 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2630 // lo/hi and swapped relative to first and second, so swap them
2631 VMReg tmp = rname_first;
2632 rname_first = rname_second;
2633 rname_second = tmp;
2634 }
2635
2636 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2637 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2638 #endif //_LP64
2639
2640
2641 #ifdef X86
2642 } else if (opr->is_double_xmm()) {
2643 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2644 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
2645 # ifdef _LP64
2646 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2647 second = &_int_0_scope_value;
2648 # else
2649 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2650 // %%% This is probably a waste but we'll keep things as they were for now
2651 if (true) {
2652 VMReg rname_second = rname_first->next();
2653 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2654 }
2655 # endif
2656 #endif
2657
2658 } else if (opr->is_double_fpu()) {
2659 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2660 // the double as float registers in the native ordering. On X86,
2661 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2662 // the low-order word of the double and fpu_regnrLo + 1 is the
2663 // name for the other half. *first and *second must represent the
2664 // least and most significant words, respectively.
2665
2666 #ifdef X86
2667 // the exact location of fpu stack values is only known
2668 // during fpu stack allocation, so the stack allocator object
2669 // must be present
2670 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2671 assert(_fpu_stack_allocator != NULL, "must be present");
2672 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2673
2674 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2675 #endif
2676 #ifdef SPARC
2677 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2678 #endif
2679 #ifdef ARM
2680 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2681 #endif
2682 #ifdef PPC
2683 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2684 #endif
2685
2686 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2687 #ifdef _LP64
2688 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2689 second = &_int_0_scope_value;
2690 #else
2691 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2692 // %%% This is probably a waste but we'll keep things as they were for now
2693 if (true) {
2694 VMReg rname_second = rname_first->next();
2695 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2696 }
2697 #endif
2698
2699 } else {
2700 ShouldNotReachHere();
2701 first = NULL;
2702 second = NULL;
2703 }
2704
2705 assert(first != NULL && second != NULL, "must be set");
2706 // The convention the interpreter uses is that the second local
2707 // holds the first raw word of the native double representation.
2708 // This is actually reasonable, since locals and stack arrays
2709 // grow downwards in all implementations.
2710 // (If, on some machine, the interpreter's Java locals or stack
2711 // were to grow upwards, the embedded doubles would be word-swapped.)
2712 scope_values->append(second);
2713 scope_values->append(first);
2714 return 2;
2715 }
2716 }
2717
2718
2719 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2720 if (value != NULL) {
2721 LIR_Opr opr = value->operand();
2722 Constant* con = value->as_Constant();
2723
2724 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2725 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2726
2727 if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2728 // Unpinned constants may have a virtual operand for a part of the lifetime
2729 // or may be illegal when it was optimized away,
2730 // so always use a constant operand
2731 opr = LIR_OprFact::value_type(con->type());
2732 }
2733 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2734
2735 if (opr->is_virtual()) {
2736 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2737
2738 BlockBegin* block = block_of_op_with_id(op_id);
2739 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2740 // generating debug information for the last instruction of a block.
2741 // if this instruction is a branch, spill moves are inserted before this branch
2742 // and so the wrong operand would be returned (spill moves at block boundaries are not
2743 // considered in the live ranges of intervals)
2744 // Solution: use the first op_id of the branch target block instead.
2745 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2746 if (block->live_out().at(opr->vreg_number())) {
2747 op_id = block->sux_at(0)->first_lir_instruction_id();
2748 mode = LIR_OpVisitState::outputMode;
2749 }
2750 }
2751 }
2752
2753 // Get current location of operand
2754 // The operand must be live because debug information is considered when building the intervals
2755 // if the interval is not live, color_lir_opr will cause an assertion failure
2756 opr = color_lir_opr(opr, op_id, mode);
2757 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2758
2759 // Append to ScopeValue array
2760 return append_scope_value_for_operand(opr, scope_values);
2761
2762 } else {
2763 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2764 assert(opr->is_constant(), "operand must be constant");
2765
2766 return append_scope_value_for_constant(opr, scope_values);
2767 }
2768 } else {
2769 // append a dummy value because real value not needed
2770 scope_values->append(&_illegal_value);
2771 return 1;
2772 }
2773 }
2774
2775
2776 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state, int cur_bci, int stack_end, int locks_end) {
2777 IRScopeDebugInfo* caller_debug_info = NULL;
2778 int stack_begin, locks_begin;
2779
2780 ValueStack* caller_state = cur_scope->caller_state();
2781 if (caller_state != NULL) {
2782 // process recursively to compute outermost scope first
2783 stack_begin = caller_state->stack_size();
2784 locks_begin = caller_state->locks_size();
2785 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state, cur_scope->caller_bci(), stack_begin, locks_begin);
2786 } else {
2787 stack_begin = 0;
2788 locks_begin = 0;
2789 }
2790
2791 // initialize these to null.
2792 // If we don't need deopt info or there are no locals, expressions or monitors,
2793 // then these get recorded as no information and avoids the allocation of 0 length arrays.
2794 GrowableArray<ScopeValue*>* locals = NULL;
2795 GrowableArray<ScopeValue*>* expressions = NULL;
2796 GrowableArray<MonitorValue*>* monitors = NULL;
2797
2798 // describe local variable values
2799 int nof_locals = cur_scope->method()->max_locals();
2800 if (nof_locals > 0) {
2801 locals = new GrowableArray<ScopeValue*>(nof_locals);
2802
2803 int pos = 0;
2804 while (pos < nof_locals) {
2805 assert(pos < cur_state->locals_size(), "why not?");
2806
2807 Value local = cur_state->local_at(pos);
2808 pos += append_scope_value(op_id, local, locals);
2809
2810 assert(locals->length() == pos, "must match");
2811 }
2812 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2813 assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2814 }
2815
2816
2817 // describe expression stack
2818 //
2819 // When we inline methods containing exception handlers, the
2820 // "lock_stacks" are changed to preserve expression stack values
2821 // in caller scopes when exception handlers are present. This
2822 // can cause callee stacks to be smaller than caller stacks.
2823 if (stack_end > innermost_state->stack_size()) {
2824 stack_end = innermost_state->stack_size();
2825 }
2826
2827
2828
2829 int nof_stack = stack_end - stack_begin;
2830 if (nof_stack > 0) {
2831 expressions = new GrowableArray<ScopeValue*>(nof_stack);
2832
2833 int pos = stack_begin;
2834 while (pos < stack_end) {
2835 Value expression = innermost_state->stack_at_inc(pos);
2836 append_scope_value(op_id, expression, expressions);
2837
2838 assert(expressions->length() + stack_begin == pos, "must match");
2839 }
2840 }
2841
2842 // describe monitors
2843 assert(locks_begin <= locks_end, "error in scope iteration");
2844 int nof_locks = locks_end - locks_begin;
2845 if (nof_locks > 0) {
2846 monitors = new GrowableArray<MonitorValue*>(nof_locks);
2847 for (int i = locks_begin; i < locks_end; i++) {
2848 monitors->append(location_for_monitor_index(i));
2849 }
2850 }
2851
2852 return new IRScopeDebugInfo(cur_scope, cur_bci, locals, expressions, monitors, caller_debug_info);
2853 }
2854
2855
2856 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2857 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2858
2859 IRScope* innermost_scope = info->scope();
2860 ValueStack* innermost_state = info->stack();
2861
2862 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2863
2864 int stack_end = innermost_state->stack_size();
2865 int locks_end = innermost_state->locks_size();
2866
2867 DEBUG_ONLY(check_stack_depth(info, stack_end));
2868
2869 if (info->_scope_debug_info == NULL) {
2870 // compute debug information
2871 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state, info->bci(), stack_end, locks_end);
2872 } else {
2873 // debug information already set. Check that it is correct from the current point of view
2874 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state, info->bci(), stack_end, locks_end)));
2875 }
2876 }
2877
2878
2879 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2880 LIR_OpVisitState visitor;
2881 int num_inst = instructions->length();
2882 bool has_dead = false;
2883
2884 for (int j = 0; j < num_inst; j++) {
2885 LIR_Op* op = instructions->at(j);
2886 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves
2887 has_dead = true;
2888 continue;
2889 }
2890 int op_id = op->id();
2891
2892 // visit instruction to get list of operands
2893 visitor.visit(op);
2894
2895 // iterate all modes of the visitor and process all virtual operands
2896 for_each_visitor_mode(mode) {
2897 int n = visitor.opr_count(mode);
2898 for (int k = 0; k < n; k++) {
2899 LIR_Opr opr = visitor.opr_at(mode, k);
2900 if (opr->is_virtual_register()) {
2901 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2902 }
2903 }
2904 }
2905
2906 if (visitor.info_count() > 0) {
2907 // exception handling
2908 if (compilation()->has_exception_handlers()) {
2909 XHandlers* xhandlers = visitor.all_xhandler();
2910 int n = xhandlers->length();
2911 for (int k = 0; k < n; k++) {
2912 XHandler* handler = xhandlers->handler_at(k);
2913 if (handler->entry_code() != NULL) {
2914 assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2915 }
2916 }
2917 } else {
2918 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2919 }
2920
2921 // compute oop map
2922 assert(iw != NULL, "needed for compute_oop_map");
2923 compute_oop_map(iw, visitor, op);
2924
2925 // compute debug information
2926 if (!use_fpu_stack_allocation()) {
2927 // compute debug information if fpu stack allocation is not needed.
2928 // when fpu stack allocation is needed, the debug information can not
2929 // be computed here because the exact location of fpu operands is not known
2930 // -> debug information is created inside the fpu stack allocator
2931 int n = visitor.info_count();
2932 for (int k = 0; k < n; k++) {
2933 compute_debug_info(visitor.info_at(k), op_id);
2934 }
2935 }
2936 }
2937
2938 #ifdef ASSERT
2939 // make sure we haven't made the op invalid.
2940 op->verify();
2941 #endif
2942
2943 // remove useless moves
2944 if (op->code() == lir_move) {
2945 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2946 LIR_Op1* move = (LIR_Op1*)op;
2947 LIR_Opr src = move->in_opr();
2948 LIR_Opr dst = move->result_opr();
2949 if (dst == src ||
2950 !dst->is_pointer() && !src->is_pointer() &&
2951 src->is_same_register(dst)) {
2952 instructions->at_put(j, NULL);
2953 has_dead = true;
2954 }
2955 }
2956 }
2957
2958 if (has_dead) {
2959 // iterate all instructions of the block and remove all null-values.
2960 int insert_point = 0;
2961 for (int j = 0; j < num_inst; j++) {
2962 LIR_Op* op = instructions->at(j);
2963 if (op != NULL) {
2964 if (insert_point != j) {
2965 instructions->at_put(insert_point, op);
2966 }
2967 insert_point++;
2968 }
2969 }
2970 instructions->truncate(insert_point);
2971 }
2972 }
2973
2974 void LinearScan::assign_reg_num() {
2975 TIME_LINEAR_SCAN(timer_assign_reg_num);
2976
2977 init_compute_debug_info();
2978 IntervalWalker* iw = init_compute_oop_maps();
2979
2980 int num_blocks = block_count();
2981 for (int i = 0; i < num_blocks; i++) {
2982 BlockBegin* block = block_at(i);
2983 assign_reg_num(block->lir()->instructions_list(), iw);
2984 }
2985 }
2986
2987
2988 void LinearScan::do_linear_scan() {
2989 NOT_PRODUCT(_total_timer.begin_method());
2990
2991 number_instructions();
2992
2993 NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
2994
2995 compute_local_live_sets();
2996 compute_global_live_sets();
2997 CHECK_BAILOUT();
2998
2999 build_intervals();
3000 CHECK_BAILOUT();
3001 sort_intervals_before_allocation();
3002
3003 NOT_PRODUCT(print_intervals("Before Register Allocation"));
3004 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3005
3006 allocate_registers();
3007 CHECK_BAILOUT();
3008
3009 resolve_data_flow();
3010 if (compilation()->has_exception_handlers()) {
3011 resolve_exception_handlers();
3012 }
3013 // fill in number of spill slots into frame_map
3014 propagate_spill_slots();
3015 CHECK_BAILOUT();
3016
3017 NOT_PRODUCT(print_intervals("After Register Allocation"));
3018 NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3019
3020 sort_intervals_after_allocation();
3021
3022 DEBUG_ONLY(verify());
3023
3024 eliminate_spill_moves();
3025 assign_reg_num();
3026 CHECK_BAILOUT();
3027
3028 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3029 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3030
3031 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3032
3033 if (use_fpu_stack_allocation()) {
3034 allocate_fpu_stack(); // Only has effect on Intel
3035 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3036 }
3037 }
3038
3039 { TIME_LINEAR_SCAN(timer_optimize_lir);
3040
3041 EdgeMoveOptimizer::optimize(ir()->code());
3042 ControlFlowOptimizer::optimize(ir()->code());
3043 // check that cfg is still correct after optimizations
3044 ir()->verify();
3045 }
3046
3047 NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3048 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3049 NOT_PRODUCT(_total_timer.end_method(this));
3050 }
3051
3052
3053 // ********** Printing functions
3054
3055 #ifndef PRODUCT
3056
3057 void LinearScan::print_timers(double total) {
3058 _total_timer.print(total);
3059 }
3060
3061 void LinearScan::print_statistics() {
3062 _stat_before_alloc.print("before allocation");
3063 _stat_after_asign.print("after assignment of register");
3064 _stat_final.print("after optimization");
3065 }
3066
3067 void LinearScan::print_bitmap(BitMap& b) {
3068 for (unsigned int i = 0; i < b.size(); i++) {
3069 if (b.at(i)) tty->print("%d ", i);
3070 }
3071 tty->cr();
3072 }
3073
3074 void LinearScan::print_intervals(const char* label) {
3075 if (TraceLinearScanLevel >= 1) {
3076 int i;
3077 tty->cr();
3078 tty->print_cr("%s", label);
3079
3080 for (i = 0; i < interval_count(); i++) {
3081 Interval* interval = interval_at(i);
3082 if (interval != NULL) {
3083 interval->print();
3084 }
3085 }
3086
3087 tty->cr();
3088 tty->print_cr("--- Basic Blocks ---");
3089 for (i = 0; i < block_count(); i++) {
3090 BlockBegin* block = block_at(i);
3091 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3092 }
3093 tty->cr();
3094 tty->cr();
3095 }
3096
3097 if (PrintCFGToFile) {
3098 CFGPrinter::print_intervals(&_intervals, label);
3099 }
3100 }
3101
3102 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3103 if (TraceLinearScanLevel >= level) {
3104 tty->cr();
3105 tty->print_cr("%s", label);
3106 print_LIR(ir()->linear_scan_order());
3107 tty->cr();
3108 }
3109
3110 if (level == 1 && PrintCFGToFile) {
3111 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3112 }
3113 }
3114
3115 #endif //PRODUCT
3116
3117
3118 // ********** verification functions for allocation
3119 // (check that all intervals have a correct register and that no registers are overwritten)
3120 #ifdef ASSERT
3121
3122 void LinearScan::verify() {
3123 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3124 verify_intervals();
3125
3126 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3127 verify_no_oops_in_fixed_intervals();
3128
3129 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3130 verify_constants();
3131
3132 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3133 verify_registers();
3134
3135 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3136 }
3137
3138 void LinearScan::verify_intervals() {
3139 int len = interval_count();
3140 bool has_error = false;
3141
3142 for (int i = 0; i < len; i++) {
3143 Interval* i1 = interval_at(i);
3144 if (i1 == NULL) continue;
3145
3146 i1->check_split_children();
3147
3148 if (i1->reg_num() != i) {
3149 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3150 has_error = true;
3151 }
3152
3153 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3154 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3155 has_error = true;
3156 }
3157
3158 if (i1->assigned_reg() == any_reg) {
3159 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3160 has_error = true;
3161 }
3162
3163 if (i1->assigned_reg() == i1->assigned_regHi()) {
3164 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3165 has_error = true;
3166 }
3167
3168 if (!is_processed_reg_num(i1->assigned_reg())) {
3169 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3170 has_error = true;
3171 }
3172
3173 if (i1->first() == Range::end()) {
3174 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3175 has_error = true;
3176 }
3177
3178 for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3179 if (r->from() >= r->to()) {
3180 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3181 has_error = true;
3182 }
3183 }
3184
3185 for (int j = i + 1; j < len; j++) {
3186 Interval* i2 = interval_at(j);
3187 if (i2 == NULL) continue;
3188
3189 // special intervals that are created in MoveResolver
3190 // -> ignore them because the range information has no meaning there
3191 if (i1->from() == 1 && i1->to() == 2) continue;
3192 if (i2->from() == 1 && i2->to() == 2) continue;
3193
3194 int r1 = i1->assigned_reg();
3195 int r1Hi = i1->assigned_regHi();
3196 int r2 = i2->assigned_reg();
3197 int r2Hi = i2->assigned_regHi();
3198 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3199 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3200 i1->print(); tty->cr();
3201 i2->print(); tty->cr();
3202 has_error = true;
3203 }
3204 }
3205 }
3206
3207 assert(has_error == false, "register allocation invalid");
3208 }
3209
3210
3211 void LinearScan::verify_no_oops_in_fixed_intervals() {
3212 Interval* fixed_intervals;
3213 Interval* other_intervals;
3214 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3215
3216 // to ensure a walking until the last instruction id, add a dummy interval
3217 // with a high operation id
3218 other_intervals = new Interval(any_reg);
3219 other_intervals->add_range(max_jint - 2, max_jint - 1);
3220 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3221
3222 LIR_OpVisitState visitor;
3223 for (int i = 0; i < block_count(); i++) {
3224 BlockBegin* block = block_at(i);
3225
3226 LIR_OpList* instructions = block->lir()->instructions_list();
3227
3228 for (int j = 0; j < instructions->length(); j++) {
3229 LIR_Op* op = instructions->at(j);
3230 int op_id = op->id();
3231
3232 visitor.visit(op);
3233
3234 if (visitor.info_count() > 0) {
3235 iw->walk_before(op->id());
3236 bool check_live = true;
3237 if (op->code() == lir_move) {
3238 LIR_Op1* move = (LIR_Op1*)op;
3239 check_live = (move->patch_code() == lir_patch_none);
3240 }
3241 LIR_OpBranch* branch = op->as_OpBranch();
3242 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3243 // Don't bother checking the stub in this case since the
3244 // exception stub will never return to normal control flow.
3245 check_live = false;
3246 }
3247
3248 // Make sure none of the fixed registers is live across an
3249 // oopmap since we can't handle that correctly.
3250 if (check_live) {
3251 for (Interval* interval = iw->active_first(fixedKind);
3252 interval != Interval::end();
3253 interval = interval->next()) {
3254 if (interval->current_to() > op->id() + 1) {
3255 // This interval is live out of this op so make sure
3256 // that this interval represents some value that's
3257 // referenced by this op either as an input or output.
3258 bool ok = false;
3259 for_each_visitor_mode(mode) {
3260 int n = visitor.opr_count(mode);
3261 for (int k = 0; k < n; k++) {
3262 LIR_Opr opr = visitor.opr_at(mode, k);
3263 if (opr->is_fixed_cpu()) {
3264 if (interval_at(reg_num(opr)) == interval) {
3265 ok = true;
3266 break;
3267 }
3268 int hi = reg_numHi(opr);
3269 if (hi != -1 && interval_at(hi) == interval) {
3270 ok = true;
3271 break;
3272 }
3273 }
3274 }
3275 }
3276 assert(ok, "fixed intervals should never be live across an oopmap point");
3277 }
3278 }
3279 }
3280 }
3281
3282 // oop-maps at calls do not contain registers, so check is not needed
3283 if (!visitor.has_call()) {
3284
3285 for_each_visitor_mode(mode) {
3286 int n = visitor.opr_count(mode);
3287 for (int k = 0; k < n; k++) {
3288 LIR_Opr opr = visitor.opr_at(mode, k);
3289
3290 if (opr->is_fixed_cpu() && opr->is_oop()) {
3291 // operand is a non-virtual cpu register and contains an oop
3292 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3293
3294 Interval* interval = interval_at(reg_num(opr));
3295 assert(interval != NULL, "no interval");
3296
3297 if (mode == LIR_OpVisitState::inputMode) {
3298 if (interval->to() >= op_id + 1) {
3299 assert(interval->to() < op_id + 2 ||
3300 interval->has_hole_between(op_id, op_id + 2),
3301 "oop input operand live after instruction");
3302 }
3303 } else if (mode == LIR_OpVisitState::outputMode) {
3304 if (interval->from() <= op_id - 1) {
3305 assert(interval->has_hole_between(op_id - 1, op_id),
3306 "oop input operand live after instruction");
3307 }
3308 }
3309 }
3310 }
3311 }
3312 }
3313 }
3314 }
3315 }
3316
3317
3318 void LinearScan::verify_constants() {
3319 int num_regs = num_virtual_regs();
3320 int size = live_set_size();
3321 int num_blocks = block_count();
3322
3323 for (int i = 0; i < num_blocks; i++) {
3324 BlockBegin* block = block_at(i);
3325 BitMap live_at_edge = block->live_in();
3326
3327 // visit all registers where the live_at_edge bit is set
3328 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3329 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3330
3331 Value value = gen()->instruction_for_vreg(r);
3332
3333 assert(value != NULL, "all intervals live across block boundaries must have Value");
3334 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3335 assert(value->operand()->vreg_number() == r, "register number must match");
3336 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3337 }
3338 }
3339 }
3340
3341
3342 class RegisterVerifier: public StackObj {
3343 private:
3344 LinearScan* _allocator;
3345 BlockList _work_list; // all blocks that must be processed
3346 IntervalsList _saved_states; // saved information of previous check
3347
3348 // simplified access to methods of LinearScan
3349 Compilation* compilation() const { return _allocator->compilation(); }
3350 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); }
3351 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); }
3352
3353 // currently, only registers are processed
3354 int state_size() { return LinearScan::nof_regs; }
3355
3356 // accessors
3357 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3358 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3359 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3360
3361 // helper functions
3362 IntervalList* copy(IntervalList* input_state);
3363 void state_put(IntervalList* input_state, int reg, Interval* interval);
3364 bool check_state(IntervalList* input_state, int reg, Interval* interval);
3365
3366 void process_block(BlockBegin* block);
3367 void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3368 void process_successor(BlockBegin* block, IntervalList* input_state);
3369 void process_operations(LIR_List* ops, IntervalList* input_state);
3370
3371 public:
3372 RegisterVerifier(LinearScan* allocator)
3373 : _allocator(allocator)
3374 , _work_list(16)
3375 , _saved_states(BlockBegin::number_of_blocks(), NULL)
3376 { }
3377
3378 void verify(BlockBegin* start);
3379 };
3380
3381
3382 // entry function from LinearScan that starts the verification
3383 void LinearScan::verify_registers() {
3384 RegisterVerifier verifier(this);
3385 verifier.verify(block_at(0));
3386 }
3387
3388
3389 void RegisterVerifier::verify(BlockBegin* start) {
3390 // setup input registers (method arguments) for first block
3391 IntervalList* input_state = new IntervalList(state_size(), NULL);
3392 CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3393 for (int n = 0; n < args->length(); n++) {
3394 LIR_Opr opr = args->at(n);
3395 if (opr->is_register()) {
3396 Interval* interval = interval_at(reg_num(opr));
3397
3398 if (interval->assigned_reg() < state_size()) {
3399 input_state->at_put(interval->assigned_reg(), interval);
3400 }
3401 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3402 input_state->at_put(interval->assigned_regHi(), interval);
3403 }
3404 }
3405 }
3406
3407 set_state_for_block(start, input_state);
3408 add_to_work_list(start);
3409
3410 // main loop for verification
3411 do {
3412 BlockBegin* block = _work_list.at(0);
3413 _work_list.remove_at(0);
3414
3415 process_block(block);
3416 } while (!_work_list.is_empty());
3417 }
3418
3419 void RegisterVerifier::process_block(BlockBegin* block) {
3420 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3421
3422 // must copy state because it is modified
3423 IntervalList* input_state = copy(state_for_block(block));
3424
3425 if (TraceLinearScanLevel >= 4) {
3426 tty->print_cr("Input-State of intervals:");
3427 tty->print(" ");
3428 for (int i = 0; i < state_size(); i++) {
3429 if (input_state->at(i) != NULL) {
3430 tty->print(" %4d", input_state->at(i)->reg_num());
3431 } else {
3432 tty->print(" __");
3433 }
3434 }
3435 tty->cr();
3436 tty->cr();
3437 }
3438
3439 // process all operations of the block
3440 process_operations(block->lir(), input_state);
3441
3442 // iterate all successors
3443 for (int i = 0; i < block->number_of_sux(); i++) {
3444 process_successor(block->sux_at(i), input_state);
3445 }
3446 }
3447
3448 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3449 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3450
3451 // must copy state because it is modified
3452 input_state = copy(input_state);
3453
3454 if (xhandler->entry_code() != NULL) {
3455 process_operations(xhandler->entry_code(), input_state);
3456 }
3457 process_successor(xhandler->entry_block(), input_state);
3458 }
3459
3460 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3461 IntervalList* saved_state = state_for_block(block);
3462
3463 if (saved_state != NULL) {
3464 // this block was already processed before.
3465 // check if new input_state is consistent with saved_state
3466
3467 bool saved_state_correct = true;
3468 for (int i = 0; i < state_size(); i++) {
3469 if (input_state->at(i) != saved_state->at(i)) {
3470 // current input_state and previous saved_state assume a different
3471 // interval in this register -> assume that this register is invalid
3472 if (saved_state->at(i) != NULL) {
3473 // invalidate old calculation only if it assumed that
3474 // register was valid. when the register was already invalid,
3475 // then the old calculation was correct.
3476 saved_state_correct = false;
3477 saved_state->at_put(i, NULL);
3478
3479 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3480 }
3481 }
3482 }
3483
3484 if (saved_state_correct) {
3485 // already processed block with correct input_state
3486 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3487 } else {
3488 // must re-visit this block
3489 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3490 add_to_work_list(block);
3491 }
3492
3493 } else {
3494 // block was not processed before, so set initial input_state
3495 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3496
3497 set_state_for_block(block, copy(input_state));
3498 add_to_work_list(block);
3499 }
3500 }
3501
3502
3503 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3504 IntervalList* copy_state = new IntervalList(input_state->length());
3505 copy_state->push_all(input_state);
3506 return copy_state;
3507 }
3508
3509 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3510 if (reg != LinearScan::any_reg && reg < state_size()) {
3511 if (interval != NULL) {
3512 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num()));
3513 } else if (input_state->at(reg) != NULL) {
3514 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg));
3515 }
3516
3517 input_state->at_put(reg, interval);
3518 }
3519 }
3520
3521 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3522 if (reg != LinearScan::any_reg && reg < state_size()) {
3523 if (input_state->at(reg) != interval) {
3524 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3525 return true;
3526 }
3527 }
3528 return false;
3529 }
3530
3531 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3532 // visit all instructions of the block
3533 LIR_OpVisitState visitor;
3534 bool has_error = false;
3535
3536 for (int i = 0; i < ops->length(); i++) {
3537 LIR_Op* op = ops->at(i);
3538 visitor.visit(op);
3539
3540 TRACE_LINEAR_SCAN(4, op->print_on(tty));
3541
3542 // check if input operands are correct
3543 int j;
3544 int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3545 for (j = 0; j < n; j++) {
3546 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3547 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3548 Interval* interval = interval_at(reg_num(opr));
3549 if (op->id() != -1) {
3550 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3551 }
3552
3553 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent());
3554 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3555
3556 // When an operand is marked with is_last_use, then the fpu stack allocator
3557 // removes the register from the fpu stack -> the register contains no value
3558 if (opr->is_last_use()) {
3559 state_put(input_state, interval->assigned_reg(), NULL);
3560 state_put(input_state, interval->assigned_regHi(), NULL);
3561 }
3562 }
3563 }
3564
3565 // invalidate all caller save registers at calls
3566 if (visitor.has_call()) {
3567 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs; j++) {
3568 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3569 }
3570 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3571 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3572 }
3573
3574 #ifdef X86
3575 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
3576 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3577 }
3578 #endif
3579 }
3580
3581 // process xhandler before output and temp operands
3582 XHandlers* xhandlers = visitor.all_xhandler();
3583 n = xhandlers->length();
3584 for (int k = 0; k < n; k++) {
3585 process_xhandler(xhandlers->handler_at(k), input_state);
3586 }
3587
3588 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3589 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3590 for (j = 0; j < n; j++) {
3591 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3592 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3593 Interval* interval = interval_at(reg_num(opr));
3594 if (op->id() != -1) {
3595 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3596 }
3597
3598 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3599 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3600 }
3601 }
3602
3603 // set output operands
3604 n = visitor.opr_count(LIR_OpVisitState::outputMode);
3605 for (j = 0; j < n; j++) {
3606 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3607 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3608 Interval* interval = interval_at(reg_num(opr));
3609 if (op->id() != -1) {
3610 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3611 }
3612
3613 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3614 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3615 }
3616 }
3617 }
3618 assert(has_error == false, "Error in register allocation");
3619 }
3620
3621 #endif // ASSERT
3622
3623
3624
3625 // **** Implementation of MoveResolver ******************************
3626
3627 MoveResolver::MoveResolver(LinearScan* allocator) :
3628 _allocator(allocator),
3629 _multiple_reads_allowed(false),
3630 _mapping_from(8),
3631 _mapping_from_opr(8),
3632 _mapping_to(8),
3633 _insert_list(NULL),
3634 _insert_idx(-1),
3635 _insertion_buffer()
3636 {
3637 for (int i = 0; i < LinearScan::nof_regs; i++) {
3638 _register_blocked[i] = 0;
3639 }
3640 DEBUG_ONLY(check_empty());
3641 }
3642
3643
3644 #ifdef ASSERT
3645
3646 void MoveResolver::check_empty() {
3647 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3648 for (int i = 0; i < LinearScan::nof_regs; i++) {
3649 assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3650 }
3651 assert(_multiple_reads_allowed == false, "must have default value");
3652 }
3653
3654 void MoveResolver::verify_before_resolve() {
3655 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3656 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3657 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3658
3659 int i, j;
3660 if (!_multiple_reads_allowed) {
3661 for (i = 0; i < _mapping_from.length(); i++) {
3662 for (j = i + 1; j < _mapping_from.length(); j++) {
3663 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3664 }
3665 }
3666 }
3667
3668 for (i = 0; i < _mapping_to.length(); i++) {
3669 for (j = i + 1; j < _mapping_to.length(); j++) {
3670 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3671 }
3672 }
3673
3674
3675 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3676 used_regs.clear();
3677 if (!_multiple_reads_allowed) {
3678 for (i = 0; i < _mapping_from.length(); i++) {
3679 Interval* it = _mapping_from.at(i);
3680 if (it != NULL) {
3681 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3682 used_regs.set_bit(it->assigned_reg());
3683
3684 if (it->assigned_regHi() != LinearScan::any_reg) {
3685 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3686 used_regs.set_bit(it->assigned_regHi());
3687 }
3688 }
3689 }
3690 }
3691
3692 used_regs.clear();
3693 for (i = 0; i < _mapping_to.length(); i++) {
3694 Interval* it = _mapping_to.at(i);
3695 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3696 used_regs.set_bit(it->assigned_reg());
3697
3698 if (it->assigned_regHi() != LinearScan::any_reg) {
3699 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3700 used_regs.set_bit(it->assigned_regHi());
3701 }
3702 }
3703
3704 used_regs.clear();
3705 for (i = 0; i < _mapping_from.length(); i++) {
3706 Interval* it = _mapping_from.at(i);
3707 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3708 used_regs.set_bit(it->assigned_reg());
3709 }
3710 }
3711 for (i = 0; i < _mapping_to.length(); i++) {
3712 Interval* it = _mapping_to.at(i);
3713 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3714 }
3715 }
3716
3717 #endif // ASSERT
3718
3719
3720 // mark assigned_reg and assigned_regHi of the interval as blocked
3721 void MoveResolver::block_registers(Interval* it) {
3722 int reg = it->assigned_reg();
3723 if (reg < LinearScan::nof_regs) {
3724 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3725 set_register_blocked(reg, 1);
3726 }
3727 reg = it->assigned_regHi();
3728 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3729 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3730 set_register_blocked(reg, 1);
3731 }
3732 }
3733
3734 // mark assigned_reg and assigned_regHi of the interval as unblocked
3735 void MoveResolver::unblock_registers(Interval* it) {
3736 int reg = it->assigned_reg();
3737 if (reg < LinearScan::nof_regs) {
3738 assert(register_blocked(reg) > 0, "register already marked as unused");
3739 set_register_blocked(reg, -1);
3740 }
3741 reg = it->assigned_regHi();
3742 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3743 assert(register_blocked(reg) > 0, "register already marked as unused");
3744 set_register_blocked(reg, -1);
3745 }
3746 }
3747
3748 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3749 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3750 int from_reg = -1;
3751 int from_regHi = -1;
3752 if (from != NULL) {
3753 from_reg = from->assigned_reg();
3754 from_regHi = from->assigned_regHi();
3755 }
3756
3757 int reg = to->assigned_reg();
3758 if (reg < LinearScan::nof_regs) {
3759 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3760 return false;
3761 }
3762 }
3763 reg = to->assigned_regHi();
3764 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3765 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3766 return false;
3767 }
3768 }
3769
3770 return true;
3771 }
3772
3773
3774 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3775 assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3776 _insertion_buffer.init(list);
3777 }
3778
3779 void MoveResolver::append_insertion_buffer() {
3780 if (_insertion_buffer.initialized()) {
3781 _insertion_buffer.lir_list()->append(&_insertion_buffer);
3782 }
3783 assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3784
3785 _insert_list = NULL;
3786 _insert_idx = -1;
3787 }
3788
3789 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3790 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3791 assert(from_interval->type() == to_interval->type(), "move between different types");
3792 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3793 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3794
3795 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3796 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3797
3798 if (!_multiple_reads_allowed) {
3799 // the last_use flag is an optimization for FPU stack allocation. When the same
3800 // input interval is used in more than one move, then it is too difficult to determine
3801 // if this move is really the last use.
3802 from_opr = from_opr->make_last_use();
3803 }
3804 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3805
3806 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3807 }
3808
3809 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3810 assert(from_opr->type() == to_interval->type(), "move between different types");
3811 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3812 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3813
3814 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3815 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3816
3817 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3818 }
3819
3820
3821 void MoveResolver::resolve_mappings() {
3822 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3823 DEBUG_ONLY(verify_before_resolve());
3824
3825 // Block all registers that are used as input operands of a move.
3826 // When a register is blocked, no move to this register is emitted.
3827 // This is necessary for detecting cycles in moves.
3828 int i;
3829 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3830 Interval* from_interval = _mapping_from.at(i);
3831 if (from_interval != NULL) {
3832 block_registers(from_interval);
3833 }
3834 }
3835
3836 int spill_candidate = -1;
3837 while (_mapping_from.length() > 0) {
3838 bool processed_interval = false;
3839
3840 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3841 Interval* from_interval = _mapping_from.at(i);
3842 Interval* to_interval = _mapping_to.at(i);
3843
3844 if (save_to_process_move(from_interval, to_interval)) {
3845 // this inverval can be processed because target is free
3846 if (from_interval != NULL) {
3847 insert_move(from_interval, to_interval);
3848 unblock_registers(from_interval);
3849 } else {
3850 insert_move(_mapping_from_opr.at(i), to_interval);
3851 }
3852 _mapping_from.remove_at(i);
3853 _mapping_from_opr.remove_at(i);
3854 _mapping_to.remove_at(i);
3855
3856 processed_interval = true;
3857 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3858 // this interval cannot be processed now because target is not free
3859 // it starts in a register, so it is a possible candidate for spilling
3860 spill_candidate = i;
3861 }
3862 }
3863
3864 if (!processed_interval) {
3865 // no move could be processed because there is a cycle in the move list
3866 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3867 assert(spill_candidate != -1, "no interval in register for spilling found");
3868
3869 // create a new spill interval and assign a stack slot to it
3870 Interval* from_interval = _mapping_from.at(spill_candidate);
3871 Interval* spill_interval = new Interval(-1);
3872 spill_interval->set_type(from_interval->type());
3873
3874 // add a dummy range because real position is difficult to calculate
3875 // Note: this range is a special case when the integrity of the allocation is checked
3876 spill_interval->add_range(1, 2);
3877
3878 // do not allocate a new spill slot for temporary interval, but
3879 // use spill slot assigned to from_interval. Otherwise moves from
3880 // one stack slot to another can happen (not allowed by LIR_Assembler
3881 int spill_slot = from_interval->canonical_spill_slot();
3882 if (spill_slot < 0) {
3883 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3884 from_interval->set_canonical_spill_slot(spill_slot);
3885 }
3886 spill_interval->assign_reg(spill_slot);
3887 allocator()->append_interval(spill_interval);
3888
3889 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3890
3891 // insert a move from register to stack and update the mapping
3892 insert_move(from_interval, spill_interval);
3893 _mapping_from.at_put(spill_candidate, spill_interval);
3894 unblock_registers(from_interval);
3895 }
3896 }
3897
3898 // reset to default value
3899 _multiple_reads_allowed = false;
3900
3901 // check that all intervals have been processed
3902 DEBUG_ONLY(check_empty());
3903 }
3904
3905
3906 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3907 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3908 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3909
3910 create_insertion_buffer(insert_list);
3911 _insert_list = insert_list;
3912 _insert_idx = insert_idx;
3913 }
3914
3915 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3916 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3917
3918 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3919 // insert position changed -> resolve current mappings
3920 resolve_mappings();
3921 }
3922
3923 if (insert_list != _insert_list) {
3924 // block changed -> append insertion_buffer because it is
3925 // bound to a specific block and create a new insertion_buffer
3926 append_insertion_buffer();
3927 create_insertion_buffer(insert_list);
3928 }
3929
3930 _insert_list = insert_list;
3931 _insert_idx = insert_idx;
3932 }
3933
3934 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
3935 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3936
3937 _mapping_from.append(from_interval);
3938 _mapping_from_opr.append(LIR_OprFact::illegalOpr);
3939 _mapping_to.append(to_interval);
3940 }
3941
3942
3943 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
3944 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3945 assert(from_opr->is_constant(), "only for constants");
3946
3947 _mapping_from.append(NULL);
3948 _mapping_from_opr.append(from_opr);
3949 _mapping_to.append(to_interval);
3950 }
3951
3952 void MoveResolver::resolve_and_append_moves() {
3953 if (has_mappings()) {
3954 resolve_mappings();
3955 }
3956 append_insertion_buffer();
3957 }
3958
3959
3960
3961 // **** Implementation of Range *************************************
3962
3963 Range::Range(int from, int to, Range* next) :
3964 _from(from),
3965 _to(to),
3966 _next(next)
3967 {
3968 }
3969
3970 // initialize sentinel
3971 Range* Range::_end = NULL;
3972 void Range::initialize(Arena* arena) {
3973 _end = new (arena) Range(max_jint, max_jint, NULL);
3974 }
3975
3976 int Range::intersects_at(Range* r2) const {
3977 const Range* r1 = this;
3978
3979 assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
3980 assert(r1 != _end && r2 != _end, "empty ranges not allowed");
3981
3982 do {
3983 if (r1->from() < r2->from()) {
3984 if (r1->to() <= r2->from()) {
3985 r1 = r1->next(); if (r1 == _end) return -1;
3986 } else {
3987 return r2->from();
3988 }
3989 } else if (r2->from() < r1->from()) {
3990 if (r2->to() <= r1->from()) {
3991 r2 = r2->next(); if (r2 == _end) return -1;
3992 } else {
3993 return r1->from();
3994 }
3995 } else { // r1->from() == r2->from()
3996 if (r1->from() == r1->to()) {
3997 r1 = r1->next(); if (r1 == _end) return -1;
3998 } else if (r2->from() == r2->to()) {
3999 r2 = r2->next(); if (r2 == _end) return -1;
4000 } else {
4001 return r1->from();
4002 }
4003 }
4004 } while (true);
4005 }
4006
4007 #ifndef PRODUCT
4008 void Range::print(outputStream* out) const {
4009 out->print("[%d, %d[ ", _from, _to);
4010 }
4011 #endif
4012
4013
4014
4015 // **** Implementation of Interval **********************************
4016
4017 // initialize sentinel
4018 Interval* Interval::_end = NULL;
4019 void Interval::initialize(Arena* arena) {
4020 Range::initialize(arena);
4021 _end = new (arena) Interval(-1);
4022 }
4023
4024 Interval::Interval(int reg_num) :
4025 _reg_num(reg_num),
4026 _type(T_ILLEGAL),
4027 _first(Range::end()),
4028 _use_pos_and_kinds(12),
4029 _current(Range::end()),
4030 _next(_end),
4031 _state(invalidState),
4032 _assigned_reg(LinearScan::any_reg),
4033 _assigned_regHi(LinearScan::any_reg),
4034 _cached_to(-1),
4035 _cached_opr(LIR_OprFact::illegalOpr),
4036 _cached_vm_reg(VMRegImpl::Bad()),
4037 _split_children(0),
4038 _canonical_spill_slot(-1),
4039 _insert_move_when_activated(false),
4040 _register_hint(NULL),
4041 _spill_state(noDefinitionFound),
4042 _spill_definition_pos(-1)
4043 {
4044 _split_parent = this;
4045 _current_split_child = this;
4046 }
4047
4048 int Interval::calc_to() {
4049 assert(_first != Range::end(), "interval has no range");
4050
4051 Range* r = _first;
4052 while (r->next() != Range::end()) {
4053 r = r->next();
4054 }
4055 return r->to();
4056 }
4057
4058
4059 #ifdef ASSERT
4060 // consistency check of split-children
4061 void Interval::check_split_children() {
4062 if (_split_children.length() > 0) {
4063 assert(is_split_parent(), "only split parents can have children");
4064
4065 for (int i = 0; i < _split_children.length(); i++) {
4066 Interval* i1 = _split_children.at(i);
4067
4068 assert(i1->split_parent() == this, "not a split child of this interval");
4069 assert(i1->type() == type(), "must be equal for all split children");
4070 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4071
4072 for (int j = i + 1; j < _split_children.length(); j++) {
4073 Interval* i2 = _split_children.at(j);
4074
4075 assert(i1->reg_num() != i2->reg_num(), "same register number");
4076
4077 if (i1->from() < i2->from()) {
4078 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4079 } else {
4080 assert(i2->from() < i1->from(), "intervals start at same op_id");
4081 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4082 }
4083 }
4084 }
4085 }
4086 }
4087 #endif // ASSERT
4088
4089 Interval* Interval::register_hint(bool search_split_child) const {
4090 if (!search_split_child) {
4091 return _register_hint;
4092 }
4093
4094 if (_register_hint != NULL) {
4095 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4096
4097 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4098 return _register_hint;
4099
4100 } else if (_register_hint->_split_children.length() > 0) {
4101 // search the first split child that has a register assigned
4102 int len = _register_hint->_split_children.length();
4103 for (int i = 0; i < len; i++) {
4104 Interval* cur = _register_hint->_split_children.at(i);
4105
4106 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4107 return cur;
4108 }
4109 }
4110 }
4111 }
4112
4113 // no hint interval found that has a register assigned
4114 return NULL;
4115 }
4116
4117
4118 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4119 assert(is_split_parent(), "can only be called for split parents");
4120 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4121
4122 Interval* result;
4123 if (_split_children.length() == 0) {
4124 result = this;
4125 } else {
4126 result = NULL;
4127 int len = _split_children.length();
4128
4129 // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4130 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4131
4132 int i;
4133 for (i = 0; i < len; i++) {
4134 Interval* cur = _split_children.at(i);
4135 if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4136 if (i > 0) {
4137 // exchange current split child to start of list (faster access for next call)
4138 _split_children.at_put(i, _split_children.at(0));
4139 _split_children.at_put(0, cur);
4140 }
4141
4142 // interval found
4143 result = cur;
4144 break;
4145 }
4146 }
4147
4148 #ifdef ASSERT
4149 for (i = 0; i < len; i++) {
4150 Interval* tmp = _split_children.at(i);
4151 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4152 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4153 result->print();
4154 tmp->print();
4155 assert(false, "two valid result intervals found");
4156 }
4157 }
4158 #endif
4159 }
4160
4161 assert(result != NULL, "no matching interval found");
4162 assert(result->covers(op_id, mode), "op_id not covered by interval");
4163
4164 return result;
4165 }
4166
4167
4168 // returns the last split child that ends before the given op_id
4169 Interval* Interval::split_child_before_op_id(int op_id) {
4170 assert(op_id >= 0, "invalid op_id");
4171
4172 Interval* parent = split_parent();
4173 Interval* result = NULL;
4174
4175 int len = parent->_split_children.length();
4176 assert(len > 0, "no split children available");
4177
4178 for (int i = len - 1; i >= 0; i--) {
4179 Interval* cur = parent->_split_children.at(i);
4180 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4181 result = cur;
4182 }
4183 }
4184
4185 assert(result != NULL, "no split child found");
4186 return result;
4187 }
4188
4189
4190 // checks if op_id is covered by any split child
4191 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4192 assert(is_split_parent(), "can only be called for split parents");
4193 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4194
4195 if (_split_children.length() == 0) {
4196 // simple case if interval was not split
4197 return covers(op_id, mode);
4198
4199 } else {
4200 // extended case: check all split children
4201 int len = _split_children.length();
4202 for (int i = 0; i < len; i++) {
4203 Interval* cur = _split_children.at(i);
4204 if (cur->covers(op_id, mode)) {
4205 return true;
4206 }
4207 }
4208 return false;
4209 }
4210 }
4211
4212
4213 // Note: use positions are sorted descending -> first use has highest index
4214 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4215 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4216
4217 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4218 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4219 return _use_pos_and_kinds.at(i);
4220 }
4221 }
4222 return max_jint;
4223 }
4224
4225 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4226 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4227
4228 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4229 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4230 return _use_pos_and_kinds.at(i);
4231 }
4232 }
4233 return max_jint;
4234 }
4235
4236 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4237 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4238
4239 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4240 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4241 return _use_pos_and_kinds.at(i);
4242 }
4243 }
4244 return max_jint;
4245 }
4246
4247 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4248 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4249
4250 int prev = 0;
4251 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4252 if (_use_pos_and_kinds.at(i) > from) {
4253 return prev;
4254 }
4255 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4256 prev = _use_pos_and_kinds.at(i);
4257 }
4258 }
4259 return prev;
4260 }
4261
4262 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4263 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4264
4265 // do not add use positions for precolored intervals because
4266 // they are never used
4267 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4268 #ifdef ASSERT
4269 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4270 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4271 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4272 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4273 if (i > 0) {
4274 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4275 }
4276 }
4277 #endif
4278
4279 // Note: add_use is called in descending order, so list gets sorted
4280 // automatically by just appending new use positions
4281 int len = _use_pos_and_kinds.length();
4282 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4283 _use_pos_and_kinds.append(pos);
4284 _use_pos_and_kinds.append(use_kind);
4285 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4286 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4287 _use_pos_and_kinds.at_put(len - 1, use_kind);
4288 }
4289 }
4290 }
4291
4292 void Interval::add_range(int from, int to) {
4293 assert(from < to, "invalid range");
4294 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4295 assert(from <= first()->to(), "not inserting at begin of interval");
4296
4297 if (first()->from() <= to) {
4298 // join intersecting ranges
4299 first()->set_from(MIN2(from, first()->from()));
4300 first()->set_to (MAX2(to, first()->to()));
4301 } else {
4302 // insert new range
4303 _first = new Range(from, to, first());
4304 }
4305 }
4306
4307 Interval* Interval::new_split_child() {
4308 // allocate new interval
4309 Interval* result = new Interval(-1);
4310 result->set_type(type());
4311
4312 Interval* parent = split_parent();
4313 result->_split_parent = parent;
4314 result->set_register_hint(parent);
4315
4316 // insert new interval in children-list of parent
4317 if (parent->_split_children.length() == 0) {
4318 assert(is_split_parent(), "list must be initialized at first split");
4319
4320 parent->_split_children = IntervalList(4);
4321 parent->_split_children.append(this);
4322 }
4323 parent->_split_children.append(result);
4324
4325 return result;
4326 }
4327
4328 // split this interval at the specified position and return
4329 // the remainder as a new interval.
4330 //
4331 // when an interval is split, a bi-directional link is established between the original interval
4332 // (the split parent) and the intervals that are split off this interval (the split children)
4333 // When a split child is split again, the new created interval is also a direct child
4334 // of the original parent (there is no tree of split children stored, but a flat list)
4335 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4336 //
4337 // Note: The new interval has no valid reg_num
4338 Interval* Interval::split(int split_pos) {
4339 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4340
4341 // allocate new interval
4342 Interval* result = new_split_child();
4343
4344 // split the ranges
4345 Range* prev = NULL;
4346 Range* cur = _first;
4347 while (cur != Range::end() && cur->to() <= split_pos) {
4348 prev = cur;
4349 cur = cur->next();
4350 }
4351 assert(cur != Range::end(), "split interval after end of last range");
4352
4353 if (cur->from() < split_pos) {
4354 result->_first = new Range(split_pos, cur->to(), cur->next());
4355 cur->set_to(split_pos);
4356 cur->set_next(Range::end());
4357
4358 } else {
4359 assert(prev != NULL, "split before start of first range");
4360 result->_first = cur;
4361 prev->set_next(Range::end());
4362 }
4363 result->_current = result->_first;
4364 _cached_to = -1; // clear cached value
4365
4366 // split list of use positions
4367 int total_len = _use_pos_and_kinds.length();
4368 int start_idx = total_len - 2;
4369 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4370 start_idx -= 2;
4371 }
4372
4373 intStack new_use_pos_and_kinds(total_len - start_idx);
4374 int i;
4375 for (i = start_idx + 2; i < total_len; i++) {
4376 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4377 }
4378
4379 _use_pos_and_kinds.truncate(start_idx + 2);
4380 result->_use_pos_and_kinds = _use_pos_and_kinds;
4381 _use_pos_and_kinds = new_use_pos_and_kinds;
4382
4383 #ifdef ASSERT
4384 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4385 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4386 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4387
4388 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4389 assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4390 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4391 }
4392 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4393 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4394 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4395 }
4396 #endif
4397
4398 return result;
4399 }
4400
4401 // split this interval at the specified position and return
4402 // the head as a new interval (the original interval is the tail)
4403 //
4404 // Currently, only the first range can be split, and the new interval
4405 // must not have split positions
4406 Interval* Interval::split_from_start(int split_pos) {
4407 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4408 assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4409 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4410 assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4411
4412 // allocate new interval
4413 Interval* result = new_split_child();
4414
4415 // the new created interval has only one range (checked by assertion above),
4416 // so the splitting of the ranges is very simple
4417 result->add_range(_first->from(), split_pos);
4418
4419 if (split_pos == _first->to()) {
4420 assert(_first->next() != Range::end(), "must not be at end");
4421 _first = _first->next();
4422 } else {
4423 _first->set_from(split_pos);
4424 }
4425
4426 return result;
4427 }
4428
4429
4430 // returns true if the op_id is inside the interval
4431 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4432 Range* cur = _first;
4433
4434 while (cur != Range::end() && cur->to() < op_id) {
4435 cur = cur->next();
4436 }
4437 if (cur != Range::end()) {
4438 assert(cur->to() != cur->next()->from(), "ranges not separated");
4439
4440 if (mode == LIR_OpVisitState::outputMode) {
4441 return cur->from() <= op_id && op_id < cur->to();
4442 } else {
4443 return cur->from() <= op_id && op_id <= cur->to();
4444 }
4445 }
4446 return false;
4447 }
4448
4449 // returns true if the interval has any hole between hole_from and hole_to
4450 // (even if the hole has only the length 1)
4451 bool Interval::has_hole_between(int hole_from, int hole_to) {
4452 assert(hole_from < hole_to, "check");
4453 assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4454
4455 Range* cur = _first;
4456 while (cur != Range::end()) {
4457 assert(cur->to() < cur->next()->from(), "no space between ranges");
4458
4459 // hole-range starts before this range -> hole
4460 if (hole_from < cur->from()) {
4461 return true;
4462
4463 // hole-range completely inside this range -> no hole
4464 } else if (hole_to <= cur->to()) {
4465 return false;
4466
4467 // overlapping of hole-range with this range -> hole
4468 } else if (hole_from <= cur->to()) {
4469 return true;
4470 }
4471
4472 cur = cur->next();
4473 }
4474
4475 return false;
4476 }
4477
4478
4479 #ifndef PRODUCT
4480 void Interval::print(outputStream* out) const {
4481 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4482 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4483
4484 const char* type_name;
4485 LIR_Opr opr = LIR_OprFact::illegal();
4486 if (reg_num() < LIR_OprDesc::vreg_base) {
4487 type_name = "fixed";
4488 // need a temporary operand for fixed intervals because type() cannot be called
4489 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4490 opr = LIR_OprFact::single_cpu(assigned_reg());
4491 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4492 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4493 #ifdef X86
4494 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
4495 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4496 #endif
4497 } else {
4498 ShouldNotReachHere();
4499 }
4500 } else {
4501 type_name = type2name(type());
4502 if (assigned_reg() != -1) {
4503 opr = LinearScan::calc_operand_for_interval(this);
4504 }
4505 }
4506
4507 out->print("%d %s ", reg_num(), type_name);
4508 if (opr->is_valid()) {
4509 out->print("\"");
4510 opr->print(out);
4511 out->print("\" ");
4512 }
4513 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4514
4515 // print ranges
4516 Range* cur = _first;
4517 while (cur != Range::end()) {
4518 cur->print(out);
4519 cur = cur->next();
4520 assert(cur != NULL, "range list not closed with range sentinel");
4521 }
4522
4523 // print use positions
4524 int prev = 0;
4525 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4526 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4527 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4528 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4529
4530 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4531 prev = _use_pos_and_kinds.at(i);
4532 }
4533
4534 out->print(" \"%s\"", SpillState2Name[spill_state()]);
4535 out->cr();
4536 }
4537 #endif
4538
4539
4540
4541 // **** Implementation of IntervalWalker ****************************
4542
4543 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4544 : _compilation(allocator->compilation())
4545 , _allocator(allocator)
4546 {
4547 _unhandled_first[fixedKind] = unhandled_fixed_first;
4548 _unhandled_first[anyKind] = unhandled_any_first;
4549 _active_first[fixedKind] = Interval::end();
4550 _inactive_first[fixedKind] = Interval::end();
4551 _active_first[anyKind] = Interval::end();
4552 _inactive_first[anyKind] = Interval::end();
4553 _current_position = -1;
4554 _current = NULL;
4555 next_interval();
4556 }
4557
4558
4559 // append interval at top of list
4560 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4561 interval->set_next(*list); *list = interval;
4562 }
4563
4564
4565 // append interval in order of current range from()
4566 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4567 Interval* prev = NULL;
4568 Interval* cur = *list;
4569 while (cur->current_from() < interval->current_from()) {
4570 prev = cur; cur = cur->next();
4571 }
4572 if (prev == NULL) {
4573 *list = interval;
4574 } else {
4575 prev->set_next(interval);
4576 }
4577 interval->set_next(cur);
4578 }
4579
4580 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4581 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4582
4583 Interval* prev = NULL;
4584 Interval* cur = *list;
4585 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4586 prev = cur; cur = cur->next();
4587 }
4588 if (prev == NULL) {
4589 *list = interval;
4590 } else {
4591 prev->set_next(interval);
4592 }
4593 interval->set_next(cur);
4594 }
4595
4596
4597 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4598 while (*list != Interval::end() && *list != i) {
4599 list = (*list)->next_addr();
4600 }
4601 if (*list != Interval::end()) {
4602 assert(*list == i, "check");
4603 *list = (*list)->next();
4604 return true;
4605 } else {
4606 return false;
4607 }
4608 }
4609
4610 void IntervalWalker::remove_from_list(Interval* i) {
4611 bool deleted;
4612
4613 if (i->state() == activeState) {
4614 deleted = remove_from_list(active_first_addr(anyKind), i);
4615 } else {
4616 assert(i->state() == inactiveState, "invalid state");
4617 deleted = remove_from_list(inactive_first_addr(anyKind), i);
4618 }
4619
4620 assert(deleted, "interval has not been found in list");
4621 }
4622
4623
4624 void IntervalWalker::walk_to(IntervalState state, int from) {
4625 assert (state == activeState || state == inactiveState, "wrong state");
4626 for_each_interval_kind(kind) {
4627 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4628 Interval* next = *prev;
4629 while (next->current_from() <= from) {
4630 Interval* cur = next;
4631 next = cur->next();
4632
4633 bool range_has_changed = false;
4634 while (cur->current_to() <= from) {
4635 cur->next_range();
4636 range_has_changed = true;
4637 }
4638
4639 // also handle move from inactive list to active list
4640 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4641
4642 if (range_has_changed) {
4643 // remove cur from list
4644 *prev = next;
4645 if (cur->current_at_end()) {
4646 // move to handled state (not maintained as a list)
4647 cur->set_state(handledState);
4648 interval_moved(cur, kind, state, handledState);
4649 } else if (cur->current_from() <= from){
4650 // sort into active list
4651 append_sorted(active_first_addr(kind), cur);
4652 cur->set_state(activeState);
4653 if (*prev == cur) {
4654 assert(state == activeState, "check");
4655 prev = cur->next_addr();
4656 }
4657 interval_moved(cur, kind, state, activeState);
4658 } else {
4659 // sort into inactive list
4660 append_sorted(inactive_first_addr(kind), cur);
4661 cur->set_state(inactiveState);
4662 if (*prev == cur) {
4663 assert(state == inactiveState, "check");
4664 prev = cur->next_addr();
4665 }
4666 interval_moved(cur, kind, state, inactiveState);
4667 }
4668 } else {
4669 prev = cur->next_addr();
4670 continue;
4671 }
4672 }
4673 }
4674 }
4675
4676
4677 void IntervalWalker::next_interval() {
4678 IntervalKind kind;
4679 Interval* any = _unhandled_first[anyKind];
4680 Interval* fixed = _unhandled_first[fixedKind];
4681
4682 if (any != Interval::end()) {
4683 // intervals may start at same position -> prefer fixed interval
4684 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4685
4686 assert (kind == fixedKind && fixed->from() <= any->from() ||
4687 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!");
4688 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4689
4690 } else if (fixed != Interval::end()) {
4691 kind = fixedKind;
4692 } else {
4693 _current = NULL; return;
4694 }
4695 _current_kind = kind;
4696 _current = _unhandled_first[kind];
4697 _unhandled_first[kind] = _current->next();
4698 _current->set_next(Interval::end());
4699 _current->rewind_range();
4700 }
4701
4702
4703 void IntervalWalker::walk_to(int lir_op_id) {
4704 assert(_current_position <= lir_op_id, "can not walk backwards");
4705 while (current() != NULL) {
4706 bool is_active = current()->from() <= lir_op_id;
4707 int id = is_active ? current()->from() : lir_op_id;
4708
4709 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4710
4711 // set _current_position prior to call of walk_to
4712 _current_position = id;
4713
4714 // call walk_to even if _current_position == id
4715 walk_to(activeState, id);
4716 walk_to(inactiveState, id);
4717
4718 if (is_active) {
4719 current()->set_state(activeState);
4720 if (activate_current()) {
4721 append_sorted(active_first_addr(current_kind()), current());
4722 interval_moved(current(), current_kind(), unhandledState, activeState);
4723 }
4724
4725 next_interval();
4726 } else {
4727 return;
4728 }
4729 }
4730 }
4731
4732 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4733 #ifndef PRODUCT
4734 if (TraceLinearScanLevel >= 4) {
4735 #define print_state(state) \
4736 switch(state) {\
4737 case unhandledState: tty->print("unhandled"); break;\
4738 case activeState: tty->print("active"); break;\
4739 case inactiveState: tty->print("inactive"); break;\
4740 case handledState: tty->print("handled"); break;\
4741 default: ShouldNotReachHere(); \
4742 }
4743
4744 print_state(from); tty->print(" to "); print_state(to);
4745 tty->fill_to(23);
4746 interval->print();
4747
4748 #undef print_state
4749 }
4750 #endif
4751 }
4752
4753
4754
4755 // **** Implementation of LinearScanWalker **************************
4756
4757 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4758 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4759 , _move_resolver(allocator)
4760 {
4761 for (int i = 0; i < LinearScan::nof_regs; i++) {
4762 _spill_intervals[i] = new IntervalList(2);
4763 }
4764 }
4765
4766
4767 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4768 for (int i = _first_reg; i <= _last_reg; i++) {
4769 _use_pos[i] = max_jint;
4770
4771 if (!only_process_use_pos) {
4772 _block_pos[i] = max_jint;
4773 _spill_intervals[i]->clear();
4774 }
4775 }
4776 }
4777
4778 inline void LinearScanWalker::exclude_from_use(int reg) {
4779 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4780 if (reg >= _first_reg && reg <= _last_reg) {
4781 _use_pos[reg] = 0;
4782 }
4783 }
4784 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4785 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4786
4787 exclude_from_use(i->assigned_reg());
4788 exclude_from_use(i->assigned_regHi());
4789 }
4790
4791 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4792 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4793
4794 if (reg >= _first_reg && reg <= _last_reg) {
4795 if (_use_pos[reg] > use_pos) {
4796 _use_pos[reg] = use_pos;
4797 }
4798 if (!only_process_use_pos) {
4799 _spill_intervals[reg]->append(i);
4800 }
4801 }
4802 }
4803 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4804 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4805 if (use_pos != -1) {
4806 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4807 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4808 }
4809 }
4810
4811 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4812 if (reg >= _first_reg && reg <= _last_reg) {
4813 if (_block_pos[reg] > block_pos) {
4814 _block_pos[reg] = block_pos;
4815 }
4816 if (_use_pos[reg] > block_pos) {
4817 _use_pos[reg] = block_pos;
4818 }
4819 }
4820 }
4821 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4822 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4823 if (block_pos != -1) {
4824 set_block_pos(i->assigned_reg(), i, block_pos);
4825 set_block_pos(i->assigned_regHi(), i, block_pos);
4826 }
4827 }
4828
4829
4830 void LinearScanWalker::free_exclude_active_fixed() {
4831 Interval* list = active_first(fixedKind);
4832 while (list != Interval::end()) {
4833 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4834 exclude_from_use(list);
4835 list = list->next();
4836 }
4837 }
4838
4839 void LinearScanWalker::free_exclude_active_any() {
4840 Interval* list = active_first(anyKind);
4841 while (list != Interval::end()) {
4842 exclude_from_use(list);
4843 list = list->next();
4844 }
4845 }
4846
4847 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4848 Interval* list = inactive_first(fixedKind);
4849 while (list != Interval::end()) {
4850 if (cur->to() <= list->current_from()) {
4851 assert(list->current_intersects_at(cur) == -1, "must not intersect");
4852 set_use_pos(list, list->current_from(), true);
4853 } else {
4854 set_use_pos(list, list->current_intersects_at(cur), true);
4855 }
4856 list = list->next();
4857 }
4858 }
4859
4860 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4861 Interval* list = inactive_first(anyKind);
4862 while (list != Interval::end()) {
4863 set_use_pos(list, list->current_intersects_at(cur), true);
4864 list = list->next();
4865 }
4866 }
4867
4868 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4869 Interval* list = unhandled_first(kind);
4870 while (list != Interval::end()) {
4871 set_use_pos(list, list->intersects_at(cur), true);
4872 if (kind == fixedKind && cur->to() <= list->from()) {
4873 set_use_pos(list, list->from(), true);
4874 }
4875 list = list->next();
4876 }
4877 }
4878
4879 void LinearScanWalker::spill_exclude_active_fixed() {
4880 Interval* list = active_first(fixedKind);
4881 while (list != Interval::end()) {
4882 exclude_from_use(list);
4883 list = list->next();
4884 }
4885 }
4886
4887 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4888 Interval* list = unhandled_first(fixedKind);
4889 while (list != Interval::end()) {
4890 set_block_pos(list, list->intersects_at(cur));
4891 list = list->next();
4892 }
4893 }
4894
4895 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4896 Interval* list = inactive_first(fixedKind);
4897 while (list != Interval::end()) {
4898 if (cur->to() > list->current_from()) {
4899 set_block_pos(list, list->current_intersects_at(cur));
4900 } else {
4901 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4902 }
4903
4904 list = list->next();
4905 }
4906 }
4907
4908 void LinearScanWalker::spill_collect_active_any() {
4909 Interval* list = active_first(anyKind);
4910 while (list != Interval::end()) {
4911 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4912 list = list->next();
4913 }
4914 }
4915
4916 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4917 Interval* list = inactive_first(anyKind);
4918 while (list != Interval::end()) {
4919 if (list->current_intersects(cur)) {
4920 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4921 }
4922 list = list->next();
4923 }
4924 }
4925
4926
4927 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4928 // output all moves here. When source and target are equal, the move is
4929 // optimized away later in assign_reg_nums
4930
4931 op_id = (op_id + 1) & ~1;
4932 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4933 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4934
4935 // calculate index of instruction inside instruction list of current block
4936 // the minimal index (for a block with no spill moves) can be calculated because the
4937 // numbering of instructions is known.
4938 // When the block already contains spill moves, the index must be increased until the
4939 // correct index is reached.
4940 LIR_OpList* list = op_block->lir()->instructions_list();
4941 int index = (op_id - list->at(0)->id()) / 2;
4942 assert(list->at(index)->id() <= op_id, "error in calculation");
4943
4944 while (list->at(index)->id() != op_id) {
4945 index++;
4946 assert(0 <= index && index < list->length(), "index out of bounds");
4947 }
4948 assert(1 <= index && index < list->length(), "index out of bounds");
4949 assert(list->at(index)->id() == op_id, "error in calculation");
4950
4951 // insert new instruction before instruction at position index
4952 _move_resolver.move_insert_position(op_block->lir(), index - 1);
4953 _move_resolver.add_mapping(src_it, dst_it);
4954 }
4955
4956
4957 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
4958 int from_block_nr = min_block->linear_scan_number();
4959 int to_block_nr = max_block->linear_scan_number();
4960
4961 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
4962 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
4963 assert(from_block_nr < to_block_nr, "must cross block boundary");
4964
4965 // Try to split at end of max_block. If this would be after
4966 // max_split_pos, then use the begin of max_block
4967 int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
4968 if (optimal_split_pos > max_split_pos) {
4969 optimal_split_pos = max_block->first_lir_instruction_id();
4970 }
4971
4972 int min_loop_depth = max_block->loop_depth();
4973 for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
4974 BlockBegin* cur = block_at(i);
4975
4976 if (cur->loop_depth() < min_loop_depth) {
4977 // block with lower loop-depth found -> split at the end of this block
4978 min_loop_depth = cur->loop_depth();
4979 optimal_split_pos = cur->last_lir_instruction_id() + 2;
4980 }
4981 }
4982 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
4983
4984 return optimal_split_pos;
4985 }
4986
4987
4988 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
4989 int optimal_split_pos = -1;
4990 if (min_split_pos == max_split_pos) {
4991 // trivial case, no optimization of split position possible
4992 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
4993 optimal_split_pos = min_split_pos;
4994
4995 } else {
4996 assert(min_split_pos < max_split_pos, "must be true then");
4997 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
4998
4999 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5000 // beginning of a block, then min_split_pos is also a possible split position.
5001 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5002 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5003
5004 // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5005 // when an interval ends at the end of the last block of the method
5006 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5007 // block at this op_id)
5008 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5009
5010 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5011 if (min_block == max_block) {
5012 // split position cannot be moved to block boundary, so split as late as possible
5013 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5014 optimal_split_pos = max_split_pos;
5015
5016 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5017 // Do not move split position if the interval has a hole before max_split_pos.
5018 // Intervals resulting from Phi-Functions have more than one definition (marked
5019 // as mustHaveRegister) with a hole before each definition. When the register is needed
5020 // for the second definition, an earlier reloading is unnecessary.
5021 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
5022 optimal_split_pos = max_split_pos;
5023
5024 } else {
5025 // seach optimal block boundary between min_split_pos and max_split_pos
5026 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5027
5028 if (do_loop_optimization) {
5029 // Loop optimization: if a loop-end marker is found between min- and max-position,
5030 // then split before this loop
5031 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5032 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
5033
5034 assert(loop_end_pos > min_split_pos, "invalid order");
5035 if (loop_end_pos < max_split_pos) {
5036 // loop-end marker found between min- and max-position
5037 // if it is not the end marker for the same loop as the min-position, then move
5038 // the max-position to this loop block.
5039 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5040 // of the interval (normally, only mustHaveRegister causes a reloading)
5041 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5042
5043 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5044 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5045
5046 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5047 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5048 optimal_split_pos = -1;
5049 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary"));
5050 } else {
5051 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful"));
5052 }
5053 }
5054 }
5055
5056 if (optimal_split_pos == -1) {
5057 // not calculated by loop optimization
5058 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5059 }
5060 }
5061 }
5062 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos));
5063
5064 return optimal_split_pos;
5065 }
5066
5067
5068 /*
5069 split an interval at the optimal position between min_split_pos and
5070 max_split_pos in two parts:
5071 1) the left part has already a location assigned
5072 2) the right part is sorted into to the unhandled-list
5073 */
5074 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5075 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print());
5076 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5077
5078 assert(it->from() < min_split_pos, "cannot split at start of interval");
5079 assert(current_position() < min_split_pos, "cannot split before current position");
5080 assert(min_split_pos <= max_split_pos, "invalid order");
5081 assert(max_split_pos <= it->to(), "cannot split after end of interval");
5082
5083 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5084
5085 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5086 assert(optimal_split_pos <= it->to(), "cannot split after end of interval");
5087 assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5088
5089 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5090 // the split position would be just before the end of the interval
5091 // -> no split at all necessary
5092 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
5093 return;
5094 }
5095
5096 // must calculate this before the actual split is performed and before split position is moved to odd op_id
5097 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5098
5099 if (!allocator()->is_block_begin(optimal_split_pos)) {
5100 // move position before actual instruction (odd op_id)
5101 optimal_split_pos = (optimal_split_pos - 1) | 1;
5102 }
5103
5104 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5105 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5106 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5107
5108 Interval* split_part = it->split(optimal_split_pos);
5109
5110 allocator()->append_interval(split_part);
5111 allocator()->copy_register_flags(it, split_part);
5112 split_part->set_insert_move_when_activated(move_necessary);
5113 append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5114
5115 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5116 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5117 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print());
5118 }
5119
5120 /*
5121 split an interval at the optimal position between min_split_pos and
5122 max_split_pos in two parts:
5123 1) the left part has already a location assigned
5124 2) the right part is always on the stack and therefore ignored in further processing
5125 */
5126 void LinearScanWalker::split_for_spilling(Interval* it) {
5127 // calculate allowed range of splitting position
5128 int max_split_pos = current_position();
5129 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5130
5131 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print());
5132 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5133
5134 assert(it->state() == activeState, "why spill interval that is not active?");
5135 assert(it->from() <= min_split_pos, "cannot split before start of interval");
5136 assert(min_split_pos <= max_split_pos, "invalid order");
5137 assert(max_split_pos < it->to(), "cannot split at end end of interval");
5138 assert(current_position() < it->to(), "interval must not end before current position");
5139
5140 if (min_split_pos == it->from()) {
5141 // the whole interval is never used, so spill it entirely to memory
5142 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
5143 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5144
5145 allocator()->assign_spill_slot(it);
5146 allocator()->change_spill_state(it, min_split_pos);
5147
5148 // Also kick parent intervals out of register to memory when they have no use
5149 // position. This avoids short interval in register surrounded by intervals in
5150 // memory -> avoid useless moves from memory to register and back
5151 Interval* parent = it;
5152 while (parent != NULL && parent->is_split_child()) {
5153 parent = parent->split_child_before_op_id(parent->from());
5154
5155 if (parent->assigned_reg() < LinearScan::nof_regs) {
5156 if (parent->first_usage(shouldHaveRegister) == max_jint) {
5157 // parent is never used, so kick it out of its assigned register
5158 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
5159 allocator()->assign_spill_slot(parent);
5160 } else {
5161 // do not go further back because the register is actually used by the interval
5162 parent = NULL;
5163 }
5164 }
5165 }
5166
5167 } else {
5168 // search optimal split pos, split interval and spill only the right hand part
5169 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5170
5171 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5172 assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5173 assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5174
5175 if (!allocator()->is_block_begin(optimal_split_pos)) {
5176 // move position before actual instruction (odd op_id)
5177 optimal_split_pos = (optimal_split_pos - 1) | 1;
5178 }
5179
5180 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5181 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5182 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5183
5184 Interval* spilled_part = it->split(optimal_split_pos);
5185 allocator()->append_interval(spilled_part);
5186 allocator()->assign_spill_slot(spilled_part);
5187 allocator()->change_spill_state(spilled_part, optimal_split_pos);
5188
5189 if (!allocator()->is_block_begin(optimal_split_pos)) {
5190 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5191 insert_move(optimal_split_pos, it, spilled_part);
5192 }
5193
5194 // the current_split_child is needed later when moves are inserted for reloading
5195 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5196 spilled_part->make_current_split_child();
5197
5198 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts"));
5199 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5200 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print());
5201 }
5202 }
5203
5204
5205 void LinearScanWalker::split_stack_interval(Interval* it) {
5206 int min_split_pos = current_position() + 1;
5207 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5208
5209 split_before_usage(it, min_split_pos, max_split_pos);
5210 }
5211
5212 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5213 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5214 int max_split_pos = register_available_until;
5215
5216 split_before_usage(it, min_split_pos, max_split_pos);
5217 }
5218
5219 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5220 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5221
5222 int current_pos = current_position();
5223 if (it->state() == inactiveState) {
5224 // the interval is currently inactive, so no spill slot is needed for now.
5225 // when the split part is activated, the interval has a new chance to get a register,
5226 // so in the best case no stack slot is necessary
5227 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5228 split_before_usage(it, current_pos + 1, current_pos + 1);
5229
5230 } else {
5231 // search the position where the interval must have a register and split
5232 // at the optimal position before.
5233 // The new created part is added to the unhandled list and will get a register
5234 // when it is activated
5235 int min_split_pos = current_pos + 1;
5236 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5237
5238 split_before_usage(it, min_split_pos, max_split_pos);
5239
5240 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5241 split_for_spilling(it);
5242 }
5243 }
5244
5245
5246 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5247 int min_full_reg = any_reg;
5248 int max_partial_reg = any_reg;
5249
5250 for (int i = _first_reg; i <= _last_reg; i++) {
5251 if (i == ignore_reg) {
5252 // this register must be ignored
5253
5254 } else if (_use_pos[i] >= interval_to) {
5255 // this register is free for the full interval
5256 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5257 min_full_reg = i;
5258 }
5259 } else if (_use_pos[i] > reg_needed_until) {
5260 // this register is at least free until reg_needed_until
5261 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5262 max_partial_reg = i;
5263 }
5264 }
5265 }
5266
5267 if (min_full_reg != any_reg) {
5268 return min_full_reg;
5269 } else if (max_partial_reg != any_reg) {
5270 *need_split = true;
5271 return max_partial_reg;
5272 } else {
5273 return any_reg;
5274 }
5275 }
5276
5277 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5278 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5279
5280 int min_full_reg = any_reg;
5281 int max_partial_reg = any_reg;
5282
5283 for (int i = _first_reg; i < _last_reg; i+=2) {
5284 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5285 // this register is free for the full interval
5286 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5287 min_full_reg = i;
5288 }
5289 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5290 // this register is at least free until reg_needed_until
5291 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5292 max_partial_reg = i;
5293 }
5294 }
5295 }
5296
5297 if (min_full_reg != any_reg) {
5298 return min_full_reg;
5299 } else if (max_partial_reg != any_reg) {
5300 *need_split = true;
5301 return max_partial_reg;
5302 } else {
5303 return any_reg;
5304 }
5305 }
5306
5307
5308 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5309 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5310
5311 init_use_lists(true);
5312 free_exclude_active_fixed();
5313 free_exclude_active_any();
5314 free_collect_inactive_fixed(cur);
5315 free_collect_inactive_any(cur);
5316 // free_collect_unhandled(fixedKind, cur);
5317 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5318
5319 // _use_pos contains the start of the next interval that has this register assigned
5320 // (either as a fixed register or a normal allocated register in the past)
5321 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5322 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:"));
5323 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i]));
5324
5325 int hint_reg, hint_regHi;
5326 Interval* register_hint = cur->register_hint();
5327 if (register_hint != NULL) {
5328 hint_reg = register_hint->assigned_reg();
5329 hint_regHi = register_hint->assigned_regHi();
5330
5331 if (allocator()->is_precolored_cpu_interval(register_hint)) {
5332 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5333 hint_regHi = hint_reg + 1; // connect e.g. eax-edx
5334 }
5335 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5336
5337 } else {
5338 hint_reg = any_reg;
5339 hint_regHi = any_reg;
5340 }
5341 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5342 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5343
5344 // the register must be free at least until this position
5345 int reg_needed_until = cur->from() + 1;
5346 int interval_to = cur->to();
5347
5348 bool need_split = false;
5349 int split_pos = -1;
5350 int reg = any_reg;
5351 int regHi = any_reg;
5352
5353 if (_adjacent_regs) {
5354 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5355 regHi = reg + 1;
5356 if (reg == any_reg) {
5357 return false;
5358 }
5359 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5360
5361 } else {
5362 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5363 if (reg == any_reg) {
5364 return false;
5365 }
5366 split_pos = _use_pos[reg];
5367
5368 if (_num_phys_regs == 2) {
5369 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5370
5371 if (_use_pos[reg] < interval_to && regHi == any_reg) {
5372 // do not split interval if only one register can be assigned until the split pos
5373 // (when one register is found for the whole interval, split&spill is only
5374 // performed for the hi register)
5375 return false;
5376
5377 } else if (regHi != any_reg) {
5378 split_pos = MIN2(split_pos, _use_pos[regHi]);
5379
5380 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5381 if (reg > regHi) {
5382 int temp = reg;
5383 reg = regHi;
5384 regHi = temp;
5385 }
5386 }
5387 }
5388 }
5389
5390 cur->assign_reg(reg, regHi);
5391 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5392
5393 assert(split_pos > 0, "invalid split_pos");
5394 if (need_split) {
5395 // register not available for full interval, so split it
5396 split_when_partial_register_available(cur, split_pos);
5397 }
5398
5399 // only return true if interval is completely assigned
5400 return _num_phys_regs == 1 || regHi != any_reg;
5401 }
5402
5403
5404 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5405 int max_reg = any_reg;
5406
5407 for (int i = _first_reg; i <= _last_reg; i++) {
5408 if (i == ignore_reg) {
5409 // this register must be ignored
5410
5411 } else if (_use_pos[i] > reg_needed_until) {
5412 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5413 max_reg = i;
5414 }
5415 }
5416 }
5417
5418 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5419 *need_split = true;
5420 }
5421
5422 return max_reg;
5423 }
5424
5425 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5426 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5427
5428 int max_reg = any_reg;
5429
5430 for (int i = _first_reg; i < _last_reg; i+=2) {
5431 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5432 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5433 max_reg = i;
5434 }
5435 }
5436 }
5437
5438 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
5439 *need_split = true;
5440 }
5441
5442 return max_reg;
5443 }
5444
5445 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5446 assert(reg != any_reg, "no register assigned");
5447
5448 for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5449 Interval* it = _spill_intervals[reg]->at(i);
5450 remove_from_list(it);
5451 split_and_spill_interval(it);
5452 }
5453
5454 if (regHi != any_reg) {
5455 IntervalList* processed = _spill_intervals[reg];
5456 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5457 Interval* it = _spill_intervals[regHi]->at(i);
5458 if (processed->index_of(it) == -1) {
5459 remove_from_list(it);
5460 split_and_spill_interval(it);
5461 }
5462 }
5463 }
5464 }
5465
5466
5467 // Split an Interval and spill it to memory so that cur can be placed in a register
5468 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5469 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5470
5471 // collect current usage of registers
5472 init_use_lists(false);
5473 spill_exclude_active_fixed();
5474 // spill_block_unhandled_fixed(cur);
5475 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5476 spill_block_inactive_fixed(cur);
5477 spill_collect_active_any();
5478 spill_collect_inactive_any(cur);
5479
5480 #ifndef PRODUCT
5481 if (TraceLinearScanLevel >= 4) {
5482 tty->print_cr(" state of registers:");
5483 for (int i = _first_reg; i <= _last_reg; i++) {
5484 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5485 for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5486 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5487 }
5488 tty->cr();
5489 }
5490 }
5491 #endif
5492
5493 // the register must be free at least until this position
5494 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5495 int interval_to = cur->to();
5496 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5497
5498 int split_pos = 0;
5499 int use_pos = 0;
5500 bool need_split = false;
5501 int reg, regHi;
5502
5503 if (_adjacent_regs) {
5504 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5505 regHi = reg + 1;
5506
5507 if (reg != any_reg) {
5508 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5509 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5510 }
5511 } else {
5512 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5513 regHi = any_reg;
5514
5515 if (reg != any_reg) {
5516 use_pos = _use_pos[reg];
5517 split_pos = _block_pos[reg];
5518
5519 if (_num_phys_regs == 2) {
5520 if (cur->assigned_reg() != any_reg) {
5521 regHi = reg;
5522 reg = cur->assigned_reg();
5523 } else {
5524 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5525 if (regHi != any_reg) {
5526 use_pos = MIN2(use_pos, _use_pos[regHi]);
5527 split_pos = MIN2(split_pos, _block_pos[regHi]);
5528 }
5529 }
5530
5531 if (regHi != any_reg && reg > regHi) {
5532 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5533 int temp = reg;
5534 reg = regHi;
5535 regHi = temp;
5536 }
5537 }
5538 }
5539 }
5540
5541 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5542 // the first use of cur is later than the spilling position -> spill cur
5543 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5544
5545 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5546 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5547 // assign a reasonable register and do a bailout in product mode to avoid errors
5548 allocator()->assign_spill_slot(cur);
5549 BAILOUT("LinearScan: no register found");
5550 }
5551
5552 split_and_spill_interval(cur);
5553 } else {
5554 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5555 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5556 assert(split_pos > 0, "invalid split_pos");
5557 assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5558
5559 cur->assign_reg(reg, regHi);
5560 if (need_split) {
5561 // register not available for full interval, so split it
5562 split_when_partial_register_available(cur, split_pos);
5563 }
5564
5565 // perform splitting and spilling for all affected intervalls
5566 split_and_spill_intersecting_intervals(reg, regHi);
5567 }
5568 }
5569
5570 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5571 #ifdef X86
5572 // fast calculation of intervals that can never get a register because the
5573 // the next instruction is a call that blocks all registers
5574 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5575
5576 // check if this interval is the result of a split operation
5577 // (an interval got a register until this position)
5578 int pos = cur->from();
5579 if ((pos & 1) == 1) {
5580 // the current instruction is a call that blocks all registers
5581 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5582 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
5583
5584 // safety check that there is really no register available
5585 assert(alloc_free_reg(cur) == false, "found a register for this interval");
5586 return true;
5587 }
5588
5589 }
5590 #endif
5591 return false;
5592 }
5593
5594 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5595 BasicType type = cur->type();
5596 _num_phys_regs = LinearScan::num_physical_regs(type);
5597 _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5598
5599 if (pd_init_regs_for_alloc(cur)) {
5600 // the appropriate register range was selected.
5601 } else if (type == T_FLOAT || type == T_DOUBLE) {
5602 _first_reg = pd_first_fpu_reg;
5603 _last_reg = pd_last_fpu_reg;
5604 } else {
5605 _first_reg = pd_first_cpu_reg;
5606 _last_reg = pd_last_cpu_reg;
5607 }
5608
5609 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5610 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5611 }
5612
5613
5614 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5615 if (op->code() != lir_move) {
5616 return false;
5617 }
5618 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5619
5620 LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5621 LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5622 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5623 }
5624
5625 // optimization (especially for phi functions of nested loops):
5626 // assign same spill slot to non-intersecting intervals
5627 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5628 if (cur->is_split_child()) {
5629 // optimization is only suitable for split parents
5630 return;
5631 }
5632
5633 Interval* register_hint = cur->register_hint(false);
5634 if (register_hint == NULL) {
5635 // cur is not the target of a move, otherwise register_hint would be set
5636 return;
5637 }
5638 assert(register_hint->is_split_parent(), "register hint must be split parent");
5639
5640 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5641 // combining the stack slots for intervals where spill move optimization is applied
5642 // is not benefitial and would cause problems
5643 return;
5644 }
5645
5646 int begin_pos = cur->from();
5647 int end_pos = cur->to();
5648 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5649 // safety check that lir_op_with_id is allowed
5650 return;
5651 }
5652
5653 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5654 // cur and register_hint are not connected with two moves
5655 return;
5656 }
5657
5658 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5659 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5660 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5661 // register_hint must be split, otherwise the re-writing of use positions does not work
5662 return;
5663 }
5664
5665 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5666 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5667 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5668 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5669
5670 if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5671 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5672 return;
5673 }
5674 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5675
5676 // modify intervals such that cur gets the same stack slot as register_hint
5677 // delete use positions to prevent the intervals to get a register at beginning
5678 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5679 cur->remove_first_use_pos();
5680 end_hint->remove_first_use_pos();
5681 }
5682
5683
5684 // allocate a physical register or memory location to an interval
5685 bool LinearScanWalker::activate_current() {
5686 Interval* cur = current();
5687 bool result = true;
5688
5689 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print());
5690 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5691
5692 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5693 // activating an interval that has a stack slot assigned -> split it at first use position
5694 // used for method parameters
5695 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
5696
5697 split_stack_interval(cur);
5698 result = false;
5699
5700 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5701 // activating an interval that must start in a stack slot, but may get a register later
5702 // used for lir_roundfp: rounding is done by store to stack and reload later
5703 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
5704 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5705
5706 allocator()->assign_spill_slot(cur);
5707 split_stack_interval(cur);
5708 result = false;
5709
5710 } else if (cur->assigned_reg() == any_reg) {
5711 // interval has not assigned register -> normal allocation
5712 // (this is the normal case for most intervals)
5713 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register"));
5714
5715 // assign same spill slot to non-intersecting intervals
5716 combine_spilled_intervals(cur);
5717
5718 init_vars_for_alloc(cur);
5719 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5720 // no empty register available.
5721 // split and spill another interval so that this interval gets a register
5722 alloc_locked_reg(cur);
5723 }
5724
5725 // spilled intervals need not be move to active-list
5726 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5727 result = false;
5728 }
5729 }
5730
5731 // load spilled values that become active from stack slot to register
5732 if (cur->insert_move_when_activated()) {
5733 assert(cur->is_split_child(), "must be");
5734 assert(cur->current_split_child() != NULL, "must be");
5735 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5736 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5737
5738 insert_move(cur->from(), cur->current_split_child(), cur);
5739 }
5740 cur->make_current_split_child();
5741
5742 return result; // true = interval is moved to active list
5743 }
5744
5745
5746 // Implementation of EdgeMoveOptimizer
5747
5748 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5749 _edge_instructions(4),
5750 _edge_instructions_idx(4)
5751 {
5752 }
5753
5754 void EdgeMoveOptimizer::optimize(BlockList* code) {
5755 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5756
5757 // ignore the first block in the list (index 0 is not processed)
5758 for (int i = code->length() - 1; i >= 1; i--) {
5759 BlockBegin* block = code->at(i);
5760
5761 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5762 optimizer.optimize_moves_at_block_end(block);
5763 }
5764 if (block->number_of_sux() == 2) {
5765 optimizer.optimize_moves_at_block_begin(block);
5766 }
5767 }
5768 }
5769
5770
5771 // clear all internal data structures
5772 void EdgeMoveOptimizer::init_instructions() {
5773 _edge_instructions.clear();
5774 _edge_instructions_idx.clear();
5775 }
5776
5777 // append a lir-instruction-list and the index of the current operation in to the list
5778 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5779 _edge_instructions.append(instructions);
5780 _edge_instructions_idx.append(instructions_idx);
5781 }
5782
5783 // return the current operation of the given edge (predecessor or successor)
5784 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5785 LIR_OpList* instructions = _edge_instructions.at(edge);
5786 int idx = _edge_instructions_idx.at(edge);
5787
5788 if (idx < instructions->length()) {
5789 return instructions->at(idx);
5790 } else {
5791 return NULL;
5792 }
5793 }
5794
5795 // removes the current operation of the given edge (predecessor or successor)
5796 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5797 LIR_OpList* instructions = _edge_instructions.at(edge);
5798 int idx = _edge_instructions_idx.at(edge);
5799 instructions->remove_at(idx);
5800
5801 if (decrement_index) {
5802 _edge_instructions_idx.at_put(edge, idx - 1);
5803 }
5804 }
5805
5806
5807 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5808 if (op1 == NULL || op2 == NULL) {
5809 // at least one block is already empty -> no optimization possible
5810 return true;
5811 }
5812
5813 if (op1->code() == lir_move && op2->code() == lir_move) {
5814 assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5815 assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5816 LIR_Op1* move1 = (LIR_Op1*)op1;
5817 LIR_Op1* move2 = (LIR_Op1*)op2;
5818 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5819 // these moves are exactly equal and can be optimized
5820 return false;
5821 }
5822
5823 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5824 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5825 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5826 LIR_Op1* fxch1 = (LIR_Op1*)op1;
5827 LIR_Op1* fxch2 = (LIR_Op1*)op2;
5828 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5829 // equal FPU stack operations can be optimized
5830 return false;
5831 }
5832
5833 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5834 // equal FPU stack operations can be optimized
5835 return false;
5836 }
5837
5838 // no optimization possible
5839 return true;
5840 }
5841
5842 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5843 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5844
5845 if (block->is_predecessor(block)) {
5846 // currently we can't handle this correctly.
5847 return;
5848 }
5849
5850 init_instructions();
5851 int num_preds = block->number_of_preds();
5852 assert(num_preds > 1, "do not call otherwise");
5853 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5854
5855 // setup a list with the lir-instructions of all predecessors
5856 int i;
5857 for (i = 0; i < num_preds; i++) {
5858 BlockBegin* pred = block->pred_at(i);
5859 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5860
5861 if (pred->number_of_sux() != 1) {
5862 // this can happen with switch-statements where multiple edges are between
5863 // the same blocks.
5864 return;
5865 }
5866
5867 assert(pred->number_of_sux() == 1, "can handle only one successor");
5868 assert(pred->sux_at(0) == block, "invalid control flow");
5869 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5870 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5871 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5872
5873 if (pred_instructions->last()->info() != NULL) {
5874 // can not optimize instructions when debug info is needed
5875 return;
5876 }
5877
5878 // ignore the unconditional branch at the end of the block
5879 append_instructions(pred_instructions, pred_instructions->length() - 2);
5880 }
5881
5882
5883 // process lir-instructions while all predecessors end with the same instruction
5884 while (true) {
5885 LIR_Op* op = instruction_at(0);
5886 for (i = 1; i < num_preds; i++) {
5887 if (operations_different(op, instruction_at(i))) {
5888 // these instructions are different and cannot be optimized ->
5889 // no further optimization possible
5890 return;
5891 }
5892 }
5893
5894 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5895
5896 // insert the instruction at the beginning of the current block
5897 block->lir()->insert_before(1, op);
5898
5899 // delete the instruction at the end of all predecessors
5900 for (i = 0; i < num_preds; i++) {
5901 remove_cur_instruction(i, true);
5902 }
5903 }
5904 }
5905
5906
5907 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5908 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5909
5910 init_instructions();
5911 int num_sux = block->number_of_sux();
5912
5913 LIR_OpList* cur_instructions = block->lir()->instructions_list();
5914
5915 assert(num_sux == 2, "method should not be called otherwise");
5916 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5917 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5918 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5919
5920 if (cur_instructions->last()->info() != NULL) {
5921 // can no optimize instructions when debug info is needed
5922 return;
5923 }
5924
5925 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5926 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5927 // not a valid case for optimization
5928 // currently, only blocks that end with two branches (conditional branch followed
5929 // by unconditional branch) are optimized
5930 return;
5931 }
5932
5933 // now it is guaranteed that the block ends with two branch instructions.
5934 // the instructions are inserted at the end of the block before these two branches
5935 int insert_idx = cur_instructions->length() - 2;
5936
5937 int i;
5938 #ifdef ASSERT
5939 for (i = insert_idx - 1; i >= 0; i--) {
5940 LIR_Op* op = cur_instructions->at(i);
5941 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
5942 assert(false, "block with two successors can have only two branch instructions");
5943 }
5944 }
5945 #endif
5946
5947 // setup a list with the lir-instructions of all successors
5948 for (i = 0; i < num_sux; i++) {
5949 BlockBegin* sux = block->sux_at(i);
5950 LIR_OpList* sux_instructions = sux->lir()->instructions_list();
5951
5952 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
5953
5954 if (sux->number_of_preds() != 1) {
5955 // this can happen with switch-statements where multiple edges are between
5956 // the same blocks.
5957 return;
5958 }
5959 assert(sux->pred_at(0) == block, "invalid control flow");
5960 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5961
5962 // ignore the label at the beginning of the block
5963 append_instructions(sux_instructions, 1);
5964 }
5965
5966 // process lir-instructions while all successors begin with the same instruction
5967 while (true) {
5968 LIR_Op* op = instruction_at(0);
5969 for (i = 1; i < num_sux; i++) {
5970 if (operations_different(op, instruction_at(i))) {
5971 // these instructions are different and cannot be optimized ->
5972 // no further optimization possible
5973 return;
5974 }
5975 }
5976
5977 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
5978
5979 // insert instruction at end of current block
5980 block->lir()->insert_before(insert_idx, op);
5981 insert_idx++;
5982
5983 // delete the instructions at the beginning of all successors
5984 for (i = 0; i < num_sux; i++) {
5985 remove_cur_instruction(i, false);
5986 }
5987 }
5988 }
5989
5990
5991 // Implementation of ControlFlowOptimizer
5992
5993 ControlFlowOptimizer::ControlFlowOptimizer() :
5994 _original_preds(4)
5995 {
5996 }
5997
5998 void ControlFlowOptimizer::optimize(BlockList* code) {
5999 ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6000
6001 // push the OSR entry block to the end so that we're not jumping over it.
6002 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6003 if (osr_entry) {
6004 int index = osr_entry->linear_scan_number();
6005 assert(code->at(index) == osr_entry, "wrong index");
6006 code->remove_at(index);
6007 code->append(osr_entry);
6008 }
6009
6010 optimizer.reorder_short_loops(code);
6011 optimizer.delete_empty_blocks(code);
6012 optimizer.delete_unnecessary_jumps(code);
6013 optimizer.delete_jumps_to_return(code);
6014 }
6015
6016 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6017 int i = header_idx + 1;
6018 int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6019 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6020 i++;
6021 }
6022
6023 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6024 int end_idx = i - 1;
6025 BlockBegin* end_block = code->at(end_idx);
6026
6027 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6028 // short loop from header_idx to end_idx found -> reorder blocks such that
6029 // the header_block is the last block instead of the first block of the loop
6030 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6031 end_idx - header_idx + 1,
6032 header_block->block_id(), end_block->block_id()));
6033
6034 for (int j = header_idx; j < end_idx; j++) {
6035 code->at_put(j, code->at(j + 1));
6036 }
6037 code->at_put(end_idx, header_block);
6038
6039 // correct the flags so that any loop alignment occurs in the right place.
6040 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6041 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6042 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6043 }
6044 }
6045 }
6046
6047 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6048 for (int i = code->length() - 1; i >= 0; i--) {
6049 BlockBegin* block = code->at(i);
6050
6051 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6052 reorder_short_loop(code, block, i);
6053 }
6054 }
6055
6056 DEBUG_ONLY(verify(code));
6057 }
6058
6059 // only blocks with exactly one successor can be deleted. Such blocks
6060 // must always end with an unconditional branch to this successor
6061 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6062 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6063 return false;
6064 }
6065
6066 LIR_OpList* instructions = block->lir()->instructions_list();
6067
6068 assert(instructions->length() >= 2, "block must have label and branch");
6069 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6070 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6071 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6072 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6073
6074 // block must have exactly one successor
6075
6076 if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6077 return true;
6078 }
6079 return false;
6080 }
6081
6082 // substitute branch targets in all branch-instructions of this blocks
6083 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6084 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6085
6086 LIR_OpList* instructions = block->lir()->instructions_list();
6087
6088 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6089 for (int i = instructions->length() - 1; i >= 1; i--) {
6090 LIR_Op* op = instructions->at(i);
6091
6092 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6093 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6094 LIR_OpBranch* branch = (LIR_OpBranch*)op;
6095
6096 if (branch->block() == target_from) {
6097 branch->change_block(target_to);
6098 }
6099 if (branch->ublock() == target_from) {
6100 branch->change_ublock(target_to);
6101 }
6102 }
6103 }
6104 }
6105
6106 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6107 int old_pos = 0;
6108 int new_pos = 0;
6109 int num_blocks = code->length();
6110
6111 while (old_pos < num_blocks) {
6112 BlockBegin* block = code->at(old_pos);
6113
6114 if (can_delete_block(block)) {
6115 BlockBegin* new_target = block->sux_at(0);
6116
6117 // propagate backward branch target flag for correct code alignment
6118 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6119 new_target->set(BlockBegin::backward_branch_target_flag);
6120 }
6121
6122 // collect a list with all predecessors that contains each predecessor only once
6123 // the predecessors of cur are changed during the substitution, so a copy of the
6124 // predecessor list is necessary
6125 int j;
6126 _original_preds.clear();
6127 for (j = block->number_of_preds() - 1; j >= 0; j--) {
6128 BlockBegin* pred = block->pred_at(j);
6129 if (_original_preds.index_of(pred) == -1) {
6130 _original_preds.append(pred);
6131 }
6132 }
6133
6134 for (j = _original_preds.length() - 1; j >= 0; j--) {
6135 BlockBegin* pred = _original_preds.at(j);
6136 substitute_branch_target(pred, block, new_target);
6137 pred->substitute_sux(block, new_target);
6138 }
6139 } else {
6140 // adjust position of this block in the block list if blocks before
6141 // have been deleted
6142 if (new_pos != old_pos) {
6143 code->at_put(new_pos, code->at(old_pos));
6144 }
6145 new_pos++;
6146 }
6147 old_pos++;
6148 }
6149 code->truncate(new_pos);
6150
6151 DEBUG_ONLY(verify(code));
6152 }
6153
6154 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6155 // skip the last block because there a branch is always necessary
6156 for (int i = code->length() - 2; i >= 0; i--) {
6157 BlockBegin* block = code->at(i);
6158 LIR_OpList* instructions = block->lir()->instructions_list();
6159
6160 LIR_Op* last_op = instructions->last();
6161 if (last_op->code() == lir_branch) {
6162 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6163 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6164
6165 assert(last_branch->block() != NULL, "last branch must always have a block as target");
6166 assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6167
6168 if (last_branch->info() == NULL) {
6169 if (last_branch->block() == code->at(i + 1)) {
6170
6171 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6172
6173 // delete last branch instruction
6174 instructions->truncate(instructions->length() - 1);
6175
6176 } else {
6177 LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6178 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6179 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6180 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6181
6182 LIR_Op2* prev_cmp = NULL;
6183
6184 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6185 prev_op = instructions->at(j);
6186 if(prev_op->code() == lir_cmp) {
6187 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6188 prev_cmp = (LIR_Op2*)prev_op;
6189 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6190 }
6191 }
6192 assert(prev_cmp != NULL, "should have found comp instruction for branch");
6193 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6194
6195 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6196
6197 // eliminate a conditional branch to the immediate successor
6198 prev_branch->change_block(last_branch->block());
6199 prev_branch->negate_cond();
6200 prev_cmp->set_condition(prev_branch->cond());
6201 instructions->truncate(instructions->length() - 1);
6202 }
6203 }
6204 }
6205 }
6206 }
6207 }
6208
6209 DEBUG_ONLY(verify(code));
6210 }
6211
6212 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6213 #ifdef ASSERT
6214 BitMap return_converted(BlockBegin::number_of_blocks());
6215 return_converted.clear();
6216 #endif
6217
6218 for (int i = code->length() - 1; i >= 0; i--) {
6219 BlockBegin* block = code->at(i);
6220 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6221 LIR_Op* cur_last_op = cur_instructions->last();
6222
6223 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6224 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6225 // the block contains only a label and a return
6226 // if a predecessor ends with an unconditional jump to this block, then the jump
6227 // can be replaced with a return instruction
6228 //
6229 // Note: the original block with only a return statement cannot be deleted completely
6230 // because the predecessors might have other (conditional) jumps to this block
6231 // -> this may lead to unnecesary return instructions in the final code
6232
6233 assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6234 assert(block->number_of_sux() == 0 ||
6235 (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6236 "blocks that end with return must not have successors");
6237
6238 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6239 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6240
6241 for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6242 BlockBegin* pred = block->pred_at(j);
6243 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6244 LIR_Op* pred_last_op = pred_instructions->last();
6245
6246 if (pred_last_op->code() == lir_branch) {
6247 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6248 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6249
6250 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6251 // replace the jump to a return with a direct return
6252 // Note: currently the edge between the blocks is not deleted
6253 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6254 #ifdef ASSERT
6255 return_converted.set_bit(pred->block_id());
6256 #endif
6257 }
6258 }
6259 }
6260 }
6261 }
6262 }
6263
6264
6265 #ifdef ASSERT
6266 void ControlFlowOptimizer::verify(BlockList* code) {
6267 for (int i = 0; i < code->length(); i++) {
6268 BlockBegin* block = code->at(i);
6269 LIR_OpList* instructions = block->lir()->instructions_list();
6270
6271 int j;
6272 for (j = 0; j < instructions->length(); j++) {
6273 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6274
6275 if (op_branch != NULL) {
6276 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
6277 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
6278 }
6279 }
6280
6281 for (j = 0; j < block->number_of_sux() - 1; j++) {
6282 BlockBegin* sux = block->sux_at(j);
6283 assert(code->index_of(sux) != -1, "successor not valid");
6284 }
6285
6286 for (j = 0; j < block->number_of_preds() - 1; j++) {
6287 BlockBegin* pred = block->pred_at(j);
6288 assert(code->index_of(pred) != -1, "successor not valid");
6289 }
6290 }
6291 }
6292 #endif
6293
6294
6295 #ifndef PRODUCT
6296
6297 // Implementation of LinearStatistic
6298
6299 const char* LinearScanStatistic::counter_name(int counter_idx) {
6300 switch (counter_idx) {
6301 case counter_method: return "compiled methods";
6302 case counter_fpu_method: return "methods using fpu";
6303 case counter_loop_method: return "methods with loops";
6304 case counter_exception_method:return "methods with xhandler";
6305
6306 case counter_loop: return "loops";
6307 case counter_block: return "blocks";
6308 case counter_loop_block: return "blocks inside loop";
6309 case counter_exception_block: return "exception handler entries";
6310 case counter_interval: return "intervals";
6311 case counter_fixed_interval: return "fixed intervals";
6312 case counter_range: return "ranges";
6313 case counter_fixed_range: return "fixed ranges";
6314 case counter_use_pos: return "use positions";
6315 case counter_fixed_use_pos: return "fixed use positions";
6316 case counter_spill_slots: return "spill slots";
6317
6318 // counter for classes of lir instructions
6319 case counter_instruction: return "total instructions";
6320 case counter_label: return "labels";
6321 case counter_entry: return "method entries";
6322 case counter_return: return "method returns";
6323 case counter_call: return "method calls";
6324 case counter_move: return "moves";
6325 case counter_cmp: return "compare";
6326 case counter_cond_branch: return "conditional branches";
6327 case counter_uncond_branch: return "unconditional branches";
6328 case counter_stub_branch: return "branches to stub";
6329 case counter_alu: return "artithmetic + logic";
6330 case counter_alloc: return "allocations";
6331 case counter_sync: return "synchronisation";
6332 case counter_throw: return "throw";
6333 case counter_unwind: return "unwind";
6334 case counter_typecheck: return "type+null-checks";
6335 case counter_fpu_stack: return "fpu-stack";
6336 case counter_misc_inst: return "other instructions";
6337 case counter_other_inst: return "misc. instructions";
6338
6339 // counter for different types of moves
6340 case counter_move_total: return "total moves";
6341 case counter_move_reg_reg: return "register->register";
6342 case counter_move_reg_stack: return "register->stack";
6343 case counter_move_stack_reg: return "stack->register";
6344 case counter_move_stack_stack:return "stack->stack";
6345 case counter_move_reg_mem: return "register->memory";
6346 case counter_move_mem_reg: return "memory->register";
6347 case counter_move_const_any: return "constant->any";
6348
6349 case blank_line_1: return "";
6350 case blank_line_2: return "";
6351
6352 default: ShouldNotReachHere(); return "";
6353 }
6354 }
6355
6356 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6357 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6358 return counter_method;
6359 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6360 return counter_block;
6361 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6362 return counter_instruction;
6363 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6364 return counter_move_total;
6365 }
6366 return invalid_counter;
6367 }
6368
6369 LinearScanStatistic::LinearScanStatistic() {
6370 for (int i = 0; i < number_of_counters; i++) {
6371 _counters_sum[i] = 0;
6372 _counters_max[i] = -1;
6373 }
6374
6375 }
6376
6377 // add the method-local numbers to the total sum
6378 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6379 for (int i = 0; i < number_of_counters; i++) {
6380 _counters_sum[i] += method_statistic._counters_sum[i];
6381 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6382 }
6383 }
6384
6385 void LinearScanStatistic::print(const char* title) {
6386 if (CountLinearScan || TraceLinearScanLevel > 0) {
6387 tty->cr();
6388 tty->print_cr("***** LinearScan statistic - %s *****", title);
6389
6390 for (int i = 0; i < number_of_counters; i++) {
6391 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6392 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6393
6394 if (base_counter(i) != invalid_counter) {
6395 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
6396 } else {
6397 tty->print(" ");
6398 }
6399
6400 if (_counters_max[i] >= 0) {
6401 tty->print("%8d", _counters_max[i]);
6402 }
6403 }
6404 tty->cr();
6405 }
6406 }
6407 }
6408
6409 void LinearScanStatistic::collect(LinearScan* allocator) {
6410 inc_counter(counter_method);
6411 if (allocator->has_fpu_registers()) {
6412 inc_counter(counter_fpu_method);
6413 }
6414 if (allocator->num_loops() > 0) {
6415 inc_counter(counter_loop_method);
6416 }
6417 inc_counter(counter_loop, allocator->num_loops());
6418 inc_counter(counter_spill_slots, allocator->max_spills());
6419
6420 int i;
6421 for (i = 0; i < allocator->interval_count(); i++) {
6422 Interval* cur = allocator->interval_at(i);
6423
6424 if (cur != NULL) {
6425 inc_counter(counter_interval);
6426 inc_counter(counter_use_pos, cur->num_use_positions());
6427 if (LinearScan::is_precolored_interval(cur)) {
6428 inc_counter(counter_fixed_interval);
6429 inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6430 }
6431
6432 Range* range = cur->first();
6433 while (range != Range::end()) {
6434 inc_counter(counter_range);
6435 if (LinearScan::is_precolored_interval(cur)) {
6436 inc_counter(counter_fixed_range);
6437 }
6438 range = range->next();
6439 }
6440 }
6441 }
6442
6443 bool has_xhandlers = false;
6444 // Note: only count blocks that are in code-emit order
6445 for (i = 0; i < allocator->ir()->code()->length(); i++) {
6446 BlockBegin* cur = allocator->ir()->code()->at(i);
6447
6448 inc_counter(counter_block);
6449 if (cur->loop_depth() > 0) {
6450 inc_counter(counter_loop_block);
6451 }
6452 if (cur->is_set(BlockBegin::exception_entry_flag)) {
6453 inc_counter(counter_exception_block);
6454 has_xhandlers = true;
6455 }
6456
6457 LIR_OpList* instructions = cur->lir()->instructions_list();
6458 for (int j = 0; j < instructions->length(); j++) {
6459 LIR_Op* op = instructions->at(j);
6460
6461 inc_counter(counter_instruction);
6462
6463 switch (op->code()) {
6464 case lir_label: inc_counter(counter_label); break;
6465 case lir_std_entry:
6466 case lir_osr_entry: inc_counter(counter_entry); break;
6467 case lir_return: inc_counter(counter_return); break;
6468
6469 case lir_rtcall:
6470 case lir_static_call:
6471 case lir_optvirtual_call:
6472 case lir_virtual_call: inc_counter(counter_call); break;
6473
6474 case lir_move: {
6475 inc_counter(counter_move);
6476 inc_counter(counter_move_total);
6477
6478 LIR_Opr in = op->as_Op1()->in_opr();
6479 LIR_Opr res = op->as_Op1()->result_opr();
6480 if (in->is_register()) {
6481 if (res->is_register()) {
6482 inc_counter(counter_move_reg_reg);
6483 } else if (res->is_stack()) {
6484 inc_counter(counter_move_reg_stack);
6485 } else if (res->is_address()) {
6486 inc_counter(counter_move_reg_mem);
6487 } else {
6488 ShouldNotReachHere();
6489 }
6490 } else if (in->is_stack()) {
6491 if (res->is_register()) {
6492 inc_counter(counter_move_stack_reg);
6493 } else {
6494 inc_counter(counter_move_stack_stack);
6495 }
6496 } else if (in->is_address()) {
6497 assert(res->is_register(), "must be");
6498 inc_counter(counter_move_mem_reg);
6499 } else if (in->is_constant()) {
6500 inc_counter(counter_move_const_any);
6501 } else {
6502 ShouldNotReachHere();
6503 }
6504 break;
6505 }
6506
6507 case lir_cmp: inc_counter(counter_cmp); break;
6508
6509 case lir_branch:
6510 case lir_cond_float_branch: {
6511 LIR_OpBranch* branch = op->as_OpBranch();
6512 if (branch->block() == NULL) {
6513 inc_counter(counter_stub_branch);
6514 } else if (branch->cond() == lir_cond_always) {
6515 inc_counter(counter_uncond_branch);
6516 } else {
6517 inc_counter(counter_cond_branch);
6518 }
6519 break;
6520 }
6521
6522 case lir_neg:
6523 case lir_add:
6524 case lir_sub:
6525 case lir_mul:
6526 case lir_mul_strictfp:
6527 case lir_div:
6528 case lir_div_strictfp:
6529 case lir_rem:
6530 case lir_sqrt:
6531 case lir_sin:
6532 case lir_cos:
6533 case lir_abs:
6534 case lir_log10:
6535 case lir_log:
6536 case lir_logic_and:
6537 case lir_logic_or:
6538 case lir_logic_xor:
6539 case lir_shl:
6540 case lir_shr:
6541 case lir_ushr: inc_counter(counter_alu); break;
6542
6543 case lir_alloc_object:
6544 case lir_alloc_array: inc_counter(counter_alloc); break;
6545
6546 case lir_monaddr:
6547 case lir_lock:
6548 case lir_unlock: inc_counter(counter_sync); break;
6549
6550 case lir_throw: inc_counter(counter_throw); break;
6551
6552 case lir_unwind: inc_counter(counter_unwind); break;
6553
6554 case lir_null_check:
6555 case lir_leal:
6556 case lir_instanceof:
6557 case lir_checkcast:
6558 case lir_store_check: inc_counter(counter_typecheck); break;
6559
6560 case lir_fpop_raw:
6561 case lir_fxch:
6562 case lir_fld: inc_counter(counter_fpu_stack); break;
6563
6564 case lir_nop:
6565 case lir_push:
6566 case lir_pop:
6567 case lir_convert:
6568 case lir_roundfp:
6569 case lir_cmove: inc_counter(counter_misc_inst); break;
6570
6571 default: inc_counter(counter_other_inst); break;
6572 }
6573 }
6574 }
6575
6576 if (has_xhandlers) {
6577 inc_counter(counter_exception_method);
6578 }
6579 }
6580
6581 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6582 if (CountLinearScan || TraceLinearScanLevel > 0) {
6583
6584 LinearScanStatistic local_statistic = LinearScanStatistic();
6585
6586 local_statistic.collect(allocator);
6587 global_statistic.sum_up(local_statistic);
6588
6589 if (TraceLinearScanLevel > 2) {
6590 local_statistic.print("current local statistic");
6591 }
6592 }
6593 }
6594
6595
6596 // Implementation of LinearTimers
6597
6598 LinearScanTimers::LinearScanTimers() {
6599 for (int i = 0; i < number_of_timers; i++) {
6600 timer(i)->reset();
6601 }
6602 }
6603
6604 const char* LinearScanTimers::timer_name(int idx) {
6605 switch (idx) {
6606 case timer_do_nothing: return "Nothing (Time Check)";
6607 case timer_number_instructions: return "Number Instructions";
6608 case timer_compute_local_live_sets: return "Local Live Sets";
6609 case timer_compute_global_live_sets: return "Global Live Sets";
6610 case timer_build_intervals: return "Build Intervals";
6611 case timer_sort_intervals_before: return "Sort Intervals Before";
6612 case timer_allocate_registers: return "Allocate Registers";
6613 case timer_resolve_data_flow: return "Resolve Data Flow";
6614 case timer_sort_intervals_after: return "Sort Intervals After";
6615 case timer_eliminate_spill_moves: return "Spill optimization";
6616 case timer_assign_reg_num: return "Assign Reg Num";
6617 case timer_allocate_fpu_stack: return "Allocate FPU Stack";
6618 case timer_optimize_lir: return "Optimize LIR";
6619 default: ShouldNotReachHere(); return "";
6620 }
6621 }
6622
6623 void LinearScanTimers::begin_method() {
6624 if (TimeEachLinearScan) {
6625 // reset all timers to measure only current method
6626 for (int i = 0; i < number_of_timers; i++) {
6627 timer(i)->reset();
6628 }
6629 }
6630 }
6631
6632 void LinearScanTimers::end_method(LinearScan* allocator) {
6633 if (TimeEachLinearScan) {
6634
6635 double c = timer(timer_do_nothing)->seconds();
6636 double total = 0;
6637 for (int i = 1; i < number_of_timers; i++) {
6638 total += timer(i)->seconds() - c;
6639 }
6640
6641 if (total >= 0.0005) {
6642 // print all information in one line for automatic processing
6643 tty->print("@"); allocator->compilation()->method()->print_name();
6644
6645 tty->print("@ %d ", allocator->compilation()->method()->code_size());
6646 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6647 tty->print("@ %d ", allocator->block_count());
6648 tty->print("@ %d ", allocator->num_virtual_regs());
6649 tty->print("@ %d ", allocator->interval_count());
6650 tty->print("@ %d ", allocator->_num_calls);
6651 tty->print("@ %d ", allocator->num_loops());
6652
6653 tty->print("@ %6.6f ", total);
6654 for (int i = 1; i < number_of_timers; i++) {
6655 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6656 }
6657 tty->cr();
6658 }
6659 }
6660 }
6661
6662 void LinearScanTimers::print(double total_time) {
6663 if (TimeLinearScan) {
6664 // correction value: sum of dummy-timer that only measures the time that
6665 // is necesary to start and stop itself
6666 double c = timer(timer_do_nothing)->seconds();
6667
6668 for (int i = 0; i < number_of_timers; i++) {
6669 double t = timer(i)->seconds();
6670 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6671 }
6672 }
6673 }
6674
6675 #endif // #ifndef PRODUCT