1 /*
2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "gc/shared/cardTableBarrierSet.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "interpreter/interpreterRuntime.hpp"
33 #include "interpreter/templateInterpreterGenerator.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "prims/jvm_misc.hpp"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.inline.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "utilities/hashtable.hpp"
44 #include "utilities/macros.hpp"
45 #if INCLUDE_ALL_GCS
46 #include "gc/g1/g1BarrierSet.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49
50 // Returns whether given imm has equal bit fields <0:size-1> and <size:2*size-1>.
51 inline bool Assembler::LogicalImmediate::has_equal_subpatterns(uintx imm, int size) {
52 uintx mask = right_n_bits(size);
53 uintx subpattern1 = mask_bits(imm, mask);
54 uintx subpattern2 = mask_bits(imm >> size, mask);
55 return subpattern1 == subpattern2;
56 }
57
58 // Returns least size that is a power of two from 2 to 64 with the proviso that given
59 // imm is composed of repeating patterns of this size.
60 inline int Assembler::LogicalImmediate::least_pattern_size(uintx imm) {
61 int size = BitsPerWord;
62 while (size > 2 && has_equal_subpatterns(imm, size >> 1)) {
63 size >>= 1;
64 }
65 return size;
66 }
67
68 // Returns count of set bits in given imm. Based on variable-precision SWAR algorithm.
69 inline int Assembler::LogicalImmediate::population_count(uintx x) {
70 x -= ((x >> 1) & 0x5555555555555555L);
71 x = (((x >> 2) & 0x3333333333333333L) + (x & 0x3333333333333333L));
72 x = (((x >> 4) + x) & 0x0f0f0f0f0f0f0f0fL);
73 x += (x >> 8);
74 x += (x >> 16);
75 x += (x >> 32);
76 return(x & 0x7f);
77 }
78
79 // Let given x be <A:B> where B = 0 and least bit of A = 1. Returns <A:C>, where C is B-size set bits.
80 inline uintx Assembler::LogicalImmediate::set_least_zeroes(uintx x) {
81 return x | (x - 1);
82 }
83
84
85 #ifdef ASSERT
86
87 // Restores immediate by encoded bit masks.
88 uintx Assembler::LogicalImmediate::decode() {
89 assert (_encoded, "should be");
90
91 int len_code = (_immN << 6) | ((~_imms) & 0x3f);
92 assert (len_code != 0, "should be");
93
94 int len = 6;
95 while (!is_set_nth_bit(len_code, len)) len--;
96 int esize = 1 << len;
97 assert (len > 0, "should be");
98 assert ((_is32bit ? 32 : 64) >= esize, "should be");
99
100 int levels = right_n_bits(len);
101 int S = _imms & levels;
102 int R = _immr & levels;
103
104 assert (S != levels, "should be");
105
106 uintx welem = right_n_bits(S + 1);
107 uintx wmask = (R == 0) ? welem : ((welem >> R) | (welem << (esize - R)));
108
109 for (int size = esize; size < 64; size <<= 1) {
110 wmask |= (wmask << size);
111 }
112
113 return wmask;
114 }
115
116 #endif
117
118
119 // Constructs LogicalImmediate by given imm. Figures out if given imm can be used in AArch64 logical
120 // instructions (AND, ANDS, EOR, ORR) and saves its encoding.
121 void Assembler::LogicalImmediate::construct(uintx imm, bool is32) {
122 _is32bit = is32;
123
124 if (is32) {
125 assert(((imm >> 32) == 0) || (((intx)imm >> 31) == -1), "32-bit immediate is out of range");
126
127 // Replicate low 32 bits.
128 imm &= 0xffffffff;
129 imm |= imm << 32;
130 }
131
132 // All-zeroes and all-ones can not be encoded.
133 if (imm != 0 && (~imm != 0)) {
134
135 // Let LPS (least pattern size) be the least size (power of two from 2 to 64) of repeating
136 // patterns in the immediate. If immediate value can be encoded, it is encoded by pattern
137 // of exactly LPS size (due to structure of valid patterns). In order to verify
138 // that immediate value can be encoded, LPS is calculated and <LPS-1:0> bits of immediate
139 // are verified to be valid pattern.
140 int lps = least_pattern_size(imm);
141 uintx lps_mask = right_n_bits(lps);
142
143 // A valid pattern has one of the following forms:
144 // | 0 x A | 1 x B | 0 x C |, where B > 0 and C > 0, or
145 // | 1 x A | 0 x B | 1 x C |, where B > 0 and C > 0.
146 // For simplicity, the second form of the pattern is inverted into the first form.
147 bool inverted = imm & 0x1;
148 uintx pattern = (inverted ? ~imm : imm) & lps_mask;
149
150 // | 0 x A | 1 x (B + C) |
151 uintx without_least_zeroes = set_least_zeroes(pattern);
152
153 // Pattern is valid iff without least zeroes it is a power of two - 1.
154 if ((without_least_zeroes & (without_least_zeroes + 1)) == 0) {
155
156 // Count B as population count of pattern.
157 int bits_count = population_count(pattern);
158
159 // Count B+C as population count of pattern without least zeroes
160 int left_range = population_count(without_least_zeroes);
161
162 // S-prefix is a part of imms field which encodes LPS.
163 // LPS | S prefix
164 // 64 | not defined
165 // 32 | 0b0
166 // 16 | 0b10
167 // 8 | 0b110
168 // 4 | 0b1110
169 // 2 | 0b11110
170 int s_prefix = (lps == 64) ? 0 : ~set_least_zeroes(lps) & 0x3f;
171
172 // immN bit is set iff LPS == 64.
173 _immN = (lps == 64) ? 1 : 0;
174 assert (!is32 || (_immN == 0), "32-bit immediate should be encoded with zero N-bit");
175
176 // immr is the rotation size.
177 _immr = lps + (inverted ? 0 : bits_count) - left_range;
178
179 // imms is the field that encodes bits count and S-prefix.
180 _imms = ((inverted ? (lps - bits_count) : bits_count) - 1) | s_prefix;
181
182 _encoded = true;
183 assert (decode() == imm, "illegal encoding");
184
185 return;
186 }
187 }
188
189 _encoded = false;
190 }