1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "jvm.h"
30 #include "asm/assembler.hpp"
31 #include "asm/assembler.inline.hpp"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/cardTable.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "nativeInst_aarch64.hpp"
40 #include "oops/compressedOops.inline.hpp"
41 #include "oops/klass.inline.hpp"
42 #include "oops/oop.hpp"
43 #include "opto/compile.hpp"
44 #include "opto/intrinsicnode.hpp"
45 #include "opto/node.hpp"
46 #include "runtime/biasedLocking.hpp"
47 #include "runtime/icache.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/jniHandles.inline.hpp"
50 #include "runtime/sharedRuntime.hpp"
51 #include "runtime/thread.hpp"
52
53 #ifdef PRODUCT
54 #define BLOCK_COMMENT(str) /* nothing */
55 #define STOP(error) stop(error)
56 #else
57 #define BLOCK_COMMENT(str) block_comment(str)
58 #define STOP(error) block_comment(error); stop(error)
59 #endif
60
61 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
62
63 // Patch any kind of instruction; there may be several instructions.
64 // Return the total length (in bytes) of the instructions.
65 int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
66 int instructions = 1;
67 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
68 long offset = (target - branch) >> 2;
69 unsigned insn = *(unsigned*)branch;
70 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
71 // Load register (literal)
72 Instruction_aarch64::spatch(branch, 23, 5, offset);
73 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
74 // Unconditional branch (immediate)
75 Instruction_aarch64::spatch(branch, 25, 0, offset);
76 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
77 // Conditional branch (immediate)
78 Instruction_aarch64::spatch(branch, 23, 5, offset);
79 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
80 // Compare & branch (immediate)
81 Instruction_aarch64::spatch(branch, 23, 5, offset);
82 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
83 // Test & branch (immediate)
84 Instruction_aarch64::spatch(branch, 18, 5, offset);
85 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
86 // PC-rel. addressing
87 offset = target-branch;
88 int shift = Instruction_aarch64::extract(insn, 31, 31);
89 if (shift) {
90 u_int64_t dest = (u_int64_t)target;
91 uint64_t pc_page = (uint64_t)branch >> 12;
92 uint64_t adr_page = (uint64_t)target >> 12;
93 unsigned offset_lo = dest & 0xfff;
94 offset = adr_page - pc_page;
95
96 // We handle 4 types of PC relative addressing
97 // 1 - adrp Rx, target_page
98 // ldr/str Ry, [Rx, #offset_in_page]
99 // 2 - adrp Rx, target_page
100 // add Ry, Rx, #offset_in_page
101 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
102 // movk Rx, #imm16<<32
103 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
104 // In the first 3 cases we must check that Rx is the same in the adrp and the
105 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end
106 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened
107 // to be followed by a random unrelated ldr/str, add or movk instruction.
108 //
109 unsigned insn2 = ((unsigned*)branch)[1];
110 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
111 Instruction_aarch64::extract(insn, 4, 0) ==
112 Instruction_aarch64::extract(insn2, 9, 5)) {
113 // Load/store register (unsigned immediate)
114 unsigned size = Instruction_aarch64::extract(insn2, 31, 30);
115 Instruction_aarch64::patch(branch + sizeof (unsigned),
116 21, 10, offset_lo >> size);
117 guarantee(((dest >> size) << size) == dest, "misaligned target");
118 instructions = 2;
119 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
120 Instruction_aarch64::extract(insn, 4, 0) ==
121 Instruction_aarch64::extract(insn2, 4, 0)) {
122 // add (immediate)
123 Instruction_aarch64::patch(branch + sizeof (unsigned),
124 21, 10, offset_lo);
125 instructions = 2;
126 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
127 Instruction_aarch64::extract(insn, 4, 0) ==
128 Instruction_aarch64::extract(insn2, 4, 0)) {
129 // movk #imm16<<32
130 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
131 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
132 long pc_page = (long)branch >> 12;
133 long adr_page = (long)dest >> 12;
134 offset = adr_page - pc_page;
135 instructions = 2;
136 }
137 }
138 int offset_lo = offset & 3;
139 offset >>= 2;
140 Instruction_aarch64::spatch(branch, 23, 5, offset);
141 Instruction_aarch64::patch(branch, 30, 29, offset_lo);
142 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) {
143 u_int64_t dest = (u_int64_t)target;
144 // Move wide constant
145 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch");
146 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch");
147 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff);
148 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
149 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
150 assert(target_addr_for_insn(branch) == target, "should be");
151 instructions = 3;
152 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
153 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
154 // nothing to do
155 assert(target == 0, "did not expect to relocate target for polling page load");
156 } else {
157 ShouldNotReachHere();
158 }
159 return instructions * NativeInstruction::instruction_size;
160 }
161
162 int MacroAssembler::patch_oop(address insn_addr, address o) {
163 int instructions;
164 unsigned insn = *(unsigned*)insn_addr;
165 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
166
167 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
168 // narrow OOPs by setting the upper 16 bits in the first
169 // instruction.
170 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
171 // Move narrow OOP
172 narrowOop n = CompressedOops::encode((oop)o);
173 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
174 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
175 instructions = 2;
176 } else {
177 // Move wide OOP
178 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
179 uintptr_t dest = (uintptr_t)o;
180 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
181 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
182 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
183 instructions = 3;
184 }
185 return instructions * NativeInstruction::instruction_size;
186 }
187
188 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
189 // Metatdata pointers are either narrow (32 bits) or wide (48 bits).
190 // We encode narrow ones by setting the upper 16 bits in the first
191 // instruction.
192 NativeInstruction *insn = nativeInstruction_at(insn_addr);
193 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
194 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
195
196 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
197 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
198 return 2 * NativeInstruction::instruction_size;
199 }
200
201 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
202 long offset = 0;
203 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
204 // Load register (literal)
205 offset = Instruction_aarch64::sextract(insn, 23, 5);
206 return address(((uint64_t)insn_addr + (offset << 2)));
207 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
208 // Unconditional branch (immediate)
209 offset = Instruction_aarch64::sextract(insn, 25, 0);
210 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
211 // Conditional branch (immediate)
212 offset = Instruction_aarch64::sextract(insn, 23, 5);
213 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
214 // Compare & branch (immediate)
215 offset = Instruction_aarch64::sextract(insn, 23, 5);
216 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
217 // Test & branch (immediate)
218 offset = Instruction_aarch64::sextract(insn, 18, 5);
219 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
220 // PC-rel. addressing
221 offset = Instruction_aarch64::extract(insn, 30, 29);
222 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
223 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0;
224 if (shift) {
225 offset <<= shift;
226 uint64_t target_page = ((uint64_t)insn_addr) + offset;
227 target_page &= ((uint64_t)-1) << shift;
228 // Return the target address for the following sequences
229 // 1 - adrp Rx, target_page
230 // ldr/str Ry, [Rx, #offset_in_page]
231 // 2 - adrp Rx, target_page
232 // add Ry, Rx, #offset_in_page
233 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0)
234 // movk Rx, #imm12<<32
235 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0)
236 //
237 // In the first two cases we check that the register is the same and
238 // return the target_page + the offset within the page.
239 // Otherwise we assume it is a page aligned relocation and return
240 // the target page only.
241 //
242 unsigned insn2 = ((unsigned*)insn_addr)[1];
243 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
244 Instruction_aarch64::extract(insn, 4, 0) ==
245 Instruction_aarch64::extract(insn2, 9, 5)) {
246 // Load/store register (unsigned immediate)
247 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
248 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30);
249 return address(target_page + (byte_offset << size));
250 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
251 Instruction_aarch64::extract(insn, 4, 0) ==
252 Instruction_aarch64::extract(insn2, 4, 0)) {
253 // add (immediate)
254 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
255 return address(target_page + byte_offset);
256 } else {
257 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
258 Instruction_aarch64::extract(insn, 4, 0) ==
259 Instruction_aarch64::extract(insn2, 4, 0)) {
260 target_page = (target_page & 0xffffffff) |
261 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
262 }
263 return (address)target_page;
264 }
265 } else {
266 ShouldNotReachHere();
267 }
268 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) {
269 u_int32_t *insns = (u_int32_t *)insn_addr;
270 // Move wide constant: movz, movk, movk. See movptr().
271 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
272 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
273 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5))
274 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
275 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
276 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
277 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
278 return 0;
279 } else {
280 ShouldNotReachHere();
281 }
282 return address(((uint64_t)insn_addr + (offset << 2)));
283 }
284
285 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
286 dsb(Assembler::SY);
287 }
288
289 void MacroAssembler::safepoint_poll(Label& slow_path) {
290 if (SafepointMechanism::uses_thread_local_poll()) {
291 ldr(rscratch1, Address(rthread, Thread::polling_page_offset()));
292 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
293 } else {
294 unsigned long offset;
295 adrp(rscratch1, ExternalAddress(SafepointSynchronize::address_of_state()), offset);
296 ldrw(rscratch1, Address(rscratch1, offset));
297 assert(SafepointSynchronize::_not_synchronized == 0, "rewrite this code");
298 cbnz(rscratch1, slow_path);
299 }
300 }
301
302 // Just like safepoint_poll, but use an acquiring load for thread-
303 // local polling.
304 //
305 // We need an acquire here to ensure that any subsequent load of the
306 // global SafepointSynchronize::_state flag is ordered after this load
307 // of the local Thread::_polling page. We don't want this poll to
308 // return false (i.e. not safepointing) and a later poll of the global
309 // SafepointSynchronize::_state spuriously to return true.
310 //
311 // This is to avoid a race when we're in a native->Java transition
312 // racing the code which wakes up from a safepoint.
313 //
314 void MacroAssembler::safepoint_poll_acquire(Label& slow_path) {
315 if (SafepointMechanism::uses_thread_local_poll()) {
316 lea(rscratch1, Address(rthread, Thread::polling_page_offset()));
317 ldar(rscratch1, rscratch1);
318 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path);
319 } else {
320 safepoint_poll(slow_path);
321 }
322 }
323
324 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
325 // we must set sp to zero to clear frame
326 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
327
328 // must clear fp, so that compiled frames are not confused; it is
329 // possible that we need it only for debugging
330 if (clear_fp) {
331 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
332 }
333
334 // Always clear the pc because it could have been set by make_walkable()
335 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
336 }
337
338 // Calls to C land
339 //
340 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
341 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
342 // has to be reset to 0. This is required to allow proper stack traversal.
343 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
344 Register last_java_fp,
345 Register last_java_pc,
346 Register scratch) {
347
348 if (last_java_pc->is_valid()) {
349 str(last_java_pc, Address(rthread,
350 JavaThread::frame_anchor_offset()
351 + JavaFrameAnchor::last_Java_pc_offset()));
352 }
353
354 // determine last_java_sp register
355 if (last_java_sp == sp) {
356 mov(scratch, sp);
357 last_java_sp = scratch;
358 } else if (!last_java_sp->is_valid()) {
359 last_java_sp = esp;
360 }
361
362 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
363
364 // last_java_fp is optional
365 if (last_java_fp->is_valid()) {
366 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
367 }
368 }
369
370 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
371 Register last_java_fp,
372 address last_java_pc,
373 Register scratch) {
374 if (last_java_pc != NULL) {
375 adr(scratch, last_java_pc);
376 } else {
377 // FIXME: This is almost never correct. We should delete all
378 // cases of set_last_Java_frame with last_java_pc=NULL and use the
379 // correct return address instead.
380 adr(scratch, pc());
381 }
382
383 str(scratch, Address(rthread,
384 JavaThread::frame_anchor_offset()
385 + JavaFrameAnchor::last_Java_pc_offset()));
386
387 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
388 }
389
390 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
391 Register last_java_fp,
392 Label &L,
393 Register scratch) {
394 if (L.is_bound()) {
395 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
396 } else {
397 InstructionMark im(this);
398 L.add_patch_at(code(), locator());
399 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch);
400 }
401 }
402
403 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
404 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
405 assert(CodeCache::find_blob(entry.target()) != NULL,
406 "destination of far call not found in code cache");
407 if (far_branches()) {
408 unsigned long offset;
409 // We can use ADRP here because we know that the total size of
410 // the code cache cannot exceed 2Gb.
411 adrp(tmp, entry, offset);
412 add(tmp, tmp, offset);
413 if (cbuf) cbuf->set_insts_mark();
414 blr(tmp);
415 } else {
416 if (cbuf) cbuf->set_insts_mark();
417 bl(entry);
418 }
419 }
420
421 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
422 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
423 assert(CodeCache::find_blob(entry.target()) != NULL,
424 "destination of far call not found in code cache");
425 if (far_branches()) {
426 unsigned long offset;
427 // We can use ADRP here because we know that the total size of
428 // the code cache cannot exceed 2Gb.
429 adrp(tmp, entry, offset);
430 add(tmp, tmp, offset);
431 if (cbuf) cbuf->set_insts_mark();
432 br(tmp);
433 } else {
434 if (cbuf) cbuf->set_insts_mark();
435 b(entry);
436 }
437 }
438
439 void MacroAssembler::reserved_stack_check() {
440 // testing if reserved zone needs to be enabled
441 Label no_reserved_zone_enabling;
442
443 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
444 cmp(sp, rscratch1);
445 br(Assembler::LO, no_reserved_zone_enabling);
446
447 enter(); // LR and FP are live.
448 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone));
449 mov(c_rarg0, rthread);
450 blr(rscratch1);
451 leave();
452
453 // We have already removed our own frame.
454 // throw_delayed_StackOverflowError will think that it's been
455 // called by our caller.
456 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
457 br(rscratch1);
458 should_not_reach_here();
459
460 bind(no_reserved_zone_enabling);
461 }
462
463 int MacroAssembler::biased_locking_enter(Register lock_reg,
464 Register obj_reg,
465 Register swap_reg,
466 Register tmp_reg,
467 bool swap_reg_contains_mark,
468 Label& done,
469 Label* slow_case,
470 BiasedLockingCounters* counters) {
471 assert(UseBiasedLocking, "why call this otherwise?");
472 assert_different_registers(lock_reg, obj_reg, swap_reg);
473
474 if (PrintBiasedLockingStatistics && counters == NULL)
475 counters = BiasedLocking::counters();
476
477 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
478 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
479 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
480 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
481 Address saved_mark_addr(lock_reg, 0);
482
483 // Biased locking
484 // See whether the lock is currently biased toward our thread and
485 // whether the epoch is still valid
486 // Note that the runtime guarantees sufficient alignment of JavaThread
487 // pointers to allow age to be placed into low bits
488 // First check to see whether biasing is even enabled for this object
489 Label cas_label;
490 int null_check_offset = -1;
491 if (!swap_reg_contains_mark) {
492 null_check_offset = offset();
493 ldr(swap_reg, mark_addr);
494 }
495 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place);
496 cmp(tmp_reg, markOopDesc::biased_lock_pattern);
497 br(Assembler::NE, cas_label);
498 // The bias pattern is present in the object's header. Need to check
499 // whether the bias owner and the epoch are both still current.
500 load_prototype_header(tmp_reg, obj_reg);
501 orr(tmp_reg, tmp_reg, rthread);
502 eor(tmp_reg, swap_reg, tmp_reg);
503 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place));
504 if (counters != NULL) {
505 Label around;
506 cbnz(tmp_reg, around);
507 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2);
508 b(done);
509 bind(around);
510 } else {
511 cbz(tmp_reg, done);
512 }
513
514 Label try_revoke_bias;
515 Label try_rebias;
516
517 // At this point we know that the header has the bias pattern and
518 // that we are not the bias owner in the current epoch. We need to
519 // figure out more details about the state of the header in order to
520 // know what operations can be legally performed on the object's
521 // header.
522
523 // If the low three bits in the xor result aren't clear, that means
524 // the prototype header is no longer biased and we have to revoke
525 // the bias on this object.
526 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place);
527 cbnz(rscratch1, try_revoke_bias);
528
529 // Biasing is still enabled for this data type. See whether the
530 // epoch of the current bias is still valid, meaning that the epoch
531 // bits of the mark word are equal to the epoch bits of the
532 // prototype header. (Note that the prototype header's epoch bits
533 // only change at a safepoint.) If not, attempt to rebias the object
534 // toward the current thread. Note that we must be absolutely sure
535 // that the current epoch is invalid in order to do this because
536 // otherwise the manipulations it performs on the mark word are
537 // illegal.
538 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place);
539 cbnz(rscratch1, try_rebias);
540
541 // The epoch of the current bias is still valid but we know nothing
542 // about the owner; it might be set or it might be clear. Try to
543 // acquire the bias of the object using an atomic operation. If this
544 // fails we will go in to the runtime to revoke the object's bias.
545 // Note that we first construct the presumed unbiased header so we
546 // don't accidentally blow away another thread's valid bias.
547 {
548 Label here;
549 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
550 andr(swap_reg, swap_reg, rscratch1);
551 orr(tmp_reg, swap_reg, rthread);
552 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
553 // If the biasing toward our thread failed, this means that
554 // another thread succeeded in biasing it toward itself and we
555 // need to revoke that bias. The revocation will occur in the
556 // interpreter runtime in the slow case.
557 bind(here);
558 if (counters != NULL) {
559 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()),
560 tmp_reg, rscratch1, rscratch2);
561 }
562 }
563 b(done);
564
565 bind(try_rebias);
566 // At this point we know the epoch has expired, meaning that the
567 // current "bias owner", if any, is actually invalid. Under these
568 // circumstances _only_, we are allowed to use the current header's
569 // value as the comparison value when doing the cas to acquire the
570 // bias in the current epoch. In other words, we allow transfer of
571 // the bias from one thread to another directly in this situation.
572 //
573 // FIXME: due to a lack of registers we currently blow away the age
574 // bits in this situation. Should attempt to preserve them.
575 {
576 Label here;
577 load_prototype_header(tmp_reg, obj_reg);
578 orr(tmp_reg, rthread, tmp_reg);
579 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case);
580 // If the biasing toward our thread failed, then another thread
581 // succeeded in biasing it toward itself and we need to revoke that
582 // bias. The revocation will occur in the runtime in the slow case.
583 bind(here);
584 if (counters != NULL) {
585 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()),
586 tmp_reg, rscratch1, rscratch2);
587 }
588 }
589 b(done);
590
591 bind(try_revoke_bias);
592 // The prototype mark in the klass doesn't have the bias bit set any
593 // more, indicating that objects of this data type are not supposed
594 // to be biased any more. We are going to try to reset the mark of
595 // this object to the prototype value and fall through to the
596 // CAS-based locking scheme. Note that if our CAS fails, it means
597 // that another thread raced us for the privilege of revoking the
598 // bias of this particular object, so it's okay to continue in the
599 // normal locking code.
600 //
601 // FIXME: due to a lack of registers we currently blow away the age
602 // bits in this situation. Should attempt to preserve them.
603 {
604 Label here, nope;
605 load_prototype_header(tmp_reg, obj_reg);
606 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope);
607 bind(here);
608
609 // Fall through to the normal CAS-based lock, because no matter what
610 // the result of the above CAS, some thread must have succeeded in
611 // removing the bias bit from the object's header.
612 if (counters != NULL) {
613 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg,
614 rscratch1, rscratch2);
615 }
616 bind(nope);
617 }
618
619 bind(cas_label);
620
621 return null_check_offset;
622 }
623
624 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
625 assert(UseBiasedLocking, "why call this otherwise?");
626
627 // Check for biased locking unlock case, which is a no-op
628 // Note: we do not have to check the thread ID for two reasons.
629 // First, the interpreter checks for IllegalMonitorStateException at
630 // a higher level. Second, if the bias was revoked while we held the
631 // lock, the object could not be rebiased toward another thread, so
632 // the bias bit would be clear.
633 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
634 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
635 cmp(temp_reg, markOopDesc::biased_lock_pattern);
636 br(Assembler::EQ, done);
637 }
638
639 static void pass_arg0(MacroAssembler* masm, Register arg) {
640 if (c_rarg0 != arg ) {
641 masm->mov(c_rarg0, arg);
642 }
643 }
644
645 static void pass_arg1(MacroAssembler* masm, Register arg) {
646 if (c_rarg1 != arg ) {
647 masm->mov(c_rarg1, arg);
648 }
649 }
650
651 static void pass_arg2(MacroAssembler* masm, Register arg) {
652 if (c_rarg2 != arg ) {
653 masm->mov(c_rarg2, arg);
654 }
655 }
656
657 static void pass_arg3(MacroAssembler* masm, Register arg) {
658 if (c_rarg3 != arg ) {
659 masm->mov(c_rarg3, arg);
660 }
661 }
662
663 void MacroAssembler::call_VM_base(Register oop_result,
664 Register java_thread,
665 Register last_java_sp,
666 address entry_point,
667 int number_of_arguments,
668 bool check_exceptions) {
669 // determine java_thread register
670 if (!java_thread->is_valid()) {
671 java_thread = rthread;
672 }
673
674 // determine last_java_sp register
675 if (!last_java_sp->is_valid()) {
676 last_java_sp = esp;
677 }
678
679 // debugging support
680 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
681 assert(java_thread == rthread, "unexpected register");
682 #ifdef ASSERT
683 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
684 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
685 #endif // ASSERT
686
687 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
688 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
689
690 // push java thread (becomes first argument of C function)
691
692 mov(c_rarg0, java_thread);
693
694 // set last Java frame before call
695 assert(last_java_sp != rfp, "can't use rfp");
696
697 Label l;
698 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
699
700 // do the call, remove parameters
701 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
702
703 // reset last Java frame
704 // Only interpreter should have to clear fp
705 reset_last_Java_frame(true);
706
707 // C++ interp handles this in the interpreter
708 check_and_handle_popframe(java_thread);
709 check_and_handle_earlyret(java_thread);
710
711 if (check_exceptions) {
712 // check for pending exceptions (java_thread is set upon return)
713 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
714 Label ok;
715 cbz(rscratch1, ok);
716 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
717 br(rscratch1);
718 bind(ok);
719 }
720
721 // get oop result if there is one and reset the value in the thread
722 if (oop_result->is_valid()) {
723 get_vm_result(oop_result, java_thread);
724 }
725 }
726
727 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
728 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
729 }
730
731 // Maybe emit a call via a trampoline. If the code cache is small
732 // trampolines won't be emitted.
733
734 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) {
735 assert(JavaThread::current()->is_Compiler_thread(), "just checking");
736 assert(entry.rspec().type() == relocInfo::runtime_call_type
737 || entry.rspec().type() == relocInfo::opt_virtual_call_type
738 || entry.rspec().type() == relocInfo::static_call_type
739 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
740
741 unsigned int start_offset = offset();
742 if (far_branches() && !Compile::current()->in_scratch_emit_size()) {
743 address stub = emit_trampoline_stub(start_offset, entry.target());
744 if (stub == NULL) {
745 return NULL; // CodeCache is full
746 }
747 }
748
749 if (cbuf) cbuf->set_insts_mark();
750 relocate(entry.rspec());
751 if (!far_branches()) {
752 bl(entry.target());
753 } else {
754 bl(pc());
755 }
756 // just need to return a non-null address
757 return pc();
758 }
759
760
761 // Emit a trampoline stub for a call to a target which is too far away.
762 //
763 // code sequences:
764 //
765 // call-site:
766 // branch-and-link to <destination> or <trampoline stub>
767 //
768 // Related trampoline stub for this call site in the stub section:
769 // load the call target from the constant pool
770 // branch (LR still points to the call site above)
771
772 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
773 address dest) {
774 address stub = start_a_stub(Compile::MAX_stubs_size/2);
775 if (stub == NULL) {
776 return NULL; // CodeBuffer::expand failed
777 }
778
779 // Create a trampoline stub relocation which relates this trampoline stub
780 // with the call instruction at insts_call_instruction_offset in the
781 // instructions code-section.
782 align(wordSize);
783 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
784 + insts_call_instruction_offset));
785 const int stub_start_offset = offset();
786
787 // Now, create the trampoline stub's code:
788 // - load the call
789 // - call
790 Label target;
791 ldr(rscratch1, target);
792 br(rscratch1);
793 bind(target);
794 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
795 "should be");
796 emit_int64((int64_t)dest);
797
798 const address stub_start_addr = addr_at(stub_start_offset);
799
800 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
801
802 end_a_stub();
803 return stub_start_addr;
804 }
805
806 address MacroAssembler::ic_call(address entry, jint method_index) {
807 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
808 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
809 // unsigned long offset;
810 // ldr_constant(rscratch2, const_ptr);
811 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
812 return trampoline_call(Address(entry, rh));
813 }
814
815 // Implementation of call_VM versions
816
817 void MacroAssembler::call_VM(Register oop_result,
818 address entry_point,
819 bool check_exceptions) {
820 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
821 }
822
823 void MacroAssembler::call_VM(Register oop_result,
824 address entry_point,
825 Register arg_1,
826 bool check_exceptions) {
827 pass_arg1(this, arg_1);
828 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
829 }
830
831 void MacroAssembler::call_VM(Register oop_result,
832 address entry_point,
833 Register arg_1,
834 Register arg_2,
835 bool check_exceptions) {
836 assert(arg_1 != c_rarg2, "smashed arg");
837 pass_arg2(this, arg_2);
838 pass_arg1(this, arg_1);
839 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
840 }
841
842 void MacroAssembler::call_VM(Register oop_result,
843 address entry_point,
844 Register arg_1,
845 Register arg_2,
846 Register arg_3,
847 bool check_exceptions) {
848 assert(arg_1 != c_rarg3, "smashed arg");
849 assert(arg_2 != c_rarg3, "smashed arg");
850 pass_arg3(this, arg_3);
851
852 assert(arg_1 != c_rarg2, "smashed arg");
853 pass_arg2(this, arg_2);
854
855 pass_arg1(this, arg_1);
856 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
857 }
858
859 void MacroAssembler::call_VM(Register oop_result,
860 Register last_java_sp,
861 address entry_point,
862 int number_of_arguments,
863 bool check_exceptions) {
864 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
865 }
866
867 void MacroAssembler::call_VM(Register oop_result,
868 Register last_java_sp,
869 address entry_point,
870 Register arg_1,
871 bool check_exceptions) {
872 pass_arg1(this, arg_1);
873 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
874 }
875
876 void MacroAssembler::call_VM(Register oop_result,
877 Register last_java_sp,
878 address entry_point,
879 Register arg_1,
880 Register arg_2,
881 bool check_exceptions) {
882
883 assert(arg_1 != c_rarg2, "smashed arg");
884 pass_arg2(this, arg_2);
885 pass_arg1(this, arg_1);
886 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
887 }
888
889 void MacroAssembler::call_VM(Register oop_result,
890 Register last_java_sp,
891 address entry_point,
892 Register arg_1,
893 Register arg_2,
894 Register arg_3,
895 bool check_exceptions) {
896 assert(arg_1 != c_rarg3, "smashed arg");
897 assert(arg_2 != c_rarg3, "smashed arg");
898 pass_arg3(this, arg_3);
899 assert(arg_1 != c_rarg2, "smashed arg");
900 pass_arg2(this, arg_2);
901 pass_arg1(this, arg_1);
902 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
903 }
904
905
906 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
907 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
908 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
909 verify_oop(oop_result, "broken oop in call_VM_base");
910 }
911
912 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
913 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
914 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
915 }
916
917 void MacroAssembler::align(int modulus) {
918 while (offset() % modulus != 0) nop();
919 }
920
921 // these are no-ops overridden by InterpreterMacroAssembler
922
923 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
924
925 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
926
927
928 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
929 Register tmp,
930 int offset) {
931 intptr_t value = *delayed_value_addr;
932 if (value != 0)
933 return RegisterOrConstant(value + offset);
934
935 // load indirectly to solve generation ordering problem
936 ldr(tmp, ExternalAddress((address) delayed_value_addr));
937
938 if (offset != 0)
939 add(tmp, tmp, offset);
940
941 return RegisterOrConstant(tmp);
942 }
943
944
945 void MacroAssembler:: notify(int type) {
946 if (type == bytecode_start) {
947 // set_last_Java_frame(esp, rfp, (address)NULL);
948 Assembler:: notify(type);
949 // reset_last_Java_frame(true);
950 }
951 else
952 Assembler:: notify(type);
953 }
954
955 // Look up the method for a megamorphic invokeinterface call.
956 // The target method is determined by <intf_klass, itable_index>.
957 // The receiver klass is in recv_klass.
958 // On success, the result will be in method_result, and execution falls through.
959 // On failure, execution transfers to the given label.
960 void MacroAssembler::lookup_interface_method(Register recv_klass,
961 Register intf_klass,
962 RegisterOrConstant itable_index,
963 Register method_result,
964 Register scan_temp,
965 Label& L_no_such_interface,
966 bool return_method) {
967 assert_different_registers(recv_klass, intf_klass, scan_temp);
968 assert_different_registers(method_result, intf_klass, scan_temp);
969 assert(recv_klass != method_result || !return_method,
970 "recv_klass can be destroyed when method isn't needed");
971 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
972 "caller must use same register for non-constant itable index as for method");
973
974 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
975 int vtable_base = in_bytes(Klass::vtable_start_offset());
976 int itentry_off = itableMethodEntry::method_offset_in_bytes();
977 int scan_step = itableOffsetEntry::size() * wordSize;
978 int vte_size = vtableEntry::size_in_bytes();
979 assert(vte_size == wordSize, "else adjust times_vte_scale");
980
981 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
982
983 // %%% Could store the aligned, prescaled offset in the klassoop.
984 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
985 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
986 add(scan_temp, scan_temp, vtable_base);
987
988 if (return_method) {
989 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
990 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
991 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
992 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
993 if (itentry_off)
994 add(recv_klass, recv_klass, itentry_off);
995 }
996
997 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
998 // if (scan->interface() == intf) {
999 // result = (klass + scan->offset() + itable_index);
1000 // }
1001 // }
1002 Label search, found_method;
1003
1004 for (int peel = 1; peel >= 0; peel--) {
1005 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
1006 cmp(intf_klass, method_result);
1007
1008 if (peel) {
1009 br(Assembler::EQ, found_method);
1010 } else {
1011 br(Assembler::NE, search);
1012 // (invert the test to fall through to found_method...)
1013 }
1014
1015 if (!peel) break;
1016
1017 bind(search);
1018
1019 // Check that the previous entry is non-null. A null entry means that
1020 // the receiver class doesn't implement the interface, and wasn't the
1021 // same as when the caller was compiled.
1022 cbz(method_result, L_no_such_interface);
1023 add(scan_temp, scan_temp, scan_step);
1024 }
1025
1026 bind(found_method);
1027
1028 // Got a hit.
1029 if (return_method) {
1030 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
1031 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1032 }
1033 }
1034
1035 // virtual method calling
1036 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1037 RegisterOrConstant vtable_index,
1038 Register method_result) {
1039 const int base = in_bytes(Klass::vtable_start_offset());
1040 assert(vtableEntry::size() * wordSize == 8,
1041 "adjust the scaling in the code below");
1042 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes();
1043
1044 if (vtable_index.is_register()) {
1045 lea(method_result, Address(recv_klass,
1046 vtable_index.as_register(),
1047 Address::lsl(LogBytesPerWord)));
1048 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1049 } else {
1050 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1051 ldr(method_result,
1052 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1053 }
1054 }
1055
1056 void MacroAssembler::check_klass_subtype(Register sub_klass,
1057 Register super_klass,
1058 Register temp_reg,
1059 Label& L_success) {
1060 Label L_failure;
1061 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
1062 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
1063 bind(L_failure);
1064 }
1065
1066
1067 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1068 Register super_klass,
1069 Register temp_reg,
1070 Label* L_success,
1071 Label* L_failure,
1072 Label* L_slow_path,
1073 RegisterOrConstant super_check_offset) {
1074 assert_different_registers(sub_klass, super_klass, temp_reg);
1075 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1076 if (super_check_offset.is_register()) {
1077 assert_different_registers(sub_klass, super_klass,
1078 super_check_offset.as_register());
1079 } else if (must_load_sco) {
1080 assert(temp_reg != noreg, "supply either a temp or a register offset");
1081 }
1082
1083 Label L_fallthrough;
1084 int label_nulls = 0;
1085 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1086 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1087 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1088 assert(label_nulls <= 1, "at most one NULL in the batch");
1089
1090 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1091 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1092 Address super_check_offset_addr(super_klass, sco_offset);
1093
1094 // Hacked jmp, which may only be used just before L_fallthrough.
1095 #define final_jmp(label) \
1096 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1097 else b(label) /*omit semi*/
1098
1099 // If the pointers are equal, we are done (e.g., String[] elements).
1100 // This self-check enables sharing of secondary supertype arrays among
1101 // non-primary types such as array-of-interface. Otherwise, each such
1102 // type would need its own customized SSA.
1103 // We move this check to the front of the fast path because many
1104 // type checks are in fact trivially successful in this manner,
1105 // so we get a nicely predicted branch right at the start of the check.
1106 cmp(sub_klass, super_klass);
1107 br(Assembler::EQ, *L_success);
1108
1109 // Check the supertype display:
1110 if (must_load_sco) {
1111 ldrw(temp_reg, super_check_offset_addr);
1112 super_check_offset = RegisterOrConstant(temp_reg);
1113 }
1114 Address super_check_addr(sub_klass, super_check_offset);
1115 ldr(rscratch1, super_check_addr);
1116 cmp(super_klass, rscratch1); // load displayed supertype
1117
1118 // This check has worked decisively for primary supers.
1119 // Secondary supers are sought in the super_cache ('super_cache_addr').
1120 // (Secondary supers are interfaces and very deeply nested subtypes.)
1121 // This works in the same check above because of a tricky aliasing
1122 // between the super_cache and the primary super display elements.
1123 // (The 'super_check_addr' can address either, as the case requires.)
1124 // Note that the cache is updated below if it does not help us find
1125 // what we need immediately.
1126 // So if it was a primary super, we can just fail immediately.
1127 // Otherwise, it's the slow path for us (no success at this point).
1128
1129 if (super_check_offset.is_register()) {
1130 br(Assembler::EQ, *L_success);
1131 cmp(super_check_offset.as_register(), sc_offset);
1132 if (L_failure == &L_fallthrough) {
1133 br(Assembler::EQ, *L_slow_path);
1134 } else {
1135 br(Assembler::NE, *L_failure);
1136 final_jmp(*L_slow_path);
1137 }
1138 } else if (super_check_offset.as_constant() == sc_offset) {
1139 // Need a slow path; fast failure is impossible.
1140 if (L_slow_path == &L_fallthrough) {
1141 br(Assembler::EQ, *L_success);
1142 } else {
1143 br(Assembler::NE, *L_slow_path);
1144 final_jmp(*L_success);
1145 }
1146 } else {
1147 // No slow path; it's a fast decision.
1148 if (L_failure == &L_fallthrough) {
1149 br(Assembler::EQ, *L_success);
1150 } else {
1151 br(Assembler::NE, *L_failure);
1152 final_jmp(*L_success);
1153 }
1154 }
1155
1156 bind(L_fallthrough);
1157
1158 #undef final_jmp
1159 }
1160
1161 // These two are taken from x86, but they look generally useful
1162
1163 // scans count pointer sized words at [addr] for occurence of value,
1164 // generic
1165 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1166 Register scratch) {
1167 Label Lloop, Lexit;
1168 cbz(count, Lexit);
1169 bind(Lloop);
1170 ldr(scratch, post(addr, wordSize));
1171 cmp(value, scratch);
1172 br(EQ, Lexit);
1173 sub(count, count, 1);
1174 cbnz(count, Lloop);
1175 bind(Lexit);
1176 }
1177
1178 // scans count 4 byte words at [addr] for occurence of value,
1179 // generic
1180 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1181 Register scratch) {
1182 Label Lloop, Lexit;
1183 cbz(count, Lexit);
1184 bind(Lloop);
1185 ldrw(scratch, post(addr, wordSize));
1186 cmpw(value, scratch);
1187 br(EQ, Lexit);
1188 sub(count, count, 1);
1189 cbnz(count, Lloop);
1190 bind(Lexit);
1191 }
1192
1193 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1194 Register super_klass,
1195 Register temp_reg,
1196 Register temp2_reg,
1197 Label* L_success,
1198 Label* L_failure,
1199 bool set_cond_codes) {
1200 assert_different_registers(sub_klass, super_klass, temp_reg);
1201 if (temp2_reg != noreg)
1202 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1203 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1204
1205 Label L_fallthrough;
1206 int label_nulls = 0;
1207 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
1208 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
1209 assert(label_nulls <= 1, "at most one NULL in the batch");
1210
1211 // a couple of useful fields in sub_klass:
1212 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1213 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1214 Address secondary_supers_addr(sub_klass, ss_offset);
1215 Address super_cache_addr( sub_klass, sc_offset);
1216
1217 BLOCK_COMMENT("check_klass_subtype_slow_path");
1218
1219 // Do a linear scan of the secondary super-klass chain.
1220 // This code is rarely used, so simplicity is a virtue here.
1221 // The repne_scan instruction uses fixed registers, which we must spill.
1222 // Don't worry too much about pre-existing connections with the input regs.
1223
1224 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1225 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1226
1227 // Get super_klass value into r0 (even if it was in r5 or r2).
1228 RegSet pushed_registers;
1229 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1230 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1231
1232 if (super_klass != r0 || UseCompressedOops) {
1233 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1234 }
1235
1236 push(pushed_registers, sp);
1237
1238 #ifndef PRODUCT
1239 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1240 Address pst_counter_addr(rscratch2);
1241 ldr(rscratch1, pst_counter_addr);
1242 add(rscratch1, rscratch1, 1);
1243 str(rscratch1, pst_counter_addr);
1244 #endif //PRODUCT
1245
1246 // We will consult the secondary-super array.
1247 ldr(r5, secondary_supers_addr);
1248 // Load the array length.
1249 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1250 // Skip to start of data.
1251 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1252
1253 cmp(sp, zr); // Clear Z flag; SP is never zero
1254 // Scan R2 words at [R5] for an occurrence of R0.
1255 // Set NZ/Z based on last compare.
1256 repne_scan(r5, r0, r2, rscratch1);
1257
1258 // Unspill the temp. registers:
1259 pop(pushed_registers, sp);
1260
1261 br(Assembler::NE, *L_failure);
1262
1263 // Success. Cache the super we found and proceed in triumph.
1264 str(super_klass, super_cache_addr);
1265
1266 if (L_success != &L_fallthrough) {
1267 b(*L_success);
1268 }
1269
1270 #undef IS_A_TEMP
1271
1272 bind(L_fallthrough);
1273 }
1274
1275
1276 void MacroAssembler::verify_oop(Register reg, const char* s) {
1277 if (!VerifyOops) return;
1278
1279 // Pass register number to verify_oop_subroutine
1280 const char* b = NULL;
1281 {
1282 ResourceMark rm;
1283 stringStream ss;
1284 ss.print("verify_oop: %s: %s", reg->name(), s);
1285 b = code_string(ss.as_string());
1286 }
1287 BLOCK_COMMENT("verify_oop {");
1288
1289 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1290 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1291
1292 mov(r0, reg);
1293 mov(rscratch1, (address)b);
1294
1295 // call indirectly to solve generation ordering problem
1296 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1297 ldr(rscratch2, Address(rscratch2));
1298 blr(rscratch2);
1299
1300 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1301 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1302
1303 BLOCK_COMMENT("} verify_oop");
1304 }
1305
1306 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1307 if (!VerifyOops) return;
1308
1309 const char* b = NULL;
1310 {
1311 ResourceMark rm;
1312 stringStream ss;
1313 ss.print("verify_oop_addr: %s", s);
1314 b = code_string(ss.as_string());
1315 }
1316 BLOCK_COMMENT("verify_oop_addr {");
1317
1318 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1319 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1320
1321 // addr may contain sp so we will have to adjust it based on the
1322 // pushes that we just did.
1323 if (addr.uses(sp)) {
1324 lea(r0, addr);
1325 ldr(r0, Address(r0, 4 * wordSize));
1326 } else {
1327 ldr(r0, addr);
1328 }
1329 mov(rscratch1, (address)b);
1330
1331 // call indirectly to solve generation ordering problem
1332 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1333 ldr(rscratch2, Address(rscratch2));
1334 blr(rscratch2);
1335
1336 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1337 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1338
1339 BLOCK_COMMENT("} verify_oop_addr");
1340 }
1341
1342 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1343 int extra_slot_offset) {
1344 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1345 int stackElementSize = Interpreter::stackElementSize;
1346 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1347 #ifdef ASSERT
1348 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1349 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1350 #endif
1351 if (arg_slot.is_constant()) {
1352 return Address(esp, arg_slot.as_constant() * stackElementSize
1353 + offset);
1354 } else {
1355 add(rscratch1, esp, arg_slot.as_register(),
1356 ext::uxtx, exact_log2(stackElementSize));
1357 return Address(rscratch1, offset);
1358 }
1359 }
1360
1361 void MacroAssembler::call_VM_leaf_base(address entry_point,
1362 int number_of_arguments,
1363 Label *retaddr) {
1364 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr);
1365 }
1366
1367 void MacroAssembler::call_VM_leaf_base1(address entry_point,
1368 int number_of_gp_arguments,
1369 int number_of_fp_arguments,
1370 ret_type type,
1371 Label *retaddr) {
1372 Label E, L;
1373
1374 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1375
1376 // We add 1 to number_of_arguments because the thread in arg0 is
1377 // not counted
1378 mov(rscratch1, entry_point);
1379 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type);
1380 if (retaddr)
1381 bind(*retaddr);
1382
1383 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1384 maybe_isb();
1385 }
1386
1387 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1388 call_VM_leaf_base(entry_point, number_of_arguments);
1389 }
1390
1391 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1392 pass_arg0(this, arg_0);
1393 call_VM_leaf_base(entry_point, 1);
1394 }
1395
1396 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1397 pass_arg0(this, arg_0);
1398 pass_arg1(this, arg_1);
1399 call_VM_leaf_base(entry_point, 2);
1400 }
1401
1402 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1403 Register arg_1, Register arg_2) {
1404 pass_arg0(this, arg_0);
1405 pass_arg1(this, arg_1);
1406 pass_arg2(this, arg_2);
1407 call_VM_leaf_base(entry_point, 3);
1408 }
1409
1410 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1411 pass_arg0(this, arg_0);
1412 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1413 }
1414
1415 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1416
1417 assert(arg_0 != c_rarg1, "smashed arg");
1418 pass_arg1(this, arg_1);
1419 pass_arg0(this, arg_0);
1420 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1421 }
1422
1423 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1424 assert(arg_0 != c_rarg2, "smashed arg");
1425 assert(arg_1 != c_rarg2, "smashed arg");
1426 pass_arg2(this, arg_2);
1427 assert(arg_0 != c_rarg1, "smashed arg");
1428 pass_arg1(this, arg_1);
1429 pass_arg0(this, arg_0);
1430 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1431 }
1432
1433 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1434 assert(arg_0 != c_rarg3, "smashed arg");
1435 assert(arg_1 != c_rarg3, "smashed arg");
1436 assert(arg_2 != c_rarg3, "smashed arg");
1437 pass_arg3(this, arg_3);
1438 assert(arg_0 != c_rarg2, "smashed arg");
1439 assert(arg_1 != c_rarg2, "smashed arg");
1440 pass_arg2(this, arg_2);
1441 assert(arg_0 != c_rarg1, "smashed arg");
1442 pass_arg1(this, arg_1);
1443 pass_arg0(this, arg_0);
1444 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1445 }
1446
1447 void MacroAssembler::null_check(Register reg, int offset) {
1448 if (needs_explicit_null_check(offset)) {
1449 // provoke OS NULL exception if reg = NULL by
1450 // accessing M[reg] w/o changing any registers
1451 // NOTE: this is plenty to provoke a segv
1452 ldr(zr, Address(reg));
1453 } else {
1454 // nothing to do, (later) access of M[reg + offset]
1455 // will provoke OS NULL exception if reg = NULL
1456 }
1457 }
1458
1459 // MacroAssembler protected routines needed to implement
1460 // public methods
1461
1462 void MacroAssembler::mov(Register r, Address dest) {
1463 code_section()->relocate(pc(), dest.rspec());
1464 u_int64_t imm64 = (u_int64_t)dest.target();
1465 movptr(r, imm64);
1466 }
1467
1468 // Move a constant pointer into r. In AArch64 mode the virtual
1469 // address space is 48 bits in size, so we only need three
1470 // instructions to create a patchable instruction sequence that can
1471 // reach anywhere.
1472 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1473 #ifndef PRODUCT
1474 {
1475 char buffer[64];
1476 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1477 block_comment(buffer);
1478 }
1479 #endif
1480 assert(imm64 < (1ul << 48), "48-bit overflow in address constant");
1481 movz(r, imm64 & 0xffff);
1482 imm64 >>= 16;
1483 movk(r, imm64 & 0xffff, 16);
1484 imm64 >>= 16;
1485 movk(r, imm64 & 0xffff, 32);
1486 }
1487
1488 // Macro to mov replicated immediate to vector register.
1489 // Vd will get the following values for different arrangements in T
1490 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh
1491 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1492 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh
1493 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1494 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1495 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1496 // T1D/T2D: invalid
1497 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
1498 assert(T != T1D && T != T2D, "invalid arrangement");
1499 if (T == T8B || T == T16B) {
1500 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)");
1501 movi(Vd, T, imm32 & 0xff, 0);
1502 return;
1503 }
1504 u_int32_t nimm32 = ~imm32;
1505 if (T == T4H || T == T8H) {
1506 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)");
1507 imm32 &= 0xffff;
1508 nimm32 &= 0xffff;
1509 }
1510 u_int32_t x = imm32;
1511 int movi_cnt = 0;
1512 int movn_cnt = 0;
1513 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
1514 x = nimm32;
1515 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
1516 if (movn_cnt < movi_cnt) imm32 = nimm32;
1517 unsigned lsl = 0;
1518 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1519 if (movn_cnt < movi_cnt)
1520 mvni(Vd, T, imm32 & 0xff, lsl);
1521 else
1522 movi(Vd, T, imm32 & 0xff, lsl);
1523 imm32 >>= 8; lsl += 8;
1524 while (imm32) {
1525 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
1526 if (movn_cnt < movi_cnt)
1527 bici(Vd, T, imm32 & 0xff, lsl);
1528 else
1529 orri(Vd, T, imm32 & 0xff, lsl);
1530 lsl += 8; imm32 >>= 8;
1531 }
1532 }
1533
1534 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64)
1535 {
1536 #ifndef PRODUCT
1537 {
1538 char buffer[64];
1539 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64);
1540 block_comment(buffer);
1541 }
1542 #endif
1543 if (operand_valid_for_logical_immediate(false, imm64)) {
1544 orr(dst, zr, imm64);
1545 } else {
1546 // we can use a combination of MOVZ or MOVN with
1547 // MOVK to build up the constant
1548 u_int64_t imm_h[4];
1549 int zero_count = 0;
1550 int neg_count = 0;
1551 int i;
1552 for (i = 0; i < 4; i++) {
1553 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1554 if (imm_h[i] == 0) {
1555 zero_count++;
1556 } else if (imm_h[i] == 0xffffL) {
1557 neg_count++;
1558 }
1559 }
1560 if (zero_count == 4) {
1561 // one MOVZ will do
1562 movz(dst, 0);
1563 } else if (neg_count == 4) {
1564 // one MOVN will do
1565 movn(dst, 0);
1566 } else if (zero_count == 3) {
1567 for (i = 0; i < 4; i++) {
1568 if (imm_h[i] != 0L) {
1569 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1570 break;
1571 }
1572 }
1573 } else if (neg_count == 3) {
1574 // one MOVN will do
1575 for (int i = 0; i < 4; i++) {
1576 if (imm_h[i] != 0xffffL) {
1577 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1578 break;
1579 }
1580 }
1581 } else if (zero_count == 2) {
1582 // one MOVZ and one MOVK will do
1583 for (i = 0; i < 3; i++) {
1584 if (imm_h[i] != 0L) {
1585 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1586 i++;
1587 break;
1588 }
1589 }
1590 for (;i < 4; i++) {
1591 if (imm_h[i] != 0L) {
1592 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1593 }
1594 }
1595 } else if (neg_count == 2) {
1596 // one MOVN and one MOVK will do
1597 for (i = 0; i < 4; i++) {
1598 if (imm_h[i] != 0xffffL) {
1599 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1600 i++;
1601 break;
1602 }
1603 }
1604 for (;i < 4; i++) {
1605 if (imm_h[i] != 0xffffL) {
1606 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1607 }
1608 }
1609 } else if (zero_count == 1) {
1610 // one MOVZ and two MOVKs will do
1611 for (i = 0; i < 4; i++) {
1612 if (imm_h[i] != 0L) {
1613 movz(dst, (u_int32_t)imm_h[i], (i << 4));
1614 i++;
1615 break;
1616 }
1617 }
1618 for (;i < 4; i++) {
1619 if (imm_h[i] != 0x0L) {
1620 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1621 }
1622 }
1623 } else if (neg_count == 1) {
1624 // one MOVN and two MOVKs will do
1625 for (i = 0; i < 4; i++) {
1626 if (imm_h[i] != 0xffffL) {
1627 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4));
1628 i++;
1629 break;
1630 }
1631 }
1632 for (;i < 4; i++) {
1633 if (imm_h[i] != 0xffffL) {
1634 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1635 }
1636 }
1637 } else {
1638 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1639 movz(dst, (u_int32_t)imm_h[0], 0);
1640 for (i = 1; i < 4; i++) {
1641 movk(dst, (u_int32_t)imm_h[i], (i << 4));
1642 }
1643 }
1644 }
1645 }
1646
1647 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32)
1648 {
1649 #ifndef PRODUCT
1650 {
1651 char buffer[64];
1652 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32);
1653 block_comment(buffer);
1654 }
1655 #endif
1656 if (operand_valid_for_logical_immediate(true, imm32)) {
1657 orrw(dst, zr, imm32);
1658 } else {
1659 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1660 // constant
1661 u_int32_t imm_h[2];
1662 imm_h[0] = imm32 & 0xffff;
1663 imm_h[1] = ((imm32 >> 16) & 0xffff);
1664 if (imm_h[0] == 0) {
1665 movzw(dst, imm_h[1], 16);
1666 } else if (imm_h[0] == 0xffff) {
1667 movnw(dst, imm_h[1] ^ 0xffff, 16);
1668 } else if (imm_h[1] == 0) {
1669 movzw(dst, imm_h[0], 0);
1670 } else if (imm_h[1] == 0xffff) {
1671 movnw(dst, imm_h[0] ^ 0xffff, 0);
1672 } else {
1673 // use a MOVZ and MOVK (makes it easier to debug)
1674 movzw(dst, imm_h[0], 0);
1675 movkw(dst, imm_h[1], 16);
1676 }
1677 }
1678 }
1679
1680 // Form an address from base + offset in Rd. Rd may or may
1681 // not actually be used: you must use the Address that is returned.
1682 // It is up to you to ensure that the shift provided matches the size
1683 // of your data.
1684 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
1685 if (Address::offset_ok_for_immed(byte_offset, shift))
1686 // It fits; no need for any heroics
1687 return Address(base, byte_offset);
1688
1689 // Don't do anything clever with negative or misaligned offsets
1690 unsigned mask = (1 << shift) - 1;
1691 if (byte_offset < 0 || byte_offset & mask) {
1692 mov(Rd, byte_offset);
1693 add(Rd, base, Rd);
1694 return Address(Rd);
1695 }
1696
1697 // See if we can do this with two 12-bit offsets
1698 {
1699 unsigned long word_offset = byte_offset >> shift;
1700 unsigned long masked_offset = word_offset & 0xfff000;
1701 if (Address::offset_ok_for_immed(word_offset - masked_offset)
1702 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1703 add(Rd, base, masked_offset << shift);
1704 word_offset -= masked_offset;
1705 return Address(Rd, word_offset << shift);
1706 }
1707 }
1708
1709 // Do it the hard way
1710 mov(Rd, byte_offset);
1711 add(Rd, base, Rd);
1712 return Address(Rd);
1713 }
1714
1715 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
1716 if (UseLSE) {
1717 mov(tmp, 1);
1718 ldadd(Assembler::word, tmp, zr, counter_addr);
1719 return;
1720 }
1721 Label retry_load;
1722 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
1723 prfm(Address(counter_addr), PSTL1STRM);
1724 bind(retry_load);
1725 // flush and load exclusive from the memory location
1726 ldxrw(tmp, counter_addr);
1727 addw(tmp, tmp, 1);
1728 // if we store+flush with no intervening write tmp wil be zero
1729 stxrw(tmp2, tmp, counter_addr);
1730 cbnzw(tmp2, retry_load);
1731 }
1732
1733
1734 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
1735 bool want_remainder, Register scratch)
1736 {
1737 // Full implementation of Java idiv and irem. The function
1738 // returns the (pc) offset of the div instruction - may be needed
1739 // for implicit exceptions.
1740 //
1741 // constraint : ra/rb =/= scratch
1742 // normal case
1743 //
1744 // input : ra: dividend
1745 // rb: divisor
1746 //
1747 // result: either
1748 // quotient (= ra idiv rb)
1749 // remainder (= ra irem rb)
1750
1751 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1752
1753 int idivl_offset = offset();
1754 if (! want_remainder) {
1755 sdivw(result, ra, rb);
1756 } else {
1757 sdivw(scratch, ra, rb);
1758 Assembler::msubw(result, scratch, rb, ra);
1759 }
1760
1761 return idivl_offset;
1762 }
1763
1764 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
1765 bool want_remainder, Register scratch)
1766 {
1767 // Full implementation of Java ldiv and lrem. The function
1768 // returns the (pc) offset of the div instruction - may be needed
1769 // for implicit exceptions.
1770 //
1771 // constraint : ra/rb =/= scratch
1772 // normal case
1773 //
1774 // input : ra: dividend
1775 // rb: divisor
1776 //
1777 // result: either
1778 // quotient (= ra idiv rb)
1779 // remainder (= ra irem rb)
1780
1781 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
1782
1783 int idivq_offset = offset();
1784 if (! want_remainder) {
1785 sdiv(result, ra, rb);
1786 } else {
1787 sdiv(scratch, ra, rb);
1788 Assembler::msub(result, scratch, rb, ra);
1789 }
1790
1791 return idivq_offset;
1792 }
1793
1794 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
1795 address prev = pc() - NativeMembar::instruction_size;
1796 address last = code()->last_insn();
1797 if (last != NULL && nativeInstruction_at(last)->is_Membar() && prev == last) {
1798 NativeMembar *bar = NativeMembar_at(prev);
1799 // We are merging two memory barrier instructions. On AArch64 we
1800 // can do this simply by ORing them together.
1801 bar->set_kind(bar->get_kind() | order_constraint);
1802 BLOCK_COMMENT("merged membar");
1803 } else {
1804 code()->set_last_insn(pc());
1805 dmb(Assembler::barrier(order_constraint));
1806 }
1807 }
1808
1809 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
1810 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
1811 merge_ldst(rt, adr, size_in_bytes, is_store);
1812 code()->clear_last_insn();
1813 return true;
1814 } else {
1815 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
1816 const unsigned mask = size_in_bytes - 1;
1817 if (adr.getMode() == Address::base_plus_offset &&
1818 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
1819 code()->set_last_insn(pc());
1820 }
1821 return false;
1822 }
1823 }
1824
1825 void MacroAssembler::ldr(Register Rx, const Address &adr) {
1826 // We always try to merge two adjacent loads into one ldp.
1827 if (!try_merge_ldst(Rx, adr, 8, false)) {
1828 Assembler::ldr(Rx, adr);
1829 }
1830 }
1831
1832 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
1833 // We always try to merge two adjacent loads into one ldp.
1834 if (!try_merge_ldst(Rw, adr, 4, false)) {
1835 Assembler::ldrw(Rw, adr);
1836 }
1837 }
1838
1839 void MacroAssembler::str(Register Rx, const Address &adr) {
1840 // We always try to merge two adjacent stores into one stp.
1841 if (!try_merge_ldst(Rx, adr, 8, true)) {
1842 Assembler::str(Rx, adr);
1843 }
1844 }
1845
1846 void MacroAssembler::strw(Register Rw, const Address &adr) {
1847 // We always try to merge two adjacent stores into one stp.
1848 if (!try_merge_ldst(Rw, adr, 4, true)) {
1849 Assembler::strw(Rw, adr);
1850 }
1851 }
1852
1853 // MacroAssembler routines found actually to be needed
1854
1855 void MacroAssembler::push(Register src)
1856 {
1857 str(src, Address(pre(esp, -1 * wordSize)));
1858 }
1859
1860 void MacroAssembler::pop(Register dst)
1861 {
1862 ldr(dst, Address(post(esp, 1 * wordSize)));
1863 }
1864
1865 // Note: load_unsigned_short used to be called load_unsigned_word.
1866 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1867 int off = offset();
1868 ldrh(dst, src);
1869 return off;
1870 }
1871
1872 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1873 int off = offset();
1874 ldrb(dst, src);
1875 return off;
1876 }
1877
1878 int MacroAssembler::load_signed_short(Register dst, Address src) {
1879 int off = offset();
1880 ldrsh(dst, src);
1881 return off;
1882 }
1883
1884 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1885 int off = offset();
1886 ldrsb(dst, src);
1887 return off;
1888 }
1889
1890 int MacroAssembler::load_signed_short32(Register dst, Address src) {
1891 int off = offset();
1892 ldrshw(dst, src);
1893 return off;
1894 }
1895
1896 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
1897 int off = offset();
1898 ldrsbw(dst, src);
1899 return off;
1900 }
1901
1902 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1903 switch (size_in_bytes) {
1904 case 8: ldr(dst, src); break;
1905 case 4: ldrw(dst, src); break;
1906 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1907 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1908 default: ShouldNotReachHere();
1909 }
1910 }
1911
1912 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1913 switch (size_in_bytes) {
1914 case 8: str(src, dst); break;
1915 case 4: strw(src, dst); break;
1916 case 2: strh(src, dst); break;
1917 case 1: strb(src, dst); break;
1918 default: ShouldNotReachHere();
1919 }
1920 }
1921
1922 void MacroAssembler::decrementw(Register reg, int value)
1923 {
1924 if (value < 0) { incrementw(reg, -value); return; }
1925 if (value == 0) { return; }
1926 if (value < (1 << 12)) { subw(reg, reg, value); return; }
1927 /* else */ {
1928 guarantee(reg != rscratch2, "invalid dst for register decrement");
1929 movw(rscratch2, (unsigned)value);
1930 subw(reg, reg, rscratch2);
1931 }
1932 }
1933
1934 void MacroAssembler::decrement(Register reg, int value)
1935 {
1936 if (value < 0) { increment(reg, -value); return; }
1937 if (value == 0) { return; }
1938 if (value < (1 << 12)) { sub(reg, reg, value); return; }
1939 /* else */ {
1940 assert(reg != rscratch2, "invalid dst for register decrement");
1941 mov(rscratch2, (unsigned long)value);
1942 sub(reg, reg, rscratch2);
1943 }
1944 }
1945
1946 void MacroAssembler::decrementw(Address dst, int value)
1947 {
1948 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
1949 ldrw(rscratch1, dst);
1950 decrementw(rscratch1, value);
1951 strw(rscratch1, dst);
1952 }
1953
1954 void MacroAssembler::decrement(Address dst, int value)
1955 {
1956 assert(!dst.uses(rscratch1), "invalid address for decrement");
1957 ldr(rscratch1, dst);
1958 decrement(rscratch1, value);
1959 str(rscratch1, dst);
1960 }
1961
1962 void MacroAssembler::incrementw(Register reg, int value)
1963 {
1964 if (value < 0) { decrementw(reg, -value); return; }
1965 if (value == 0) { return; }
1966 if (value < (1 << 12)) { addw(reg, reg, value); return; }
1967 /* else */ {
1968 assert(reg != rscratch2, "invalid dst for register increment");
1969 movw(rscratch2, (unsigned)value);
1970 addw(reg, reg, rscratch2);
1971 }
1972 }
1973
1974 void MacroAssembler::increment(Register reg, int value)
1975 {
1976 if (value < 0) { decrement(reg, -value); return; }
1977 if (value == 0) { return; }
1978 if (value < (1 << 12)) { add(reg, reg, value); return; }
1979 /* else */ {
1980 assert(reg != rscratch2, "invalid dst for register increment");
1981 movw(rscratch2, (unsigned)value);
1982 add(reg, reg, rscratch2);
1983 }
1984 }
1985
1986 void MacroAssembler::incrementw(Address dst, int value)
1987 {
1988 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1989 ldrw(rscratch1, dst);
1990 incrementw(rscratch1, value);
1991 strw(rscratch1, dst);
1992 }
1993
1994 void MacroAssembler::increment(Address dst, int value)
1995 {
1996 assert(!dst.uses(rscratch1), "invalid dst for address increment");
1997 ldr(rscratch1, dst);
1998 increment(rscratch1, value);
1999 str(rscratch1, dst);
2000 }
2001
2002
2003 void MacroAssembler::pusha() {
2004 push(0x7fffffff, sp);
2005 }
2006
2007 void MacroAssembler::popa() {
2008 pop(0x7fffffff, sp);
2009 }
2010
2011 // Push lots of registers in the bit set supplied. Don't push sp.
2012 // Return the number of words pushed
2013 int MacroAssembler::push(unsigned int bitset, Register stack) {
2014 int words_pushed = 0;
2015
2016 // Scan bitset to accumulate register pairs
2017 unsigned char regs[32];
2018 int count = 0;
2019 for (int reg = 0; reg <= 30; reg++) {
2020 if (1 & bitset)
2021 regs[count++] = reg;
2022 bitset >>= 1;
2023 }
2024 regs[count++] = zr->encoding_nocheck();
2025 count &= ~1; // Only push an even nuber of regs
2026
2027 if (count) {
2028 stp(as_Register(regs[0]), as_Register(regs[1]),
2029 Address(pre(stack, -count * wordSize)));
2030 words_pushed += 2;
2031 }
2032 for (int i = 2; i < count; i += 2) {
2033 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2034 Address(stack, i * wordSize));
2035 words_pushed += 2;
2036 }
2037
2038 assert(words_pushed == count, "oops, pushed != count");
2039
2040 return count;
2041 }
2042
2043 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2044 int words_pushed = 0;
2045
2046 // Scan bitset to accumulate register pairs
2047 unsigned char regs[32];
2048 int count = 0;
2049 for (int reg = 0; reg <= 30; reg++) {
2050 if (1 & bitset)
2051 regs[count++] = reg;
2052 bitset >>= 1;
2053 }
2054 regs[count++] = zr->encoding_nocheck();
2055 count &= ~1;
2056
2057 for (int i = 2; i < count; i += 2) {
2058 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2059 Address(stack, i * wordSize));
2060 words_pushed += 2;
2061 }
2062 if (count) {
2063 ldp(as_Register(regs[0]), as_Register(regs[1]),
2064 Address(post(stack, count * wordSize)));
2065 words_pushed += 2;
2066 }
2067
2068 assert(words_pushed == count, "oops, pushed != count");
2069
2070 return count;
2071 }
2072 #ifdef ASSERT
2073 void MacroAssembler::verify_heapbase(const char* msg) {
2074 #if 0
2075 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
2076 assert (Universe::heap() != NULL, "java heap should be initialized");
2077 if (CheckCompressedOops) {
2078 Label ok;
2079 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
2080 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2081 br(Assembler::EQ, ok);
2082 stop(msg);
2083 bind(ok);
2084 pop(1 << rscratch1->encoding(), sp);
2085 }
2086 #endif
2087 }
2088 #endif
2089
2090 void MacroAssembler::resolve_jobject(Register value, Register thread, Register tmp) {
2091 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
2092 Label done, not_weak;
2093 cbz(value, done); // Use NULL as-is.
2094
2095 STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u);
2096 tbz(r0, 0, not_weak); // Test for jweak tag.
2097
2098 // Resolve jweak.
2099 bs->load_at(this, IN_ROOT | ON_PHANTOM_OOP_REF, T_OBJECT,
2100 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
2101 verify_oop(value);
2102 b(done);
2103
2104 bind(not_weak);
2105 // Resolve (untagged) jobject.
2106 bs->load_at(this, IN_ROOT | IN_CONCURRENT_ROOT, T_OBJECT,
2107 value, Address(value, 0), tmp, thread);
2108 verify_oop(value);
2109 bind(done);
2110 }
2111
2112 void MacroAssembler::stop(const char* msg) {
2113 address ip = pc();
2114 pusha();
2115 mov(c_rarg0, (address)msg);
2116 mov(c_rarg1, (address)ip);
2117 mov(c_rarg2, sp);
2118 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
2119 // call(c_rarg3);
2120 blrt(c_rarg3, 3, 0, 1);
2121 hlt(0);
2122 }
2123
2124 void MacroAssembler::unimplemented(const char* what) {
2125 const char* buf = NULL;
2126 {
2127 ResourceMark rm;
2128 stringStream ss;
2129 ss.print("unimplemented: %s", what);
2130 buf = code_string(ss.as_string());
2131 }
2132 stop(buf);
2133 }
2134
2135 // If a constant does not fit in an immediate field, generate some
2136 // number of MOV instructions and then perform the operation.
2137 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
2138 add_sub_imm_insn insn1,
2139 add_sub_reg_insn insn2) {
2140 assert(Rd != zr, "Rd = zr and not setting flags?");
2141 if (operand_valid_for_add_sub_immediate((int)imm)) {
2142 (this->*insn1)(Rd, Rn, imm);
2143 } else {
2144 if (uabs(imm) < (1 << 24)) {
2145 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
2146 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
2147 } else {
2148 assert_different_registers(Rd, Rn);
2149 mov(Rd, (uint64_t)imm);
2150 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2151 }
2152 }
2153 }
2154
2155 // Seperate vsn which sets the flags. Optimisations are more restricted
2156 // because we must set the flags correctly.
2157 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
2158 add_sub_imm_insn insn1,
2159 add_sub_reg_insn insn2) {
2160 if (operand_valid_for_add_sub_immediate((int)imm)) {
2161 (this->*insn1)(Rd, Rn, imm);
2162 } else {
2163 assert_different_registers(Rd, Rn);
2164 assert(Rd != zr, "overflow in immediate operand");
2165 mov(Rd, (uint64_t)imm);
2166 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2167 }
2168 }
2169
2170
2171 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2172 if (increment.is_register()) {
2173 add(Rd, Rn, increment.as_register());
2174 } else {
2175 add(Rd, Rn, increment.as_constant());
2176 }
2177 }
2178
2179 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2180 if (increment.is_register()) {
2181 addw(Rd, Rn, increment.as_register());
2182 } else {
2183 addw(Rd, Rn, increment.as_constant());
2184 }
2185 }
2186
2187 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2188 if (decrement.is_register()) {
2189 sub(Rd, Rn, decrement.as_register());
2190 } else {
2191 sub(Rd, Rn, decrement.as_constant());
2192 }
2193 }
2194
2195 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2196 if (decrement.is_register()) {
2197 subw(Rd, Rn, decrement.as_register());
2198 } else {
2199 subw(Rd, Rn, decrement.as_constant());
2200 }
2201 }
2202
2203 void MacroAssembler::reinit_heapbase()
2204 {
2205 if (UseCompressedOops) {
2206 if (Universe::is_fully_initialized()) {
2207 mov(rheapbase, Universe::narrow_ptrs_base());
2208 } else {
2209 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
2210 ldr(rheapbase, Address(rheapbase));
2211 }
2212 }
2213 }
2214
2215 // this simulates the behaviour of the x86 cmpxchg instruction using a
2216 // load linked/store conditional pair. we use the acquire/release
2217 // versions of these instructions so that we flush pending writes as
2218 // per Java semantics.
2219
2220 // n.b the x86 version assumes the old value to be compared against is
2221 // in rax and updates rax with the value located in memory if the
2222 // cmpxchg fails. we supply a register for the old value explicitly
2223
2224 // the aarch64 load linked/store conditional instructions do not
2225 // accept an offset. so, unlike x86, we must provide a plain register
2226 // to identify the memory word to be compared/exchanged rather than a
2227 // register+offset Address.
2228
2229 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2230 Label &succeed, Label *fail) {
2231 // oldv holds comparison value
2232 // newv holds value to write in exchange
2233 // addr identifies memory word to compare against/update
2234 if (UseLSE) {
2235 mov(tmp, oldv);
2236 casal(Assembler::xword, oldv, newv, addr);
2237 cmp(tmp, oldv);
2238 br(Assembler::EQ, succeed);
2239 membar(AnyAny);
2240 } else {
2241 Label retry_load, nope;
2242 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2243 prfm(Address(addr), PSTL1STRM);
2244 bind(retry_load);
2245 // flush and load exclusive from the memory location
2246 // and fail if it is not what we expect
2247 ldaxr(tmp, addr);
2248 cmp(tmp, oldv);
2249 br(Assembler::NE, nope);
2250 // if we store+flush with no intervening write tmp wil be zero
2251 stlxr(tmp, newv, addr);
2252 cbzw(tmp, succeed);
2253 // retry so we only ever return after a load fails to compare
2254 // ensures we don't return a stale value after a failed write.
2255 b(retry_load);
2256 // if the memory word differs we return it in oldv and signal a fail
2257 bind(nope);
2258 membar(AnyAny);
2259 mov(oldv, tmp);
2260 }
2261 if (fail)
2262 b(*fail);
2263 }
2264
2265 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
2266 Label &succeed, Label *fail) {
2267 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
2268 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
2269 }
2270
2271 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2272 Label &succeed, Label *fail) {
2273 // oldv holds comparison value
2274 // newv holds value to write in exchange
2275 // addr identifies memory word to compare against/update
2276 // tmp returns 0/1 for success/failure
2277 if (UseLSE) {
2278 mov(tmp, oldv);
2279 casal(Assembler::word, oldv, newv, addr);
2280 cmp(tmp, oldv);
2281 br(Assembler::EQ, succeed);
2282 membar(AnyAny);
2283 } else {
2284 Label retry_load, nope;
2285 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2286 prfm(Address(addr), PSTL1STRM);
2287 bind(retry_load);
2288 // flush and load exclusive from the memory location
2289 // and fail if it is not what we expect
2290 ldaxrw(tmp, addr);
2291 cmp(tmp, oldv);
2292 br(Assembler::NE, nope);
2293 // if we store+flush with no intervening write tmp wil be zero
2294 stlxrw(tmp, newv, addr);
2295 cbzw(tmp, succeed);
2296 // retry so we only ever return after a load fails to compare
2297 // ensures we don't return a stale value after a failed write.
2298 b(retry_load);
2299 // if the memory word differs we return it in oldv and signal a fail
2300 bind(nope);
2301 membar(AnyAny);
2302 mov(oldv, tmp);
2303 }
2304 if (fail)
2305 b(*fail);
2306 }
2307
2308 // A generic CAS; success or failure is in the EQ flag. A weak CAS
2309 // doesn't retry and may fail spuriously. If the oldval is wanted,
2310 // Pass a register for the result, otherwise pass noreg.
2311
2312 // Clobbers rscratch1
2313 void MacroAssembler::cmpxchg(Register addr, Register expected,
2314 Register new_val,
2315 enum operand_size size,
2316 bool acquire, bool release,
2317 bool weak,
2318 Register result) {
2319 if (result == noreg) result = rscratch1;
2320 if (UseLSE) {
2321 mov(result, expected);
2322 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
2323 cmp(result, expected);
2324 } else {
2325 BLOCK_COMMENT("cmpxchg {");
2326 Label retry_load, done;
2327 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
2328 prfm(Address(addr), PSTL1STRM);
2329 bind(retry_load);
2330 load_exclusive(result, addr, size, acquire);
2331 if (size == xword)
2332 cmp(result, expected);
2333 else
2334 cmpw(result, expected);
2335 br(Assembler::NE, done);
2336 store_exclusive(rscratch1, new_val, addr, size, release);
2337 if (weak) {
2338 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
2339 } else {
2340 cbnzw(rscratch1, retry_load);
2341 }
2342 bind(done);
2343 BLOCK_COMMENT("} cmpxchg");
2344 }
2345 }
2346
2347 static bool different(Register a, RegisterOrConstant b, Register c) {
2348 if (b.is_constant())
2349 return a != c;
2350 else
2351 return a != b.as_register() && a != c && b.as_register() != c;
2352 }
2353
2354 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
2355 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
2356 if (UseLSE) { \
2357 prev = prev->is_valid() ? prev : zr; \
2358 if (incr.is_register()) { \
2359 AOP(sz, incr.as_register(), prev, addr); \
2360 } else { \
2361 mov(rscratch2, incr.as_constant()); \
2362 AOP(sz, rscratch2, prev, addr); \
2363 } \
2364 return; \
2365 } \
2366 Register result = rscratch2; \
2367 if (prev->is_valid()) \
2368 result = different(prev, incr, addr) ? prev : rscratch2; \
2369 \
2370 Label retry_load; \
2371 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \
2372 prfm(Address(addr), PSTL1STRM); \
2373 bind(retry_load); \
2374 LDXR(result, addr); \
2375 OP(rscratch1, result, incr); \
2376 STXR(rscratch2, rscratch1, addr); \
2377 cbnzw(rscratch2, retry_load); \
2378 if (prev->is_valid() && prev != result) { \
2379 IOP(prev, rscratch1, incr); \
2380 } \
2381 }
2382
2383 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
2384 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
2385 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
2386 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
2387
2388 #undef ATOMIC_OP
2389
2390 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
2391 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2392 if (UseLSE) { \
2393 prev = prev->is_valid() ? prev : zr; \
2394 AOP(sz, newv, prev, addr); \
2395 return; \
2396 } \
2397 Register result = rscratch2; \
2398 if (prev->is_valid()) \
2399 result = different(prev, newv, addr) ? prev : rscratch2; \
2400 \
2401 Label retry_load; \
2402 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \
2403 prfm(Address(addr), PSTL1STRM); \
2404 bind(retry_load); \
2405 LDXR(result, addr); \
2406 STXR(rscratch1, newv, addr); \
2407 cbnzw(rscratch1, retry_load); \
2408 if (prev->is_valid() && prev != result) \
2409 mov(prev, result); \
2410 }
2411
2412 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
2413 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
2414 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
2415 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
2416
2417 #undef ATOMIC_XCHG
2418
2419 void MacroAssembler::incr_allocated_bytes(Register thread,
2420 Register var_size_in_bytes,
2421 int con_size_in_bytes,
2422 Register t1) {
2423 if (!thread->is_valid()) {
2424 thread = rthread;
2425 }
2426 assert(t1->is_valid(), "need temp reg");
2427
2428 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2429 if (var_size_in_bytes->is_valid()) {
2430 add(t1, t1, var_size_in_bytes);
2431 } else {
2432 add(t1, t1, con_size_in_bytes);
2433 }
2434 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset())));
2435 }
2436
2437 #ifndef PRODUCT
2438 extern "C" void findpc(intptr_t x);
2439 #endif
2440
2441 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2442 {
2443 // In order to get locks to work, we need to fake a in_VM state
2444 if (ShowMessageBoxOnError ) {
2445 JavaThread* thread = JavaThread::current();
2446 JavaThreadState saved_state = thread->thread_state();
2447 thread->set_thread_state(_thread_in_vm);
2448 #ifndef PRODUCT
2449 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2450 ttyLocker ttyl;
2451 BytecodeCounter::print();
2452 }
2453 #endif
2454 if (os::message_box(msg, "Execution stopped, print registers?")) {
2455 ttyLocker ttyl;
2456 tty->print_cr(" pc = 0x%016lx", pc);
2457 #ifndef PRODUCT
2458 tty->cr();
2459 findpc(pc);
2460 tty->cr();
2461 #endif
2462 tty->print_cr(" r0 = 0x%016lx", regs[0]);
2463 tty->print_cr(" r1 = 0x%016lx", regs[1]);
2464 tty->print_cr(" r2 = 0x%016lx", regs[2]);
2465 tty->print_cr(" r3 = 0x%016lx", regs[3]);
2466 tty->print_cr(" r4 = 0x%016lx", regs[4]);
2467 tty->print_cr(" r5 = 0x%016lx", regs[5]);
2468 tty->print_cr(" r6 = 0x%016lx", regs[6]);
2469 tty->print_cr(" r7 = 0x%016lx", regs[7]);
2470 tty->print_cr(" r8 = 0x%016lx", regs[8]);
2471 tty->print_cr(" r9 = 0x%016lx", regs[9]);
2472 tty->print_cr("r10 = 0x%016lx", regs[10]);
2473 tty->print_cr("r11 = 0x%016lx", regs[11]);
2474 tty->print_cr("r12 = 0x%016lx", regs[12]);
2475 tty->print_cr("r13 = 0x%016lx", regs[13]);
2476 tty->print_cr("r14 = 0x%016lx", regs[14]);
2477 tty->print_cr("r15 = 0x%016lx", regs[15]);
2478 tty->print_cr("r16 = 0x%016lx", regs[16]);
2479 tty->print_cr("r17 = 0x%016lx", regs[17]);
2480 tty->print_cr("r18 = 0x%016lx", regs[18]);
2481 tty->print_cr("r19 = 0x%016lx", regs[19]);
2482 tty->print_cr("r20 = 0x%016lx", regs[20]);
2483 tty->print_cr("r21 = 0x%016lx", regs[21]);
2484 tty->print_cr("r22 = 0x%016lx", regs[22]);
2485 tty->print_cr("r23 = 0x%016lx", regs[23]);
2486 tty->print_cr("r24 = 0x%016lx", regs[24]);
2487 tty->print_cr("r25 = 0x%016lx", regs[25]);
2488 tty->print_cr("r26 = 0x%016lx", regs[26]);
2489 tty->print_cr("r27 = 0x%016lx", regs[27]);
2490 tty->print_cr("r28 = 0x%016lx", regs[28]);
2491 tty->print_cr("r30 = 0x%016lx", regs[30]);
2492 tty->print_cr("r31 = 0x%016lx", regs[31]);
2493 BREAKPOINT;
2494 }
2495 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
2496 } else {
2497 ttyLocker ttyl;
2498 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
2499 msg);
2500 assert(false, "DEBUG MESSAGE: %s", msg);
2501 }
2502 }
2503
2504 #ifdef BUILTIN_SIM
2505 // routine to generate an x86 prolog for a stub function which
2506 // bootstraps into the generated ARM code which directly follows the
2507 // stub
2508 //
2509 // the argument encodes the number of general and fp registers
2510 // passed by the caller and the callng convention (currently just
2511 // the number of general registers and assumes C argument passing)
2512
2513 extern "C" {
2514 int aarch64_stub_prolog_size();
2515 void aarch64_stub_prolog();
2516 void aarch64_prolog();
2517 }
2518
2519 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type,
2520 address *prolog_ptr)
2521 {
2522 int calltype = (((ret_type & 0x3) << 8) |
2523 ((fp_arg_count & 0xf) << 4) |
2524 (gp_arg_count & 0xf));
2525
2526 // the addresses for the x86 to ARM entry code we need to use
2527 address start = pc();
2528 // printf("start = %lx\n", start);
2529 int byteCount = aarch64_stub_prolog_size();
2530 // printf("byteCount = %x\n", byteCount);
2531 int instructionCount = (byteCount + 3)/ 4;
2532 // printf("instructionCount = %x\n", instructionCount);
2533 for (int i = 0; i < instructionCount; i++) {
2534 nop();
2535 }
2536
2537 memcpy(start, (void*)aarch64_stub_prolog, byteCount);
2538
2539 // write the address of the setup routine and the call format at the
2540 // end of into the copied code
2541 u_int64_t *patch_end = (u_int64_t *)(start + byteCount);
2542 if (prolog_ptr)
2543 patch_end[-2] = (u_int64_t)prolog_ptr;
2544 patch_end[-1] = calltype;
2545 }
2546 #endif
2547
2548 void MacroAssembler::push_call_clobbered_registers() {
2549 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2550
2551 // Push v0-v7, v16-v31.
2552 for (int i = 30; i >= 0; i -= 2) {
2553 if (i <= v7->encoding() || i >= v16->encoding()) {
2554 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2555 Address(pre(sp, -2 * wordSize)));
2556 }
2557 }
2558 }
2559
2560 void MacroAssembler::pop_call_clobbered_registers() {
2561
2562 for (int i = 0; i < 32; i += 2) {
2563 if (i <= v7->encoding() || i >= v16->encoding()) {
2564 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2565 Address(post(sp, 2 * wordSize)));
2566 }
2567 }
2568
2569 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2570 }
2571
2572 void MacroAssembler::push_CPU_state(bool save_vectors) {
2573 push(0x3fffffff, sp); // integer registers except lr & sp
2574
2575 if (!save_vectors) {
2576 for (int i = 30; i >= 0; i -= 2)
2577 stpd(as_FloatRegister(i), as_FloatRegister(i+1),
2578 Address(pre(sp, -2 * wordSize)));
2579 } else {
2580 for (int i = 30; i >= 0; i -= 2)
2581 stpq(as_FloatRegister(i), as_FloatRegister(i+1),
2582 Address(pre(sp, -4 * wordSize)));
2583 }
2584 }
2585
2586 void MacroAssembler::pop_CPU_state(bool restore_vectors) {
2587 if (!restore_vectors) {
2588 for (int i = 0; i < 32; i += 2)
2589 ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
2590 Address(post(sp, 2 * wordSize)));
2591 } else {
2592 for (int i = 0; i < 32; i += 2)
2593 ldpq(as_FloatRegister(i), as_FloatRegister(i+1),
2594 Address(post(sp, 4 * wordSize)));
2595 }
2596
2597 pop(0x3fffffff, sp); // integer registers except lr & sp
2598 }
2599
2600 /**
2601 * Helpers for multiply_to_len().
2602 */
2603 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
2604 Register src1, Register src2) {
2605 adds(dest_lo, dest_lo, src1);
2606 adc(dest_hi, dest_hi, zr);
2607 adds(dest_lo, dest_lo, src2);
2608 adc(final_dest_hi, dest_hi, zr);
2609 }
2610
2611 // Generate an address from (r + r1 extend offset). "size" is the
2612 // size of the operand. The result may be in rscratch2.
2613 Address MacroAssembler::offsetted_address(Register r, Register r1,
2614 Address::extend ext, int offset, int size) {
2615 if (offset || (ext.shift() % size != 0)) {
2616 lea(rscratch2, Address(r, r1, ext));
2617 return Address(rscratch2, offset);
2618 } else {
2619 return Address(r, r1, ext);
2620 }
2621 }
2622
2623 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
2624 {
2625 assert(offset >= 0, "spill to negative address?");
2626 // Offset reachable ?
2627 // Not aligned - 9 bits signed offset
2628 // Aligned - 12 bits unsigned offset shifted
2629 Register base = sp;
2630 if ((offset & (size-1)) && offset >= (1<<8)) {
2631 add(tmp, base, offset & ((1<<12)-1));
2632 base = tmp;
2633 offset &= -1<<12;
2634 }
2635
2636 if (offset >= (1<<12) * size) {
2637 add(tmp, base, offset & (((1<<12)-1)<<12));
2638 base = tmp;
2639 offset &= ~(((1<<12)-1)<<12);
2640 }
2641
2642 return Address(base, offset);
2643 }
2644
2645 // Checks whether offset is aligned.
2646 // Returns true if it is, else false.
2647 bool MacroAssembler::merge_alignment_check(Register base,
2648 size_t size,
2649 long cur_offset,
2650 long prev_offset) const {
2651 if (AvoidUnalignedAccesses) {
2652 if (base == sp) {
2653 // Checks whether low offset if aligned to pair of registers.
2654 long pair_mask = size * 2 - 1;
2655 long offset = prev_offset > cur_offset ? cur_offset : prev_offset;
2656 return (offset & pair_mask) == 0;
2657 } else { // If base is not sp, we can't guarantee the access is aligned.
2658 return false;
2659 }
2660 } else {
2661 long mask = size - 1;
2662 // Load/store pair instruction only supports element size aligned offset.
2663 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
2664 }
2665 }
2666
2667 // Checks whether current and previous loads/stores can be merged.
2668 // Returns true if it can be merged, else false.
2669 bool MacroAssembler::ldst_can_merge(Register rt,
2670 const Address &adr,
2671 size_t cur_size_in_bytes,
2672 bool is_store) const {
2673 address prev = pc() - NativeInstruction::instruction_size;
2674 address last = code()->last_insn();
2675
2676 if (last == NULL || !nativeInstruction_at(last)->is_Imm_LdSt()) {
2677 return false;
2678 }
2679
2680 if (adr.getMode() != Address::base_plus_offset || prev != last) {
2681 return false;
2682 }
2683
2684 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
2685 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
2686
2687 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
2688 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
2689
2690 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
2691 return false;
2692 }
2693
2694 long max_offset = 63 * prev_size_in_bytes;
2695 long min_offset = -64 * prev_size_in_bytes;
2696
2697 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
2698
2699 // Only same base can be merged.
2700 if (adr.base() != prev_ldst->base()) {
2701 return false;
2702 }
2703
2704 long cur_offset = adr.offset();
2705 long prev_offset = prev_ldst->offset();
2706 size_t diff = abs(cur_offset - prev_offset);
2707 if (diff != prev_size_in_bytes) {
2708 return false;
2709 }
2710
2711 // Following cases can not be merged:
2712 // ldr x2, [x2, #8]
2713 // ldr x3, [x2, #16]
2714 // or:
2715 // ldr x2, [x3, #8]
2716 // ldr x2, [x3, #16]
2717 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
2718 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
2719 return false;
2720 }
2721
2722 long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
2723 // Offset range must be in ldp/stp instruction's range.
2724 if (low_offset > max_offset || low_offset < min_offset) {
2725 return false;
2726 }
2727
2728 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
2729 return true;
2730 }
2731
2732 return false;
2733 }
2734
2735 // Merge current load/store with previous load/store into ldp/stp.
2736 void MacroAssembler::merge_ldst(Register rt,
2737 const Address &adr,
2738 size_t cur_size_in_bytes,
2739 bool is_store) {
2740
2741 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
2742
2743 Register rt_low, rt_high;
2744 address prev = pc() - NativeInstruction::instruction_size;
2745 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
2746
2747 long offset;
2748
2749 if (adr.offset() < prev_ldst->offset()) {
2750 offset = adr.offset();
2751 rt_low = rt;
2752 rt_high = prev_ldst->target();
2753 } else {
2754 offset = prev_ldst->offset();
2755 rt_low = prev_ldst->target();
2756 rt_high = rt;
2757 }
2758
2759 Address adr_p = Address(prev_ldst->base(), offset);
2760 // Overwrite previous generated binary.
2761 code_section()->set_end(prev);
2762
2763 const int sz = prev_ldst->size_in_bytes();
2764 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
2765 if (!is_store) {
2766 BLOCK_COMMENT("merged ldr pair");
2767 if (sz == 8) {
2768 ldp(rt_low, rt_high, adr_p);
2769 } else {
2770 ldpw(rt_low, rt_high, adr_p);
2771 }
2772 } else {
2773 BLOCK_COMMENT("merged str pair");
2774 if (sz == 8) {
2775 stp(rt_low, rt_high, adr_p);
2776 } else {
2777 stpw(rt_low, rt_high, adr_p);
2778 }
2779 }
2780 }
2781
2782 /**
2783 * Multiply 64 bit by 64 bit first loop.
2784 */
2785 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2786 Register y, Register y_idx, Register z,
2787 Register carry, Register product,
2788 Register idx, Register kdx) {
2789 //
2790 // jlong carry, x[], y[], z[];
2791 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2792 // huge_128 product = y[idx] * x[xstart] + carry;
2793 // z[kdx] = (jlong)product;
2794 // carry = (jlong)(product >>> 64);
2795 // }
2796 // z[xstart] = carry;
2797 //
2798
2799 Label L_first_loop, L_first_loop_exit;
2800 Label L_one_x, L_one_y, L_multiply;
2801
2802 subsw(xstart, xstart, 1);
2803 br(Assembler::MI, L_one_x);
2804
2805 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
2806 ldr(x_xstart, Address(rscratch1));
2807 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
2808
2809 bind(L_first_loop);
2810 subsw(idx, idx, 1);
2811 br(Assembler::MI, L_first_loop_exit);
2812 subsw(idx, idx, 1);
2813 br(Assembler::MI, L_one_y);
2814 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2815 ldr(y_idx, Address(rscratch1));
2816 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
2817 bind(L_multiply);
2818
2819 // AArch64 has a multiply-accumulate instruction that we can't use
2820 // here because it has no way to process carries, so we have to use
2821 // separate add and adc instructions. Bah.
2822 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
2823 mul(product, x_xstart, y_idx);
2824 adds(product, product, carry);
2825 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
2826
2827 subw(kdx, kdx, 2);
2828 ror(product, product, 32); // back to big-endian
2829 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
2830
2831 b(L_first_loop);
2832
2833 bind(L_one_y);
2834 ldrw(y_idx, Address(y, 0));
2835 b(L_multiply);
2836
2837 bind(L_one_x);
2838 ldrw(x_xstart, Address(x, 0));
2839 b(L_first_loop);
2840
2841 bind(L_first_loop_exit);
2842 }
2843
2844 /**
2845 * Multiply 128 bit by 128. Unrolled inner loop.
2846 *
2847 */
2848 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
2849 Register carry, Register carry2,
2850 Register idx, Register jdx,
2851 Register yz_idx1, Register yz_idx2,
2852 Register tmp, Register tmp3, Register tmp4,
2853 Register tmp6, Register product_hi) {
2854
2855 // jlong carry, x[], y[], z[];
2856 // int kdx = ystart+1;
2857 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
2858 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
2859 // jlong carry2 = (jlong)(tmp3 >>> 64);
2860 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
2861 // carry = (jlong)(tmp4 >>> 64);
2862 // z[kdx+idx+1] = (jlong)tmp3;
2863 // z[kdx+idx] = (jlong)tmp4;
2864 // }
2865 // idx += 2;
2866 // if (idx > 0) {
2867 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
2868 // z[kdx+idx] = (jlong)yz_idx1;
2869 // carry = (jlong)(yz_idx1 >>> 64);
2870 // }
2871 //
2872
2873 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
2874
2875 lsrw(jdx, idx, 2);
2876
2877 bind(L_third_loop);
2878
2879 subsw(jdx, jdx, 1);
2880 br(Assembler::MI, L_third_loop_exit);
2881 subw(idx, idx, 4);
2882
2883 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2884
2885 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
2886
2887 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2888
2889 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
2890 ror(yz_idx2, yz_idx2, 32);
2891
2892 ldp(rscratch2, rscratch1, Address(tmp6, 0));
2893
2894 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2895 umulh(tmp4, product_hi, yz_idx1);
2896
2897 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
2898 ror(rscratch2, rscratch2, 32);
2899
2900 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
2901 umulh(carry2, product_hi, yz_idx2);
2902
2903 // propagate sum of both multiplications into carry:tmp4:tmp3
2904 adds(tmp3, tmp3, carry);
2905 adc(tmp4, tmp4, zr);
2906 adds(tmp3, tmp3, rscratch1);
2907 adcs(tmp4, tmp4, tmp);
2908 adc(carry, carry2, zr);
2909 adds(tmp4, tmp4, rscratch2);
2910 adc(carry, carry, zr);
2911
2912 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
2913 ror(tmp4, tmp4, 32);
2914 stp(tmp4, tmp3, Address(tmp6, 0));
2915
2916 b(L_third_loop);
2917 bind (L_third_loop_exit);
2918
2919 andw (idx, idx, 0x3);
2920 cbz(idx, L_post_third_loop_done);
2921
2922 Label L_check_1;
2923 subsw(idx, idx, 2);
2924 br(Assembler::MI, L_check_1);
2925
2926 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2927 ldr(yz_idx1, Address(rscratch1, 0));
2928 ror(yz_idx1, yz_idx1, 32);
2929 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
2930 umulh(tmp4, product_hi, yz_idx1);
2931 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2932 ldr(yz_idx2, Address(rscratch1, 0));
2933 ror(yz_idx2, yz_idx2, 32);
2934
2935 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
2936
2937 ror(tmp3, tmp3, 32);
2938 str(tmp3, Address(rscratch1, 0));
2939
2940 bind (L_check_1);
2941
2942 andw (idx, idx, 0x1);
2943 subsw(idx, idx, 1);
2944 br(Assembler::MI, L_post_third_loop_done);
2945 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
2946 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
2947 umulh(carry2, tmp4, product_hi);
2948 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2949
2950 add2_with_carry(carry2, tmp3, tmp4, carry);
2951
2952 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
2953 extr(carry, carry2, tmp3, 32);
2954
2955 bind(L_post_third_loop_done);
2956 }
2957
2958 /**
2959 * Code for BigInteger::multiplyToLen() instrinsic.
2960 *
2961 * r0: x
2962 * r1: xlen
2963 * r2: y
2964 * r3: ylen
2965 * r4: z
2966 * r5: zlen
2967 * r10: tmp1
2968 * r11: tmp2
2969 * r12: tmp3
2970 * r13: tmp4
2971 * r14: tmp5
2972 * r15: tmp6
2973 * r16: tmp7
2974 *
2975 */
2976 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
2977 Register z, Register zlen,
2978 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
2979 Register tmp5, Register tmp6, Register product_hi) {
2980
2981 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
2982
2983 const Register idx = tmp1;
2984 const Register kdx = tmp2;
2985 const Register xstart = tmp3;
2986
2987 const Register y_idx = tmp4;
2988 const Register carry = tmp5;
2989 const Register product = xlen;
2990 const Register x_xstart = zlen; // reuse register
2991
2992 // First Loop.
2993 //
2994 // final static long LONG_MASK = 0xffffffffL;
2995 // int xstart = xlen - 1;
2996 // int ystart = ylen - 1;
2997 // long carry = 0;
2998 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
2999 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
3000 // z[kdx] = (int)product;
3001 // carry = product >>> 32;
3002 // }
3003 // z[xstart] = (int)carry;
3004 //
3005
3006 movw(idx, ylen); // idx = ylen;
3007 movw(kdx, zlen); // kdx = xlen+ylen;
3008 mov(carry, zr); // carry = 0;
3009
3010 Label L_done;
3011
3012 movw(xstart, xlen);
3013 subsw(xstart, xstart, 1);
3014 br(Assembler::MI, L_done);
3015
3016 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
3017
3018 Label L_second_loop;
3019 cbzw(kdx, L_second_loop);
3020
3021 Label L_carry;
3022 subw(kdx, kdx, 1);
3023 cbzw(kdx, L_carry);
3024
3025 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3026 lsr(carry, carry, 32);
3027 subw(kdx, kdx, 1);
3028
3029 bind(L_carry);
3030 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3031
3032 // Second and third (nested) loops.
3033 //
3034 // for (int i = xstart-1; i >= 0; i--) { // Second loop
3035 // carry = 0;
3036 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
3037 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
3038 // (z[k] & LONG_MASK) + carry;
3039 // z[k] = (int)product;
3040 // carry = product >>> 32;
3041 // }
3042 // z[i] = (int)carry;
3043 // }
3044 //
3045 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
3046
3047 const Register jdx = tmp1;
3048
3049 bind(L_second_loop);
3050 mov(carry, zr); // carry = 0;
3051 movw(jdx, ylen); // j = ystart+1
3052
3053 subsw(xstart, xstart, 1); // i = xstart-1;
3054 br(Assembler::MI, L_done);
3055
3056 str(z, Address(pre(sp, -4 * wordSize)));
3057
3058 Label L_last_x;
3059 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
3060 subsw(xstart, xstart, 1); // i = xstart-1;
3061 br(Assembler::MI, L_last_x);
3062
3063 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
3064 ldr(product_hi, Address(rscratch1));
3065 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
3066
3067 Label L_third_loop_prologue;
3068 bind(L_third_loop_prologue);
3069
3070 str(ylen, Address(sp, wordSize));
3071 stp(x, xstart, Address(sp, 2 * wordSize));
3072 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
3073 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
3074 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
3075 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
3076
3077 addw(tmp3, xlen, 1);
3078 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3079 subsw(tmp3, tmp3, 1);
3080 br(Assembler::MI, L_done);
3081
3082 lsr(carry, carry, 32);
3083 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3084 b(L_second_loop);
3085
3086 // Next infrequent code is moved outside loops.
3087 bind(L_last_x);
3088 ldrw(product_hi, Address(x, 0));
3089 b(L_third_loop_prologue);
3090
3091 bind(L_done);
3092 }
3093
3094 // Code for BigInteger::mulAdd instrinsic
3095 // out = r0
3096 // in = r1
3097 // offset = r2 (already out.length-offset)
3098 // len = r3
3099 // k = r4
3100 //
3101 // pseudo code from java implementation:
3102 // carry = 0;
3103 // offset = out.length-offset - 1;
3104 // for (int j=len-1; j >= 0; j--) {
3105 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
3106 // out[offset--] = (int)product;
3107 // carry = product >>> 32;
3108 // }
3109 // return (int)carry;
3110 void MacroAssembler::mul_add(Register out, Register in, Register offset,
3111 Register len, Register k) {
3112 Label LOOP, END;
3113 // pre-loop
3114 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
3115 csel(out, zr, out, Assembler::EQ);
3116 br(Assembler::EQ, END);
3117 add(in, in, len, LSL, 2); // in[j+1] address
3118 add(offset, out, offset, LSL, 2); // out[offset + 1] address
3119 mov(out, zr); // used to keep carry now
3120 BIND(LOOP);
3121 ldrw(rscratch1, Address(pre(in, -4)));
3122 madd(rscratch1, rscratch1, k, out);
3123 ldrw(rscratch2, Address(pre(offset, -4)));
3124 add(rscratch1, rscratch1, rscratch2);
3125 strw(rscratch1, Address(offset));
3126 lsr(out, rscratch1, 32);
3127 subs(len, len, 1);
3128 br(Assembler::NE, LOOP);
3129 BIND(END);
3130 }
3131
3132 /**
3133 * Emits code to update CRC-32 with a byte value according to constants in table
3134 *
3135 * @param [in,out]crc Register containing the crc.
3136 * @param [in]val Register containing the byte to fold into the CRC.
3137 * @param [in]table Register containing the table of crc constants.
3138 *
3139 * uint32_t crc;
3140 * val = crc_table[(val ^ crc) & 0xFF];
3141 * crc = val ^ (crc >> 8);
3142 *
3143 */
3144 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
3145 eor(val, val, crc);
3146 andr(val, val, 0xff);
3147 ldrw(val, Address(table, val, Address::lsl(2)));
3148 eor(crc, val, crc, Assembler::LSR, 8);
3149 }
3150
3151 /**
3152 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
3153 *
3154 * @param [in,out]crc Register containing the crc.
3155 * @param [in]v Register containing the 32-bit to fold into the CRC.
3156 * @param [in]table0 Register containing table 0 of crc constants.
3157 * @param [in]table1 Register containing table 1 of crc constants.
3158 * @param [in]table2 Register containing table 2 of crc constants.
3159 * @param [in]table3 Register containing table 3 of crc constants.
3160 *
3161 * uint32_t crc;
3162 * v = crc ^ v
3163 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
3164 *
3165 */
3166 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
3167 Register table0, Register table1, Register table2, Register table3,
3168 bool upper) {
3169 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
3170 uxtb(tmp, v);
3171 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
3172 ubfx(tmp, v, 8, 8);
3173 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
3174 eor(crc, crc, tmp);
3175 ubfx(tmp, v, 16, 8);
3176 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
3177 eor(crc, crc, tmp);
3178 ubfx(tmp, v, 24, 8);
3179 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
3180 eor(crc, crc, tmp);
3181 }
3182
3183 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
3184 Register len, Register tmp0, Register tmp1, Register tmp2,
3185 Register tmp3) {
3186 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3187 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3188
3189 mvnw(crc, crc);
3190
3191 subs(len, len, 128);
3192 br(Assembler::GE, CRC_by64_pre);
3193 BIND(CRC_less64);
3194 adds(len, len, 128-32);
3195 br(Assembler::GE, CRC_by32_loop);
3196 BIND(CRC_less32);
3197 adds(len, len, 32-4);
3198 br(Assembler::GE, CRC_by4_loop);
3199 adds(len, len, 4);
3200 br(Assembler::GT, CRC_by1_loop);
3201 b(L_exit);
3202
3203 BIND(CRC_by32_loop);
3204 ldp(tmp0, tmp1, Address(post(buf, 16)));
3205 subs(len, len, 32);
3206 crc32x(crc, crc, tmp0);
3207 ldr(tmp2, Address(post(buf, 8)));
3208 crc32x(crc, crc, tmp1);
3209 ldr(tmp3, Address(post(buf, 8)));
3210 crc32x(crc, crc, tmp2);
3211 crc32x(crc, crc, tmp3);
3212 br(Assembler::GE, CRC_by32_loop);
3213 cmn(len, 32);
3214 br(Assembler::NE, CRC_less32);
3215 b(L_exit);
3216
3217 BIND(CRC_by4_loop);
3218 ldrw(tmp0, Address(post(buf, 4)));
3219 subs(len, len, 4);
3220 crc32w(crc, crc, tmp0);
3221 br(Assembler::GE, CRC_by4_loop);
3222 adds(len, len, 4);
3223 br(Assembler::LE, L_exit);
3224 BIND(CRC_by1_loop);
3225 ldrb(tmp0, Address(post(buf, 1)));
3226 subs(len, len, 1);
3227 crc32b(crc, crc, tmp0);
3228 br(Assembler::GT, CRC_by1_loop);
3229 b(L_exit);
3230
3231 BIND(CRC_by64_pre);
3232 sub(buf, buf, 8);
3233 ldp(tmp0, tmp1, Address(buf, 8));
3234 crc32x(crc, crc, tmp0);
3235 ldr(tmp2, Address(buf, 24));
3236 crc32x(crc, crc, tmp1);
3237 ldr(tmp3, Address(buf, 32));
3238 crc32x(crc, crc, tmp2);
3239 ldr(tmp0, Address(buf, 40));
3240 crc32x(crc, crc, tmp3);
3241 ldr(tmp1, Address(buf, 48));
3242 crc32x(crc, crc, tmp0);
3243 ldr(tmp2, Address(buf, 56));
3244 crc32x(crc, crc, tmp1);
3245 ldr(tmp3, Address(pre(buf, 64)));
3246
3247 b(CRC_by64_loop);
3248
3249 align(CodeEntryAlignment);
3250 BIND(CRC_by64_loop);
3251 subs(len, len, 64);
3252 crc32x(crc, crc, tmp2);
3253 ldr(tmp0, Address(buf, 8));
3254 crc32x(crc, crc, tmp3);
3255 ldr(tmp1, Address(buf, 16));
3256 crc32x(crc, crc, tmp0);
3257 ldr(tmp2, Address(buf, 24));
3258 crc32x(crc, crc, tmp1);
3259 ldr(tmp3, Address(buf, 32));
3260 crc32x(crc, crc, tmp2);
3261 ldr(tmp0, Address(buf, 40));
3262 crc32x(crc, crc, tmp3);
3263 ldr(tmp1, Address(buf, 48));
3264 crc32x(crc, crc, tmp0);
3265 ldr(tmp2, Address(buf, 56));
3266 crc32x(crc, crc, tmp1);
3267 ldr(tmp3, Address(pre(buf, 64)));
3268 br(Assembler::GE, CRC_by64_loop);
3269
3270 // post-loop
3271 crc32x(crc, crc, tmp2);
3272 crc32x(crc, crc, tmp3);
3273
3274 sub(len, len, 64);
3275 add(buf, buf, 8);
3276 cmn(len, 128);
3277 br(Assembler::NE, CRC_less64);
3278 BIND(L_exit);
3279 mvnw(crc, crc);
3280 }
3281
3282 /**
3283 * @param crc register containing existing CRC (32-bit)
3284 * @param buf register pointing to input byte buffer (byte*)
3285 * @param len register containing number of bytes
3286 * @param table register that will contain address of CRC table
3287 * @param tmp scratch register
3288 */
3289 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
3290 Register table0, Register table1, Register table2, Register table3,
3291 Register tmp, Register tmp2, Register tmp3) {
3292 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
3293 unsigned long offset;
3294
3295 if (UseCRC32) {
3296 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
3297 return;
3298 }
3299
3300 mvnw(crc, crc);
3301
3302 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
3303 if (offset) add(table0, table0, offset);
3304 add(table1, table0, 1*256*sizeof(juint));
3305 add(table2, table0, 2*256*sizeof(juint));
3306 add(table3, table0, 3*256*sizeof(juint));
3307
3308 if (UseNeon) {
3309 cmp(len, 64);
3310 br(Assembler::LT, L_by16);
3311 eor(v16, T16B, v16, v16);
3312
3313 Label L_fold;
3314
3315 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
3316
3317 ld1(v0, v1, T2D, post(buf, 32));
3318 ld1r(v4, T2D, post(tmp, 8));
3319 ld1r(v5, T2D, post(tmp, 8));
3320 ld1r(v6, T2D, post(tmp, 8));
3321 ld1r(v7, T2D, post(tmp, 8));
3322 mov(v16, T4S, 0, crc);
3323
3324 eor(v0, T16B, v0, v16);
3325 sub(len, len, 64);
3326
3327 BIND(L_fold);
3328 pmull(v22, T8H, v0, v5, T8B);
3329 pmull(v20, T8H, v0, v7, T8B);
3330 pmull(v23, T8H, v0, v4, T8B);
3331 pmull(v21, T8H, v0, v6, T8B);
3332
3333 pmull2(v18, T8H, v0, v5, T16B);
3334 pmull2(v16, T8H, v0, v7, T16B);
3335 pmull2(v19, T8H, v0, v4, T16B);
3336 pmull2(v17, T8H, v0, v6, T16B);
3337
3338 uzp1(v24, v20, v22, T8H);
3339 uzp2(v25, v20, v22, T8H);
3340 eor(v20, T16B, v24, v25);
3341
3342 uzp1(v26, v16, v18, T8H);
3343 uzp2(v27, v16, v18, T8H);
3344 eor(v16, T16B, v26, v27);
3345
3346 ushll2(v22, T4S, v20, T8H, 8);
3347 ushll(v20, T4S, v20, T4H, 8);
3348
3349 ushll2(v18, T4S, v16, T8H, 8);
3350 ushll(v16, T4S, v16, T4H, 8);
3351
3352 eor(v22, T16B, v23, v22);
3353 eor(v18, T16B, v19, v18);
3354 eor(v20, T16B, v21, v20);
3355 eor(v16, T16B, v17, v16);
3356
3357 uzp1(v17, v16, v20, T2D);
3358 uzp2(v21, v16, v20, T2D);
3359 eor(v17, T16B, v17, v21);
3360
3361 ushll2(v20, T2D, v17, T4S, 16);
3362 ushll(v16, T2D, v17, T2S, 16);
3363
3364 eor(v20, T16B, v20, v22);
3365 eor(v16, T16B, v16, v18);
3366
3367 uzp1(v17, v20, v16, T2D);
3368 uzp2(v21, v20, v16, T2D);
3369 eor(v28, T16B, v17, v21);
3370
3371 pmull(v22, T8H, v1, v5, T8B);
3372 pmull(v20, T8H, v1, v7, T8B);
3373 pmull(v23, T8H, v1, v4, T8B);
3374 pmull(v21, T8H, v1, v6, T8B);
3375
3376 pmull2(v18, T8H, v1, v5, T16B);
3377 pmull2(v16, T8H, v1, v7, T16B);
3378 pmull2(v19, T8H, v1, v4, T16B);
3379 pmull2(v17, T8H, v1, v6, T16B);
3380
3381 ld1(v0, v1, T2D, post(buf, 32));
3382
3383 uzp1(v24, v20, v22, T8H);
3384 uzp2(v25, v20, v22, T8H);
3385 eor(v20, T16B, v24, v25);
3386
3387 uzp1(v26, v16, v18, T8H);
3388 uzp2(v27, v16, v18, T8H);
3389 eor(v16, T16B, v26, v27);
3390
3391 ushll2(v22, T4S, v20, T8H, 8);
3392 ushll(v20, T4S, v20, T4H, 8);
3393
3394 ushll2(v18, T4S, v16, T8H, 8);
3395 ushll(v16, T4S, v16, T4H, 8);
3396
3397 eor(v22, T16B, v23, v22);
3398 eor(v18, T16B, v19, v18);
3399 eor(v20, T16B, v21, v20);
3400 eor(v16, T16B, v17, v16);
3401
3402 uzp1(v17, v16, v20, T2D);
3403 uzp2(v21, v16, v20, T2D);
3404 eor(v16, T16B, v17, v21);
3405
3406 ushll2(v20, T2D, v16, T4S, 16);
3407 ushll(v16, T2D, v16, T2S, 16);
3408
3409 eor(v20, T16B, v22, v20);
3410 eor(v16, T16B, v16, v18);
3411
3412 uzp1(v17, v20, v16, T2D);
3413 uzp2(v21, v20, v16, T2D);
3414 eor(v20, T16B, v17, v21);
3415
3416 shl(v16, T2D, v28, 1);
3417 shl(v17, T2D, v20, 1);
3418
3419 eor(v0, T16B, v0, v16);
3420 eor(v1, T16B, v1, v17);
3421
3422 subs(len, len, 32);
3423 br(Assembler::GE, L_fold);
3424
3425 mov(crc, 0);
3426 mov(tmp, v0, T1D, 0);
3427 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3428 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3429 mov(tmp, v0, T1D, 1);
3430 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3431 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3432 mov(tmp, v1, T1D, 0);
3433 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3434 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3435 mov(tmp, v1, T1D, 1);
3436 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3437 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3438
3439 add(len, len, 32);
3440 }
3441
3442 BIND(L_by16);
3443 subs(len, len, 16);
3444 br(Assembler::GE, L_by16_loop);
3445 adds(len, len, 16-4);
3446 br(Assembler::GE, L_by4_loop);
3447 adds(len, len, 4);
3448 br(Assembler::GT, L_by1_loop);
3449 b(L_exit);
3450
3451 BIND(L_by4_loop);
3452 ldrw(tmp, Address(post(buf, 4)));
3453 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
3454 subs(len, len, 4);
3455 br(Assembler::GE, L_by4_loop);
3456 adds(len, len, 4);
3457 br(Assembler::LE, L_exit);
3458 BIND(L_by1_loop);
3459 subs(len, len, 1);
3460 ldrb(tmp, Address(post(buf, 1)));
3461 update_byte_crc32(crc, tmp, table0);
3462 br(Assembler::GT, L_by1_loop);
3463 b(L_exit);
3464
3465 align(CodeEntryAlignment);
3466 BIND(L_by16_loop);
3467 subs(len, len, 16);
3468 ldp(tmp, tmp3, Address(post(buf, 16)));
3469 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
3470 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3471 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
3472 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
3473 br(Assembler::GE, L_by16_loop);
3474 adds(len, len, 16-4);
3475 br(Assembler::GE, L_by4_loop);
3476 adds(len, len, 4);
3477 br(Assembler::GT, L_by1_loop);
3478 BIND(L_exit);
3479 mvnw(crc, crc);
3480 }
3481
3482 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
3483 Register len, Register tmp0, Register tmp1, Register tmp2,
3484 Register tmp3) {
3485 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3486 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3487
3488 subs(len, len, 128);
3489 br(Assembler::GE, CRC_by64_pre);
3490 BIND(CRC_less64);
3491 adds(len, len, 128-32);
3492 br(Assembler::GE, CRC_by32_loop);
3493 BIND(CRC_less32);
3494 adds(len, len, 32-4);
3495 br(Assembler::GE, CRC_by4_loop);
3496 adds(len, len, 4);
3497 br(Assembler::GT, CRC_by1_loop);
3498 b(L_exit);
3499
3500 BIND(CRC_by32_loop);
3501 ldp(tmp0, tmp1, Address(post(buf, 16)));
3502 subs(len, len, 32);
3503 crc32cx(crc, crc, tmp0);
3504 ldr(tmp2, Address(post(buf, 8)));
3505 crc32cx(crc, crc, tmp1);
3506 ldr(tmp3, Address(post(buf, 8)));
3507 crc32cx(crc, crc, tmp2);
3508 crc32cx(crc, crc, tmp3);
3509 br(Assembler::GE, CRC_by32_loop);
3510 cmn(len, 32);
3511 br(Assembler::NE, CRC_less32);
3512 b(L_exit);
3513
3514 BIND(CRC_by4_loop);
3515 ldrw(tmp0, Address(post(buf, 4)));
3516 subs(len, len, 4);
3517 crc32cw(crc, crc, tmp0);
3518 br(Assembler::GE, CRC_by4_loop);
3519 adds(len, len, 4);
3520 br(Assembler::LE, L_exit);
3521 BIND(CRC_by1_loop);
3522 ldrb(tmp0, Address(post(buf, 1)));
3523 subs(len, len, 1);
3524 crc32cb(crc, crc, tmp0);
3525 br(Assembler::GT, CRC_by1_loop);
3526 b(L_exit);
3527
3528 BIND(CRC_by64_pre);
3529 sub(buf, buf, 8);
3530 ldp(tmp0, tmp1, Address(buf, 8));
3531 crc32cx(crc, crc, tmp0);
3532 ldr(tmp2, Address(buf, 24));
3533 crc32cx(crc, crc, tmp1);
3534 ldr(tmp3, Address(buf, 32));
3535 crc32cx(crc, crc, tmp2);
3536 ldr(tmp0, Address(buf, 40));
3537 crc32cx(crc, crc, tmp3);
3538 ldr(tmp1, Address(buf, 48));
3539 crc32cx(crc, crc, tmp0);
3540 ldr(tmp2, Address(buf, 56));
3541 crc32cx(crc, crc, tmp1);
3542 ldr(tmp3, Address(pre(buf, 64)));
3543
3544 b(CRC_by64_loop);
3545
3546 align(CodeEntryAlignment);
3547 BIND(CRC_by64_loop);
3548 subs(len, len, 64);
3549 crc32cx(crc, crc, tmp2);
3550 ldr(tmp0, Address(buf, 8));
3551 crc32cx(crc, crc, tmp3);
3552 ldr(tmp1, Address(buf, 16));
3553 crc32cx(crc, crc, tmp0);
3554 ldr(tmp2, Address(buf, 24));
3555 crc32cx(crc, crc, tmp1);
3556 ldr(tmp3, Address(buf, 32));
3557 crc32cx(crc, crc, tmp2);
3558 ldr(tmp0, Address(buf, 40));
3559 crc32cx(crc, crc, tmp3);
3560 ldr(tmp1, Address(buf, 48));
3561 crc32cx(crc, crc, tmp0);
3562 ldr(tmp2, Address(buf, 56));
3563 crc32cx(crc, crc, tmp1);
3564 ldr(tmp3, Address(pre(buf, 64)));
3565 br(Assembler::GE, CRC_by64_loop);
3566
3567 // post-loop
3568 crc32cx(crc, crc, tmp2);
3569 crc32cx(crc, crc, tmp3);
3570
3571 sub(len, len, 64);
3572 add(buf, buf, 8);
3573 cmn(len, 128);
3574 br(Assembler::NE, CRC_less64);
3575 BIND(L_exit);
3576 }
3577
3578 /**
3579 * @param crc register containing existing CRC (32-bit)
3580 * @param buf register pointing to input byte buffer (byte*)
3581 * @param len register containing number of bytes
3582 * @param table register that will contain address of CRC table
3583 * @param tmp scratch register
3584 */
3585 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
3586 Register table0, Register table1, Register table2, Register table3,
3587 Register tmp, Register tmp2, Register tmp3) {
3588 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
3589 }
3590
3591
3592 SkipIfEqual::SkipIfEqual(
3593 MacroAssembler* masm, const bool* flag_addr, bool value) {
3594 _masm = masm;
3595 unsigned long offset;
3596 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
3597 _masm->ldrb(rscratch1, Address(rscratch1, offset));
3598 _masm->cbzw(rscratch1, _label);
3599 }
3600
3601 SkipIfEqual::~SkipIfEqual() {
3602 _masm->bind(_label);
3603 }
3604
3605 void MacroAssembler::addptr(const Address &dst, int32_t src) {
3606 Address adr;
3607 switch(dst.getMode()) {
3608 case Address::base_plus_offset:
3609 // This is the expected mode, although we allow all the other
3610 // forms below.
3611 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
3612 break;
3613 default:
3614 lea(rscratch2, dst);
3615 adr = Address(rscratch2);
3616 break;
3617 }
3618 ldr(rscratch1, adr);
3619 add(rscratch1, rscratch1, src);
3620 str(rscratch1, adr);
3621 }
3622
3623 void MacroAssembler::cmpptr(Register src1, Address src2) {
3624 unsigned long offset;
3625 adrp(rscratch1, src2, offset);
3626 ldr(rscratch1, Address(rscratch1, offset));
3627 cmp(src1, rscratch1);
3628 }
3629
3630 void MacroAssembler::load_klass(Register dst, Register src) {
3631 if (UseCompressedClassPointers) {
3632 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3633 decode_klass_not_null(dst);
3634 } else {
3635 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3636 }
3637 }
3638
3639 // ((OopHandle)result).resolve();
3640 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
3641 // OopHandle::resolve is an indirection.
3642 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
3643 bs->load_at(this, IN_ROOT | IN_CONCURRENT_ROOT, T_OBJECT,
3644 result, Address(result, 0), tmp, rthread);
3645 }
3646
3647 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp) {
3648 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
3649 ldr(dst, Address(rmethod, Method::const_offset()));
3650 ldr(dst, Address(dst, ConstMethod::constants_offset()));
3651 ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes()));
3652 ldr(dst, Address(dst, mirror_offset));
3653 resolve_oop_handle(dst, tmp);
3654 }
3655
3656 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3657 if (UseCompressedClassPointers) {
3658 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3659 if (Universe::narrow_klass_base() == NULL) {
3660 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
3661 return;
3662 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3663 && Universe::narrow_klass_shift() == 0) {
3664 // Only the bottom 32 bits matter
3665 cmpw(trial_klass, tmp);
3666 return;
3667 }
3668 decode_klass_not_null(tmp);
3669 } else {
3670 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3671 }
3672 cmp(trial_klass, tmp);
3673 }
3674
3675 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3676 load_klass(dst, src);
3677 ldr(dst, Address(dst, Klass::prototype_header_offset()));
3678 }
3679
3680 void MacroAssembler::store_klass(Register dst, Register src) {
3681 // FIXME: Should this be a store release? concurrent gcs assumes
3682 // klass length is valid if klass field is not null.
3683 if (UseCompressedClassPointers) {
3684 encode_klass_not_null(src);
3685 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3686 } else {
3687 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3688 }
3689 }
3690
3691 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3692 if (UseCompressedClassPointers) {
3693 // Store to klass gap in destination
3694 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3695 }
3696 }
3697
3698 // Algorithm must match CompressedOops::encode.
3699 void MacroAssembler::encode_heap_oop(Register d, Register s) {
3700 #ifdef ASSERT
3701 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
3702 #endif
3703 verify_oop(s, "broken oop in encode_heap_oop");
3704 if (Universe::narrow_oop_base() == NULL) {
3705 if (Universe::narrow_oop_shift() != 0) {
3706 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3707 lsr(d, s, LogMinObjAlignmentInBytes);
3708 } else {
3709 mov(d, s);
3710 }
3711 } else {
3712 subs(d, s, rheapbase);
3713 csel(d, d, zr, Assembler::HS);
3714 lsr(d, d, LogMinObjAlignmentInBytes);
3715
3716 /* Old algorithm: is this any worse?
3717 Label nonnull;
3718 cbnz(r, nonnull);
3719 sub(r, r, rheapbase);
3720 bind(nonnull);
3721 lsr(r, r, LogMinObjAlignmentInBytes);
3722 */
3723 }
3724 }
3725
3726 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3727 #ifdef ASSERT
3728 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
3729 if (CheckCompressedOops) {
3730 Label ok;
3731 cbnz(r, ok);
3732 stop("null oop passed to encode_heap_oop_not_null");
3733 bind(ok);
3734 }
3735 #endif
3736 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3737 if (Universe::narrow_oop_base() != NULL) {
3738 sub(r, r, rheapbase);
3739 }
3740 if (Universe::narrow_oop_shift() != 0) {
3741 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3742 lsr(r, r, LogMinObjAlignmentInBytes);
3743 }
3744 }
3745
3746 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3747 #ifdef ASSERT
3748 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
3749 if (CheckCompressedOops) {
3750 Label ok;
3751 cbnz(src, ok);
3752 stop("null oop passed to encode_heap_oop_not_null2");
3753 bind(ok);
3754 }
3755 #endif
3756 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3757
3758 Register data = src;
3759 if (Universe::narrow_oop_base() != NULL) {
3760 sub(dst, src, rheapbase);
3761 data = dst;
3762 }
3763 if (Universe::narrow_oop_shift() != 0) {
3764 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3765 lsr(dst, data, LogMinObjAlignmentInBytes);
3766 data = dst;
3767 }
3768 if (data == src)
3769 mov(dst, src);
3770 }
3771
3772 void MacroAssembler::decode_heap_oop(Register d, Register s) {
3773 #ifdef ASSERT
3774 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
3775 #endif
3776 if (Universe::narrow_oop_base() == NULL) {
3777 if (Universe::narrow_oop_shift() != 0 || d != s) {
3778 lsl(d, s, Universe::narrow_oop_shift());
3779 }
3780 } else {
3781 Label done;
3782 if (d != s)
3783 mov(d, s);
3784 cbz(s, done);
3785 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
3786 bind(done);
3787 }
3788 verify_oop(d, "broken oop in decode_heap_oop");
3789 }
3790
3791 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3792 assert (UseCompressedOops, "should only be used for compressed headers");
3793 assert (Universe::heap() != NULL, "java heap should be initialized");
3794 // Cannot assert, unverified entry point counts instructions (see .ad file)
3795 // vtableStubs also counts instructions in pd_code_size_limit.
3796 // Also do not verify_oop as this is called by verify_oop.
3797 if (Universe::narrow_oop_shift() != 0) {
3798 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3799 if (Universe::narrow_oop_base() != NULL) {
3800 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3801 } else {
3802 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
3803 }
3804 } else {
3805 assert (Universe::narrow_oop_base() == NULL, "sanity");
3806 }
3807 }
3808
3809 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3810 assert (UseCompressedOops, "should only be used for compressed headers");
3811 assert (Universe::heap() != NULL, "java heap should be initialized");
3812 // Cannot assert, unverified entry point counts instructions (see .ad file)
3813 // vtableStubs also counts instructions in pd_code_size_limit.
3814 // Also do not verify_oop as this is called by verify_oop.
3815 if (Universe::narrow_oop_shift() != 0) {
3816 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3817 if (Universe::narrow_oop_base() != NULL) {
3818 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3819 } else {
3820 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
3821 }
3822 } else {
3823 assert (Universe::narrow_oop_base() == NULL, "sanity");
3824 if (dst != src) {
3825 mov(dst, src);
3826 }
3827 }
3828 }
3829
3830 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3831 if (Universe::narrow_klass_base() == NULL) {
3832 if (Universe::narrow_klass_shift() != 0) {
3833 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3834 lsr(dst, src, LogKlassAlignmentInBytes);
3835 } else {
3836 if (dst != src) mov(dst, src);
3837 }
3838 return;
3839 }
3840
3841 if (use_XOR_for_compressed_class_base) {
3842 if (Universe::narrow_klass_shift() != 0) {
3843 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3844 lsr(dst, dst, LogKlassAlignmentInBytes);
3845 } else {
3846 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3847 }
3848 return;
3849 }
3850
3851 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3852 && Universe::narrow_klass_shift() == 0) {
3853 movw(dst, src);
3854 return;
3855 }
3856
3857 #ifdef ASSERT
3858 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?");
3859 #endif
3860
3861 Register rbase = dst;
3862 if (dst == src) rbase = rheapbase;
3863 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3864 sub(dst, src, rbase);
3865 if (Universe::narrow_klass_shift() != 0) {
3866 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3867 lsr(dst, dst, LogKlassAlignmentInBytes);
3868 }
3869 if (dst == src) reinit_heapbase();
3870 }
3871
3872 void MacroAssembler::encode_klass_not_null(Register r) {
3873 encode_klass_not_null(r, r);
3874 }
3875
3876 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3877 Register rbase = dst;
3878 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3879
3880 if (Universe::narrow_klass_base() == NULL) {
3881 if (Universe::narrow_klass_shift() != 0) {
3882 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3883 lsl(dst, src, LogKlassAlignmentInBytes);
3884 } else {
3885 if (dst != src) mov(dst, src);
3886 }
3887 return;
3888 }
3889
3890 if (use_XOR_for_compressed_class_base) {
3891 if (Universe::narrow_klass_shift() != 0) {
3892 lsl(dst, src, LogKlassAlignmentInBytes);
3893 eor(dst, dst, (uint64_t)Universe::narrow_klass_base());
3894 } else {
3895 eor(dst, src, (uint64_t)Universe::narrow_klass_base());
3896 }
3897 return;
3898 }
3899
3900 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0
3901 && Universe::narrow_klass_shift() == 0) {
3902 if (dst != src)
3903 movw(dst, src);
3904 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32);
3905 return;
3906 }
3907
3908 // Cannot assert, unverified entry point counts instructions (see .ad file)
3909 // vtableStubs also counts instructions in pd_code_size_limit.
3910 // Also do not verify_oop as this is called by verify_oop.
3911 if (dst == src) rbase = rheapbase;
3912 mov(rbase, (uint64_t)Universe::narrow_klass_base());
3913 if (Universe::narrow_klass_shift() != 0) {
3914 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3915 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes);
3916 } else {
3917 add(dst, rbase, src);
3918 }
3919 if (dst == src) reinit_heapbase();
3920 }
3921
3922 void MacroAssembler::decode_klass_not_null(Register r) {
3923 decode_klass_not_null(r, r);
3924 }
3925
3926 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
3927 #ifdef ASSERT
3928 {
3929 ThreadInVMfromUnknown tiv;
3930 assert (UseCompressedOops, "should only be used for compressed oops");
3931 assert (Universe::heap() != NULL, "java heap should be initialized");
3932 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3933 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
3934 }
3935 #endif
3936 int oop_index = oop_recorder()->find_index(obj);
3937 InstructionMark im(this);
3938 RelocationHolder rspec = oop_Relocation::spec(oop_index);
3939 code_section()->relocate(inst_mark(), rspec);
3940 movz(dst, 0xDEAD, 16);
3941 movk(dst, 0xBEEF);
3942 }
3943
3944 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
3945 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3946 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
3947 int index = oop_recorder()->find_index(k);
3948 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop");
3949
3950 InstructionMark im(this);
3951 RelocationHolder rspec = metadata_Relocation::spec(index);
3952 code_section()->relocate(inst_mark(), rspec);
3953 narrowKlass nk = Klass::encode_klass(k);
3954 movz(dst, (nk >> 16), 16);
3955 movk(dst, nk & 0xffff);
3956 }
3957
3958 void MacroAssembler::load_heap_oop(Register dst, Address src)
3959 {
3960 if (UseCompressedOops) {
3961 ldrw(dst, src);
3962 decode_heap_oop(dst);
3963 } else {
3964 ldr(dst, src);
3965 }
3966 }
3967
3968 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src)
3969 {
3970 if (UseCompressedOops) {
3971 ldrw(dst, src);
3972 decode_heap_oop_not_null(dst);
3973 } else {
3974 ldr(dst, src);
3975 }
3976 }
3977
3978 void MacroAssembler::store_heap_oop(Address dst, Register src) {
3979 if (UseCompressedOops) {
3980 assert(!dst.uses(src), "not enough registers");
3981 encode_heap_oop(src);
3982 strw(src, dst);
3983 } else
3984 str(src, dst);
3985 }
3986
3987 // Used for storing NULLs.
3988 void MacroAssembler::store_heap_oop_null(Address dst) {
3989 if (UseCompressedOops) {
3990 strw(zr, dst);
3991 } else
3992 str(zr, dst);
3993 }
3994
3995 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
3996 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
3997 int index = oop_recorder()->allocate_metadata_index(obj);
3998 RelocationHolder rspec = metadata_Relocation::spec(index);
3999 return Address((address)obj, rspec);
4000 }
4001
4002 // Move an oop into a register. immediate is true if we want
4003 // immediate instrcutions, i.e. we are not going to patch this
4004 // instruction while the code is being executed by another thread. In
4005 // that case we can use move immediates rather than the constant pool.
4006 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
4007 int oop_index;
4008 if (obj == NULL) {
4009 oop_index = oop_recorder()->allocate_oop_index(obj);
4010 } else {
4011 #ifdef ASSERT
4012 {
4013 ThreadInVMfromUnknown tiv;
4014 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop");
4015 }
4016 #endif
4017 oop_index = oop_recorder()->find_index(obj);
4018 }
4019 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4020 if (! immediate) {
4021 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
4022 ldr_constant(dst, Address(dummy, rspec));
4023 } else
4024 mov(dst, Address((address)obj, rspec));
4025 }
4026
4027 // Move a metadata address into a register.
4028 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
4029 int oop_index;
4030 if (obj == NULL) {
4031 oop_index = oop_recorder()->allocate_metadata_index(obj);
4032 } else {
4033 oop_index = oop_recorder()->find_index(obj);
4034 }
4035 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4036 mov(dst, Address((address)obj, rspec));
4037 }
4038
4039 Address MacroAssembler::constant_oop_address(jobject obj) {
4040 #ifdef ASSERT
4041 {
4042 ThreadInVMfromUnknown tiv;
4043 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4044 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
4045 }
4046 #endif
4047 int oop_index = oop_recorder()->find_index(obj);
4048 return Address((address)obj, oop_Relocation::spec(oop_index));
4049 }
4050
4051 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4052 void MacroAssembler::tlab_allocate(Register obj,
4053 Register var_size_in_bytes,
4054 int con_size_in_bytes,
4055 Register t1,
4056 Register t2,
4057 Label& slow_case) {
4058 assert_different_registers(obj, t2);
4059 assert_different_registers(obj, var_size_in_bytes);
4060 Register end = t2;
4061
4062 // verify_tlab();
4063
4064 ldr(obj, Address(rthread, JavaThread::tlab_top_offset()));
4065 if (var_size_in_bytes == noreg) {
4066 lea(end, Address(obj, con_size_in_bytes));
4067 } else {
4068 lea(end, Address(obj, var_size_in_bytes));
4069 }
4070 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset()));
4071 cmp(end, rscratch1);
4072 br(Assembler::HI, slow_case);
4073
4074 // update the tlab top pointer
4075 str(end, Address(rthread, JavaThread::tlab_top_offset()));
4076
4077 // recover var_size_in_bytes if necessary
4078 if (var_size_in_bytes == end) {
4079 sub(var_size_in_bytes, var_size_in_bytes, obj);
4080 }
4081 // verify_tlab();
4082 }
4083
4084 // Zero words; len is in bytes
4085 // Destroys all registers except addr
4086 // len must be a nonzero multiple of wordSize
4087 void MacroAssembler::zero_memory(Register addr, Register len, Register t1) {
4088 assert_different_registers(addr, len, t1, rscratch1, rscratch2);
4089
4090 #ifdef ASSERT
4091 { Label L;
4092 tst(len, BytesPerWord - 1);
4093 br(Assembler::EQ, L);
4094 stop("len is not a multiple of BytesPerWord");
4095 bind(L);
4096 }
4097 #endif
4098
4099 #ifndef PRODUCT
4100 block_comment("zero memory");
4101 #endif
4102
4103 Label loop;
4104 Label entry;
4105
4106 // Algorithm:
4107 //
4108 // scratch1 = cnt & 7;
4109 // cnt -= scratch1;
4110 // p += scratch1;
4111 // switch (scratch1) {
4112 // do {
4113 // cnt -= 8;
4114 // p[-8] = 0;
4115 // case 7:
4116 // p[-7] = 0;
4117 // case 6:
4118 // p[-6] = 0;
4119 // // ...
4120 // case 1:
4121 // p[-1] = 0;
4122 // case 0:
4123 // p += 8;
4124 // } while (cnt);
4125 // }
4126
4127 const int unroll = 8; // Number of str(zr) instructions we'll unroll
4128
4129 lsr(len, len, LogBytesPerWord);
4130 andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll
4131 sub(len, len, rscratch1); // cnt -= unroll
4132 // t1 always points to the end of the region we're about to zero
4133 add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord);
4134 adr(rscratch2, entry);
4135 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2);
4136 br(rscratch2);
4137 bind(loop);
4138 sub(len, len, unroll);
4139 for (int i = -unroll; i < 0; i++)
4140 Assembler::str(zr, Address(t1, i * wordSize));
4141 bind(entry);
4142 add(t1, t1, unroll * wordSize);
4143 cbnz(len, loop);
4144 }
4145
4146 // Defines obj, preserves var_size_in_bytes
4147 void MacroAssembler::eden_allocate(Register obj,
4148 Register var_size_in_bytes,
4149 int con_size_in_bytes,
4150 Register t1,
4151 Label& slow_case) {
4152 assert_different_registers(obj, var_size_in_bytes, t1);
4153 if (!Universe::heap()->supports_inline_contig_alloc()) {
4154 b(slow_case);
4155 } else {
4156 Register end = t1;
4157 Register heap_end = rscratch2;
4158 Label retry;
4159 bind(retry);
4160 {
4161 unsigned long offset;
4162 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
4163 ldr(heap_end, Address(rscratch1, offset));
4164 }
4165
4166 ExternalAddress heap_top((address) Universe::heap()->top_addr());
4167
4168 // Get the current top of the heap
4169 {
4170 unsigned long offset;
4171 adrp(rscratch1, heap_top, offset);
4172 // Use add() here after ARDP, rather than lea().
4173 // lea() does not generate anything if its offset is zero.
4174 // However, relocs expect to find either an ADD or a load/store
4175 // insn after an ADRP. add() always generates an ADD insn, even
4176 // for add(Rn, Rn, 0).
4177 add(rscratch1, rscratch1, offset);
4178 ldaxr(obj, rscratch1);
4179 }
4180
4181 // Adjust it my the size of our new object
4182 if (var_size_in_bytes == noreg) {
4183 lea(end, Address(obj, con_size_in_bytes));
4184 } else {
4185 lea(end, Address(obj, var_size_in_bytes));
4186 }
4187
4188 // if end < obj then we wrapped around high memory
4189 cmp(end, obj);
4190 br(Assembler::LO, slow_case);
4191
4192 cmp(end, heap_end);
4193 br(Assembler::HI, slow_case);
4194
4195 // If heap_top hasn't been changed by some other thread, update it.
4196 stlxr(rscratch2, end, rscratch1);
4197 cbnzw(rscratch2, retry);
4198 }
4199 }
4200
4201 void MacroAssembler::verify_tlab() {
4202 #ifdef ASSERT
4203 if (UseTLAB && VerifyOops) {
4204 Label next, ok;
4205
4206 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4207
4208 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4209 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4210 cmp(rscratch2, rscratch1);
4211 br(Assembler::HS, next);
4212 STOP("assert(top >= start)");
4213 should_not_reach_here();
4214
4215 bind(next);
4216 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4217 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4218 cmp(rscratch2, rscratch1);
4219 br(Assembler::HS, ok);
4220 STOP("assert(top <= end)");
4221 should_not_reach_here();
4222
4223 bind(ok);
4224 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4225 }
4226 #endif
4227 }
4228
4229 // Writes to stack successive pages until offset reached to check for
4230 // stack overflow + shadow pages. This clobbers tmp.
4231 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4232 assert_different_registers(tmp, size, rscratch1);
4233 mov(tmp, sp);
4234 // Bang stack for total size given plus shadow page size.
4235 // Bang one page at a time because large size can bang beyond yellow and
4236 // red zones.
4237 Label loop;
4238 mov(rscratch1, os::vm_page_size());
4239 bind(loop);
4240 lea(tmp, Address(tmp, -os::vm_page_size()));
4241 subsw(size, size, rscratch1);
4242 str(size, Address(tmp));
4243 br(Assembler::GT, loop);
4244
4245 // Bang down shadow pages too.
4246 // At this point, (tmp-0) is the last address touched, so don't
4247 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4248 // was post-decremented.) Skip this address by starting at i=1, and
4249 // touch a few more pages below. N.B. It is important to touch all
4250 // the way down to and including i=StackShadowPages.
4251 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
4252 // this could be any sized move but this is can be a debugging crumb
4253 // so the bigger the better.
4254 lea(tmp, Address(tmp, -os::vm_page_size()));
4255 str(size, Address(tmp));
4256 }
4257 }
4258
4259
4260 // Move the address of the polling page into dest.
4261 void MacroAssembler::get_polling_page(Register dest, address page, relocInfo::relocType rtype) {
4262 if (SafepointMechanism::uses_thread_local_poll()) {
4263 ldr(dest, Address(rthread, Thread::polling_page_offset()));
4264 } else {
4265 unsigned long off;
4266 adrp(dest, Address(page, rtype), off);
4267 assert(off == 0, "polling page must be page aligned");
4268 }
4269 }
4270
4271 // Move the address of the polling page into r, then read the polling
4272 // page.
4273 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) {
4274 get_polling_page(r, page, rtype);
4275 return read_polling_page(r, rtype);
4276 }
4277
4278 // Read the polling page. The address of the polling page must
4279 // already be in r.
4280 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
4281 InstructionMark im(this);
4282 code_section()->relocate(inst_mark(), rtype);
4283 ldrw(zr, Address(r, 0));
4284 return inst_mark();
4285 }
4286
4287 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
4288 relocInfo::relocType rtype = dest.rspec().reloc()->type();
4289 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
4290 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
4291 unsigned long dest_page = (unsigned long)dest.target() >> 12;
4292 long offset_low = dest_page - low_page;
4293 long offset_high = dest_page - high_page;
4294
4295 assert(is_valid_AArch64_address(dest.target()), "bad address");
4296 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
4297
4298 InstructionMark im(this);
4299 code_section()->relocate(inst_mark(), dest.rspec());
4300 // 8143067: Ensure that the adrp can reach the dest from anywhere within
4301 // the code cache so that if it is relocated we know it will still reach
4302 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
4303 _adrp(reg1, dest.target());
4304 } else {
4305 unsigned long target = (unsigned long)dest.target();
4306 unsigned long adrp_target
4307 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
4308
4309 _adrp(reg1, (address)adrp_target);
4310 movk(reg1, target >> 32, 32);
4311 }
4312 byte_offset = (unsigned long)dest.target() & 0xfff;
4313 }
4314
4315 void MacroAssembler::load_byte_map_base(Register reg) {
4316 jbyte *byte_map_base =
4317 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
4318
4319 if (is_valid_AArch64_address((address)byte_map_base)) {
4320 // Strictly speaking the byte_map_base isn't an address at all,
4321 // and it might even be negative.
4322 unsigned long offset;
4323 adrp(reg, ExternalAddress((address)byte_map_base), offset);
4324 // We expect offset to be zero with most collectors.
4325 if (offset != 0) {
4326 add(reg, reg, offset);
4327 }
4328 } else {
4329 mov(reg, (uint64_t)byte_map_base);
4330 }
4331 }
4332
4333 void MacroAssembler::build_frame(int framesize) {
4334 assert(framesize > 0, "framesize must be > 0");
4335 if (framesize < ((1 << 9) + 2 * wordSize)) {
4336 sub(sp, sp, framesize);
4337 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4338 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
4339 } else {
4340 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
4341 if (PreserveFramePointer) mov(rfp, sp);
4342 if (framesize < ((1 << 12) + 2 * wordSize))
4343 sub(sp, sp, framesize - 2 * wordSize);
4344 else {
4345 mov(rscratch1, framesize - 2 * wordSize);
4346 sub(sp, sp, rscratch1);
4347 }
4348 }
4349 }
4350
4351 void MacroAssembler::remove_frame(int framesize) {
4352 assert(framesize > 0, "framesize must be > 0");
4353 if (framesize < ((1 << 9) + 2 * wordSize)) {
4354 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4355 add(sp, sp, framesize);
4356 } else {
4357 if (framesize < ((1 << 12) + 2 * wordSize))
4358 add(sp, sp, framesize - 2 * wordSize);
4359 else {
4360 mov(rscratch1, framesize - 2 * wordSize);
4361 add(sp, sp, rscratch1);
4362 }
4363 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4364 }
4365 }
4366
4367 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
4368
4369 // Search for str1 in str2 and return index or -1
4370 void MacroAssembler::string_indexof(Register str2, Register str1,
4371 Register cnt2, Register cnt1,
4372 Register tmp1, Register tmp2,
4373 Register tmp3, Register tmp4,
4374 int icnt1, Register result, int ae) {
4375 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH;
4376
4377 Register ch1 = rscratch1;
4378 Register ch2 = rscratch2;
4379 Register cnt1tmp = tmp1;
4380 Register cnt2tmp = tmp2;
4381 Register cnt1_neg = cnt1;
4382 Register cnt2_neg = cnt2;
4383 Register result_tmp = tmp4;
4384
4385 bool isL = ae == StrIntrinsicNode::LL;
4386
4387 bool str1_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL;
4388 bool str2_isL = ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::LU;
4389 int str1_chr_shift = str1_isL ? 0:1;
4390 int str2_chr_shift = str2_isL ? 0:1;
4391 int str1_chr_size = str1_isL ? 1:2;
4392 int str2_chr_size = str2_isL ? 1:2;
4393 chr_insn str1_load_1chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb :
4394 (chr_insn)&MacroAssembler::ldrh;
4395 chr_insn str2_load_1chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb :
4396 (chr_insn)&MacroAssembler::ldrh;
4397 chr_insn load_2chr = isL ? (chr_insn)&MacroAssembler::ldrh : (chr_insn)&MacroAssembler::ldrw;
4398 chr_insn load_4chr = isL ? (chr_insn)&MacroAssembler::ldrw : (chr_insn)&MacroAssembler::ldr;
4399
4400 // Note, inline_string_indexOf() generates checks:
4401 // if (substr.count > string.count) return -1;
4402 // if (substr.count == 0) return 0;
4403
4404 // We have two strings, a source string in str2, cnt2 and a pattern string
4405 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
4406
4407 // For larger pattern and source we use a simplified Boyer Moore algorithm.
4408 // With a small pattern and source we use linear scan.
4409
4410 if (icnt1 == -1) {
4411 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256
4412 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use
4413 br(LO, LINEARSEARCH); // a byte array.
4414 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM
4415 br(HS, LINEARSEARCH);
4416 }
4417
4418 // The Boyer Moore alogorithm is based on the description here:-
4419 //
4420 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm
4421 //
4422 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule
4423 // and the 'Good Suffix' rule.
4424 //
4425 // These rules are essentially heuristics for how far we can shift the
4426 // pattern along the search string.
4427 //
4428 // The implementation here uses the 'Bad Character' rule only because of the
4429 // complexity of initialisation for the 'Good Suffix' rule.
4430 //
4431 // This is also known as the Boyer-Moore-Horspool algorithm:-
4432 //
4433 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm
4434 //
4435 // #define ASIZE 128
4436 //
4437 // int bm(unsigned char *x, int m, unsigned char *y, int n) {
4438 // int i, j;
4439 // unsigned c;
4440 // unsigned char bc[ASIZE];
4441 //
4442 // /* Preprocessing */
4443 // for (i = 0; i < ASIZE; ++i)
4444 // bc[i] = 0;
4445 // for (i = 0; i < m - 1; ) {
4446 // c = x[i];
4447 // ++i;
4448 // if (c < ASIZE) bc[c] = i;
4449 // }
4450 //
4451 // /* Searching */
4452 // j = 0;
4453 // while (j <= n - m) {
4454 // c = y[i+j];
4455 // if (x[m-1] == c)
4456 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i);
4457 // if (i < 0) return j;
4458 // if (c < ASIZE)
4459 // j = j - bc[y[j+m-1]] + m;
4460 // else
4461 // j += 1; // Advance by 1 only if char >= ASIZE
4462 // }
4463 // }
4464
4465 if (icnt1 == -1) {
4466 BIND(BM);
4467
4468 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP;
4469 Label BMADV, BMMATCH, BMCHECKEND;
4470
4471 Register cnt1end = tmp2;
4472 Register str2end = cnt2;
4473 Register skipch = tmp2;
4474
4475 // Restrict ASIZE to 128 to reduce stack space/initialisation.
4476 // The presence of chars >= ASIZE in the target string does not affect
4477 // performance, but we must be careful not to initialise them in the stack
4478 // array.
4479 // The presence of chars >= ASIZE in the source string may adversely affect
4480 // performance since we can only advance by one when we encounter one.
4481
4482 stp(zr, zr, pre(sp, -128));
4483 for (int i = 1; i < 8; i++)
4484 stp(zr, zr, Address(sp, i*16));
4485
4486 mov(cnt1tmp, 0);
4487 sub(cnt1end, cnt1, 1);
4488 BIND(BCLOOP);
4489 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4490 cmp(ch1, 128);
4491 add(cnt1tmp, cnt1tmp, 1);
4492 br(HS, BCSKIP);
4493 strb(cnt1tmp, Address(sp, ch1));
4494 BIND(BCSKIP);
4495 cmp(cnt1tmp, cnt1end);
4496 br(LT, BCLOOP);
4497
4498 mov(result_tmp, str2);
4499
4500 sub(cnt2, cnt2, cnt1);
4501 add(str2end, str2, cnt2, LSL, str2_chr_shift);
4502 BIND(BMLOOPSTR2);
4503 sub(cnt1tmp, cnt1, 1);
4504 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4505 (this->*str2_load_1chr)(skipch, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift)));
4506 cmp(ch1, skipch);
4507 br(NE, BMSKIP);
4508 subs(cnt1tmp, cnt1tmp, 1);
4509 br(LT, BMMATCH);
4510 BIND(BMLOOPSTR1);
4511 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp, Address::lsl(str1_chr_shift)));
4512 (this->*str2_load_1chr)(ch2, Address(str2, cnt1tmp, Address::lsl(str2_chr_shift)));
4513 cmp(ch1, ch2);
4514 br(NE, BMSKIP);
4515 subs(cnt1tmp, cnt1tmp, 1);
4516 br(GE, BMLOOPSTR1);
4517 BIND(BMMATCH);
4518 sub(result, str2, result_tmp);
4519 if (!str2_isL) lsr(result, result, 1);
4520 add(sp, sp, 128);
4521 b(DONE);
4522 BIND(BMADV);
4523 add(str2, str2, str2_chr_size);
4524 b(BMCHECKEND);
4525 BIND(BMSKIP);
4526 cmp(skipch, 128);
4527 br(HS, BMADV);
4528 ldrb(ch2, Address(sp, skipch));
4529 add(str2, str2, cnt1, LSL, str2_chr_shift);
4530 sub(str2, str2, ch2, LSL, str2_chr_shift);
4531 BIND(BMCHECKEND);
4532 cmp(str2, str2end);
4533 br(LE, BMLOOPSTR2);
4534 add(sp, sp, 128);
4535 b(NOMATCH);
4536 }
4537
4538 BIND(LINEARSEARCH);
4539 {
4540 Label DO1, DO2, DO3;
4541
4542 Register str2tmp = tmp2;
4543 Register first = tmp3;
4544
4545 if (icnt1 == -1)
4546 {
4547 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT;
4548
4549 cmp(cnt1, str1_isL == str2_isL ? 4 : 2);
4550 br(LT, DOSHORT);
4551
4552 sub(cnt2, cnt2, cnt1);
4553 mov(result_tmp, cnt2);
4554
4555 lea(str1, Address(str1, cnt1, Address::lsl(str1_chr_shift)));
4556 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4557 sub(cnt1_neg, zr, cnt1, LSL, str1_chr_shift);
4558 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4559 (this->*str1_load_1chr)(first, Address(str1, cnt1_neg));
4560
4561 BIND(FIRST_LOOP);
4562 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg));
4563 cmp(first, ch2);
4564 br(EQ, STR1_LOOP);
4565 BIND(STR2_NEXT);
4566 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4567 br(LE, FIRST_LOOP);
4568 b(NOMATCH);
4569
4570 BIND(STR1_LOOP);
4571 adds(cnt1tmp, cnt1_neg, str1_chr_size);
4572 add(cnt2tmp, cnt2_neg, str2_chr_size);
4573 br(GE, MATCH);
4574
4575 BIND(STR1_NEXT);
4576 (this->*str1_load_1chr)(ch1, Address(str1, cnt1tmp));
4577 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp));
4578 cmp(ch1, ch2);
4579 br(NE, STR2_NEXT);
4580 adds(cnt1tmp, cnt1tmp, str1_chr_size);
4581 add(cnt2tmp, cnt2tmp, str2_chr_size);
4582 br(LT, STR1_NEXT);
4583 b(MATCH);
4584
4585 BIND(DOSHORT);
4586 if (str1_isL == str2_isL) {
4587 cmp(cnt1, 2);
4588 br(LT, DO1);
4589 br(GT, DO3);
4590 }
4591 }
4592
4593 if (icnt1 == 4) {
4594 Label CH1_LOOP;
4595
4596 (this->*load_4chr)(ch1, str1);
4597 sub(cnt2, cnt2, 4);
4598 mov(result_tmp, cnt2);
4599 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4600 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4601
4602 BIND(CH1_LOOP);
4603 (this->*load_4chr)(ch2, Address(str2, cnt2_neg));
4604 cmp(ch1, ch2);
4605 br(EQ, MATCH);
4606 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4607 br(LE, CH1_LOOP);
4608 b(NOMATCH);
4609 }
4610
4611 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 2) {
4612 Label CH1_LOOP;
4613
4614 BIND(DO2);
4615 (this->*load_2chr)(ch1, str1);
4616 sub(cnt2, cnt2, 2);
4617 mov(result_tmp, cnt2);
4618 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4619 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4620
4621 BIND(CH1_LOOP);
4622 (this->*load_2chr)(ch2, Address(str2, cnt2_neg));
4623 cmp(ch1, ch2);
4624 br(EQ, MATCH);
4625 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4626 br(LE, CH1_LOOP);
4627 b(NOMATCH);
4628 }
4629
4630 if ((icnt1 == -1 && str1_isL == str2_isL) || icnt1 == 3) {
4631 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP;
4632
4633 BIND(DO3);
4634 (this->*load_2chr)(first, str1);
4635 (this->*str1_load_1chr)(ch1, Address(str1, 2*str1_chr_size));
4636
4637 sub(cnt2, cnt2, 3);
4638 mov(result_tmp, cnt2);
4639 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4640 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4641
4642 BIND(FIRST_LOOP);
4643 (this->*load_2chr)(ch2, Address(str2, cnt2_neg));
4644 cmpw(first, ch2);
4645 br(EQ, STR1_LOOP);
4646 BIND(STR2_NEXT);
4647 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4648 br(LE, FIRST_LOOP);
4649 b(NOMATCH);
4650
4651 BIND(STR1_LOOP);
4652 add(cnt2tmp, cnt2_neg, 2*str2_chr_size);
4653 (this->*str2_load_1chr)(ch2, Address(str2, cnt2tmp));
4654 cmp(ch1, ch2);
4655 br(NE, STR2_NEXT);
4656 b(MATCH);
4657 }
4658
4659 if (icnt1 == -1 || icnt1 == 1) {
4660 Label CH1_LOOP, HAS_ZERO;
4661 Label DO1_SHORT, DO1_LOOP;
4662
4663 BIND(DO1);
4664 (this->*str1_load_1chr)(ch1, str1);
4665 cmp(cnt2, 8);
4666 br(LT, DO1_SHORT);
4667
4668 if (str2_isL) {
4669 if (!str1_isL) {
4670 tst(ch1, 0xff00);
4671 br(NE, NOMATCH);
4672 }
4673 orr(ch1, ch1, ch1, LSL, 8);
4674 }
4675 orr(ch1, ch1, ch1, LSL, 16);
4676 orr(ch1, ch1, ch1, LSL, 32);
4677
4678 sub(cnt2, cnt2, 8/str2_chr_size);
4679 mov(result_tmp, cnt2);
4680 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4681 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4682
4683 mov(tmp3, str2_isL ? 0x0101010101010101 : 0x0001000100010001);
4684 BIND(CH1_LOOP);
4685 ldr(ch2, Address(str2, cnt2_neg));
4686 eor(ch2, ch1, ch2);
4687 sub(tmp1, ch2, tmp3);
4688 orr(tmp2, ch2, str2_isL ? 0x7f7f7f7f7f7f7f7f : 0x7fff7fff7fff7fff);
4689 bics(tmp1, tmp1, tmp2);
4690 br(NE, HAS_ZERO);
4691 adds(cnt2_neg, cnt2_neg, 8);
4692 br(LT, CH1_LOOP);
4693
4694 cmp(cnt2_neg, 8);
4695 mov(cnt2_neg, 0);
4696 br(LT, CH1_LOOP);
4697 b(NOMATCH);
4698
4699 BIND(HAS_ZERO);
4700 rev(tmp1, tmp1);
4701 clz(tmp1, tmp1);
4702 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3);
4703 b(MATCH);
4704
4705 BIND(DO1_SHORT);
4706 mov(result_tmp, cnt2);
4707 lea(str2, Address(str2, cnt2, Address::lsl(str2_chr_shift)));
4708 sub(cnt2_neg, zr, cnt2, LSL, str2_chr_shift);
4709 BIND(DO1_LOOP);
4710 (this->*str2_load_1chr)(ch2, Address(str2, cnt2_neg));
4711 cmpw(ch1, ch2);
4712 br(EQ, MATCH);
4713 adds(cnt2_neg, cnt2_neg, str2_chr_size);
4714 br(LT, DO1_LOOP);
4715 }
4716 }
4717 BIND(NOMATCH);
4718 mov(result, -1);
4719 b(DONE);
4720 BIND(MATCH);
4721 add(result, result_tmp, cnt2_neg, ASR, str2_chr_shift);
4722 BIND(DONE);
4723 }
4724
4725 typedef void (MacroAssembler::* chr_insn)(Register Rt, const Address &adr);
4726 typedef void (MacroAssembler::* uxt_insn)(Register Rd, Register Rn);
4727
4728 void MacroAssembler::string_indexof_char(Register str1, Register cnt1,
4729 Register ch, Register result,
4730 Register tmp1, Register tmp2, Register tmp3)
4731 {
4732 Label CH1_LOOP, HAS_ZERO, DO1_SHORT, DO1_LOOP, MATCH, NOMATCH, DONE;
4733 Register cnt1_neg = cnt1;
4734 Register ch1 = rscratch1;
4735 Register result_tmp = rscratch2;
4736
4737 cmp(cnt1, 4);
4738 br(LT, DO1_SHORT);
4739
4740 orr(ch, ch, ch, LSL, 16);
4741 orr(ch, ch, ch, LSL, 32);
4742
4743 sub(cnt1, cnt1, 4);
4744 mov(result_tmp, cnt1);
4745 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4746 sub(cnt1_neg, zr, cnt1, LSL, 1);
4747
4748 mov(tmp3, 0x0001000100010001);
4749
4750 BIND(CH1_LOOP);
4751 ldr(ch1, Address(str1, cnt1_neg));
4752 eor(ch1, ch, ch1);
4753 sub(tmp1, ch1, tmp3);
4754 orr(tmp2, ch1, 0x7fff7fff7fff7fff);
4755 bics(tmp1, tmp1, tmp2);
4756 br(NE, HAS_ZERO);
4757 adds(cnt1_neg, cnt1_neg, 8);
4758 br(LT, CH1_LOOP);
4759
4760 cmp(cnt1_neg, 8);
4761 mov(cnt1_neg, 0);
4762 br(LT, CH1_LOOP);
4763 b(NOMATCH);
4764
4765 BIND(HAS_ZERO);
4766 rev(tmp1, tmp1);
4767 clz(tmp1, tmp1);
4768 add(cnt1_neg, cnt1_neg, tmp1, LSR, 3);
4769 b(MATCH);
4770
4771 BIND(DO1_SHORT);
4772 mov(result_tmp, cnt1);
4773 lea(str1, Address(str1, cnt1, Address::uxtw(1)));
4774 sub(cnt1_neg, zr, cnt1, LSL, 1);
4775 BIND(DO1_LOOP);
4776 ldrh(ch1, Address(str1, cnt1_neg));
4777 cmpw(ch, ch1);
4778 br(EQ, MATCH);
4779 adds(cnt1_neg, cnt1_neg, 2);
4780 br(LT, DO1_LOOP);
4781 BIND(NOMATCH);
4782 mov(result, -1);
4783 b(DONE);
4784 BIND(MATCH);
4785 add(result, result_tmp, cnt1_neg, ASR, 1);
4786 BIND(DONE);
4787 }
4788
4789 // Compare strings.
4790 void MacroAssembler::string_compare(Register str1, Register str2,
4791 Register cnt1, Register cnt2, Register result,
4792 Register tmp1,
4793 FloatRegister vtmp, FloatRegister vtmpZ, int ae) {
4794 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING,
4795 NEXT_WORD, DIFFERENCE;
4796
4797 bool isLL = ae == StrIntrinsicNode::LL;
4798 bool isLU = ae == StrIntrinsicNode::LU;
4799 bool isUL = ae == StrIntrinsicNode::UL;
4800
4801 bool str1_isL = isLL || isLU;
4802 bool str2_isL = isLL || isUL;
4803
4804 int str1_chr_shift = str1_isL ? 0 : 1;
4805 int str2_chr_shift = str2_isL ? 0 : 1;
4806 int str1_chr_size = str1_isL ? 1 : 2;
4807 int str2_chr_size = str2_isL ? 1 : 2;
4808
4809 chr_insn str1_load_chr = str1_isL ? (chr_insn)&MacroAssembler::ldrb :
4810 (chr_insn)&MacroAssembler::ldrh;
4811 chr_insn str2_load_chr = str2_isL ? (chr_insn)&MacroAssembler::ldrb :
4812 (chr_insn)&MacroAssembler::ldrh;
4813 uxt_insn ext_chr = isLL ? (uxt_insn)&MacroAssembler::uxtbw :
4814 (uxt_insn)&MacroAssembler::uxthw;
4815
4816 BLOCK_COMMENT("string_compare {");
4817
4818 // Bizzarely, the counts are passed in bytes, regardless of whether they
4819 // are L or U strings, however the result is always in characters.
4820 if (!str1_isL) asrw(cnt1, cnt1, 1);
4821 if (!str2_isL) asrw(cnt2, cnt2, 1);
4822
4823 // Compute the minimum of the string lengths and save the difference.
4824 subsw(tmp1, cnt1, cnt2);
4825 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min
4826
4827 // A very short string
4828 cmpw(cnt2, isLL ? 8:4);
4829 br(Assembler::LT, SHORT_STRING);
4830
4831 // Check if the strings start at the same location.
4832 cmp(str1, str2);
4833 br(Assembler::EQ, LENGTH_DIFF);
4834
4835 // Compare longwords
4836 {
4837 subw(cnt2, cnt2, isLL ? 8:4); // The last longword is a special case
4838
4839 // Move both string pointers to the last longword of their
4840 // strings, negate the remaining count, and convert it to bytes.
4841 lea(str1, Address(str1, cnt2, Address::uxtw(str1_chr_shift)));
4842 lea(str2, Address(str2, cnt2, Address::uxtw(str2_chr_shift)));
4843 if (isLU || isUL) {
4844 sub(cnt1, zr, cnt2, LSL, str1_chr_shift);
4845 eor(vtmpZ, T16B, vtmpZ, vtmpZ);
4846 }
4847 sub(cnt2, zr, cnt2, LSL, str2_chr_shift);
4848
4849 // Loop, loading longwords and comparing them into rscratch2.
4850 bind(NEXT_WORD);
4851 if (isLU) {
4852 ldrs(vtmp, Address(str1, cnt1));
4853 zip1(vtmp, T8B, vtmp, vtmpZ);
4854 umov(result, vtmp, D, 0);
4855 } else {
4856 ldr(result, Address(str1, isUL ? cnt1:cnt2));
4857 }
4858 if (isUL) {
4859 ldrs(vtmp, Address(str2, cnt2));
4860 zip1(vtmp, T8B, vtmp, vtmpZ);
4861 umov(rscratch1, vtmp, D, 0);
4862 } else {
4863 ldr(rscratch1, Address(str2, cnt2));
4864 }
4865 adds(cnt2, cnt2, isUL ? 4:8);
4866 if (isLU || isUL) add(cnt1, cnt1, isLU ? 4:8);
4867 eor(rscratch2, result, rscratch1);
4868 cbnz(rscratch2, DIFFERENCE);
4869 br(Assembler::LT, NEXT_WORD);
4870
4871 // Last longword. In the case where length == 4 we compare the
4872 // same longword twice, but that's still faster than another
4873 // conditional branch.
4874
4875 if (isLU) {
4876 ldrs(vtmp, Address(str1));
4877 zip1(vtmp, T8B, vtmp, vtmpZ);
4878 umov(result, vtmp, D, 0);
4879 } else {
4880 ldr(result, Address(str1));
4881 }
4882 if (isUL) {
4883 ldrs(vtmp, Address(str2));
4884 zip1(vtmp, T8B, vtmp, vtmpZ);
4885 umov(rscratch1, vtmp, D, 0);
4886 } else {
4887 ldr(rscratch1, Address(str2));
4888 }
4889 eor(rscratch2, result, rscratch1);
4890 cbz(rscratch2, LENGTH_DIFF);
4891
4892 // Find the first different characters in the longwords and
4893 // compute their difference.
4894 bind(DIFFERENCE);
4895 rev(rscratch2, rscratch2);
4896 clz(rscratch2, rscratch2);
4897 andr(rscratch2, rscratch2, isLL ? -8 : -16);
4898 lsrv(result, result, rscratch2);
4899 (this->*ext_chr)(result, result);
4900 lsrv(rscratch1, rscratch1, rscratch2);
4901 (this->*ext_chr)(rscratch1, rscratch1);
4902 subw(result, result, rscratch1);
4903 b(DONE);
4904 }
4905
4906 bind(SHORT_STRING);
4907 // Is the minimum length zero?
4908 cbz(cnt2, LENGTH_DIFF);
4909
4910 bind(SHORT_LOOP);
4911 (this->*str1_load_chr)(result, Address(post(str1, str1_chr_size)));
4912 (this->*str2_load_chr)(cnt1, Address(post(str2, str2_chr_size)));
4913 subw(result, result, cnt1);
4914 cbnz(result, DONE);
4915 sub(cnt2, cnt2, 1);
4916 cbnz(cnt2, SHORT_LOOP);
4917
4918 // Strings are equal up to min length. Return the length difference.
4919 bind(LENGTH_DIFF);
4920 mov(result, tmp1);
4921
4922 // That's it
4923 bind(DONE);
4924
4925 BLOCK_COMMENT("} string_compare");
4926 }
4927
4928 // This method checks if provided byte array contains byte with highest bit set.
4929 void MacroAssembler::has_negatives(Register ary1, Register len, Register result) {
4930 // Simple and most common case of aligned small array which is not at the
4931 // end of memory page is placed here. All other cases are in stub.
4932 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
4933 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
4934 assert_different_registers(ary1, len, result);
4935
4936 cmpw(len, 0);
4937 br(LE, SET_RESULT);
4938 cmpw(len, 4 * wordSize);
4939 br(GE, STUB_LONG); // size > 32 then go to stub
4940
4941 int shift = 64 - exact_log2(os::vm_page_size());
4942 lsl(rscratch1, ary1, shift);
4943 mov(rscratch2, (size_t)(4 * wordSize) << shift);
4944 adds(rscratch2, rscratch1, rscratch2); // At end of page?
4945 br(CS, STUB); // at the end of page then go to stub
4946 subs(len, len, wordSize);
4947 br(LT, END);
4948
4949 BIND(LOOP);
4950 ldr(rscratch1, Address(post(ary1, wordSize)));
4951 tst(rscratch1, UPPER_BIT_MASK);
4952 br(NE, SET_RESULT);
4953 subs(len, len, wordSize);
4954 br(GE, LOOP);
4955 cmpw(len, -wordSize);
4956 br(EQ, SET_RESULT);
4957
4958 BIND(END);
4959 ldr(result, Address(ary1));
4960 sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
4961 lslv(result, result, len);
4962 tst(result, UPPER_BIT_MASK);
4963 b(SET_RESULT);
4964
4965 BIND(STUB);
4966 RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives());
4967 assert(has_neg.target() != NULL, "has_negatives stub has not been generated");
4968 trampoline_call(has_neg);
4969 b(DONE);
4970
4971 BIND(STUB_LONG);
4972 RuntimeAddress has_neg_long = RuntimeAddress(
4973 StubRoutines::aarch64::has_negatives_long());
4974 assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated");
4975 trampoline_call(has_neg_long);
4976 b(DONE);
4977
4978 BIND(SET_RESULT);
4979 cset(result, NE); // set true or false
4980
4981 BIND(DONE);
4982 }
4983
4984 void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
4985 Register tmp4, Register tmp5, Register result,
4986 Register cnt1, int elem_size)
4987 {
4988 Label DONE;
4989 Register tmp1 = rscratch1;
4990 Register tmp2 = rscratch2;
4991 Register cnt2 = tmp2; // cnt2 only used in array length compare
4992 int elem_per_word = wordSize/elem_size;
4993 int log_elem_size = exact_log2(elem_size);
4994 int length_offset = arrayOopDesc::length_offset_in_bytes();
4995 int base_offset
4996 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
4997 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
4998
4999 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5000 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5001
5002 #ifndef PRODUCT
5003 {
5004 const char kind = (elem_size == 2) ? 'U' : 'L';
5005 char comment[64];
5006 snprintf(comment, sizeof comment, "array_equals%c{", kind);
5007 BLOCK_COMMENT(comment);
5008 }
5009 #endif
5010 if (UseSimpleArrayEquals) {
5011 Label NEXT_WORD, SHORT, SAME, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5012 // if (a1==a2)
5013 // return true;
5014 // if (a==null || a2==null)
5015 // return false;
5016 // a1 & a2 == 0 means (some-pointer is null) or
5017 // (very-rare-or-even-probably-impossible-pointer-values)
5018 // so, we can save one branch in most cases
5019 eor(rscratch1, a1, a2);
5020 tst(a1, a2);
5021 mov(result, false);
5022 cbz(rscratch1, SAME);
5023 br(EQ, A_MIGHT_BE_NULL);
5024 // if (a1.length != a2.length)
5025 // return false;
5026 bind(A_IS_NOT_NULL);
5027 ldrw(cnt1, Address(a1, length_offset));
5028 ldrw(cnt2, Address(a2, length_offset));
5029 eorw(tmp5, cnt1, cnt2);
5030 cbnzw(tmp5, DONE);
5031 lea(a1, Address(a1, base_offset));
5032 lea(a2, Address(a2, base_offset));
5033 // Check for short strings, i.e. smaller than wordSize.
5034 subs(cnt1, cnt1, elem_per_word);
5035 br(Assembler::LT, SHORT);
5036 // Main 8 byte comparison loop.
5037 bind(NEXT_WORD); {
5038 ldr(tmp1, Address(post(a1, wordSize)));
5039 ldr(tmp2, Address(post(a2, wordSize)));
5040 subs(cnt1, cnt1, elem_per_word);
5041 eor(tmp5, tmp1, tmp2);
5042 cbnz(tmp5, DONE);
5043 } br(GT, NEXT_WORD);
5044 // Last longword. In the case where length == 4 we compare the
5045 // same longword twice, but that's still faster than another
5046 // conditional branch.
5047 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5048 // length == 4.
5049 if (log_elem_size > 0)
5050 lsl(cnt1, cnt1, log_elem_size);
5051 ldr(tmp3, Address(a1, cnt1));
5052 ldr(tmp4, Address(a2, cnt1));
5053 eor(tmp5, tmp3, tmp4);
5054 cbnz(tmp5, DONE);
5055 b(SAME);
5056 bind(A_MIGHT_BE_NULL);
5057 // in case both a1 and a2 are not-null, proceed with loads
5058 cbz(a1, DONE);
5059 cbz(a2, DONE);
5060 b(A_IS_NOT_NULL);
5061 bind(SHORT);
5062
5063 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5064 {
5065 ldrw(tmp1, Address(post(a1, 4)));
5066 ldrw(tmp2, Address(post(a2, 4)));
5067 eorw(tmp5, tmp1, tmp2);
5068 cbnzw(tmp5, DONE);
5069 }
5070 bind(TAIL03);
5071 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5072 {
5073 ldrh(tmp3, Address(post(a1, 2)));
5074 ldrh(tmp4, Address(post(a2, 2)));
5075 eorw(tmp5, tmp3, tmp4);
5076 cbnzw(tmp5, DONE);
5077 }
5078 bind(TAIL01);
5079 if (elem_size == 1) { // Only needed when comparing byte arrays.
5080 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5081 {
5082 ldrb(tmp1, a1);
5083 ldrb(tmp2, a2);
5084 eorw(tmp5, tmp1, tmp2);
5085 cbnzw(tmp5, DONE);
5086 }
5087 }
5088 bind(SAME);
5089 mov(result, true);
5090 } else {
5091 Label NEXT_DWORD, A_IS_NULL, SHORT, TAIL, TAIL2, STUB, EARLY_OUT,
5092 CSET_EQ, LAST_CHECK, LEN_IS_ZERO, SAME;
5093 cbz(a1, A_IS_NULL);
5094 ldrw(cnt1, Address(a1, length_offset));
5095 cbz(a2, A_IS_NULL);
5096 ldrw(cnt2, Address(a2, length_offset));
5097 mov(result, false);
5098 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5099 // faster to perform another branch before comparing a1 and a2
5100 cmp(cnt1, elem_per_word);
5101 br(LE, SHORT); // short or same
5102 cmp(a1, a2);
5103 br(EQ, SAME);
5104 ldr(tmp3, Address(pre(a1, base_offset)));
5105 cmp(cnt1, stubBytesThreshold);
5106 br(GE, STUB);
5107 ldr(tmp4, Address(pre(a2, base_offset)));
5108 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5109 cmp(cnt2, cnt1);
5110 br(NE, DONE);
5111
5112 // Main 16 byte comparison loop with 2 exits
5113 bind(NEXT_DWORD); {
5114 ldr(tmp1, Address(pre(a1, wordSize)));
5115 ldr(tmp2, Address(pre(a2, wordSize)));
5116 subs(cnt1, cnt1, 2 * elem_per_word);
5117 br(LE, TAIL);
5118 eor(tmp4, tmp3, tmp4);
5119 cbnz(tmp4, DONE);
5120 ldr(tmp3, Address(pre(a1, wordSize)));
5121 ldr(tmp4, Address(pre(a2, wordSize)));
5122 cmp(cnt1, elem_per_word);
5123 br(LE, TAIL2);
5124 cmp(tmp1, tmp2);
5125 } br(EQ, NEXT_DWORD);
5126 b(DONE);
5127
5128 bind(TAIL);
5129 eor(tmp4, tmp3, tmp4);
5130 eor(tmp2, tmp1, tmp2);
5131 lslv(tmp2, tmp2, tmp5);
5132 orr(tmp5, tmp4, tmp2);
5133 cmp(tmp5, zr);
5134 b(CSET_EQ);
5135
5136 bind(TAIL2);
5137 eor(tmp2, tmp1, tmp2);
5138 cbnz(tmp2, DONE);
5139 b(LAST_CHECK);
5140
5141 bind(STUB);
5142 ldr(tmp4, Address(pre(a2, base_offset)));
5143 cmp(cnt2, cnt1);
5144 br(NE, DONE);
5145 if (elem_size == 2) { // convert to byte counter
5146 lsl(cnt1, cnt1, 1);
5147 }
5148 eor(tmp5, tmp3, tmp4);
5149 cbnz(tmp5, DONE);
5150 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
5151 assert(stub.target() != NULL, "array_equals_long stub has not been generated");
5152 trampoline_call(stub);
5153 b(DONE);
5154
5155 bind(SAME);
5156 mov(result, true);
5157 b(DONE);
5158 bind(A_IS_NULL);
5159 // a1 or a2 is null. if a2 == a2 then return true. else return false
5160 cmp(a1, a2);
5161 b(CSET_EQ);
5162 bind(EARLY_OUT);
5163 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
5164 // so, if a2 == null => return false(0), else return true, so we can return a2
5165 mov(result, a2);
5166 b(DONE);
5167 bind(LEN_IS_ZERO);
5168 cmp(cnt2, zr);
5169 b(CSET_EQ);
5170 bind(SHORT);
5171 cbz(cnt1, LEN_IS_ZERO);
5172 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5173 ldr(tmp3, Address(a1, base_offset));
5174 ldr(tmp4, Address(a2, base_offset));
5175 bind(LAST_CHECK);
5176 eor(tmp4, tmp3, tmp4);
5177 lslv(tmp5, tmp4, tmp5);
5178 cmp(tmp5, zr);
5179 bind(CSET_EQ);
5180 cset(result, EQ);
5181 }
5182
5183 // That's it.
5184 bind(DONE);
5185
5186 BLOCK_COMMENT("} array_equals");
5187 }
5188
5189 // Compare Strings
5190
5191 // For Strings we're passed the address of the first characters in a1
5192 // and a2 and the length in cnt1.
5193 // elem_size is the element size in bytes: either 1 or 2.
5194 // There are two implementations. For arrays >= 8 bytes, all
5195 // comparisons (including the final one, which may overlap) are
5196 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
5197 // halfword, then a short, and then a byte.
5198
5199 void MacroAssembler::string_equals(Register a1, Register a2,
5200 Register result, Register cnt1, int elem_size)
5201 {
5202 Label SAME, DONE, SHORT, NEXT_WORD;
5203 Register tmp1 = rscratch1;
5204 Register tmp2 = rscratch2;
5205 Register cnt2 = tmp2; // cnt2 only used in array length compare
5206
5207 assert(elem_size == 1 || elem_size == 2, "must be 2 or 1 byte");
5208 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5209
5210 #ifndef PRODUCT
5211 {
5212 const char kind = (elem_size == 2) ? 'U' : 'L';
5213 char comment[64];
5214 snprintf(comment, sizeof comment, "{string_equals%c", kind);
5215 BLOCK_COMMENT(comment);
5216 }
5217 #endif
5218
5219 mov(result, false);
5220
5221 // Check for short strings, i.e. smaller than wordSize.
5222 subs(cnt1, cnt1, wordSize);
5223 br(Assembler::LT, SHORT);
5224 // Main 8 byte comparison loop.
5225 bind(NEXT_WORD); {
5226 ldr(tmp1, Address(post(a1, wordSize)));
5227 ldr(tmp2, Address(post(a2, wordSize)));
5228 subs(cnt1, cnt1, wordSize);
5229 eor(tmp1, tmp1, tmp2);
5230 cbnz(tmp1, DONE);
5231 } br(GT, NEXT_WORD);
5232 // Last longword. In the case where length == 4 we compare the
5233 // same longword twice, but that's still faster than another
5234 // conditional branch.
5235 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5236 // length == 4.
5237 ldr(tmp1, Address(a1, cnt1));
5238 ldr(tmp2, Address(a2, cnt1));
5239 eor(tmp2, tmp1, tmp2);
5240 cbnz(tmp2, DONE);
5241 b(SAME);
5242
5243 bind(SHORT);
5244 Label TAIL03, TAIL01;
5245
5246 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
5247 {
5248 ldrw(tmp1, Address(post(a1, 4)));
5249 ldrw(tmp2, Address(post(a2, 4)));
5250 eorw(tmp1, tmp1, tmp2);
5251 cbnzw(tmp1, DONE);
5252 }
5253 bind(TAIL03);
5254 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
5255 {
5256 ldrh(tmp1, Address(post(a1, 2)));
5257 ldrh(tmp2, Address(post(a2, 2)));
5258 eorw(tmp1, tmp1, tmp2);
5259 cbnzw(tmp1, DONE);
5260 }
5261 bind(TAIL01);
5262 if (elem_size == 1) { // Only needed when comparing 1-byte elements
5263 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5264 {
5265 ldrb(tmp1, a1);
5266 ldrb(tmp2, a2);
5267 eorw(tmp1, tmp1, tmp2);
5268 cbnzw(tmp1, DONE);
5269 }
5270 }
5271 // Arrays are equal.
5272 bind(SAME);
5273 mov(result, true);
5274
5275 // That's it.
5276 bind(DONE);
5277 BLOCK_COMMENT("} string_equals");
5278 }
5279
5280
5281 // The size of the blocks erased by the zero_blocks stub. We must
5282 // handle anything smaller than this ourselves in zero_words().
5283 const int MacroAssembler::zero_words_block_size = 8;
5284
5285 // zero_words() is used by C2 ClearArray patterns. It is as small as
5286 // possible, handling small word counts locally and delegating
5287 // anything larger to the zero_blocks stub. It is expanded many times
5288 // in compiled code, so it is important to keep it short.
5289
5290 // ptr: Address of a buffer to be zeroed.
5291 // cnt: Count in HeapWords.
5292 //
5293 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
5294 void MacroAssembler::zero_words(Register ptr, Register cnt)
5295 {
5296 assert(is_power_of_2(zero_words_block_size), "adjust this");
5297 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
5298
5299 BLOCK_COMMENT("zero_words {");
5300 cmp(cnt, zero_words_block_size);
5301 Label around, done, done16;
5302 br(LO, around);
5303 {
5304 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5305 assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated");
5306 if (StubRoutines::aarch64::complete()) {
5307 trampoline_call(zero_blocks);
5308 } else {
5309 bl(zero_blocks);
5310 }
5311 }
5312 bind(around);
5313 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
5314 Label l;
5315 tbz(cnt, exact_log2(i), l);
5316 for (int j = 0; j < i; j += 2) {
5317 stp(zr, zr, post(ptr, 16));
5318 }
5319 bind(l);
5320 }
5321 {
5322 Label l;
5323 tbz(cnt, 0, l);
5324 str(zr, Address(ptr));
5325 bind(l);
5326 }
5327 BLOCK_COMMENT("} zero_words");
5328 }
5329
5330 // base: Address of a buffer to be zeroed, 8 bytes aligned.
5331 // cnt: Immediate count in HeapWords.
5332 #define SmallArraySize (18 * BytesPerLong)
5333 void MacroAssembler::zero_words(Register base, u_int64_t cnt)
5334 {
5335 BLOCK_COMMENT("zero_words {");
5336 int i = cnt & 1; // store any odd word to start
5337 if (i) str(zr, Address(base));
5338
5339 if (cnt <= SmallArraySize / BytesPerLong) {
5340 for (; i < (int)cnt; i += 2)
5341 stp(zr, zr, Address(base, i * wordSize));
5342 } else {
5343 const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll
5344 int remainder = cnt % (2 * unroll);
5345 for (; i < remainder; i += 2)
5346 stp(zr, zr, Address(base, i * wordSize));
5347
5348 Label loop;
5349 Register cnt_reg = rscratch1;
5350 Register loop_base = rscratch2;
5351 cnt = cnt - remainder;
5352 mov(cnt_reg, cnt);
5353 // adjust base and prebias by -2 * wordSize so we can pre-increment
5354 add(loop_base, base, (remainder - 2) * wordSize);
5355 bind(loop);
5356 sub(cnt_reg, cnt_reg, 2 * unroll);
5357 for (i = 1; i < unroll; i++)
5358 stp(zr, zr, Address(loop_base, 2 * i * wordSize));
5359 stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize)));
5360 cbnz(cnt_reg, loop);
5361 }
5362 BLOCK_COMMENT("} zero_words");
5363 }
5364
5365 // Zero blocks of memory by using DC ZVA.
5366 //
5367 // Aligns the base address first sufficently for DC ZVA, then uses
5368 // DC ZVA repeatedly for every full block. cnt is the size to be
5369 // zeroed in HeapWords. Returns the count of words left to be zeroed
5370 // in cnt.
5371 //
5372 // NOTE: This is intended to be used in the zero_blocks() stub. If
5373 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
5374 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
5375 Register tmp = rscratch1;
5376 Register tmp2 = rscratch2;
5377 int zva_length = VM_Version::zva_length();
5378 Label initial_table_end, loop_zva;
5379 Label fini;
5380
5381 // Base must be 16 byte aligned. If not just return and let caller handle it
5382 tst(base, 0x0f);
5383 br(Assembler::NE, fini);
5384 // Align base with ZVA length.
5385 neg(tmp, base);
5386 andr(tmp, tmp, zva_length - 1);
5387
5388 // tmp: the number of bytes to be filled to align the base with ZVA length.
5389 add(base, base, tmp);
5390 sub(cnt, cnt, tmp, Assembler::ASR, 3);
5391 adr(tmp2, initial_table_end);
5392 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
5393 br(tmp2);
5394
5395 for (int i = -zva_length + 16; i < 0; i += 16)
5396 stp(zr, zr, Address(base, i));
5397 bind(initial_table_end);
5398
5399 sub(cnt, cnt, zva_length >> 3);
5400 bind(loop_zva);
5401 dc(Assembler::ZVA, base);
5402 subs(cnt, cnt, zva_length >> 3);
5403 add(base, base, zva_length);
5404 br(Assembler::GE, loop_zva);
5405 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
5406 bind(fini);
5407 }
5408
5409 // base: Address of a buffer to be filled, 8 bytes aligned.
5410 // cnt: Count in 8-byte unit.
5411 // value: Value to be filled with.
5412 // base will point to the end of the buffer after filling.
5413 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
5414 {
5415 // Algorithm:
5416 //
5417 // scratch1 = cnt & 7;
5418 // cnt -= scratch1;
5419 // p += scratch1;
5420 // switch (scratch1) {
5421 // do {
5422 // cnt -= 8;
5423 // p[-8] = v;
5424 // case 7:
5425 // p[-7] = v;
5426 // case 6:
5427 // p[-6] = v;
5428 // // ...
5429 // case 1:
5430 // p[-1] = v;
5431 // case 0:
5432 // p += 8;
5433 // } while (cnt);
5434 // }
5435
5436 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
5437
5438 Label fini, skip, entry, loop;
5439 const int unroll = 8; // Number of stp instructions we'll unroll
5440
5441 cbz(cnt, fini);
5442 tbz(base, 3, skip);
5443 str(value, Address(post(base, 8)));
5444 sub(cnt, cnt, 1);
5445 bind(skip);
5446
5447 andr(rscratch1, cnt, (unroll-1) * 2);
5448 sub(cnt, cnt, rscratch1);
5449 add(base, base, rscratch1, Assembler::LSL, 3);
5450 adr(rscratch2, entry);
5451 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
5452 br(rscratch2);
5453
5454 bind(loop);
5455 add(base, base, unroll * 16);
5456 for (int i = -unroll; i < 0; i++)
5457 stp(value, value, Address(base, i * 16));
5458 bind(entry);
5459 subs(cnt, cnt, unroll * 2);
5460 br(Assembler::GE, loop);
5461
5462 tbz(cnt, 0, fini);
5463 str(value, Address(post(base, 8)));
5464 bind(fini);
5465 }
5466
5467 // Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and
5468 // java/lang/StringUTF16.compress.
5469 void MacroAssembler::encode_iso_array(Register src, Register dst,
5470 Register len, Register result,
5471 FloatRegister Vtmp1, FloatRegister Vtmp2,
5472 FloatRegister Vtmp3, FloatRegister Vtmp4)
5473 {
5474 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1;
5475 Register tmp1 = rscratch1;
5476
5477 mov(result, len); // Save initial len
5478
5479 #ifndef BUILTIN_SIM
5480 subs(len, len, 32);
5481 br(LT, LOOP_8);
5482
5483 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions
5484 // to convert chars to bytes. These set the 'QC' bit in the FPSR if
5485 // any char could not fit in a byte, so clear the FPSR so we can test it.
5486 clear_fpsr();
5487
5488 BIND(NEXT_32);
5489 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src);
5490 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half
5491 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half
5492 uqxtn(Vtmp2, T8B, Vtmp3, T8H);
5493 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2
5494 get_fpsr(tmp1);
5495 cbnzw(tmp1, LOOP_8);
5496 st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
5497 subs(len, len, 32);
5498 add(src, src, 64);
5499 br(GE, NEXT_32);
5500
5501 BIND(LOOP_8);
5502 adds(len, len, 32-8);
5503 br(LT, LOOP_1);
5504 clear_fpsr(); // QC may be set from loop above, clear again
5505 BIND(NEXT_8);
5506 ld1(Vtmp1, T8H, src);
5507 uqxtn(Vtmp1, T8B, Vtmp1, T8H);
5508 get_fpsr(tmp1);
5509 cbnzw(tmp1, LOOP_1);
5510 st1(Vtmp1, T8B, post(dst, 8));
5511 subs(len, len, 8);
5512 add(src, src, 16);
5513 br(GE, NEXT_8);
5514
5515 BIND(LOOP_1);
5516 adds(len, len, 8);
5517 br(LE, DONE);
5518 #else
5519 cbz(len, DONE);
5520 #endif
5521 BIND(NEXT_1);
5522 ldrh(tmp1, Address(post(src, 2)));
5523 tst(tmp1, 0xff00);
5524 br(NE, DONE);
5525 strb(tmp1, Address(post(dst, 1)));
5526 subs(len, len, 1);
5527 br(GT, NEXT_1);
5528
5529 BIND(DONE);
5530 sub(result, result, len); // Return index where we stopped
5531 // Return len == 0 if we processed all
5532 // characters
5533 }
5534
5535
5536 // Inflate byte[] array to char[].
5537 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
5538 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
5539 Register tmp4) {
5540 Label big, done;
5541
5542 assert_different_registers(src, dst, len, tmp4, rscratch1);
5543
5544 fmovd(vtmp1 , zr);
5545 lsrw(rscratch1, len, 3);
5546
5547 cbnzw(rscratch1, big);
5548
5549 // Short string: less than 8 bytes.
5550 {
5551 Label loop, around, tiny;
5552
5553 subsw(len, len, 4);
5554 andw(len, len, 3);
5555 br(LO, tiny);
5556
5557 // Use SIMD to do 4 bytes.
5558 ldrs(vtmp2, post(src, 4));
5559 zip1(vtmp3, T8B, vtmp2, vtmp1);
5560 strd(vtmp3, post(dst, 8));
5561
5562 cbzw(len, done);
5563
5564 // Do the remaining bytes by steam.
5565 bind(loop);
5566 ldrb(tmp4, post(src, 1));
5567 strh(tmp4, post(dst, 2));
5568 subw(len, len, 1);
5569
5570 bind(tiny);
5571 cbnz(len, loop);
5572
5573 bind(around);
5574 b(done);
5575 }
5576
5577 // Unpack the bytes 8 at a time.
5578 bind(big);
5579 andw(len, len, 7);
5580
5581 {
5582 Label loop, around;
5583
5584 bind(loop);
5585 ldrd(vtmp2, post(src, 8));
5586 sub(rscratch1, rscratch1, 1);
5587 zip1(vtmp3, T16B, vtmp2, vtmp1);
5588 st1(vtmp3, T8H, post(dst, 16));
5589 cbnz(rscratch1, loop);
5590
5591 bind(around);
5592 }
5593
5594 // Do the tail of up to 8 bytes.
5595 sub(src, src, 8);
5596 add(src, src, len, ext::uxtw, 0);
5597 ldrd(vtmp2, Address(src));
5598 sub(dst, dst, 16);
5599 add(dst, dst, len, ext::uxtw, 1);
5600 zip1(vtmp3, T16B, vtmp2, vtmp1);
5601 st1(vtmp3, T8H, Address(dst));
5602
5603 bind(done);
5604 }
5605
5606 // Compress char[] array to byte[].
5607 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
5608 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
5609 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
5610 Register result) {
5611 encode_iso_array(src, dst, len, result,
5612 tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg);
5613 cmp(len, zr);
5614 csel(result, result, zr, EQ);
5615 }
5616
5617 // get_thread() can be called anywhere inside generated code so we
5618 // need to save whatever non-callee save context might get clobbered
5619 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
5620 // the call setup code.
5621 //
5622 // aarch64_get_thread_helper() clobbers only r0, r1, and flags.
5623 //
5624 void MacroAssembler::get_thread(Register dst) {
5625 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst;
5626 push(saved_regs, sp);
5627
5628 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5629 blrt(lr, 1, 0, 1);
5630 if (dst != c_rarg0) {
5631 mov(dst, c_rarg0);
5632 }
5633
5634 pop(saved_regs, sp);
5635 }