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src/hotspot/cpu/arm/macroAssembler_arm.cpp
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rev 49911 : imported patch removeAllGCs
*** 42,52 ****
#include "runtime/objectMonitor.hpp"
#include "runtime/os.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "utilities/macros.hpp"
! #if INCLUDE_ALL_GCS
#include "gc/g1/g1BarrierSet.hpp"
#include "gc/g1/g1CardTable.hpp"
#include "gc/g1/g1ThreadLocalData.hpp"
#include "gc/g1/heapRegion.hpp"
#endif
--- 42,52 ----
#include "runtime/objectMonitor.hpp"
#include "runtime/os.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "utilities/macros.hpp"
! #if INCLUDE_G1GC
#include "gc/g1/g1BarrierSet.hpp"
#include "gc/g1/g1CardTable.hpp"
#include "gc/g1/g1ThreadLocalData.hpp"
#include "gc/g1/heapRegion.hpp"
#endif
*** 2132,2150 ****
STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u);
tbz(value, 0, not_weak); // Test for jweak tag.
// Resolve jweak.
ldr(value, Address(value, -JNIHandles::weak_tag_value));
verify_oop(value);
! #if INCLUDE_ALL_GCS
if (UseG1GC) {
g1_write_barrier_pre(noreg, // store_addr
noreg, // new_val
value, // pre_val
tmp1, // tmp1
tmp2); // tmp2
}
! #endif // INCLUDE_ALL_GCS
b(done);
bind(not_weak);
// Resolve (untagged) jobject.
ldr(value, Address(value));
verify_oop(value);
--- 2132,2150 ----
STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u);
tbz(value, 0, not_weak); // Test for jweak tag.
// Resolve jweak.
ldr(value, Address(value, -JNIHandles::weak_tag_value));
verify_oop(value);
! #if INCLUDE_G1GC
if (UseG1GC) {
g1_write_barrier_pre(noreg, // store_addr
noreg, // new_val
value, // pre_val
tmp1, // tmp1
tmp2); // tmp2
}
! #endif // INCLUDE_G1GC
b(done);
bind(not_weak);
// Resolve (untagged) jobject.
ldr(value, Address(value));
verify_oop(value);
*** 2152,2162 ****
}
//////////////////////////////////////////////////////////////////////////////////
! #if INCLUDE_ALL_GCS
// G1 pre-barrier.
// Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
// If store_addr != noreg, then previous value is loaded from [store_addr];
// in such case store_addr and new_val registers are preserved;
--- 2152,2162 ----
}
//////////////////////////////////////////////////////////////////////////////////
! #if INCLUDE_G1GC
// G1 pre-barrier.
// Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
// If store_addr != noreg, then previous value is loaded from [store_addr];
// in such case store_addr and new_val registers are preserved;
*** 2325,2335 ****
call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), R0, R1);
bind(done);
}
! #endif // INCLUDE_ALL_GCS
//////////////////////////////////////////////////////////////////////////////////
#ifdef AARCH64
--- 2325,2335 ----
call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), R0, R1);
bind(done);
}
! #endif // INCLUDE_G1GC
//////////////////////////////////////////////////////////////////////////////////
#ifdef AARCH64
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