--- old/src/hotspot/cpu/arm/macroAssembler_arm.cpp	2018-04-27 15:30:33.182201197 +0200
+++ new/src/hotspot/cpu/arm/macroAssembler_arm.cpp	2018-04-27 15:30:32.926201206 +0200
@@ -44,7 +44,7 @@
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "utilities/macros.hpp"
-#if INCLUDE_ALL_GCS
+#if INCLUDE_G1GC
 #include "gc/g1/g1BarrierSet.hpp"
 #include "gc/g1/g1CardTable.hpp"
 #include "gc/g1/g1ThreadLocalData.hpp"
@@ -2134,7 +2134,7 @@
   // Resolve jweak.
   ldr(value, Address(value, -JNIHandles::weak_tag_value));
   verify_oop(value);
-#if INCLUDE_ALL_GCS
+#if INCLUDE_G1GC
   if (UseG1GC) {
     g1_write_barrier_pre(noreg, // store_addr
                          noreg, // new_val
@@ -2142,7 +2142,7 @@
                          tmp1,  // tmp1
                          tmp2); // tmp2
     }
-#endif // INCLUDE_ALL_GCS
+#endif // INCLUDE_G1GC
   b(done);
   bind(not_weak);
   // Resolve (untagged) jobject.
@@ -2154,7 +2154,7 @@
 
 //////////////////////////////////////////////////////////////////////////////////
 
-#if INCLUDE_ALL_GCS
+#if INCLUDE_G1GC
 
 // G1 pre-barrier.
 // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
@@ -2327,7 +2327,7 @@
   bind(done);
 }
 
-#endif // INCLUDE_ALL_GCS
+#endif // INCLUDE_G1GC
 
 //////////////////////////////////////////////////////////////////////////////////