/* * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef OS_CPU_AIX_PPC_ORDERACCESS_AIX_PPC_HPP #define OS_CPU_AIX_PPC_ORDERACCESS_AIX_PPC_HPP // Included in orderAccess.hpp header file. // Compiler version last used for testing: xlc 12 // Please update this information when this file changes // Implementation of class OrderAccess. // // Machine barrier instructions: // // - sync Two-way memory barrier, aka fence. // - lwsync orders Store|Store, // Load|Store, // Load|Load, // but not Store|Load // - eieio orders Store|Store // - isync Invalidates speculatively executed instructions, // but isync may complete before storage accesses // associated with instructions preceding isync have // been performed. // // Semantic barrier instructions: // (as defined in orderAccess.hpp) // // - release orders Store|Store, (maps to lwsync) // Load|Store // - acquire orders Load|Store, (maps to lwsync) // Load|Load // - fence orders Store|Store, (maps to sync) // Load|Store, // Load|Load, // Store|Load // #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory"); #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory"); #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory"); #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory"); inline void OrderAccess::loadload() { inlasm_lwsync(); } inline void OrderAccess::storestore() { inlasm_lwsync(); } inline void OrderAccess::loadstore() { inlasm_lwsync(); } inline void OrderAccess::storeload() { inlasm_sync(); } inline void OrderAccess::acquire() { inlasm_lwsync(); } inline void OrderAccess::release() { inlasm_lwsync(); } inline void OrderAccess::fence() { inlasm_sync(); } inline void OrderAccess::cross_modify_fence() { inlasm_isync(); } #undef inlasm_sync #undef inlasm_lwsync #undef inlasm_eieio #undef inlasm_isync #endif // OS_CPU_AIX_PPC_ORDERACCESS_AIX_PPC_HPP