13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP
27 #define OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP
28
29 #ifndef PPC64
30 #error "Atomic currently only implemented for PPC64"
31 #endif
32
33 #include "utilities/debug.hpp"
34
35 // Implementation of class atomic
36
37 //
38 // machine barrier instructions:
39 //
40 // - sync two-way memory barrier, aka fence
41 // - lwsync orders Store|Store,
42 // Load|Store,
43 // Load|Load,
44 // but not Store|Load
45 // - eieio orders memory accesses for device memory (only)
46 // - isync invalidates speculatively executed instructions
47 // From the POWER ISA 2.06 documentation:
48 // "[...] an isync instruction prevents the execution of
49 // instructions following the isync until instructions
50 // preceding the isync have completed, [...]"
51 // From IBM's AIX assembler reference:
52 // "The isync [...] instructions causes the processor to
381 /* exit */
382 "2: \n"
383 /* out */
384 : [old_value] "=&r" (old_value),
385 "=m" (*dest)
386 /* in */
387 : [dest] "b" (dest),
388 [zero] "r" (zero),
389 [compare_value] "r" (compare_value),
390 [exchange_value] "r" (exchange_value),
391 "m" (*dest)
392 /* clobber */
393 : "cc",
394 "memory"
395 );
396
397 post_membar(order);
398
399 return old_value;
400 }
401
402 #endif // OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP
|
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP
27 #define OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP
28
29 #ifndef PPC64
30 #error "Atomic currently only implemented for PPC64"
31 #endif
32
33 #include "orderAccess_aix_ppc.hpp"
34 #include "utilities/debug.hpp"
35
36 // Implementation of class atomic
37
38 //
39 // machine barrier instructions:
40 //
41 // - sync two-way memory barrier, aka fence
42 // - lwsync orders Store|Store,
43 // Load|Store,
44 // Load|Load,
45 // but not Store|Load
46 // - eieio orders memory accesses for device memory (only)
47 // - isync invalidates speculatively executed instructions
48 // From the POWER ISA 2.06 documentation:
49 // "[...] an isync instruction prevents the execution of
50 // instructions following the isync until instructions
51 // preceding the isync have completed, [...]"
52 // From IBM's AIX assembler reference:
53 // "The isync [...] instructions causes the processor to
382 /* exit */
383 "2: \n"
384 /* out */
385 : [old_value] "=&r" (old_value),
386 "=m" (*dest)
387 /* in */
388 : [dest] "b" (dest),
389 [zero] "r" (zero),
390 [compare_value] "r" (compare_value),
391 [exchange_value] "r" (exchange_value),
392 "m" (*dest)
393 /* clobber */
394 : "cc",
395 "memory"
396 );
397
398 post_membar(order);
399
400 return old_value;
401 }
402
403 template<size_t byte_size>
404 struct Atomic::PlatformOrderedLoad<byte_size, X_ACQUIRE> {
405 template <typename T>
406 T operator()(const volatile T* p) const {
407 T t = Atomic::load(p);
408 // Use twi-isync for load_acquire (faster than lwsync).
409 __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (t) : "memory");
410 return t;
411 }
412 };
413
414 #endif // OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP
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