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src/hotspot/os_cpu/aix_ppc/orderAccess_aix_ppc.hpp

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  47 //                   associated with instructions preceding isync have
  48 //                   been performed.
  49 //
  50 // Semantic barrier instructions:
  51 // (as defined in orderAccess.hpp)
  52 //
  53 // - release         orders Store|Store,       (maps to lwsync)
  54 //                           Load|Store
  55 // - acquire         orders  Load|Store,       (maps to lwsync)
  56 //                           Load|Load
  57 // - fence           orders Store|Store,       (maps to sync)
  58 //                           Load|Store,
  59 //                           Load|Load,
  60 //                          Store|Load
  61 //
  62 
  63 #define inlasm_sync()     __asm__ __volatile__ ("sync"   : : : "memory");
  64 #define inlasm_lwsync()   __asm__ __volatile__ ("lwsync" : : : "memory");
  65 #define inlasm_eieio()    __asm__ __volatile__ ("eieio"  : : : "memory");
  66 #define inlasm_isync()    __asm__ __volatile__ ("isync"  : : : "memory");
  67 // Use twi-isync for load_acquire (faster than lwsync).
  68 #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
  69 
  70 inline void OrderAccess::loadload()   { inlasm_lwsync(); }
  71 inline void OrderAccess::storestore() { inlasm_lwsync(); }
  72 inline void OrderAccess::loadstore()  { inlasm_lwsync(); }
  73 inline void OrderAccess::storeload()  { inlasm_sync();   }
  74 
  75 inline void OrderAccess::acquire()    { inlasm_lwsync(); }
  76 inline void OrderAccess::release()    { inlasm_lwsync(); }
  77 inline void OrderAccess::fence()      { inlasm_sync();   }
  78 inline void OrderAccess::cross_modify_fence()
  79                                       { inlasm_isync();  }
  80 
  81 template<size_t byte_size>
  82 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE>
  83 {
  84   template <typename T>
  85   T operator()(const volatile T* p) const { T t = Atomic::load(p); inlasm_acquire_reg(t); return t; }
  86 };
  87 
  88 #undef inlasm_sync
  89 #undef inlasm_lwsync
  90 #undef inlasm_eieio
  91 #undef inlasm_isync
  92 
  93 #endif // OS_CPU_AIX_PPC_ORDERACCESS_AIX_PPC_HPP


  47 //                   associated with instructions preceding isync have
  48 //                   been performed.
  49 //
  50 // Semantic barrier instructions:
  51 // (as defined in orderAccess.hpp)
  52 //
  53 // - release         orders Store|Store,       (maps to lwsync)
  54 //                           Load|Store
  55 // - acquire         orders  Load|Store,       (maps to lwsync)
  56 //                           Load|Load
  57 // - fence           orders Store|Store,       (maps to sync)
  58 //                           Load|Store,
  59 //                           Load|Load,
  60 //                          Store|Load
  61 //
  62 
  63 #define inlasm_sync()     __asm__ __volatile__ ("sync"   : : : "memory");
  64 #define inlasm_lwsync()   __asm__ __volatile__ ("lwsync" : : : "memory");
  65 #define inlasm_eieio()    __asm__ __volatile__ ("eieio"  : : : "memory");
  66 #define inlasm_isync()    __asm__ __volatile__ ("isync"  : : : "memory");


  67 
  68 inline void OrderAccess::loadload()   { inlasm_lwsync(); }
  69 inline void OrderAccess::storestore() { inlasm_lwsync(); }
  70 inline void OrderAccess::loadstore()  { inlasm_lwsync(); }
  71 inline void OrderAccess::storeload()  { inlasm_sync();   }
  72 
  73 inline void OrderAccess::acquire()    { inlasm_lwsync(); }
  74 inline void OrderAccess::release()    { inlasm_lwsync(); }
  75 inline void OrderAccess::fence()      { inlasm_sync();   }
  76 inline void OrderAccess::cross_modify_fence()
  77                                       { inlasm_isync();  }







  78 
  79 #undef inlasm_sync
  80 #undef inlasm_lwsync
  81 #undef inlasm_eieio
  82 #undef inlasm_isync
  83 
  84 #endif // OS_CPU_AIX_PPC_ORDERACCESS_AIX_PPC_HPP
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