1 /*
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   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
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   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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  24 
  25 #ifndef OS_CPU_BSD_X86_ORDERACCESS_BSD_X86_HPP
  26 #define OS_CPU_BSD_X86_ORDERACCESS_BSD_X86_HPP
  27 
  28 // Included in orderAccess.hpp header file.
  29 
  30 // Compiler version last used for testing: clang 5.1
  31 // Please update this information when this file changes
  32 
  33 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
  34 static inline void compiler_barrier() {
  35   __asm__ volatile ("" : : : "memory");
  36 }
  37 
  38 // x86 is TSO and hence only needs a fence for storeload
  39 // However, a compiler barrier is still needed to prevent reordering
  40 // between volatile and non-volatile memory accesses.
  41 
  42 // Implementation of class OrderAccess.
  43 
  44 inline void OrderAccess::loadload()   { compiler_barrier(); }
  45 inline void OrderAccess::storestore() { compiler_barrier(); }
  46 inline void OrderAccess::loadstore()  { compiler_barrier(); }
  47 inline void OrderAccess::storeload()  { fence();            }
  48 
  49 inline void OrderAccess::acquire()    { compiler_barrier(); }
  50 inline void OrderAccess::release()    { compiler_barrier(); }
  51 
  52 inline void OrderAccess::fence() {
  53   // always use locked addl since mfence is sometimes expensive
  54 #ifdef AMD64
  55   __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
  56 #else
  57   __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
  58 #endif
  59   compiler_barrier();
  60 }
  61 
  62 inline void OrderAccess::cross_modify_fence() {
  63   int idx = 0;
  64   __asm__ volatile ("cpuid " : "+a" (idx) : : "ebx", "ecx", "edx", "memory");
  65 }
  66 
  67 #endif // OS_CPU_BSD_X86_ORDERACCESS_BSD_X86_HPP