1 /* 2 * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016, 2019 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef OS_CPU_LINUX_S390_ORDERACCESS_LINUX_S390_HPP 27 #define OS_CPU_LINUX_S390_ORDERACCESS_LINUX_S390_HPP 28 29 // Included in orderAccess.hpp header file. 30 31 #include "runtime/vm_version.hpp" 32 33 // Implementation of class OrderAccess. 34 35 // 36 // machine barrier instructions: 37 // 38 // - z_sync two-way memory barrier, aka fence 39 // 40 // semantic barrier instructions: 41 // (as defined in orderAccess.hpp) 42 // 43 // - z_release orders Store|Store, (maps to compiler barrier) 44 // Load|Store 45 // - z_acquire orders Load|Store, (maps to compiler barrier) 46 // Load|Load 47 // - z_fence orders Store|Store, (maps to z_sync) 48 // Load|Store, 49 // Load|Load, 50 // Store|Load 51 // 52 53 54 // Only load-after-store-order is not guaranteed on z/Architecture, i.e. only 'fence' 55 // is needed. 56 57 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions. 58 #define inlasm_compiler_barrier() __asm__ volatile ("" : : : "memory"); 59 // "bcr 15, 0" is used as two way memory barrier. 60 #define inlasm_zarch_sync() __asm__ __volatile__ ("bcr 15, 0" : : : "memory"); 61 62 // Release and acquire are empty on z/Architecture, but potential 63 // optimizations of gcc must be forbidden by OrderAccess::release and 64 // OrderAccess::acquire. 65 #define inlasm_zarch_release() inlasm_compiler_barrier() 66 #define inlasm_zarch_acquire() inlasm_compiler_barrier() 67 #define inlasm_zarch_fence() inlasm_zarch_sync() 68 69 inline void OrderAccess::loadload() { inlasm_compiler_barrier(); } 70 inline void OrderAccess::storestore() { inlasm_compiler_barrier(); } 71 inline void OrderAccess::loadstore() { inlasm_compiler_barrier(); } 72 inline void OrderAccess::storeload() { inlasm_zarch_sync(); } 73 74 inline void OrderAccess::acquire() { inlasm_zarch_acquire(); } 75 inline void OrderAccess::release() { inlasm_zarch_release(); } 76 inline void OrderAccess::fence() { inlasm_zarch_sync(); } 77 inline void OrderAccess::cross_modify_fence() { inlasm_zarch_sync(); } 78 79 template<size_t byte_size> 80 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE> 81 { 82 template <typename T> 83 T operator()(const volatile T* p) const { T t = *p; inlasm_zarch_acquire(); return t; } 84 }; 85 86 #undef inlasm_compiler_barrier 87 #undef inlasm_zarch_sync 88 #undef inlasm_zarch_release 89 #undef inlasm_zarch_acquire 90 #undef inlasm_zarch_fence 91 92 #endif // OS_CPU_LINUX_S390_ORDERACCESS_LINUX_S390_HPP