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src/hotspot/os_cpu/linux_arm/atomic_linux_arm.hpp

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  37  * However, gcc emits LDRD/STRD instructions on v5te and LDM/STM on v5t
  38  * when loading/storing 64 bits.
  39  * For non-MP machines (which is all we support for ARM < v7)
  40  * under current Linux distros these instructions appear atomic.
  41  * See section A3.5.3 of ARM Architecture Reference Manual for ARM v7.
  42  * Also, for cmpxchg64, if ARM < v7 we check for cmpxchg64 support in the
  43  * Linux kernel using _kuser_helper_version. See entry-armv.S in the Linux
  44  * kernel source or kernel_user_helpers.txt in Linux Doc.
  45  */
  46 
  47 template<>
  48 template<typename T>
  49 inline T Atomic::PlatformLoad<8>::operator()(T const volatile* src) const {
  50   STATIC_ASSERT(8 == sizeof(T));
  51   return PrimitiveConversions::cast<T>(
  52     (*os::atomic_load_long_func)(reinterpret_cast<const volatile int64_t*>(src)));
  53 }
  54 
  55 template<>
  56 template<typename T>
  57 inline void Atomic::PlatformStore<8>::operator()(T store_value,
  58                                                  T volatile* dest) const {
  59   STATIC_ASSERT(8 == sizeof(T));
  60   (*os::atomic_store_long_func)(
  61     PrimitiveConversions::cast<int64_t>(store_value), reinterpret_cast<volatile int64_t*>(dest));
  62 }
  63 
  64 // As per atomic.hpp all read-modify-write operations have to provide two-way
  65 // barriers semantics.
  66 //
  67 // For ARMv7 we add explicit barriers in the stubs.
  68 
  69 template<size_t byte_size>
  70 struct Atomic::PlatformAdd
  71   : Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> >
  72 {
  73   template<typename I, typename D>
  74   D add_and_fetch(I add_value, D volatile* dest, atomic_memory_order order) const;
  75 };
  76 
  77 template<>
  78 template<typename I, typename D>




  37  * However, gcc emits LDRD/STRD instructions on v5te and LDM/STM on v5t
  38  * when loading/storing 64 bits.
  39  * For non-MP machines (which is all we support for ARM < v7)
  40  * under current Linux distros these instructions appear atomic.
  41  * See section A3.5.3 of ARM Architecture Reference Manual for ARM v7.
  42  * Also, for cmpxchg64, if ARM < v7 we check for cmpxchg64 support in the
  43  * Linux kernel using _kuser_helper_version. See entry-armv.S in the Linux
  44  * kernel source or kernel_user_helpers.txt in Linux Doc.
  45  */
  46 
  47 template<>
  48 template<typename T>
  49 inline T Atomic::PlatformLoad<8>::operator()(T const volatile* src) const {
  50   STATIC_ASSERT(8 == sizeof(T));
  51   return PrimitiveConversions::cast<T>(
  52     (*os::atomic_load_long_func)(reinterpret_cast<const volatile int64_t*>(src)));
  53 }
  54 
  55 template<>
  56 template<typename T>
  57 inline void Atomic::PlatformStore<8>::operator()(T volatile* dest,
  58                                                  T store_value) const {
  59   STATIC_ASSERT(8 == sizeof(T));
  60   (*os::atomic_store_long_func)(
  61     PrimitiveConversions::cast<int64_t>(store_value), reinterpret_cast<volatile int64_t*>(dest));
  62 }
  63 
  64 // As per atomic.hpp all read-modify-write operations have to provide two-way
  65 // barriers semantics.
  66 //
  67 // For ARMv7 we add explicit barriers in the stubs.
  68 
  69 template<size_t byte_size>
  70 struct Atomic::PlatformAdd
  71   : Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> >
  72 {
  73   template<typename I, typename D>
  74   D add_and_fetch(I add_value, D volatile* dest, atomic_memory_order order) const;
  75 };
  76 
  77 template<>
  78 template<typename I, typename D>


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