1 /*
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   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
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   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef OS_CPU_WINDOWS_X86_ATOMIC_WINDOWS_X86_HPP
  26 #define OS_CPU_WINDOWS_X86_ATOMIC_WINDOWS_X86_HPP
  27 
  28 #include "runtime/os.hpp"
  29 
  30 // Note that in MSVC, volatile memory accesses are explicitly
  31 // guaranteed to have acquire release semantics (w.r.t. compiler
  32 // reordering) and therefore does not even need a compiler barrier
  33 // for normal acquire release accesses. And all generalized
  34 // bound calls like release_store go through OrderAccess::load
  35 // and OrderAccess::store which do volatile memory accesses.
  36 template<> inline void ScopedFence<X_ACQUIRE>::postfix()       { }
  37 template<> inline void ScopedFence<RELEASE_X>::prefix()        { }
  38 template<> inline void ScopedFence<RELEASE_X_FENCE>::prefix()  { }
  39 template<> inline void ScopedFence<RELEASE_X_FENCE>::postfix() { OrderAccess::fence(); }
  40 
  41 // The following alternative implementations are needed because
  42 // Windows 95 doesn't support (some of) the corresponding Windows NT
  43 // calls. Furthermore, these versions allow inlining in the caller.
  44 // (More precisely: The documentation for InterlockedExchange says
  45 // it is supported for Windows 95. However, when single-stepping
  46 // through the assembly code we cannot step into the routine and
  47 // when looking at the routine address we see only garbage code.
  48 // Better safe then sorry!). Was bug 7/31/98 (gri).
  49 //
  50 // Performance note: On uniprocessors, the 'lock' prefixes are not
  51 // necessary (and expensive). We should generate separate cases if
  52 // this becomes a performance problem.
  53 
  54 #pragma warning(disable: 4035) // Disables warnings reporting missing return statement
  55 
  56 template<size_t byte_size>
  57 struct Atomic::PlatformAdd
  58   : Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> >
  59 {
  60   template<typename D, typename I>
  61   D add_and_fetch(D volatile* dest, I add_value, atomic_memory_order order) const;
  62 };
  63 
  64 #ifdef AMD64
  65 template<>
  66 template<typename D, typename I>
  67 inline D Atomic::PlatformAdd<4>::add_and_fetch(D volatile* dest, I add_value,
  68                                                atomic_memory_order order) const {
  69   return add_using_helper<int32_t>(os::atomic_add_func, dest, add_value);
  70 }
  71 
  72 template<>
  73 template<typename D, typename I>
  74 inline D Atomic::PlatformAdd<8>::add_and_fetch(D volatile* dest, I add_value,
  75                                                atomic_memory_order order) const {
  76   return add_using_helper<int64_t>(os::atomic_add_long_func, dest, add_value);
  77 }
  78 
  79 #define DEFINE_STUB_XCHG(ByteSize, StubType, StubName)                  \
  80   template<>                                                            \
  81   template<typename T>                                                  \
  82   inline T Atomic::PlatformXchg<ByteSize>::operator()(T volatile* dest, \
  83                                                       T exchange_value, \
  84                                                       atomic_memory_order order) const { \
  85     STATIC_ASSERT(ByteSize == sizeof(T));                               \
  86     return xchg_using_helper<StubType>(StubName, dest, exchange_value); \
  87   }
  88 
  89 DEFINE_STUB_XCHG(4, int32_t, os::atomic_xchg_func)
  90 DEFINE_STUB_XCHG(8, int64_t, os::atomic_xchg_long_func)
  91 
  92 #undef DEFINE_STUB_XCHG
  93 
  94 #define DEFINE_STUB_CMPXCHG(ByteSize, StubType, StubName)               \
  95   template<>                                                            \
  96   template<typename T>                                                  \
  97   inline T Atomic::PlatformCmpxchg<ByteSize>::operator()(T exchange_value, \
  98                                                          T volatile* dest, \
  99                                                          T compare_value, \
 100                                                          atomic_memory_order order) const { \
 101     STATIC_ASSERT(ByteSize == sizeof(T));                               \
 102     return cmpxchg_using_helper<StubType>(StubName, exchange_value, dest, compare_value); \
 103   }
 104 
 105 DEFINE_STUB_CMPXCHG(1, int8_t,  os::atomic_cmpxchg_byte_func)
 106 DEFINE_STUB_CMPXCHG(4, int32_t, os::atomic_cmpxchg_func)
 107 DEFINE_STUB_CMPXCHG(8, int64_t, os::atomic_cmpxchg_long_func)
 108 
 109 #undef DEFINE_STUB_CMPXCHG
 110 
 111 #else // !AMD64
 112 
 113 template<>
 114 template<typename D, typename I>
 115 inline D Atomic::PlatformAdd<4>::add_and_fetch(D volatile* dest, I add_value,
 116                                                atomic_memory_order order) const {
 117   STATIC_ASSERT(4 == sizeof(I));
 118   STATIC_ASSERT(4 == sizeof(D));
 119   __asm {
 120     mov edx, dest;
 121     mov eax, add_value;
 122     mov ecx, eax;
 123     lock xadd dword ptr [edx], eax;
 124     add eax, ecx;
 125   }
 126 }
 127 
 128 template<>
 129 template<typename T>
 130 inline T Atomic::PlatformXchg<4>::operator()(T volatile* dest,
 131                                              T exchange_value,
 132                                              atomic_memory_order order) const {
 133   STATIC_ASSERT(4 == sizeof(T));
 134   // alternative for InterlockedExchange
 135   __asm {
 136     mov eax, exchange_value;
 137     mov ecx, dest;
 138     xchg eax, dword ptr [ecx];
 139   }
 140 }
 141 
 142 template<>
 143 template<typename T>
 144 inline T Atomic::PlatformCmpxchg<1>::operator()(T exchange_value,
 145                                                 T volatile* dest,
 146                                                 T compare_value,
 147                                                 atomic_memory_order order) const {
 148   STATIC_ASSERT(1 == sizeof(T));
 149   // alternative for InterlockedCompareExchange
 150   __asm {
 151     mov edx, dest
 152     mov cl, exchange_value
 153     mov al, compare_value
 154     lock cmpxchg byte ptr [edx], cl
 155   }
 156 }
 157 
 158 template<>
 159 template<typename T>
 160 inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value,
 161                                                 T volatile* dest,
 162                                                 T compare_value,
 163                                                 atomic_memory_order order) const {
 164   STATIC_ASSERT(4 == sizeof(T));
 165   // alternative for InterlockedCompareExchange
 166   __asm {
 167     mov edx, dest
 168     mov ecx, exchange_value
 169     mov eax, compare_value
 170     lock cmpxchg dword ptr [edx], ecx
 171   }
 172 }
 173 
 174 template<>
 175 template<typename T>
 176 inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
 177                                                 T volatile* dest,
 178                                                 T compare_value,
 179                                                 atomic_memory_order order) const {
 180   STATIC_ASSERT(8 == sizeof(T));
 181   int32_t ex_lo  = (int32_t)exchange_value;
 182   int32_t ex_hi  = *( ((int32_t*)&exchange_value) + 1 );
 183   int32_t cmp_lo = (int32_t)compare_value;
 184   int32_t cmp_hi = *( ((int32_t*)&compare_value) + 1 );
 185   __asm {
 186     push ebx
 187     push edi
 188     mov eax, cmp_lo
 189     mov edx, cmp_hi
 190     mov edi, dest
 191     mov ebx, ex_lo
 192     mov ecx, ex_hi
 193     lock cmpxchg8b qword ptr [edi]
 194     pop edi
 195     pop ebx
 196   }
 197 }
 198 
 199 template<>
 200 template<typename T>
 201 inline T Atomic::PlatformLoad<8>::operator()(T const volatile* src) const {
 202   STATIC_ASSERT(8 == sizeof(T));
 203   volatile T dest;
 204   volatile T* pdest = &dest;
 205   __asm {
 206     mov eax, src
 207     fild     qword ptr [eax]
 208     mov eax, pdest
 209     fistp    qword ptr [eax]
 210   }
 211   return dest;
 212 }
 213 
 214 template<>
 215 template<typename T>
 216 inline void Atomic::PlatformStore<8>::operator()(T volatile* dest,
 217                                                  T store_value) const {
 218   STATIC_ASSERT(8 == sizeof(T));
 219   volatile T* src = &store_value;
 220   __asm {
 221     mov eax, src
 222     fild     qword ptr [eax]
 223     mov eax, dest
 224     fistp    qword ptr [eax]
 225   }
 226 }
 227 
 228 #endif // AMD64
 229 
 230 #pragma warning(default: 4035) // Enables warnings reporting missing return statement
 231 
 232 #ifndef AMD64
 233 template<>
 234 struct Atomic::PlatformOrderedStore<1, RELEASE_X_FENCE>
 235 {
 236   template <typename T>
 237   void operator()(volatile T* p, T v) const {
 238     __asm {
 239       mov edx, p;
 240       mov al, v;
 241       xchg al, byte ptr [edx];
 242     }
 243   }
 244 };
 245 
 246 template<>
 247 struct Atomic::PlatformOrderedStore<2, RELEASE_X_FENCE>
 248 {
 249   template <typename T>
 250   void operator()(volatile T* p, T v) const {
 251     __asm {
 252       mov edx, p;
 253       mov ax, v;
 254       xchg ax, word ptr [edx];
 255     }
 256   }
 257 };
 258 
 259 template<>
 260 struct Atomic::PlatformOrderedStore<4, RELEASE_X_FENCE>
 261 {
 262   template <typename T>
 263   void operator()(volatile T* p, T v) const {
 264     __asm {
 265       mov edx, p;
 266       mov eax, v;
 267       xchg eax, dword ptr [edx];
 268     }
 269   }
 270 };
 271 #endif // AMD64
 272 
 273 #endif // OS_CPU_WINDOWS_X86_ATOMIC_WINDOWS_X86_HPP