11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_ARM_NATIVEINST_ARM_32_HPP
26 #define CPU_ARM_NATIVEINST_ARM_32_HPP
27
28 #include "asm/macroAssembler.hpp"
29 #include "code/codeCache.hpp"
30 #include "runtime/icache.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/thread.hpp"
33 #include "register_arm.hpp"
34
35 // -------------------------------------------------------------------
36
37 // Some experimental projects extend the ARM back-end by implementing
38 // what the front-end usually assumes is a single native instruction
39 // with a sequence of instructions.
40 //
41 // The 'Raw' variants are the low level initial code (usually one
42 // instruction wide but some of them were already composed
43 // instructions). They should be used only by the back-end.
44 //
45 // The non-raw classes are the front-end entry point, hiding potential
46 // back-end extensions or the actual instructions size.
47 class NativeInstruction;
48 class NativeCall;
49
50 class RawNativeInstruction {
|
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_ARM_NATIVEINST_ARM_32_HPP
26 #define CPU_ARM_NATIVEINST_ARM_32_HPP
27
28 #include "asm/macroAssembler.hpp"
29 #include "code/codeCache.hpp"
30 #include "runtime/icache.hpp"
31 #include "runtime/orderAccess.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/thread.hpp"
34 #include "register_arm.hpp"
35
36 // -------------------------------------------------------------------
37
38 // Some experimental projects extend the ARM back-end by implementing
39 // what the front-end usually assumes is a single native instruction
40 // with a sequence of instructions.
41 //
42 // The 'Raw' variants are the low level initial code (usually one
43 // instruction wide but some of them were already composed
44 // instructions). They should be used only by the back-end.
45 //
46 // The non-raw classes are the front-end entry point, hiding potential
47 // back-end extensions or the actual instructions size.
48 class NativeInstruction;
49 class NativeCall;
50
51 class RawNativeInstruction {
|