1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "utilities/macros.hpp"
43 #if INCLUDE_ALL_GCS
44 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
45 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
46 #include "gc_implementation/g1/heapRegion.hpp"
47 #endif // INCLUDE_ALL_GCS
48
49 #ifdef PRODUCT
50 #define BLOCK_COMMENT(str) /* nothing */
51 #define STOP(error) stop(error)
52 #else
53 #define BLOCK_COMMENT(str) block_comment(str)
54 #define STOP(error) block_comment(error); stop(error)
55 #endif
56
57 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
58
59 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
60
61 #ifdef ASSERT
62 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
63 #endif
64
65 static Assembler::Condition reverse[] = {
66 Assembler::noOverflow /* overflow = 0x0 */ ,
67 Assembler::overflow /* noOverflow = 0x1 */ ,
68 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
69 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
70 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
71 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
72 Assembler::above /* belowEqual = 0x6 */ ,
73 Assembler::belowEqual /* above = 0x7 */ ,
74 Assembler::positive /* negative = 0x8 */ ,
75 Assembler::negative /* positive = 0x9 */ ,
76 Assembler::noParity /* parity = 0xa */ ,
77 Assembler::parity /* noParity = 0xb */ ,
78 Assembler::greaterEqual /* less = 0xc */ ,
79 Assembler::less /* greaterEqual = 0xd */ ,
80 Assembler::greater /* lessEqual = 0xe */ ,
81 Assembler::lessEqual /* greater = 0xf, */
82
83 };
84
85
86 // Implementation of MacroAssembler
87
88 // First all the versions that have distinct versions depending on 32/64 bit
89 // Unless the difference is trivial (1 line or so).
90
91 #ifndef _LP64
92
93 // 32bit versions
94
95 Address MacroAssembler::as_Address(AddressLiteral adr) {
96 return Address(adr.target(), adr.rspec());
97 }
98
99 Address MacroAssembler::as_Address(ArrayAddress adr) {
100 return Address::make_array(adr);
101 }
102
103 void MacroAssembler::call_VM_leaf_base(address entry_point,
104 int number_of_arguments) {
105 call(RuntimeAddress(entry_point));
106 increment(rsp, number_of_arguments * wordSize);
107 }
108
109 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
110 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
111 }
112
113 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpoop(Address src1, jobject obj) {
118 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop(Register src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::extend_sign(Register hi, Register lo) {
126 // According to Intel Doc. AP-526, "Integer Divide", p.18.
127 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
128 cdql();
129 } else {
130 movl(hi, lo);
131 sarl(hi, 31);
132 }
133 }
134
135 void MacroAssembler::jC2(Register tmp, Label& L) {
136 // set parity bit if FPU flag C2 is set (via rax)
137 save_rax(tmp);
138 fwait(); fnstsw_ax();
139 sahf();
140 restore_rax(tmp);
141 // branch
142 jcc(Assembler::parity, L);
143 }
144
145 void MacroAssembler::jnC2(Register tmp, Label& L) {
146 // set parity bit if FPU flag C2 is set (via rax)
147 save_rax(tmp);
148 fwait(); fnstsw_ax();
149 sahf();
150 restore_rax(tmp);
151 // branch
152 jcc(Assembler::noParity, L);
153 }
154
155 // 32bit can do a case table jump in one instruction but we no longer allow the base
156 // to be installed in the Address class
157 void MacroAssembler::jump(ArrayAddress entry) {
158 jmp(as_Address(entry));
159 }
160
161 // Note: y_lo will be destroyed
162 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
163 // Long compare for Java (semantics as described in JVM spec.)
164 Label high, low, done;
165
166 cmpl(x_hi, y_hi);
167 jcc(Assembler::less, low);
168 jcc(Assembler::greater, high);
169 // x_hi is the return register
170 xorl(x_hi, x_hi);
171 cmpl(x_lo, y_lo);
172 jcc(Assembler::below, low);
173 jcc(Assembler::equal, done);
174
175 bind(high);
176 xorl(x_hi, x_hi);
177 increment(x_hi);
178 jmp(done);
179
180 bind(low);
181 xorl(x_hi, x_hi);
182 decrementl(x_hi);
183
184 bind(done);
185 }
186
187 void MacroAssembler::lea(Register dst, AddressLiteral src) {
188 mov_literal32(dst, (int32_t)src.target(), src.rspec());
189 }
190
191 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
192 // leal(dst, as_Address(adr));
193 // see note in movl as to why we must use a move
194 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
195 }
196
197 void MacroAssembler::leave() {
198 mov(rsp, rbp);
199 pop(rbp);
200 }
201
202 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
203 // Multiplication of two Java long values stored on the stack
204 // as illustrated below. Result is in rdx:rax.
205 //
206 // rsp ---> [ ?? ] \ \
207 // .... | y_rsp_offset |
208 // [ y_lo ] / (in bytes) | x_rsp_offset
209 // [ y_hi ] | (in bytes)
210 // .... |
211 // [ x_lo ] /
212 // [ x_hi ]
213 // ....
214 //
215 // Basic idea: lo(result) = lo(x_lo * y_lo)
216 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
217 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
218 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
219 Label quick;
220 // load x_hi, y_hi and check if quick
221 // multiplication is possible
222 movl(rbx, x_hi);
223 movl(rcx, y_hi);
224 movl(rax, rbx);
225 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
226 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
227 // do full multiplication
228 // 1st step
229 mull(y_lo); // x_hi * y_lo
230 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
231 // 2nd step
232 movl(rax, x_lo);
233 mull(rcx); // x_lo * y_hi
234 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
235 // 3rd step
236 bind(quick); // note: rbx, = 0 if quick multiply!
237 movl(rax, x_lo);
238 mull(y_lo); // x_lo * y_lo
239 addl(rdx, rbx); // correct hi(x_lo * y_lo)
240 }
241
242 void MacroAssembler::lneg(Register hi, Register lo) {
243 negl(lo);
244 adcl(hi, 0);
245 negl(hi);
246 }
247
248 void MacroAssembler::lshl(Register hi, Register lo) {
249 // Java shift left long support (semantics as described in JVM spec., p.305)
250 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
251 // shift value is in rcx !
252 assert(hi != rcx, "must not use rcx");
253 assert(lo != rcx, "must not use rcx");
254 const Register s = rcx; // shift count
255 const int n = BitsPerWord;
256 Label L;
257 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
258 cmpl(s, n); // if (s < n)
259 jcc(Assembler::less, L); // else (s >= n)
260 movl(hi, lo); // x := x << n
261 xorl(lo, lo);
262 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
263 bind(L); // s (mod n) < n
264 shldl(hi, lo); // x := x << s
265 shll(lo);
266 }
267
268
269 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
270 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
271 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
272 assert(hi != rcx, "must not use rcx");
273 assert(lo != rcx, "must not use rcx");
274 const Register s = rcx; // shift count
275 const int n = BitsPerWord;
276 Label L;
277 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
278 cmpl(s, n); // if (s < n)
279 jcc(Assembler::less, L); // else (s >= n)
280 movl(lo, hi); // x := x >> n
281 if (sign_extension) sarl(hi, 31);
282 else xorl(hi, hi);
283 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
284 bind(L); // s (mod n) < n
285 shrdl(lo, hi); // x := x >> s
286 if (sign_extension) sarl(hi);
287 else shrl(hi);
288 }
289
290 void MacroAssembler::movoop(Register dst, jobject obj) {
291 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
292 }
293
294 void MacroAssembler::movoop(Address dst, jobject obj) {
295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
296 }
297
298 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
299 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
300 }
301
302 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
304 }
305
306 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
307 // scratch register is not used,
308 // it is defined to match parameters of 64-bit version of this method.
309 if (src.is_lval()) {
310 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
311 } else {
312 movl(dst, as_Address(src));
313 }
314 }
315
316 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
317 movl(as_Address(dst), src);
318 }
319
320 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
321 movl(dst, as_Address(src));
322 }
323
324 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
325 void MacroAssembler::movptr(Address dst, intptr_t src) {
326 movl(dst, src);
327 }
328
329
330 void MacroAssembler::pop_callee_saved_registers() {
331 pop(rcx);
332 pop(rdx);
333 pop(rdi);
334 pop(rsi);
335 }
336
337 void MacroAssembler::pop_fTOS() {
338 fld_d(Address(rsp, 0));
339 addl(rsp, 2 * wordSize);
340 }
341
342 void MacroAssembler::push_callee_saved_registers() {
343 push(rsi);
344 push(rdi);
345 push(rdx);
346 push(rcx);
347 }
348
349 void MacroAssembler::push_fTOS() {
350 subl(rsp, 2 * wordSize);
351 fstp_d(Address(rsp, 0));
352 }
353
354
355 void MacroAssembler::pushoop(jobject obj) {
356 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
357 }
358
359 void MacroAssembler::pushklass(Metadata* obj) {
360 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
361 }
362
363 void MacroAssembler::pushptr(AddressLiteral src) {
364 if (src.is_lval()) {
365 push_literal32((int32_t)src.target(), src.rspec());
366 } else {
367 pushl(as_Address(src));
368 }
369 }
370
371 void MacroAssembler::set_word_if_not_zero(Register dst) {
372 xorl(dst, dst);
373 set_byte_if_not_zero(dst);
374 }
375
376 static void pass_arg0(MacroAssembler* masm, Register arg) {
377 masm->push(arg);
378 }
379
380 static void pass_arg1(MacroAssembler* masm, Register arg) {
381 masm->push(arg);
382 }
383
384 static void pass_arg2(MacroAssembler* masm, Register arg) {
385 masm->push(arg);
386 }
387
388 static void pass_arg3(MacroAssembler* masm, Register arg) {
389 masm->push(arg);
390 }
391
392 #ifndef PRODUCT
393 extern "C" void findpc(intptr_t x);
394 #endif
395
396 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
397 // In order to get locks to work, we need to fake a in_VM state
398 JavaThread* thread = JavaThread::current();
399 JavaThreadState saved_state = thread->thread_state();
400 thread->set_thread_state(_thread_in_vm);
401 if (ShowMessageBoxOnError) {
402 JavaThread* thread = JavaThread::current();
403 JavaThreadState saved_state = thread->thread_state();
404 thread->set_thread_state(_thread_in_vm);
405 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
406 ttyLocker ttyl;
407 BytecodeCounter::print();
408 }
409 // To see where a verify_oop failed, get $ebx+40/X for this frame.
410 // This is the value of eip which points to where verify_oop will return.
411 if (os::message_box(msg, "Execution stopped, print registers?")) {
412 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
413 BREAKPOINT;
414 }
415 } else {
416 ttyLocker ttyl;
417 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
418 }
419 // Don't assert holding the ttyLock
420 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
421 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
422 }
423
424 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
425 ttyLocker ttyl;
426 FlagSetting fs(Debugging, true);
427 tty->print_cr("eip = 0x%08x", eip);
428 #ifndef PRODUCT
429 if ((WizardMode || Verbose) && PrintMiscellaneous) {
430 tty->cr();
431 findpc(eip);
432 tty->cr();
433 }
434 #endif
435 #define PRINT_REG(rax) \
436 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
437 PRINT_REG(rax);
438 PRINT_REG(rbx);
439 PRINT_REG(rcx);
440 PRINT_REG(rdx);
441 PRINT_REG(rdi);
442 PRINT_REG(rsi);
443 PRINT_REG(rbp);
444 PRINT_REG(rsp);
445 #undef PRINT_REG
446 // Print some words near top of staack.
447 int* dump_sp = (int*) rsp;
448 for (int col1 = 0; col1 < 8; col1++) {
449 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
450 os::print_location(tty, *dump_sp++);
451 }
452 for (int row = 0; row < 16; row++) {
453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
454 for (int col = 0; col < 8; col++) {
455 tty->print(" 0x%08x", *dump_sp++);
456 }
457 tty->cr();
458 }
459 // Print some instructions around pc:
460 Disassembler::decode((address)eip-64, (address)eip);
461 tty->print_cr("--------");
462 Disassembler::decode((address)eip, (address)eip+32);
463 }
464
465 void MacroAssembler::stop(const char* msg) {
466 ExternalAddress message((address)msg);
467 // push address of message
468 pushptr(message.addr());
469 { Label L; call(L, relocInfo::none); bind(L); } // push eip
470 pusha(); // push registers
471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
472 hlt();
473 }
474
475 void MacroAssembler::warn(const char* msg) {
476 push_CPU_state();
477
478 ExternalAddress message((address) msg);
479 // push address of message
480 pushptr(message.addr());
481
482 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
483 addl(rsp, wordSize); // discard argument
484 pop_CPU_state();
485 }
486
487 void MacroAssembler::print_state() {
488 { Label L; call(L, relocInfo::none); bind(L); } // push eip
489 pusha(); // push registers
490
491 push_CPU_state();
492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
493 pop_CPU_state();
494
495 popa();
496 addl(rsp, wordSize);
497 }
498
499 #else // _LP64
500
501 // 64 bit versions
502
503 Address MacroAssembler::as_Address(AddressLiteral adr) {
504 // amd64 always does this as a pc-rel
505 // we can be absolute or disp based on the instruction type
506 // jmp/call are displacements others are absolute
507 assert(!adr.is_lval(), "must be rval");
508 assert(reachable(adr), "must be");
509 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
510
511 }
512
513 Address MacroAssembler::as_Address(ArrayAddress adr) {
514 AddressLiteral base = adr.base();
515 lea(rscratch1, base);
516 Address index = adr.index();
517 assert(index._disp == 0, "must not have disp"); // maybe it can?
518 Address array(rscratch1, index._index, index._scale, index._disp);
519 return array;
520 }
521
522 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
523 Label L, E;
524
525 #ifdef _WIN64
526 // Windows always allocates space for it's register args
527 assert(num_args <= 4, "only register arguments supported");
528 subq(rsp, frame::arg_reg_save_area_bytes);
529 #endif
530
531 // Align stack if necessary
532 testl(rsp, 15);
533 jcc(Assembler::zero, L);
534
535 subq(rsp, 8);
536 {
537 call(RuntimeAddress(entry_point));
538 }
539 addq(rsp, 8);
540 jmp(E);
541
542 bind(L);
543 {
544 call(RuntimeAddress(entry_point));
545 }
546
547 bind(E);
548
549 #ifdef _WIN64
550 // restore stack pointer
551 addq(rsp, frame::arg_reg_save_area_bytes);
552 #endif
553
554 }
555
556 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
557 assert(!src2.is_lval(), "should use cmpptr");
558
559 if (reachable(src2)) {
560 cmpq(src1, as_Address(src2));
561 } else {
562 lea(rscratch1, src2);
563 Assembler::cmpq(src1, Address(rscratch1, 0));
564 }
565 }
566
567 int MacroAssembler::corrected_idivq(Register reg) {
568 // Full implementation of Java ldiv and lrem; checks for special
569 // case as described in JVM spec., p.243 & p.271. The function
570 // returns the (pc) offset of the idivl instruction - may be needed
571 // for implicit exceptions.
572 //
573 // normal case special case
574 //
575 // input : rax: dividend min_long
576 // reg: divisor (may not be eax/edx) -1
577 //
578 // output: rax: quotient (= rax idiv reg) min_long
579 // rdx: remainder (= rax irem reg) 0
580 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
581 static const int64_t min_long = 0x8000000000000000;
582 Label normal_case, special_case;
583
584 // check for special case
585 cmp64(rax, ExternalAddress((address) &min_long));
586 jcc(Assembler::notEqual, normal_case);
587 xorl(rdx, rdx); // prepare rdx for possible special case (where
588 // remainder = 0)
589 cmpq(reg, -1);
590 jcc(Assembler::equal, special_case);
591
592 // handle normal case
593 bind(normal_case);
594 cdqq();
595 int idivq_offset = offset();
596 idivq(reg);
597
598 // normal and special case exit
599 bind(special_case);
600
601 return idivq_offset;
602 }
603
604 void MacroAssembler::decrementq(Register reg, int value) {
605 if (value == min_jint) { subq(reg, value); return; }
606 if (value < 0) { incrementq(reg, -value); return; }
607 if (value == 0) { ; return; }
608 if (value == 1 && UseIncDec) { decq(reg) ; return; }
609 /* else */ { subq(reg, value) ; return; }
610 }
611
612 void MacroAssembler::decrementq(Address dst, int value) {
613 if (value == min_jint) { subq(dst, value); return; }
614 if (value < 0) { incrementq(dst, -value); return; }
615 if (value == 0) { ; return; }
616 if (value == 1 && UseIncDec) { decq(dst) ; return; }
617 /* else */ { subq(dst, value) ; return; }
618 }
619
620 void MacroAssembler::incrementq(AddressLiteral dst) {
621 if (reachable(dst)) {
622 incrementq(as_Address(dst));
623 } else {
624 lea(rscratch1, dst);
625 incrementq(Address(rscratch1, 0));
626 }
627 }
628
629 void MacroAssembler::incrementq(Register reg, int value) {
630 if (value == min_jint) { addq(reg, value); return; }
631 if (value < 0) { decrementq(reg, -value); return; }
632 if (value == 0) { ; return; }
633 if (value == 1 && UseIncDec) { incq(reg) ; return; }
634 /* else */ { addq(reg, value) ; return; }
635 }
636
637 void MacroAssembler::incrementq(Address dst, int value) {
638 if (value == min_jint) { addq(dst, value); return; }
639 if (value < 0) { decrementq(dst, -value); return; }
640 if (value == 0) { ; return; }
641 if (value == 1 && UseIncDec) { incq(dst) ; return; }
642 /* else */ { addq(dst, value) ; return; }
643 }
644
645 // 32bit can do a case table jump in one instruction but we no longer allow the base
646 // to be installed in the Address class
647 void MacroAssembler::jump(ArrayAddress entry) {
648 lea(rscratch1, entry.base());
649 Address dispatch = entry.index();
650 assert(dispatch._base == noreg, "must be");
651 dispatch._base = rscratch1;
652 jmp(dispatch);
653 }
654
655 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 cmpq(x_lo, y_lo);
658 }
659
660 void MacroAssembler::lea(Register dst, AddressLiteral src) {
661 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
662 }
663
664 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
665 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
666 movptr(dst, rscratch1);
667 }
668
669 void MacroAssembler::leave() {
670 // %%% is this really better? Why not on 32bit too?
671 emit_int8((unsigned char)0xC9); // LEAVE
672 }
673
674 void MacroAssembler::lneg(Register hi, Register lo) {
675 ShouldNotReachHere(); // 64bit doesn't use two regs
676 negq(lo);
677 }
678
679 void MacroAssembler::movoop(Register dst, jobject obj) {
680 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
681 }
682
683 void MacroAssembler::movoop(Address dst, jobject obj) {
684 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
685 movq(dst, rscratch1);
686 }
687
688 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
689 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
690 }
691
692 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
693 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
694 movq(dst, rscratch1);
695 }
696
697 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
698 if (src.is_lval()) {
699 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
700 } else {
701 if (reachable(src)) {
702 movq(dst, as_Address(src));
703 } else {
704 lea(scratch, src);
705 movq(dst, Address(scratch, 0));
706 }
707 }
708 }
709
710 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
711 movq(as_Address(dst), src);
712 }
713
714 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
715 movq(dst, as_Address(src));
716 }
717
718 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
719 void MacroAssembler::movptr(Address dst, intptr_t src) {
720 mov64(rscratch1, src);
721 movq(dst, rscratch1);
722 }
723
724 // These are mostly for initializing NULL
725 void MacroAssembler::movptr(Address dst, int32_t src) {
726 movslq(dst, src);
727 }
728
729 void MacroAssembler::movptr(Register dst, int32_t src) {
730 mov64(dst, (intptr_t)src);
731 }
732
733 void MacroAssembler::pushoop(jobject obj) {
734 movoop(rscratch1, obj);
735 push(rscratch1);
736 }
737
738 void MacroAssembler::pushklass(Metadata* obj) {
739 mov_metadata(rscratch1, obj);
740 push(rscratch1);
741 }
742
743 void MacroAssembler::pushptr(AddressLiteral src) {
744 lea(rscratch1, src);
745 if (src.is_lval()) {
746 push(rscratch1);
747 } else {
748 pushq(Address(rscratch1, 0));
749 }
750 }
751
752 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
753 bool clear_pc) {
754 // we must set sp to zero to clear frame
755 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
756 // must clear fp, so that compiled frames are not confused; it is
757 // possible that we need it only for debugging
758 if (clear_fp) {
759 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
760 }
761
762 if (clear_pc) {
763 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
764 }
765 }
766
767 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
768 Register last_java_fp,
769 address last_java_pc) {
770 // determine last_java_sp register
771 if (!last_java_sp->is_valid()) {
772 last_java_sp = rsp;
773 }
774
775 // last_java_fp is optional
776 if (last_java_fp->is_valid()) {
777 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
778 last_java_fp);
779 }
780
781 // last_java_pc is optional
782 if (last_java_pc != NULL) {
783 Address java_pc(r15_thread,
784 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
785 lea(rscratch1, InternalAddress(last_java_pc));
786 movptr(java_pc, rscratch1);
787 }
788
789 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
790 }
791
792 static void pass_arg0(MacroAssembler* masm, Register arg) {
793 if (c_rarg0 != arg ) {
794 masm->mov(c_rarg0, arg);
795 }
796 }
797
798 static void pass_arg1(MacroAssembler* masm, Register arg) {
799 if (c_rarg1 != arg ) {
800 masm->mov(c_rarg1, arg);
801 }
802 }
803
804 static void pass_arg2(MacroAssembler* masm, Register arg) {
805 if (c_rarg2 != arg ) {
806 masm->mov(c_rarg2, arg);
807 }
808 }
809
810 static void pass_arg3(MacroAssembler* masm, Register arg) {
811 if (c_rarg3 != arg ) {
812 masm->mov(c_rarg3, arg);
813 }
814 }
815
816 void MacroAssembler::stop(const char* msg) {
817 address rip = pc();
818 pusha(); // get regs on stack
819 lea(c_rarg0, ExternalAddress((address) msg));
820 lea(c_rarg1, InternalAddress(rip));
821 movq(c_rarg2, rsp); // pass pointer to regs array
822 andq(rsp, -16); // align stack as required by ABI
823 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
824 hlt();
825 }
826
827 void MacroAssembler::warn(const char* msg) {
828 push(rbp);
829 movq(rbp, rsp);
830 andq(rsp, -16); // align stack as required by push_CPU_state and call
831 push_CPU_state(); // keeps alignment at 16 bytes
832 lea(c_rarg0, ExternalAddress((address) msg));
833 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
834 pop_CPU_state();
835 mov(rsp, rbp);
836 pop(rbp);
837 }
838
839 void MacroAssembler::print_state() {
840 address rip = pc();
841 pusha(); // get regs on stack
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846
847 lea(c_rarg0, InternalAddress(rip));
848 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
849 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
850
851 pop_CPU_state();
852 mov(rsp, rbp);
853 pop(rbp);
854 popa();
855 }
856
857 #ifndef PRODUCT
858 extern "C" void findpc(intptr_t x);
859 #endif
860
861 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
862 // In order to get locks to work, we need to fake a in_VM state
863 if (ShowMessageBoxOnError) {
864 JavaThread* thread = JavaThread::current();
865 JavaThreadState saved_state = thread->thread_state();
866 thread->set_thread_state(_thread_in_vm);
867 #ifndef PRODUCT
868 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
869 ttyLocker ttyl;
870 BytecodeCounter::print();
871 }
872 #endif
873 // To see where a verify_oop failed, get $ebx+40/X for this frame.
874 // XXX correct this offset for amd64
875 // This is the value of eip which points to where verify_oop will return.
876 if (os::message_box(msg, "Execution stopped, print registers?")) {
877 print_state64(pc, regs);
878 BREAKPOINT;
879 assert(false, "start up GDB");
880 }
881 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
882 } else {
883 ttyLocker ttyl;
884 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
885 msg);
886 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
887 }
888 }
889
890 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
891 ttyLocker ttyl;
892 FlagSetting fs(Debugging, true);
893 tty->print_cr("rip = 0x%016lx", pc);
894 #ifndef PRODUCT
895 tty->cr();
896 findpc(pc);
897 tty->cr();
898 #endif
899 #define PRINT_REG(rax, value) \
900 { tty->print("%s = ", #rax); os::print_location(tty, value); }
901 PRINT_REG(rax, regs[15]);
902 PRINT_REG(rbx, regs[12]);
903 PRINT_REG(rcx, regs[14]);
904 PRINT_REG(rdx, regs[13]);
905 PRINT_REG(rdi, regs[8]);
906 PRINT_REG(rsi, regs[9]);
907 PRINT_REG(rbp, regs[10]);
908 PRINT_REG(rsp, regs[11]);
909 PRINT_REG(r8 , regs[7]);
910 PRINT_REG(r9 , regs[6]);
911 PRINT_REG(r10, regs[5]);
912 PRINT_REG(r11, regs[4]);
913 PRINT_REG(r12, regs[3]);
914 PRINT_REG(r13, regs[2]);
915 PRINT_REG(r14, regs[1]);
916 PRINT_REG(r15, regs[0]);
917 #undef PRINT_REG
918 // Print some words near top of staack.
919 int64_t* rsp = (int64_t*) regs[11];
920 int64_t* dump_sp = rsp;
921 for (int col1 = 0; col1 < 8; col1++) {
922 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
923 os::print_location(tty, *dump_sp++);
924 }
925 for (int row = 0; row < 25; row++) {
926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
927 for (int col = 0; col < 4; col++) {
928 tty->print(" 0x%016lx", *dump_sp++);
929 }
930 tty->cr();
931 }
932 // Print some instructions around pc:
933 Disassembler::decode((address)pc-64, (address)pc);
934 tty->print_cr("--------");
935 Disassembler::decode((address)pc, (address)pc+32);
936 }
937
938 #endif // _LP64
939
940 // Now versions that are common to 32/64 bit
941
942 void MacroAssembler::addptr(Register dst, int32_t imm32) {
943 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
944 }
945
946 void MacroAssembler::addptr(Register dst, Register src) {
947 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
948 }
949
950 void MacroAssembler::addptr(Address dst, Register src) {
951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
952 }
953
954 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
955 if (reachable(src)) {
956 Assembler::addsd(dst, as_Address(src));
957 } else {
958 lea(rscratch1, src);
959 Assembler::addsd(dst, Address(rscratch1, 0));
960 }
961 }
962
963 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
964 if (reachable(src)) {
965 addss(dst, as_Address(src));
966 } else {
967 lea(rscratch1, src);
968 addss(dst, Address(rscratch1, 0));
969 }
970 }
971
972 void MacroAssembler::align(int modulus) {
973 if (offset() % modulus != 0) {
974 nop(modulus - (offset() % modulus));
975 }
976 }
977
978 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
979 // Used in sign-masking with aligned address.
980 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
981 if (reachable(src)) {
982 Assembler::andpd(dst, as_Address(src));
983 } else {
984 lea(rscratch1, src);
985 Assembler::andpd(dst, Address(rscratch1, 0));
986 }
987 }
988
989 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
990 // Used in sign-masking with aligned address.
991 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
992 if (reachable(src)) {
993 Assembler::andps(dst, as_Address(src));
994 } else {
995 lea(rscratch1, src);
996 Assembler::andps(dst, Address(rscratch1, 0));
997 }
998 }
999
1000 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1001 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1002 }
1003
1004 void MacroAssembler::atomic_incl(Address counter_addr) {
1005 if (os::is_MP())
1006 lock();
1007 incrementl(counter_addr);
1008 }
1009
1010 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1011 if (reachable(counter_addr)) {
1012 atomic_incl(as_Address(counter_addr));
1013 } else {
1014 lea(scr, counter_addr);
1015 atomic_incl(Address(scr, 0));
1016 }
1017 }
1018
1019 #ifdef _LP64
1020 void MacroAssembler::atomic_incq(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementq(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incq(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incq(Address(scr, 0));
1032 }
1033 }
1034 #endif
1035
1036 // Writes to stack successive pages until offset reached to check for
1037 // stack overflow + shadow pages. This clobbers tmp.
1038 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1039 movptr(tmp, rsp);
1040 // Bang stack for total size given plus shadow page size.
1041 // Bang one page at a time because large size can bang beyond yellow and
1042 // red zones.
1043 Label loop;
1044 bind(loop);
1045 movl(Address(tmp, (-os::vm_page_size())), size );
1046 subptr(tmp, os::vm_page_size());
1047 subl(size, os::vm_page_size());
1048 jcc(Assembler::greater, loop);
1049
1050 // Bang down shadow pages too.
1051 // At this point, (tmp-0) is the last address touched, so don't
1052 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1053 // was post-decremented.) Skip this address by starting at i=1, and
1054 // touch a few more pages below. N.B. It is important to touch all
1055 // the way down to and including i=StackShadowPages.
1056 for (int i = 1; i < StackShadowPages; i++) {
1057 // this could be any sized move but this is can be a debugging crumb
1058 // so the bigger the better.
1059 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1060 }
1061 }
1062
1063 int MacroAssembler::biased_locking_enter(Register lock_reg,
1064 Register obj_reg,
1065 Register swap_reg,
1066 Register tmp_reg,
1067 bool swap_reg_contains_mark,
1068 Label& done,
1069 Label* slow_case,
1070 BiasedLockingCounters* counters) {
1071 assert(UseBiasedLocking, "why call this otherwise?");
1072 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1073 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1074 bool need_tmp_reg = false;
1075 if (tmp_reg == noreg) {
1076 need_tmp_reg = true;
1077 tmp_reg = lock_reg;
1078 assert_different_registers(lock_reg, obj_reg, swap_reg);
1079 } else {
1080 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1081 }
1082 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1083 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1084 Address saved_mark_addr(lock_reg, 0);
1085
1086 if (PrintBiasedLockingStatistics && counters == NULL) {
1087 counters = BiasedLocking::counters();
1088 }
1089 // Biased locking
1090 // See whether the lock is currently biased toward our thread and
1091 // whether the epoch is still valid
1092 // Note that the runtime guarantees sufficient alignment of JavaThread
1093 // pointers to allow age to be placed into low bits
1094 // First check to see whether biasing is even enabled for this object
1095 Label cas_label;
1096 int null_check_offset = -1;
1097 if (!swap_reg_contains_mark) {
1098 null_check_offset = offset();
1099 movptr(swap_reg, mark_addr);
1100 }
1101 if (need_tmp_reg) {
1102 push(tmp_reg);
1103 }
1104 movptr(tmp_reg, swap_reg);
1105 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1106 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1107 if (need_tmp_reg) {
1108 pop(tmp_reg);
1109 }
1110 jcc(Assembler::notEqual, cas_label);
1111 // The bias pattern is present in the object's header. Need to check
1112 // whether the bias owner and the epoch are both still current.
1113 #ifndef _LP64
1114 // Note that because there is no current thread register on x86_32 we
1115 // need to store off the mark word we read out of the object to
1116 // avoid reloading it and needing to recheck invariants below. This
1117 // store is unfortunate but it makes the overall code shorter and
1118 // simpler.
1119 movptr(saved_mark_addr, swap_reg);
1120 #endif
1121 if (need_tmp_reg) {
1122 push(tmp_reg);
1123 }
1124 if (swap_reg_contains_mark) {
1125 null_check_offset = offset();
1126 }
1127 load_prototype_header(tmp_reg, obj_reg);
1128 #ifdef _LP64
1129 orptr(tmp_reg, r15_thread);
1130 xorptr(tmp_reg, swap_reg);
1131 Register header_reg = tmp_reg;
1132 #else
1133 xorptr(tmp_reg, swap_reg);
1134 get_thread(swap_reg);
1135 xorptr(swap_reg, tmp_reg);
1136 Register header_reg = swap_reg;
1137 #endif
1138 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1139 if (need_tmp_reg) {
1140 pop(tmp_reg);
1141 }
1142 if (counters != NULL) {
1143 cond_inc32(Assembler::zero,
1144 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1145 }
1146 jcc(Assembler::equal, done);
1147
1148 Label try_revoke_bias;
1149 Label try_rebias;
1150
1151 // At this point we know that the header has the bias pattern and
1152 // that we are not the bias owner in the current epoch. We need to
1153 // figure out more details about the state of the header in order to
1154 // know what operations can be legally performed on the object's
1155 // header.
1156
1157 // If the low three bits in the xor result aren't clear, that means
1158 // the prototype header is no longer biased and we have to revoke
1159 // the bias on this object.
1160 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1161 jccb(Assembler::notZero, try_revoke_bias);
1162
1163 // Biasing is still enabled for this data type. See whether the
1164 // epoch of the current bias is still valid, meaning that the epoch
1165 // bits of the mark word are equal to the epoch bits of the
1166 // prototype header. (Note that the prototype header's epoch bits
1167 // only change at a safepoint.) If not, attempt to rebias the object
1168 // toward the current thread. Note that we must be absolutely sure
1169 // that the current epoch is invalid in order to do this because
1170 // otherwise the manipulations it performs on the mark word are
1171 // illegal.
1172 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1173 jccb(Assembler::notZero, try_rebias);
1174
1175 // The epoch of the current bias is still valid but we know nothing
1176 // about the owner; it might be set or it might be clear. Try to
1177 // acquire the bias of the object using an atomic operation. If this
1178 // fails we will go in to the runtime to revoke the object's bias.
1179 // Note that we first construct the presumed unbiased header so we
1180 // don't accidentally blow away another thread's valid bias.
1181 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1182 andptr(swap_reg,
1183 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1184 if (need_tmp_reg) {
1185 push(tmp_reg);
1186 }
1187 #ifdef _LP64
1188 movptr(tmp_reg, swap_reg);
1189 orptr(tmp_reg, r15_thread);
1190 #else
1191 get_thread(tmp_reg);
1192 orptr(tmp_reg, swap_reg);
1193 #endif
1194 if (os::is_MP()) {
1195 lock();
1196 }
1197 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1198 if (need_tmp_reg) {
1199 pop(tmp_reg);
1200 }
1201 // If the biasing toward our thread failed, this means that
1202 // another thread succeeded in biasing it toward itself and we
1203 // need to revoke that bias. The revocation will occur in the
1204 // interpreter runtime in the slow case.
1205 if (counters != NULL) {
1206 cond_inc32(Assembler::zero,
1207 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1208 }
1209 if (slow_case != NULL) {
1210 jcc(Assembler::notZero, *slow_case);
1211 }
1212 jmp(done);
1213
1214 bind(try_rebias);
1215 // At this point we know the epoch has expired, meaning that the
1216 // current "bias owner", if any, is actually invalid. Under these
1217 // circumstances _only_, we are allowed to use the current header's
1218 // value as the comparison value when doing the cas to acquire the
1219 // bias in the current epoch. In other words, we allow transfer of
1220 // the bias from one thread to another directly in this situation.
1221 //
1222 // FIXME: due to a lack of registers we currently blow away the age
1223 // bits in this situation. Should attempt to preserve them.
1224 if (need_tmp_reg) {
1225 push(tmp_reg);
1226 }
1227 load_prototype_header(tmp_reg, obj_reg);
1228 #ifdef _LP64
1229 orptr(tmp_reg, r15_thread);
1230 #else
1231 get_thread(swap_reg);
1232 orptr(tmp_reg, swap_reg);
1233 movptr(swap_reg, saved_mark_addr);
1234 #endif
1235 if (os::is_MP()) {
1236 lock();
1237 }
1238 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1239 if (need_tmp_reg) {
1240 pop(tmp_reg);
1241 }
1242 // If the biasing toward our thread failed, then another thread
1243 // succeeded in biasing it toward itself and we need to revoke that
1244 // bias. The revocation will occur in the runtime in the slow case.
1245 if (counters != NULL) {
1246 cond_inc32(Assembler::zero,
1247 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1248 }
1249 if (slow_case != NULL) {
1250 jcc(Assembler::notZero, *slow_case);
1251 }
1252 jmp(done);
1253
1254 bind(try_revoke_bias);
1255 // The prototype mark in the klass doesn't have the bias bit set any
1256 // more, indicating that objects of this data type are not supposed
1257 // to be biased any more. We are going to try to reset the mark of
1258 // this object to the prototype value and fall through to the
1259 // CAS-based locking scheme. Note that if our CAS fails, it means
1260 // that another thread raced us for the privilege of revoking the
1261 // bias of this particular object, so it's okay to continue in the
1262 // normal locking code.
1263 //
1264 // FIXME: due to a lack of registers we currently blow away the age
1265 // bits in this situation. Should attempt to preserve them.
1266 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1267 if (need_tmp_reg) {
1268 push(tmp_reg);
1269 }
1270 load_prototype_header(tmp_reg, obj_reg);
1271 if (os::is_MP()) {
1272 lock();
1273 }
1274 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1275 if (need_tmp_reg) {
1276 pop(tmp_reg);
1277 }
1278 // Fall through to the normal CAS-based lock, because no matter what
1279 // the result of the above CAS, some thread must have succeeded in
1280 // removing the bias bit from the object's header.
1281 if (counters != NULL) {
1282 cond_inc32(Assembler::zero,
1283 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1284 }
1285
1286 bind(cas_label);
1287
1288 return null_check_offset;
1289 }
1290
1291 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1292 assert(UseBiasedLocking, "why call this otherwise?");
1293
1294 // Check for biased locking unlock case, which is a no-op
1295 // Note: we do not have to check the thread ID for two reasons.
1296 // First, the interpreter checks for IllegalMonitorStateException at
1297 // a higher level. Second, if the bias was revoked while we held the
1298 // lock, the object could not be rebiased toward another thread, so
1299 // the bias bit would be clear.
1300 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1301 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1302 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1303 jcc(Assembler::equal, done);
1304 }
1305
1306 #ifdef COMPILER2
1307
1308 #if INCLUDE_RTM_OPT
1309
1310 // Update rtm_counters based on abort status
1311 // input: abort_status
1312 // rtm_counters (RTMLockingCounters*)
1313 // flags are killed
1314 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1315
1316 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1317 if (PrintPreciseRTMLockingStatistics) {
1318 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1319 Label check_abort;
1320 testl(abort_status, (1<<i));
1321 jccb(Assembler::equal, check_abort);
1322 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1323 bind(check_abort);
1324 }
1325 }
1326 }
1327
1328 // Branch if (random & (count-1) != 0), count is 2^n
1329 // tmp, scr and flags are killed
1330 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1331 assert(tmp == rax, "");
1332 assert(scr == rdx, "");
1333 rdtsc(); // modifies EDX:EAX
1334 andptr(tmp, count-1);
1335 jccb(Assembler::notZero, brLabel);
1336 }
1337
1338 // Perform abort ratio calculation, set no_rtm bit if high ratio
1339 // input: rtm_counters_Reg (RTMLockingCounters* address)
1340 // tmpReg, rtm_counters_Reg and flags are killed
1341 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1342 Register rtm_counters_Reg,
1343 RTMLockingCounters* rtm_counters,
1344 Metadata* method_data) {
1345 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1346
1347 if (RTMLockingCalculationDelay > 0) {
1348 // Delay calculation
1349 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1350 testptr(tmpReg, tmpReg);
1351 jccb(Assembler::equal, L_done);
1352 }
1353 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1354 // Aborted transactions = abort_count * 100
1355 // All transactions = total_count * RTMTotalCountIncrRate
1356 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1357
1358 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1359 cmpptr(tmpReg, RTMAbortThreshold);
1360 jccb(Assembler::below, L_check_always_rtm2);
1361 imulptr(tmpReg, tmpReg, 100);
1362
1363 Register scrReg = rtm_counters_Reg;
1364 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1365 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1366 imulptr(scrReg, scrReg, RTMAbortRatio);
1367 cmpptr(tmpReg, scrReg);
1368 jccb(Assembler::below, L_check_always_rtm1);
1369 if (method_data != NULL) {
1370 // set rtm_state to "no rtm" in MDO
1371 mov_metadata(tmpReg, method_data);
1372 if (os::is_MP()) {
1373 lock();
1374 }
1375 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1376 }
1377 jmpb(L_done);
1378 bind(L_check_always_rtm1);
1379 // Reload RTMLockingCounters* address
1380 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1381 bind(L_check_always_rtm2);
1382 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1383 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1384 jccb(Assembler::below, L_done);
1385 if (method_data != NULL) {
1386 // set rtm_state to "always rtm" in MDO
1387 mov_metadata(tmpReg, method_data);
1388 if (os::is_MP()) {
1389 lock();
1390 }
1391 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1392 }
1393 bind(L_done);
1394 }
1395
1396 // Update counters and perform abort ratio calculation
1397 // input: abort_status_Reg
1398 // rtm_counters_Reg, flags are killed
1399 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1400 Register rtm_counters_Reg,
1401 RTMLockingCounters* rtm_counters,
1402 Metadata* method_data,
1403 bool profile_rtm) {
1404
1405 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1406 // update rtm counters based on rax value at abort
1407 // reads abort_status_Reg, updates flags
1408 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1409 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1410 if (profile_rtm) {
1411 // Save abort status because abort_status_Reg is used by following code.
1412 if (RTMRetryCount > 0) {
1413 push(abort_status_Reg);
1414 }
1415 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1416 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1417 // restore abort status
1418 if (RTMRetryCount > 0) {
1419 pop(abort_status_Reg);
1420 }
1421 }
1422 }
1423
1424 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1425 // inputs: retry_count_Reg
1426 // : abort_status_Reg
1427 // output: retry_count_Reg decremented by 1
1428 // flags are killed
1429 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1430 Label doneRetry;
1431 assert(abort_status_Reg == rax, "");
1432 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1433 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1434 // if reason is in 0x6 and retry count != 0 then retry
1435 andptr(abort_status_Reg, 0x6);
1436 jccb(Assembler::zero, doneRetry);
1437 testl(retry_count_Reg, retry_count_Reg);
1438 jccb(Assembler::zero, doneRetry);
1439 pause();
1440 decrementl(retry_count_Reg);
1441 jmp(retryLabel);
1442 bind(doneRetry);
1443 }
1444
1445 // Spin and retry if lock is busy,
1446 // inputs: box_Reg (monitor address)
1447 // : retry_count_Reg
1448 // output: retry_count_Reg decremented by 1
1449 // : clear z flag if retry count exceeded
1450 // tmp_Reg, scr_Reg, flags are killed
1451 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1452 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1453 Label SpinLoop, SpinExit, doneRetry;
1454 // Clean monitor_value bit to get valid pointer
1455 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1456
1457 testl(retry_count_Reg, retry_count_Reg);
1458 jccb(Assembler::zero, doneRetry);
1459 decrementl(retry_count_Reg);
1460 movptr(scr_Reg, RTMSpinLoopCount);
1461
1462 bind(SpinLoop);
1463 pause();
1464 decrementl(scr_Reg);
1465 jccb(Assembler::lessEqual, SpinExit);
1466 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1467 testptr(tmp_Reg, tmp_Reg);
1468 jccb(Assembler::notZero, SpinLoop);
1469
1470 bind(SpinExit);
1471 jmp(retryLabel);
1472 bind(doneRetry);
1473 incrementl(retry_count_Reg); // clear z flag
1474 }
1475
1476 // Use RTM for normal stack locks
1477 // Input: objReg (object to lock)
1478 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1479 Register retry_on_abort_count_Reg,
1480 RTMLockingCounters* stack_rtm_counters,
1481 Metadata* method_data, bool profile_rtm,
1482 Label& DONE_LABEL, Label& IsInflated) {
1483 assert(UseRTMForStackLocks, "why call this otherwise?");
1484 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1485 assert(tmpReg == rax, "");
1486 assert(scrReg == rdx, "");
1487 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1488
1489 if (RTMRetryCount > 0) {
1490 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1491 bind(L_rtm_retry);
1492 }
1493 movptr(tmpReg, Address(objReg, 0));
1494 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1495 jcc(Assembler::notZero, IsInflated);
1496
1497 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1498 Label L_noincrement;
1499 if (RTMTotalCountIncrRate > 1) {
1500 // tmpReg, scrReg and flags are killed
1501 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1502 }
1503 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1504 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1505 bind(L_noincrement);
1506 }
1507 xbegin(L_on_abort);
1508 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1509 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1510 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1511 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1512
1513 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1514 if (UseRTMXendForLockBusy) {
1515 xend();
1516 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1517 jmp(L_decrement_retry);
1518 }
1519 else {
1520 xabort(0);
1521 }
1522 bind(L_on_abort);
1523 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1524 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1525 }
1526 bind(L_decrement_retry);
1527 if (RTMRetryCount > 0) {
1528 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1529 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1530 }
1531 }
1532
1533 // Use RTM for inflating locks
1534 // inputs: objReg (object to lock)
1535 // boxReg (on-stack box address (displaced header location) - KILLED)
1536 // tmpReg (ObjectMonitor address + 2(monitor_value))
1537 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1538 Register scrReg, Register retry_on_busy_count_Reg,
1539 Register retry_on_abort_count_Reg,
1540 RTMLockingCounters* rtm_counters,
1541 Metadata* method_data, bool profile_rtm,
1542 Label& DONE_LABEL) {
1543 assert(UseRTMLocking, "why call this otherwise?");
1544 assert(tmpReg == rax, "");
1545 assert(scrReg == rdx, "");
1546 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1547 // Clean monitor_value bit to get valid pointer
1548 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1549
1550 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1551 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1552 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1553
1554 if (RTMRetryCount > 0) {
1555 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1556 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1557 bind(L_rtm_retry);
1558 }
1559 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1560 Label L_noincrement;
1561 if (RTMTotalCountIncrRate > 1) {
1562 // tmpReg, scrReg and flags are killed
1563 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1564 }
1565 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1566 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1567 bind(L_noincrement);
1568 }
1569 xbegin(L_on_abort);
1570 movptr(tmpReg, Address(objReg, 0));
1571 movptr(tmpReg, Address(tmpReg, owner_offset));
1572 testptr(tmpReg, tmpReg);
1573 jcc(Assembler::zero, DONE_LABEL);
1574 if (UseRTMXendForLockBusy) {
1575 xend();
1576 jmp(L_decrement_retry);
1577 }
1578 else {
1579 xabort(0);
1580 }
1581 bind(L_on_abort);
1582 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1583 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1584 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1585 }
1586 if (RTMRetryCount > 0) {
1587 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1588 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1589 }
1590
1591 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1592 testptr(tmpReg, tmpReg) ;
1593 jccb(Assembler::notZero, L_decrement_retry) ;
1594
1595 // Appears unlocked - try to swing _owner from null to non-null.
1596 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1597 #ifdef _LP64
1598 Register threadReg = r15_thread;
1599 #else
1600 get_thread(scrReg);
1601 Register threadReg = scrReg;
1602 #endif
1603 if (os::is_MP()) {
1604 lock();
1605 }
1606 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1607
1608 if (RTMRetryCount > 0) {
1609 // success done else retry
1610 jccb(Assembler::equal, DONE_LABEL) ;
1611 bind(L_decrement_retry);
1612 // Spin and retry if lock is busy.
1613 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1614 }
1615 else {
1616 bind(L_decrement_retry);
1617 }
1618 }
1619
1620 #endif // INCLUDE_RTM_OPT
1621
1622 // Fast_Lock and Fast_Unlock used by C2
1623
1624 // Because the transitions from emitted code to the runtime
1625 // monitorenter/exit helper stubs are so slow it's critical that
1626 // we inline both the stack-locking fast-path and the inflated fast path.
1627 //
1628 // See also: cmpFastLock and cmpFastUnlock.
1629 //
1630 // What follows is a specialized inline transliteration of the code
1631 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1632 // another option would be to emit TrySlowEnter and TrySlowExit methods
1633 // at startup-time. These methods would accept arguments as
1634 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1635 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1636 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1637 // In practice, however, the # of lock sites is bounded and is usually small.
1638 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1639 // if the processor uses simple bimodal branch predictors keyed by EIP
1640 // Since the helper routines would be called from multiple synchronization
1641 // sites.
1642 //
1643 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1644 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1645 // to those specialized methods. That'd give us a mostly platform-independent
1646 // implementation that the JITs could optimize and inline at their pleasure.
1647 // Done correctly, the only time we'd need to cross to native could would be
1648 // to park() or unpark() threads. We'd also need a few more unsafe operators
1649 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1650 // (b) explicit barriers or fence operations.
1651 //
1652 // TODO:
1653 //
1654 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1655 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1656 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1657 // the lock operators would typically be faster than reifying Self.
1658 //
1659 // * Ideally I'd define the primitives as:
1660 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1661 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1662 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1663 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1664 // Furthermore the register assignments are overconstrained, possibly resulting in
1665 // sub-optimal code near the synchronization site.
1666 //
1667 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1668 // Alternately, use a better sp-proximity test.
1669 //
1670 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1671 // Either one is sufficient to uniquely identify a thread.
1672 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1673 //
1674 // * Intrinsify notify() and notifyAll() for the common cases where the
1675 // object is locked by the calling thread but the waitlist is empty.
1676 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1677 //
1678 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1679 // But beware of excessive branch density on AMD Opterons.
1680 //
1681 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1682 // or failure of the fast-path. If the fast-path fails then we pass
1683 // control to the slow-path, typically in C. In Fast_Lock and
1684 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1685 // will emit a conditional branch immediately after the node.
1686 // So we have branches to branches and lots of ICC.ZF games.
1687 // Instead, it might be better to have C2 pass a "FailureLabel"
1688 // into Fast_Lock and Fast_Unlock. In the case of success, control
1689 // will drop through the node. ICC.ZF is undefined at exit.
1690 // In the case of failure, the node will branch directly to the
1691 // FailureLabel
1692
1693
1694 // obj: object to lock
1695 // box: on-stack box address (displaced header location) - KILLED
1696 // rax,: tmp -- KILLED
1697 // scr: tmp -- KILLED
1698 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1699 Register scrReg, Register cx1Reg, Register cx2Reg,
1700 BiasedLockingCounters* counters,
1701 RTMLockingCounters* rtm_counters,
1702 RTMLockingCounters* stack_rtm_counters,
1703 Metadata* method_data,
1704 bool use_rtm, bool profile_rtm) {
1705 // Ensure the register assignents are disjoint
1706 assert(tmpReg == rax, "");
1707
1708 if (use_rtm) {
1709 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1710 } else {
1711 assert(cx1Reg == noreg, "");
1712 assert(cx2Reg == noreg, "");
1713 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1714 }
1715
1716 if (counters != NULL) {
1717 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1718 }
1719 if (EmitSync & 1) {
1720 // set box->dhw = unused_mark (3)
1721 // Force all sync thru slow-path: slow_enter() and slow_exit()
1722 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1723 cmpptr (rsp, (int32_t)NULL_WORD);
1724 } else
1725 if (EmitSync & 2) {
1726 Label DONE_LABEL ;
1727 if (UseBiasedLocking) {
1728 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1729 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1730 }
1731
1732 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1733 orptr (tmpReg, 0x1);
1734 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1735 if (os::is_MP()) {
1736 lock();
1737 }
1738 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1739 jccb(Assembler::equal, DONE_LABEL);
1740 // Recursive locking
1741 subptr(tmpReg, rsp);
1742 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1743 movptr(Address(boxReg, 0), tmpReg);
1744 bind(DONE_LABEL);
1745 } else {
1746 // Possible cases that we'll encounter in fast_lock
1747 // ------------------------------------------------
1748 // * Inflated
1749 // -- unlocked
1750 // -- Locked
1751 // = by self
1752 // = by other
1753 // * biased
1754 // -- by Self
1755 // -- by other
1756 // * neutral
1757 // * stack-locked
1758 // -- by self
1759 // = sp-proximity test hits
1760 // = sp-proximity test generates false-negative
1761 // -- by other
1762 //
1763
1764 Label IsInflated, DONE_LABEL;
1765
1766 // it's stack-locked, biased or neutral
1767 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1768 // order to reduce the number of conditional branches in the most common cases.
1769 // Beware -- there's a subtle invariant that fetch of the markword
1770 // at [FETCH], below, will never observe a biased encoding (*101b).
1771 // If this invariant is not held we risk exclusion (safety) failure.
1772 if (UseBiasedLocking && !UseOptoBiasInlining) {
1773 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, counters);
1774 }
1775
1776 #if INCLUDE_RTM_OPT
1777 if (UseRTMForStackLocks && use_rtm) {
1778 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1779 stack_rtm_counters, method_data, profile_rtm,
1780 DONE_LABEL, IsInflated);
1781 }
1782 #endif // INCLUDE_RTM_OPT
1783
1784 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1785 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1786 jccb(Assembler::notZero, IsInflated);
1787
1788 // Attempt stack-locking ...
1789 orptr (tmpReg, markOopDesc::unlocked_value);
1790 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1791 if (os::is_MP()) {
1792 lock();
1793 }
1794 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1795 if (counters != NULL) {
1796 cond_inc32(Assembler::equal,
1797 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1798 }
1799 jcc(Assembler::equal, DONE_LABEL); // Success
1800
1801 // Recursive locking.
1802 // The object is stack-locked: markword contains stack pointer to BasicLock.
1803 // Locked by current thread if difference with current SP is less than one page.
1804 subptr(tmpReg, rsp);
1805 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1806 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1807 movptr(Address(boxReg, 0), tmpReg);
1808 if (counters != NULL) {
1809 cond_inc32(Assembler::equal,
1810 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1811 }
1812 jmp(DONE_LABEL);
1813
1814 bind(IsInflated);
1815 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + 2(monitor_value)
1816
1817 #if INCLUDE_RTM_OPT
1818 // Use the same RTM locking code in 32- and 64-bit VM.
1819 if (use_rtm) {
1820 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1821 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1822 } else {
1823 #endif // INCLUDE_RTM_OPT
1824
1825 #ifndef _LP64
1826 // The object is inflated.
1827 //
1828 // TODO-FIXME: eliminate the ugly use of manifest constants:
1829 // Use markOopDesc::monitor_value instead of "2".
1830 // use markOop::unused_mark() instead of "3".
1831 // The tmpReg value is an objectMonitor reference ORed with
1832 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
1833 // objectmonitor pointer by masking off the "2" bit or we can just
1834 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
1835 // field offsets with "-2" to compensate for and annul the low-order tag bit.
1836 //
1837 // I use the latter as it avoids AGI stalls.
1838 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
1839 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
1840 //
1841 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
1842
1843 // boxReg refers to the on-stack BasicLock in the current frame.
1844 // We'd like to write:
1845 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
1846 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1847 // additional latency as we have another ST in the store buffer that must drain.
1848
1849 if (EmitSync & 8192) {
1850 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1851 get_thread (scrReg);
1852 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1853 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1854 if (os::is_MP()) {
1855 lock();
1856 }
1857 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1858 } else
1859 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1860 movptr(scrReg, boxReg);
1861 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1862
1863 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1864 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1865 // prefetchw [eax + Offset(_owner)-2]
1866 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1867 }
1868
1869 if ((EmitSync & 64) == 0) {
1870 // Optimistic form: consider XORL tmpReg,tmpReg
1871 movptr(tmpReg, NULL_WORD);
1872 } else {
1873 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1874 // Test-And-CAS instead of CAS
1875 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1876 testptr(tmpReg, tmpReg); // Locked ?
1877 jccb (Assembler::notZero, DONE_LABEL);
1878 }
1879
1880 // Appears unlocked - try to swing _owner from null to non-null.
1881 // Ideally, I'd manifest "Self" with get_thread and then attempt
1882 // to CAS the register containing Self into m->Owner.
1883 // But we don't have enough registers, so instead we can either try to CAS
1884 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1885 // we later store "Self" into m->Owner. Transiently storing a stack address
1886 // (rsp or the address of the box) into m->owner is harmless.
1887 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1888 if (os::is_MP()) {
1889 lock();
1890 }
1891 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1892 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1893 jccb (Assembler::notZero, DONE_LABEL);
1894 get_thread (scrReg); // beware: clobbers ICCs
1895 movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg);
1896 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1897
1898 // If the CAS fails we can either retry or pass control to the slow-path.
1899 // We use the latter tactic.
1900 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1901 // If the CAS was successful ...
1902 // Self has acquired the lock
1903 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1904 // Intentional fall-through into DONE_LABEL ...
1905 } else {
1906 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1907 movptr(boxReg, tmpReg);
1908
1909 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1910 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1911 // prefetchw [eax + Offset(_owner)-2]
1912 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1913 }
1914
1915 if ((EmitSync & 64) == 0) {
1916 // Optimistic form
1917 xorptr (tmpReg, tmpReg);
1918 } else {
1919 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1920 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1921 testptr(tmpReg, tmpReg); // Locked ?
1922 jccb (Assembler::notZero, DONE_LABEL);
1923 }
1924
1925 // Appears unlocked - try to swing _owner from null to non-null.
1926 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1927 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1928 get_thread (scrReg);
1929 if (os::is_MP()) {
1930 lock();
1931 }
1932 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1933
1934 // If the CAS fails we can either retry or pass control to the slow-path.
1935 // We use the latter tactic.
1936 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1937 // If the CAS was successful ...
1938 // Self has acquired the lock
1939 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1940 // Intentional fall-through into DONE_LABEL ...
1941 }
1942 #else // _LP64
1943 // It's inflated
1944
1945 // TODO: someday avoid the ST-before-CAS penalty by
1946 // relocating (deferring) the following ST.
1947 // We should also think about trying a CAS without having
1948 // fetched _owner. If the CAS is successful we may
1949 // avoid an RTO->RTS upgrade on the $line.
1950
1951 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1952 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1953
1954 movptr (boxReg, tmpReg);
1955 movptr (tmpReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1956 testptr(tmpReg, tmpReg);
1957 jccb (Assembler::notZero, DONE_LABEL);
1958
1959 // It's inflated and appears unlocked
1960 if (os::is_MP()) {
1961 lock();
1962 }
1963 cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1964 // Intentional fall-through into DONE_LABEL ...
1965 #endif // _LP64
1966
1967 #if INCLUDE_RTM_OPT
1968 } // use_rtm()
1969 #endif
1970 // DONE_LABEL is a hot target - we'd really like to place it at the
1971 // start of cache line by padding with NOPs.
1972 // See the AMD and Intel software optimization manuals for the
1973 // most efficient "long" NOP encodings.
1974 // Unfortunately none of our alignment mechanisms suffice.
1975 bind(DONE_LABEL);
1976
1977 // At DONE_LABEL the icc ZFlag is set as follows ...
1978 // Fast_Unlock uses the same protocol.
1979 // ZFlag == 1 -> Success
1980 // ZFlag == 0 -> Failure - force control through the slow-path
1981 }
1982 }
1983
1984 // obj: object to unlock
1985 // box: box address (displaced header location), killed. Must be EAX.
1986 // tmp: killed, cannot be obj nor box.
1987 //
1988 // Some commentary on balanced locking:
1989 //
1990 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1991 // Methods that don't have provably balanced locking are forced to run in the
1992 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1993 // The interpreter provides two properties:
1994 // I1: At return-time the interpreter automatically and quietly unlocks any
1995 // objects acquired the current activation (frame). Recall that the
1996 // interpreter maintains an on-stack list of locks currently held by
1997 // a frame.
1998 // I2: If a method attempts to unlock an object that is not held by the
1999 // the frame the interpreter throws IMSX.
2000 //
2001 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
2002 // B() doesn't have provably balanced locking so it runs in the interpreter.
2003 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
2004 // is still locked by A().
2005 //
2006 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
2007 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
2008 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
2009 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
2010
2011 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
2012 assert(boxReg == rax, "");
2013 assert_different_registers(objReg, boxReg, tmpReg);
2014
2015 if (EmitSync & 4) {
2016 // Disable - inhibit all inlining. Force control through the slow-path
2017 cmpptr (rsp, 0);
2018 } else
2019 if (EmitSync & 8) {
2020 Label DONE_LABEL;
2021 if (UseBiasedLocking) {
2022 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2023 }
2024 // Classic stack-locking code ...
2025 // Check whether the displaced header is 0
2026 //(=> recursive unlock)
2027 movptr(tmpReg, Address(boxReg, 0));
2028 testptr(tmpReg, tmpReg);
2029 jccb(Assembler::zero, DONE_LABEL);
2030 // If not recursive lock, reset the header to displaced header
2031 if (os::is_MP()) {
2032 lock();
2033 }
2034 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2035 bind(DONE_LABEL);
2036 } else {
2037 Label DONE_LABEL, Stacked, CheckSucc;
2038
2039 // Critically, the biased locking test must have precedence over
2040 // and appear before the (box->dhw == 0) recursive stack-lock test.
2041 if (UseBiasedLocking && !UseOptoBiasInlining) {
2042 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2043 }
2044
2045 #if INCLUDE_RTM_OPT
2046 if (UseRTMForStackLocks && use_rtm) {
2047 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2048 Label L_regular_unlock;
2049 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2050 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2051 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2052 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2053 xend(); // otherwise end...
2054 jmp(DONE_LABEL); // ... and we're done
2055 bind(L_regular_unlock);
2056 }
2057 #endif
2058
2059 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2060 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2061 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2062 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2063 jccb (Assembler::zero, Stacked);
2064
2065 // It's inflated.
2066 #if INCLUDE_RTM_OPT
2067 if (use_rtm) {
2068 Label L_regular_inflated_unlock;
2069 // Clean monitor_value bit to get valid pointer
2070 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
2071 movptr(boxReg, Address(tmpReg, owner_offset));
2072 testptr(boxReg, boxReg);
2073 jccb(Assembler::notZero, L_regular_inflated_unlock);
2074 xend();
2075 jmpb(DONE_LABEL);
2076 bind(L_regular_inflated_unlock);
2077 }
2078 #endif
2079
2080 // Despite our balanced locking property we still check that m->_owner == Self
2081 // as java routines or native JNI code called by this thread might
2082 // have released the lock.
2083 // Refer to the comments in synchronizer.cpp for how we might encode extra
2084 // state in _succ so we can avoid fetching EntryList|cxq.
2085 //
2086 // I'd like to add more cases in fast_lock() and fast_unlock() --
2087 // such as recursive enter and exit -- but we have to be wary of
2088 // I$ bloat, T$ effects and BP$ effects.
2089 //
2090 // If there's no contention try a 1-0 exit. That is, exit without
2091 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2092 // we detect and recover from the race that the 1-0 exit admits.
2093 //
2094 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2095 // before it STs null into _owner, releasing the lock. Updates
2096 // to data protected by the critical section must be visible before
2097 // we drop the lock (and thus before any other thread could acquire
2098 // the lock and observe the fields protected by the lock).
2099 // IA32's memory-model is SPO, so STs are ordered with respect to
2100 // each other and there's no need for an explicit barrier (fence).
2101 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2102 #ifndef _LP64
2103 get_thread (boxReg);
2104 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2105 // prefetchw [ebx + Offset(_owner)-2]
2106 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2107 }
2108
2109 // Note that we could employ various encoding schemes to reduce
2110 // the number of loads below (currently 4) to just 2 or 3.
2111 // Refer to the comments in synchronizer.cpp.
2112 // In practice the chain of fetches doesn't seem to impact performance, however.
2113 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2114 // Attempt to reduce branch density - AMD's branch predictor.
2115 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2116 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2117 orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2118 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2119 jccb (Assembler::notZero, DONE_LABEL);
2120 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2121 jmpb (DONE_LABEL);
2122 } else {
2123 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2124 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2125 jccb (Assembler::notZero, DONE_LABEL);
2126 movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2127 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2128 jccb (Assembler::notZero, CheckSucc);
2129 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2130 jmpb (DONE_LABEL);
2131 }
2132
2133 // The Following code fragment (EmitSync & 65536) improves the performance of
2134 // contended applications and contended synchronization microbenchmarks.
2135 // Unfortunately the emission of the code - even though not executed - causes regressions
2136 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2137 // with an equal number of never-executed NOPs results in the same regression.
2138 // We leave it off by default.
2139
2140 if ((EmitSync & 65536) != 0) {
2141 Label LSuccess, LGoSlowPath ;
2142
2143 bind (CheckSucc);
2144
2145 // Optional pre-test ... it's safe to elide this
2146 if ((EmitSync & 16) == 0) {
2147 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2148 jccb (Assembler::zero, LGoSlowPath);
2149 }
2150
2151 // We have a classic Dekker-style idiom:
2152 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2153 // There are a number of ways to implement the barrier:
2154 // (1) lock:andl &m->_owner, 0
2155 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2156 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2157 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2158 // (2) If supported, an explicit MFENCE is appealing.
2159 // In older IA32 processors MFENCE is slower than lock:add or xchg
2160 // particularly if the write-buffer is full as might be the case if
2161 // if stores closely precede the fence or fence-equivalent instruction.
2162 // In more modern implementations MFENCE appears faster, however.
2163 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2164 // The $lines underlying the top-of-stack should be in M-state.
2165 // The locked add instruction is serializing, of course.
2166 // (4) Use xchg, which is serializing
2167 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2168 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2169 // The integer condition codes will tell us if succ was 0.
2170 // Since _succ and _owner should reside in the same $line and
2171 // we just stored into _owner, it's likely that the $line
2172 // remains in M-state for the lock:orl.
2173 //
2174 // We currently use (3), although it's likely that switching to (2)
2175 // is correct for the future.
2176
2177 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2178 if (os::is_MP()) {
2179 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2180 mfence();
2181 } else {
2182 lock (); addptr(Address(rsp, 0), 0);
2183 }
2184 }
2185 // Ratify _succ remains non-null
2186 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0);
2187 jccb (Assembler::notZero, LSuccess);
2188
2189 xorptr(boxReg, boxReg); // box is really EAX
2190 if (os::is_MP()) { lock(); }
2191 cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2192 jccb (Assembler::notEqual, LSuccess);
2193 // Since we're low on registers we installed rsp as a placeholding in _owner.
2194 // Now install Self over rsp. This is safe as we're transitioning from
2195 // non-null to non=null
2196 get_thread (boxReg);
2197 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg);
2198 // Intentional fall-through into LGoSlowPath ...
2199
2200 bind (LGoSlowPath);
2201 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2202 jmpb (DONE_LABEL);
2203
2204 bind (LSuccess);
2205 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2206 jmpb (DONE_LABEL);
2207 }
2208
2209 bind (Stacked);
2210 // It's not inflated and it's not recursively stack-locked and it's not biased.
2211 // It must be stack-locked.
2212 // Try to reset the header to displaced header.
2213 // The "box" value on the stack is stable, so we can reload
2214 // and be assured we observe the same value as above.
2215 movptr(tmpReg, Address(boxReg, 0));
2216 if (os::is_MP()) {
2217 lock();
2218 }
2219 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2220 // Intention fall-thru into DONE_LABEL
2221
2222 // DONE_LABEL is a hot target - we'd really like to place it at the
2223 // start of cache line by padding with NOPs.
2224 // See the AMD and Intel software optimization manuals for the
2225 // most efficient "long" NOP encodings.
2226 // Unfortunately none of our alignment mechanisms suffice.
2227 if ((EmitSync & 65536) == 0) {
2228 bind (CheckSucc);
2229 }
2230 #else // _LP64
2231 // It's inflated
2232 movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2233 xorptr(boxReg, r15_thread);
2234 orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2235 jccb (Assembler::notZero, DONE_LABEL);
2236 movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2237 orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2238 jccb (Assembler::notZero, CheckSucc);
2239 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2240 jmpb (DONE_LABEL);
2241
2242 if ((EmitSync & 65536) == 0) {
2243 Label LSuccess, LGoSlowPath ;
2244 bind (CheckSucc);
2245 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2246 jccb (Assembler::zero, LGoSlowPath);
2247
2248 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2249 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2250 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2251 // are all faster when the write buffer is populated.
2252 movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2253 if (os::is_MP()) {
2254 lock (); addl (Address(rsp, 0), 0);
2255 }
2256 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2257 jccb (Assembler::notZero, LSuccess);
2258
2259 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2260 if (os::is_MP()) { lock(); }
2261 cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2262 jccb (Assembler::notEqual, LSuccess);
2263 // Intentional fall-through into slow-path
2264
2265 bind (LGoSlowPath);
2266 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2267 jmpb (DONE_LABEL);
2268
2269 bind (LSuccess);
2270 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2271 jmpb (DONE_LABEL);
2272 }
2273
2274 bind (Stacked);
2275 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2276 if (os::is_MP()) { lock(); }
2277 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2278
2279 if (EmitSync & 65536) {
2280 bind (CheckSucc);
2281 }
2282 #endif
2283 bind(DONE_LABEL);
2284 // Avoid branch to branch on AMD processors
2285 if (EmitSync & 32768) {
2286 nop();
2287 }
2288 }
2289 }
2290 #endif // COMPILER2
2291
2292 void MacroAssembler::c2bool(Register x) {
2293 // implements x == 0 ? 0 : 1
2294 // note: must only look at least-significant byte of x
2295 // since C-style booleans are stored in one byte
2296 // only! (was bug)
2297 andl(x, 0xFF);
2298 setb(Assembler::notZero, x);
2299 }
2300
2301 // Wouldn't need if AddressLiteral version had new name
2302 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2303 Assembler::call(L, rtype);
2304 }
2305
2306 void MacroAssembler::call(Register entry) {
2307 Assembler::call(entry);
2308 }
2309
2310 void MacroAssembler::call(AddressLiteral entry) {
2311 if (reachable(entry)) {
2312 Assembler::call_literal(entry.target(), entry.rspec());
2313 } else {
2314 lea(rscratch1, entry);
2315 Assembler::call(rscratch1);
2316 }
2317 }
2318
2319 void MacroAssembler::ic_call(address entry) {
2320 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2321 movptr(rax, (intptr_t)Universe::non_oop_word());
2322 call(AddressLiteral(entry, rh));
2323 }
2324
2325 // Implementation of call_VM versions
2326
2327 void MacroAssembler::call_VM(Register oop_result,
2328 address entry_point,
2329 bool check_exceptions) {
2330 Label C, E;
2331 call(C, relocInfo::none);
2332 jmp(E);
2333
2334 bind(C);
2335 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2336 ret(0);
2337
2338 bind(E);
2339 }
2340
2341 void MacroAssembler::call_VM(Register oop_result,
2342 address entry_point,
2343 Register arg_1,
2344 bool check_exceptions) {
2345 Label C, E;
2346 call(C, relocInfo::none);
2347 jmp(E);
2348
2349 bind(C);
2350 pass_arg1(this, arg_1);
2351 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2352 ret(0);
2353
2354 bind(E);
2355 }
2356
2357 void MacroAssembler::call_VM(Register oop_result,
2358 address entry_point,
2359 Register arg_1,
2360 Register arg_2,
2361 bool check_exceptions) {
2362 Label C, E;
2363 call(C, relocInfo::none);
2364 jmp(E);
2365
2366 bind(C);
2367
2368 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2369
2370 pass_arg2(this, arg_2);
2371 pass_arg1(this, arg_1);
2372 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2373 ret(0);
2374
2375 bind(E);
2376 }
2377
2378 void MacroAssembler::call_VM(Register oop_result,
2379 address entry_point,
2380 Register arg_1,
2381 Register arg_2,
2382 Register arg_3,
2383 bool check_exceptions) {
2384 Label C, E;
2385 call(C, relocInfo::none);
2386 jmp(E);
2387
2388 bind(C);
2389
2390 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2391 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2392 pass_arg3(this, arg_3);
2393
2394 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2395 pass_arg2(this, arg_2);
2396
2397 pass_arg1(this, arg_1);
2398 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2399 ret(0);
2400
2401 bind(E);
2402 }
2403
2404 void MacroAssembler::call_VM(Register oop_result,
2405 Register last_java_sp,
2406 address entry_point,
2407 int number_of_arguments,
2408 bool check_exceptions) {
2409 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2410 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2411 }
2412
2413 void MacroAssembler::call_VM(Register oop_result,
2414 Register last_java_sp,
2415 address entry_point,
2416 Register arg_1,
2417 bool check_exceptions) {
2418 pass_arg1(this, arg_1);
2419 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2420 }
2421
2422 void MacroAssembler::call_VM(Register oop_result,
2423 Register last_java_sp,
2424 address entry_point,
2425 Register arg_1,
2426 Register arg_2,
2427 bool check_exceptions) {
2428
2429 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2430 pass_arg2(this, arg_2);
2431 pass_arg1(this, arg_1);
2432 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2433 }
2434
2435 void MacroAssembler::call_VM(Register oop_result,
2436 Register last_java_sp,
2437 address entry_point,
2438 Register arg_1,
2439 Register arg_2,
2440 Register arg_3,
2441 bool check_exceptions) {
2442 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2443 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2444 pass_arg3(this, arg_3);
2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2446 pass_arg2(this, arg_2);
2447 pass_arg1(this, arg_1);
2448 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2449 }
2450
2451 void MacroAssembler::super_call_VM(Register oop_result,
2452 Register last_java_sp,
2453 address entry_point,
2454 int number_of_arguments,
2455 bool check_exceptions) {
2456 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2457 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2458 }
2459
2460 void MacroAssembler::super_call_VM(Register oop_result,
2461 Register last_java_sp,
2462 address entry_point,
2463 Register arg_1,
2464 bool check_exceptions) {
2465 pass_arg1(this, arg_1);
2466 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2467 }
2468
2469 void MacroAssembler::super_call_VM(Register oop_result,
2470 Register last_java_sp,
2471 address entry_point,
2472 Register arg_1,
2473 Register arg_2,
2474 bool check_exceptions) {
2475
2476 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2477 pass_arg2(this, arg_2);
2478 pass_arg1(this, arg_1);
2479 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2480 }
2481
2482 void MacroAssembler::super_call_VM(Register oop_result,
2483 Register last_java_sp,
2484 address entry_point,
2485 Register arg_1,
2486 Register arg_2,
2487 Register arg_3,
2488 bool check_exceptions) {
2489 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2490 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2491 pass_arg3(this, arg_3);
2492 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2493 pass_arg2(this, arg_2);
2494 pass_arg1(this, arg_1);
2495 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2496 }
2497
2498 void MacroAssembler::call_VM_base(Register oop_result,
2499 Register java_thread,
2500 Register last_java_sp,
2501 address entry_point,
2502 int number_of_arguments,
2503 bool check_exceptions) {
2504 // determine java_thread register
2505 if (!java_thread->is_valid()) {
2506 #ifdef _LP64
2507 java_thread = r15_thread;
2508 #else
2509 java_thread = rdi;
2510 get_thread(java_thread);
2511 #endif // LP64
2512 }
2513 // determine last_java_sp register
2514 if (!last_java_sp->is_valid()) {
2515 last_java_sp = rsp;
2516 }
2517 // debugging support
2518 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2519 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2520 #ifdef ASSERT
2521 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2522 // r12 is the heapbase.
2523 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2524 #endif // ASSERT
2525
2526 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2527 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2528
2529 // push java thread (becomes first argument of C function)
2530
2531 NOT_LP64(push(java_thread); number_of_arguments++);
2532 LP64_ONLY(mov(c_rarg0, r15_thread));
2533
2534 // set last Java frame before call
2535 assert(last_java_sp != rbp, "can't use ebp/rbp");
2536
2537 // Only interpreter should have to set fp
2538 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2539
2540 // do the call, remove parameters
2541 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2542
2543 // restore the thread (cannot use the pushed argument since arguments
2544 // may be overwritten by C code generated by an optimizing compiler);
2545 // however can use the register value directly if it is callee saved.
2546 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2547 // rdi & rsi (also r15) are callee saved -> nothing to do
2548 #ifdef ASSERT
2549 guarantee(java_thread != rax, "change this code");
2550 push(rax);
2551 { Label L;
2552 get_thread(rax);
2553 cmpptr(java_thread, rax);
2554 jcc(Assembler::equal, L);
2555 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2556 bind(L);
2557 }
2558 pop(rax);
2559 #endif
2560 } else {
2561 get_thread(java_thread);
2562 }
2563 // reset last Java frame
2564 // Only interpreter should have to clear fp
2565 reset_last_Java_frame(java_thread, true, false);
2566
2567 #ifndef CC_INTERP
2568 // C++ interp handles this in the interpreter
2569 check_and_handle_popframe(java_thread);
2570 check_and_handle_earlyret(java_thread);
2571 #endif /* CC_INTERP */
2572
2573 if (check_exceptions) {
2574 // check for pending exceptions (java_thread is set upon return)
2575 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2576 #ifndef _LP64
2577 jump_cc(Assembler::notEqual,
2578 RuntimeAddress(StubRoutines::forward_exception_entry()));
2579 #else
2580 // This used to conditionally jump to forward_exception however it is
2581 // possible if we relocate that the branch will not reach. So we must jump
2582 // around so we can always reach
2583
2584 Label ok;
2585 jcc(Assembler::equal, ok);
2586 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2587 bind(ok);
2588 #endif // LP64
2589 }
2590
2591 // get oop result if there is one and reset the value in the thread
2592 if (oop_result->is_valid()) {
2593 get_vm_result(oop_result, java_thread);
2594 }
2595 }
2596
2597 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2598
2599 // Calculate the value for last_Java_sp
2600 // somewhat subtle. call_VM does an intermediate call
2601 // which places a return address on the stack just under the
2602 // stack pointer as the user finsihed with it. This allows
2603 // use to retrieve last_Java_pc from last_Java_sp[-1].
2604 // On 32bit we then have to push additional args on the stack to accomplish
2605 // the actual requested call. On 64bit call_VM only can use register args
2606 // so the only extra space is the return address that call_VM created.
2607 // This hopefully explains the calculations here.
2608
2609 #ifdef _LP64
2610 // We've pushed one address, correct last_Java_sp
2611 lea(rax, Address(rsp, wordSize));
2612 #else
2613 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2614 #endif // LP64
2615
2616 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2617
2618 }
2619
2620 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2621 call_VM_leaf_base(entry_point, number_of_arguments);
2622 }
2623
2624 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2625 pass_arg0(this, arg_0);
2626 call_VM_leaf(entry_point, 1);
2627 }
2628
2629 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2630
2631 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2632 pass_arg1(this, arg_1);
2633 pass_arg0(this, arg_0);
2634 call_VM_leaf(entry_point, 2);
2635 }
2636
2637 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2638 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2639 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2640 pass_arg2(this, arg_2);
2641 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2642 pass_arg1(this, arg_1);
2643 pass_arg0(this, arg_0);
2644 call_VM_leaf(entry_point, 3);
2645 }
2646
2647 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2648 pass_arg0(this, arg_0);
2649 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2650 }
2651
2652 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2653
2654 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2655 pass_arg1(this, arg_1);
2656 pass_arg0(this, arg_0);
2657 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2658 }
2659
2660 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2661 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2662 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2663 pass_arg2(this, arg_2);
2664 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2665 pass_arg1(this, arg_1);
2666 pass_arg0(this, arg_0);
2667 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2668 }
2669
2670 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2671 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2672 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2673 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2674 pass_arg3(this, arg_3);
2675 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2676 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2677 pass_arg2(this, arg_2);
2678 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2679 pass_arg1(this, arg_1);
2680 pass_arg0(this, arg_0);
2681 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2682 }
2683
2684 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2685 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2686 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2687 verify_oop(oop_result, "broken oop in call_VM_base");
2688 }
2689
2690 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2691 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2692 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2693 }
2694
2695 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2696 }
2697
2698 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2699 }
2700
2701 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2702 if (reachable(src1)) {
2703 cmpl(as_Address(src1), imm);
2704 } else {
2705 lea(rscratch1, src1);
2706 cmpl(Address(rscratch1, 0), imm);
2707 }
2708 }
2709
2710 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2711 assert(!src2.is_lval(), "use cmpptr");
2712 if (reachable(src2)) {
2713 cmpl(src1, as_Address(src2));
2714 } else {
2715 lea(rscratch1, src2);
2716 cmpl(src1, Address(rscratch1, 0));
2717 }
2718 }
2719
2720 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2721 Assembler::cmpl(src1, imm);
2722 }
2723
2724 void MacroAssembler::cmp32(Register src1, Address src2) {
2725 Assembler::cmpl(src1, src2);
2726 }
2727
2728 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2729 ucomisd(opr1, opr2);
2730
2731 Label L;
2732 if (unordered_is_less) {
2733 movl(dst, -1);
2734 jcc(Assembler::parity, L);
2735 jcc(Assembler::below , L);
2736 movl(dst, 0);
2737 jcc(Assembler::equal , L);
2738 increment(dst);
2739 } else { // unordered is greater
2740 movl(dst, 1);
2741 jcc(Assembler::parity, L);
2742 jcc(Assembler::above , L);
2743 movl(dst, 0);
2744 jcc(Assembler::equal , L);
2745 decrementl(dst);
2746 }
2747 bind(L);
2748 }
2749
2750 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2751 ucomiss(opr1, opr2);
2752
2753 Label L;
2754 if (unordered_is_less) {
2755 movl(dst, -1);
2756 jcc(Assembler::parity, L);
2757 jcc(Assembler::below , L);
2758 movl(dst, 0);
2759 jcc(Assembler::equal , L);
2760 increment(dst);
2761 } else { // unordered is greater
2762 movl(dst, 1);
2763 jcc(Assembler::parity, L);
2764 jcc(Assembler::above , L);
2765 movl(dst, 0);
2766 jcc(Assembler::equal , L);
2767 decrementl(dst);
2768 }
2769 bind(L);
2770 }
2771
2772
2773 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2774 if (reachable(src1)) {
2775 cmpb(as_Address(src1), imm);
2776 } else {
2777 lea(rscratch1, src1);
2778 cmpb(Address(rscratch1, 0), imm);
2779 }
2780 }
2781
2782 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2783 #ifdef _LP64
2784 if (src2.is_lval()) {
2785 movptr(rscratch1, src2);
2786 Assembler::cmpq(src1, rscratch1);
2787 } else if (reachable(src2)) {
2788 cmpq(src1, as_Address(src2));
2789 } else {
2790 lea(rscratch1, src2);
2791 Assembler::cmpq(src1, Address(rscratch1, 0));
2792 }
2793 #else
2794 if (src2.is_lval()) {
2795 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2796 } else {
2797 cmpl(src1, as_Address(src2));
2798 }
2799 #endif // _LP64
2800 }
2801
2802 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2803 assert(src2.is_lval(), "not a mem-mem compare");
2804 #ifdef _LP64
2805 // moves src2's literal address
2806 movptr(rscratch1, src2);
2807 Assembler::cmpq(src1, rscratch1);
2808 #else
2809 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2810 #endif // _LP64
2811 }
2812
2813 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2814 if (reachable(adr)) {
2815 if (os::is_MP())
2816 lock();
2817 cmpxchgptr(reg, as_Address(adr));
2818 } else {
2819 lea(rscratch1, adr);
2820 if (os::is_MP())
2821 lock();
2822 cmpxchgptr(reg, Address(rscratch1, 0));
2823 }
2824 }
2825
2826 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2827 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2828 }
2829
2830 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2831 if (reachable(src)) {
2832 Assembler::comisd(dst, as_Address(src));
2833 } else {
2834 lea(rscratch1, src);
2835 Assembler::comisd(dst, Address(rscratch1, 0));
2836 }
2837 }
2838
2839 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2840 if (reachable(src)) {
2841 Assembler::comiss(dst, as_Address(src));
2842 } else {
2843 lea(rscratch1, src);
2844 Assembler::comiss(dst, Address(rscratch1, 0));
2845 }
2846 }
2847
2848
2849 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2850 Condition negated_cond = negate_condition(cond);
2851 Label L;
2852 jcc(negated_cond, L);
2853 pushf(); // Preserve flags
2854 atomic_incl(counter_addr);
2855 popf();
2856 bind(L);
2857 }
2858
2859 int MacroAssembler::corrected_idivl(Register reg) {
2860 // Full implementation of Java idiv and irem; checks for
2861 // special case as described in JVM spec., p.243 & p.271.
2862 // The function returns the (pc) offset of the idivl
2863 // instruction - may be needed for implicit exceptions.
2864 //
2865 // normal case special case
2866 //
2867 // input : rax,: dividend min_int
2868 // reg: divisor (may not be rax,/rdx) -1
2869 //
2870 // output: rax,: quotient (= rax, idiv reg) min_int
2871 // rdx: remainder (= rax, irem reg) 0
2872 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2873 const int min_int = 0x80000000;
2874 Label normal_case, special_case;
2875
2876 // check for special case
2877 cmpl(rax, min_int);
2878 jcc(Assembler::notEqual, normal_case);
2879 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2880 cmpl(reg, -1);
2881 jcc(Assembler::equal, special_case);
2882
2883 // handle normal case
2884 bind(normal_case);
2885 cdql();
2886 int idivl_offset = offset();
2887 idivl(reg);
2888
2889 // normal and special case exit
2890 bind(special_case);
2891
2892 return idivl_offset;
2893 }
2894
2895
2896
2897 void MacroAssembler::decrementl(Register reg, int value) {
2898 if (value == min_jint) {subl(reg, value) ; return; }
2899 if (value < 0) { incrementl(reg, -value); return; }
2900 if (value == 0) { ; return; }
2901 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2902 /* else */ { subl(reg, value) ; return; }
2903 }
2904
2905 void MacroAssembler::decrementl(Address dst, int value) {
2906 if (value == min_jint) {subl(dst, value) ; return; }
2907 if (value < 0) { incrementl(dst, -value); return; }
2908 if (value == 0) { ; return; }
2909 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2910 /* else */ { subl(dst, value) ; return; }
2911 }
2912
2913 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2914 assert (shift_value > 0, "illegal shift value");
2915 Label _is_positive;
2916 testl (reg, reg);
2917 jcc (Assembler::positive, _is_positive);
2918 int offset = (1 << shift_value) - 1 ;
2919
2920 if (offset == 1) {
2921 incrementl(reg);
2922 } else {
2923 addl(reg, offset);
2924 }
2925
2926 bind (_is_positive);
2927 sarl(reg, shift_value);
2928 }
2929
2930 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2931 if (reachable(src)) {
2932 Assembler::divsd(dst, as_Address(src));
2933 } else {
2934 lea(rscratch1, src);
2935 Assembler::divsd(dst, Address(rscratch1, 0));
2936 }
2937 }
2938
2939 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2940 if (reachable(src)) {
2941 Assembler::divss(dst, as_Address(src));
2942 } else {
2943 lea(rscratch1, src);
2944 Assembler::divss(dst, Address(rscratch1, 0));
2945 }
2946 }
2947
2948 // !defined(COMPILER2) is because of stupid core builds
2949 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2950 void MacroAssembler::empty_FPU_stack() {
2951 if (VM_Version::supports_mmx()) {
2952 emms();
2953 } else {
2954 for (int i = 8; i-- > 0; ) ffree(i);
2955 }
2956 }
2957 #endif // !LP64 || C1 || !C2
2958
2959
2960 // Defines obj, preserves var_size_in_bytes
2961 void MacroAssembler::eden_allocate(Register obj,
2962 Register var_size_in_bytes,
2963 int con_size_in_bytes,
2964 Register t1,
2965 Label& slow_case) {
2966 assert(obj == rax, "obj must be in rax, for cmpxchg");
2967 assert_different_registers(obj, var_size_in_bytes, t1);
2968 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
2969 jmp(slow_case);
2970 } else {
2971 Register end = t1;
2972 Label retry;
2973 bind(retry);
2974 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2975 movptr(obj, heap_top);
2976 if (var_size_in_bytes == noreg) {
2977 lea(end, Address(obj, con_size_in_bytes));
2978 } else {
2979 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2980 }
2981 // if end < obj then we wrapped around => object too long => slow case
2982 cmpptr(end, obj);
2983 jcc(Assembler::below, slow_case);
2984 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2985 jcc(Assembler::above, slow_case);
2986 // Compare obj with the top addr, and if still equal, store the new top addr in
2987 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2988 // it otherwise. Use lock prefix for atomicity on MPs.
2989 locked_cmpxchgptr(end, heap_top);
2990 jcc(Assembler::notEqual, retry);
2991 }
2992 }
2993
2994 void MacroAssembler::enter() {
2995 push(rbp);
2996 mov(rbp, rsp);
2997 }
2998
2999 // A 5 byte nop that is safe for patching (see patch_verified_entry)
3000 void MacroAssembler::fat_nop() {
3001 if (UseAddressNop) {
3002 addr_nop_5();
3003 } else {
3004 emit_int8(0x26); // es:
3005 emit_int8(0x2e); // cs:
3006 emit_int8(0x64); // fs:
3007 emit_int8(0x65); // gs:
3008 emit_int8((unsigned char)0x90);
3009 }
3010 }
3011
3012 void MacroAssembler::fcmp(Register tmp) {
3013 fcmp(tmp, 1, true, true);
3014 }
3015
3016 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3017 assert(!pop_right || pop_left, "usage error");
3018 if (VM_Version::supports_cmov()) {
3019 assert(tmp == noreg, "unneeded temp");
3020 if (pop_left) {
3021 fucomip(index);
3022 } else {
3023 fucomi(index);
3024 }
3025 if (pop_right) {
3026 fpop();
3027 }
3028 } else {
3029 assert(tmp != noreg, "need temp");
3030 if (pop_left) {
3031 if (pop_right) {
3032 fcompp();
3033 } else {
3034 fcomp(index);
3035 }
3036 } else {
3037 fcom(index);
3038 }
3039 // convert FPU condition into eflags condition via rax,
3040 save_rax(tmp);
3041 fwait(); fnstsw_ax();
3042 sahf();
3043 restore_rax(tmp);
3044 }
3045 // condition codes set as follows:
3046 //
3047 // CF (corresponds to C0) if x < y
3048 // PF (corresponds to C2) if unordered
3049 // ZF (corresponds to C3) if x = y
3050 }
3051
3052 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3053 fcmp2int(dst, unordered_is_less, 1, true, true);
3054 }
3055
3056 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3057 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3058 Label L;
3059 if (unordered_is_less) {
3060 movl(dst, -1);
3061 jcc(Assembler::parity, L);
3062 jcc(Assembler::below , L);
3063 movl(dst, 0);
3064 jcc(Assembler::equal , L);
3065 increment(dst);
3066 } else { // unordered is greater
3067 movl(dst, 1);
3068 jcc(Assembler::parity, L);
3069 jcc(Assembler::above , L);
3070 movl(dst, 0);
3071 jcc(Assembler::equal , L);
3072 decrementl(dst);
3073 }
3074 bind(L);
3075 }
3076
3077 void MacroAssembler::fld_d(AddressLiteral src) {
3078 fld_d(as_Address(src));
3079 }
3080
3081 void MacroAssembler::fld_s(AddressLiteral src) {
3082 fld_s(as_Address(src));
3083 }
3084
3085 void MacroAssembler::fld_x(AddressLiteral src) {
3086 Assembler::fld_x(as_Address(src));
3087 }
3088
3089 void MacroAssembler::fldcw(AddressLiteral src) {
3090 Assembler::fldcw(as_Address(src));
3091 }
3092
3093 void MacroAssembler::pow_exp_core_encoding() {
3094 // kills rax, rcx, rdx
3095 subptr(rsp,sizeof(jdouble));
3096 // computes 2^X. Stack: X ...
3097 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3098 // keep it on the thread's stack to compute 2^int(X) later
3099 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3100 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3101 fld_s(0); // Stack: X X ...
3102 frndint(); // Stack: int(X) X ...
3103 fsuba(1); // Stack: int(X) X-int(X) ...
3104 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3105 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3106 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3107 faddp(1); // Stack: 2^(X-int(X))
3108 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3109 // shift int(X)+1023 to exponent position.
3110 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3111 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3112 // values so detect them and set result to NaN.
3113 movl(rax,Address(rsp,0));
3114 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3115 addl(rax, 1023);
3116 movl(rdx,rax);
3117 shll(rax,20);
3118 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3119 addl(rdx,1);
3120 // Check that 1 < int(X)+1023+1 < 2048
3121 // in 3 steps:
3122 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3123 // 2- (int(X)+1023+1)&-2048 != 0
3124 // 3- (int(X)+1023+1)&-2048 != 1
3125 // Do 2- first because addl just updated the flags.
3126 cmov32(Assembler::equal,rax,rcx);
3127 cmpl(rdx,1);
3128 cmov32(Assembler::equal,rax,rcx);
3129 testl(rdx,rcx);
3130 cmov32(Assembler::notEqual,rax,rcx);
3131 movl(Address(rsp,4),rax);
3132 movl(Address(rsp,0),0);
3133 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3134 addptr(rsp,sizeof(jdouble));
3135 }
3136
3137 void MacroAssembler::increase_precision() {
3138 subptr(rsp, BytesPerWord);
3139 fnstcw(Address(rsp, 0));
3140 movl(rax, Address(rsp, 0));
3141 orl(rax, 0x300);
3142 push(rax);
3143 fldcw(Address(rsp, 0));
3144 pop(rax);
3145 }
3146
3147 void MacroAssembler::restore_precision() {
3148 fldcw(Address(rsp, 0));
3149 addptr(rsp, BytesPerWord);
3150 }
3151
3152 void MacroAssembler::fast_pow() {
3153 // computes X^Y = 2^(Y * log2(X))
3154 // if fast computation is not possible, result is NaN. Requires
3155 // fallback from user of this macro.
3156 // increase precision for intermediate steps of the computation
3157 BLOCK_COMMENT("fast_pow {");
3158 increase_precision();
3159 fyl2x(); // Stack: (Y*log2(X)) ...
3160 pow_exp_core_encoding(); // Stack: exp(X) ...
3161 restore_precision();
3162 BLOCK_COMMENT("} fast_pow");
3163 }
3164
3165 void MacroAssembler::fast_exp() {
3166 // computes exp(X) = 2^(X * log2(e))
3167 // if fast computation is not possible, result is NaN. Requires
3168 // fallback from user of this macro.
3169 // increase precision for intermediate steps of the computation
3170 increase_precision();
3171 fldl2e(); // Stack: log2(e) X ...
3172 fmulp(1); // Stack: (X*log2(e)) ...
3173 pow_exp_core_encoding(); // Stack: exp(X) ...
3174 restore_precision();
3175 }
3176
3177 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3178 // kills rax, rcx, rdx
3179 // pow and exp needs 2 extra registers on the fpu stack.
3180 Label slow_case, done;
3181 Register tmp = noreg;
3182 if (!VM_Version::supports_cmov()) {
3183 // fcmp needs a temporary so preserve rdx,
3184 tmp = rdx;
3185 }
3186 Register tmp2 = rax;
3187 Register tmp3 = rcx;
3188
3189 if (is_exp) {
3190 // Stack: X
3191 fld_s(0); // duplicate argument for runtime call. Stack: X X
3192 fast_exp(); // Stack: exp(X) X
3193 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3194 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3195 jcc(Assembler::parity, slow_case);
3196 // get rid of duplicate argument. Stack: exp(X)
3197 if (num_fpu_regs_in_use > 0) {
3198 fxch();
3199 fpop();
3200 } else {
3201 ffree(1);
3202 }
3203 jmp(done);
3204 } else {
3205 // Stack: X Y
3206 Label x_negative, y_odd;
3207
3208 fldz(); // Stack: 0 X Y
3209 fcmp(tmp, 1, true, false); // Stack: X Y
3210 jcc(Assembler::above, x_negative);
3211
3212 // X >= 0
3213
3214 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3215 fld_s(1); // Stack: X Y X Y
3216 fast_pow(); // Stack: X^Y X Y
3217 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3218 // X^Y not equal to itself: X^Y is NaN go to slow case.
3219 jcc(Assembler::parity, slow_case);
3220 // get rid of duplicate arguments. Stack: X^Y
3221 if (num_fpu_regs_in_use > 0) {
3222 fxch(); fpop();
3223 fxch(); fpop();
3224 } else {
3225 ffree(2);
3226 ffree(1);
3227 }
3228 jmp(done);
3229
3230 // X <= 0
3231 bind(x_negative);
3232
3233 fld_s(1); // Stack: Y X Y
3234 frndint(); // Stack: int(Y) X Y
3235 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3236 jcc(Assembler::notEqual, slow_case);
3237
3238 subptr(rsp, 8);
3239
3240 // For X^Y, when X < 0, Y has to be an integer and the final
3241 // result depends on whether it's odd or even. We just checked
3242 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3243 // integer to test its parity. If int(Y) is huge and doesn't fit
3244 // in the 64 bit integer range, the integer indefinite value will
3245 // end up in the gp registers. Huge numbers are all even, the
3246 // integer indefinite number is even so it's fine.
3247
3248 #ifdef ASSERT
3249 // Let's check we don't end up with an integer indefinite number
3250 // when not expected. First test for huge numbers: check whether
3251 // int(Y)+1 == int(Y) which is true for very large numbers and
3252 // those are all even. A 64 bit integer is guaranteed to not
3253 // overflow for numbers where y+1 != y (when precision is set to
3254 // double precision).
3255 Label y_not_huge;
3256
3257 fld1(); // Stack: 1 int(Y) X Y
3258 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3259
3260 #ifdef _LP64
3261 // trip to memory to force the precision down from double extended
3262 // precision
3263 fstp_d(Address(rsp, 0));
3264 fld_d(Address(rsp, 0));
3265 #endif
3266
3267 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3268 #endif
3269
3270 // move int(Y) as 64 bit integer to thread's stack
3271 fistp_d(Address(rsp,0)); // Stack: X Y
3272
3273 #ifdef ASSERT
3274 jcc(Assembler::notEqual, y_not_huge);
3275
3276 // Y is huge so we know it's even. It may not fit in a 64 bit
3277 // integer and we don't want the debug code below to see the
3278 // integer indefinite value so overwrite int(Y) on the thread's
3279 // stack with 0.
3280 movl(Address(rsp, 0), 0);
3281 movl(Address(rsp, 4), 0);
3282
3283 bind(y_not_huge);
3284 #endif
3285
3286 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3287 fld_s(1); // Stack: X Y X Y
3288 fabs(); // Stack: abs(X) Y X Y
3289 fast_pow(); // Stack: abs(X)^Y X Y
3290 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3291 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3292
3293 pop(tmp2);
3294 NOT_LP64(pop(tmp3));
3295 jcc(Assembler::parity, slow_case);
3296
3297 #ifdef ASSERT
3298 // Check that int(Y) is not integer indefinite value (int
3299 // overflow). Shouldn't happen because for values that would
3300 // overflow, 1+int(Y)==Y which was tested earlier.
3301 #ifndef _LP64
3302 {
3303 Label integer;
3304 testl(tmp2, tmp2);
3305 jcc(Assembler::notZero, integer);
3306 cmpl(tmp3, 0x80000000);
3307 jcc(Assembler::notZero, integer);
3308 STOP("integer indefinite value shouldn't be seen here");
3309 bind(integer);
3310 }
3311 #else
3312 {
3313 Label integer;
3314 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3315 shlq(tmp3, 1);
3316 jcc(Assembler::carryClear, integer);
3317 jcc(Assembler::notZero, integer);
3318 STOP("integer indefinite value shouldn't be seen here");
3319 bind(integer);
3320 }
3321 #endif
3322 #endif
3323
3324 // get rid of duplicate arguments. Stack: X^Y
3325 if (num_fpu_regs_in_use > 0) {
3326 fxch(); fpop();
3327 fxch(); fpop();
3328 } else {
3329 ffree(2);
3330 ffree(1);
3331 }
3332
3333 testl(tmp2, 1);
3334 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3335 // X <= 0, Y even: X^Y = -abs(X)^Y
3336
3337 fchs(); // Stack: -abs(X)^Y Y
3338 jmp(done);
3339 }
3340
3341 // slow case: runtime call
3342 bind(slow_case);
3343
3344 fpop(); // pop incorrect result or int(Y)
3345
3346 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3347 is_exp ? 1 : 2, num_fpu_regs_in_use);
3348
3349 // Come here with result in F-TOS
3350 bind(done);
3351 }
3352
3353 void MacroAssembler::fpop() {
3354 ffree();
3355 fincstp();
3356 }
3357
3358 void MacroAssembler::fremr(Register tmp) {
3359 save_rax(tmp);
3360 { Label L;
3361 bind(L);
3362 fprem();
3363 fwait(); fnstsw_ax();
3364 #ifdef _LP64
3365 testl(rax, 0x400);
3366 jcc(Assembler::notEqual, L);
3367 #else
3368 sahf();
3369 jcc(Assembler::parity, L);
3370 #endif // _LP64
3371 }
3372 restore_rax(tmp);
3373 // Result is in ST0.
3374 // Note: fxch & fpop to get rid of ST1
3375 // (otherwise FPU stack could overflow eventually)
3376 fxch(1);
3377 fpop();
3378 }
3379
3380
3381 void MacroAssembler::incrementl(AddressLiteral dst) {
3382 if (reachable(dst)) {
3383 incrementl(as_Address(dst));
3384 } else {
3385 lea(rscratch1, dst);
3386 incrementl(Address(rscratch1, 0));
3387 }
3388 }
3389
3390 void MacroAssembler::incrementl(ArrayAddress dst) {
3391 incrementl(as_Address(dst));
3392 }
3393
3394 void MacroAssembler::incrementl(Register reg, int value) {
3395 if (value == min_jint) {addl(reg, value) ; return; }
3396 if (value < 0) { decrementl(reg, -value); return; }
3397 if (value == 0) { ; return; }
3398 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3399 /* else */ { addl(reg, value) ; return; }
3400 }
3401
3402 void MacroAssembler::incrementl(Address dst, int value) {
3403 if (value == min_jint) {addl(dst, value) ; return; }
3404 if (value < 0) { decrementl(dst, -value); return; }
3405 if (value == 0) { ; return; }
3406 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3407 /* else */ { addl(dst, value) ; return; }
3408 }
3409
3410 void MacroAssembler::jump(AddressLiteral dst) {
3411 if (reachable(dst)) {
3412 jmp_literal(dst.target(), dst.rspec());
3413 } else {
3414 lea(rscratch1, dst);
3415 jmp(rscratch1);
3416 }
3417 }
3418
3419 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3420 if (reachable(dst)) {
3421 InstructionMark im(this);
3422 relocate(dst.reloc());
3423 const int short_size = 2;
3424 const int long_size = 6;
3425 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3426 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3427 // 0111 tttn #8-bit disp
3428 emit_int8(0x70 | cc);
3429 emit_int8((offs - short_size) & 0xFF);
3430 } else {
3431 // 0000 1111 1000 tttn #32-bit disp
3432 emit_int8(0x0F);
3433 emit_int8((unsigned char)(0x80 | cc));
3434 emit_int32(offs - long_size);
3435 }
3436 } else {
3437 #ifdef ASSERT
3438 warning("reversing conditional branch");
3439 #endif /* ASSERT */
3440 Label skip;
3441 jccb(reverse[cc], skip);
3442 lea(rscratch1, dst);
3443 Assembler::jmp(rscratch1);
3444 bind(skip);
3445 }
3446 }
3447
3448 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3449 if (reachable(src)) {
3450 Assembler::ldmxcsr(as_Address(src));
3451 } else {
3452 lea(rscratch1, src);
3453 Assembler::ldmxcsr(Address(rscratch1, 0));
3454 }
3455 }
3456
3457 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3458 int off;
3459 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3460 off = offset();
3461 movsbl(dst, src); // movsxb
3462 } else {
3463 off = load_unsigned_byte(dst, src);
3464 shll(dst, 24);
3465 sarl(dst, 24);
3466 }
3467 return off;
3468 }
3469
3470 // Note: load_signed_short used to be called load_signed_word.
3471 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3472 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3473 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3474 int MacroAssembler::load_signed_short(Register dst, Address src) {
3475 int off;
3476 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3477 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3478 // version but this is what 64bit has always done. This seems to imply
3479 // that users are only using 32bits worth.
3480 off = offset();
3481 movswl(dst, src); // movsxw
3482 } else {
3483 off = load_unsigned_short(dst, src);
3484 shll(dst, 16);
3485 sarl(dst, 16);
3486 }
3487 return off;
3488 }
3489
3490 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3491 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3492 // and "3.9 Partial Register Penalties", p. 22).
3493 int off;
3494 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3495 off = offset();
3496 movzbl(dst, src); // movzxb
3497 } else {
3498 xorl(dst, dst);
3499 off = offset();
3500 movb(dst, src);
3501 }
3502 return off;
3503 }
3504
3505 // Note: load_unsigned_short used to be called load_unsigned_word.
3506 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3507 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3508 // and "3.9 Partial Register Penalties", p. 22).
3509 int off;
3510 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3511 off = offset();
3512 movzwl(dst, src); // movzxw
3513 } else {
3514 xorl(dst, dst);
3515 off = offset();
3516 movw(dst, src);
3517 }
3518 return off;
3519 }
3520
3521 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3522 switch (size_in_bytes) {
3523 #ifndef _LP64
3524 case 8:
3525 assert(dst2 != noreg, "second dest register required");
3526 movl(dst, src);
3527 movl(dst2, src.plus_disp(BytesPerInt));
3528 break;
3529 #else
3530 case 8: movq(dst, src); break;
3531 #endif
3532 case 4: movl(dst, src); break;
3533 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3534 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3535 default: ShouldNotReachHere();
3536 }
3537 }
3538
3539 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3540 switch (size_in_bytes) {
3541 #ifndef _LP64
3542 case 8:
3543 assert(src2 != noreg, "second source register required");
3544 movl(dst, src);
3545 movl(dst.plus_disp(BytesPerInt), src2);
3546 break;
3547 #else
3548 case 8: movq(dst, src); break;
3549 #endif
3550 case 4: movl(dst, src); break;
3551 case 2: movw(dst, src); break;
3552 case 1: movb(dst, src); break;
3553 default: ShouldNotReachHere();
3554 }
3555 }
3556
3557 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3558 if (reachable(dst)) {
3559 movl(as_Address(dst), src);
3560 } else {
3561 lea(rscratch1, dst);
3562 movl(Address(rscratch1, 0), src);
3563 }
3564 }
3565
3566 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3567 if (reachable(src)) {
3568 movl(dst, as_Address(src));
3569 } else {
3570 lea(rscratch1, src);
3571 movl(dst, Address(rscratch1, 0));
3572 }
3573 }
3574
3575 // C++ bool manipulation
3576
3577 void MacroAssembler::movbool(Register dst, Address src) {
3578 if(sizeof(bool) == 1)
3579 movb(dst, src);
3580 else if(sizeof(bool) == 2)
3581 movw(dst, src);
3582 else if(sizeof(bool) == 4)
3583 movl(dst, src);
3584 else
3585 // unsupported
3586 ShouldNotReachHere();
3587 }
3588
3589 void MacroAssembler::movbool(Address dst, bool boolconst) {
3590 if(sizeof(bool) == 1)
3591 movb(dst, (int) boolconst);
3592 else if(sizeof(bool) == 2)
3593 movw(dst, (int) boolconst);
3594 else if(sizeof(bool) == 4)
3595 movl(dst, (int) boolconst);
3596 else
3597 // unsupported
3598 ShouldNotReachHere();
3599 }
3600
3601 void MacroAssembler::movbool(Address dst, Register src) {
3602 if(sizeof(bool) == 1)
3603 movb(dst, src);
3604 else if(sizeof(bool) == 2)
3605 movw(dst, src);
3606 else if(sizeof(bool) == 4)
3607 movl(dst, src);
3608 else
3609 // unsupported
3610 ShouldNotReachHere();
3611 }
3612
3613 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3614 movb(as_Address(dst), src);
3615 }
3616
3617 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3618 if (reachable(src)) {
3619 movdl(dst, as_Address(src));
3620 } else {
3621 lea(rscratch1, src);
3622 movdl(dst, Address(rscratch1, 0));
3623 }
3624 }
3625
3626 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3627 if (reachable(src)) {
3628 movq(dst, as_Address(src));
3629 } else {
3630 lea(rscratch1, src);
3631 movq(dst, Address(rscratch1, 0));
3632 }
3633 }
3634
3635 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3636 if (reachable(src)) {
3637 if (UseXmmLoadAndClearUpper) {
3638 movsd (dst, as_Address(src));
3639 } else {
3640 movlpd(dst, as_Address(src));
3641 }
3642 } else {
3643 lea(rscratch1, src);
3644 if (UseXmmLoadAndClearUpper) {
3645 movsd (dst, Address(rscratch1, 0));
3646 } else {
3647 movlpd(dst, Address(rscratch1, 0));
3648 }
3649 }
3650 }
3651
3652 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3653 if (reachable(src)) {
3654 movss(dst, as_Address(src));
3655 } else {
3656 lea(rscratch1, src);
3657 movss(dst, Address(rscratch1, 0));
3658 }
3659 }
3660
3661 void MacroAssembler::movptr(Register dst, Register src) {
3662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3663 }
3664
3665 void MacroAssembler::movptr(Register dst, Address src) {
3666 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3667 }
3668
3669 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3670 void MacroAssembler::movptr(Register dst, intptr_t src) {
3671 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3672 }
3673
3674 void MacroAssembler::movptr(Address dst, Register src) {
3675 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3676 }
3677
3678 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3679 if (reachable(src)) {
3680 Assembler::movdqu(dst, as_Address(src));
3681 } else {
3682 lea(rscratch1, src);
3683 Assembler::movdqu(dst, Address(rscratch1, 0));
3684 }
3685 }
3686
3687 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3688 if (reachable(src)) {
3689 Assembler::movdqa(dst, as_Address(src));
3690 } else {
3691 lea(rscratch1, src);
3692 Assembler::movdqa(dst, Address(rscratch1, 0));
3693 }
3694 }
3695
3696 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3697 if (reachable(src)) {
3698 Assembler::movsd(dst, as_Address(src));
3699 } else {
3700 lea(rscratch1, src);
3701 Assembler::movsd(dst, Address(rscratch1, 0));
3702 }
3703 }
3704
3705 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3706 if (reachable(src)) {
3707 Assembler::movss(dst, as_Address(src));
3708 } else {
3709 lea(rscratch1, src);
3710 Assembler::movss(dst, Address(rscratch1, 0));
3711 }
3712 }
3713
3714 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3715 if (reachable(src)) {
3716 Assembler::mulsd(dst, as_Address(src));
3717 } else {
3718 lea(rscratch1, src);
3719 Assembler::mulsd(dst, Address(rscratch1, 0));
3720 }
3721 }
3722
3723 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3724 if (reachable(src)) {
3725 Assembler::mulss(dst, as_Address(src));
3726 } else {
3727 lea(rscratch1, src);
3728 Assembler::mulss(dst, Address(rscratch1, 0));
3729 }
3730 }
3731
3732 void MacroAssembler::null_check(Register reg, int offset) {
3733 if (needs_explicit_null_check(offset)) {
3734 // provoke OS NULL exception if reg = NULL by
3735 // accessing M[reg] w/o changing any (non-CC) registers
3736 // NOTE: cmpl is plenty here to provoke a segv
3737 cmpptr(rax, Address(reg, 0));
3738 // Note: should probably use testl(rax, Address(reg, 0));
3739 // may be shorter code (however, this version of
3740 // testl needs to be implemented first)
3741 } else {
3742 // nothing to do, (later) access of M[reg + offset]
3743 // will provoke OS NULL exception if reg = NULL
3744 }
3745 }
3746
3747 void MacroAssembler::os_breakpoint() {
3748 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3749 // (e.g., MSVC can't call ps() otherwise)
3750 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3751 }
3752
3753 void MacroAssembler::pop_CPU_state() {
3754 pop_FPU_state();
3755 pop_IU_state();
3756 }
3757
3758 void MacroAssembler::pop_FPU_state() {
3759 NOT_LP64(frstor(Address(rsp, 0));)
3760 LP64_ONLY(fxrstor(Address(rsp, 0));)
3761 addptr(rsp, FPUStateSizeInWords * wordSize);
3762 }
3763
3764 void MacroAssembler::pop_IU_state() {
3765 popa();
3766 LP64_ONLY(addq(rsp, 8));
3767 popf();
3768 }
3769
3770 // Save Integer and Float state
3771 // Warning: Stack must be 16 byte aligned (64bit)
3772 void MacroAssembler::push_CPU_state() {
3773 push_IU_state();
3774 push_FPU_state();
3775 }
3776
3777 void MacroAssembler::push_FPU_state() {
3778 subptr(rsp, FPUStateSizeInWords * wordSize);
3779 #ifndef _LP64
3780 fnsave(Address(rsp, 0));
3781 fwait();
3782 #else
3783 fxsave(Address(rsp, 0));
3784 #endif // LP64
3785 }
3786
3787 void MacroAssembler::push_IU_state() {
3788 // Push flags first because pusha kills them
3789 pushf();
3790 // Make sure rsp stays 16-byte aligned
3791 LP64_ONLY(subq(rsp, 8));
3792 pusha();
3793 }
3794
3795 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3796 // determine java_thread register
3797 if (!java_thread->is_valid()) {
3798 java_thread = rdi;
3799 get_thread(java_thread);
3800 }
3801 // we must set sp to zero to clear frame
3802 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3803 if (clear_fp) {
3804 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3805 }
3806
3807 if (clear_pc)
3808 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3809
3810 }
3811
3812 void MacroAssembler::restore_rax(Register tmp) {
3813 if (tmp == noreg) pop(rax);
3814 else if (tmp != rax) mov(rax, tmp);
3815 }
3816
3817 void MacroAssembler::round_to(Register reg, int modulus) {
3818 addptr(reg, modulus - 1);
3819 andptr(reg, -modulus);
3820 }
3821
3822 void MacroAssembler::save_rax(Register tmp) {
3823 if (tmp == noreg) push(rax);
3824 else if (tmp != rax) mov(tmp, rax);
3825 }
3826
3827 // Write serialization page so VM thread can do a pseudo remote membar.
3828 // We use the current thread pointer to calculate a thread specific
3829 // offset to write to within the page. This minimizes bus traffic
3830 // due to cache line collision.
3831 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3832 movl(tmp, thread);
3833 shrl(tmp, os::get_serialize_page_shift_count());
3834 andl(tmp, (os::vm_page_size() - sizeof(int)));
3835
3836 Address index(noreg, tmp, Address::times_1);
3837 ExternalAddress page(os::get_memory_serialize_page());
3838
3839 // Size of store must match masking code above
3840 movl(as_Address(ArrayAddress(page, index)), tmp);
3841 }
3842
3843 // Calls to C land
3844 //
3845 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3846 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3847 // has to be reset to 0. This is required to allow proper stack traversal.
3848 void MacroAssembler::set_last_Java_frame(Register java_thread,
3849 Register last_java_sp,
3850 Register last_java_fp,
3851 address last_java_pc) {
3852 // determine java_thread register
3853 if (!java_thread->is_valid()) {
3854 java_thread = rdi;
3855 get_thread(java_thread);
3856 }
3857 // determine last_java_sp register
3858 if (!last_java_sp->is_valid()) {
3859 last_java_sp = rsp;
3860 }
3861
3862 // last_java_fp is optional
3863
3864 if (last_java_fp->is_valid()) {
3865 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3866 }
3867
3868 // last_java_pc is optional
3869
3870 if (last_java_pc != NULL) {
3871 lea(Address(java_thread,
3872 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3873 InternalAddress(last_java_pc));
3874
3875 }
3876 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3877 }
3878
3879 void MacroAssembler::shlptr(Register dst, int imm8) {
3880 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3881 }
3882
3883 void MacroAssembler::shrptr(Register dst, int imm8) {
3884 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3885 }
3886
3887 void MacroAssembler::sign_extend_byte(Register reg) {
3888 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3889 movsbl(reg, reg); // movsxb
3890 } else {
3891 shll(reg, 24);
3892 sarl(reg, 24);
3893 }
3894 }
3895
3896 void MacroAssembler::sign_extend_short(Register reg) {
3897 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3898 movswl(reg, reg); // movsxw
3899 } else {
3900 shll(reg, 16);
3901 sarl(reg, 16);
3902 }
3903 }
3904
3905 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3906 assert(reachable(src), "Address should be reachable");
3907 testl(dst, as_Address(src));
3908 }
3909
3910 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3911 if (reachable(src)) {
3912 Assembler::sqrtsd(dst, as_Address(src));
3913 } else {
3914 lea(rscratch1, src);
3915 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3916 }
3917 }
3918
3919 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3920 if (reachable(src)) {
3921 Assembler::sqrtss(dst, as_Address(src));
3922 } else {
3923 lea(rscratch1, src);
3924 Assembler::sqrtss(dst, Address(rscratch1, 0));
3925 }
3926 }
3927
3928 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3929 if (reachable(src)) {
3930 Assembler::subsd(dst, as_Address(src));
3931 } else {
3932 lea(rscratch1, src);
3933 Assembler::subsd(dst, Address(rscratch1, 0));
3934 }
3935 }
3936
3937 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3938 if (reachable(src)) {
3939 Assembler::subss(dst, as_Address(src));
3940 } else {
3941 lea(rscratch1, src);
3942 Assembler::subss(dst, Address(rscratch1, 0));
3943 }
3944 }
3945
3946 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3947 if (reachable(src)) {
3948 Assembler::ucomisd(dst, as_Address(src));
3949 } else {
3950 lea(rscratch1, src);
3951 Assembler::ucomisd(dst, Address(rscratch1, 0));
3952 }
3953 }
3954
3955 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3956 if (reachable(src)) {
3957 Assembler::ucomiss(dst, as_Address(src));
3958 } else {
3959 lea(rscratch1, src);
3960 Assembler::ucomiss(dst, Address(rscratch1, 0));
3961 }
3962 }
3963
3964 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3965 // Used in sign-bit flipping with aligned address.
3966 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3967 if (reachable(src)) {
3968 Assembler::xorpd(dst, as_Address(src));
3969 } else {
3970 lea(rscratch1, src);
3971 Assembler::xorpd(dst, Address(rscratch1, 0));
3972 }
3973 }
3974
3975 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3976 // Used in sign-bit flipping with aligned address.
3977 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3978 if (reachable(src)) {
3979 Assembler::xorps(dst, as_Address(src));
3980 } else {
3981 lea(rscratch1, src);
3982 Assembler::xorps(dst, Address(rscratch1, 0));
3983 }
3984 }
3985
3986 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3987 // Used in sign-bit flipping with aligned address.
3988 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3989 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3990 if (reachable(src)) {
3991 Assembler::pshufb(dst, as_Address(src));
3992 } else {
3993 lea(rscratch1, src);
3994 Assembler::pshufb(dst, Address(rscratch1, 0));
3995 }
3996 }
3997
3998 // AVX 3-operands instructions
3999
4000 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4001 if (reachable(src)) {
4002 vaddsd(dst, nds, as_Address(src));
4003 } else {
4004 lea(rscratch1, src);
4005 vaddsd(dst, nds, Address(rscratch1, 0));
4006 }
4007 }
4008
4009 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4010 if (reachable(src)) {
4011 vaddss(dst, nds, as_Address(src));
4012 } else {
4013 lea(rscratch1, src);
4014 vaddss(dst, nds, Address(rscratch1, 0));
4015 }
4016 }
4017
4018 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4019 if (reachable(src)) {
4020 vandpd(dst, nds, as_Address(src), vector256);
4021 } else {
4022 lea(rscratch1, src);
4023 vandpd(dst, nds, Address(rscratch1, 0), vector256);
4024 }
4025 }
4026
4027 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4028 if (reachable(src)) {
4029 vandps(dst, nds, as_Address(src), vector256);
4030 } else {
4031 lea(rscratch1, src);
4032 vandps(dst, nds, Address(rscratch1, 0), vector256);
4033 }
4034 }
4035
4036 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4037 if (reachable(src)) {
4038 vdivsd(dst, nds, as_Address(src));
4039 } else {
4040 lea(rscratch1, src);
4041 vdivsd(dst, nds, Address(rscratch1, 0));
4042 }
4043 }
4044
4045 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4046 if (reachable(src)) {
4047 vdivss(dst, nds, as_Address(src));
4048 } else {
4049 lea(rscratch1, src);
4050 vdivss(dst, nds, Address(rscratch1, 0));
4051 }
4052 }
4053
4054 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4055 if (reachable(src)) {
4056 vmulsd(dst, nds, as_Address(src));
4057 } else {
4058 lea(rscratch1, src);
4059 vmulsd(dst, nds, Address(rscratch1, 0));
4060 }
4061 }
4062
4063 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4064 if (reachable(src)) {
4065 vmulss(dst, nds, as_Address(src));
4066 } else {
4067 lea(rscratch1, src);
4068 vmulss(dst, nds, Address(rscratch1, 0));
4069 }
4070 }
4071
4072 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4073 if (reachable(src)) {
4074 vsubsd(dst, nds, as_Address(src));
4075 } else {
4076 lea(rscratch1, src);
4077 vsubsd(dst, nds, Address(rscratch1, 0));
4078 }
4079 }
4080
4081 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4082 if (reachable(src)) {
4083 vsubss(dst, nds, as_Address(src));
4084 } else {
4085 lea(rscratch1, src);
4086 vsubss(dst, nds, Address(rscratch1, 0));
4087 }
4088 }
4089
4090 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4091 if (reachable(src)) {
4092 vxorpd(dst, nds, as_Address(src), vector256);
4093 } else {
4094 lea(rscratch1, src);
4095 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4096 }
4097 }
4098
4099 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4100 if (reachable(src)) {
4101 vxorps(dst, nds, as_Address(src), vector256);
4102 } else {
4103 lea(rscratch1, src);
4104 vxorps(dst, nds, Address(rscratch1, 0), vector256);
4105 }
4106 }
4107
4108
4109 //////////////////////////////////////////////////////////////////////////////////
4110 #if INCLUDE_ALL_GCS
4111
4112 void MacroAssembler::g1_write_barrier_pre(Register obj,
4113 Register pre_val,
4114 Register thread,
4115 Register tmp,
4116 bool tosca_live,
4117 bool expand_call) {
4118
4119 // If expand_call is true then we expand the call_VM_leaf macro
4120 // directly to skip generating the check by
4121 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4122
4123 #ifdef _LP64
4124 assert(thread == r15_thread, "must be");
4125 #endif // _LP64
4126
4127 Label done;
4128 Label runtime;
4129
4130 assert(pre_val != noreg, "check this code");
4131
4132 if (obj != noreg) {
4133 assert_different_registers(obj, pre_val, tmp);
4134 assert(pre_val != rax, "check this code");
4135 }
4136
4137 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4138 PtrQueue::byte_offset_of_active()));
4139 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4140 PtrQueue::byte_offset_of_index()));
4141 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4142 PtrQueue::byte_offset_of_buf()));
4143
4144
4145 // Is marking active?
4146 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4147 cmpl(in_progress, 0);
4148 } else {
4149 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4150 cmpb(in_progress, 0);
4151 }
4152 jcc(Assembler::equal, done);
4153
4154 // Do we need to load the previous value?
4155 if (obj != noreg) {
4156 load_heap_oop(pre_val, Address(obj, 0));
4157 }
4158
4159 // Is the previous value null?
4160 cmpptr(pre_val, (int32_t) NULL_WORD);
4161 jcc(Assembler::equal, done);
4162
4163 // Can we store original value in the thread's buffer?
4164 // Is index == 0?
4165 // (The index field is typed as size_t.)
4166
4167 movptr(tmp, index); // tmp := *index_adr
4168 cmpptr(tmp, 0); // tmp == 0?
4169 jcc(Assembler::equal, runtime); // If yes, goto runtime
4170
4171 subptr(tmp, wordSize); // tmp := tmp - wordSize
4172 movptr(index, tmp); // *index_adr := tmp
4173 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4174
4175 // Record the previous value
4176 movptr(Address(tmp, 0), pre_val);
4177 jmp(done);
4178
4179 bind(runtime);
4180 // save the live input values
4181 if(tosca_live) push(rax);
4182
4183 if (obj != noreg && obj != rax)
4184 push(obj);
4185
4186 if (pre_val != rax)
4187 push(pre_val);
4188
4189 // Calling the runtime using the regular call_VM_leaf mechanism generates
4190 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4191 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4192 //
4193 // If we care generating the pre-barrier without a frame (e.g. in the
4194 // intrinsified Reference.get() routine) then ebp might be pointing to
4195 // the caller frame and so this check will most likely fail at runtime.
4196 //
4197 // Expanding the call directly bypasses the generation of the check.
4198 // So when we do not have have a full interpreter frame on the stack
4199 // expand_call should be passed true.
4200
4201 NOT_LP64( push(thread); )
4202
4203 if (expand_call) {
4204 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4205 pass_arg1(this, thread);
4206 pass_arg0(this, pre_val);
4207 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4208 } else {
4209 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4210 }
4211
4212 NOT_LP64( pop(thread); )
4213
4214 // save the live input values
4215 if (pre_val != rax)
4216 pop(pre_val);
4217
4218 if (obj != noreg && obj != rax)
4219 pop(obj);
4220
4221 if(tosca_live) pop(rax);
4222
4223 bind(done);
4224 }
4225
4226 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4227 Register new_val,
4228 Register thread,
4229 Register tmp,
4230 Register tmp2) {
4231 #ifdef _LP64
4232 assert(thread == r15_thread, "must be");
4233 #endif // _LP64
4234
4235 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4236 PtrQueue::byte_offset_of_index()));
4237 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4238 PtrQueue::byte_offset_of_buf()));
4239
4240 BarrierSet* bs = Universe::heap()->barrier_set();
4241 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4242 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4243
4244 Label done;
4245 Label runtime;
4246
4247 // Does store cross heap regions?
4248
4249 movptr(tmp, store_addr);
4250 xorptr(tmp, new_val);
4251 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4252 jcc(Assembler::equal, done);
4253
4254 // crosses regions, storing NULL?
4255
4256 cmpptr(new_val, (int32_t) NULL_WORD);
4257 jcc(Assembler::equal, done);
4258
4259 // storing region crossing non-NULL, is card already dirty?
4260
4261 const Register card_addr = tmp;
4262 const Register cardtable = tmp2;
4263
4264 movptr(card_addr, store_addr);
4265 shrptr(card_addr, CardTableModRefBS::card_shift);
4266 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4267 // a valid address and therefore is not properly handled by the relocation code.
4268 movptr(cardtable, (intptr_t)ct->byte_map_base);
4269 addptr(card_addr, cardtable);
4270
4271 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4272 jcc(Assembler::equal, done);
4273
4274 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4275 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4276 jcc(Assembler::equal, done);
4277
4278
4279 // storing a region crossing, non-NULL oop, card is clean.
4280 // dirty card and log.
4281
4282 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4283
4284 cmpl(queue_index, 0);
4285 jcc(Assembler::equal, runtime);
4286 subl(queue_index, wordSize);
4287 movptr(tmp2, buffer);
4288 #ifdef _LP64
4289 movslq(rscratch1, queue_index);
4290 addq(tmp2, rscratch1);
4291 movq(Address(tmp2, 0), card_addr);
4292 #else
4293 addl(tmp2, queue_index);
4294 movl(Address(tmp2, 0), card_addr);
4295 #endif
4296 jmp(done);
4297
4298 bind(runtime);
4299 // save the live input values
4300 push(store_addr);
4301 push(new_val);
4302 #ifdef _LP64
4303 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4304 #else
4305 push(thread);
4306 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4307 pop(thread);
4308 #endif
4309 pop(new_val);
4310 pop(store_addr);
4311
4312 bind(done);
4313 }
4314
4315 #endif // INCLUDE_ALL_GCS
4316 //////////////////////////////////////////////////////////////////////////////////
4317
4318
4319 void MacroAssembler::store_check(Register obj) {
4320 // Does a store check for the oop in register obj. The content of
4321 // register obj is destroyed afterwards.
4322 store_check_part_1(obj);
4323 store_check_part_2(obj);
4324 }
4325
4326 void MacroAssembler::store_check(Register obj, Address dst) {
4327 store_check(obj);
4328 }
4329
4330
4331 // split the store check operation so that other instructions can be scheduled inbetween
4332 void MacroAssembler::store_check_part_1(Register obj) {
4333 BarrierSet* bs = Universe::heap()->barrier_set();
4334 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4335 shrptr(obj, CardTableModRefBS::card_shift);
4336 }
4337
4338 void MacroAssembler::store_check_part_2(Register obj) {
4339 BarrierSet* bs = Universe::heap()->barrier_set();
4340 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4341 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4342 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4343
4344 // The calculation for byte_map_base is as follows:
4345 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4346 // So this essentially converts an address to a displacement and it will
4347 // never need to be relocated. On 64bit however the value may be too
4348 // large for a 32bit displacement.
4349 intptr_t disp = (intptr_t) ct->byte_map_base;
4350 if (is_simm32(disp)) {
4351 Address cardtable(noreg, obj, Address::times_1, disp);
4352 movb(cardtable, 0);
4353 } else {
4354 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4355 // displacement and done in a single instruction given favorable mapping and a
4356 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4357 // entry and that entry is not properly handled by the relocation code.
4358 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4359 Address index(noreg, obj, Address::times_1);
4360 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4361 }
4362 }
4363
4364 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4365 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4366 }
4367
4368 // Force generation of a 4 byte immediate value even if it fits into 8bit
4369 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4370 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4371 }
4372
4373 void MacroAssembler::subptr(Register dst, Register src) {
4374 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4375 }
4376
4377 // C++ bool manipulation
4378 void MacroAssembler::testbool(Register dst) {
4379 if(sizeof(bool) == 1)
4380 testb(dst, 0xff);
4381 else if(sizeof(bool) == 2) {
4382 // testw implementation needed for two byte bools
4383 ShouldNotReachHere();
4384 } else if(sizeof(bool) == 4)
4385 testl(dst, dst);
4386 else
4387 // unsupported
4388 ShouldNotReachHere();
4389 }
4390
4391 void MacroAssembler::testptr(Register dst, Register src) {
4392 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4393 }
4394
4395 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4396 void MacroAssembler::tlab_allocate(Register obj,
4397 Register var_size_in_bytes,
4398 int con_size_in_bytes,
4399 Register t1,
4400 Register t2,
4401 Label& slow_case) {
4402 assert_different_registers(obj, t1, t2);
4403 assert_different_registers(obj, var_size_in_bytes, t1);
4404 Register end = t2;
4405 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4406
4407 verify_tlab();
4408
4409 NOT_LP64(get_thread(thread));
4410
4411 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4412 if (var_size_in_bytes == noreg) {
4413 lea(end, Address(obj, con_size_in_bytes));
4414 } else {
4415 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4416 }
4417 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4418 jcc(Assembler::above, slow_case);
4419
4420 // update the tlab top pointer
4421 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4422
4423 // recover var_size_in_bytes if necessary
4424 if (var_size_in_bytes == end) {
4425 subptr(var_size_in_bytes, obj);
4426 }
4427 verify_tlab();
4428 }
4429
4430 // Preserves rbx, and rdx.
4431 Register MacroAssembler::tlab_refill(Label& retry,
4432 Label& try_eden,
4433 Label& slow_case) {
4434 Register top = rax;
4435 Register t1 = rcx;
4436 Register t2 = rsi;
4437 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4438 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4439 Label do_refill, discard_tlab;
4440
4441 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4442 // No allocation in the shared eden.
4443 jmp(slow_case);
4444 }
4445
4446 NOT_LP64(get_thread(thread_reg));
4447
4448 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4449 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4450
4451 // calculate amount of free space
4452 subptr(t1, top);
4453 shrptr(t1, LogHeapWordSize);
4454
4455 // Retain tlab and allocate object in shared space if
4456 // the amount free in the tlab is too large to discard.
4457 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4458 jcc(Assembler::lessEqual, discard_tlab);
4459
4460 // Retain
4461 // %%% yuck as movptr...
4462 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4463 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4464 if (TLABStats) {
4465 // increment number of slow_allocations
4466 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4467 }
4468 jmp(try_eden);
4469
4470 bind(discard_tlab);
4471 if (TLABStats) {
4472 // increment number of refills
4473 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4474 // accumulate wastage -- t1 is amount free in tlab
4475 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4476 }
4477
4478 // if tlab is currently allocated (top or end != null) then
4479 // fill [top, end + alignment_reserve) with array object
4480 testptr(top, top);
4481 jcc(Assembler::zero, do_refill);
4482
4483 // set up the mark word
4484 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4485 // set the length to the remaining space
4486 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4487 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4488 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4489 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4490 // set klass to intArrayKlass
4491 // dubious reloc why not an oop reloc?
4492 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4493 // store klass last. concurrent gcs assumes klass length is valid if
4494 // klass field is not null.
4495 store_klass(top, t1);
4496
4497 movptr(t1, top);
4498 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4499 incr_allocated_bytes(thread_reg, t1, 0);
4500
4501 // refill the tlab with an eden allocation
4502 bind(do_refill);
4503 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4504 shlptr(t1, LogHeapWordSize);
4505 // allocate new tlab, address returned in top
4506 eden_allocate(top, t1, 0, t2, slow_case);
4507
4508 // Check that t1 was preserved in eden_allocate.
4509 #ifdef ASSERT
4510 if (UseTLAB) {
4511 Label ok;
4512 Register tsize = rsi;
4513 assert_different_registers(tsize, thread_reg, t1);
4514 push(tsize);
4515 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4516 shlptr(tsize, LogHeapWordSize);
4517 cmpptr(t1, tsize);
4518 jcc(Assembler::equal, ok);
4519 STOP("assert(t1 != tlab size)");
4520 should_not_reach_here();
4521
4522 bind(ok);
4523 pop(tsize);
4524 }
4525 #endif
4526 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4527 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4528 addptr(top, t1);
4529 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4530 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4531 verify_tlab();
4532 jmp(retry);
4533
4534 return thread_reg; // for use by caller
4535 }
4536
4537 void MacroAssembler::incr_allocated_bytes(Register thread,
4538 Register var_size_in_bytes,
4539 int con_size_in_bytes,
4540 Register t1) {
4541 if (!thread->is_valid()) {
4542 #ifdef _LP64
4543 thread = r15_thread;
4544 #else
4545 assert(t1->is_valid(), "need temp reg");
4546 thread = t1;
4547 get_thread(thread);
4548 #endif
4549 }
4550
4551 #ifdef _LP64
4552 if (var_size_in_bytes->is_valid()) {
4553 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4554 } else {
4555 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4556 }
4557 #else
4558 if (var_size_in_bytes->is_valid()) {
4559 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4560 } else {
4561 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4562 }
4563 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4564 #endif
4565 }
4566
4567 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4568 pusha();
4569
4570 // if we are coming from c1, xmm registers may be live
4571 int off = 0;
4572 if (UseSSE == 1) {
4573 subptr(rsp, sizeof(jdouble)*8);
4574 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4575 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4576 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4577 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4578 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4579 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4580 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4581 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4582 } else if (UseSSE >= 2) {
4583 #ifdef COMPILER2
4584 if (MaxVectorSize > 16) {
4585 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4586 // Save upper half of YMM registes
4587 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4588 vextractf128h(Address(rsp, 0),xmm0);
4589 vextractf128h(Address(rsp, 16),xmm1);
4590 vextractf128h(Address(rsp, 32),xmm2);
4591 vextractf128h(Address(rsp, 48),xmm3);
4592 vextractf128h(Address(rsp, 64),xmm4);
4593 vextractf128h(Address(rsp, 80),xmm5);
4594 vextractf128h(Address(rsp, 96),xmm6);
4595 vextractf128h(Address(rsp,112),xmm7);
4596 #ifdef _LP64
4597 vextractf128h(Address(rsp,128),xmm8);
4598 vextractf128h(Address(rsp,144),xmm9);
4599 vextractf128h(Address(rsp,160),xmm10);
4600 vextractf128h(Address(rsp,176),xmm11);
4601 vextractf128h(Address(rsp,192),xmm12);
4602 vextractf128h(Address(rsp,208),xmm13);
4603 vextractf128h(Address(rsp,224),xmm14);
4604 vextractf128h(Address(rsp,240),xmm15);
4605 #endif
4606 }
4607 #endif
4608 // Save whole 128bit (16 bytes) XMM regiters
4609 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4610 movdqu(Address(rsp,off++*16),xmm0);
4611 movdqu(Address(rsp,off++*16),xmm1);
4612 movdqu(Address(rsp,off++*16),xmm2);
4613 movdqu(Address(rsp,off++*16),xmm3);
4614 movdqu(Address(rsp,off++*16),xmm4);
4615 movdqu(Address(rsp,off++*16),xmm5);
4616 movdqu(Address(rsp,off++*16),xmm6);
4617 movdqu(Address(rsp,off++*16),xmm7);
4618 #ifdef _LP64
4619 movdqu(Address(rsp,off++*16),xmm8);
4620 movdqu(Address(rsp,off++*16),xmm9);
4621 movdqu(Address(rsp,off++*16),xmm10);
4622 movdqu(Address(rsp,off++*16),xmm11);
4623 movdqu(Address(rsp,off++*16),xmm12);
4624 movdqu(Address(rsp,off++*16),xmm13);
4625 movdqu(Address(rsp,off++*16),xmm14);
4626 movdqu(Address(rsp,off++*16),xmm15);
4627 #endif
4628 }
4629
4630 // Preserve registers across runtime call
4631 int incoming_argument_and_return_value_offset = -1;
4632 if (num_fpu_regs_in_use > 1) {
4633 // Must preserve all other FPU regs (could alternatively convert
4634 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4635 // FPU state, but can not trust C compiler)
4636 NEEDS_CLEANUP;
4637 // NOTE that in this case we also push the incoming argument(s) to
4638 // the stack and restore it later; we also use this stack slot to
4639 // hold the return value from dsin, dcos etc.
4640 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4641 subptr(rsp, sizeof(jdouble));
4642 fstp_d(Address(rsp, 0));
4643 }
4644 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4645 for (int i = nb_args-1; i >= 0; i--) {
4646 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4647 }
4648 }
4649
4650 subptr(rsp, nb_args*sizeof(jdouble));
4651 for (int i = 0; i < nb_args; i++) {
4652 fstp_d(Address(rsp, i*sizeof(jdouble)));
4653 }
4654
4655 #ifdef _LP64
4656 if (nb_args > 0) {
4657 movdbl(xmm0, Address(rsp, 0));
4658 }
4659 if (nb_args > 1) {
4660 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4661 }
4662 assert(nb_args <= 2, "unsupported number of args");
4663 #endif // _LP64
4664
4665 // NOTE: we must not use call_VM_leaf here because that requires a
4666 // complete interpreter frame in debug mode -- same bug as 4387334
4667 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4668 // do proper 64bit abi
4669
4670 NEEDS_CLEANUP;
4671 // Need to add stack banging before this runtime call if it needs to
4672 // be taken; however, there is no generic stack banging routine at
4673 // the MacroAssembler level
4674
4675 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4676
4677 #ifdef _LP64
4678 movsd(Address(rsp, 0), xmm0);
4679 fld_d(Address(rsp, 0));
4680 #endif // _LP64
4681 addptr(rsp, sizeof(jdouble) * nb_args);
4682 if (num_fpu_regs_in_use > 1) {
4683 // Must save return value to stack and then restore entire FPU
4684 // stack except incoming arguments
4685 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4686 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4687 fld_d(Address(rsp, 0));
4688 addptr(rsp, sizeof(jdouble));
4689 }
4690 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4691 addptr(rsp, sizeof(jdouble) * nb_args);
4692 }
4693
4694 off = 0;
4695 if (UseSSE == 1) {
4696 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4697 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4698 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4699 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4700 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4701 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4702 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4703 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4704 addptr(rsp, sizeof(jdouble)*8);
4705 } else if (UseSSE >= 2) {
4706 // Restore whole 128bit (16 bytes) XMM regiters
4707 movdqu(xmm0, Address(rsp,off++*16));
4708 movdqu(xmm1, Address(rsp,off++*16));
4709 movdqu(xmm2, Address(rsp,off++*16));
4710 movdqu(xmm3, Address(rsp,off++*16));
4711 movdqu(xmm4, Address(rsp,off++*16));
4712 movdqu(xmm5, Address(rsp,off++*16));
4713 movdqu(xmm6, Address(rsp,off++*16));
4714 movdqu(xmm7, Address(rsp,off++*16));
4715 #ifdef _LP64
4716 movdqu(xmm8, Address(rsp,off++*16));
4717 movdqu(xmm9, Address(rsp,off++*16));
4718 movdqu(xmm10, Address(rsp,off++*16));
4719 movdqu(xmm11, Address(rsp,off++*16));
4720 movdqu(xmm12, Address(rsp,off++*16));
4721 movdqu(xmm13, Address(rsp,off++*16));
4722 movdqu(xmm14, Address(rsp,off++*16));
4723 movdqu(xmm15, Address(rsp,off++*16));
4724 #endif
4725 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4726 #ifdef COMPILER2
4727 if (MaxVectorSize > 16) {
4728 // Restore upper half of YMM registes.
4729 vinsertf128h(xmm0, Address(rsp, 0));
4730 vinsertf128h(xmm1, Address(rsp, 16));
4731 vinsertf128h(xmm2, Address(rsp, 32));
4732 vinsertf128h(xmm3, Address(rsp, 48));
4733 vinsertf128h(xmm4, Address(rsp, 64));
4734 vinsertf128h(xmm5, Address(rsp, 80));
4735 vinsertf128h(xmm6, Address(rsp, 96));
4736 vinsertf128h(xmm7, Address(rsp,112));
4737 #ifdef _LP64
4738 vinsertf128h(xmm8, Address(rsp,128));
4739 vinsertf128h(xmm9, Address(rsp,144));
4740 vinsertf128h(xmm10, Address(rsp,160));
4741 vinsertf128h(xmm11, Address(rsp,176));
4742 vinsertf128h(xmm12, Address(rsp,192));
4743 vinsertf128h(xmm13, Address(rsp,208));
4744 vinsertf128h(xmm14, Address(rsp,224));
4745 vinsertf128h(xmm15, Address(rsp,240));
4746 #endif
4747 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4748 }
4749 #endif
4750 }
4751 popa();
4752 }
4753
4754 static const double pi_4 = 0.7853981633974483;
4755
4756 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4757 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4758 // was attempted in this code; unfortunately it appears that the
4759 // switch to 80-bit precision and back causes this to be
4760 // unprofitable compared with simply performing a runtime call if
4761 // the argument is out of the (-pi/4, pi/4) range.
4762
4763 Register tmp = noreg;
4764 if (!VM_Version::supports_cmov()) {
4765 // fcmp needs a temporary so preserve rbx,
4766 tmp = rbx;
4767 push(tmp);
4768 }
4769
4770 Label slow_case, done;
4771
4772 ExternalAddress pi4_adr = (address)&pi_4;
4773 if (reachable(pi4_adr)) {
4774 // x ?<= pi/4
4775 fld_d(pi4_adr);
4776 fld_s(1); // Stack: X PI/4 X
4777 fabs(); // Stack: |X| PI/4 X
4778 fcmp(tmp);
4779 jcc(Assembler::above, slow_case);
4780
4781 // fastest case: -pi/4 <= x <= pi/4
4782 switch(trig) {
4783 case 's':
4784 fsin();
4785 break;
4786 case 'c':
4787 fcos();
4788 break;
4789 case 't':
4790 ftan();
4791 break;
4792 default:
4793 assert(false, "bad intrinsic");
4794 break;
4795 }
4796 jmp(done);
4797 }
4798
4799 // slow case: runtime call
4800 bind(slow_case);
4801
4802 switch(trig) {
4803 case 's':
4804 {
4805 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4806 }
4807 break;
4808 case 'c':
4809 {
4810 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4811 }
4812 break;
4813 case 't':
4814 {
4815 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4816 }
4817 break;
4818 default:
4819 assert(false, "bad intrinsic");
4820 break;
4821 }
4822
4823 // Come here with result in F-TOS
4824 bind(done);
4825
4826 if (tmp != noreg) {
4827 pop(tmp);
4828 }
4829 }
4830
4831
4832 // Look up the method for a megamorphic invokeinterface call.
4833 // The target method is determined by <intf_klass, itable_index>.
4834 // The receiver klass is in recv_klass.
4835 // On success, the result will be in method_result, and execution falls through.
4836 // On failure, execution transfers to the given label.
4837 void MacroAssembler::lookup_interface_method(Register recv_klass,
4838 Register intf_klass,
4839 RegisterOrConstant itable_index,
4840 Register method_result,
4841 Register scan_temp,
4842 Label& L_no_such_interface) {
4843 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4844 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4845 "caller must use same register for non-constant itable index as for method");
4846
4847 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4848 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4849 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4850 int scan_step = itableOffsetEntry::size() * wordSize;
4851 int vte_size = vtableEntry::size() * wordSize;
4852 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4853 assert(vte_size == wordSize, "else adjust times_vte_scale");
4854
4855 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4856
4857 // %%% Could store the aligned, prescaled offset in the klassoop.
4858 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4859 if (HeapWordsPerLong > 1) {
4860 // Round up to align_object_offset boundary
4861 // see code for InstanceKlass::start_of_itable!
4862 round_to(scan_temp, BytesPerLong);
4863 }
4864
4865 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4866 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4867 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4868
4869 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4870 // if (scan->interface() == intf) {
4871 // result = (klass + scan->offset() + itable_index);
4872 // }
4873 // }
4874 Label search, found_method;
4875
4876 for (int peel = 1; peel >= 0; peel--) {
4877 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4878 cmpptr(intf_klass, method_result);
4879
4880 if (peel) {
4881 jccb(Assembler::equal, found_method);
4882 } else {
4883 jccb(Assembler::notEqual, search);
4884 // (invert the test to fall through to found_method...)
4885 }
4886
4887 if (!peel) break;
4888
4889 bind(search);
4890
4891 // Check that the previous entry is non-null. A null entry means that
4892 // the receiver class doesn't implement the interface, and wasn't the
4893 // same as when the caller was compiled.
4894 testptr(method_result, method_result);
4895 jcc(Assembler::zero, L_no_such_interface);
4896 addptr(scan_temp, scan_step);
4897 }
4898
4899 bind(found_method);
4900
4901 // Got a hit.
4902 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4903 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4904 }
4905
4906
4907 // virtual method calling
4908 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4909 RegisterOrConstant vtable_index,
4910 Register method_result) {
4911 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4912 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4913 Address vtable_entry_addr(recv_klass,
4914 vtable_index, Address::times_ptr,
4915 base + vtableEntry::method_offset_in_bytes());
4916 movptr(method_result, vtable_entry_addr);
4917 }
4918
4919
4920 void MacroAssembler::check_klass_subtype(Register sub_klass,
4921 Register super_klass,
4922 Register temp_reg,
4923 Label& L_success) {
4924 Label L_failure;
4925 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4926 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4927 bind(L_failure);
4928 }
4929
4930
4931 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4932 Register super_klass,
4933 Register temp_reg,
4934 Label* L_success,
4935 Label* L_failure,
4936 Label* L_slow_path,
4937 RegisterOrConstant super_check_offset) {
4938 assert_different_registers(sub_klass, super_klass, temp_reg);
4939 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4940 if (super_check_offset.is_register()) {
4941 assert_different_registers(sub_klass, super_klass,
4942 super_check_offset.as_register());
4943 } else if (must_load_sco) {
4944 assert(temp_reg != noreg, "supply either a temp or a register offset");
4945 }
4946
4947 Label L_fallthrough;
4948 int label_nulls = 0;
4949 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4950 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4951 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4952 assert(label_nulls <= 1, "at most one NULL in the batch");
4953
4954 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4955 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4956 Address super_check_offset_addr(super_klass, sco_offset);
4957
4958 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4959 // range of a jccb. If this routine grows larger, reconsider at
4960 // least some of these.
4961 #define local_jcc(assembler_cond, label) \
4962 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4963 else jcc( assembler_cond, label) /*omit semi*/
4964
4965 // Hacked jmp, which may only be used just before L_fallthrough.
4966 #define final_jmp(label) \
4967 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4968 else jmp(label) /*omit semi*/
4969
4970 // If the pointers are equal, we are done (e.g., String[] elements).
4971 // This self-check enables sharing of secondary supertype arrays among
4972 // non-primary types such as array-of-interface. Otherwise, each such
4973 // type would need its own customized SSA.
4974 // We move this check to the front of the fast path because many
4975 // type checks are in fact trivially successful in this manner,
4976 // so we get a nicely predicted branch right at the start of the check.
4977 cmpptr(sub_klass, super_klass);
4978 local_jcc(Assembler::equal, *L_success);
4979
4980 // Check the supertype display:
4981 if (must_load_sco) {
4982 // Positive movl does right thing on LP64.
4983 movl(temp_reg, super_check_offset_addr);
4984 super_check_offset = RegisterOrConstant(temp_reg);
4985 }
4986 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4987 cmpptr(super_klass, super_check_addr); // load displayed supertype
4988
4989 // This check has worked decisively for primary supers.
4990 // Secondary supers are sought in the super_cache ('super_cache_addr').
4991 // (Secondary supers are interfaces and very deeply nested subtypes.)
4992 // This works in the same check above because of a tricky aliasing
4993 // between the super_cache and the primary super display elements.
4994 // (The 'super_check_addr' can address either, as the case requires.)
4995 // Note that the cache is updated below if it does not help us find
4996 // what we need immediately.
4997 // So if it was a primary super, we can just fail immediately.
4998 // Otherwise, it's the slow path for us (no success at this point).
4999
5000 if (super_check_offset.is_register()) {
5001 local_jcc(Assembler::equal, *L_success);
5002 cmpl(super_check_offset.as_register(), sc_offset);
5003 if (L_failure == &L_fallthrough) {
5004 local_jcc(Assembler::equal, *L_slow_path);
5005 } else {
5006 local_jcc(Assembler::notEqual, *L_failure);
5007 final_jmp(*L_slow_path);
5008 }
5009 } else if (super_check_offset.as_constant() == sc_offset) {
5010 // Need a slow path; fast failure is impossible.
5011 if (L_slow_path == &L_fallthrough) {
5012 local_jcc(Assembler::equal, *L_success);
5013 } else {
5014 local_jcc(Assembler::notEqual, *L_slow_path);
5015 final_jmp(*L_success);
5016 }
5017 } else {
5018 // No slow path; it's a fast decision.
5019 if (L_failure == &L_fallthrough) {
5020 local_jcc(Assembler::equal, *L_success);
5021 } else {
5022 local_jcc(Assembler::notEqual, *L_failure);
5023 final_jmp(*L_success);
5024 }
5025 }
5026
5027 bind(L_fallthrough);
5028
5029 #undef local_jcc
5030 #undef final_jmp
5031 }
5032
5033
5034 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5035 Register super_klass,
5036 Register temp_reg,
5037 Register temp2_reg,
5038 Label* L_success,
5039 Label* L_failure,
5040 bool set_cond_codes) {
5041 assert_different_registers(sub_klass, super_klass, temp_reg);
5042 if (temp2_reg != noreg)
5043 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5044 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5045
5046 Label L_fallthrough;
5047 int label_nulls = 0;
5048 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5049 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5050 assert(label_nulls <= 1, "at most one NULL in the batch");
5051
5052 // a couple of useful fields in sub_klass:
5053 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5054 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5055 Address secondary_supers_addr(sub_klass, ss_offset);
5056 Address super_cache_addr( sub_klass, sc_offset);
5057
5058 // Do a linear scan of the secondary super-klass chain.
5059 // This code is rarely used, so simplicity is a virtue here.
5060 // The repne_scan instruction uses fixed registers, which we must spill.
5061 // Don't worry too much about pre-existing connections with the input regs.
5062
5063 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5064 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5065
5066 // Get super_klass value into rax (even if it was in rdi or rcx).
5067 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5068 if (super_klass != rax || UseCompressedOops) {
5069 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5070 mov(rax, super_klass);
5071 }
5072 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5073 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5074
5075 #ifndef PRODUCT
5076 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5077 ExternalAddress pst_counter_addr((address) pst_counter);
5078 NOT_LP64( incrementl(pst_counter_addr) );
5079 LP64_ONLY( lea(rcx, pst_counter_addr) );
5080 LP64_ONLY( incrementl(Address(rcx, 0)) );
5081 #endif //PRODUCT
5082
5083 // We will consult the secondary-super array.
5084 movptr(rdi, secondary_supers_addr);
5085 // Load the array length. (Positive movl does right thing on LP64.)
5086 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5087 // Skip to start of data.
5088 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5089
5090 // Scan RCX words at [RDI] for an occurrence of RAX.
5091 // Set NZ/Z based on last compare.
5092 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5093 // not change flags (only scas instruction which is repeated sets flags).
5094 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5095
5096 testptr(rax,rax); // Set Z = 0
5097 repne_scan();
5098
5099 // Unspill the temp. registers:
5100 if (pushed_rdi) pop(rdi);
5101 if (pushed_rcx) pop(rcx);
5102 if (pushed_rax) pop(rax);
5103
5104 if (set_cond_codes) {
5105 // Special hack for the AD files: rdi is guaranteed non-zero.
5106 assert(!pushed_rdi, "rdi must be left non-NULL");
5107 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5108 }
5109
5110 if (L_failure == &L_fallthrough)
5111 jccb(Assembler::notEqual, *L_failure);
5112 else jcc(Assembler::notEqual, *L_failure);
5113
5114 // Success. Cache the super we found and proceed in triumph.
5115 movptr(super_cache_addr, super_klass);
5116
5117 if (L_success != &L_fallthrough) {
5118 jmp(*L_success);
5119 }
5120
5121 #undef IS_A_TEMP
5122
5123 bind(L_fallthrough);
5124 }
5125
5126
5127 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5128 if (VM_Version::supports_cmov()) {
5129 cmovl(cc, dst, src);
5130 } else {
5131 Label L;
5132 jccb(negate_condition(cc), L);
5133 movl(dst, src);
5134 bind(L);
5135 }
5136 }
5137
5138 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5139 if (VM_Version::supports_cmov()) {
5140 cmovl(cc, dst, src);
5141 } else {
5142 Label L;
5143 jccb(negate_condition(cc), L);
5144 movl(dst, src);
5145 bind(L);
5146 }
5147 }
5148
5149 void MacroAssembler::verify_oop(Register reg, const char* s) {
5150 if (!VerifyOops) return;
5151
5152 // Pass register number to verify_oop_subroutine
5153 const char* b = NULL;
5154 {
5155 ResourceMark rm;
5156 stringStream ss;
5157 ss.print("verify_oop: %s: %s", reg->name(), s);
5158 b = code_string(ss.as_string());
5159 }
5160 BLOCK_COMMENT("verify_oop {");
5161 #ifdef _LP64
5162 push(rscratch1); // save r10, trashed by movptr()
5163 #endif
5164 push(rax); // save rax,
5165 push(reg); // pass register argument
5166 ExternalAddress buffer((address) b);
5167 // avoid using pushptr, as it modifies scratch registers
5168 // and our contract is not to modify anything
5169 movptr(rax, buffer.addr());
5170 push(rax);
5171 // call indirectly to solve generation ordering problem
5172 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5173 call(rax);
5174 // Caller pops the arguments (oop, message) and restores rax, r10
5175 BLOCK_COMMENT("} verify_oop");
5176 }
5177
5178
5179 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5180 Register tmp,
5181 int offset) {
5182 intptr_t value = *delayed_value_addr;
5183 if (value != 0)
5184 return RegisterOrConstant(value + offset);
5185
5186 // load indirectly to solve generation ordering problem
5187 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5188
5189 #ifdef ASSERT
5190 { Label L;
5191 testptr(tmp, tmp);
5192 if (WizardMode) {
5193 const char* buf = NULL;
5194 {
5195 ResourceMark rm;
5196 stringStream ss;
5197 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5198 buf = code_string(ss.as_string());
5199 }
5200 jcc(Assembler::notZero, L);
5201 STOP(buf);
5202 } else {
5203 jccb(Assembler::notZero, L);
5204 hlt();
5205 }
5206 bind(L);
5207 }
5208 #endif
5209
5210 if (offset != 0)
5211 addptr(tmp, offset);
5212
5213 return RegisterOrConstant(tmp);
5214 }
5215
5216
5217 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5218 int extra_slot_offset) {
5219 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5220 int stackElementSize = Interpreter::stackElementSize;
5221 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5222 #ifdef ASSERT
5223 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5224 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5225 #endif
5226 Register scale_reg = noreg;
5227 Address::ScaleFactor scale_factor = Address::no_scale;
5228 if (arg_slot.is_constant()) {
5229 offset += arg_slot.as_constant() * stackElementSize;
5230 } else {
5231 scale_reg = arg_slot.as_register();
5232 scale_factor = Address::times(stackElementSize);
5233 }
5234 offset += wordSize; // return PC is on stack
5235 return Address(rsp, scale_reg, scale_factor, offset);
5236 }
5237
5238
5239 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5240 if (!VerifyOops) return;
5241
5242 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5243 // Pass register number to verify_oop_subroutine
5244 const char* b = NULL;
5245 {
5246 ResourceMark rm;
5247 stringStream ss;
5248 ss.print("verify_oop_addr: %s", s);
5249 b = code_string(ss.as_string());
5250 }
5251 #ifdef _LP64
5252 push(rscratch1); // save r10, trashed by movptr()
5253 #endif
5254 push(rax); // save rax,
5255 // addr may contain rsp so we will have to adjust it based on the push
5256 // we just did (and on 64 bit we do two pushes)
5257 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5258 // stores rax into addr which is backwards of what was intended.
5259 if (addr.uses(rsp)) {
5260 lea(rax, addr);
5261 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5262 } else {
5263 pushptr(addr);
5264 }
5265
5266 ExternalAddress buffer((address) b);
5267 // pass msg argument
5268 // avoid using pushptr, as it modifies scratch registers
5269 // and our contract is not to modify anything
5270 movptr(rax, buffer.addr());
5271 push(rax);
5272
5273 // call indirectly to solve generation ordering problem
5274 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5275 call(rax);
5276 // Caller pops the arguments (addr, message) and restores rax, r10.
5277 }
5278
5279 void MacroAssembler::verify_tlab() {
5280 #ifdef ASSERT
5281 if (UseTLAB && VerifyOops) {
5282 Label next, ok;
5283 Register t1 = rsi;
5284 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5285
5286 push(t1);
5287 NOT_LP64(push(thread_reg));
5288 NOT_LP64(get_thread(thread_reg));
5289
5290 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5291 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5292 jcc(Assembler::aboveEqual, next);
5293 STOP("assert(top >= start)");
5294 should_not_reach_here();
5295
5296 bind(next);
5297 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5298 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5299 jcc(Assembler::aboveEqual, ok);
5300 STOP("assert(top <= end)");
5301 should_not_reach_here();
5302
5303 bind(ok);
5304 NOT_LP64(pop(thread_reg));
5305 pop(t1);
5306 }
5307 #endif
5308 }
5309
5310 class ControlWord {
5311 public:
5312 int32_t _value;
5313
5314 int rounding_control() const { return (_value >> 10) & 3 ; }
5315 int precision_control() const { return (_value >> 8) & 3 ; }
5316 bool precision() const { return ((_value >> 5) & 1) != 0; }
5317 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5318 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5319 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5320 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5321 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5322
5323 void print() const {
5324 // rounding control
5325 const char* rc;
5326 switch (rounding_control()) {
5327 case 0: rc = "round near"; break;
5328 case 1: rc = "round down"; break;
5329 case 2: rc = "round up "; break;
5330 case 3: rc = "chop "; break;
5331 };
5332 // precision control
5333 const char* pc;
5334 switch (precision_control()) {
5335 case 0: pc = "24 bits "; break;
5336 case 1: pc = "reserved"; break;
5337 case 2: pc = "53 bits "; break;
5338 case 3: pc = "64 bits "; break;
5339 };
5340 // flags
5341 char f[9];
5342 f[0] = ' ';
5343 f[1] = ' ';
5344 f[2] = (precision ()) ? 'P' : 'p';
5345 f[3] = (underflow ()) ? 'U' : 'u';
5346 f[4] = (overflow ()) ? 'O' : 'o';
5347 f[5] = (zero_divide ()) ? 'Z' : 'z';
5348 f[6] = (denormalized()) ? 'D' : 'd';
5349 f[7] = (invalid ()) ? 'I' : 'i';
5350 f[8] = '\x0';
5351 // output
5352 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5353 }
5354
5355 };
5356
5357 class StatusWord {
5358 public:
5359 int32_t _value;
5360
5361 bool busy() const { return ((_value >> 15) & 1) != 0; }
5362 bool C3() const { return ((_value >> 14) & 1) != 0; }
5363 bool C2() const { return ((_value >> 10) & 1) != 0; }
5364 bool C1() const { return ((_value >> 9) & 1) != 0; }
5365 bool C0() const { return ((_value >> 8) & 1) != 0; }
5366 int top() const { return (_value >> 11) & 7 ; }
5367 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5368 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5369 bool precision() const { return ((_value >> 5) & 1) != 0; }
5370 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5371 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5372 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5373 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5374 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5375
5376 void print() const {
5377 // condition codes
5378 char c[5];
5379 c[0] = (C3()) ? '3' : '-';
5380 c[1] = (C2()) ? '2' : '-';
5381 c[2] = (C1()) ? '1' : '-';
5382 c[3] = (C0()) ? '0' : '-';
5383 c[4] = '\x0';
5384 // flags
5385 char f[9];
5386 f[0] = (error_status()) ? 'E' : '-';
5387 f[1] = (stack_fault ()) ? 'S' : '-';
5388 f[2] = (precision ()) ? 'P' : '-';
5389 f[3] = (underflow ()) ? 'U' : '-';
5390 f[4] = (overflow ()) ? 'O' : '-';
5391 f[5] = (zero_divide ()) ? 'Z' : '-';
5392 f[6] = (denormalized()) ? 'D' : '-';
5393 f[7] = (invalid ()) ? 'I' : '-';
5394 f[8] = '\x0';
5395 // output
5396 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5397 }
5398
5399 };
5400
5401 class TagWord {
5402 public:
5403 int32_t _value;
5404
5405 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5406
5407 void print() const {
5408 printf("%04x", _value & 0xFFFF);
5409 }
5410
5411 };
5412
5413 class FPU_Register {
5414 public:
5415 int32_t _m0;
5416 int32_t _m1;
5417 int16_t _ex;
5418
5419 bool is_indefinite() const {
5420 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5421 }
5422
5423 void print() const {
5424 char sign = (_ex < 0) ? '-' : '+';
5425 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5426 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5427 };
5428
5429 };
5430
5431 class FPU_State {
5432 public:
5433 enum {
5434 register_size = 10,
5435 number_of_registers = 8,
5436 register_mask = 7
5437 };
5438
5439 ControlWord _control_word;
5440 StatusWord _status_word;
5441 TagWord _tag_word;
5442 int32_t _error_offset;
5443 int32_t _error_selector;
5444 int32_t _data_offset;
5445 int32_t _data_selector;
5446 int8_t _register[register_size * number_of_registers];
5447
5448 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5449 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5450
5451 const char* tag_as_string(int tag) const {
5452 switch (tag) {
5453 case 0: return "valid";
5454 case 1: return "zero";
5455 case 2: return "special";
5456 case 3: return "empty";
5457 }
5458 ShouldNotReachHere();
5459 return NULL;
5460 }
5461
5462 void print() const {
5463 // print computation registers
5464 { int t = _status_word.top();
5465 for (int i = 0; i < number_of_registers; i++) {
5466 int j = (i - t) & register_mask;
5467 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5468 st(j)->print();
5469 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5470 }
5471 }
5472 printf("\n");
5473 // print control registers
5474 printf("ctrl = "); _control_word.print(); printf("\n");
5475 printf("stat = "); _status_word .print(); printf("\n");
5476 printf("tags = "); _tag_word .print(); printf("\n");
5477 }
5478
5479 };
5480
5481 class Flag_Register {
5482 public:
5483 int32_t _value;
5484
5485 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5486 bool direction() const { return ((_value >> 10) & 1) != 0; }
5487 bool sign() const { return ((_value >> 7) & 1) != 0; }
5488 bool zero() const { return ((_value >> 6) & 1) != 0; }
5489 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5490 bool parity() const { return ((_value >> 2) & 1) != 0; }
5491 bool carry() const { return ((_value >> 0) & 1) != 0; }
5492
5493 void print() const {
5494 // flags
5495 char f[8];
5496 f[0] = (overflow ()) ? 'O' : '-';
5497 f[1] = (direction ()) ? 'D' : '-';
5498 f[2] = (sign ()) ? 'S' : '-';
5499 f[3] = (zero ()) ? 'Z' : '-';
5500 f[4] = (auxiliary_carry()) ? 'A' : '-';
5501 f[5] = (parity ()) ? 'P' : '-';
5502 f[6] = (carry ()) ? 'C' : '-';
5503 f[7] = '\x0';
5504 // output
5505 printf("%08x flags = %s", _value, f);
5506 }
5507
5508 };
5509
5510 class IU_Register {
5511 public:
5512 int32_t _value;
5513
5514 void print() const {
5515 printf("%08x %11d", _value, _value);
5516 }
5517
5518 };
5519
5520 class IU_State {
5521 public:
5522 Flag_Register _eflags;
5523 IU_Register _rdi;
5524 IU_Register _rsi;
5525 IU_Register _rbp;
5526 IU_Register _rsp;
5527 IU_Register _rbx;
5528 IU_Register _rdx;
5529 IU_Register _rcx;
5530 IU_Register _rax;
5531
5532 void print() const {
5533 // computation registers
5534 printf("rax, = "); _rax.print(); printf("\n");
5535 printf("rbx, = "); _rbx.print(); printf("\n");
5536 printf("rcx = "); _rcx.print(); printf("\n");
5537 printf("rdx = "); _rdx.print(); printf("\n");
5538 printf("rdi = "); _rdi.print(); printf("\n");
5539 printf("rsi = "); _rsi.print(); printf("\n");
5540 printf("rbp, = "); _rbp.print(); printf("\n");
5541 printf("rsp = "); _rsp.print(); printf("\n");
5542 printf("\n");
5543 // control registers
5544 printf("flgs = "); _eflags.print(); printf("\n");
5545 }
5546 };
5547
5548
5549 class CPU_State {
5550 public:
5551 FPU_State _fpu_state;
5552 IU_State _iu_state;
5553
5554 void print() const {
5555 printf("--------------------------------------------------\n");
5556 _iu_state .print();
5557 printf("\n");
5558 _fpu_state.print();
5559 printf("--------------------------------------------------\n");
5560 }
5561
5562 };
5563
5564
5565 static void _print_CPU_state(CPU_State* state) {
5566 state->print();
5567 };
5568
5569
5570 void MacroAssembler::print_CPU_state() {
5571 push_CPU_state();
5572 push(rsp); // pass CPU state
5573 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5574 addptr(rsp, wordSize); // discard argument
5575 pop_CPU_state();
5576 }
5577
5578
5579 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5580 static int counter = 0;
5581 FPU_State* fs = &state->_fpu_state;
5582 counter++;
5583 // For leaf calls, only verify that the top few elements remain empty.
5584 // We only need 1 empty at the top for C2 code.
5585 if( stack_depth < 0 ) {
5586 if( fs->tag_for_st(7) != 3 ) {
5587 printf("FPR7 not empty\n");
5588 state->print();
5589 assert(false, "error");
5590 return false;
5591 }
5592 return true; // All other stack states do not matter
5593 }
5594
5595 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5596 "bad FPU control word");
5597
5598 // compute stack depth
5599 int i = 0;
5600 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5601 int d = i;
5602 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5603 // verify findings
5604 if (i != FPU_State::number_of_registers) {
5605 // stack not contiguous
5606 printf("%s: stack not contiguous at ST%d\n", s, i);
5607 state->print();
5608 assert(false, "error");
5609 return false;
5610 }
5611 // check if computed stack depth corresponds to expected stack depth
5612 if (stack_depth < 0) {
5613 // expected stack depth is -stack_depth or less
5614 if (d > -stack_depth) {
5615 // too many elements on the stack
5616 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5617 state->print();
5618 assert(false, "error");
5619 return false;
5620 }
5621 } else {
5622 // expected stack depth is stack_depth
5623 if (d != stack_depth) {
5624 // wrong stack depth
5625 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5626 state->print();
5627 assert(false, "error");
5628 return false;
5629 }
5630 }
5631 // everything is cool
5632 return true;
5633 }
5634
5635
5636 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5637 if (!VerifyFPU) return;
5638 push_CPU_state();
5639 push(rsp); // pass CPU state
5640 ExternalAddress msg((address) s);
5641 // pass message string s
5642 pushptr(msg.addr());
5643 push(stack_depth); // pass stack depth
5644 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5645 addptr(rsp, 3 * wordSize); // discard arguments
5646 // check for error
5647 { Label L;
5648 testl(rax, rax);
5649 jcc(Assembler::notZero, L);
5650 int3(); // break if error condition
5651 bind(L);
5652 }
5653 pop_CPU_state();
5654 }
5655
5656 void MacroAssembler::restore_cpu_control_state_after_jni() {
5657 // Either restore the MXCSR register after returning from the JNI Call
5658 // or verify that it wasn't changed (with -Xcheck:jni flag).
5659 if (VM_Version::supports_sse()) {
5660 if (RestoreMXCSROnJNICalls) {
5661 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5662 } else if (CheckJNICalls) {
5663 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5664 }
5665 }
5666 if (VM_Version::supports_avx()) {
5667 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5668 vzeroupper();
5669 }
5670
5671 #ifndef _LP64
5672 // Either restore the x87 floating pointer control word after returning
5673 // from the JNI call or verify that it wasn't changed.
5674 if (CheckJNICalls) {
5675 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5676 }
5677 #endif // _LP64
5678 }
5679
5680
5681 void MacroAssembler::load_klass(Register dst, Register src) {
5682 #ifdef _LP64
5683 if (UseCompressedClassPointers) {
5684 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5685 decode_klass_not_null(dst);
5686 } else
5687 #endif
5688 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5689 }
5690
5691 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5692 load_klass(dst, src);
5693 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5694 }
5695
5696 void MacroAssembler::store_klass(Register dst, Register src) {
5697 #ifdef _LP64
5698 if (UseCompressedClassPointers) {
5699 encode_klass_not_null(src);
5700 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5701 } else
5702 #endif
5703 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5704 }
5705
5706 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5707 #ifdef _LP64
5708 // FIXME: Must change all places where we try to load the klass.
5709 if (UseCompressedOops) {
5710 movl(dst, src);
5711 decode_heap_oop(dst);
5712 } else
5713 #endif
5714 movptr(dst, src);
5715 }
5716
5717 // Doesn't do verfication, generates fixed size code
5718 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5719 #ifdef _LP64
5720 if (UseCompressedOops) {
5721 movl(dst, src);
5722 decode_heap_oop_not_null(dst);
5723 } else
5724 #endif
5725 movptr(dst, src);
5726 }
5727
5728 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5729 #ifdef _LP64
5730 if (UseCompressedOops) {
5731 assert(!dst.uses(src), "not enough registers");
5732 encode_heap_oop(src);
5733 movl(dst, src);
5734 } else
5735 #endif
5736 movptr(dst, src);
5737 }
5738
5739 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5740 assert_different_registers(src1, tmp);
5741 #ifdef _LP64
5742 if (UseCompressedOops) {
5743 bool did_push = false;
5744 if (tmp == noreg) {
5745 tmp = rax;
5746 push(tmp);
5747 did_push = true;
5748 assert(!src2.uses(rsp), "can't push");
5749 }
5750 load_heap_oop(tmp, src2);
5751 cmpptr(src1, tmp);
5752 if (did_push) pop(tmp);
5753 } else
5754 #endif
5755 cmpptr(src1, src2);
5756 }
5757
5758 // Used for storing NULLs.
5759 void MacroAssembler::store_heap_oop_null(Address dst) {
5760 #ifdef _LP64
5761 if (UseCompressedOops) {
5762 movl(dst, (int32_t)NULL_WORD);
5763 } else {
5764 movslq(dst, (int32_t)NULL_WORD);
5765 }
5766 #else
5767 movl(dst, (int32_t)NULL_WORD);
5768 #endif
5769 }
5770
5771 #ifdef _LP64
5772 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5773 if (UseCompressedClassPointers) {
5774 // Store to klass gap in destination
5775 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5776 }
5777 }
5778
5779 #ifdef ASSERT
5780 void MacroAssembler::verify_heapbase(const char* msg) {
5781 assert (UseCompressedOops, "should be compressed");
5782 assert (Universe::heap() != NULL, "java heap should be initialized");
5783 if (CheckCompressedOops) {
5784 Label ok;
5785 push(rscratch1); // cmpptr trashes rscratch1
5786 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5787 jcc(Assembler::equal, ok);
5788 STOP(msg);
5789 bind(ok);
5790 pop(rscratch1);
5791 }
5792 }
5793 #endif
5794
5795 // Algorithm must match oop.inline.hpp encode_heap_oop.
5796 void MacroAssembler::encode_heap_oop(Register r) {
5797 #ifdef ASSERT
5798 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5799 #endif
5800 verify_oop(r, "broken oop in encode_heap_oop");
5801 if (Universe::narrow_oop_base() == NULL) {
5802 if (Universe::narrow_oop_shift() != 0) {
5803 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5804 shrq(r, LogMinObjAlignmentInBytes);
5805 }
5806 return;
5807 }
5808 testq(r, r);
5809 cmovq(Assembler::equal, r, r12_heapbase);
5810 subq(r, r12_heapbase);
5811 shrq(r, LogMinObjAlignmentInBytes);
5812 }
5813
5814 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5815 #ifdef ASSERT
5816 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5817 if (CheckCompressedOops) {
5818 Label ok;
5819 testq(r, r);
5820 jcc(Assembler::notEqual, ok);
5821 STOP("null oop passed to encode_heap_oop_not_null");
5822 bind(ok);
5823 }
5824 #endif
5825 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5826 if (Universe::narrow_oop_base() != NULL) {
5827 subq(r, r12_heapbase);
5828 }
5829 if (Universe::narrow_oop_shift() != 0) {
5830 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5831 shrq(r, LogMinObjAlignmentInBytes);
5832 }
5833 }
5834
5835 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5836 #ifdef ASSERT
5837 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5838 if (CheckCompressedOops) {
5839 Label ok;
5840 testq(src, src);
5841 jcc(Assembler::notEqual, ok);
5842 STOP("null oop passed to encode_heap_oop_not_null2");
5843 bind(ok);
5844 }
5845 #endif
5846 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5847 if (dst != src) {
5848 movq(dst, src);
5849 }
5850 if (Universe::narrow_oop_base() != NULL) {
5851 subq(dst, r12_heapbase);
5852 }
5853 if (Universe::narrow_oop_shift() != 0) {
5854 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5855 shrq(dst, LogMinObjAlignmentInBytes);
5856 }
5857 }
5858
5859 void MacroAssembler::decode_heap_oop(Register r) {
5860 #ifdef ASSERT
5861 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5862 #endif
5863 if (Universe::narrow_oop_base() == NULL) {
5864 if (Universe::narrow_oop_shift() != 0) {
5865 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5866 shlq(r, LogMinObjAlignmentInBytes);
5867 }
5868 } else {
5869 Label done;
5870 shlq(r, LogMinObjAlignmentInBytes);
5871 jccb(Assembler::equal, done);
5872 addq(r, r12_heapbase);
5873 bind(done);
5874 }
5875 verify_oop(r, "broken oop in decode_heap_oop");
5876 }
5877
5878 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5879 // Note: it will change flags
5880 assert (UseCompressedOops, "should only be used for compressed headers");
5881 assert (Universe::heap() != NULL, "java heap should be initialized");
5882 // Cannot assert, unverified entry point counts instructions (see .ad file)
5883 // vtableStubs also counts instructions in pd_code_size_limit.
5884 // Also do not verify_oop as this is called by verify_oop.
5885 if (Universe::narrow_oop_shift() != 0) {
5886 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5887 shlq(r, LogMinObjAlignmentInBytes);
5888 if (Universe::narrow_oop_base() != NULL) {
5889 addq(r, r12_heapbase);
5890 }
5891 } else {
5892 assert (Universe::narrow_oop_base() == NULL, "sanity");
5893 }
5894 }
5895
5896 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5897 // Note: it will change flags
5898 assert (UseCompressedOops, "should only be used for compressed headers");
5899 assert (Universe::heap() != NULL, "java heap should be initialized");
5900 // Cannot assert, unverified entry point counts instructions (see .ad file)
5901 // vtableStubs also counts instructions in pd_code_size_limit.
5902 // Also do not verify_oop as this is called by verify_oop.
5903 if (Universe::narrow_oop_shift() != 0) {
5904 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5905 if (LogMinObjAlignmentInBytes == Address::times_8) {
5906 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5907 } else {
5908 if (dst != src) {
5909 movq(dst, src);
5910 }
5911 shlq(dst, LogMinObjAlignmentInBytes);
5912 if (Universe::narrow_oop_base() != NULL) {
5913 addq(dst, r12_heapbase);
5914 }
5915 }
5916 } else {
5917 assert (Universe::narrow_oop_base() == NULL, "sanity");
5918 if (dst != src) {
5919 movq(dst, src);
5920 }
5921 }
5922 }
5923
5924 void MacroAssembler::encode_klass_not_null(Register r) {
5925 if (Universe::narrow_klass_base() != NULL) {
5926 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5927 assert(r != r12_heapbase, "Encoding a klass in r12");
5928 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5929 subq(r, r12_heapbase);
5930 }
5931 if (Universe::narrow_klass_shift() != 0) {
5932 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5933 shrq(r, LogKlassAlignmentInBytes);
5934 }
5935 if (Universe::narrow_klass_base() != NULL) {
5936 reinit_heapbase();
5937 }
5938 }
5939
5940 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5941 if (dst == src) {
5942 encode_klass_not_null(src);
5943 } else {
5944 if (Universe::narrow_klass_base() != NULL) {
5945 mov64(dst, (int64_t)Universe::narrow_klass_base());
5946 negq(dst);
5947 addq(dst, src);
5948 } else {
5949 movptr(dst, src);
5950 }
5951 if (Universe::narrow_klass_shift() != 0) {
5952 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5953 shrq(dst, LogKlassAlignmentInBytes);
5954 }
5955 }
5956 }
5957
5958 // Function instr_size_for_decode_klass_not_null() counts the instructions
5959 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5960 // when (Universe::heap() != NULL). Hence, if the instructions they
5961 // generate change, then this method needs to be updated.
5962 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5963 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5964 if (Universe::narrow_klass_base() != NULL) {
5965 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5966 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5967 } else {
5968 // longest load decode klass function, mov64, leaq
5969 return 16;
5970 }
5971 }
5972
5973 // !!! If the instructions that get generated here change then function
5974 // instr_size_for_decode_klass_not_null() needs to get updated.
5975 void MacroAssembler::decode_klass_not_null(Register r) {
5976 // Note: it will change flags
5977 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5978 assert(r != r12_heapbase, "Decoding a klass in r12");
5979 // Cannot assert, unverified entry point counts instructions (see .ad file)
5980 // vtableStubs also counts instructions in pd_code_size_limit.
5981 // Also do not verify_oop as this is called by verify_oop.
5982 if (Universe::narrow_klass_shift() != 0) {
5983 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5984 shlq(r, LogKlassAlignmentInBytes);
5985 }
5986 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5987 if (Universe::narrow_klass_base() != NULL) {
5988 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5989 addq(r, r12_heapbase);
5990 reinit_heapbase();
5991 }
5992 }
5993
5994 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5995 // Note: it will change flags
5996 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5997 if (dst == src) {
5998 decode_klass_not_null(dst);
5999 } else {
6000 // Cannot assert, unverified entry point counts instructions (see .ad file)
6001 // vtableStubs also counts instructions in pd_code_size_limit.
6002 // Also do not verify_oop as this is called by verify_oop.
6003 mov64(dst, (int64_t)Universe::narrow_klass_base());
6004 if (Universe::narrow_klass_shift() != 0) {
6005 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6006 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6007 leaq(dst, Address(dst, src, Address::times_8, 0));
6008 } else {
6009 addq(dst, src);
6010 }
6011 }
6012 }
6013
6014 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6015 assert (UseCompressedOops, "should only be used for compressed headers");
6016 assert (Universe::heap() != NULL, "java heap should be initialized");
6017 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6018 int oop_index = oop_recorder()->find_index(obj);
6019 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6020 mov_narrow_oop(dst, oop_index, rspec);
6021 }
6022
6023 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6024 assert (UseCompressedOops, "should only be used for compressed headers");
6025 assert (Universe::heap() != NULL, "java heap should be initialized");
6026 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6027 int oop_index = oop_recorder()->find_index(obj);
6028 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6029 mov_narrow_oop(dst, oop_index, rspec);
6030 }
6031
6032 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6033 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6034 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6035 int klass_index = oop_recorder()->find_index(k);
6036 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6037 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6038 }
6039
6040 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6041 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6042 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6043 int klass_index = oop_recorder()->find_index(k);
6044 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6045 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6046 }
6047
6048 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6049 assert (UseCompressedOops, "should only be used for compressed headers");
6050 assert (Universe::heap() != NULL, "java heap should be initialized");
6051 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6052 int oop_index = oop_recorder()->find_index(obj);
6053 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6054 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6055 }
6056
6057 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6058 assert (UseCompressedOops, "should only be used for compressed headers");
6059 assert (Universe::heap() != NULL, "java heap should be initialized");
6060 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6061 int oop_index = oop_recorder()->find_index(obj);
6062 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6063 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6064 }
6065
6066 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6067 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6068 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6069 int klass_index = oop_recorder()->find_index(k);
6070 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6071 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6072 }
6073
6074 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6075 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6076 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6077 int klass_index = oop_recorder()->find_index(k);
6078 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6079 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6080 }
6081
6082 void MacroAssembler::reinit_heapbase() {
6083 if (UseCompressedOops || UseCompressedClassPointers) {
6084 if (Universe::heap() != NULL) {
6085 if (Universe::narrow_oop_base() == NULL) {
6086 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6087 } else {
6088 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6089 }
6090 } else {
6091 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6092 }
6093 }
6094 }
6095
6096 #endif // _LP64
6097
6098
6099 // C2 compiled method's prolog code.
6100 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6101
6102 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6103 // NativeJump::patch_verified_entry will be able to patch out the entry
6104 // code safely. The push to verify stack depth is ok at 5 bytes,
6105 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6106 // stack bang then we must use the 6 byte frame allocation even if
6107 // we have no frame. :-(
6108 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6109
6110 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6111 // Remove word for return addr
6112 framesize -= wordSize;
6113 stack_bang_size -= wordSize;
6114
6115 // Calls to C2R adapters often do not accept exceptional returns.
6116 // We require that their callers must bang for them. But be careful, because
6117 // some VM calls (such as call site linkage) can use several kilobytes of
6118 // stack. But the stack safety zone should account for that.
6119 // See bugs 4446381, 4468289, 4497237.
6120 if (stack_bang_size > 0) {
6121 generate_stack_overflow_check(stack_bang_size);
6122
6123 // We always push rbp, so that on return to interpreter rbp, will be
6124 // restored correctly and we can correct the stack.
6125 push(rbp);
6126 // Remove word for ebp
6127 framesize -= wordSize;
6128
6129 // Create frame
6130 if (framesize) {
6131 subptr(rsp, framesize);
6132 }
6133 } else {
6134 // Create frame (force generation of a 4 byte immediate value)
6135 subptr_imm32(rsp, framesize);
6136
6137 // Save RBP register now.
6138 framesize -= wordSize;
6139 movptr(Address(rsp, framesize), rbp);
6140 }
6141
6142 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6143 framesize -= wordSize;
6144 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6145 }
6146
6147 #ifndef _LP64
6148 // If method sets FPU control word do it now
6149 if (fp_mode_24b) {
6150 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6151 }
6152 if (UseSSE >= 2 && VerifyFPU) {
6153 verify_FPU(0, "FPU stack must be clean on entry");
6154 }
6155 #endif
6156
6157 #ifdef ASSERT
6158 if (VerifyStackAtCalls) {
6159 Label L;
6160 push(rax);
6161 mov(rax, rsp);
6162 andptr(rax, StackAlignmentInBytes-1);
6163 cmpptr(rax, StackAlignmentInBytes-wordSize);
6164 pop(rax);
6165 jcc(Assembler::equal, L);
6166 STOP("Stack is not properly aligned!");
6167 bind(L);
6168 }
6169 #endif
6170
6171 }
6172
6173 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6174 // cnt - number of qwords (8-byte words).
6175 // base - start address, qword aligned.
6176 assert(base==rdi, "base register must be edi for rep stos");
6177 assert(tmp==rax, "tmp register must be eax for rep stos");
6178 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6179
6180 xorptr(tmp, tmp);
6181 if (UseFastStosb) {
6182 shlptr(cnt,3); // convert to number of bytes
6183 rep_stosb();
6184 } else {
6185 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6186 rep_stos();
6187 }
6188 }
6189
6190 // IndexOf for constant substrings with size >= 8 chars
6191 // which don't need to be loaded through stack.
6192 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6193 Register cnt1, Register cnt2,
6194 int int_cnt2, Register result,
6195 XMMRegister vec, Register tmp) {
6196 ShortBranchVerifier sbv(this);
6197 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6198
6199 // This method uses pcmpestri inxtruction with bound registers
6200 // inputs:
6201 // xmm - substring
6202 // rax - substring length (elements count)
6203 // mem - scanned string
6204 // rdx - string length (elements count)
6205 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6206 // outputs:
6207 // rcx - matched index in string
6208 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6209
6210 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6211 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6212 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6213
6214 // Note, inline_string_indexOf() generates checks:
6215 // if (substr.count > string.count) return -1;
6216 // if (substr.count == 0) return 0;
6217 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6218
6219 // Load substring.
6220 movdqu(vec, Address(str2, 0));
6221 movl(cnt2, int_cnt2);
6222 movptr(result, str1); // string addr
6223
6224 if (int_cnt2 > 8) {
6225 jmpb(SCAN_TO_SUBSTR);
6226
6227 // Reload substr for rescan, this code
6228 // is executed only for large substrings (> 8 chars)
6229 bind(RELOAD_SUBSTR);
6230 movdqu(vec, Address(str2, 0));
6231 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6232
6233 bind(RELOAD_STR);
6234 // We came here after the beginning of the substring was
6235 // matched but the rest of it was not so we need to search
6236 // again. Start from the next element after the previous match.
6237
6238 // cnt2 is number of substring reminding elements and
6239 // cnt1 is number of string reminding elements when cmp failed.
6240 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6241 subl(cnt1, cnt2);
6242 addl(cnt1, int_cnt2);
6243 movl(cnt2, int_cnt2); // Now restore cnt2
6244
6245 decrementl(cnt1); // Shift to next element
6246 cmpl(cnt1, cnt2);
6247 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6248
6249 addptr(result, 2);
6250
6251 } // (int_cnt2 > 8)
6252
6253 // Scan string for start of substr in 16-byte vectors
6254 bind(SCAN_TO_SUBSTR);
6255 pcmpestri(vec, Address(result, 0), 0x0d);
6256 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6257 subl(cnt1, 8);
6258 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6259 cmpl(cnt1, cnt2);
6260 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6261 addptr(result, 16);
6262 jmpb(SCAN_TO_SUBSTR);
6263
6264 // Found a potential substr
6265 bind(FOUND_CANDIDATE);
6266 // Matched whole vector if first element matched (tmp(rcx) == 0).
6267 if (int_cnt2 == 8) {
6268 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6269 } else { // int_cnt2 > 8
6270 jccb(Assembler::overflow, FOUND_SUBSTR);
6271 }
6272 // After pcmpestri tmp(rcx) contains matched element index
6273 // Compute start addr of substr
6274 lea(result, Address(result, tmp, Address::times_2));
6275
6276 // Make sure string is still long enough
6277 subl(cnt1, tmp);
6278 cmpl(cnt1, cnt2);
6279 if (int_cnt2 == 8) {
6280 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6281 } else { // int_cnt2 > 8
6282 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6283 }
6284 // Left less then substring.
6285
6286 bind(RET_NOT_FOUND);
6287 movl(result, -1);
6288 jmpb(EXIT);
6289
6290 if (int_cnt2 > 8) {
6291 // This code is optimized for the case when whole substring
6292 // is matched if its head is matched.
6293 bind(MATCH_SUBSTR_HEAD);
6294 pcmpestri(vec, Address(result, 0), 0x0d);
6295 // Reload only string if does not match
6296 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6297
6298 Label CONT_SCAN_SUBSTR;
6299 // Compare the rest of substring (> 8 chars).
6300 bind(FOUND_SUBSTR);
6301 // First 8 chars are already matched.
6302 negptr(cnt2);
6303 addptr(cnt2, 8);
6304
6305 bind(SCAN_SUBSTR);
6306 subl(cnt1, 8);
6307 cmpl(cnt2, -8); // Do not read beyond substring
6308 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6309 // Back-up strings to avoid reading beyond substring:
6310 // cnt1 = cnt1 - cnt2 + 8
6311 addl(cnt1, cnt2); // cnt2 is negative
6312 addl(cnt1, 8);
6313 movl(cnt2, 8); negptr(cnt2);
6314 bind(CONT_SCAN_SUBSTR);
6315 if (int_cnt2 < (int)G) {
6316 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6317 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6318 } else {
6319 // calculate index in register to avoid integer overflow (int_cnt2*2)
6320 movl(tmp, int_cnt2);
6321 addptr(tmp, cnt2);
6322 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6323 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6324 }
6325 // Need to reload strings pointers if not matched whole vector
6326 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6327 addptr(cnt2, 8);
6328 jcc(Assembler::negative, SCAN_SUBSTR);
6329 // Fall through if found full substring
6330
6331 } // (int_cnt2 > 8)
6332
6333 bind(RET_FOUND);
6334 // Found result if we matched full small substring.
6335 // Compute substr offset
6336 subptr(result, str1);
6337 shrl(result, 1); // index
6338 bind(EXIT);
6339
6340 } // string_indexofC8
6341
6342 // Small strings are loaded through stack if they cross page boundary.
6343 void MacroAssembler::string_indexof(Register str1, Register str2,
6344 Register cnt1, Register cnt2,
6345 int int_cnt2, Register result,
6346 XMMRegister vec, Register tmp) {
6347 ShortBranchVerifier sbv(this);
6348 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6349 //
6350 // int_cnt2 is length of small (< 8 chars) constant substring
6351 // or (-1) for non constant substring in which case its length
6352 // is in cnt2 register.
6353 //
6354 // Note, inline_string_indexOf() generates checks:
6355 // if (substr.count > string.count) return -1;
6356 // if (substr.count == 0) return 0;
6357 //
6358 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6359
6360 // This method uses pcmpestri inxtruction with bound registers
6361 // inputs:
6362 // xmm - substring
6363 // rax - substring length (elements count)
6364 // mem - scanned string
6365 // rdx - string length (elements count)
6366 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6367 // outputs:
6368 // rcx - matched index in string
6369 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6370
6371 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6372 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6373 FOUND_CANDIDATE;
6374
6375 { //========================================================
6376 // We don't know where these strings are located
6377 // and we can't read beyond them. Load them through stack.
6378 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6379
6380 movptr(tmp, rsp); // save old SP
6381
6382 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6383 if (int_cnt2 == 1) { // One char
6384 load_unsigned_short(result, Address(str2, 0));
6385 movdl(vec, result); // move 32 bits
6386 } else if (int_cnt2 == 2) { // Two chars
6387 movdl(vec, Address(str2, 0)); // move 32 bits
6388 } else if (int_cnt2 == 4) { // Four chars
6389 movq(vec, Address(str2, 0)); // move 64 bits
6390 } else { // cnt2 = { 3, 5, 6, 7 }
6391 // Array header size is 12 bytes in 32-bit VM
6392 // + 6 bytes for 3 chars == 18 bytes,
6393 // enough space to load vec and shift.
6394 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6395 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6396 psrldq(vec, 16-(int_cnt2*2));
6397 }
6398 } else { // not constant substring
6399 cmpl(cnt2, 8);
6400 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6401
6402 // We can read beyond string if srt+16 does not cross page boundary
6403 // since heaps are aligned and mapped by pages.
6404 assert(os::vm_page_size() < (int)G, "default page should be small");
6405 movl(result, str2); // We need only low 32 bits
6406 andl(result, (os::vm_page_size()-1));
6407 cmpl(result, (os::vm_page_size()-16));
6408 jccb(Assembler::belowEqual, CHECK_STR);
6409
6410 // Move small strings to stack to allow load 16 bytes into vec.
6411 subptr(rsp, 16);
6412 int stk_offset = wordSize-2;
6413 push(cnt2);
6414
6415 bind(COPY_SUBSTR);
6416 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6417 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6418 decrement(cnt2);
6419 jccb(Assembler::notZero, COPY_SUBSTR);
6420
6421 pop(cnt2);
6422 movptr(str2, rsp); // New substring address
6423 } // non constant
6424
6425 bind(CHECK_STR);
6426 cmpl(cnt1, 8);
6427 jccb(Assembler::aboveEqual, BIG_STRINGS);
6428
6429 // Check cross page boundary.
6430 movl(result, str1); // We need only low 32 bits
6431 andl(result, (os::vm_page_size()-1));
6432 cmpl(result, (os::vm_page_size()-16));
6433 jccb(Assembler::belowEqual, BIG_STRINGS);
6434
6435 subptr(rsp, 16);
6436 int stk_offset = -2;
6437 if (int_cnt2 < 0) { // not constant
6438 push(cnt2);
6439 stk_offset += wordSize;
6440 }
6441 movl(cnt2, cnt1);
6442
6443 bind(COPY_STR);
6444 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6445 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6446 decrement(cnt2);
6447 jccb(Assembler::notZero, COPY_STR);
6448
6449 if (int_cnt2 < 0) { // not constant
6450 pop(cnt2);
6451 }
6452 movptr(str1, rsp); // New string address
6453
6454 bind(BIG_STRINGS);
6455 // Load substring.
6456 if (int_cnt2 < 0) { // -1
6457 movdqu(vec, Address(str2, 0));
6458 push(cnt2); // substr count
6459 push(str2); // substr addr
6460 push(str1); // string addr
6461 } else {
6462 // Small (< 8 chars) constant substrings are loaded already.
6463 movl(cnt2, int_cnt2);
6464 }
6465 push(tmp); // original SP
6466
6467 } // Finished loading
6468
6469 //========================================================
6470 // Start search
6471 //
6472
6473 movptr(result, str1); // string addr
6474
6475 if (int_cnt2 < 0) { // Only for non constant substring
6476 jmpb(SCAN_TO_SUBSTR);
6477
6478 // SP saved at sp+0
6479 // String saved at sp+1*wordSize
6480 // Substr saved at sp+2*wordSize
6481 // Substr count saved at sp+3*wordSize
6482
6483 // Reload substr for rescan, this code
6484 // is executed only for large substrings (> 8 chars)
6485 bind(RELOAD_SUBSTR);
6486 movptr(str2, Address(rsp, 2*wordSize));
6487 movl(cnt2, Address(rsp, 3*wordSize));
6488 movdqu(vec, Address(str2, 0));
6489 // We came here after the beginning of the substring was
6490 // matched but the rest of it was not so we need to search
6491 // again. Start from the next element after the previous match.
6492 subptr(str1, result); // Restore counter
6493 shrl(str1, 1);
6494 addl(cnt1, str1);
6495 decrementl(cnt1); // Shift to next element
6496 cmpl(cnt1, cnt2);
6497 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6498
6499 addptr(result, 2);
6500 } // non constant
6501
6502 // Scan string for start of substr in 16-byte vectors
6503 bind(SCAN_TO_SUBSTR);
6504 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6505 pcmpestri(vec, Address(result, 0), 0x0d);
6506 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6507 subl(cnt1, 8);
6508 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6509 cmpl(cnt1, cnt2);
6510 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6511 addptr(result, 16);
6512
6513 bind(ADJUST_STR);
6514 cmpl(cnt1, 8); // Do not read beyond string
6515 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6516 // Back-up string to avoid reading beyond string.
6517 lea(result, Address(result, cnt1, Address::times_2, -16));
6518 movl(cnt1, 8);
6519 jmpb(SCAN_TO_SUBSTR);
6520
6521 // Found a potential substr
6522 bind(FOUND_CANDIDATE);
6523 // After pcmpestri tmp(rcx) contains matched element index
6524
6525 // Make sure string is still long enough
6526 subl(cnt1, tmp);
6527 cmpl(cnt1, cnt2);
6528 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6529 // Left less then substring.
6530
6531 bind(RET_NOT_FOUND);
6532 movl(result, -1);
6533 jmpb(CLEANUP);
6534
6535 bind(FOUND_SUBSTR);
6536 // Compute start addr of substr
6537 lea(result, Address(result, tmp, Address::times_2));
6538
6539 if (int_cnt2 > 0) { // Constant substring
6540 // Repeat search for small substring (< 8 chars)
6541 // from new point without reloading substring.
6542 // Have to check that we don't read beyond string.
6543 cmpl(tmp, 8-int_cnt2);
6544 jccb(Assembler::greater, ADJUST_STR);
6545 // Fall through if matched whole substring.
6546 } else { // non constant
6547 assert(int_cnt2 == -1, "should be != 0");
6548
6549 addl(tmp, cnt2);
6550 // Found result if we matched whole substring.
6551 cmpl(tmp, 8);
6552 jccb(Assembler::lessEqual, RET_FOUND);
6553
6554 // Repeat search for small substring (<= 8 chars)
6555 // from new point 'str1' without reloading substring.
6556 cmpl(cnt2, 8);
6557 // Have to check that we don't read beyond string.
6558 jccb(Assembler::lessEqual, ADJUST_STR);
6559
6560 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6561 // Compare the rest of substring (> 8 chars).
6562 movptr(str1, result);
6563
6564 cmpl(tmp, cnt2);
6565 // First 8 chars are already matched.
6566 jccb(Assembler::equal, CHECK_NEXT);
6567
6568 bind(SCAN_SUBSTR);
6569 pcmpestri(vec, Address(str1, 0), 0x0d);
6570 // Need to reload strings pointers if not matched whole vector
6571 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6572
6573 bind(CHECK_NEXT);
6574 subl(cnt2, 8);
6575 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6576 addptr(str1, 16);
6577 addptr(str2, 16);
6578 subl(cnt1, 8);
6579 cmpl(cnt2, 8); // Do not read beyond substring
6580 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6581 // Back-up strings to avoid reading beyond substring.
6582 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6583 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6584 subl(cnt1, cnt2);
6585 movl(cnt2, 8);
6586 addl(cnt1, 8);
6587 bind(CONT_SCAN_SUBSTR);
6588 movdqu(vec, Address(str2, 0));
6589 jmpb(SCAN_SUBSTR);
6590
6591 bind(RET_FOUND_LONG);
6592 movptr(str1, Address(rsp, wordSize));
6593 } // non constant
6594
6595 bind(RET_FOUND);
6596 // Compute substr offset
6597 subptr(result, str1);
6598 shrl(result, 1); // index
6599
6600 bind(CLEANUP);
6601 pop(rsp); // restore SP
6602
6603 } // string_indexof
6604
6605 // Compare strings.
6606 void MacroAssembler::string_compare(Register str1, Register str2,
6607 Register cnt1, Register cnt2, Register result,
6608 XMMRegister vec1) {
6609 ShortBranchVerifier sbv(this);
6610 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6611
6612 // Compute the minimum of the string lengths and the
6613 // difference of the string lengths (stack).
6614 // Do the conditional move stuff
6615 movl(result, cnt1);
6616 subl(cnt1, cnt2);
6617 push(cnt1);
6618 cmov32(Assembler::lessEqual, cnt2, result);
6619
6620 // Is the minimum length zero?
6621 testl(cnt2, cnt2);
6622 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6623
6624 // Compare first characters
6625 load_unsigned_short(result, Address(str1, 0));
6626 load_unsigned_short(cnt1, Address(str2, 0));
6627 subl(result, cnt1);
6628 jcc(Assembler::notZero, POP_LABEL);
6629 cmpl(cnt2, 1);
6630 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6631
6632 // Check if the strings start at the same location.
6633 cmpptr(str1, str2);
6634 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6635
6636 Address::ScaleFactor scale = Address::times_2;
6637 int stride = 8;
6638
6639 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6640 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6641 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6642 Label COMPARE_TAIL_LONG;
6643 int pcmpmask = 0x19;
6644
6645 // Setup to compare 16-chars (32-bytes) vectors,
6646 // start from first character again because it has aligned address.
6647 int stride2 = 16;
6648 int adr_stride = stride << scale;
6649 int adr_stride2 = stride2 << scale;
6650
6651 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6652 // rax and rdx are used by pcmpestri as elements counters
6653 movl(result, cnt2);
6654 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6655 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6656
6657 // fast path : compare first 2 8-char vectors.
6658 bind(COMPARE_16_CHARS);
6659 movdqu(vec1, Address(str1, 0));
6660 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6661 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6662
6663 movdqu(vec1, Address(str1, adr_stride));
6664 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6665 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6666 addl(cnt1, stride);
6667
6668 // Compare the characters at index in cnt1
6669 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6670 load_unsigned_short(result, Address(str1, cnt1, scale));
6671 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6672 subl(result, cnt2);
6673 jmp(POP_LABEL);
6674
6675 // Setup the registers to start vector comparison loop
6676 bind(COMPARE_WIDE_VECTORS);
6677 lea(str1, Address(str1, result, scale));
6678 lea(str2, Address(str2, result, scale));
6679 subl(result, stride2);
6680 subl(cnt2, stride2);
6681 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6682 negptr(result);
6683
6684 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6685 bind(COMPARE_WIDE_VECTORS_LOOP);
6686 vmovdqu(vec1, Address(str1, result, scale));
6687 vpxor(vec1, Address(str2, result, scale));
6688 vptest(vec1, vec1);
6689 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6690 addptr(result, stride2);
6691 subl(cnt2, stride2);
6692 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6693 // clean upper bits of YMM registers
6694 vzeroupper();
6695
6696 // compare wide vectors tail
6697 bind(COMPARE_WIDE_TAIL);
6698 testptr(result, result);
6699 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6700
6701 movl(result, stride2);
6702 movl(cnt2, result);
6703 negptr(result);
6704 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6705
6706 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6707 bind(VECTOR_NOT_EQUAL);
6708 // clean upper bits of YMM registers
6709 vzeroupper();
6710 lea(str1, Address(str1, result, scale));
6711 lea(str2, Address(str2, result, scale));
6712 jmp(COMPARE_16_CHARS);
6713
6714 // Compare tail chars, length between 1 to 15 chars
6715 bind(COMPARE_TAIL_LONG);
6716 movl(cnt2, result);
6717 cmpl(cnt2, stride);
6718 jccb(Assembler::less, COMPARE_SMALL_STR);
6719
6720 movdqu(vec1, Address(str1, 0));
6721 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6722 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6723 subptr(cnt2, stride);
6724 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6725 lea(str1, Address(str1, result, scale));
6726 lea(str2, Address(str2, result, scale));
6727 negptr(cnt2);
6728 jmpb(WHILE_HEAD_LABEL);
6729
6730 bind(COMPARE_SMALL_STR);
6731 } else if (UseSSE42Intrinsics) {
6732 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6733 int pcmpmask = 0x19;
6734 // Setup to compare 8-char (16-byte) vectors,
6735 // start from first character again because it has aligned address.
6736 movl(result, cnt2);
6737 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6738 jccb(Assembler::zero, COMPARE_TAIL);
6739
6740 lea(str1, Address(str1, result, scale));
6741 lea(str2, Address(str2, result, scale));
6742 negptr(result);
6743
6744 // pcmpestri
6745 // inputs:
6746 // vec1- substring
6747 // rax - negative string length (elements count)
6748 // mem - scaned string
6749 // rdx - string length (elements count)
6750 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6751 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6752 // outputs:
6753 // rcx - first mismatched element index
6754 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6755
6756 bind(COMPARE_WIDE_VECTORS);
6757 movdqu(vec1, Address(str1, result, scale));
6758 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6759 // After pcmpestri cnt1(rcx) contains mismatched element index
6760
6761 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6762 addptr(result, stride);
6763 subptr(cnt2, stride);
6764 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6765
6766 // compare wide vectors tail
6767 testptr(result, result);
6768 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6769
6770 movl(cnt2, stride);
6771 movl(result, stride);
6772 negptr(result);
6773 movdqu(vec1, Address(str1, result, scale));
6774 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6775 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6776
6777 // Mismatched characters in the vectors
6778 bind(VECTOR_NOT_EQUAL);
6779 addptr(cnt1, result);
6780 load_unsigned_short(result, Address(str1, cnt1, scale));
6781 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6782 subl(result, cnt2);
6783 jmpb(POP_LABEL);
6784
6785 bind(COMPARE_TAIL); // limit is zero
6786 movl(cnt2, result);
6787 // Fallthru to tail compare
6788 }
6789 // Shift str2 and str1 to the end of the arrays, negate min
6790 lea(str1, Address(str1, cnt2, scale));
6791 lea(str2, Address(str2, cnt2, scale));
6792 decrementl(cnt2); // first character was compared already
6793 negptr(cnt2);
6794
6795 // Compare the rest of the elements
6796 bind(WHILE_HEAD_LABEL);
6797 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6798 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6799 subl(result, cnt1);
6800 jccb(Assembler::notZero, POP_LABEL);
6801 increment(cnt2);
6802 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6803
6804 // Strings are equal up to min length. Return the length difference.
6805 bind(LENGTH_DIFF_LABEL);
6806 pop(result);
6807 jmpb(DONE_LABEL);
6808
6809 // Discard the stored length difference
6810 bind(POP_LABEL);
6811 pop(cnt1);
6812
6813 // That's it
6814 bind(DONE_LABEL);
6815 }
6816
6817 // Compare char[] arrays aligned to 4 bytes or substrings.
6818 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6819 Register limit, Register result, Register chr,
6820 XMMRegister vec1, XMMRegister vec2) {
6821 ShortBranchVerifier sbv(this);
6822 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6823
6824 int length_offset = arrayOopDesc::length_offset_in_bytes();
6825 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6826
6827 // Check the input args
6828 cmpptr(ary1, ary2);
6829 jcc(Assembler::equal, TRUE_LABEL);
6830
6831 if (is_array_equ) {
6832 // Need additional checks for arrays_equals.
6833 testptr(ary1, ary1);
6834 jcc(Assembler::zero, FALSE_LABEL);
6835 testptr(ary2, ary2);
6836 jcc(Assembler::zero, FALSE_LABEL);
6837
6838 // Check the lengths
6839 movl(limit, Address(ary1, length_offset));
6840 cmpl(limit, Address(ary2, length_offset));
6841 jcc(Assembler::notEqual, FALSE_LABEL);
6842 }
6843
6844 // count == 0
6845 testl(limit, limit);
6846 jcc(Assembler::zero, TRUE_LABEL);
6847
6848 if (is_array_equ) {
6849 // Load array address
6850 lea(ary1, Address(ary1, base_offset));
6851 lea(ary2, Address(ary2, base_offset));
6852 }
6853
6854 shll(limit, 1); // byte count != 0
6855 movl(result, limit); // copy
6856
6857 if (UseAVX >= 2) {
6858 // With AVX2, use 32-byte vector compare
6859 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6860
6861 // Compare 32-byte vectors
6862 andl(result, 0x0000001e); // tail count (in bytes)
6863 andl(limit, 0xffffffe0); // vector count (in bytes)
6864 jccb(Assembler::zero, COMPARE_TAIL);
6865
6866 lea(ary1, Address(ary1, limit, Address::times_1));
6867 lea(ary2, Address(ary2, limit, Address::times_1));
6868 negptr(limit);
6869
6870 bind(COMPARE_WIDE_VECTORS);
6871 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6872 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6873 vpxor(vec1, vec2);
6874
6875 vptest(vec1, vec1);
6876 jccb(Assembler::notZero, FALSE_LABEL);
6877 addptr(limit, 32);
6878 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6879
6880 testl(result, result);
6881 jccb(Assembler::zero, TRUE_LABEL);
6882
6883 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6884 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6885 vpxor(vec1, vec2);
6886
6887 vptest(vec1, vec1);
6888 jccb(Assembler::notZero, FALSE_LABEL);
6889 jmpb(TRUE_LABEL);
6890
6891 bind(COMPARE_TAIL); // limit is zero
6892 movl(limit, result);
6893 // Fallthru to tail compare
6894 } else if (UseSSE42Intrinsics) {
6895 // With SSE4.2, use double quad vector compare
6896 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6897
6898 // Compare 16-byte vectors
6899 andl(result, 0x0000000e); // tail count (in bytes)
6900 andl(limit, 0xfffffff0); // vector count (in bytes)
6901 jccb(Assembler::zero, COMPARE_TAIL);
6902
6903 lea(ary1, Address(ary1, limit, Address::times_1));
6904 lea(ary2, Address(ary2, limit, Address::times_1));
6905 negptr(limit);
6906
6907 bind(COMPARE_WIDE_VECTORS);
6908 movdqu(vec1, Address(ary1, limit, Address::times_1));
6909 movdqu(vec2, Address(ary2, limit, Address::times_1));
6910 pxor(vec1, vec2);
6911
6912 ptest(vec1, vec1);
6913 jccb(Assembler::notZero, FALSE_LABEL);
6914 addptr(limit, 16);
6915 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6916
6917 testl(result, result);
6918 jccb(Assembler::zero, TRUE_LABEL);
6919
6920 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6921 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6922 pxor(vec1, vec2);
6923
6924 ptest(vec1, vec1);
6925 jccb(Assembler::notZero, FALSE_LABEL);
6926 jmpb(TRUE_LABEL);
6927
6928 bind(COMPARE_TAIL); // limit is zero
6929 movl(limit, result);
6930 // Fallthru to tail compare
6931 }
6932
6933 // Compare 4-byte vectors
6934 andl(limit, 0xfffffffc); // vector count (in bytes)
6935 jccb(Assembler::zero, COMPARE_CHAR);
6936
6937 lea(ary1, Address(ary1, limit, Address::times_1));
6938 lea(ary2, Address(ary2, limit, Address::times_1));
6939 negptr(limit);
6940
6941 bind(COMPARE_VECTORS);
6942 movl(chr, Address(ary1, limit, Address::times_1));
6943 cmpl(chr, Address(ary2, limit, Address::times_1));
6944 jccb(Assembler::notEqual, FALSE_LABEL);
6945 addptr(limit, 4);
6946 jcc(Assembler::notZero, COMPARE_VECTORS);
6947
6948 // Compare trailing char (final 2 bytes), if any
6949 bind(COMPARE_CHAR);
6950 testl(result, 0x2); // tail char
6951 jccb(Assembler::zero, TRUE_LABEL);
6952 load_unsigned_short(chr, Address(ary1, 0));
6953 load_unsigned_short(limit, Address(ary2, 0));
6954 cmpl(chr, limit);
6955 jccb(Assembler::notEqual, FALSE_LABEL);
6956
6957 bind(TRUE_LABEL);
6958 movl(result, 1); // return true
6959 jmpb(DONE);
6960
6961 bind(FALSE_LABEL);
6962 xorl(result, result); // return false
6963
6964 // That's it
6965 bind(DONE);
6966 if (UseAVX >= 2) {
6967 // clean upper bits of YMM registers
6968 vzeroupper();
6969 }
6970 }
6971
6972 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6973 Register to, Register value, Register count,
6974 Register rtmp, XMMRegister xtmp) {
6975 ShortBranchVerifier sbv(this);
6976 assert_different_registers(to, value, count, rtmp);
6977 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6978 Label L_fill_2_bytes, L_fill_4_bytes;
6979
6980 int shift = -1;
6981 switch (t) {
6982 case T_BYTE:
6983 shift = 2;
6984 break;
6985 case T_SHORT:
6986 shift = 1;
6987 break;
6988 case T_INT:
6989 shift = 0;
6990 break;
6991 default: ShouldNotReachHere();
6992 }
6993
6994 if (t == T_BYTE) {
6995 andl(value, 0xff);
6996 movl(rtmp, value);
6997 shll(rtmp, 8);
6998 orl(value, rtmp);
6999 }
7000 if (t == T_SHORT) {
7001 andl(value, 0xffff);
7002 }
7003 if (t == T_BYTE || t == T_SHORT) {
7004 movl(rtmp, value);
7005 shll(rtmp, 16);
7006 orl(value, rtmp);
7007 }
7008
7009 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7010 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7011 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7012 // align source address at 4 bytes address boundary
7013 if (t == T_BYTE) {
7014 // One byte misalignment happens only for byte arrays
7015 testptr(to, 1);
7016 jccb(Assembler::zero, L_skip_align1);
7017 movb(Address(to, 0), value);
7018 increment(to);
7019 decrement(count);
7020 BIND(L_skip_align1);
7021 }
7022 // Two bytes misalignment happens only for byte and short (char) arrays
7023 testptr(to, 2);
7024 jccb(Assembler::zero, L_skip_align2);
7025 movw(Address(to, 0), value);
7026 addptr(to, 2);
7027 subl(count, 1<<(shift-1));
7028 BIND(L_skip_align2);
7029 }
7030 if (UseSSE < 2) {
7031 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7032 // Fill 32-byte chunks
7033 subl(count, 8 << shift);
7034 jcc(Assembler::less, L_check_fill_8_bytes);
7035 align(16);
7036
7037 BIND(L_fill_32_bytes_loop);
7038
7039 for (int i = 0; i < 32; i += 4) {
7040 movl(Address(to, i), value);
7041 }
7042
7043 addptr(to, 32);
7044 subl(count, 8 << shift);
7045 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7046 BIND(L_check_fill_8_bytes);
7047 addl(count, 8 << shift);
7048 jccb(Assembler::zero, L_exit);
7049 jmpb(L_fill_8_bytes);
7050
7051 //
7052 // length is too short, just fill qwords
7053 //
7054 BIND(L_fill_8_bytes_loop);
7055 movl(Address(to, 0), value);
7056 movl(Address(to, 4), value);
7057 addptr(to, 8);
7058 BIND(L_fill_8_bytes);
7059 subl(count, 1 << (shift + 1));
7060 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7061 // fall through to fill 4 bytes
7062 } else {
7063 Label L_fill_32_bytes;
7064 if (!UseUnalignedLoadStores) {
7065 // align to 8 bytes, we know we are 4 byte aligned to start
7066 testptr(to, 4);
7067 jccb(Assembler::zero, L_fill_32_bytes);
7068 movl(Address(to, 0), value);
7069 addptr(to, 4);
7070 subl(count, 1<<shift);
7071 }
7072 BIND(L_fill_32_bytes);
7073 {
7074 assert( UseSSE >= 2, "supported cpu only" );
7075 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7076 movdl(xtmp, value);
7077 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7078 // Fill 64-byte chunks
7079 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7080 vpbroadcastd(xtmp, xtmp);
7081
7082 subl(count, 16 << shift);
7083 jcc(Assembler::less, L_check_fill_32_bytes);
7084 align(16);
7085
7086 BIND(L_fill_64_bytes_loop);
7087 vmovdqu(Address(to, 0), xtmp);
7088 vmovdqu(Address(to, 32), xtmp);
7089 addptr(to, 64);
7090 subl(count, 16 << shift);
7091 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7092
7093 BIND(L_check_fill_32_bytes);
7094 addl(count, 8 << shift);
7095 jccb(Assembler::less, L_check_fill_8_bytes);
7096 vmovdqu(Address(to, 0), xtmp);
7097 addptr(to, 32);
7098 subl(count, 8 << shift);
7099
7100 BIND(L_check_fill_8_bytes);
7101 // clean upper bits of YMM registers
7102 vzeroupper();
7103 } else {
7104 // Fill 32-byte chunks
7105 pshufd(xtmp, xtmp, 0);
7106
7107 subl(count, 8 << shift);
7108 jcc(Assembler::less, L_check_fill_8_bytes);
7109 align(16);
7110
7111 BIND(L_fill_32_bytes_loop);
7112
7113 if (UseUnalignedLoadStores) {
7114 movdqu(Address(to, 0), xtmp);
7115 movdqu(Address(to, 16), xtmp);
7116 } else {
7117 movq(Address(to, 0), xtmp);
7118 movq(Address(to, 8), xtmp);
7119 movq(Address(to, 16), xtmp);
7120 movq(Address(to, 24), xtmp);
7121 }
7122
7123 addptr(to, 32);
7124 subl(count, 8 << shift);
7125 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7126
7127 BIND(L_check_fill_8_bytes);
7128 }
7129 addl(count, 8 << shift);
7130 jccb(Assembler::zero, L_exit);
7131 jmpb(L_fill_8_bytes);
7132
7133 //
7134 // length is too short, just fill qwords
7135 //
7136 BIND(L_fill_8_bytes_loop);
7137 movq(Address(to, 0), xtmp);
7138 addptr(to, 8);
7139 BIND(L_fill_8_bytes);
7140 subl(count, 1 << (shift + 1));
7141 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7142 }
7143 }
7144 // fill trailing 4 bytes
7145 BIND(L_fill_4_bytes);
7146 testl(count, 1<<shift);
7147 jccb(Assembler::zero, L_fill_2_bytes);
7148 movl(Address(to, 0), value);
7149 if (t == T_BYTE || t == T_SHORT) {
7150 addptr(to, 4);
7151 BIND(L_fill_2_bytes);
7152 // fill trailing 2 bytes
7153 testl(count, 1<<(shift-1));
7154 jccb(Assembler::zero, L_fill_byte);
7155 movw(Address(to, 0), value);
7156 if (t == T_BYTE) {
7157 addptr(to, 2);
7158 BIND(L_fill_byte);
7159 // fill trailing byte
7160 testl(count, 1);
7161 jccb(Assembler::zero, L_exit);
7162 movb(Address(to, 0), value);
7163 } else {
7164 BIND(L_fill_byte);
7165 }
7166 } else {
7167 BIND(L_fill_2_bytes);
7168 }
7169 BIND(L_exit);
7170 }
7171
7172 // encode char[] to byte[] in ISO_8859_1
7173 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7174 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7175 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7176 Register tmp5, Register result) {
7177 // rsi: src
7178 // rdi: dst
7179 // rdx: len
7180 // rcx: tmp5
7181 // rax: result
7182 ShortBranchVerifier sbv(this);
7183 assert_different_registers(src, dst, len, tmp5, result);
7184 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7185
7186 // set result
7187 xorl(result, result);
7188 // check for zero length
7189 testl(len, len);
7190 jcc(Assembler::zero, L_done);
7191 movl(result, len);
7192
7193 // Setup pointers
7194 lea(src, Address(src, len, Address::times_2)); // char[]
7195 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7196 negptr(len);
7197
7198 if (UseSSE42Intrinsics || UseAVX >= 2) {
7199 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7200 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7201
7202 if (UseAVX >= 2) {
7203 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7204 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7205 movdl(tmp1Reg, tmp5);
7206 vpbroadcastd(tmp1Reg, tmp1Reg);
7207 jmpb(L_chars_32_check);
7208
7209 bind(L_copy_32_chars);
7210 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7211 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7212 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7213 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7214 jccb(Assembler::notZero, L_copy_32_chars_exit);
7215 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7216 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7217 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7218
7219 bind(L_chars_32_check);
7220 addptr(len, 32);
7221 jccb(Assembler::lessEqual, L_copy_32_chars);
7222
7223 bind(L_copy_32_chars_exit);
7224 subptr(len, 16);
7225 jccb(Assembler::greater, L_copy_16_chars_exit);
7226
7227 } else if (UseSSE42Intrinsics) {
7228 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7229 movdl(tmp1Reg, tmp5);
7230 pshufd(tmp1Reg, tmp1Reg, 0);
7231 jmpb(L_chars_16_check);
7232 }
7233
7234 bind(L_copy_16_chars);
7235 if (UseAVX >= 2) {
7236 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7237 vptest(tmp2Reg, tmp1Reg);
7238 jccb(Assembler::notZero, L_copy_16_chars_exit);
7239 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7240 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7241 } else {
7242 if (UseAVX > 0) {
7243 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7244 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7245 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7246 } else {
7247 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7248 por(tmp2Reg, tmp3Reg);
7249 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7250 por(tmp2Reg, tmp4Reg);
7251 }
7252 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7253 jccb(Assembler::notZero, L_copy_16_chars_exit);
7254 packuswb(tmp3Reg, tmp4Reg);
7255 }
7256 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7257
7258 bind(L_chars_16_check);
7259 addptr(len, 16);
7260 jccb(Assembler::lessEqual, L_copy_16_chars);
7261
7262 bind(L_copy_16_chars_exit);
7263 if (UseAVX >= 2) {
7264 // clean upper bits of YMM registers
7265 vzeroupper();
7266 }
7267 subptr(len, 8);
7268 jccb(Assembler::greater, L_copy_8_chars_exit);
7269
7270 bind(L_copy_8_chars);
7271 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7272 ptest(tmp3Reg, tmp1Reg);
7273 jccb(Assembler::notZero, L_copy_8_chars_exit);
7274 packuswb(tmp3Reg, tmp1Reg);
7275 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7276 addptr(len, 8);
7277 jccb(Assembler::lessEqual, L_copy_8_chars);
7278
7279 bind(L_copy_8_chars_exit);
7280 subptr(len, 8);
7281 jccb(Assembler::zero, L_done);
7282 }
7283
7284 bind(L_copy_1_char);
7285 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7286 testl(tmp5, 0xff00); // check if Unicode char
7287 jccb(Assembler::notZero, L_copy_1_char_exit);
7288 movb(Address(dst, len, Address::times_1, 0), tmp5);
7289 addptr(len, 1);
7290 jccb(Assembler::less, L_copy_1_char);
7291
7292 bind(L_copy_1_char_exit);
7293 addptr(result, len); // len is negative count of not processed elements
7294 bind(L_done);
7295 }
7296
7297 /**
7298 * Emits code to update CRC-32 with a byte value according to constants in table
7299 *
7300 * @param [in,out]crc Register containing the crc.
7301 * @param [in]val Register containing the byte to fold into the CRC.
7302 * @param [in]table Register containing the table of crc constants.
7303 *
7304 * uint32_t crc;
7305 * val = crc_table[(val ^ crc) & 0xFF];
7306 * crc = val ^ (crc >> 8);
7307 *
7308 */
7309 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7310 xorl(val, crc);
7311 andl(val, 0xFF);
7312 shrl(crc, 8); // unsigned shift
7313 xorl(crc, Address(table, val, Address::times_4, 0));
7314 }
7315
7316 /**
7317 * Fold 128-bit data chunk
7318 */
7319 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7320 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7321 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7322 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
7323 pxor(xcrc, xtmp);
7324 }
7325
7326 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7327 vpclmulhdq(xtmp, xK, xcrc);
7328 vpclmulldq(xcrc, xK, xcrc);
7329 pxor(xcrc, xbuf);
7330 pxor(xcrc, xtmp);
7331 }
7332
7333 /**
7334 * 8-bit folds to compute 32-bit CRC
7335 *
7336 * uint64_t xcrc;
7337 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7338 */
7339 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7340 movdl(tmp, xcrc);
7341 andl(tmp, 0xFF);
7342 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7343 psrldq(xcrc, 1); // unsigned shift one byte
7344 pxor(xcrc, xtmp);
7345 }
7346
7347 /**
7348 * uint32_t crc;
7349 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7350 */
7351 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7352 movl(tmp, crc);
7353 andl(tmp, 0xFF);
7354 shrl(crc, 8);
7355 xorl(crc, Address(table, tmp, Address::times_4, 0));
7356 }
7357
7358 /**
7359 * @param crc register containing existing CRC (32-bit)
7360 * @param buf register pointing to input byte buffer (byte*)
7361 * @param len register containing number of bytes
7362 * @param table register that will contain address of CRC table
7363 * @param tmp scratch register
7364 */
7365 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7366 assert_different_registers(crc, buf, len, table, tmp, rax);
7367
7368 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7369 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7370
7371 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7372 notl(crc); // ~crc
7373 cmpl(len, 16);
7374 jcc(Assembler::less, L_tail);
7375
7376 // Align buffer to 16 bytes
7377 movl(tmp, buf);
7378 andl(tmp, 0xF);
7379 jccb(Assembler::zero, L_aligned);
7380 subl(tmp, 16);
7381 addl(len, tmp);
7382
7383 align(4);
7384 BIND(L_align_loop);
7385 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7386 update_byte_crc32(crc, rax, table);
7387 increment(buf);
7388 incrementl(tmp);
7389 jccb(Assembler::less, L_align_loop);
7390
7391 BIND(L_aligned);
7392 movl(tmp, len); // save
7393 shrl(len, 4);
7394 jcc(Assembler::zero, L_tail_restore);
7395
7396 // Fold crc into first bytes of vector
7397 movdqa(xmm1, Address(buf, 0));
7398 movdl(rax, xmm1);
7399 xorl(crc, rax);
7400 pinsrd(xmm1, crc, 0);
7401 addptr(buf, 16);
7402 subl(len, 4); // len > 0
7403 jcc(Assembler::less, L_fold_tail);
7404
7405 movdqa(xmm2, Address(buf, 0));
7406 movdqa(xmm3, Address(buf, 16));
7407 movdqa(xmm4, Address(buf, 32));
7408 addptr(buf, 48);
7409 subl(len, 3);
7410 jcc(Assembler::lessEqual, L_fold_512b);
7411
7412 // Fold total 512 bits of polynomial on each iteration,
7413 // 128 bits per each of 4 parallel streams.
7414 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7415
7416 align(32);
7417 BIND(L_fold_512b_loop);
7418 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7419 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7420 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7421 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7422 addptr(buf, 64);
7423 subl(len, 4);
7424 jcc(Assembler::greater, L_fold_512b_loop);
7425
7426 // Fold 512 bits to 128 bits.
7427 BIND(L_fold_512b);
7428 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7429 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7430 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7431 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7432
7433 // Fold the rest of 128 bits data chunks
7434 BIND(L_fold_tail);
7435 addl(len, 3);
7436 jccb(Assembler::lessEqual, L_fold_128b);
7437 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7438
7439 BIND(L_fold_tail_loop);
7440 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7441 addptr(buf, 16);
7442 decrementl(len);
7443 jccb(Assembler::greater, L_fold_tail_loop);
7444
7445 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7446 BIND(L_fold_128b);
7447 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7448 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7449 vpand(xmm3, xmm0, xmm2, false /* vector256 */);
7450 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7451 psrldq(xmm1, 8);
7452 psrldq(xmm2, 4);
7453 pxor(xmm0, xmm1);
7454 pxor(xmm0, xmm2);
7455
7456 // 8 8-bit folds to compute 32-bit CRC.
7457 for (int j = 0; j < 4; j++) {
7458 fold_8bit_crc32(xmm0, table, xmm1, rax);
7459 }
7460 movdl(crc, xmm0); // mov 32 bits to general register
7461 for (int j = 0; j < 4; j++) {
7462 fold_8bit_crc32(crc, table, rax);
7463 }
7464
7465 BIND(L_tail_restore);
7466 movl(len, tmp); // restore
7467 BIND(L_tail);
7468 andl(len, 0xf);
7469 jccb(Assembler::zero, L_exit);
7470
7471 // Fold the rest of bytes
7472 align(4);
7473 BIND(L_tail_loop);
7474 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7475 update_byte_crc32(crc, rax, table);
7476 increment(buf);
7477 decrementl(len);
7478 jccb(Assembler::greater, L_tail_loop);
7479
7480 BIND(L_exit);
7481 notl(crc); // ~c
7482 }
7483
7484 #undef BIND
7485 #undef BLOCK_COMMENT
7486
7487
7488 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
7489 switch (cond) {
7490 // Note some conditions are synonyms for others
7491 case Assembler::zero: return Assembler::notZero;
7492 case Assembler::notZero: return Assembler::zero;
7493 case Assembler::less: return Assembler::greaterEqual;
7494 case Assembler::lessEqual: return Assembler::greater;
7495 case Assembler::greater: return Assembler::lessEqual;
7496 case Assembler::greaterEqual: return Assembler::less;
7497 case Assembler::below: return Assembler::aboveEqual;
7498 case Assembler::belowEqual: return Assembler::above;
7499 case Assembler::above: return Assembler::belowEqual;
7500 case Assembler::aboveEqual: return Assembler::below;
7501 case Assembler::overflow: return Assembler::noOverflow;
7502 case Assembler::noOverflow: return Assembler::overflow;
7503 case Assembler::negative: return Assembler::positive;
7504 case Assembler::positive: return Assembler::negative;
7505 case Assembler::parity: return Assembler::noParity;
7506 case Assembler::noParity: return Assembler::parity;
7507 }
7508 ShouldNotReachHere(); return Assembler::overflow;
7509 }
7510
7511 SkipIfEqual::SkipIfEqual(
7512 MacroAssembler* masm, const bool* flag_addr, bool value) {
7513 _masm = masm;
7514 _masm->cmp8(ExternalAddress((address)flag_addr), value);
7515 _masm->jcc(Assembler::equal, _label);
7516 }
7517
7518 SkipIfEqual::~SkipIfEqual() {
7519 _masm->bind(_label);
7520 }