1 /* 2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #ifndef _WINDOWS 27 #include "alloca.h" 28 #else //WINDOWS 29 #include <intrin.h> 30 #endif 31 #include "asm/macroAssembler.hpp" 32 #include "asm/macroAssembler.inline.hpp" 33 #include "code/debugInfoRec.hpp" 34 #include "code/icBuffer.hpp" 35 #include "code/vtableStubs.hpp" 36 #include "interpreter/interpreter.hpp" 37 #include "oops/compiledICHolder.hpp" 38 #include "prims/jvmtiRedefineClassesTrace.hpp" 39 #include "runtime/sharedRuntime.hpp" 40 #include "runtime/vframeArray.hpp" 41 #include "vmreg_x86.inline.hpp" 42 #ifdef COMPILER1 43 #include "c1/c1_Runtime1.hpp" 44 #endif 45 #ifdef COMPILER2 46 #include "opto/runtime.hpp" 47 #endif 48 49 #define __ masm-> 50 51 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; 52 53 class SimpleRuntimeFrame { 54 55 public: 56 57 // Most of the runtime stubs have this simple frame layout. 58 // This class exists to make the layout shared in one place. 59 // Offsets are for compiler stack slots, which are jints. 60 enum layout { 61 // The frame sender code expects that rbp will be in the "natural" place and 62 // will override any oopMap setting for it. We must therefore force the layout 63 // so that it agrees with the frame sender code. 64 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt, 65 rbp_off2, 66 return_off, return_off2, 67 framesize 68 }; 69 }; 70 71 class RegisterSaver { 72 // Capture info about frame layout. Layout offsets are in jint 73 // units because compiler frame slots are jints. 74 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off 75 enum layout { 76 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area 77 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area 78 DEF_XMM_OFFS(0), 79 DEF_XMM_OFFS(1), 80 DEF_XMM_OFFS(2), 81 DEF_XMM_OFFS(3), 82 DEF_XMM_OFFS(4), 83 DEF_XMM_OFFS(5), 84 DEF_XMM_OFFS(6), 85 DEF_XMM_OFFS(7), 86 DEF_XMM_OFFS(8), 87 DEF_XMM_OFFS(9), 88 DEF_XMM_OFFS(10), 89 DEF_XMM_OFFS(11), 90 DEF_XMM_OFFS(12), 91 DEF_XMM_OFFS(13), 92 DEF_XMM_OFFS(14), 93 DEF_XMM_OFFS(15), 94 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt), 95 fpu_stateH_end, 96 r15_off, r15H_off, 97 r14_off, r14H_off, 98 r13_off, r13H_off, 99 r12_off, r12H_off, 100 r11_off, r11H_off, 101 r10_off, r10H_off, 102 r9_off, r9H_off, 103 r8_off, r8H_off, 104 rdi_off, rdiH_off, 105 rsi_off, rsiH_off, 106 ignore_off, ignoreH_off, // extra copy of rbp 107 rsp_off, rspH_off, 108 rbx_off, rbxH_off, 109 rdx_off, rdxH_off, 110 rcx_off, rcxH_off, 111 rax_off, raxH_off, 112 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state 113 align_off, alignH_off, 114 flags_off, flagsH_off, 115 // The frame sender code expects that rbp will be in the "natural" place and 116 // will override any oopMap setting for it. We must therefore force the layout 117 // so that it agrees with the frame sender code. 118 rbp_off, rbpH_off, // copy of rbp we will restore 119 return_off, returnH_off, // slot for return address 120 reg_save_size // size in compiler stack slots 121 }; 122 123 public: 124 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false); 125 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false); 126 127 // Offsets into the register save area 128 // Used by deoptimization when it is managing result register 129 // values on its own 130 131 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; } 132 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; } 133 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; } 134 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; } 135 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; } 136 137 // During deoptimization only the result registers need to be restored, 138 // all the other values have already been extracted. 139 static void restore_result_registers(MacroAssembler* masm); 140 }; 141 142 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { 143 int vect_words = 0; 144 #ifdef COMPILER2 145 if (save_vectors) { 146 assert(UseAVX > 0, "256bit vectors are supported only with AVX"); 147 assert(MaxVectorSize == 32, "only 256bit vectors are supported now"); 148 // Save upper half of YMM registes 149 vect_words = 16 * 16 / wordSize; 150 additional_frame_words += vect_words; 151 } 152 #else 153 assert(!save_vectors, "vectors are generated only by C2"); 154 #endif 155 156 // Always make the frame size 16-byte aligned 157 int frame_size_in_bytes = round_to(additional_frame_words*wordSize + 158 reg_save_size*BytesPerInt, 16); 159 // OopMap frame size is in compiler stack slots (jint's) not bytes or words 160 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; 161 // The caller will allocate additional_frame_words 162 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; 163 // CodeBlob frame size is in words. 164 int frame_size_in_words = frame_size_in_bytes / wordSize; 165 *total_frame_words = frame_size_in_words; 166 167 // Save registers, fpu state, and flags. 168 // We assume caller has already pushed the return address onto the 169 // stack, so rsp is 8-byte aligned here. 170 // We push rpb twice in this sequence because we want the real rbp 171 // to be under the return like a normal enter. 172 173 __ enter(); // rsp becomes 16-byte aligned here 174 __ push_CPU_state(); // Push a multiple of 16 bytes 175 176 if (vect_words > 0) { 177 assert(vect_words*wordSize == 256, ""); 178 __ subptr(rsp, 256); // Save upper half of YMM registes 179 __ vextractf128h(Address(rsp, 0),xmm0); 180 __ vextractf128h(Address(rsp, 16),xmm1); 181 __ vextractf128h(Address(rsp, 32),xmm2); 182 __ vextractf128h(Address(rsp, 48),xmm3); 183 __ vextractf128h(Address(rsp, 64),xmm4); 184 __ vextractf128h(Address(rsp, 80),xmm5); 185 __ vextractf128h(Address(rsp, 96),xmm6); 186 __ vextractf128h(Address(rsp,112),xmm7); 187 __ vextractf128h(Address(rsp,128),xmm8); 188 __ vextractf128h(Address(rsp,144),xmm9); 189 __ vextractf128h(Address(rsp,160),xmm10); 190 __ vextractf128h(Address(rsp,176),xmm11); 191 __ vextractf128h(Address(rsp,192),xmm12); 192 __ vextractf128h(Address(rsp,208),xmm13); 193 __ vextractf128h(Address(rsp,224),xmm14); 194 __ vextractf128h(Address(rsp,240),xmm15); 195 } 196 if (frame::arg_reg_save_area_bytes != 0) { 197 // Allocate argument register save area 198 __ subptr(rsp, frame::arg_reg_save_area_bytes); 199 } 200 201 // Set an oopmap for the call site. This oopmap will map all 202 // oop-registers and debug-info registers as callee-saved. This 203 // will allow deoptimization at this safepoint to find all possible 204 // debug-info recordings, as well as let GC find all oops. 205 206 OopMapSet *oop_maps = new OopMapSet(); 207 OopMap* map = new OopMap(frame_size_in_slots, 0); 208 209 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_slots) 210 211 map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg()); 212 map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg()); 213 map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg()); 214 map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg()); 215 // rbp location is known implicitly by the frame sender code, needs no oopmap 216 // and the location where rbp was saved by is ignored 217 map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg()); 218 map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg()); 219 map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg()); 220 map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg()); 221 map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg()); 222 map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg()); 223 map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg()); 224 map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg()); 225 map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg()); 226 map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg()); 227 map->set_callee_saved(STACK_OFFSET(xmm0_off ), xmm0->as_VMReg()); 228 map->set_callee_saved(STACK_OFFSET(xmm1_off ), xmm1->as_VMReg()); 229 map->set_callee_saved(STACK_OFFSET(xmm2_off ), xmm2->as_VMReg()); 230 map->set_callee_saved(STACK_OFFSET(xmm3_off ), xmm3->as_VMReg()); 231 map->set_callee_saved(STACK_OFFSET(xmm4_off ), xmm4->as_VMReg()); 232 map->set_callee_saved(STACK_OFFSET(xmm5_off ), xmm5->as_VMReg()); 233 map->set_callee_saved(STACK_OFFSET(xmm6_off ), xmm6->as_VMReg()); 234 map->set_callee_saved(STACK_OFFSET(xmm7_off ), xmm7->as_VMReg()); 235 map->set_callee_saved(STACK_OFFSET(xmm8_off ), xmm8->as_VMReg()); 236 map->set_callee_saved(STACK_OFFSET(xmm9_off ), xmm9->as_VMReg()); 237 map->set_callee_saved(STACK_OFFSET(xmm10_off), xmm10->as_VMReg()); 238 map->set_callee_saved(STACK_OFFSET(xmm11_off), xmm11->as_VMReg()); 239 map->set_callee_saved(STACK_OFFSET(xmm12_off), xmm12->as_VMReg()); 240 map->set_callee_saved(STACK_OFFSET(xmm13_off), xmm13->as_VMReg()); 241 map->set_callee_saved(STACK_OFFSET(xmm14_off), xmm14->as_VMReg()); 242 map->set_callee_saved(STACK_OFFSET(xmm15_off), xmm15->as_VMReg()); 243 244 // %%% These should all be a waste but we'll keep things as they were for now 245 if (true) { 246 map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next()); 247 map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next()); 248 map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next()); 249 map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next()); 250 // rbp location is known implicitly by the frame sender code, needs no oopmap 251 map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next()); 252 map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next()); 253 map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next()); 254 map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next()); 255 map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next()); 256 map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next()); 257 map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next()); 258 map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next()); 259 map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next()); 260 map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next()); 261 map->set_callee_saved(STACK_OFFSET(xmm0H_off ), xmm0->as_VMReg()->next()); 262 map->set_callee_saved(STACK_OFFSET(xmm1H_off ), xmm1->as_VMReg()->next()); 263 map->set_callee_saved(STACK_OFFSET(xmm2H_off ), xmm2->as_VMReg()->next()); 264 map->set_callee_saved(STACK_OFFSET(xmm3H_off ), xmm3->as_VMReg()->next()); 265 map->set_callee_saved(STACK_OFFSET(xmm4H_off ), xmm4->as_VMReg()->next()); 266 map->set_callee_saved(STACK_OFFSET(xmm5H_off ), xmm5->as_VMReg()->next()); 267 map->set_callee_saved(STACK_OFFSET(xmm6H_off ), xmm6->as_VMReg()->next()); 268 map->set_callee_saved(STACK_OFFSET(xmm7H_off ), xmm7->as_VMReg()->next()); 269 map->set_callee_saved(STACK_OFFSET(xmm8H_off ), xmm8->as_VMReg()->next()); 270 map->set_callee_saved(STACK_OFFSET(xmm9H_off ), xmm9->as_VMReg()->next()); 271 map->set_callee_saved(STACK_OFFSET(xmm10H_off), xmm10->as_VMReg()->next()); 272 map->set_callee_saved(STACK_OFFSET(xmm11H_off), xmm11->as_VMReg()->next()); 273 map->set_callee_saved(STACK_OFFSET(xmm12H_off), xmm12->as_VMReg()->next()); 274 map->set_callee_saved(STACK_OFFSET(xmm13H_off), xmm13->as_VMReg()->next()); 275 map->set_callee_saved(STACK_OFFSET(xmm14H_off), xmm14->as_VMReg()->next()); 276 map->set_callee_saved(STACK_OFFSET(xmm15H_off), xmm15->as_VMReg()->next()); 277 } 278 279 return map; 280 } 281 282 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { 283 if (frame::arg_reg_save_area_bytes != 0) { 284 // Pop arg register save area 285 __ addptr(rsp, frame::arg_reg_save_area_bytes); 286 } 287 #ifdef COMPILER2 288 if (restore_vectors) { 289 // Restore upper half of YMM registes. 290 assert(UseAVX > 0, "256bit vectors are supported only with AVX"); 291 assert(MaxVectorSize == 32, "only 256bit vectors are supported now"); 292 __ vinsertf128h(xmm0, Address(rsp, 0)); 293 __ vinsertf128h(xmm1, Address(rsp, 16)); 294 __ vinsertf128h(xmm2, Address(rsp, 32)); 295 __ vinsertf128h(xmm3, Address(rsp, 48)); 296 __ vinsertf128h(xmm4, Address(rsp, 64)); 297 __ vinsertf128h(xmm5, Address(rsp, 80)); 298 __ vinsertf128h(xmm6, Address(rsp, 96)); 299 __ vinsertf128h(xmm7, Address(rsp,112)); 300 __ vinsertf128h(xmm8, Address(rsp,128)); 301 __ vinsertf128h(xmm9, Address(rsp,144)); 302 __ vinsertf128h(xmm10, Address(rsp,160)); 303 __ vinsertf128h(xmm11, Address(rsp,176)); 304 __ vinsertf128h(xmm12, Address(rsp,192)); 305 __ vinsertf128h(xmm13, Address(rsp,208)); 306 __ vinsertf128h(xmm14, Address(rsp,224)); 307 __ vinsertf128h(xmm15, Address(rsp,240)); 308 __ addptr(rsp, 256); 309 } 310 #else 311 assert(!restore_vectors, "vectors are generated only by C2"); 312 #endif 313 // Recover CPU state 314 __ pop_CPU_state(); 315 // Get the rbp described implicitly by the calling convention (no oopMap) 316 __ pop(rbp); 317 } 318 319 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { 320 321 // Just restore result register. Only used by deoptimization. By 322 // now any callee save register that needs to be restored to a c2 323 // caller of the deoptee has been extracted into the vframeArray 324 // and will be stuffed into the c2i adapter we create for later 325 // restoration so only result registers need to be restored here. 326 327 // Restore fp result register 328 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes())); 329 // Restore integer result register 330 __ movptr(rax, Address(rsp, rax_offset_in_bytes())); 331 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes())); 332 333 // Pop all of the register save are off the stack except the return address 334 __ addptr(rsp, return_offset_in_bytes()); 335 } 336 337 // Is vector's size (in bytes) bigger than a size saved by default? 338 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. 339 bool SharedRuntime::is_wide_vector(int size) { 340 return size > 16; 341 } 342 343 // The java_calling_convention describes stack locations as ideal slots on 344 // a frame with no abi restrictions. Since we must observe abi restrictions 345 // (like the placement of the register window) the slots must be biased by 346 // the following value. 347 static int reg2offset_in(VMReg r) { 348 // Account for saved rbp and return address 349 // This should really be in_preserve_stack_slots 350 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; 351 } 352 353 static int reg2offset_out(VMReg r) { 354 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 355 } 356 357 // --------------------------------------------------------------------------- 358 // Read the array of BasicTypes from a signature, and compute where the 359 // arguments should go. Values in the VMRegPair regs array refer to 4-byte 360 // quantities. Values less than VMRegImpl::stack0 are registers, those above 361 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer 362 // as framesizes are fixed. 363 // VMRegImpl::stack0 refers to the first slot 0(sp). 364 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register 365 // up to RegisterImpl::number_of_registers) are the 64-bit 366 // integer registers. 367 368 // Note: the INPUTS in sig_bt are in units of Java argument words, which are 369 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit 370 // units regardless of build. Of course for i486 there is no 64 bit build 371 372 // The Java calling convention is a "shifted" version of the C ABI. 373 // By skipping the first C ABI register we can call non-static jni methods 374 // with small numbers of arguments without having to shuffle the arguments 375 // at all. Since we control the java ABI we ought to at least get some 376 // advantage out of it. 377 378 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, 379 VMRegPair *regs, 380 int total_args_passed, 381 int is_outgoing) { 382 383 // Create the mapping between argument positions and 384 // registers. 385 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = { 386 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5 387 }; 388 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = { 389 j_farg0, j_farg1, j_farg2, j_farg3, 390 j_farg4, j_farg5, j_farg6, j_farg7 391 }; 392 393 394 uint int_args = 0; 395 uint fp_args = 0; 396 uint stk_args = 0; // inc by 2 each time 397 398 for (int i = 0; i < total_args_passed; i++) { 399 switch (sig_bt[i]) { 400 case T_BOOLEAN: 401 case T_CHAR: 402 case T_BYTE: 403 case T_SHORT: 404 case T_INT: 405 if (int_args < Argument::n_int_register_parameters_j) { 406 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); 407 } else { 408 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 409 stk_args += 2; 410 } 411 break; 412 case T_VOID: 413 // halves of T_LONG or T_DOUBLE 414 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); 415 regs[i].set_bad(); 416 break; 417 case T_LONG: 418 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 419 // fall through 420 case T_OBJECT: 421 case T_ARRAY: 422 case T_ADDRESS: 423 if (int_args < Argument::n_int_register_parameters_j) { 424 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); 425 } else { 426 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 427 stk_args += 2; 428 } 429 break; 430 case T_FLOAT: 431 if (fp_args < Argument::n_float_register_parameters_j) { 432 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); 433 } else { 434 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 435 stk_args += 2; 436 } 437 break; 438 case T_DOUBLE: 439 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 440 if (fp_args < Argument::n_float_register_parameters_j) { 441 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); 442 } else { 443 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 444 stk_args += 2; 445 } 446 break; 447 default: 448 ShouldNotReachHere(); 449 break; 450 } 451 } 452 453 return round_to(stk_args, 2); 454 } 455 456 // Patch the callers callsite with entry to compiled code if it exists. 457 static void patch_callers_callsite(MacroAssembler *masm) { 458 Label L; 459 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); 460 __ jcc(Assembler::equal, L); 461 462 // Save the current stack pointer 463 __ mov(r13, rsp); 464 // Schedule the branch target address early. 465 // Call into the VM to patch the caller, then jump to compiled callee 466 // rax isn't live so capture return address while we easily can 467 __ movptr(rax, Address(rsp, 0)); 468 469 // align stack so push_CPU_state doesn't fault 470 __ andptr(rsp, -(StackAlignmentInBytes)); 471 __ push_CPU_state(); 472 473 // VM needs caller's callsite 474 // VM needs target method 475 // This needs to be a long call since we will relocate this adapter to 476 // the codeBuffer and it may not reach 477 478 // Allocate argument register save area 479 if (frame::arg_reg_save_area_bytes != 0) { 480 __ subptr(rsp, frame::arg_reg_save_area_bytes); 481 } 482 __ mov(c_rarg0, rbx); 483 __ mov(c_rarg1, rax); 484 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); 485 486 // De-allocate argument register save area 487 if (frame::arg_reg_save_area_bytes != 0) { 488 __ addptr(rsp, frame::arg_reg_save_area_bytes); 489 } 490 491 __ pop_CPU_state(); 492 // restore sp 493 __ mov(rsp, r13); 494 __ bind(L); 495 } 496 497 498 static void gen_c2i_adapter(MacroAssembler *masm, 499 int total_args_passed, 500 int comp_args_on_stack, 501 const BasicType *sig_bt, 502 const VMRegPair *regs, 503 Label& skip_fixup) { 504 // Before we get into the guts of the C2I adapter, see if we should be here 505 // at all. We've come from compiled code and are attempting to jump to the 506 // interpreter, which means the caller made a static call to get here 507 // (vcalls always get a compiled target if there is one). Check for a 508 // compiled target. If there is one, we need to patch the caller's call. 509 patch_callers_callsite(masm); 510 511 __ bind(skip_fixup); 512 513 // Since all args are passed on the stack, total_args_passed * 514 // Interpreter::stackElementSize is the space we need. Plus 1 because 515 // we also account for the return address location since 516 // we store it first rather than hold it in rax across all the shuffling 517 518 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize; 519 520 // stack is aligned, keep it that way 521 extraspace = round_to(extraspace, 2*wordSize); 522 523 // Get return address 524 __ pop(rax); 525 526 // set senderSP value 527 __ mov(r13, rsp); 528 529 __ subptr(rsp, extraspace); 530 531 // Store the return address in the expected location 532 __ movptr(Address(rsp, 0), rax); 533 534 // Now write the args into the outgoing interpreter space 535 for (int i = 0; i < total_args_passed; i++) { 536 if (sig_bt[i] == T_VOID) { 537 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 538 continue; 539 } 540 541 // offset to start parameters 542 int st_off = (total_args_passed - i) * Interpreter::stackElementSize; 543 int next_off = st_off - Interpreter::stackElementSize; 544 545 // Say 4 args: 546 // i st_off 547 // 0 32 T_LONG 548 // 1 24 T_VOID 549 // 2 16 T_OBJECT 550 // 3 8 T_BOOL 551 // - 0 return address 552 // 553 // However to make thing extra confusing. Because we can fit a long/double in 554 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter 555 // leaves one slot empty and only stores to a single slot. In this case the 556 // slot that is occupied is the T_VOID slot. See I said it was confusing. 557 558 VMReg r_1 = regs[i].first(); 559 VMReg r_2 = regs[i].second(); 560 if (!r_1->is_valid()) { 561 assert(!r_2->is_valid(), ""); 562 continue; 563 } 564 if (r_1->is_stack()) { 565 // memory to memory use rax 566 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace; 567 if (!r_2->is_valid()) { 568 // sign extend?? 569 __ movl(rax, Address(rsp, ld_off)); 570 __ movptr(Address(rsp, st_off), rax); 571 572 } else { 573 574 __ movq(rax, Address(rsp, ld_off)); 575 576 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG 577 // T_DOUBLE and T_LONG use two slots in the interpreter 578 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { 579 // ld_off == LSW, ld_off+wordSize == MSW 580 // st_off == MSW, next_off == LSW 581 __ movq(Address(rsp, next_off), rax); 582 #ifdef ASSERT 583 // Overwrite the unused slot with known junk 584 __ mov64(rax, CONST64(0xdeadffffdeadaaaa)); 585 __ movptr(Address(rsp, st_off), rax); 586 #endif /* ASSERT */ 587 } else { 588 __ movq(Address(rsp, st_off), rax); 589 } 590 } 591 } else if (r_1->is_Register()) { 592 Register r = r_1->as_Register(); 593 if (!r_2->is_valid()) { 594 // must be only an int (or less ) so move only 32bits to slot 595 // why not sign extend?? 596 __ movl(Address(rsp, st_off), r); 597 } else { 598 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG 599 // T_DOUBLE and T_LONG use two slots in the interpreter 600 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { 601 // long/double in gpr 602 #ifdef ASSERT 603 // Overwrite the unused slot with known junk 604 __ mov64(rax, CONST64(0xdeadffffdeadaaab)); 605 __ movptr(Address(rsp, st_off), rax); 606 #endif /* ASSERT */ 607 __ movq(Address(rsp, next_off), r); 608 } else { 609 __ movptr(Address(rsp, st_off), r); 610 } 611 } 612 } else { 613 assert(r_1->is_XMMRegister(), ""); 614 if (!r_2->is_valid()) { 615 // only a float use just part of the slot 616 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister()); 617 } else { 618 #ifdef ASSERT 619 // Overwrite the unused slot with known junk 620 __ mov64(rax, CONST64(0xdeadffffdeadaaac)); 621 __ movptr(Address(rsp, st_off), rax); 622 #endif /* ASSERT */ 623 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister()); 624 } 625 } 626 } 627 628 // Schedule the branch target address early. 629 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset()))); 630 __ jmp(rcx); 631 } 632 633 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, 634 address code_start, address code_end, 635 Label& L_ok) { 636 Label L_fail; 637 __ lea(temp_reg, ExternalAddress(code_start)); 638 __ cmpptr(pc_reg, temp_reg); 639 __ jcc(Assembler::belowEqual, L_fail); 640 __ lea(temp_reg, ExternalAddress(code_end)); 641 __ cmpptr(pc_reg, temp_reg); 642 __ jcc(Assembler::below, L_ok); 643 __ bind(L_fail); 644 } 645 646 static void gen_i2c_adapter(MacroAssembler *masm, 647 int total_args_passed, 648 int comp_args_on_stack, 649 const BasicType *sig_bt, 650 const VMRegPair *regs) { 651 652 // Note: r13 contains the senderSP on entry. We must preserve it since 653 // we may do a i2c -> c2i transition if we lose a race where compiled 654 // code goes non-entrant while we get args ready. 655 // In addition we use r13 to locate all the interpreter args as 656 // we must align the stack to 16 bytes on an i2c entry else we 657 // lose alignment we expect in all compiled code and register 658 // save code can segv when fxsave instructions find improperly 659 // aligned stack pointer. 660 661 // Adapters can be frameless because they do not require the caller 662 // to perform additional cleanup work, such as correcting the stack pointer. 663 // An i2c adapter is frameless because the *caller* frame, which is interpreted, 664 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), 665 // even if a callee has modified the stack pointer. 666 // A c2i adapter is frameless because the *callee* frame, which is interpreted, 667 // routinely repairs its caller's stack pointer (from sender_sp, which is set 668 // up via the senderSP register). 669 // In other words, if *either* the caller or callee is interpreted, we can 670 // get the stack pointer repaired after a call. 671 // This is why c2i and i2c adapters cannot be indefinitely composed. 672 // In particular, if a c2i adapter were to somehow call an i2c adapter, 673 // both caller and callee would be compiled methods, and neither would 674 // clean up the stack pointer changes performed by the two adapters. 675 // If this happens, control eventually transfers back to the compiled 676 // caller, but with an uncorrected stack, causing delayed havoc. 677 678 // Pick up the return address 679 __ movptr(rax, Address(rsp, 0)); 680 681 if (VerifyAdapterCalls && 682 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { 683 // So, let's test for cascading c2i/i2c adapters right now. 684 // assert(Interpreter::contains($return_addr) || 685 // StubRoutines::contains($return_addr), 686 // "i2c adapter must return to an interpreter frame"); 687 __ block_comment("verify_i2c { "); 688 Label L_ok; 689 if (Interpreter::code() != NULL) 690 range_check(masm, rax, r11, 691 Interpreter::code()->code_start(), Interpreter::code()->code_end(), 692 L_ok); 693 if (StubRoutines::code1() != NULL) 694 range_check(masm, rax, r11, 695 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), 696 L_ok); 697 if (StubRoutines::code2() != NULL) 698 range_check(masm, rax, r11, 699 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), 700 L_ok); 701 const char* msg = "i2c adapter must return to an interpreter frame"; 702 __ block_comment(msg); 703 __ stop(msg); 704 __ bind(L_ok); 705 __ block_comment("} verify_i2ce "); 706 } 707 708 // Must preserve original SP for loading incoming arguments because 709 // we need to align the outgoing SP for compiled code. 710 __ movptr(r11, rsp); 711 712 // Cut-out for having no stack args. Since up to 2 int/oop args are passed 713 // in registers, we will occasionally have no stack args. 714 int comp_words_on_stack = 0; 715 if (comp_args_on_stack) { 716 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in 717 // registers are below. By subtracting stack0, we either get a negative 718 // number (all values in registers) or the maximum stack slot accessed. 719 720 // Convert 4-byte c2 stack slots to words. 721 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; 722 // Round up to miminum stack alignment, in wordSize 723 comp_words_on_stack = round_to(comp_words_on_stack, 2); 724 __ subptr(rsp, comp_words_on_stack * wordSize); 725 } 726 727 728 // Ensure compiled code always sees stack at proper alignment 729 __ andptr(rsp, -16); 730 731 // push the return address and misalign the stack that youngest frame always sees 732 // as far as the placement of the call instruction 733 __ push(rax); 734 735 // Put saved SP in another register 736 const Register saved_sp = rax; 737 __ movptr(saved_sp, r11); 738 739 // Will jump to the compiled code just as if compiled code was doing it. 740 // Pre-load the register-jump target early, to schedule it better. 741 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset()))); 742 743 // Now generate the shuffle code. Pick up all register args and move the 744 // rest through the floating point stack top. 745 for (int i = 0; i < total_args_passed; i++) { 746 if (sig_bt[i] == T_VOID) { 747 // Longs and doubles are passed in native word order, but misaligned 748 // in the 32-bit build. 749 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 750 continue; 751 } 752 753 // Pick up 0, 1 or 2 words from SP+offset. 754 755 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), 756 "scrambled load targets?"); 757 // Load in argument order going down. 758 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize; 759 // Point to interpreter value (vs. tag) 760 int next_off = ld_off - Interpreter::stackElementSize; 761 // 762 // 763 // 764 VMReg r_1 = regs[i].first(); 765 VMReg r_2 = regs[i].second(); 766 if (!r_1->is_valid()) { 767 assert(!r_2->is_valid(), ""); 768 continue; 769 } 770 if (r_1->is_stack()) { 771 // Convert stack slot to an SP offset (+ wordSize to account for return address ) 772 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize; 773 774 // We can use r13 as a temp here because compiled code doesn't need r13 as an input 775 // and if we end up going thru a c2i because of a miss a reasonable value of r13 776 // will be generated. 777 if (!r_2->is_valid()) { 778 // sign extend??? 779 __ movl(r13, Address(saved_sp, ld_off)); 780 __ movptr(Address(rsp, st_off), r13); 781 } else { 782 // 783 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE 784 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case 785 // So we must adjust where to pick up the data to match the interpreter. 786 // 787 // Interpreter local[n] == MSW, local[n+1] == LSW however locals 788 // are accessed as negative so LSW is at LOW address 789 790 // ld_off is MSW so get LSW 791 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? 792 next_off : ld_off; 793 __ movq(r13, Address(saved_sp, offset)); 794 // st_off is LSW (i.e. reg.first()) 795 __ movq(Address(rsp, st_off), r13); 796 } 797 } else if (r_1->is_Register()) { // Register argument 798 Register r = r_1->as_Register(); 799 assert(r != rax, "must be different"); 800 if (r_2->is_valid()) { 801 // 802 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE 803 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case 804 // So we must adjust where to pick up the data to match the interpreter. 805 806 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? 807 next_off : ld_off; 808 809 // this can be a misaligned move 810 __ movq(r, Address(saved_sp, offset)); 811 } else { 812 // sign extend and use a full word? 813 __ movl(r, Address(saved_sp, ld_off)); 814 } 815 } else { 816 if (!r_2->is_valid()) { 817 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off)); 818 } else { 819 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off)); 820 } 821 } 822 } 823 824 // 6243940 We might end up in handle_wrong_method if 825 // the callee is deoptimized as we race thru here. If that 826 // happens we don't want to take a safepoint because the 827 // caller frame will look interpreted and arguments are now 828 // "compiled" so it is much better to make this transition 829 // invisible to the stack walking code. Unfortunately if 830 // we try and find the callee by normal means a safepoint 831 // is possible. So we stash the desired callee in the thread 832 // and the vm will find there should this case occur. 833 834 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx); 835 836 // put Method* where a c2i would expect should we end up there 837 // only needed becaus eof c2 resolve stubs return Method* as a result in 838 // rax 839 __ mov(rax, rbx); 840 __ jmp(r11); 841 } 842 843 // --------------------------------------------------------------- 844 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, 845 int total_args_passed, 846 int comp_args_on_stack, 847 const BasicType *sig_bt, 848 const VMRegPair *regs, 849 AdapterFingerPrint* fingerprint) { 850 address i2c_entry = __ pc(); 851 852 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); 853 854 // ------------------------------------------------------------------------- 855 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls 856 // to the interpreter. The args start out packed in the compiled layout. They 857 // need to be unpacked into the interpreter layout. This will almost always 858 // require some stack space. We grow the current (compiled) stack, then repack 859 // the args. We finally end in a jump to the generic interpreter entry point. 860 // On exit from the interpreter, the interpreter will restore our SP (lest the 861 // compiled code, which relys solely on SP and not RBP, get sick). 862 863 address c2i_unverified_entry = __ pc(); 864 Label skip_fixup; 865 Label ok; 866 867 Register holder = rax; 868 Register receiver = j_rarg0; 869 Register temp = rbx; 870 871 { 872 __ load_klass(temp, receiver); 873 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset())); 874 __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset())); 875 __ jcc(Assembler::equal, ok); 876 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 877 878 __ bind(ok); 879 // Method might have been compiled since the call site was patched to 880 // interpreted if that is the case treat it as a miss so we can get 881 // the call site corrected. 882 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); 883 __ jcc(Assembler::equal, skip_fixup); 884 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 885 } 886 887 address c2i_entry = __ pc(); 888 889 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); 890 891 __ flush(); 892 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); 893 } 894 895 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, 896 VMRegPair *regs, 897 VMRegPair *regs2, 898 int total_args_passed) { 899 assert(regs2 == NULL, "not needed on x86"); 900 // We return the amount of VMRegImpl stack slots we need to reserve for all 901 // the arguments NOT counting out_preserve_stack_slots. 902 903 // NOTE: These arrays will have to change when c1 is ported 904 #ifdef _WIN64 905 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { 906 c_rarg0, c_rarg1, c_rarg2, c_rarg3 907 }; 908 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { 909 c_farg0, c_farg1, c_farg2, c_farg3 910 }; 911 #else 912 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { 913 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5 914 }; 915 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { 916 c_farg0, c_farg1, c_farg2, c_farg3, 917 c_farg4, c_farg5, c_farg6, c_farg7 918 }; 919 #endif // _WIN64 920 921 922 uint int_args = 0; 923 uint fp_args = 0; 924 uint stk_args = 0; // inc by 2 each time 925 926 for (int i = 0; i < total_args_passed; i++) { 927 switch (sig_bt[i]) { 928 case T_BOOLEAN: 929 case T_CHAR: 930 case T_BYTE: 931 case T_SHORT: 932 case T_INT: 933 if (int_args < Argument::n_int_register_parameters_c) { 934 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); 935 #ifdef _WIN64 936 fp_args++; 937 // Allocate slots for callee to stuff register args the stack. 938 stk_args += 2; 939 #endif 940 } else { 941 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 942 stk_args += 2; 943 } 944 break; 945 case T_LONG: 946 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 947 // fall through 948 case T_OBJECT: 949 case T_ARRAY: 950 case T_ADDRESS: 951 case T_METADATA: 952 if (int_args < Argument::n_int_register_parameters_c) { 953 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); 954 #ifdef _WIN64 955 fp_args++; 956 stk_args += 2; 957 #endif 958 } else { 959 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 960 stk_args += 2; 961 } 962 break; 963 case T_FLOAT: 964 if (fp_args < Argument::n_float_register_parameters_c) { 965 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); 966 #ifdef _WIN64 967 int_args++; 968 // Allocate slots for callee to stuff register args the stack. 969 stk_args += 2; 970 #endif 971 } else { 972 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 973 stk_args += 2; 974 } 975 break; 976 case T_DOUBLE: 977 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 978 if (fp_args < Argument::n_float_register_parameters_c) { 979 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); 980 #ifdef _WIN64 981 int_args++; 982 // Allocate slots for callee to stuff register args the stack. 983 stk_args += 2; 984 #endif 985 } else { 986 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 987 stk_args += 2; 988 } 989 break; 990 case T_VOID: // Halves of longs and doubles 991 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); 992 regs[i].set_bad(); 993 break; 994 default: 995 ShouldNotReachHere(); 996 break; 997 } 998 } 999 #ifdef _WIN64 1000 // windows abi requires that we always allocate enough stack space 1001 // for 4 64bit registers to be stored down. 1002 if (stk_args < 8) { 1003 stk_args = 8; 1004 } 1005 #endif // _WIN64 1006 1007 return stk_args; 1008 } 1009 1010 // On 64 bit we will store integer like items to the stack as 1011 // 64 bits items (sparc abi) even though java would only store 1012 // 32bits for a parameter. On 32bit it will simply be 32 bits 1013 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 1014 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1015 if (src.first()->is_stack()) { 1016 if (dst.first()->is_stack()) { 1017 // stack to stack 1018 __ movslq(rax, Address(rbp, reg2offset_in(src.first()))); 1019 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1020 } else { 1021 // stack to reg 1022 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1023 } 1024 } else if (dst.first()->is_stack()) { 1025 // reg to stack 1026 // Do we really have to sign extend??? 1027 // __ movslq(src.first()->as_Register(), src.first()->as_Register()); 1028 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1029 } else { 1030 // Do we really have to sign extend??? 1031 // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); 1032 if (dst.first() != src.first()) { 1033 __ movq(dst.first()->as_Register(), src.first()->as_Register()); 1034 } 1035 } 1036 } 1037 1038 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1039 if (src.first()->is_stack()) { 1040 if (dst.first()->is_stack()) { 1041 // stack to stack 1042 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 1043 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1044 } else { 1045 // stack to reg 1046 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1047 } 1048 } else if (dst.first()->is_stack()) { 1049 // reg to stack 1050 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1051 } else { 1052 if (dst.first() != src.first()) { 1053 __ movq(dst.first()->as_Register(), src.first()->as_Register()); 1054 } 1055 } 1056 } 1057 1058 // An oop arg. Must pass a handle not the oop itself 1059 static void object_move(MacroAssembler* masm, 1060 OopMap* map, 1061 int oop_handle_offset, 1062 int framesize_in_slots, 1063 VMRegPair src, 1064 VMRegPair dst, 1065 bool is_receiver, 1066 int* receiver_offset) { 1067 1068 // must pass a handle. First figure out the location we use as a handle 1069 1070 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); 1071 1072 // See if oop is NULL if it is we need no handle 1073 1074 if (src.first()->is_stack()) { 1075 1076 // Oop is already on the stack as an argument 1077 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1078 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 1079 if (is_receiver) { 1080 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 1081 } 1082 1083 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD); 1084 __ lea(rHandle, Address(rbp, reg2offset_in(src.first()))); 1085 // conditionally move a NULL 1086 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); 1087 } else { 1088 1089 // Oop is in an a register we must store it to the space we reserve 1090 // on the stack for oop_handles and pass a handle if oop is non-NULL 1091 1092 const Register rOop = src.first()->as_Register(); 1093 int oop_slot; 1094 if (rOop == j_rarg0) 1095 oop_slot = 0; 1096 else if (rOop == j_rarg1) 1097 oop_slot = 1; 1098 else if (rOop == j_rarg2) 1099 oop_slot = 2; 1100 else if (rOop == j_rarg3) 1101 oop_slot = 3; 1102 else if (rOop == j_rarg4) 1103 oop_slot = 4; 1104 else { 1105 assert(rOop == j_rarg5, "wrong register"); 1106 oop_slot = 5; 1107 } 1108 1109 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; 1110 int offset = oop_slot*VMRegImpl::stack_slot_size; 1111 1112 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 1113 // Store oop in handle area, may be NULL 1114 __ movptr(Address(rsp, offset), rOop); 1115 if (is_receiver) { 1116 *receiver_offset = offset; 1117 } 1118 1119 __ cmpptr(rOop, (int32_t)NULL_WORD); 1120 __ lea(rHandle, Address(rsp, offset)); 1121 // conditionally move a NULL from the handle area where it was just stored 1122 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); 1123 } 1124 1125 // If arg is on the stack then place it otherwise it is already in correct reg. 1126 if (dst.first()->is_stack()) { 1127 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); 1128 } 1129 } 1130 1131 // A float arg may have to do float reg int reg conversion 1132 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1133 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 1134 1135 // The calling conventions assures us that each VMregpair is either 1136 // all really one physical register or adjacent stack slots. 1137 // This greatly simplifies the cases here compared to sparc. 1138 1139 if (src.first()->is_stack()) { 1140 if (dst.first()->is_stack()) { 1141 __ movl(rax, Address(rbp, reg2offset_in(src.first()))); 1142 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax); 1143 } else { 1144 // stack to reg 1145 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 1146 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()))); 1147 } 1148 } else if (dst.first()->is_stack()) { 1149 // reg to stack 1150 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 1151 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); 1152 } else { 1153 // reg to reg 1154 // In theory these overlap but the ordering is such that this is likely a nop 1155 if ( src.first() != dst.first()) { 1156 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 1157 } 1158 } 1159 } 1160 1161 // A long move 1162 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1163 1164 // The calling conventions assures us that each VMregpair is either 1165 // all really one physical register or adjacent stack slots. 1166 // This greatly simplifies the cases here compared to sparc. 1167 1168 if (src.is_single_phys_reg() ) { 1169 if (dst.is_single_phys_reg()) { 1170 if (dst.first() != src.first()) { 1171 __ mov(dst.first()->as_Register(), src.first()->as_Register()); 1172 } 1173 } else { 1174 assert(dst.is_single_reg(), "not a stack pair"); 1175 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1176 } 1177 } else if (dst.is_single_phys_reg()) { 1178 assert(src.is_single_reg(), "not a stack pair"); 1179 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first()))); 1180 } else { 1181 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 1182 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 1183 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1184 } 1185 } 1186 1187 // A double move 1188 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1189 1190 // The calling conventions assures us that each VMregpair is either 1191 // all really one physical register or adjacent stack slots. 1192 // This greatly simplifies the cases here compared to sparc. 1193 1194 if (src.is_single_phys_reg() ) { 1195 if (dst.is_single_phys_reg()) { 1196 // In theory these overlap but the ordering is such that this is likely a nop 1197 if ( src.first() != dst.first()) { 1198 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 1199 } 1200 } else { 1201 assert(dst.is_single_reg(), "not a stack pair"); 1202 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); 1203 } 1204 } else if (dst.is_single_phys_reg()) { 1205 assert(src.is_single_reg(), "not a stack pair"); 1206 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first()))); 1207 } else { 1208 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 1209 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 1210 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); 1211 } 1212 } 1213 1214 1215 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1216 // We always ignore the frame_slots arg and just use the space just below frame pointer 1217 // which by this time is free to use 1218 switch (ret_type) { 1219 case T_FLOAT: 1220 __ movflt(Address(rbp, -wordSize), xmm0); 1221 break; 1222 case T_DOUBLE: 1223 __ movdbl(Address(rbp, -wordSize), xmm0); 1224 break; 1225 case T_VOID: break; 1226 default: { 1227 __ movptr(Address(rbp, -wordSize), rax); 1228 } 1229 } 1230 } 1231 1232 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1233 // We always ignore the frame_slots arg and just use the space just below frame pointer 1234 // which by this time is free to use 1235 switch (ret_type) { 1236 case T_FLOAT: 1237 __ movflt(xmm0, Address(rbp, -wordSize)); 1238 break; 1239 case T_DOUBLE: 1240 __ movdbl(xmm0, Address(rbp, -wordSize)); 1241 break; 1242 case T_VOID: break; 1243 default: { 1244 __ movptr(rax, Address(rbp, -wordSize)); 1245 } 1246 } 1247 } 1248 1249 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { 1250 for ( int i = first_arg ; i < arg_count ; i++ ) { 1251 if (args[i].first()->is_Register()) { 1252 __ push(args[i].first()->as_Register()); 1253 } else if (args[i].first()->is_XMMRegister()) { 1254 __ subptr(rsp, 2*wordSize); 1255 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister()); 1256 } 1257 } 1258 } 1259 1260 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { 1261 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { 1262 if (args[i].first()->is_Register()) { 1263 __ pop(args[i].first()->as_Register()); 1264 } else if (args[i].first()->is_XMMRegister()) { 1265 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0)); 1266 __ addptr(rsp, 2*wordSize); 1267 } 1268 } 1269 } 1270 1271 1272 static void save_or_restore_arguments(MacroAssembler* masm, 1273 const int stack_slots, 1274 const int total_in_args, 1275 const int arg_save_area, 1276 OopMap* map, 1277 VMRegPair* in_regs, 1278 BasicType* in_sig_bt) { 1279 // if map is non-NULL then the code should store the values, 1280 // otherwise it should load them. 1281 int slot = arg_save_area; 1282 // Save down double word first 1283 for ( int i = 0; i < total_in_args; i++) { 1284 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) { 1285 int offset = slot * VMRegImpl::stack_slot_size; 1286 slot += VMRegImpl::slots_per_word; 1287 assert(slot <= stack_slots, "overflow"); 1288 if (map != NULL) { 1289 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); 1290 } else { 1291 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); 1292 } 1293 } 1294 if (in_regs[i].first()->is_Register() && 1295 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { 1296 int offset = slot * VMRegImpl::stack_slot_size; 1297 if (map != NULL) { 1298 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); 1299 if (in_sig_bt[i] == T_ARRAY) { 1300 map->set_oop(VMRegImpl::stack2reg(slot));; 1301 } 1302 } else { 1303 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); 1304 } 1305 slot += VMRegImpl::slots_per_word; 1306 } 1307 } 1308 // Save or restore single word registers 1309 for ( int i = 0; i < total_in_args; i++) { 1310 if (in_regs[i].first()->is_Register()) { 1311 int offset = slot * VMRegImpl::stack_slot_size; 1312 slot++; 1313 assert(slot <= stack_slots, "overflow"); 1314 1315 // Value is in an input register pass we must flush it to the stack 1316 const Register reg = in_regs[i].first()->as_Register(); 1317 switch (in_sig_bt[i]) { 1318 case T_BOOLEAN: 1319 case T_CHAR: 1320 case T_BYTE: 1321 case T_SHORT: 1322 case T_INT: 1323 if (map != NULL) { 1324 __ movl(Address(rsp, offset), reg); 1325 } else { 1326 __ movl(reg, Address(rsp, offset)); 1327 } 1328 break; 1329 case T_ARRAY: 1330 case T_LONG: 1331 // handled above 1332 break; 1333 case T_OBJECT: 1334 default: ShouldNotReachHere(); 1335 } 1336 } else if (in_regs[i].first()->is_XMMRegister()) { 1337 if (in_sig_bt[i] == T_FLOAT) { 1338 int offset = slot * VMRegImpl::stack_slot_size; 1339 slot++; 1340 assert(slot <= stack_slots, "overflow"); 1341 if (map != NULL) { 1342 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); 1343 } else { 1344 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); 1345 } 1346 } 1347 } else if (in_regs[i].first()->is_stack()) { 1348 if (in_sig_bt[i] == T_ARRAY && map != NULL) { 1349 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1350 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); 1351 } 1352 } 1353 } 1354 } 1355 1356 1357 // Check GC_locker::needs_gc and enter the runtime if it's true. This 1358 // keeps a new JNI critical region from starting until a GC has been 1359 // forced. Save down any oops in registers and describe them in an 1360 // OopMap. 1361 static void check_needs_gc_for_critical_native(MacroAssembler* masm, 1362 int stack_slots, 1363 int total_c_args, 1364 int total_in_args, 1365 int arg_save_area, 1366 OopMapSet* oop_maps, 1367 VMRegPair* in_regs, 1368 BasicType* in_sig_bt) { 1369 __ block_comment("check GC_locker::needs_gc"); 1370 Label cont; 1371 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false); 1372 __ jcc(Assembler::equal, cont); 1373 1374 // Save down any incoming oops and call into the runtime to halt for a GC 1375 1376 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1377 save_or_restore_arguments(masm, stack_slots, total_in_args, 1378 arg_save_area, map, in_regs, in_sig_bt); 1379 1380 address the_pc = __ pc(); 1381 oop_maps->add_gc_map( __ offset(), map); 1382 __ set_last_Java_frame(rsp, noreg, the_pc); 1383 1384 __ block_comment("block_for_jni_critical"); 1385 __ movptr(c_rarg0, r15_thread); 1386 __ mov(r12, rsp); // remember sp 1387 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 1388 __ andptr(rsp, -16); // align stack as required by ABI 1389 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical))); 1390 __ mov(rsp, r12); // restore sp 1391 __ reinit_heapbase(); 1392 1393 __ reset_last_Java_frame(false); 1394 1395 save_or_restore_arguments(masm, stack_slots, total_in_args, 1396 arg_save_area, NULL, in_regs, in_sig_bt); 1397 1398 __ bind(cont); 1399 #ifdef ASSERT 1400 if (StressCriticalJNINatives) { 1401 // Stress register saving 1402 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1403 save_or_restore_arguments(masm, stack_slots, total_in_args, 1404 arg_save_area, map, in_regs, in_sig_bt); 1405 // Destroy argument registers 1406 for (int i = 0; i < total_in_args - 1; i++) { 1407 if (in_regs[i].first()->is_Register()) { 1408 const Register reg = in_regs[i].first()->as_Register(); 1409 __ xorptr(reg, reg); 1410 } else if (in_regs[i].first()->is_XMMRegister()) { 1411 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister()); 1412 } else if (in_regs[i].first()->is_FloatRegister()) { 1413 ShouldNotReachHere(); 1414 } else if (in_regs[i].first()->is_stack()) { 1415 // Nothing to do 1416 } else { 1417 ShouldNotReachHere(); 1418 } 1419 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) { 1420 i++; 1421 } 1422 } 1423 1424 save_or_restore_arguments(masm, stack_slots, total_in_args, 1425 arg_save_area, NULL, in_regs, in_sig_bt); 1426 } 1427 #endif 1428 } 1429 1430 // Unpack an array argument into a pointer to the body and the length 1431 // if the array is non-null, otherwise pass 0 for both. 1432 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { 1433 Register tmp_reg = rax; 1434 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg, 1435 "possible collision"); 1436 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg, 1437 "possible collision"); 1438 1439 __ block_comment("unpack_array_argument {"); 1440 1441 // Pass the length, ptr pair 1442 Label is_null, done; 1443 VMRegPair tmp; 1444 tmp.set_ptr(tmp_reg->as_VMReg()); 1445 if (reg.first()->is_stack()) { 1446 // Load the arg up from the stack 1447 move_ptr(masm, reg, tmp); 1448 reg = tmp; 1449 } 1450 __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); 1451 __ jccb(Assembler::equal, is_null); 1452 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type))); 1453 move_ptr(masm, tmp, body_arg); 1454 // load the length relative to the body. 1455 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() - 1456 arrayOopDesc::base_offset_in_bytes(in_elem_type))); 1457 move32_64(masm, tmp, length_arg); 1458 __ jmpb(done); 1459 __ bind(is_null); 1460 // Pass zeros 1461 __ xorptr(tmp_reg, tmp_reg); 1462 move_ptr(masm, tmp, body_arg); 1463 move32_64(masm, tmp, length_arg); 1464 __ bind(done); 1465 1466 __ block_comment("} unpack_array_argument"); 1467 } 1468 1469 1470 // Different signatures may require very different orders for the move 1471 // to avoid clobbering other arguments. There's no simple way to 1472 // order them safely. Compute a safe order for issuing stores and 1473 // break any cycles in those stores. This code is fairly general but 1474 // it's not necessary on the other platforms so we keep it in the 1475 // platform dependent code instead of moving it into a shared file. 1476 // (See bugs 7013347 & 7145024.) 1477 // Note that this code is specific to LP64. 1478 class ComputeMoveOrder: public StackObj { 1479 class MoveOperation: public ResourceObj { 1480 friend class ComputeMoveOrder; 1481 private: 1482 VMRegPair _src; 1483 VMRegPair _dst; 1484 int _src_index; 1485 int _dst_index; 1486 bool _processed; 1487 MoveOperation* _next; 1488 MoveOperation* _prev; 1489 1490 static int get_id(VMRegPair r) { 1491 return r.first()->value(); 1492 } 1493 1494 public: 1495 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): 1496 _src(src) 1497 , _src_index(src_index) 1498 , _dst(dst) 1499 , _dst_index(dst_index) 1500 , _next(NULL) 1501 , _prev(NULL) 1502 , _processed(false) { 1503 } 1504 1505 VMRegPair src() const { return _src; } 1506 int src_id() const { return get_id(src()); } 1507 int src_index() const { return _src_index; } 1508 VMRegPair dst() const { return _dst; } 1509 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; } 1510 int dst_index() const { return _dst_index; } 1511 int dst_id() const { return get_id(dst()); } 1512 MoveOperation* next() const { return _next; } 1513 MoveOperation* prev() const { return _prev; } 1514 void set_processed() { _processed = true; } 1515 bool is_processed() const { return _processed; } 1516 1517 // insert 1518 void break_cycle(VMRegPair temp_register) { 1519 // create a new store following the last store 1520 // to move from the temp_register to the original 1521 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst()); 1522 1523 // break the cycle of links and insert new_store at the end 1524 // break the reverse link. 1525 MoveOperation* p = prev(); 1526 assert(p->next() == this, "must be"); 1527 _prev = NULL; 1528 p->_next = new_store; 1529 new_store->_prev = p; 1530 1531 // change the original store to save it's value in the temp. 1532 set_dst(-1, temp_register); 1533 } 1534 1535 void link(GrowableArray<MoveOperation*>& killer) { 1536 // link this store in front the store that it depends on 1537 MoveOperation* n = killer.at_grow(src_id(), NULL); 1538 if (n != NULL) { 1539 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet"); 1540 _next = n; 1541 n->_prev = this; 1542 } 1543 } 1544 }; 1545 1546 private: 1547 GrowableArray<MoveOperation*> edges; 1548 1549 public: 1550 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs, 1551 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) { 1552 // Move operations where the dest is the stack can all be 1553 // scheduled first since they can't interfere with the other moves. 1554 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { 1555 if (in_sig_bt[i] == T_ARRAY) { 1556 c_arg--; 1557 if (out_regs[c_arg].first()->is_stack() && 1558 out_regs[c_arg + 1].first()->is_stack()) { 1559 arg_order.push(i); 1560 arg_order.push(c_arg); 1561 } else { 1562 if (out_regs[c_arg].first()->is_stack() || 1563 in_regs[i].first() == out_regs[c_arg].first()) { 1564 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]); 1565 } else { 1566 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); 1567 } 1568 } 1569 } else if (in_sig_bt[i] == T_VOID) { 1570 arg_order.push(i); 1571 arg_order.push(c_arg); 1572 } else { 1573 if (out_regs[c_arg].first()->is_stack() || 1574 in_regs[i].first() == out_regs[c_arg].first()) { 1575 arg_order.push(i); 1576 arg_order.push(c_arg); 1577 } else { 1578 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); 1579 } 1580 } 1581 } 1582 // Break any cycles in the register moves and emit the in the 1583 // proper order. 1584 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg); 1585 for (int i = 0; i < stores->length(); i++) { 1586 arg_order.push(stores->at(i)->src_index()); 1587 arg_order.push(stores->at(i)->dst_index()); 1588 } 1589 } 1590 1591 // Collected all the move operations 1592 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) { 1593 if (src.first() == dst.first()) return; 1594 edges.append(new MoveOperation(src_index, src, dst_index, dst)); 1595 } 1596 1597 // Walk the edges breaking cycles between moves. The result list 1598 // can be walked in order to produce the proper set of loads 1599 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) { 1600 // Record which moves kill which values 1601 GrowableArray<MoveOperation*> killer; 1602 for (int i = 0; i < edges.length(); i++) { 1603 MoveOperation* s = edges.at(i); 1604 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer"); 1605 killer.at_put_grow(s->dst_id(), s, NULL); 1606 } 1607 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL, 1608 "make sure temp isn't in the registers that are killed"); 1609 1610 // create links between loads and stores 1611 for (int i = 0; i < edges.length(); i++) { 1612 edges.at(i)->link(killer); 1613 } 1614 1615 // at this point, all the move operations are chained together 1616 // in a doubly linked list. Processing it backwards finds 1617 // the beginning of the chain, forwards finds the end. If there's 1618 // a cycle it can be broken at any point, so pick an edge and walk 1619 // backward until the list ends or we end where we started. 1620 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>(); 1621 for (int e = 0; e < edges.length(); e++) { 1622 MoveOperation* s = edges.at(e); 1623 if (!s->is_processed()) { 1624 MoveOperation* start = s; 1625 // search for the beginning of the chain or cycle 1626 while (start->prev() != NULL && start->prev() != s) { 1627 start = start->prev(); 1628 } 1629 if (start->prev() == s) { 1630 start->break_cycle(temp_register); 1631 } 1632 // walk the chain forward inserting to store list 1633 while (start != NULL) { 1634 stores->append(start); 1635 start->set_processed(); 1636 start = start->next(); 1637 } 1638 } 1639 } 1640 return stores; 1641 } 1642 }; 1643 1644 static void verify_oop_args(MacroAssembler* masm, 1645 methodHandle method, 1646 const BasicType* sig_bt, 1647 const VMRegPair* regs) { 1648 Register temp_reg = rbx; // not part of any compiled calling seq 1649 if (VerifyOops) { 1650 for (int i = 0; i < method->size_of_parameters(); i++) { 1651 if (sig_bt[i] == T_OBJECT || 1652 sig_bt[i] == T_ARRAY) { 1653 VMReg r = regs[i].first(); 1654 assert(r->is_valid(), "bad oop arg"); 1655 if (r->is_stack()) { 1656 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); 1657 __ verify_oop(temp_reg); 1658 } else { 1659 __ verify_oop(r->as_Register()); 1660 } 1661 } 1662 } 1663 } 1664 } 1665 1666 static void gen_special_dispatch(MacroAssembler* masm, 1667 methodHandle method, 1668 const BasicType* sig_bt, 1669 const VMRegPair* regs) { 1670 verify_oop_args(masm, method, sig_bt, regs); 1671 vmIntrinsics::ID iid = method->intrinsic_id(); 1672 1673 // Now write the args into the outgoing interpreter space 1674 bool has_receiver = false; 1675 Register receiver_reg = noreg; 1676 int member_arg_pos = -1; 1677 Register member_reg = noreg; 1678 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); 1679 if (ref_kind != 0) { 1680 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument 1681 member_reg = rbx; // known to be free at this point 1682 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); 1683 } else if (iid == vmIntrinsics::_invokeBasic) { 1684 has_receiver = true; 1685 } else { 1686 fatal(err_msg_res("unexpected intrinsic id %d", iid)); 1687 } 1688 1689 if (member_reg != noreg) { 1690 // Load the member_arg into register, if necessary. 1691 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); 1692 VMReg r = regs[member_arg_pos].first(); 1693 if (r->is_stack()) { 1694 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); 1695 } else { 1696 // no data motion is needed 1697 member_reg = r->as_Register(); 1698 } 1699 } 1700 1701 if (has_receiver) { 1702 // Make sure the receiver is loaded into a register. 1703 assert(method->size_of_parameters() > 0, "oob"); 1704 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); 1705 VMReg r = regs[0].first(); 1706 assert(r->is_valid(), "bad receiver arg"); 1707 if (r->is_stack()) { 1708 // Porting note: This assumes that compiled calling conventions always 1709 // pass the receiver oop in a register. If this is not true on some 1710 // platform, pick a temp and load the receiver from stack. 1711 fatal("receiver always in a register"); 1712 receiver_reg = j_rarg0; // known to be free at this point 1713 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); 1714 } else { 1715 // no data motion is needed 1716 receiver_reg = r->as_Register(); 1717 } 1718 } 1719 1720 // Figure out which address we are really jumping to: 1721 MethodHandles::generate_method_handle_dispatch(masm, iid, 1722 receiver_reg, member_reg, /*for_compiler_entry:*/ true); 1723 } 1724 1725 // --------------------------------------------------------------------------- 1726 // Generate a native wrapper for a given method. The method takes arguments 1727 // in the Java compiled code convention, marshals them to the native 1728 // convention (handlizes oops, etc), transitions to native, makes the call, 1729 // returns to java state (possibly blocking), unhandlizes any result and 1730 // returns. 1731 // 1732 // Critical native functions are a shorthand for the use of 1733 // GetPrimtiveArrayCritical and disallow the use of any other JNI 1734 // functions. The wrapper is expected to unpack the arguments before 1735 // passing them to the callee and perform checks before and after the 1736 // native call to ensure that they GC_locker 1737 // lock_critical/unlock_critical semantics are followed. Some other 1738 // parts of JNI setup are skipped like the tear down of the JNI handle 1739 // block and the check for pending exceptions it's impossible for them 1740 // to be thrown. 1741 // 1742 // They are roughly structured like this: 1743 // if (GC_locker::needs_gc()) 1744 // SharedRuntime::block_for_jni_critical(); 1745 // tranistion to thread_in_native 1746 // unpack arrray arguments and call native entry point 1747 // check for safepoint in progress 1748 // check if any thread suspend flags are set 1749 // call into JVM and possible unlock the JNI critical 1750 // if a GC was suppressed while in the critical native. 1751 // transition back to thread_in_Java 1752 // return to caller 1753 // 1754 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, 1755 methodHandle method, 1756 int compile_id, 1757 BasicType* in_sig_bt, 1758 VMRegPair* in_regs, 1759 BasicType ret_type) { 1760 if (method->is_method_handle_intrinsic()) { 1761 vmIntrinsics::ID iid = method->intrinsic_id(); 1762 intptr_t start = (intptr_t)__ pc(); 1763 int vep_offset = ((intptr_t)__ pc()) - start; 1764 gen_special_dispatch(masm, 1765 method, 1766 in_sig_bt, 1767 in_regs); 1768 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period 1769 __ flush(); 1770 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually 1771 return nmethod::new_native_nmethod(method, 1772 compile_id, 1773 masm->code(), 1774 vep_offset, 1775 frame_complete, 1776 stack_slots / VMRegImpl::slots_per_word, 1777 in_ByteSize(-1), 1778 in_ByteSize(-1), 1779 (OopMapSet*)NULL); 1780 } 1781 bool is_critical_native = true; 1782 address native_func = method->critical_native_function(); 1783 if (native_func == NULL) { 1784 native_func = method->native_function(); 1785 is_critical_native = false; 1786 } 1787 assert(native_func != NULL, "must have function"); 1788 1789 // An OopMap for lock (and class if static) 1790 OopMapSet *oop_maps = new OopMapSet(); 1791 intptr_t start = (intptr_t)__ pc(); 1792 1793 // We have received a description of where all the java arg are located 1794 // on entry to the wrapper. We need to convert these args to where 1795 // the jni function will expect them. To figure out where they go 1796 // we convert the java signature to a C signature by inserting 1797 // the hidden arguments as arg[0] and possibly arg[1] (static method) 1798 1799 const int total_in_args = method->size_of_parameters(); 1800 int total_c_args = total_in_args; 1801 if (!is_critical_native) { 1802 total_c_args += 1; 1803 if (method->is_static()) { 1804 total_c_args++; 1805 } 1806 } else { 1807 for (int i = 0; i < total_in_args; i++) { 1808 if (in_sig_bt[i] == T_ARRAY) { 1809 total_c_args++; 1810 } 1811 } 1812 } 1813 1814 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); 1815 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); 1816 BasicType* in_elem_bt = NULL; 1817 1818 int argc = 0; 1819 if (!is_critical_native) { 1820 out_sig_bt[argc++] = T_ADDRESS; 1821 if (method->is_static()) { 1822 out_sig_bt[argc++] = T_OBJECT; 1823 } 1824 1825 for (int i = 0; i < total_in_args ; i++ ) { 1826 out_sig_bt[argc++] = in_sig_bt[i]; 1827 } 1828 } else { 1829 Thread* THREAD = Thread::current(); 1830 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); 1831 SignatureStream ss(method->signature()); 1832 for (int i = 0; i < total_in_args ; i++ ) { 1833 if (in_sig_bt[i] == T_ARRAY) { 1834 // Arrays are passed as int, elem* pair 1835 out_sig_bt[argc++] = T_INT; 1836 out_sig_bt[argc++] = T_ADDRESS; 1837 Symbol* atype = ss.as_symbol(CHECK_NULL); 1838 const char* at = atype->as_C_string(); 1839 if (strlen(at) == 2) { 1840 assert(at[0] == '[', "must be"); 1841 switch (at[1]) { 1842 case 'B': in_elem_bt[i] = T_BYTE; break; 1843 case 'C': in_elem_bt[i] = T_CHAR; break; 1844 case 'D': in_elem_bt[i] = T_DOUBLE; break; 1845 case 'F': in_elem_bt[i] = T_FLOAT; break; 1846 case 'I': in_elem_bt[i] = T_INT; break; 1847 case 'J': in_elem_bt[i] = T_LONG; break; 1848 case 'S': in_elem_bt[i] = T_SHORT; break; 1849 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; 1850 default: ShouldNotReachHere(); 1851 } 1852 } 1853 } else { 1854 out_sig_bt[argc++] = in_sig_bt[i]; 1855 in_elem_bt[i] = T_VOID; 1856 } 1857 if (in_sig_bt[i] != T_VOID) { 1858 assert(in_sig_bt[i] == ss.type(), "must match"); 1859 ss.next(); 1860 } 1861 } 1862 } 1863 1864 // Now figure out where the args must be stored and how much stack space 1865 // they require. 1866 int out_arg_slots; 1867 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); 1868 1869 // Compute framesize for the wrapper. We need to handlize all oops in 1870 // incoming registers 1871 1872 // Calculate the total number of stack slots we will need. 1873 1874 // First count the abi requirement plus all of the outgoing args 1875 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 1876 1877 // Now the space for the inbound oop handle area 1878 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers 1879 if (is_critical_native) { 1880 // Critical natives may have to call out so they need a save area 1881 // for register arguments. 1882 int double_slots = 0; 1883 int single_slots = 0; 1884 for ( int i = 0; i < total_in_args; i++) { 1885 if (in_regs[i].first()->is_Register()) { 1886 const Register reg = in_regs[i].first()->as_Register(); 1887 switch (in_sig_bt[i]) { 1888 case T_BOOLEAN: 1889 case T_BYTE: 1890 case T_SHORT: 1891 case T_CHAR: 1892 case T_INT: single_slots++; break; 1893 case T_ARRAY: // specific to LP64 (7145024) 1894 case T_LONG: double_slots++; break; 1895 default: ShouldNotReachHere(); 1896 } 1897 } else if (in_regs[i].first()->is_XMMRegister()) { 1898 switch (in_sig_bt[i]) { 1899 case T_FLOAT: single_slots++; break; 1900 case T_DOUBLE: double_slots++; break; 1901 default: ShouldNotReachHere(); 1902 } 1903 } else if (in_regs[i].first()->is_FloatRegister()) { 1904 ShouldNotReachHere(); 1905 } 1906 } 1907 total_save_slots = double_slots * 2 + single_slots; 1908 // align the save area 1909 if (double_slots != 0) { 1910 stack_slots = round_to(stack_slots, 2); 1911 } 1912 } 1913 1914 int oop_handle_offset = stack_slots; 1915 stack_slots += total_save_slots; 1916 1917 // Now any space we need for handlizing a klass if static method 1918 1919 int klass_slot_offset = 0; 1920 int klass_offset = -1; 1921 int lock_slot_offset = 0; 1922 bool is_static = false; 1923 1924 if (method->is_static()) { 1925 klass_slot_offset = stack_slots; 1926 stack_slots += VMRegImpl::slots_per_word; 1927 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; 1928 is_static = true; 1929 } 1930 1931 // Plus a lock if needed 1932 1933 if (method->is_synchronized()) { 1934 lock_slot_offset = stack_slots; 1935 stack_slots += VMRegImpl::slots_per_word; 1936 } 1937 1938 // Now a place (+2) to save return values or temp during shuffling 1939 // + 4 for return address (which we own) and saved rbp 1940 stack_slots += 6; 1941 1942 // Ok The space we have allocated will look like: 1943 // 1944 // 1945 // FP-> | | 1946 // |---------------------| 1947 // | 2 slots for moves | 1948 // |---------------------| 1949 // | lock box (if sync) | 1950 // |---------------------| <- lock_slot_offset 1951 // | klass (if static) | 1952 // |---------------------| <- klass_slot_offset 1953 // | oopHandle area | 1954 // |---------------------| <- oop_handle_offset (6 java arg registers) 1955 // | outbound memory | 1956 // | based arguments | 1957 // | | 1958 // |---------------------| 1959 // | | 1960 // SP-> | out_preserved_slots | 1961 // 1962 // 1963 1964 1965 // Now compute actual number of stack words we need rounding to make 1966 // stack properly aligned. 1967 stack_slots = round_to(stack_slots, StackAlignmentInSlots); 1968 1969 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 1970 1971 // First thing make an ic check to see if we should even be here 1972 1973 // We are free to use all registers as temps without saving them and 1974 // restoring them except rbp. rbp is the only callee save register 1975 // as far as the interpreter and the compiler(s) are concerned. 1976 1977 1978 const Register ic_reg = rax; 1979 const Register receiver = j_rarg0; 1980 1981 Label hit; 1982 Label exception_pending; 1983 1984 assert_different_registers(ic_reg, receiver, rscratch1); 1985 __ verify_oop(receiver); 1986 __ load_klass(rscratch1, receiver); 1987 __ cmpq(ic_reg, rscratch1); 1988 __ jcc(Assembler::equal, hit); 1989 1990 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1991 1992 // Verified entry point must be aligned 1993 __ align(8); 1994 1995 __ bind(hit); 1996 1997 int vep_offset = ((intptr_t)__ pc()) - start; 1998 1999 // The instruction at the verified entry point must be 5 bytes or longer 2000 // because it can be patched on the fly by make_non_entrant. The stack bang 2001 // instruction fits that requirement. 2002 2003 // Generate stack overflow check 2004 2005 if (UseStackBanging) { 2006 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); 2007 } else { 2008 // need a 5 byte instruction to allow MT safe patching to non-entrant 2009 __ fat_nop(); 2010 } 2011 2012 // Generate a new frame for the wrapper. 2013 __ enter(); 2014 // -2 because return address is already present and so is saved rbp 2015 __ subptr(rsp, stack_size - 2*wordSize); 2016 2017 // Frame is now completed as far as size and linkage. 2018 int frame_complete = ((intptr_t)__ pc()) - start; 2019 2020 if (UseRTMLocking) { 2021 // Abort RTM transaction before calling JNI 2022 // because critical section will be large and will be 2023 // aborted anyway. Also nmethod could be deoptimized. 2024 __ xabort(0); 2025 } 2026 2027 #ifdef ASSERT 2028 { 2029 Label L; 2030 __ mov(rax, rsp); 2031 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI) 2032 __ cmpptr(rax, rsp); 2033 __ jcc(Assembler::equal, L); 2034 __ stop("improperly aligned stack"); 2035 __ bind(L); 2036 } 2037 #endif /* ASSERT */ 2038 2039 2040 // We use r14 as the oop handle for the receiver/klass 2041 // It is callee save so it survives the call to native 2042 2043 const Register oop_handle_reg = r14; 2044 2045 if (is_critical_native) { 2046 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, 2047 oop_handle_offset, oop_maps, in_regs, in_sig_bt); 2048 } 2049 2050 // 2051 // We immediately shuffle the arguments so that any vm call we have to 2052 // make from here on out (sync slow path, jvmti, etc.) we will have 2053 // captured the oops from our caller and have a valid oopMap for 2054 // them. 2055 2056 // ----------------- 2057 // The Grand Shuffle 2058 2059 // The Java calling convention is either equal (linux) or denser (win64) than the 2060 // c calling convention. However the because of the jni_env argument the c calling 2061 // convention always has at least one more (and two for static) arguments than Java. 2062 // Therefore if we move the args from java -> c backwards then we will never have 2063 // a register->register conflict and we don't have to build a dependency graph 2064 // and figure out how to break any cycles. 2065 // 2066 2067 // Record esp-based slot for receiver on stack for non-static methods 2068 int receiver_offset = -1; 2069 2070 // This is a trick. We double the stack slots so we can claim 2071 // the oops in the caller's frame. Since we are sure to have 2072 // more args than the caller doubling is enough to make 2073 // sure we can capture all the incoming oop args from the 2074 // caller. 2075 // 2076 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 2077 2078 // Mark location of rbp (someday) 2079 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp)); 2080 2081 // Use eax, ebx as temporaries during any memory-memory moves we have to do 2082 // All inbound args are referenced based on rbp and all outbound args via rsp. 2083 2084 2085 #ifdef ASSERT 2086 bool reg_destroyed[RegisterImpl::number_of_registers]; 2087 bool freg_destroyed[XMMRegisterImpl::number_of_registers]; 2088 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 2089 reg_destroyed[r] = false; 2090 } 2091 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) { 2092 freg_destroyed[f] = false; 2093 } 2094 2095 #endif /* ASSERT */ 2096 2097 // This may iterate in two different directions depending on the 2098 // kind of native it is. The reason is that for regular JNI natives 2099 // the incoming and outgoing registers are offset upwards and for 2100 // critical natives they are offset down. 2101 GrowableArray<int> arg_order(2 * total_in_args); 2102 VMRegPair tmp_vmreg; 2103 tmp_vmreg.set2(rbx->as_VMReg()); 2104 2105 if (!is_critical_native) { 2106 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { 2107 arg_order.push(i); 2108 arg_order.push(c_arg); 2109 } 2110 } else { 2111 // Compute a valid move order, using tmp_vmreg to break any cycles 2112 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); 2113 } 2114 2115 int temploc = -1; 2116 for (int ai = 0; ai < arg_order.length(); ai += 2) { 2117 int i = arg_order.at(ai); 2118 int c_arg = arg_order.at(ai + 1); 2119 __ block_comment(err_msg("move %d -> %d", i, c_arg)); 2120 if (c_arg == -1) { 2121 assert(is_critical_native, "should only be required for critical natives"); 2122 // This arg needs to be moved to a temporary 2123 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); 2124 in_regs[i] = tmp_vmreg; 2125 temploc = i; 2126 continue; 2127 } else if (i == -1) { 2128 assert(is_critical_native, "should only be required for critical natives"); 2129 // Read from the temporary location 2130 assert(temploc != -1, "must be valid"); 2131 i = temploc; 2132 temploc = -1; 2133 } 2134 #ifdef ASSERT 2135 if (in_regs[i].first()->is_Register()) { 2136 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); 2137 } else if (in_regs[i].first()->is_XMMRegister()) { 2138 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!"); 2139 } 2140 if (out_regs[c_arg].first()->is_Register()) { 2141 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 2142 } else if (out_regs[c_arg].first()->is_XMMRegister()) { 2143 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; 2144 } 2145 #endif /* ASSERT */ 2146 switch (in_sig_bt[i]) { 2147 case T_ARRAY: 2148 if (is_critical_native) { 2149 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); 2150 c_arg++; 2151 #ifdef ASSERT 2152 if (out_regs[c_arg].first()->is_Register()) { 2153 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 2154 } else if (out_regs[c_arg].first()->is_XMMRegister()) { 2155 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; 2156 } 2157 #endif 2158 break; 2159 } 2160 case T_OBJECT: 2161 assert(!is_critical_native, "no oop arguments"); 2162 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], 2163 ((i == 0) && (!is_static)), 2164 &receiver_offset); 2165 break; 2166 case T_VOID: 2167 break; 2168 2169 case T_FLOAT: 2170 float_move(masm, in_regs[i], out_regs[c_arg]); 2171 break; 2172 2173 case T_DOUBLE: 2174 assert( i + 1 < total_in_args && 2175 in_sig_bt[i + 1] == T_VOID && 2176 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 2177 double_move(masm, in_regs[i], out_regs[c_arg]); 2178 break; 2179 2180 case T_LONG : 2181 long_move(masm, in_regs[i], out_regs[c_arg]); 2182 break; 2183 2184 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 2185 2186 default: 2187 move32_64(masm, in_regs[i], out_regs[c_arg]); 2188 } 2189 } 2190 2191 int c_arg; 2192 2193 // Pre-load a static method's oop into r14. Used both by locking code and 2194 // the normal JNI call code. 2195 if (!is_critical_native) { 2196 // point c_arg at the first arg that is already loaded in case we 2197 // need to spill before we call out 2198 c_arg = total_c_args - total_in_args; 2199 2200 if (method->is_static()) { 2201 2202 // load oop into a register 2203 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror())); 2204 2205 // Now handlize the static class mirror it's known not-null. 2206 __ movptr(Address(rsp, klass_offset), oop_handle_reg); 2207 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); 2208 2209 // Now get the handle 2210 __ lea(oop_handle_reg, Address(rsp, klass_offset)); 2211 // store the klass handle as second argument 2212 __ movptr(c_rarg1, oop_handle_reg); 2213 // and protect the arg if we must spill 2214 c_arg--; 2215 } 2216 } else { 2217 // For JNI critical methods we need to save all registers in save_args. 2218 c_arg = 0; 2219 } 2220 2221 // Change state to native (we save the return address in the thread, since it might not 2222 // be pushed on the stack when we do a a stack traversal). It is enough that the pc() 2223 // points into the right code segment. It does not have to be the correct return pc. 2224 // We use the same pc/oopMap repeatedly when we call out 2225 2226 intptr_t the_pc = (intptr_t) __ pc(); 2227 oop_maps->add_gc_map(the_pc - start, map); 2228 2229 __ set_last_Java_frame(rsp, noreg, (address)the_pc); 2230 2231 2232 // We have all of the arguments setup at this point. We must not touch any register 2233 // argument registers at this point (what if we save/restore them there are no oop? 2234 2235 { 2236 SkipIfEqual skip(masm, &DTraceMethodProbes, false); 2237 // protect the args we've loaded 2238 save_args(masm, total_c_args, c_arg, out_regs); 2239 __ mov_metadata(c_rarg1, method()); 2240 __ call_VM_leaf( 2241 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), 2242 r15_thread, c_rarg1); 2243 restore_args(masm, total_c_args, c_arg, out_regs); 2244 } 2245 2246 // RedefineClasses() tracing support for obsolete method entry 2247 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { 2248 // protect the args we've loaded 2249 save_args(masm, total_c_args, c_arg, out_regs); 2250 __ mov_metadata(c_rarg1, method()); 2251 __ call_VM_leaf( 2252 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), 2253 r15_thread, c_rarg1); 2254 restore_args(masm, total_c_args, c_arg, out_regs); 2255 } 2256 2257 // Lock a synchronized method 2258 2259 // Register definitions used by locking and unlocking 2260 2261 const Register swap_reg = rax; // Must use rax for cmpxchg instruction 2262 const Register obj_reg = rbx; // Will contain the oop 2263 const Register lock_reg = r13; // Address of compiler lock object (BasicLock) 2264 const Register old_hdr = r13; // value of old header at unlock time 2265 2266 Label slow_path_lock; 2267 Label lock_done; 2268 2269 if (method->is_synchronized()) { 2270 assert(!is_critical_native, "unhandled"); 2271 2272 2273 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes(); 2274 2275 // Get the handle (the 2nd argument) 2276 __ mov(oop_handle_reg, c_rarg1); 2277 2278 // Get address of the box 2279 2280 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2281 2282 // Load the oop from the handle 2283 __ movptr(obj_reg, Address(oop_handle_reg, 0)); 2284 2285 if (UseBiasedLocking) { 2286 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock); 2287 } 2288 2289 // Load immediate 1 into swap_reg %rax 2290 __ movl(swap_reg, 1); 2291 2292 // Load (object->mark() | 1) into swap_reg %rax 2293 __ orptr(swap_reg, Address(obj_reg, 0)); 2294 2295 // Save (object->mark() | 1) into BasicLock's displaced header 2296 __ movptr(Address(lock_reg, mark_word_offset), swap_reg); 2297 2298 if (os::is_MP()) { 2299 __ lock(); 2300 } 2301 2302 // src -> dest iff dest == rax else rax <- dest 2303 __ cmpxchgptr(lock_reg, Address(obj_reg, 0)); 2304 __ jcc(Assembler::equal, lock_done); 2305 2306 // Hmm should this move to the slow path code area??? 2307 2308 // Test if the oopMark is an obvious stack pointer, i.e., 2309 // 1) (mark & 3) == 0, and 2310 // 2) rsp <= mark < mark + os::pagesize() 2311 // These 3 tests can be done by evaluating the following 2312 // expression: ((mark - rsp) & (3 - os::vm_page_size())), 2313 // assuming both stack pointer and pagesize have their 2314 // least significant 2 bits clear. 2315 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg 2316 2317 __ subptr(swap_reg, rsp); 2318 __ andptr(swap_reg, 3 - os::vm_page_size()); 2319 2320 // Save the test result, for recursive case, the result is zero 2321 __ movptr(Address(lock_reg, mark_word_offset), swap_reg); 2322 __ jcc(Assembler::notEqual, slow_path_lock); 2323 2324 // Slow path will re-enter here 2325 2326 __ bind(lock_done); 2327 } 2328 2329 2330 // Finally just about ready to make the JNI call 2331 2332 2333 // get JNIEnv* which is first argument to native 2334 if (!is_critical_native) { 2335 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset()))); 2336 } 2337 2338 // Now set thread in native 2339 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native); 2340 2341 __ call(RuntimeAddress(native_func)); 2342 2343 // Verify or restore cpu control state after JNI call 2344 __ restore_cpu_control_state_after_jni(); 2345 2346 // Unpack native results. 2347 switch (ret_type) { 2348 case T_BOOLEAN: __ c2bool(rax); break; 2349 case T_CHAR : __ movzwl(rax, rax); break; 2350 case T_BYTE : __ sign_extend_byte (rax); break; 2351 case T_SHORT : __ sign_extend_short(rax); break; 2352 case T_INT : /* nothing to do */ break; 2353 case T_DOUBLE : 2354 case T_FLOAT : 2355 // Result is in xmm0 we'll save as needed 2356 break; 2357 case T_ARRAY: // Really a handle 2358 case T_OBJECT: // Really a handle 2359 break; // can't de-handlize until after safepoint check 2360 case T_VOID: break; 2361 case T_LONG: break; 2362 default : ShouldNotReachHere(); 2363 } 2364 2365 // Switch thread to "native transition" state before reading the synchronization state. 2366 // This additional state is necessary because reading and testing the synchronization 2367 // state is not atomic w.r.t. GC, as this scenario demonstrates: 2368 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. 2369 // VM thread changes sync state to synchronizing and suspends threads for GC. 2370 // Thread A is resumed to finish this native method, but doesn't block here since it 2371 // didn't see any synchronization is progress, and escapes. 2372 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans); 2373 2374 if(os::is_MP()) { 2375 if (UseMembar) { 2376 // Force this write out before the read below 2377 __ membar(Assembler::Membar_mask_bits( 2378 Assembler::LoadLoad | Assembler::LoadStore | 2379 Assembler::StoreLoad | Assembler::StoreStore)); 2380 } else { 2381 // Write serialization page so VM thread can do a pseudo remote membar. 2382 // We use the current thread pointer to calculate a thread specific 2383 // offset to write to within the page. This minimizes bus traffic 2384 // due to cache line collision. 2385 __ serialize_memory(r15_thread, rcx); 2386 } 2387 } 2388 2389 Label after_transition; 2390 2391 // check for safepoint operation in progress and/or pending suspend requests 2392 { 2393 Label Continue; 2394 2395 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()), 2396 SafepointSynchronize::_not_synchronized); 2397 2398 Label L; 2399 __ jcc(Assembler::notEqual, L); 2400 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0); 2401 __ jcc(Assembler::equal, Continue); 2402 __ bind(L); 2403 2404 // Don't use call_VM as it will see a possible pending exception and forward it 2405 // and never return here preventing us from clearing _last_native_pc down below. 2406 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are 2407 // preserved and correspond to the bcp/locals pointers. So we do a runtime call 2408 // by hand. 2409 // 2410 save_native_result(masm, ret_type, stack_slots); 2411 __ mov(c_rarg0, r15_thread); 2412 __ mov(r12, rsp); // remember sp 2413 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 2414 __ andptr(rsp, -16); // align stack as required by ABI 2415 if (!is_critical_native) { 2416 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans))); 2417 } else { 2418 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); 2419 } 2420 __ mov(rsp, r12); // restore sp 2421 __ reinit_heapbase(); 2422 // Restore any method result value 2423 restore_native_result(masm, ret_type, stack_slots); 2424 2425 if (is_critical_native) { 2426 // The call above performed the transition to thread_in_Java so 2427 // skip the transition logic below. 2428 __ jmpb(after_transition); 2429 } 2430 2431 __ bind(Continue); 2432 } 2433 2434 // change thread state 2435 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java); 2436 __ bind(after_transition); 2437 2438 Label reguard; 2439 Label reguard_done; 2440 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled); 2441 __ jcc(Assembler::equal, reguard); 2442 __ bind(reguard_done); 2443 2444 // native result if any is live 2445 2446 // Unlock 2447 Label unlock_done; 2448 Label slow_path_unlock; 2449 if (method->is_synchronized()) { 2450 2451 // Get locked oop from the handle we passed to jni 2452 __ movptr(obj_reg, Address(oop_handle_reg, 0)); 2453 2454 Label done; 2455 2456 if (UseBiasedLocking) { 2457 __ biased_locking_exit(obj_reg, old_hdr, done); 2458 } 2459 2460 // Simple recursive lock? 2461 2462 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD); 2463 __ jcc(Assembler::equal, done); 2464 2465 // Must save rax if if it is live now because cmpxchg must use it 2466 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { 2467 save_native_result(masm, ret_type, stack_slots); 2468 } 2469 2470 2471 // get address of the stack lock 2472 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2473 // get old displaced header 2474 __ movptr(old_hdr, Address(rax, 0)); 2475 2476 // Atomic swap old header if oop still contains the stack lock 2477 if (os::is_MP()) { 2478 __ lock(); 2479 } 2480 __ cmpxchgptr(old_hdr, Address(obj_reg, 0)); 2481 __ jcc(Assembler::notEqual, slow_path_unlock); 2482 2483 // slow path re-enters here 2484 __ bind(unlock_done); 2485 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { 2486 restore_native_result(masm, ret_type, stack_slots); 2487 } 2488 2489 __ bind(done); 2490 2491 } 2492 { 2493 SkipIfEqual skip(masm, &DTraceMethodProbes, false); 2494 save_native_result(masm, ret_type, stack_slots); 2495 __ mov_metadata(c_rarg1, method()); 2496 __ call_VM_leaf( 2497 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), 2498 r15_thread, c_rarg1); 2499 restore_native_result(masm, ret_type, stack_slots); 2500 } 2501 2502 __ reset_last_Java_frame(false); 2503 2504 // Unbox oop result, e.g. JNIHandles::resolve value. 2505 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { 2506 __ resolve_jobject(rax /* value */, 2507 r15_thread /* thread */, 2508 rcx /* tmp */); 2509 } 2510 2511 if (!is_critical_native) { 2512 // reset handle block 2513 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset())); 2514 __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD); 2515 } 2516 2517 // pop our frame 2518 2519 __ leave(); 2520 2521 if (!is_critical_native) { 2522 // Any exception pending? 2523 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); 2524 __ jcc(Assembler::notEqual, exception_pending); 2525 } 2526 2527 // Return 2528 2529 __ ret(0); 2530 2531 // Unexpected paths are out of line and go here 2532 2533 if (!is_critical_native) { 2534 // forward the exception 2535 __ bind(exception_pending); 2536 2537 // and forward the exception 2538 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2539 } 2540 2541 // Slow path locking & unlocking 2542 if (method->is_synchronized()) { 2543 2544 // BEGIN Slow path lock 2545 __ bind(slow_path_lock); 2546 2547 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM 2548 // args are (oop obj, BasicLock* lock, JavaThread* thread) 2549 2550 // protect the args we've loaded 2551 save_args(masm, total_c_args, c_arg, out_regs); 2552 2553 __ mov(c_rarg0, obj_reg); 2554 __ mov(c_rarg1, lock_reg); 2555 __ mov(c_rarg2, r15_thread); 2556 2557 // Not a leaf but we have last_Java_frame setup as we want 2558 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3); 2559 restore_args(masm, total_c_args, c_arg, out_regs); 2560 2561 #ifdef ASSERT 2562 { Label L; 2563 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); 2564 __ jcc(Assembler::equal, L); 2565 __ stop("no pending exception allowed on exit from monitorenter"); 2566 __ bind(L); 2567 } 2568 #endif 2569 __ jmp(lock_done); 2570 2571 // END Slow path lock 2572 2573 // BEGIN Slow path unlock 2574 __ bind(slow_path_unlock); 2575 2576 // If we haven't already saved the native result we must save it now as xmm registers 2577 // are still exposed. 2578 2579 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { 2580 save_native_result(masm, ret_type, stack_slots); 2581 } 2582 2583 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2584 2585 __ mov(c_rarg0, obj_reg); 2586 __ mov(r12, rsp); // remember sp 2587 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 2588 __ andptr(rsp, -16); // align stack as required by ABI 2589 2590 // Save pending exception around call to VM (which contains an EXCEPTION_MARK) 2591 // NOTE that obj_reg == rbx currently 2592 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset()))); 2593 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); 2594 2595 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C))); 2596 __ mov(rsp, r12); // restore sp 2597 __ reinit_heapbase(); 2598 #ifdef ASSERT 2599 { 2600 Label L; 2601 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD); 2602 __ jcc(Assembler::equal, L); 2603 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); 2604 __ bind(L); 2605 } 2606 #endif /* ASSERT */ 2607 2608 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx); 2609 2610 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { 2611 restore_native_result(masm, ret_type, stack_slots); 2612 } 2613 __ jmp(unlock_done); 2614 2615 // END Slow path unlock 2616 2617 } // synchronized 2618 2619 // SLOW PATH Reguard the stack if needed 2620 2621 __ bind(reguard); 2622 save_native_result(masm, ret_type, stack_slots); 2623 __ mov(r12, rsp); // remember sp 2624 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows 2625 __ andptr(rsp, -16); // align stack as required by ABI 2626 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages))); 2627 __ mov(rsp, r12); // restore sp 2628 __ reinit_heapbase(); 2629 restore_native_result(masm, ret_type, stack_slots); 2630 // and continue 2631 __ jmp(reguard_done); 2632 2633 2634 2635 __ flush(); 2636 2637 nmethod *nm = nmethod::new_native_nmethod(method, 2638 compile_id, 2639 masm->code(), 2640 vep_offset, 2641 frame_complete, 2642 stack_slots / VMRegImpl::slots_per_word, 2643 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), 2644 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), 2645 oop_maps); 2646 2647 if (is_critical_native) { 2648 nm->set_lazy_critical_native(true); 2649 } 2650 2651 return nm; 2652 2653 } 2654 2655 #ifdef HAVE_DTRACE_H 2656 // --------------------------------------------------------------------------- 2657 // Generate a dtrace nmethod for a given signature. The method takes arguments 2658 // in the Java compiled code convention, marshals them to the native 2659 // abi and then leaves nops at the position you would expect to call a native 2660 // function. When the probe is enabled the nops are replaced with a trap 2661 // instruction that dtrace inserts and the trace will cause a notification 2662 // to dtrace. 2663 // 2664 // The probes are only able to take primitive types and java/lang/String as 2665 // arguments. No other java types are allowed. Strings are converted to utf8 2666 // strings so that from dtrace point of view java strings are converted to C 2667 // strings. There is an arbitrary fixed limit on the total space that a method 2668 // can use for converting the strings. (256 chars per string in the signature). 2669 // So any java string larger then this is truncated. 2670 2671 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; 2672 static bool offsets_initialized = false; 2673 2674 2675 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm, 2676 methodHandle method) { 2677 2678 2679 // generate_dtrace_nmethod is guarded by a mutex so we are sure to 2680 // be single threaded in this method. 2681 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); 2682 2683 if (!offsets_initialized) { 2684 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize; 2685 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize; 2686 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize; 2687 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize; 2688 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize; 2689 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize; 2690 2691 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize; 2692 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize; 2693 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize; 2694 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize; 2695 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize; 2696 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize; 2697 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize; 2698 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize; 2699 2700 offsets_initialized = true; 2701 } 2702 // Fill in the signature array, for the calling-convention call. 2703 int total_args_passed = method->size_of_parameters(); 2704 2705 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); 2706 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); 2707 2708 // The signature we are going to use for the trap that dtrace will see 2709 // java/lang/String is converted. We drop "this" and any other object 2710 // is converted to NULL. (A one-slot java/lang/Long object reference 2711 // is converted to a two-slot long, which is why we double the allocation). 2712 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); 2713 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); 2714 2715 int i=0; 2716 int total_strings = 0; 2717 int first_arg_to_pass = 0; 2718 int total_c_args = 0; 2719 2720 // Skip the receiver as dtrace doesn't want to see it 2721 if( !method->is_static() ) { 2722 in_sig_bt[i++] = T_OBJECT; 2723 first_arg_to_pass = 1; 2724 } 2725 2726 // We need to convert the java args to where a native (non-jni) function 2727 // would expect them. To figure out where they go we convert the java 2728 // signature to a C signature. 2729 2730 SignatureStream ss(method->signature()); 2731 for ( ; !ss.at_return_type(); ss.next()) { 2732 BasicType bt = ss.type(); 2733 in_sig_bt[i++] = bt; // Collect remaining bits of signature 2734 out_sig_bt[total_c_args++] = bt; 2735 if( bt == T_OBJECT) { 2736 Symbol* s = ss.as_symbol_or_null(); // symbol is created 2737 if (s == vmSymbols::java_lang_String()) { 2738 total_strings++; 2739 out_sig_bt[total_c_args-1] = T_ADDRESS; 2740 } else if (s == vmSymbols::java_lang_Boolean() || 2741 s == vmSymbols::java_lang_Character() || 2742 s == vmSymbols::java_lang_Byte() || 2743 s == vmSymbols::java_lang_Short() || 2744 s == vmSymbols::java_lang_Integer() || 2745 s == vmSymbols::java_lang_Float()) { 2746 out_sig_bt[total_c_args-1] = T_INT; 2747 } else if (s == vmSymbols::java_lang_Long() || 2748 s == vmSymbols::java_lang_Double()) { 2749 out_sig_bt[total_c_args-1] = T_LONG; 2750 out_sig_bt[total_c_args++] = T_VOID; 2751 } 2752 } else if ( bt == T_LONG || bt == T_DOUBLE ) { 2753 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots 2754 // We convert double to long 2755 out_sig_bt[total_c_args-1] = T_LONG; 2756 out_sig_bt[total_c_args++] = T_VOID; 2757 } else if ( bt == T_FLOAT) { 2758 // We convert float to int 2759 out_sig_bt[total_c_args-1] = T_INT; 2760 } 2761 } 2762 2763 assert(i==total_args_passed, "validly parsed signature"); 2764 2765 // Now get the compiled-Java layout as input arguments 2766 int comp_args_on_stack; 2767 comp_args_on_stack = SharedRuntime::java_calling_convention( 2768 in_sig_bt, in_regs, total_args_passed, false); 2769 2770 // Now figure out where the args must be stored and how much stack space 2771 // they require (neglecting out_preserve_stack_slots but space for storing 2772 // the 1st six register arguments). It's weird see int_stk_helper. 2773 2774 int out_arg_slots; 2775 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); 2776 2777 // Calculate the total number of stack slots we will need. 2778 2779 // First count the abi requirement plus all of the outgoing args 2780 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 2781 2782 // Now space for the string(s) we must convert 2783 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1); 2784 for (i = 0; i < total_strings ; i++) { 2785 string_locs[i] = stack_slots; 2786 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size; 2787 } 2788 2789 // Plus the temps we might need to juggle register args 2790 // regs take two slots each 2791 stack_slots += (Argument::n_int_register_parameters_c + 2792 Argument::n_float_register_parameters_c) * 2; 2793 2794 2795 // + 4 for return address (which we own) and saved rbp, 2796 2797 stack_slots += 4; 2798 2799 // Ok The space we have allocated will look like: 2800 // 2801 // 2802 // FP-> | | 2803 // |---------------------| 2804 // | string[n] | 2805 // |---------------------| <- string_locs[n] 2806 // | string[n-1] | 2807 // |---------------------| <- string_locs[n-1] 2808 // | ... | 2809 // | ... | 2810 // |---------------------| <- string_locs[1] 2811 // | string[0] | 2812 // |---------------------| <- string_locs[0] 2813 // | outbound memory | 2814 // | based arguments | 2815 // | | 2816 // |---------------------| 2817 // | | 2818 // SP-> | out_preserved_slots | 2819 // 2820 // 2821 2822 // Now compute actual number of stack words we need rounding to make 2823 // stack properly aligned. 2824 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); 2825 2826 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 2827 2828 intptr_t start = (intptr_t)__ pc(); 2829 2830 // First thing make an ic check to see if we should even be here 2831 2832 // We are free to use all registers as temps without saving them and 2833 // restoring them except rbp. rbp, is the only callee save register 2834 // as far as the interpreter and the compiler(s) are concerned. 2835 2836 const Register ic_reg = rax; 2837 const Register receiver = rcx; 2838 Label hit; 2839 Label exception_pending; 2840 2841 2842 __ verify_oop(receiver); 2843 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes())); 2844 __ jcc(Assembler::equal, hit); 2845 2846 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 2847 2848 // verified entry must be aligned for code patching. 2849 // and the first 5 bytes must be in the same cache line 2850 // if we align at 8 then we will be sure 5 bytes are in the same line 2851 __ align(8); 2852 2853 __ bind(hit); 2854 2855 int vep_offset = ((intptr_t)__ pc()) - start; 2856 2857 2858 // The instruction at the verified entry point must be 5 bytes or longer 2859 // because it can be patched on the fly by make_non_entrant. The stack bang 2860 // instruction fits that requirement. 2861 2862 // Generate stack overflow check 2863 2864 if (UseStackBanging) { 2865 if (stack_size <= StackShadowPages*os::vm_page_size()) { 2866 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); 2867 } else { 2868 __ movl(rax, stack_size); 2869 __ bang_stack_size(rax, rbx); 2870 } 2871 } else { 2872 // need a 5 byte instruction to allow MT safe patching to non-entrant 2873 __ fat_nop(); 2874 } 2875 2876 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5, 2877 "valid size for make_non_entrant"); 2878 2879 // Generate a new frame for the wrapper. 2880 __ enter(); 2881 2882 // -4 because return address is already present and so is saved rbp, 2883 if (stack_size - 2*wordSize != 0) { 2884 __ subq(rsp, stack_size - 2*wordSize); 2885 } 2886 2887 // Frame is now completed as far a size and linkage. 2888 2889 int frame_complete = ((intptr_t)__ pc()) - start; 2890 2891 int c_arg, j_arg; 2892 2893 // State of input register args 2894 2895 bool live[ConcreteRegisterImpl::number_of_registers]; 2896 2897 live[j_rarg0->as_VMReg()->value()] = false; 2898 live[j_rarg1->as_VMReg()->value()] = false; 2899 live[j_rarg2->as_VMReg()->value()] = false; 2900 live[j_rarg3->as_VMReg()->value()] = false; 2901 live[j_rarg4->as_VMReg()->value()] = false; 2902 live[j_rarg5->as_VMReg()->value()] = false; 2903 2904 live[j_farg0->as_VMReg()->value()] = false; 2905 live[j_farg1->as_VMReg()->value()] = false; 2906 live[j_farg2->as_VMReg()->value()] = false; 2907 live[j_farg3->as_VMReg()->value()] = false; 2908 live[j_farg4->as_VMReg()->value()] = false; 2909 live[j_farg5->as_VMReg()->value()] = false; 2910 live[j_farg6->as_VMReg()->value()] = false; 2911 live[j_farg7->as_VMReg()->value()] = false; 2912 2913 2914 bool rax_is_zero = false; 2915 2916 // All args (except strings) destined for the stack are moved first 2917 for (j_arg = first_arg_to_pass, c_arg = 0 ; 2918 j_arg < total_args_passed ; j_arg++, c_arg++ ) { 2919 VMRegPair src = in_regs[j_arg]; 2920 VMRegPair dst = out_regs[c_arg]; 2921 2922 // Get the real reg value or a dummy (rsp) 2923 2924 int src_reg = src.first()->is_reg() ? 2925 src.first()->value() : 2926 rsp->as_VMReg()->value(); 2927 2928 bool useless = in_sig_bt[j_arg] == T_ARRAY || 2929 (in_sig_bt[j_arg] == T_OBJECT && 2930 out_sig_bt[c_arg] != T_INT && 2931 out_sig_bt[c_arg] != T_ADDRESS && 2932 out_sig_bt[c_arg] != T_LONG); 2933 2934 live[src_reg] = !useless; 2935 2936 if (dst.first()->is_stack()) { 2937 2938 // Even though a string arg in a register is still live after this loop 2939 // after the string conversion loop (next) it will be dead so we take 2940 // advantage of that now for simpler code to manage live. 2941 2942 live[src_reg] = false; 2943 switch (in_sig_bt[j_arg]) { 2944 2945 case T_ARRAY: 2946 case T_OBJECT: 2947 { 2948 Address stack_dst(rsp, reg2offset_out(dst.first())); 2949 2950 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { 2951 // need to unbox a one-word value 2952 Register in_reg = rax; 2953 if ( src.first()->is_reg() ) { 2954 in_reg = src.first()->as_Register(); 2955 } else { 2956 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); 2957 rax_is_zero = false; 2958 } 2959 Label skipUnbox; 2960 __ movptr(Address(rsp, reg2offset_out(dst.first())), 2961 (int32_t)NULL_WORD); 2962 __ testq(in_reg, in_reg); 2963 __ jcc(Assembler::zero, skipUnbox); 2964 2965 BasicType bt = out_sig_bt[c_arg]; 2966 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); 2967 Address src1(in_reg, box_offset); 2968 if ( bt == T_LONG ) { 2969 __ movq(in_reg, src1); 2970 __ movq(stack_dst, in_reg); 2971 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); 2972 ++c_arg; // skip over T_VOID to keep the loop indices in sync 2973 } else { 2974 __ movl(in_reg, src1); 2975 __ movl(stack_dst, in_reg); 2976 } 2977 2978 __ bind(skipUnbox); 2979 } else if (out_sig_bt[c_arg] != T_ADDRESS) { 2980 // Convert the arg to NULL 2981 if (!rax_is_zero) { 2982 __ xorq(rax, rax); 2983 rax_is_zero = true; 2984 } 2985 __ movq(stack_dst, rax); 2986 } 2987 } 2988 break; 2989 2990 case T_VOID: 2991 break; 2992 2993 case T_FLOAT: 2994 // This does the right thing since we know it is destined for the 2995 // stack 2996 float_move(masm, src, dst); 2997 break; 2998 2999 case T_DOUBLE: 3000 // This does the right thing since we know it is destined for the 3001 // stack 3002 double_move(masm, src, dst); 3003 break; 3004 3005 case T_LONG : 3006 long_move(masm, src, dst); 3007 break; 3008 3009 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 3010 3011 default: 3012 move32_64(masm, src, dst); 3013 } 3014 } 3015 3016 } 3017 3018 // If we have any strings we must store any register based arg to the stack 3019 // This includes any still live xmm registers too. 3020 3021 int sid = 0; 3022 3023 if (total_strings > 0 ) { 3024 for (j_arg = first_arg_to_pass, c_arg = 0 ; 3025 j_arg < total_args_passed ; j_arg++, c_arg++ ) { 3026 VMRegPair src = in_regs[j_arg]; 3027 VMRegPair dst = out_regs[c_arg]; 3028 3029 if (src.first()->is_reg()) { 3030 Address src_tmp(rbp, fp_offset[src.first()->value()]); 3031 3032 // string oops were left untouched by the previous loop even if the 3033 // eventual (converted) arg is destined for the stack so park them 3034 // away now (except for first) 3035 3036 if (out_sig_bt[c_arg] == T_ADDRESS) { 3037 Address utf8_addr = Address( 3038 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); 3039 if (sid != 1) { 3040 // The first string arg won't be killed until after the utf8 3041 // conversion 3042 __ movq(utf8_addr, src.first()->as_Register()); 3043 } 3044 } else if (dst.first()->is_reg()) { 3045 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) { 3046 3047 // Convert the xmm register to an int and store it in the reserved 3048 // location for the eventual c register arg 3049 XMMRegister f = src.first()->as_XMMRegister(); 3050 if (in_sig_bt[j_arg] == T_FLOAT) { 3051 __ movflt(src_tmp, f); 3052 } else { 3053 __ movdbl(src_tmp, f); 3054 } 3055 } else { 3056 // If the arg is an oop type we don't support don't bother to store 3057 // it remember string was handled above. 3058 bool useless = in_sig_bt[j_arg] == T_ARRAY || 3059 (in_sig_bt[j_arg] == T_OBJECT && 3060 out_sig_bt[c_arg] != T_INT && 3061 out_sig_bt[c_arg] != T_LONG); 3062 3063 if (!useless) { 3064 __ movq(src_tmp, src.first()->as_Register()); 3065 } 3066 } 3067 } 3068 } 3069 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { 3070 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); 3071 ++c_arg; // skip over T_VOID to keep the loop indices in sync 3072 } 3073 } 3074 3075 // Now that the volatile registers are safe, convert all the strings 3076 sid = 0; 3077 3078 for (j_arg = first_arg_to_pass, c_arg = 0 ; 3079 j_arg < total_args_passed ; j_arg++, c_arg++ ) { 3080 if (out_sig_bt[c_arg] == T_ADDRESS) { 3081 // It's a string 3082 Address utf8_addr = Address( 3083 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); 3084 // The first string we find might still be in the original java arg 3085 // register 3086 3087 VMReg src = in_regs[j_arg].first(); 3088 3089 // We will need to eventually save the final argument to the trap 3090 // in the von-volatile location dedicated to src. This is the offset 3091 // from fp we will use. 3092 int src_off = src->is_reg() ? 3093 fp_offset[src->value()] : reg2offset_in(src); 3094 3095 // This is where the argument will eventually reside 3096 VMRegPair dst = out_regs[c_arg]; 3097 3098 if (src->is_reg()) { 3099 if (sid == 1) { 3100 __ movq(c_rarg0, src->as_Register()); 3101 } else { 3102 __ movq(c_rarg0, utf8_addr); 3103 } 3104 } else { 3105 // arg is still in the original location 3106 __ movq(c_rarg0, Address(rbp, reg2offset_in(src))); 3107 } 3108 Label done, convert; 3109 3110 // see if the oop is NULL 3111 __ testq(c_rarg0, c_rarg0); 3112 __ jcc(Assembler::notEqual, convert); 3113 3114 if (dst.first()->is_reg()) { 3115 // Save the ptr to utf string in the origina src loc or the tmp 3116 // dedicated to it 3117 __ movq(Address(rbp, src_off), c_rarg0); 3118 } else { 3119 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0); 3120 } 3121 __ jmp(done); 3122 3123 __ bind(convert); 3124 3125 __ lea(c_rarg1, utf8_addr); 3126 if (dst.first()->is_reg()) { 3127 __ movq(Address(rbp, src_off), c_rarg1); 3128 } else { 3129 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1); 3130 } 3131 // And do the conversion 3132 __ call(RuntimeAddress( 3133 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf))); 3134 3135 __ bind(done); 3136 } 3137 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { 3138 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); 3139 ++c_arg; // skip over T_VOID to keep the loop indices in sync 3140 } 3141 } 3142 // The get_utf call killed all the c_arg registers 3143 live[c_rarg0->as_VMReg()->value()] = false; 3144 live[c_rarg1->as_VMReg()->value()] = false; 3145 live[c_rarg2->as_VMReg()->value()] = false; 3146 live[c_rarg3->as_VMReg()->value()] = false; 3147 live[c_rarg4->as_VMReg()->value()] = false; 3148 live[c_rarg5->as_VMReg()->value()] = false; 3149 3150 live[c_farg0->as_VMReg()->value()] = false; 3151 live[c_farg1->as_VMReg()->value()] = false; 3152 live[c_farg2->as_VMReg()->value()] = false; 3153 live[c_farg3->as_VMReg()->value()] = false; 3154 live[c_farg4->as_VMReg()->value()] = false; 3155 live[c_farg5->as_VMReg()->value()] = false; 3156 live[c_farg6->as_VMReg()->value()] = false; 3157 live[c_farg7->as_VMReg()->value()] = false; 3158 } 3159 3160 // Now we can finally move the register args to their desired locations 3161 3162 rax_is_zero = false; 3163 3164 for (j_arg = first_arg_to_pass, c_arg = 0 ; 3165 j_arg < total_args_passed ; j_arg++, c_arg++ ) { 3166 3167 VMRegPair src = in_regs[j_arg]; 3168 VMRegPair dst = out_regs[c_arg]; 3169 3170 // Only need to look for args destined for the interger registers (since we 3171 // convert float/double args to look like int/long outbound) 3172 if (dst.first()->is_reg()) { 3173 Register r = dst.first()->as_Register(); 3174 3175 // Check if the java arg is unsupported and thereofre useless 3176 bool useless = in_sig_bt[j_arg] == T_ARRAY || 3177 (in_sig_bt[j_arg] == T_OBJECT && 3178 out_sig_bt[c_arg] != T_INT && 3179 out_sig_bt[c_arg] != T_ADDRESS && 3180 out_sig_bt[c_arg] != T_LONG); 3181 3182 3183 // If we're going to kill an existing arg save it first 3184 if (live[dst.first()->value()]) { 3185 // you can't kill yourself 3186 if (src.first() != dst.first()) { 3187 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r); 3188 } 3189 } 3190 if (src.first()->is_reg()) { 3191 if (live[src.first()->value()] ) { 3192 if (in_sig_bt[j_arg] == T_FLOAT) { 3193 __ movdl(r, src.first()->as_XMMRegister()); 3194 } else if (in_sig_bt[j_arg] == T_DOUBLE) { 3195 __ movdq(r, src.first()->as_XMMRegister()); 3196 } else if (r != src.first()->as_Register()) { 3197 if (!useless) { 3198 __ movq(r, src.first()->as_Register()); 3199 } 3200 } 3201 } else { 3202 // If the arg is an oop type we don't support don't bother to store 3203 // it 3204 if (!useless) { 3205 if (in_sig_bt[j_arg] == T_DOUBLE || 3206 in_sig_bt[j_arg] == T_LONG || 3207 in_sig_bt[j_arg] == T_OBJECT ) { 3208 __ movq(r, Address(rbp, fp_offset[src.first()->value()])); 3209 } else { 3210 __ movl(r, Address(rbp, fp_offset[src.first()->value()])); 3211 } 3212 } 3213 } 3214 live[src.first()->value()] = false; 3215 } else if (!useless) { 3216 // full sized move even for int should be ok 3217 __ movq(r, Address(rbp, reg2offset_in(src.first()))); 3218 } 3219 3220 // At this point r has the original java arg in the final location 3221 // (assuming it wasn't useless). If the java arg was an oop 3222 // we have a bit more to do 3223 3224 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) { 3225 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { 3226 // need to unbox a one-word value 3227 Label skip; 3228 __ testq(r, r); 3229 __ jcc(Assembler::equal, skip); 3230 BasicType bt = out_sig_bt[c_arg]; 3231 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); 3232 Address src1(r, box_offset); 3233 if ( bt == T_LONG ) { 3234 __ movq(r, src1); 3235 } else { 3236 __ movl(r, src1); 3237 } 3238 __ bind(skip); 3239 3240 } else if (out_sig_bt[c_arg] != T_ADDRESS) { 3241 // Convert the arg to NULL 3242 __ xorq(r, r); 3243 } 3244 } 3245 3246 // dst can longer be holding an input value 3247 live[dst.first()->value()] = false; 3248 } 3249 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { 3250 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); 3251 ++c_arg; // skip over T_VOID to keep the loop indices in sync 3252 } 3253 } 3254 3255 3256 // Ok now we are done. Need to place the nop that dtrace wants in order to 3257 // patch in the trap 3258 int patch_offset = ((intptr_t)__ pc()) - start; 3259 3260 __ nop(); 3261 3262 3263 // Return 3264 3265 __ leave(); 3266 __ ret(0); 3267 3268 __ flush(); 3269 3270 nmethod *nm = nmethod::new_dtrace_nmethod( 3271 method, masm->code(), vep_offset, patch_offset, frame_complete, 3272 stack_slots / VMRegImpl::slots_per_word); 3273 return nm; 3274 3275 } 3276 3277 #endif // HAVE_DTRACE_H 3278 3279 // this function returns the adjust size (in number of words) to a c2i adapter 3280 // activation for use during deoptimization 3281 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) { 3282 return (callee_locals - callee_parameters) * Interpreter::stackElementWords; 3283 } 3284 3285 3286 uint SharedRuntime::out_preserve_stack_slots() { 3287 return 0; 3288 } 3289 3290 //------------------------------generate_deopt_blob---------------------------- 3291 void SharedRuntime::generate_deopt_blob() { 3292 // Allocate space for the code 3293 ResourceMark rm; 3294 // Setup code generation tools 3295 CodeBuffer buffer("deopt_blob", 2048, 1024); 3296 MacroAssembler* masm = new MacroAssembler(&buffer); 3297 int frame_size_in_words; 3298 OopMap* map = NULL; 3299 OopMapSet *oop_maps = new OopMapSet(); 3300 3301 // ------------- 3302 // This code enters when returning to a de-optimized nmethod. A return 3303 // address has been pushed on the the stack, and return values are in 3304 // registers. 3305 // If we are doing a normal deopt then we were called from the patched 3306 // nmethod from the point we returned to the nmethod. So the return 3307 // address on the stack is wrong by NativeCall::instruction_size 3308 // We will adjust the value so it looks like we have the original return 3309 // address on the stack (like when we eagerly deoptimized). 3310 // In the case of an exception pending when deoptimizing, we enter 3311 // with a return address on the stack that points after the call we patched 3312 // into the exception handler. We have the following register state from, 3313 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp). 3314 // rax: exception oop 3315 // rbx: exception handler 3316 // rdx: throwing pc 3317 // So in this case we simply jam rdx into the useless return address and 3318 // the stack looks just like we want. 3319 // 3320 // At this point we need to de-opt. We save the argument return 3321 // registers. We call the first C routine, fetch_unroll_info(). This 3322 // routine captures the return values and returns a structure which 3323 // describes the current frame size and the sizes of all replacement frames. 3324 // The current frame is compiled code and may contain many inlined 3325 // functions, each with their own JVM state. We pop the current frame, then 3326 // push all the new frames. Then we call the C routine unpack_frames() to 3327 // populate these frames. Finally unpack_frames() returns us the new target 3328 // address. Notice that callee-save registers are BLOWN here; they have 3329 // already been captured in the vframeArray at the time the return PC was 3330 // patched. 3331 address start = __ pc(); 3332 Label cont; 3333 3334 // Prolog for non exception case! 3335 3336 // Save everything in sight. 3337 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 3338 3339 // Normal deoptimization. Save exec mode for unpack_frames. 3340 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved 3341 __ jmp(cont); 3342 3343 int reexecute_offset = __ pc() - start; 3344 3345 // Reexecute case 3346 // return address is the pc describes what bci to do re-execute at 3347 3348 // No need to update map as each call to save_live_registers will produce identical oopmap 3349 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 3350 3351 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved 3352 __ jmp(cont); 3353 3354 int exception_offset = __ pc() - start; 3355 3356 // Prolog for exception case 3357 3358 // all registers are dead at this entry point, except for rax, and 3359 // rdx which contain the exception oop and exception pc 3360 // respectively. Set them in TLS and fall thru to the 3361 // unpack_with_exception_in_tls entry point. 3362 3363 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); 3364 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax); 3365 3366 int exception_in_tls_offset = __ pc() - start; 3367 3368 // new implementation because exception oop is now passed in JavaThread 3369 3370 // Prolog for exception case 3371 // All registers must be preserved because they might be used by LinearScan 3372 // Exceptiop oop and throwing PC are passed in JavaThread 3373 // tos: stack at point of call to method that threw the exception (i.e. only 3374 // args are on the stack, no return address) 3375 3376 // make room on stack for the return address 3377 // It will be patched later with the throwing pc. The correct value is not 3378 // available now because loading it from memory would destroy registers. 3379 __ push(0); 3380 3381 // Save everything in sight. 3382 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 3383 3384 // Now it is safe to overwrite any register 3385 3386 // Deopt during an exception. Save exec mode for unpack_frames. 3387 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved 3388 3389 // load throwing pc from JavaThread and patch it as the return address 3390 // of the current frame. Then clear the field in JavaThread 3391 3392 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); 3393 __ movptr(Address(rbp, wordSize), rdx); 3394 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 3395 3396 #ifdef ASSERT 3397 // verify that there is really an exception oop in JavaThread 3398 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); 3399 __ verify_oop(rax); 3400 3401 // verify that there is no pending exception 3402 Label no_pending_exception; 3403 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); 3404 __ testptr(rax, rax); 3405 __ jcc(Assembler::zero, no_pending_exception); 3406 __ stop("must not have pending exception here"); 3407 __ bind(no_pending_exception); 3408 #endif 3409 3410 __ bind(cont); 3411 3412 // Call C code. Need thread and this frame, but NOT official VM entry 3413 // crud. We cannot block on this call, no GC can happen. 3414 // 3415 // UnrollBlock* fetch_unroll_info(JavaThread* thread) 3416 3417 // fetch_unroll_info needs to call last_java_frame(). 3418 3419 __ set_last_Java_frame(noreg, noreg, NULL); 3420 #ifdef ASSERT 3421 { Label L; 3422 __ cmpptr(Address(r15_thread, 3423 JavaThread::last_Java_fp_offset()), 3424 (int32_t)0); 3425 __ jcc(Assembler::equal, L); 3426 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); 3427 __ bind(L); 3428 } 3429 #endif // ASSERT 3430 __ mov(c_rarg0, r15_thread); 3431 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); 3432 3433 // Need to have an oopmap that tells fetch_unroll_info where to 3434 // find any register it might need. 3435 oop_maps->add_gc_map(__ pc() - start, map); 3436 3437 __ reset_last_Java_frame(false); 3438 3439 // Load UnrollBlock* into rdi 3440 __ mov(rdi, rax); 3441 3442 Label noException; 3443 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending? 3444 __ jcc(Assembler::notEqual, noException); 3445 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); 3446 // QQQ this is useless it was NULL above 3447 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); 3448 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); 3449 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 3450 3451 __ verify_oop(rax); 3452 3453 // Overwrite the result registers with the exception results. 3454 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); 3455 // I think this is useless 3456 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx); 3457 3458 __ bind(noException); 3459 3460 // Only register save data is on the stack. 3461 // Now restore the result registers. Everything else is either dead 3462 // or captured in the vframeArray. 3463 RegisterSaver::restore_result_registers(masm); 3464 3465 // All of the register save area has been popped of the stack. Only the 3466 // return address remains. 3467 3468 // Pop all the frames we must move/replace. 3469 // 3470 // Frame picture (youngest to oldest) 3471 // 1: self-frame (no frame link) 3472 // 2: deopting frame (no frame link) 3473 // 3: caller of deopting frame (could be compiled/interpreted). 3474 // 3475 // Note: by leaving the return address of self-frame on the stack 3476 // and using the size of frame 2 to adjust the stack 3477 // when we are done the return to frame 3 will still be on the stack. 3478 3479 // Pop deoptimized frame 3480 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes())); 3481 __ addptr(rsp, rcx); 3482 3483 // rsp should be pointing at the return address to the caller (3) 3484 3485 // Pick up the initial fp we should save 3486 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved) 3487 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); 3488 3489 #ifdef ASSERT 3490 // Compilers generate code that bang the stack by as much as the 3491 // interpreter would need. So this stack banging should never 3492 // trigger a fault. Verify that it does not on non product builds. 3493 if (UseStackBanging) { 3494 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); 3495 __ bang_stack_size(rbx, rcx); 3496 } 3497 #endif 3498 3499 // Load address of array of frame pcs into rcx 3500 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); 3501 3502 // Trash the old pc 3503 __ addptr(rsp, wordSize); 3504 3505 // Load address of array of frame sizes into rsi 3506 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes())); 3507 3508 // Load counter into rdx 3509 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes())); 3510 3511 // Now adjust the caller's stack to make up for the extra locals 3512 // but record the original sp so that we can save it in the skeletal interpreter 3513 // frame and the stack walking of interpreter_sender will get the unextended sp 3514 // value and not the "real" sp value. 3515 3516 const Register sender_sp = r8; 3517 3518 __ mov(sender_sp, rsp); 3519 __ movl(rbx, Address(rdi, 3520 Deoptimization::UnrollBlock:: 3521 caller_adjustment_offset_in_bytes())); 3522 __ subptr(rsp, rbx); 3523 3524 // Push interpreter frames in a loop 3525 Label loop; 3526 __ bind(loop); 3527 __ movptr(rbx, Address(rsi, 0)); // Load frame size 3528 #ifdef CC_INTERP 3529 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and 3530 #ifdef ASSERT 3531 __ push(0xDEADDEAD); // Make a recognizable pattern 3532 __ push(0xDEADDEAD); 3533 #else /* ASSERT */ 3534 __ subptr(rsp, 2*wordSize); // skip the "static long no_param" 3535 #endif /* ASSERT */ 3536 #else 3537 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand 3538 #endif // CC_INTERP 3539 __ pushptr(Address(rcx, 0)); // Save return address 3540 __ enter(); // Save old & set new ebp 3541 __ subptr(rsp, rbx); // Prolog 3542 #ifdef CC_INTERP 3543 __ movptr(Address(rbp, 3544 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), 3545 sender_sp); // Make it walkable 3546 #else /* CC_INTERP */ 3547 // This value is corrected by layout_activation_impl 3548 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); 3549 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable 3550 #endif /* CC_INTERP */ 3551 __ mov(sender_sp, rsp); // Pass sender_sp to next frame 3552 __ addptr(rsi, wordSize); // Bump array pointer (sizes) 3553 __ addptr(rcx, wordSize); // Bump array pointer (pcs) 3554 __ decrementl(rdx); // Decrement counter 3555 __ jcc(Assembler::notZero, loop); 3556 __ pushptr(Address(rcx, 0)); // Save final return address 3557 3558 // Re-push self-frame 3559 __ enter(); // Save old & set new ebp 3560 3561 // Allocate a full sized register save area. 3562 // Return address and rbp are in place, so we allocate two less words. 3563 __ subptr(rsp, (frame_size_in_words - 2) * wordSize); 3564 3565 // Restore frame locals after moving the frame 3566 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0); 3567 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); 3568 3569 // Call C code. Need thread but NOT official VM entry 3570 // crud. We cannot block on this call, no GC can happen. Call should 3571 // restore return values to their stack-slots with the new SP. 3572 // 3573 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode) 3574 3575 // Use rbp because the frames look interpreted now 3576 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. 3577 // Don't need the precise return PC here, just precise enough to point into this code blob. 3578 address the_pc = __ pc(); 3579 __ set_last_Java_frame(noreg, rbp, the_pc); 3580 3581 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI 3582 __ mov(c_rarg0, r15_thread); 3583 __ movl(c_rarg1, r14); // second arg: exec_mode 3584 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); 3585 // Revert SP alignment after call since we're going to do some SP relative addressing below 3586 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset())); 3587 3588 // Set an oopmap for the call site 3589 // Use the same PC we used for the last java frame 3590 oop_maps->add_gc_map(the_pc - start, 3591 new OopMap( frame_size_in_words, 0 )); 3592 3593 // Clear fp AND pc 3594 __ reset_last_Java_frame(true); 3595 3596 // Collect return values 3597 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes())); 3598 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes())); 3599 // I think this is useless (throwing pc?) 3600 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes())); 3601 3602 // Pop self-frame. 3603 __ leave(); // Epilog 3604 3605 // Jump to interpreter 3606 __ ret(0); 3607 3608 // Make sure all code is generated 3609 masm->flush(); 3610 3611 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); 3612 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); 3613 } 3614 3615 #ifdef COMPILER2 3616 //------------------------------generate_uncommon_trap_blob-------------------- 3617 void SharedRuntime::generate_uncommon_trap_blob() { 3618 // Allocate space for the code 3619 ResourceMark rm; 3620 // Setup code generation tools 3621 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); 3622 MacroAssembler* masm = new MacroAssembler(&buffer); 3623 3624 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); 3625 3626 address start = __ pc(); 3627 3628 if (UseRTMLocking) { 3629 // Abort RTM transaction before possible nmethod deoptimization. 3630 __ xabort(0); 3631 } 3632 3633 // Push self-frame. We get here with a return address on the 3634 // stack, so rsp is 8-byte aligned until we allocate our frame. 3635 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog! 3636 3637 // No callee saved registers. rbp is assumed implicitly saved 3638 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); 3639 3640 // compiler left unloaded_class_index in j_rarg0 move to where the 3641 // runtime expects it. 3642 __ movl(c_rarg1, j_rarg0); 3643 3644 __ set_last_Java_frame(noreg, noreg, NULL); 3645 3646 // Call C code. Need thread but NOT official VM entry 3647 // crud. We cannot block on this call, no GC can happen. Call should 3648 // capture callee-saved registers as well as return values. 3649 // Thread is in rdi already. 3650 // 3651 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index); 3652 3653 __ mov(c_rarg0, r15_thread); 3654 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); 3655 3656 // Set an oopmap for the call site 3657 OopMapSet* oop_maps = new OopMapSet(); 3658 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0); 3659 3660 // location of rbp is known implicitly by the frame sender code 3661 3662 oop_maps->add_gc_map(__ pc() - start, map); 3663 3664 __ reset_last_Java_frame(false); 3665 3666 // Load UnrollBlock* into rdi 3667 __ mov(rdi, rax); 3668 3669 // Pop all the frames we must move/replace. 3670 // 3671 // Frame picture (youngest to oldest) 3672 // 1: self-frame (no frame link) 3673 // 2: deopting frame (no frame link) 3674 // 3: caller of deopting frame (could be compiled/interpreted). 3675 3676 // Pop self-frame. We have no frame, and must rely only on rax and rsp. 3677 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog! 3678 3679 // Pop deoptimized frame (int) 3680 __ movl(rcx, Address(rdi, 3681 Deoptimization::UnrollBlock:: 3682 size_of_deoptimized_frame_offset_in_bytes())); 3683 __ addptr(rsp, rcx); 3684 3685 // rsp should be pointing at the return address to the caller (3) 3686 3687 // Pick up the initial fp we should save 3688 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved) 3689 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); 3690 3691 #ifdef ASSERT 3692 // Compilers generate code that bang the stack by as much as the 3693 // interpreter would need. So this stack banging should never 3694 // trigger a fault. Verify that it does not on non product builds. 3695 if (UseStackBanging) { 3696 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); 3697 __ bang_stack_size(rbx, rcx); 3698 } 3699 #endif 3700 3701 // Load address of array of frame pcs into rcx (address*) 3702 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); 3703 3704 // Trash the return pc 3705 __ addptr(rsp, wordSize); 3706 3707 // Load address of array of frame sizes into rsi (intptr_t*) 3708 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock:: frame_sizes_offset_in_bytes())); 3709 3710 // Counter 3711 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock:: number_of_frames_offset_in_bytes())); // (int) 3712 3713 // Now adjust the caller's stack to make up for the extra locals but 3714 // record the original sp so that we can save it in the skeletal 3715 // interpreter frame and the stack walking of interpreter_sender 3716 // will get the unextended sp value and not the "real" sp value. 3717 3718 const Register sender_sp = r8; 3719 3720 __ mov(sender_sp, rsp); 3721 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock:: caller_adjustment_offset_in_bytes())); // (int) 3722 __ subptr(rsp, rbx); 3723 3724 // Push interpreter frames in a loop 3725 Label loop; 3726 __ bind(loop); 3727 __ movptr(rbx, Address(rsi, 0)); // Load frame size 3728 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand 3729 __ pushptr(Address(rcx, 0)); // Save return address 3730 __ enter(); // Save old & set new rbp 3731 __ subptr(rsp, rbx); // Prolog 3732 #ifdef CC_INTERP 3733 __ movptr(Address(rbp, 3734 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), 3735 sender_sp); // Make it walkable 3736 #else // CC_INTERP 3737 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), 3738 sender_sp); // Make it walkable 3739 // This value is corrected by layout_activation_impl 3740 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); 3741 #endif // CC_INTERP 3742 __ mov(sender_sp, rsp); // Pass sender_sp to next frame 3743 __ addptr(rsi, wordSize); // Bump array pointer (sizes) 3744 __ addptr(rcx, wordSize); // Bump array pointer (pcs) 3745 __ decrementl(rdx); // Decrement counter 3746 __ jcc(Assembler::notZero, loop); 3747 __ pushptr(Address(rcx, 0)); // Save final return address 3748 3749 // Re-push self-frame 3750 __ enter(); // Save old & set new rbp 3751 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt); 3752 // Prolog 3753 3754 // Use rbp because the frames look interpreted now 3755 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. 3756 // Don't need the precise return PC here, just precise enough to point into this code blob. 3757 address the_pc = __ pc(); 3758 __ set_last_Java_frame(noreg, rbp, the_pc); 3759 3760 // Call C code. Need thread but NOT official VM entry 3761 // crud. We cannot block on this call, no GC can happen. Call should 3762 // restore return values to their stack-slots with the new SP. 3763 // Thread is in rdi already. 3764 // 3765 // BasicType unpack_frames(JavaThread* thread, int exec_mode); 3766 3767 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI 3768 __ mov(c_rarg0, r15_thread); 3769 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap); 3770 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); 3771 3772 // Set an oopmap for the call site 3773 // Use the same PC we used for the last java frame 3774 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); 3775 3776 // Clear fp AND pc 3777 __ reset_last_Java_frame(true); 3778 3779 // Pop self-frame. 3780 __ leave(); // Epilog 3781 3782 // Jump to interpreter 3783 __ ret(0); 3784 3785 // Make sure all code is generated 3786 masm->flush(); 3787 3788 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, 3789 SimpleRuntimeFrame::framesize >> 1); 3790 } 3791 #endif // COMPILER2 3792 3793 3794 //------------------------------generate_handler_blob------ 3795 // 3796 // Generate a special Compile2Runtime blob that saves all registers, 3797 // and setup oopmap. 3798 // 3799 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { 3800 assert(StubRoutines::forward_exception_entry() != NULL, 3801 "must be generated before"); 3802 3803 ResourceMark rm; 3804 OopMapSet *oop_maps = new OopMapSet(); 3805 OopMap* map; 3806 3807 // Allocate space for the code. Setup code generation tools. 3808 CodeBuffer buffer("handler_blob", 2048, 1024); 3809 MacroAssembler* masm = new MacroAssembler(&buffer); 3810 3811 address start = __ pc(); 3812 address call_pc = NULL; 3813 int frame_size_in_words; 3814 bool cause_return = (poll_type == POLL_AT_RETURN); 3815 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP); 3816 3817 if (UseRTMLocking) { 3818 // Abort RTM transaction before calling runtime 3819 // because critical section will be large and will be 3820 // aborted anyway. Also nmethod could be deoptimized. 3821 __ xabort(0); 3822 } 3823 3824 // Make room for return address (or push it again) 3825 if (!cause_return) { 3826 __ push(rbx); 3827 } 3828 3829 // Save registers, fpu state, and flags 3830 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors); 3831 3832 // The following is basically a call_VM. However, we need the precise 3833 // address of the call in order to generate an oopmap. Hence, we do all the 3834 // work outselves. 3835 3836 __ set_last_Java_frame(noreg, noreg, NULL); 3837 3838 // The return address must always be correct so that frame constructor never 3839 // sees an invalid pc. 3840 3841 if (!cause_return) { 3842 // overwrite the dummy value we pushed on entry 3843 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset())); 3844 __ movptr(Address(rbp, wordSize), c_rarg0); 3845 } 3846 3847 // Do the call 3848 __ mov(c_rarg0, r15_thread); 3849 __ call(RuntimeAddress(call_ptr)); 3850 3851 // Set an oopmap for the call site. This oopmap will map all 3852 // oop-registers and debug-info registers as callee-saved. This 3853 // will allow deoptimization at this safepoint to find all possible 3854 // debug-info recordings, as well as let GC find all oops. 3855 3856 oop_maps->add_gc_map( __ pc() - start, map); 3857 3858 Label noException; 3859 3860 __ reset_last_Java_frame(false); 3861 3862 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 3863 __ jcc(Assembler::equal, noException); 3864 3865 // Exception pending 3866 3867 RegisterSaver::restore_live_registers(masm, save_vectors); 3868 3869 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 3870 3871 // No exception case 3872 __ bind(noException); 3873 3874 // Normal exit, restore registers and exit. 3875 RegisterSaver::restore_live_registers(masm, save_vectors); 3876 3877 __ ret(0); 3878 3879 // Make sure all code is generated 3880 masm->flush(); 3881 3882 // Fill-out other meta info 3883 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); 3884 } 3885 3886 // 3887 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss 3888 // 3889 // Generate a stub that calls into vm to find out the proper destination 3890 // of a java call. All the argument registers are live at this point 3891 // but since this is generic code we don't know what they are and the caller 3892 // must do any gc of the args. 3893 // 3894 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { 3895 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 3896 3897 // allocate space for the code 3898 ResourceMark rm; 3899 3900 CodeBuffer buffer(name, 1000, 512); 3901 MacroAssembler* masm = new MacroAssembler(&buffer); 3902 3903 int frame_size_in_words; 3904 3905 OopMapSet *oop_maps = new OopMapSet(); 3906 OopMap* map = NULL; 3907 3908 int start = __ offset(); 3909 3910 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 3911 3912 int frame_complete = __ offset(); 3913 3914 __ set_last_Java_frame(noreg, noreg, NULL); 3915 3916 __ mov(c_rarg0, r15_thread); 3917 3918 __ call(RuntimeAddress(destination)); 3919 3920 3921 // Set an oopmap for the call site. 3922 // We need this not only for callee-saved registers, but also for volatile 3923 // registers that the compiler might be keeping live across a safepoint. 3924 3925 oop_maps->add_gc_map( __ offset() - start, map); 3926 3927 // rax contains the address we are going to jump to assuming no exception got installed 3928 3929 // clear last_Java_sp 3930 __ reset_last_Java_frame(false); 3931 // check for pending exceptions 3932 Label pending; 3933 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 3934 __ jcc(Assembler::notEqual, pending); 3935 3936 // get the returned Method* 3937 __ get_vm_result_2(rbx, r15_thread); 3938 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx); 3939 3940 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); 3941 3942 RegisterSaver::restore_live_registers(masm); 3943 3944 // We are back the the original state on entry and ready to go. 3945 3946 __ jmp(rax); 3947 3948 // Pending exception after the safepoint 3949 3950 __ bind(pending); 3951 3952 RegisterSaver::restore_live_registers(masm); 3953 3954 // exception pending => remove activation and forward to exception handler 3955 3956 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD); 3957 3958 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); 3959 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 3960 3961 // ------------- 3962 // make sure all code is generated 3963 masm->flush(); 3964 3965 // return the blob 3966 // frame_size_words or bytes?? 3967 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true); 3968 } 3969 3970 3971 //------------------------------Montgomery multiplication------------------------ 3972 // 3973 3974 #ifndef _WINDOWS 3975 3976 // Subtract 0:b from carry:a. Return carry. 3977 static julong 3978 sub(julong a[], julong b[], julong carry, long len) { 3979 long long i = 0, cnt = len; 3980 julong tmp; 3981 asm volatile("clc; " 3982 "0: ; " 3983 "mov (%[b], %[i], 8), %[tmp]; " 3984 "sbb %[tmp], (%[a], %[i], 8); " 3985 "inc %[i]; dec %[cnt]; " 3986 "jne 0b; " 3987 "mov %[carry], %[tmp]; sbb $0, %[tmp]; " 3988 : [i]"+r"(i), [cnt]"+r"(cnt), [tmp]"=&r"(tmp) 3989 : [a]"r"(a), [b]"r"(b), [carry]"r"(carry) 3990 : "memory"); 3991 return tmp; 3992 } 3993 3994 // Multiply (unsigned) Long A by Long B, accumulating the double- 3995 // length result into the accumulator formed of T0, T1, and T2. 3996 #define MACC(A, B, T0, T1, T2) \ 3997 do { \ 3998 unsigned long hi, lo; \ 3999 asm volatile("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4" \ 4000 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \ 4001 : "r"(A), "a"(B) : "cc"); \ 4002 } while(0) 4003 4004 // As above, but add twice the double-length result into the 4005 // accumulator. 4006 #define MACC2(A, B, T0, T1, T2) \ 4007 do { \ 4008 unsigned long hi, lo; \ 4009 asm volatile("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4;" \ 4010 "add %%rax, %2; adc %%rdx, %3; adc $0, %4" \ 4011 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \ 4012 : "r"(A), "a"(B) : "cc"); \ 4013 } while(0) 4014 4015 #else //_WINDOWS 4016 4017 // Visual Studio 2010 does not have _addcarry_u64 instrinsic 4018 // (TBD: does 2015?) 4019 #if defined(_WINDOWS) && _MSC_VER >= 1910 4020 static julong 4021 sub(julong a[], julong b[], julong carry, long len) { 4022 long i; 4023 julong tmp; 4024 unsigned char c = 1; 4025 for (i = 0; i < len; i++) { 4026 c = _addcarry_u64(c, a[i], ~b[i], &tmp); 4027 a[i] = tmp; 4028 } 4029 c = _addcarry_u64(c, carry, ~0, &tmp); 4030 return tmp; 4031 } 4032 4033 // Multiply (unsigned) Long A by Long B, accumulating the double- 4034 // length result into the accumulator formed of T0, T1, and T2. 4035 #define MACC(A, B, T0, T1, T2) \ 4036 do { \ 4037 julong hi, lo; \ 4038 lo = _umul128(A, B, &hi); \ 4039 unsigned char c = _addcarry_u64(0, lo, T0, &T0); \ 4040 c = _addcarry_u64(c, hi, T1, &T1); \ 4041 _addcarry_u64(c, T2, 0, &T2); \ 4042 } while(0) 4043 4044 // As above, but add twice the double-length result into the 4045 // accumulator. 4046 #define MACC2(A, B, T0, T1, T2) \ 4047 do { \ 4048 julong hi, lo; \ 4049 lo = _umul128(A, B, &hi); \ 4050 unsigned char c = _addcarry_u64(0, lo, T0, &T0); \ 4051 c = _addcarry_u64(c, hi, T1, &T1); \ 4052 _addcarry_u64(c, T2, 0, &T2); \ 4053 c = _addcarry_u64(0, lo, T0, &T0); \ 4054 c = _addcarry_u64(c, hi, T1, &T1); \ 4055 _addcarry_u64(c, T2, 0, &T2); \ 4056 } while(0) 4057 4058 #endif // defined(_WINDOWS) && _MSC_VER >= 1910 4059 #endif // defined(_WINDOWS) 4060 4061 #if !(defined(_WINDOWS) && _MSC_VER < 1910) 4062 4063 // Fast Montgomery multiplication. The derivation of the algorithm is 4064 // in A Cryptographic Library for the Motorola DSP56000, 4065 // Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237. 4066 4067 static void NOINLINE 4068 montgomery_multiply(julong a[], julong b[], julong n[], 4069 julong m[], julong inv, int len) { 4070 julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator 4071 int i; 4072 4073 assert(inv * n[0] == ULLONG_MAX, "broken inverse in Montgomery multiply"); 4074 4075 for (i = 0; i < len; i++) { 4076 int j; 4077 for (j = 0; j < i; j++) { 4078 MACC(a[j], b[i-j], t0, t1, t2); 4079 MACC(m[j], n[i-j], t0, t1, t2); 4080 } 4081 MACC(a[i], b[0], t0, t1, t2); 4082 m[i] = t0 * inv; 4083 MACC(m[i], n[0], t0, t1, t2); 4084 4085 assert(t0 == 0, "broken Montgomery multiply"); 4086 4087 t0 = t1; t1 = t2; t2 = 0; 4088 } 4089 4090 for (i = len; i < 2*len; i++) { 4091 int j; 4092 for (j = i-len+1; j < len; j++) { 4093 MACC(a[j], b[i-j], t0, t1, t2); 4094 MACC(m[j], n[i-j], t0, t1, t2); 4095 } 4096 m[i-len] = t0; 4097 t0 = t1; t1 = t2; t2 = 0; 4098 } 4099 4100 while (t0) 4101 t0 = sub(m, n, t0, len); 4102 } 4103 4104 // Fast Montgomery squaring. This uses asymptotically 25% fewer 4105 // multiplies so it should be up to 25% faster than Montgomery 4106 // multiplication. However, its loop control is more complex and it 4107 // may actually run slower on some machines. 4108 4109 static void NOINLINE 4110 montgomery_square(julong a[], julong n[], 4111 julong m[], julong inv, int len) { 4112 julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator 4113 int i; 4114 4115 assert(inv * n[0] == ULLONG_MAX, "broken inverse in Montgomery square"); 4116 4117 for (i = 0; i < len; i++) { 4118 int j; 4119 int end = (i+1)/2; 4120 for (j = 0; j < end; j++) { 4121 MACC2(a[j], a[i-j], t0, t1, t2); 4122 MACC(m[j], n[i-j], t0, t1, t2); 4123 } 4124 if ((i & 1) == 0) { 4125 MACC(a[j], a[j], t0, t1, t2); 4126 } 4127 for (; j < i; j++) { 4128 MACC(m[j], n[i-j], t0, t1, t2); 4129 } 4130 m[i] = t0 * inv; 4131 MACC(m[i], n[0], t0, t1, t2); 4132 4133 assert(t0 == 0, "broken Montgomery square"); 4134 4135 t0 = t1; t1 = t2; t2 = 0; 4136 } 4137 4138 for (i = len; i < 2*len; i++) { 4139 int start = i-len+1; 4140 int end = start + (len - start)/2; 4141 int j; 4142 for (j = start; j < end; j++) { 4143 MACC2(a[j], a[i-j], t0, t1, t2); 4144 MACC(m[j], n[i-j], t0, t1, t2); 4145 } 4146 if ((i & 1) == 0) { 4147 MACC(a[j], a[j], t0, t1, t2); 4148 } 4149 for (; j < len; j++) { 4150 MACC(m[j], n[i-j], t0, t1, t2); 4151 } 4152 m[i-len] = t0; 4153 t0 = t1; t1 = t2; t2 = 0; 4154 } 4155 4156 while (t0) 4157 t0 = sub(m, n, t0, len); 4158 } 4159 4160 // Swap words in a longword. 4161 static julong swap(julong x) { 4162 return (x << 32) | (x >> 32); 4163 } 4164 4165 // Copy len longwords from s to d, word-swapping as we go. The 4166 // destination array is reversed. 4167 static void reverse_words(julong *s, julong *d, int len) { 4168 d += len; 4169 while(len-- > 0) { 4170 d--; 4171 *d = swap(*s); 4172 s++; 4173 } 4174 } 4175 4176 // The threshold at which squaring is advantageous was determined 4177 // experimentally on an i7-3930K (Ivy Bridge) CPU @ 3.5GHz. 4178 #define MONTGOMERY_SQUARING_THRESHOLD 64 4179 4180 void SharedRuntime::montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints, 4181 jint len, jlong inv, 4182 jint *m_ints) { 4183 assert(len % 2 == 0, "array length in montgomery_multiply must be even"); 4184 int longwords = len/2; 4185 4186 // Make very sure we don't use so much space that the stack might 4187 // overflow. 512 jints corresponds to an 16384-bit integer and 4188 // will use here a total of 8k bytes of stack space. 4189 int total_allocation = longwords * sizeof (julong) * 4; 4190 guarantee(total_allocation <= 8192, "must be"); 4191 julong *scratch = (julong *)alloca(total_allocation); 4192 4193 // Local scratch arrays 4194 julong 4195 *a = scratch + 0 * longwords, 4196 *b = scratch + 1 * longwords, 4197 *n = scratch + 2 * longwords, 4198 *m = scratch + 3 * longwords; 4199 4200 reverse_words((julong *)a_ints, a, longwords); 4201 reverse_words((julong *)b_ints, b, longwords); 4202 reverse_words((julong *)n_ints, n, longwords); 4203 4204 ::montgomery_multiply(a, b, n, m, (julong)inv, longwords); 4205 4206 reverse_words(m, (julong *)m_ints, longwords); 4207 } 4208 4209 void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints, 4210 jint len, jlong inv, 4211 jint *m_ints) { 4212 assert(len % 2 == 0, "array length in montgomery_square must be even"); 4213 int longwords = len/2; 4214 4215 // Make very sure we don't use so much space that the stack might 4216 // overflow. 512 jints corresponds to an 16384-bit integer and 4217 // will use here a total of 6k bytes of stack space. 4218 int total_allocation = longwords * sizeof (julong) * 3; 4219 guarantee(total_allocation <= 8192, "must be"); 4220 julong *scratch = (julong *)alloca(total_allocation); 4221 4222 // Local scratch arrays 4223 julong 4224 *a = scratch + 0 * longwords, 4225 *n = scratch + 1 * longwords, 4226 *m = scratch + 2 * longwords; 4227 4228 reverse_words((julong *)a_ints, a, longwords); 4229 reverse_words((julong *)n_ints, n, longwords); 4230 4231 //montgomery_square fails to pass BigIntegerTest on solaris amd64 4232 //on jdk7 and jdk8. 4233 #ifndef SOLARIS 4234 if (len >= MONTGOMERY_SQUARING_THRESHOLD) { 4235 #else 4236 if (0) { 4237 #endif 4238 ::montgomery_square(a, n, m, (julong)inv, longwords); 4239 } else { 4240 ::montgomery_multiply(a, a, n, m, (julong)inv, longwords); 4241 } 4242 4243 reverse_words(m, (julong *)m_ints, longwords); 4244 } 4245 4246 #endif // !(defined(_WINDOWS) && MSVC < VS2017) 4247 4248 #ifdef COMPILER2 4249 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame 4250 // 4251 //------------------------------generate_exception_blob--------------------------- 4252 // creates exception blob at the end 4253 // Using exception blob, this code is jumped from a compiled method. 4254 // (see emit_exception_handler in x86_64.ad file) 4255 // 4256 // Given an exception pc at a call we call into the runtime for the 4257 // handler in this method. This handler might merely restore state 4258 // (i.e. callee save registers) unwind the frame and jump to the 4259 // exception handler for the nmethod if there is no Java level handler 4260 // for the nmethod. 4261 // 4262 // This code is entered with a jmp. 4263 // 4264 // Arguments: 4265 // rax: exception oop 4266 // rdx: exception pc 4267 // 4268 // Results: 4269 // rax: exception oop 4270 // rdx: exception pc in caller or ??? 4271 // destination: exception handler of caller 4272 // 4273 // Note: the exception pc MUST be at a call (precise debug information) 4274 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved. 4275 // 4276 4277 void OptoRuntime::generate_exception_blob() { 4278 assert(!OptoRuntime::is_callee_saved_register(RDX_num), ""); 4279 assert(!OptoRuntime::is_callee_saved_register(RAX_num), ""); 4280 assert(!OptoRuntime::is_callee_saved_register(RCX_num), ""); 4281 4282 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); 4283 4284 // Allocate space for the code 4285 ResourceMark rm; 4286 // Setup code generation tools 4287 CodeBuffer buffer("exception_blob", 2048, 1024); 4288 MacroAssembler* masm = new MacroAssembler(&buffer); 4289 4290 4291 address start = __ pc(); 4292 4293 // Exception pc is 'return address' for stack walker 4294 __ push(rdx); 4295 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog 4296 4297 // Save callee-saved registers. See x86_64.ad. 4298 4299 // rbp is an implicitly saved callee saved register (i.e., the calling 4300 // convention will save/restore it in the prolog/epilog). Other than that 4301 // there are no callee save registers now that adapter frames are gone. 4302 4303 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); 4304 4305 // Store exception in Thread object. We cannot pass any arguments to the 4306 // handle_exception call, since we do not want to make any assumption 4307 // about the size of the frame where the exception happened in. 4308 // c_rarg0 is either rdi (Linux) or rcx (Windows). 4309 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax); 4310 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); 4311 4312 // This call does all the hard work. It checks if an exception handler 4313 // exists in the method. 4314 // If so, it returns the handler address. 4315 // If not, it prepares for stack-unwinding, restoring the callee-save 4316 // registers of the frame being removed. 4317 // 4318 // address OptoRuntime::handle_exception_C(JavaThread* thread) 4319 4320 // At a method handle call, the stack may not be properly aligned 4321 // when returning with an exception. 4322 address the_pc = __ pc(); 4323 __ set_last_Java_frame(noreg, noreg, the_pc); 4324 __ mov(c_rarg0, r15_thread); 4325 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack 4326 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); 4327 4328 // Set an oopmap for the call site. This oopmap will only be used if we 4329 // are unwinding the stack. Hence, all locations will be dead. 4330 // Callee-saved registers will be the same as the frame above (i.e., 4331 // handle_exception_stub), since they were restored when we got the 4332 // exception. 4333 4334 OopMapSet* oop_maps = new OopMapSet(); 4335 4336 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); 4337 4338 __ reset_last_Java_frame(false); 4339 4340 // Restore callee-saved registers 4341 4342 // rbp is an implicitly saved callee-saved register (i.e., the calling 4343 // convention will save restore it in prolog/epilog) Other than that 4344 // there are no callee save registers now that adapter frames are gone. 4345 4346 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt)); 4347 4348 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog 4349 __ pop(rdx); // No need for exception pc anymore 4350 4351 // rax: exception handler 4352 4353 // We have a handler in rax (could be deopt blob). 4354 __ mov(r8, rax); 4355 4356 // Get the exception oop 4357 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); 4358 // Get the exception pc in case we are deoptimized 4359 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); 4360 #ifdef ASSERT 4361 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD); 4362 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD); 4363 #endif 4364 // Clear the exception oop so GC no longer processes it as a root. 4365 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD); 4366 4367 // rax: exception oop 4368 // r8: exception handler 4369 // rdx: exception pc 4370 // Jump to handler 4371 4372 __ jmp(r8); 4373 4374 // Make sure all code is generated 4375 masm->flush(); 4376 4377 // Set exception blob 4378 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); 4379 } 4380 #endif // COMPILER2