rev 9211 : 8140645: Recent Developments for AIX
Summary: Port recent developments from SAP for AIX to the OpenJDK

   1 //
   2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright 2012, 2015 SAP AG. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 
 258 // ----------------------------
 259 // Specify priority of register selection within phases of register
 260 // allocation. Highest priority is first. A useful heuristic is to
 261 // give registers a low priority when they are required by machine
 262 // instructions, like EAX and EDX on I486, and choose no-save registers
 263 // before save-on-call, & save-on-call before save-on-entry. Registers
 264 // which participate in fixed calling sequences should come last.
 265 // Registers which are used as pairs must fall on an even boundary.
 266 
 267 // It's worth about 1% on SPEC geomean to get this right.
 268 
 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 271 // R3_num. Therefore, R3_num may not be (and in reality is not)
 272 // the same as R3->encoding()! Furthermore, we cannot make any
 273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 274 // Additionally, the function
 275 //   static enum RC rc_class(OptoReg::Name reg )
 276 // maps a given <register>_num value to its chunk type (except for flags)
 277 // and its current implementation relies on chunk0 and chunk1 having a
 278 // size of 64 each.
 279 
 280 // If you change this allocation class, please have a look at the
 281 // default values for the parameters RoundRobinIntegerRegIntervalStart
 282 // and RoundRobinFloatRegIntervalStart
 283 
 284 alloc_class chunk0 (
 285   // Chunk0 contains *all* 64 integer registers halves.
 286 
 287   // "non-volatile" registers
 288   R14, R14_H,
 289   R15, R15_H,
 290   R17, R17_H,
 291   R18, R18_H,
 292   R19, R19_H,
 293   R20, R20_H,
 294   R21, R21_H,
 295   R22, R22_H,
 296   R23, R23_H,
 297   R24, R24_H,
 298   R25, R25_H,
 299   R26, R26_H,
 300   R27, R27_H,
 301   R28, R28_H,
 302   R29, R29_H,
 303   R30, R30_H,
 304   R31, R31_H,
 305 
 306   // scratch/special registers
 307   R11, R11_H,
 308   R12, R12_H,
 309 
 310   // argument registers
 311   R10, R10_H,
 312   R9,  R9_H,
 313   R8,  R8_H,
 314   R7,  R7_H,
 315   R6,  R6_H,
 316   R5,  R5_H,
 317   R4,  R4_H,
 318   R3,  R3_H,
 319 
 320   // special registers, not available for allocation
 321   R16, R16_H,     // R16_thread
 322   R13, R13_H,     // system thread id
 323   R2,  R2_H,      // may be used for TOC
 324   R1,  R1_H,      // SP
 325   R0,  R0_H       // R0 (scratch)
 326 );
 327 
 328 // If you change this allocation class, please have a look at the
 329 // default values for the parameters RoundRobinIntegerRegIntervalStart
 330 // and RoundRobinFloatRegIntervalStart
 331 
 332 alloc_class chunk1 (
 333   // Chunk1 contains *all* 64 floating-point registers halves.
 334 
 335   // scratch register
 336   F0,  F0_H,
 337 
 338   // argument registers
 339   F13, F13_H,
 340   F12, F12_H,
 341   F11, F11_H,
 342   F10, F10_H,
 343   F9,  F9_H,
 344   F8,  F8_H,
 345   F7,  F7_H,
 346   F6,  F6_H,
 347   F5,  F5_H,
 348   F4,  F4_H,
 349   F3,  F3_H,
 350   F2,  F2_H,
 351   F1,  F1_H,
 352 
 353   // non-volatile registers
 354   F14, F14_H,
 355   F15, F15_H,
 356   F16, F16_H,
 357   F17, F17_H,
 358   F18, F18_H,
 359   F19, F19_H,
 360   F20, F20_H,
 361   F21, F21_H,
 362   F22, F22_H,
 363   F23, F23_H,
 364   F24, F24_H,
 365   F25, F25_H,
 366   F26, F26_H,
 367   F27, F27_H,
 368   F28, F28_H,
 369   F29, F29_H,
 370   F30, F30_H,
 371   F31, F31_H
 372 );
 373 
 374 alloc_class chunk2 (
 375   // Chunk2 contains *all* 8 condition code registers.
 376 
 377   CCR0,
 378   CCR1,
 379   CCR2,
 380   CCR3,
 381   CCR4,
 382   CCR5,
 383   CCR6,
 384   CCR7
 385 );
 386 
 387 alloc_class chunk3 (
 388   // special registers
 389   // These registers are not allocated, but used for nodes generated by postalloc expand.
 390   SR_XER,
 391   SR_LR,
 392   SR_CTR,
 393   SR_VRSAVE,
 394   SR_SPEFSCR,
 395   SR_PPR
 396 );
 397 
 398 //-------Architecture Description Register Classes-----------------------
 399 
 400 // Several register classes are automatically defined based upon
 401 // information in this architecture description.
 402 
 403 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 404 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 407 //
 408 
 409 // ----------------------------
 410 // 32 Bit Register Classes
 411 // ----------------------------
 412 
 413 // We specify registers twice, once as read/write, and once read-only.
 414 // We use the read-only registers for source operands. With this, we
 415 // can include preset read only registers in this class, as a hard-coded
 416 // '0'-register. (We used to simulate this on ppc.)
 417 
 418 // 32 bit registers that can be read and written i.e. these registers
 419 // can be dest (or src) of normal instructions.
 420 reg_class bits32_reg_rw(
 421 /*R0*/              // R0
 422 /*R1*/              // SP
 423   R2,               // TOC
 424   R3,
 425   R4,
 426   R5,
 427   R6,
 428   R7,
 429   R8,
 430   R9,
 431   R10,
 432   R11,
 433   R12,
 434 /*R13*/             // system thread id
 435   R14,
 436   R15,
 437 /*R16*/             // R16_thread
 438   R17,
 439   R18,
 440   R19,
 441   R20,
 442   R21,
 443   R22,
 444   R23,
 445   R24,
 446   R25,
 447   R26,
 448   R27,
 449   R28,
 450 /*R29,*/             // global TOC
 451   R30,
 452   R31
 453 );
 454 
 455 // 32 bit registers that can only be read i.e. these registers can
 456 // only be src of all instructions.
 457 reg_class bits32_reg_ro(
 458 /*R0*/              // R0
 459 /*R1*/              // SP
 460   R2                // TOC
 461   R3,
 462   R4,
 463   R5,
 464   R6,
 465   R7,
 466   R8,
 467   R9,
 468   R10,
 469   R11,
 470   R12,
 471 /*R13*/             // system thread id
 472   R14,
 473   R15,
 474 /*R16*/             // R16_thread
 475   R17,
 476   R18,
 477   R19,
 478   R20,
 479   R21,
 480   R22,
 481   R23,
 482   R24,
 483   R25,
 484   R26,
 485   R27,
 486   R28,
 487 /*R29,*/
 488   R30,
 489   R31
 490 );
 491 
 492 reg_class rscratch1_bits32_reg(R11);
 493 reg_class rscratch2_bits32_reg(R12);
 494 reg_class rarg1_bits32_reg(R3);
 495 reg_class rarg2_bits32_reg(R4);
 496 reg_class rarg3_bits32_reg(R5);
 497 reg_class rarg4_bits32_reg(R6);
 498 
 499 // ----------------------------
 500 // 64 Bit Register Classes
 501 // ----------------------------
 502 // 64-bit build means 64-bit pointers means hi/lo pairs
 503 
 504 reg_class rscratch1_bits64_reg(R11_H, R11);
 505 reg_class rscratch2_bits64_reg(R12_H, R12);
 506 reg_class rarg1_bits64_reg(R3_H, R3);
 507 reg_class rarg2_bits64_reg(R4_H, R4);
 508 reg_class rarg3_bits64_reg(R5_H, R5);
 509 reg_class rarg4_bits64_reg(R6_H, R6);
 510 // Thread register, 'written' by tlsLoadP, see there.
 511 reg_class thread_bits64_reg(R16_H, R16);
 512 
 513 reg_class r19_bits64_reg(R19_H, R19);
 514 
 515 // 64 bit registers that can be read and written i.e. these registers
 516 // can be dest (or src) of normal instructions.
 517 reg_class bits64_reg_rw(
 518 /*R0_H,  R0*/     // R0
 519 /*R1_H,  R1*/     // SP
 520   R2_H,  R2,      // TOC
 521   R3_H,  R3,
 522   R4_H,  R4,
 523   R5_H,  R5,
 524   R6_H,  R6,
 525   R7_H,  R7,
 526   R8_H,  R8,
 527   R9_H,  R9,
 528   R10_H, R10,
 529   R11_H, R11,
 530   R12_H, R12,
 531 /*R13_H, R13*/   // system thread id
 532   R14_H, R14,
 533   R15_H, R15,
 534 /*R16_H, R16*/   // R16_thread
 535   R17_H, R17,
 536   R18_H, R18,
 537   R19_H, R19,
 538   R20_H, R20,
 539   R21_H, R21,
 540   R22_H, R22,
 541   R23_H, R23,
 542   R24_H, R24,
 543   R25_H, R25,
 544   R26_H, R26,
 545   R27_H, R27,
 546   R28_H, R28,
 547 /*R29_H, R29,*/
 548   R30_H, R30,
 549   R31_H, R31
 550 );
 551 
 552 // 64 bit registers used excluding r2, r11 and r12
 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 554 // r2, r11 and r12 internally.
 555 reg_class bits64_reg_leaf_call(
 556 /*R0_H,  R0*/     // R0
 557 /*R1_H,  R1*/     // SP
 558 /*R2_H,  R2*/     // TOC
 559   R3_H,  R3,
 560   R4_H,  R4,
 561   R5_H,  R5,
 562   R6_H,  R6,
 563   R7_H,  R7,
 564   R8_H,  R8,
 565   R9_H,  R9,
 566   R10_H, R10,
 567 /*R11_H, R11*/
 568 /*R12_H, R12*/
 569 /*R13_H, R13*/   // system thread id
 570   R14_H, R14,
 571   R15_H, R15,
 572 /*R16_H, R16*/   // R16_thread
 573   R17_H, R17,
 574   R18_H, R18,
 575   R19_H, R19,
 576   R20_H, R20,
 577   R21_H, R21,
 578   R22_H, R22,
 579   R23_H, R23,
 580   R24_H, R24,
 581   R25_H, R25,
 582   R26_H, R26,
 583   R27_H, R27,
 584   R28_H, R28,
 585 /*R29_H, R29,*/
 586   R30_H, R30,
 587   R31_H, R31
 588 );
 589 
 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 591 // which uses r19 as inline cache internally and expanded LeafCall which uses
 592 // r2, r11 and r12 internally.
 593 reg_class bits64_constant_table_base(
 594 /*R0_H,  R0*/     // R0
 595 /*R1_H,  R1*/     // SP
 596 /*R2_H,  R2*/     // TOC
 597   R3_H,  R3,
 598   R4_H,  R4,
 599   R5_H,  R5,
 600   R6_H,  R6,
 601   R7_H,  R7,
 602   R8_H,  R8,
 603   R9_H,  R9,
 604   R10_H, R10,
 605 /*R11_H, R11*/
 606 /*R12_H, R12*/
 607 /*R13_H, R13*/   // system thread id
 608   R14_H, R14,
 609   R15_H, R15,
 610 /*R16_H, R16*/   // R16_thread
 611   R17_H, R17,
 612   R18_H, R18,
 613 /*R19_H, R19*/
 614   R20_H, R20,
 615   R21_H, R21,
 616   R22_H, R22,
 617   R23_H, R23,
 618   R24_H, R24,
 619   R25_H, R25,
 620   R26_H, R26,
 621   R27_H, R27,
 622   R28_H, R28,
 623 /*R29_H, R29,*/
 624   R30_H, R30,
 625   R31_H, R31
 626 );
 627 
 628 // 64 bit registers that can only be read i.e. these registers can
 629 // only be src of all instructions.
 630 reg_class bits64_reg_ro(
 631 /*R0_H,  R0*/     // R0
 632   R1_H,  R1,
 633   R2_H,  R2,       // TOC
 634   R3_H,  R3,
 635   R4_H,  R4,
 636   R5_H,  R5,
 637   R6_H,  R6,
 638   R7_H,  R7,
 639   R8_H,  R8,
 640   R9_H,  R9,
 641   R10_H, R10,
 642   R11_H, R11,
 643   R12_H, R12,
 644 /*R13_H, R13*/   // system thread id
 645   R14_H, R14,
 646   R15_H, R15,
 647   R16_H, R16,    // R16_thread
 648   R17_H, R17,
 649   R18_H, R18,
 650   R19_H, R19,
 651   R20_H, R20,
 652   R21_H, R21,
 653   R22_H, R22,
 654   R23_H, R23,
 655   R24_H, R24,
 656   R25_H, R25,
 657   R26_H, R26,
 658   R27_H, R27,
 659   R28_H, R28,
 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 661   R30_H, R30,
 662   R31_H, R31
 663 );
 664 
 665 
 666 // ----------------------------
 667 // Special Class for Condition Code Flags Register
 668 
 669 reg_class int_flags(
 670 /*CCR0*/             // scratch
 671 /*CCR1*/             // scratch
 672 /*CCR2*/             // nv!
 673 /*CCR3*/             // nv!
 674 /*CCR4*/             // nv!
 675   CCR5,
 676   CCR6,
 677   CCR7
 678 );
 679 
 680 reg_class int_flags_ro(
 681   CCR0,
 682   CCR1,
 683   CCR2,
 684   CCR3,
 685   CCR4,
 686   CCR5,
 687   CCR6,
 688   CCR7
 689 );
 690 
 691 reg_class int_flags_CR0(CCR0);
 692 reg_class int_flags_CR1(CCR1);
 693 reg_class int_flags_CR6(CCR6);
 694 reg_class ctr_reg(SR_CTR);
 695 
 696 // ----------------------------
 697 // Float Register Classes
 698 // ----------------------------
 699 
 700 reg_class flt_reg(
 701 /*F0*/              // scratch
 702   F1,
 703   F2,
 704   F3,
 705   F4,
 706   F5,
 707   F6,
 708   F7,
 709   F8,
 710   F9,
 711   F10,
 712   F11,
 713   F12,
 714   F13,
 715   F14,              // nv!
 716   F15,              // nv!
 717   F16,              // nv!
 718   F17,              // nv!
 719   F18,              // nv!
 720   F19,              // nv!
 721   F20,              // nv!
 722   F21,              // nv!
 723   F22,              // nv!
 724   F23,              // nv!
 725   F24,              // nv!
 726   F25,              // nv!
 727   F26,              // nv!
 728   F27,              // nv!
 729   F28,              // nv!
 730   F29,              // nv!
 731   F30,              // nv!
 732   F31               // nv!
 733 );
 734 
 735 // Double precision float registers have virtual `high halves' that
 736 // are needed by the allocator.
 737 reg_class dbl_reg(
 738 /*F0,  F0_H*/     // scratch
 739   F1,  F1_H,
 740   F2,  F2_H,
 741   F3,  F3_H,
 742   F4,  F4_H,
 743   F5,  F5_H,
 744   F6,  F6_H,
 745   F7,  F7_H,
 746   F8,  F8_H,
 747   F9,  F9_H,
 748   F10, F10_H,
 749   F11, F11_H,
 750   F12, F12_H,
 751   F13, F13_H,
 752   F14, F14_H,    // nv!
 753   F15, F15_H,    // nv!
 754   F16, F16_H,    // nv!
 755   F17, F17_H,    // nv!
 756   F18, F18_H,    // nv!
 757   F19, F19_H,    // nv!
 758   F20, F20_H,    // nv!
 759   F21, F21_H,    // nv!
 760   F22, F22_H,    // nv!
 761   F23, F23_H,    // nv!
 762   F24, F24_H,    // nv!
 763   F25, F25_H,    // nv!
 764   F26, F26_H,    // nv!
 765   F27, F27_H,    // nv!
 766   F28, F28_H,    // nv!
 767   F29, F29_H,    // nv!
 768   F30, F30_H,    // nv!
 769   F31, F31_H     // nv!
 770 );
 771 
 772  %}
 773 
 774 //----------DEFINITION BLOCK---------------------------------------------------
 775 // Define name --> value mappings to inform the ADLC of an integer valued name
 776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 777 // Format:
 778 //        int_def  <name>         ( <int_value>, <expression>);
 779 // Generated Code in ad_<arch>.hpp
 780 //        #define  <name>   (<expression>)
 781 //        // value == <int_value>
 782 // Generated code in ad_<arch>.cpp adlc_verification()
 783 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 784 //
 785 definitions %{
 786   // The default cost (of an ALU instruction).
 787   int_def DEFAULT_COST_LOW        (     30,      30);
 788   int_def DEFAULT_COST            (    100,     100);
 789   int_def HUGE_COST               (1000000, 1000000);
 790 
 791   // Memory refs
 792   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 793   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 794 
 795   // Branches are even more expensive.
 796   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 797   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 798 %}
 799 
 800 
 801 //----------SOURCE BLOCK-------------------------------------------------------
 802 // This is a block of C++ code which provides values, functions, and
 803 // definitions necessary in the rest of the architecture description.
 804 source_hpp %{
 805   // Header information of the source block.
 806   // Method declarations/definitions which are used outside
 807   // the ad-scope can conveniently be defined here.
 808   //
 809   // To keep related declarations/definitions/uses close together,
 810   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 811 
 812   // Returns true if Node n is followed by a MemBar node that
 813   // will do an acquire. If so, this node must not do the acquire
 814   // operation.
 815   bool followed_by_acquire(const Node *n);
 816 %}
 817 
 818 source %{
 819 
 820 // Optimize load-acquire.
 821 //
 822 // Check if acquire is unnecessary due to following operation that does
 823 // acquire anyways.
 824 // Walk the pattern:
 825 //
 826 //      n: Load.acq
 827 //           |
 828 //      MemBarAcquire
 829 //       |         |
 830 //  Proj(ctrl)  Proj(mem)
 831 //       |         |
 832 //   MemBarRelease/Volatile
 833 //
 834 bool followed_by_acquire(const Node *load) {
 835   assert(load->is_Load(), "So far implemented only for loads.");
 836 
 837   // Find MemBarAcquire.
 838   const Node *mba = NULL;
 839   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
 840     const Node *out = load->fast_out(i);
 841     if (out->Opcode() == Op_MemBarAcquire) {
 842       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
 843       mba = out;
 844       break;
 845     }
 846   }
 847   if (!mba) return false;
 848 
 849   // Find following MemBar node.
 850   //
 851   // The following node must be reachable by control AND memory
 852   // edge to assure no other operations are in between the two nodes.
 853   //
 854   // So first get the Proj node, mem_proj, to use it to iterate forward.
 855   Node *mem_proj = NULL;
 856   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
 857     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found
 858     assert(mem_proj->is_Proj(), "only projections here");
 859     ProjNode *proj = mem_proj->as_Proj();
 860     if (proj->_con == TypeFunc::Memory &&
 861         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
 862       break;
 863   }
 864   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
 865 
 866   // Search MemBar behind Proj. If there are other memory operations
 867   // behind the Proj we lost.
 868   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
 869     Node *x = mem_proj->fast_out(j);
 870     // Proj might have an edge to a store or load node which precedes the membar.
 871     if (x->is_Mem()) return false;
 872 
 873     // On PPC64 release and volatile are implemented by an instruction
 874     // that also has acquire semantics. I.e. there is no need for an
 875     // acquire before these.
 876     int xop = x->Opcode();
 877     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
 878       // Make sure we're not missing Call/Phi/MergeMem by checking
 879       // control edges. The control edge must directly lead back
 880       // to the MemBarAcquire
 881       Node *ctrl_proj = x->in(0);
 882       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
 883         return true;
 884       }
 885     }
 886   }
 887 
 888   return false;
 889 }
 890 
 891 #define __ _masm.
 892 
 893 // Tertiary op of a LoadP or StoreP encoding.
 894 #define REGP_OP true
 895 
 896 // ****************************************************************************
 897 
 898 // REQUIRED FUNCTIONALITY
 899 
 900 // !!!!! Special hack to get all type of calls to specify the byte offset
 901 //       from the start of the call to the point where the return address
 902 //       will point.
 903 
 904 // PPC port: Removed use of lazy constant construct.
 905 
 906 int MachCallStaticJavaNode::ret_addr_offset() {
 907   // It's only a single branch-and-link instruction.
 908   return 4;
 909 }
 910 
 911 int MachCallDynamicJavaNode::ret_addr_offset() {
 912   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
 913   // postalloc expanded calls if we use inline caches and do not update method data.
 914   if (UseInlineCaches)
 915     return 4;
 916 
 917   int vtable_index = this->_vtable_index;
 918   if (vtable_index < 0) {
 919     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
 920     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 921     return 12;
 922   } else {
 923     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 924     return 24;
 925   }
 926 }
 927 
 928 int MachCallRuntimeNode::ret_addr_offset() {
 929 #if defined(ABI_ELFv2)
 930   return 28;
 931 #else
 932   return 40;
 933 #endif
 934 }
 935 
 936 //=============================================================================
 937 
 938 // condition code conversions
 939 
 940 static int cc_to_boint(int cc) {
 941   return Assembler::bcondCRbiIs0 | (cc & 8);
 942 }
 943 
 944 static int cc_to_inverse_boint(int cc) {
 945   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
 946 }
 947 
 948 static int cc_to_biint(int cc, int flags_reg) {
 949   return (flags_reg << 2) | (cc & 3);
 950 }
 951 
 952 //=============================================================================
 953 
 954 // Compute padding required for nodes which need alignment. The padding
 955 // is the number of bytes (not instructions) which will be inserted before
 956 // the instruction. The padding must match the size of a NOP instruction.
 957 
 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
 959   return (3*4-current_offset)&31;
 960 }
 961 
 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
 963   return (2*4-current_offset)&31;
 964 }
 965 
 966 int string_indexOf_immNode::compute_padding(int current_offset) const {
 967   return (3*4-current_offset)&31;
 968 }
 969 
 970 int string_indexOfNode::compute_padding(int current_offset) const {
 971   return (1*4-current_offset)&31;
 972 }
 973 
 974 int string_compareNode::compute_padding(int current_offset) const {
 975   return (4*4-current_offset)&31;
 976 }
 977 
 978 int string_equals_immNode::compute_padding(int current_offset) const {
 979   if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
 980   return (2*4-current_offset)&31;
 981 }
 982 
 983 int string_equalsNode::compute_padding(int current_offset) const {
 984   return (7*4-current_offset)&31;
 985 }
 986 
 987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
 988   return (2*4-current_offset)&31;
 989 }
 990 
 991 //=============================================================================
 992 
 993 // Indicate if the safepoint node needs the polling page as an input.
 994 bool SafePointNode::needs_polling_address_input() {
 995   // The address is loaded from thread by a seperate node.
 996   return true;
 997 }
 998 
 999 //=============================================================================
1000 
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003   MacroAssembler _masm(&cbuf);
1004   __ illtrap();
1005 }
1006 
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009   st->print("BREAKPOINT");
1010 }
1011 #endif
1012 
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014   emit_break(cbuf);
1015 }
1016 
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018   return MachNode::size(ra_);
1019 }
1020 
1021 //=============================================================================
1022 
1023 void emit_nop(CodeBuffer &cbuf) {
1024   MacroAssembler _masm(&cbuf);
1025   __ nop();
1026 }
1027 
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029   *((int*)(cbuf.insts_end())) = value;
1030   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032 
1033 //=============================================================================
1034 
1035 %} // interrupt source
1036 
1037 source_hpp %{ // Header information of the source block.
1038 
1039 //--------------------------------------------------------------
1040 //---<  Used for optimization in Compile::Shorten_branches  >---
1041 //--------------------------------------------------------------
1042 
1043 const uint trampoline_stub_size     =  6 * BytesPerInstWord;
1044 
1045 class CallStubImpl {
1046 
1047  public:
1048 
1049   // Emit call stub, compiled java to interpreter.
1050   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051 
1052   // Size of call trampoline stub.
1053   // This doesn't need to be accurate to the byte, but it
1054   // must be larger than or equal to the real size of the stub.
1055   static uint size_call_trampoline() {
1056     return trampoline_stub_size;
1057   }
1058 
1059   // number of relocations needed by a call trampoline stub
1060   static uint reloc_call_trampoline() {
1061     return 5;
1062   }
1063 
1064 };
1065 
1066 %} // end source_hpp
1067 
1068 source %{
1069 
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 //   branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 //   load the call target from the constant pool
1079 //   branch via CTR (LR/link still points to the call-site above)
1080 
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082   // Start the stub.
1083   address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084   if (stub == NULL) {
1085     ciEnv::current()->record_failure("CodeCache is full");
1086     return;
1087   }
1088 
1089   // For java_to_interp stubs we use R11_scratch1 as scratch register
1090   // and in call trampoline stubs we use R12_scratch2. This way we
1091   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092   Register reg_scratch = R12_scratch2;
1093 
1094   // Create a trampoline stub relocation which relates this trampoline stub
1095   // with the call instruction at insts_call_instruction_offset in the
1096   // instructions code-section.
1097   __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098   const int stub_start_offset = __ offset();
1099 
1100   // Now, create the trampoline stub's code:
1101   // - load the TOC
1102   // - load the call target from the constant pool
1103   // - call
1104   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105   __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106   __ mtctr(reg_scratch);
1107   __ bctr();
1108 
1109   const address stub_start_addr = __ addr_at(stub_start_offset);
1110 
1111   // FIXME: Assert that the trampoline stub can be identified and patched.
1112 
1113   // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114   assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115          "encoded offset into the constant pool must match");
1116   // Trampoline_stub_size should be good.
1117   assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118   assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119 
1120   // End the stub.
1121   __ end_a_stub();
1122 }
1123 
1124 //=============================================================================
1125 
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 //   branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 //   load the call target from the constant pool
1135 //   branch via CTR (LR/link still points to the call-site above)
1136 //
1137 
1138 typedef struct {
1139   int insts_call_instruction_offset;
1140   int ret_addr_offset;
1141 } EmitCallOffsets;
1142 
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149   EmitCallOffsets offsets = { -1, -1 };
1150   const int start_offset = __ offset();
1151   offsets.insts_call_instruction_offset = __ offset();
1152 
1153   // No entry point given, use the current pc.
1154   if (entry_point == NULL) entry_point = __ pc();
1155 
1156   if (!Compile::current()->in_scratch_emit_size()) {
1157     // Put the entry point as a constant into the constant pool.
1158     const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1159     const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160 
1161     // Emit the trampoline stub which will be related to the branch-and-link below.
1162     CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163     if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1164     __ relocate(rtype);
1165   }
1166 
1167   // Note: At this point we do not have the address of the trampoline
1168   // stub, and the entry point might be too far away for bl, so __ pc()
1169   // serves as dummy and the bl will be patched later.
1170   __ bl((address) __ pc());
1171 
1172   offsets.ret_addr_offset = __ offset() - start_offset;
1173 
1174   return offsets;
1175 }
1176 
1177 //=============================================================================
1178 
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180 
1181 static inline jlong replicate_immF(float con) {
1182   // Replicate float con 2 times and pack into vector.
1183   int val = *((int*)&con);
1184   jlong lval = val;
1185   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186   return lval;
1187 }
1188 
1189 //=============================================================================
1190 
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193   return 0;  // absolute addressing, no offset
1194 }
1195 
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198   iRegPdstOper *op_dst = new iRegPdstOper();
1199   MachNode *m1 = new loadToc_hiNode();
1200   MachNode *m2 = new loadToc_loNode();
1201 
1202   m1->add_req(NULL);
1203   m2->add_req(NULL, m1);
1204   m1->_opnds[0] = op_dst;
1205   m2->_opnds[0] = op_dst;
1206   m2->_opnds[1] = op_dst;
1207   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209   nodes->push(m1);
1210   nodes->push(m2);
1211 }
1212 
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214   // Is postalloc expanded.
1215   ShouldNotReachHere();
1216 }
1217 
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219   return 0;
1220 }
1221 
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227 
1228 //=============================================================================
1229 
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232   Compile* C = ra_->C;
1233   const long framesize = C->frame_slots() << LogBytesPerInt;
1234 
1235   st->print("PROLOG\n\t");
1236   if (C->need_stack_bang(framesize)) {
1237     st->print("stack_overflow_check\n\t");
1238   }
1239 
1240   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241     st->print("save return pc\n\t");
1242     st->print("push frame %ld\n\t", -framesize);
1243   }
1244 }
1245 #endif
1246 
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1256                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257                 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1259                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1261                   C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1264                   Unimplemented();                                                    \
1265                 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1267                   Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1269                   Unimplemented()
1270 #endif
1271 
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273   Compile* C = ra_->C;
1274   MacroAssembler _masm(&cbuf);
1275 
1276   const long framesize = C->frame_size_in_bytes();
1277   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278 
1279   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1280 
1281   const Register return_pc            = R20; // Must match return_addr() in frame section.
1282   const Register callers_sp           = R21;
1283   const Register push_frame_temp      = R22;
1284   const Register toc_temp             = R23;
1285   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286 
1287   if (method_is_frameless) {
1288     // Add nop at beginning of all frameless methods to prevent any
1289     // oop instructions from getting overwritten by make_not_entrant
1290     // (patching attempt would fail).
1291     ___(nop) nop();
1292   } else {
1293     // Get return pc.
1294     ___(mflr) mflr(return_pc);
1295   }
1296 
1297   // Calls to C2R adapters often do not accept exceptional returns.
1298   // We require that their callers must bang for them. But be
1299   // careful, because some VM calls (such as call site linkage) can
1300   // use several kilobytes of stack. But the stack safety zone should
1301   // account for that. See bugs 4446381, 4468289, 4497237.
1302 
1303   int bangsize = C->bang_size_in_bytes();
1304   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306     // Unfortunately we cannot use the function provided in
1307     // assembler.cpp as we have to emulate the pipes. So I had to
1308     // insert the code of generate_stack_overflow_check(), see
1309     // assembler.cpp for some illuminative comments.
1310     const int page_size = os::vm_page_size();
1311     int bang_end = StackShadowPages * page_size;
1312 
1313     // This is how far the previous frame's stack banging extended.
1314     const int bang_end_safe = bang_end;
1315 
1316     if (bangsize > page_size) {
1317       bang_end += bangsize;
1318     }
1319 
1320     int bang_offset = bang_end_safe;
1321 
1322     while (bang_offset <= bang_end) {
1323       // Need at least one stack bang at end of shadow zone.
1324 
1325       // Again I had to copy code, this time from assembler_ppc.cpp,
1326       // bang_stack_with_offset - see there for comments.
1327 
1328       // Stack grows down, caller passes positive offset.
1329       assert(bang_offset > 0, "must bang with positive offset");
1330 
1331       long stdoffset = -bang_offset;
1332 
1333       if (Assembler::is_simm(stdoffset, 16)) {
1334         // Signed 16 bit offset, a simple std is ok.
1335         if (UseLoadInstructionsForStackBangingPPC64) {
1336           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1337         } else {
1338           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339         }
1340       } else if (Assembler::is_simm(stdoffset, 31)) {
1341         // Use largeoffset calculations for addis & ld/std.
1342         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344 
1345         Register tmp = R11;
1346         ___(addis) addis(tmp, R1_SP, hi);
1347         if (UseLoadInstructionsForStackBangingPPC64) {
1348           ___(ld) ld(R0, lo, tmp);
1349         } else {
1350           ___(std) std(R0, lo, tmp);
1351         }
1352       } else {
1353         ShouldNotReachHere();
1354       }
1355 
1356       bang_offset += page_size;
1357     }
1358     // R11 trashed
1359   } // C->need_stack_bang(framesize) && UseStackBanging
1360 
1361   unsigned int bytes = (unsigned int)framesize;
1362   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363   ciMethod *currMethod = C->method();
1364 
1365   // Optimized version for most common case.
1366   if (UsePower6SchedulerPPC64 &&
1367       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368       !(false /* ConstantsALot TODO: PPC port*/)) {
1369     ___(or) mr(callers_sp, R1_SP);
1370     ___(std) std(return_pc, _abi(lr), R1_SP);
1371     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372     return;
1373   }
1374 
1375   if (!method_is_frameless) {
1376     // Get callers sp.
1377     ___(or) mr(callers_sp, R1_SP);
1378 
1379     // Push method's frame, modifies SP.
1380     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381     // The ABI is already accounted for in 'framesize' via the
1382     // 'out_preserve' area.
1383     Register tmp = push_frame_temp;
1384     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385     if (Assembler::is_simm(-offset, 16)) {
1386       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387     } else {
1388       long x = -offset;
1389       // Had to insert load_const(tmp, -offset).
1390       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392       ___(rldicr) sldi(tmp, tmp, 32);
1393       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1395 
1396       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397     }
1398   }
1399 #if 0 // TODO: PPC port
1400   // For testing large constant pools, emit a lot of constants to constant pool.
1401   // "Randomize" const_size.
1402   if (ConstantsALot) {
1403     const int num_consts = const_size();
1404     for (int i = 0; i < num_consts; i++) {
1405       __ long_constant(0xB0B5B00BBABE);
1406     }
1407   }
1408 #endif
1409   if (!method_is_frameless) {
1410     // Save return pc.
1411     ___(std) std(return_pc, _abi(lr), callers_sp);
1412   }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417 
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419   // Variable size. determine dynamically.
1420   return MachNode::size(ra_);
1421 }
1422 
1423 int MachPrologNode::reloc() const {
1424   // Return number of relocatable values contained in this instruction.
1425   return 1; // 1 reloc entry for load_const(toc).
1426 }
1427 
1428 //=============================================================================
1429 
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432   Compile* C = ra_->C;
1433 
1434   st->print("EPILOG\n\t");
1435   st->print("restore return pc\n\t");
1436   st->print("pop frame\n\t");
1437 
1438   if (do_polling() && C->is_method_compilation()) {
1439     st->print("touch polling page\n\t");
1440   }
1441 }
1442 #endif
1443 
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445   Compile* C = ra_->C;
1446   MacroAssembler _masm(&cbuf);
1447 
1448   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449   assert(framesize >= 0, "negative frame-size?");
1450 
1451   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1453   const Register return_pc        = R11;
1454   const Register polling_page     = R12;
1455 
1456   if (!method_is_frameless) {
1457     // Restore return pc relative to callers' sp.
1458     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459   }
1460 
1461   if (method_needs_polling) {
1462     if (LoadPollAddressFromThread) {
1463       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464       Unimplemented();
1465     } else {
1466       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467     }
1468   }
1469 
1470   if (!method_is_frameless) {
1471     // Move return pc to LR.
1472     __ mtlr(return_pc);
1473     // Pop frame (fixed frame-size).
1474     __ addi(R1_SP, R1_SP, (int)framesize);
1475   }
1476 
1477   if (method_needs_polling) {
1478     // We need to mark the code position where the load from the safepoint
1479     // polling page was emitted as relocInfo::poll_return_type here.
1480     __ relocate(relocInfo::poll_return_type);
1481     __ load_from_polling_page(polling_page);
1482   }
1483 }
1484 
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486   // Variable size. Determine dynamically.
1487   return MachNode::size(ra_);
1488 }
1489 
1490 int MachEpilogNode::reloc() const {
1491   // Return number of relocatable values contained in this instruction.
1492   return 1; // 1 for load_from_polling_page.
1493 }
1494 
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496   return MachNode::pipeline_class();
1497 }
1498 
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503   assert(do_polling(), "no return for this epilog node");
1504   return 0;
1505 }
1506 
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509   MacroAssembler _masm(&cbuf);
1510   if (LoadPollAddressFromThread) {
1511     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512   } else {
1513     _masm.nop();
1514   }
1515 }
1516 
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518   if (LoadPollAddressFromThread) {
1519     return 4;
1520   } else {
1521     return 4;
1522   }
1523 }
1524 
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530 
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532   return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535 
1536 // =============================================================================
1537 
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541 
1542 static enum RC rc_class(OptoReg::Name reg) {
1543   // Return the register class for the given register. The given register
1544   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545   // enumeration in adGlobals_ppc.hpp.
1546 
1547   if (reg == OptoReg::Bad) return rc_bad;
1548 
1549   // We have 64 integer register halves, starting at index 0.
1550   if (reg < 64) return rc_int;
1551 
1552   // We have 64 floating-point register halves, starting at index 64.
1553   if (reg < 64+64) return rc_float;
1554 
1555   // Between float regs & stack are the flags regs.
1556   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557 
1558   return rc_stack;
1559 }
1560 
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562                         bool do_print, Compile* C, outputStream *st) {
1563 
1564   assert(opcode == Assembler::LD_OPCODE   ||
1565          opcode == Assembler::STD_OPCODE  ||
1566          opcode == Assembler::LWZ_OPCODE  ||
1567          opcode == Assembler::STW_OPCODE  ||
1568          opcode == Assembler::LFD_OPCODE  ||
1569          opcode == Assembler::STFD_OPCODE ||
1570          opcode == Assembler::LFS_OPCODE  ||
1571          opcode == Assembler::STFS_OPCODE,
1572          "opcode not supported");
1573 
1574   if (cbuf) {
1575     int d =
1576       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580   }
1581 #ifndef PRODUCT
1582   else if (do_print) {
1583     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584               op_str,
1585               Matcher::regName[reg],
1586               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587   }
1588 #endif
1589   return 4; // size
1590 }
1591 
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593   Compile* C = ra_->C;
1594 
1595   // Get registers to move.
1596   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600 
1601   enum RC src_hi_rc = rc_class(src_hi);
1602   enum RC src_lo_rc = rc_class(src_lo);
1603   enum RC dst_hi_rc = rc_class(dst_hi);
1604   enum RC dst_lo_rc = rc_class(dst_lo);
1605 
1606   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607   if (src_hi != OptoReg::Bad)
1608     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610            "expected aligned-adjacent pairs");
1611   // Generate spill code!
1612   int size = 0;
1613 
1614   if (src_lo == dst_lo && src_hi == dst_hi)
1615     return size;            // Self copy, no move.
1616 
1617   // --------------------------------------
1618   // Memory->Memory Spill. Use R0 to hold the value.
1619   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620     int src_offset = ra_->reg2offset(src_lo);
1621     int dst_offset = ra_->reg2offset(dst_lo);
1622     if (src_hi != OptoReg::Bad) {
1623       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624              "expected same type of move for high parts");
1625       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1626       if (!cbuf && !do_size) st->print("\n\t");
1627       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628     } else {
1629       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630       if (!cbuf && !do_size) st->print("\n\t");
1631       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632     }
1633     return size;
1634   }
1635 
1636   // --------------------------------------
1637   // Check for float->int copy; requires a trip through memory.
1638   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639     Unimplemented();
1640   }
1641 
1642   // --------------------------------------
1643   // Check for integer reg-reg copy.
1644   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647       size = (Rsrc != Rdst) ? 4 : 0;
1648 
1649       if (cbuf) {
1650         MacroAssembler _masm(cbuf);
1651         if (size) {
1652           __ mr(Rdst, Rsrc);
1653         }
1654       }
1655 #ifndef PRODUCT
1656       else if (!do_size) {
1657         if (size) {
1658           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659         } else {
1660           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661         }
1662       }
1663 #endif
1664       return size;
1665   }
1666 
1667   // Check for integer store.
1668   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669     int dst_offset = ra_->reg2offset(dst_lo);
1670     if (src_hi != OptoReg::Bad) {
1671       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672              "expected same type of move for high parts");
1673       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674     } else {
1675       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676     }
1677     return size;
1678   }
1679 
1680   // Check for integer load.
1681   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682     int src_offset = ra_->reg2offset(src_lo);
1683     if (src_hi != OptoReg::Bad) {
1684       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685              "expected same type of move for high parts");
1686       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687     } else {
1688       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689     }
1690     return size;
1691   }
1692 
1693   // Check for float reg-reg copy.
1694   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695     if (cbuf) {
1696       MacroAssembler _masm(cbuf);
1697       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699       __ fmr(Rdst, Rsrc);
1700     }
1701 #ifndef PRODUCT
1702     else if (!do_size) {
1703       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704     }
1705 #endif
1706     return 4;
1707   }
1708 
1709   // Check for float store.
1710   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711     int dst_offset = ra_->reg2offset(dst_lo);
1712     if (src_hi != OptoReg::Bad) {
1713       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714              "expected same type of move for high parts");
1715       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716     } else {
1717       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718     }
1719     return size;
1720   }
1721 
1722   // Check for float load.
1723   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724     int src_offset = ra_->reg2offset(src_lo);
1725     if (src_hi != OptoReg::Bad) {
1726       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727              "expected same type of move for high parts");
1728       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729     } else {
1730       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731     }
1732     return size;
1733   }
1734 
1735   // --------------------------------------------------------------------
1736   // Check for hi bits still needing moving. Only happens for misaligned
1737   // arguments to native calls.
1738   if (src_hi == dst_hi)
1739     return size;               // Self copy; no move.
1740 
1741   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742   ShouldNotReachHere(); // Unimplemented
1743   return 0;
1744 }
1745 
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748   if (!ra_)
1749     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750   else
1751     implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754 
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756   implementation(&cbuf, ra_, false, NULL);
1757 }
1758 
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760   return implementation(NULL, ra_, true, NULL);
1761 }
1762 
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768   assert(ra_->node_regs_max_index() != 0, "");
1769 
1770   // Get registers to move.
1771   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775 
1776   enum RC src_lo_rc = rc_class(src_lo);
1777   enum RC dst_lo_rc = rc_class(dst_lo);
1778 
1779   if (src_lo == dst_lo && src_hi == dst_hi)
1780     return ppc64Opcode_none;            // Self copy, no move.
1781 
1782   // --------------------------------------
1783   // Memory->Memory Spill. Use R0 to hold the value.
1784   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785     return ppc64Opcode_compound;
1786   }
1787 
1788   // --------------------------------------
1789   // Check for float->int copy; requires a trip through memory.
1790   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791     Unimplemented();
1792   }
1793 
1794   // --------------------------------------
1795   // Check for integer reg-reg copy.
1796   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799     if (Rsrc == Rdst) {
1800       return ppc64Opcode_none;
1801     } else {
1802       return ppc64Opcode_or;
1803     }
1804   }
1805 
1806   // Check for integer store.
1807   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808     if (src_hi != OptoReg::Bad) {
1809       return ppc64Opcode_std;
1810     } else {
1811       return ppc64Opcode_stw;
1812     }
1813   }
1814 
1815   // Check for integer load.
1816   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817     if (src_hi != OptoReg::Bad) {
1818       return ppc64Opcode_ld;
1819     } else {
1820       return ppc64Opcode_lwz;
1821     }
1822   }
1823 
1824   // Check for float reg-reg copy.
1825   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826     return ppc64Opcode_fmr;
1827   }
1828 
1829   // Check for float store.
1830   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831     if (src_hi != OptoReg::Bad) {
1832       return ppc64Opcode_stfd;
1833     } else {
1834       return ppc64Opcode_stfs;
1835     }
1836   }
1837 
1838   // Check for float load.
1839   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840     if (src_hi != OptoReg::Bad) {
1841       return ppc64Opcode_lfd;
1842     } else {
1843       return ppc64Opcode_lfs;
1844     }
1845   }
1846 
1847   // --------------------------------------------------------------------
1848   // Check for hi bits still needing moving. Only happens for misaligned
1849   // arguments to native calls.
1850   if (src_hi == dst_hi) {
1851     return ppc64Opcode_none;               // Self copy; no move.
1852   }
1853 
1854   ShouldNotReachHere();
1855   return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858 
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861   st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864 
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866   MacroAssembler _masm(&cbuf);
1867   // _count contains the number of nops needed for padding.
1868   for (int i = 0; i < _count; i++) {
1869     __ nop();
1870   }
1871 }
1872 
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874   return _count * 4;
1875 }
1876 
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880   char reg_str[128];
1881   ra_->dump_register(this, reg_str);
1882   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885 
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887   MacroAssembler _masm(&cbuf);
1888 
1889   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890   int reg    = ra_->get_encode(this);
1891 
1892   if (Assembler::is_simm(offset, 16)) {
1893     __ addi(as_Register(reg), R1, offset);
1894   } else {
1895     ShouldNotReachHere();
1896   }
1897 }
1898 
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901   return 4;
1902 }
1903 
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906   st->print_cr("---- MachUEPNode ----");
1907   st->print_cr("...");
1908 }
1909 #endif
1910 
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912   // This is the unverified entry point.
1913   MacroAssembler _masm(&cbuf);
1914 
1915   // Inline_cache contains a klass.
1916   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
1917   Register receiver_klass = R12_scratch2;  // tmp
1918 
1919   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920   assert(R11_scratch1 == R11, "need prologue scratch register");
1921 
1922   // Check for NULL argument if we don't have implicit null checks.
1923   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924     if (TrapBasedNullChecks) {
1925       __ trap_null_check(R3_ARG1);
1926     } else {
1927       Label valid;
1928       __ cmpdi(CCR0, R3_ARG1, 0);
1929       __ bne_predict_taken(CCR0, valid);
1930       // We have a null argument, branch to ic_miss_stub.
1931       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932                            relocInfo::runtime_call_type);
1933       __ bind(valid);
1934     }
1935   }
1936   // Assume argument is not NULL, load klass from receiver.
1937   __ load_klass(receiver_klass, R3_ARG1);
1938 
1939   if (TrapBasedICMissChecks) {
1940     __ trap_ic_miss_check(receiver_klass, ic_klass);
1941   } else {
1942     Label valid;
1943     __ cmpd(CCR0, receiver_klass, ic_klass);
1944     __ beq_predict_taken(CCR0, valid);
1945     // We have an unexpected klass, branch to ic_miss_stub.
1946     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947                          relocInfo::runtime_call_type);
1948     __ bind(valid);
1949   }
1950 
1951   // Argument is valid and klass is as expected, continue.
1952 }
1953 
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957   return 0;
1958 }
1959 #endif
1960 
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962   // Variable size. Determine dynamically.
1963   return MachNode::size(ra_);
1964 }
1965 
1966 //=============================================================================
1967 
1968 %} // interrupt source
1969 
1970 source_hpp %{ // Header information of the source block.
1971 
1972 class HandlerImpl {
1973 
1974  public:
1975 
1976   static int emit_exception_handler(CodeBuffer &cbuf);
1977   static int emit_deopt_handler(CodeBuffer& cbuf);
1978 
1979   static uint size_exception_handler() {
1980     // The exception_handler is a b64_patchable.
1981     return MacroAssembler::b64_patchable_size;
1982   }
1983 
1984   static uint size_deopt_handler() {
1985     // The deopt_handler is a bl64_patchable.
1986     return MacroAssembler::bl64_patchable_size;
1987   }
1988 
1989 };
1990 
1991 %} // end source_hpp
1992 
1993 source %{
1994 
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996   MacroAssembler _masm(&cbuf);
1997 
1998   address base = __ start_a_stub(size_exception_handler());
1999   if (base == NULL) return 0; // CodeBuffer::expand failed
2000 
2001   int offset = __ offset();
2002   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003                        relocInfo::runtime_call_type);
2004   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005   __ end_a_stub();
2006 
2007   return offset;
2008 }
2009 
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013   MacroAssembler _masm(&cbuf);
2014 
2015   address base = __ start_a_stub(size_deopt_handler());
2016   if (base == NULL) return 0; // CodeBuffer::expand failed
2017 
2018   int offset = __ offset();
2019   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020                         relocInfo::runtime_call_type);
2021   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022   __ end_a_stub();
2023 
2024   return offset;
2025 }
2026 
2027 //=============================================================================
2028 
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031   if (as_Register(reg_enc) == R1_SP) {
2032     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033   }
2034   return 0;
2035 }
2036 
2037 const bool Matcher::match_rule_supported(int opcode) {
2038   if (!has_match_rule(opcode))
2039     return false;
2040 
2041   switch (opcode) {
2042   case Op_SqrtD:
2043     return VM_Version::has_fsqrt();
2044   case Op_CountLeadingZerosI:
2045   case Op_CountLeadingZerosL:
2046   case Op_CountTrailingZerosI:
2047   case Op_CountTrailingZerosL:
2048     if (!UseCountLeadingZerosInstructionsPPC64)
2049       return false;
2050     break;
2051 
2052   case Op_PopCountI:
2053   case Op_PopCountL:
2054     return (UsePopCountInstruction && VM_Version::has_popcntw());
2055 
2056   case Op_StrComp:
2057     return SpecialStringCompareTo;
2058   case Op_StrEquals:
2059     return SpecialStringEquals;
2060   case Op_StrIndexOf:
2061     return SpecialStringIndexOf;
2062   }
2063 
2064   return true;  // Per default match rules are supported.
2065 }
2066 
2067 const int Matcher::float_pressure(int default_pressure_threshold) {
2068   return default_pressure_threshold;
2069 }
2070 
2071 int Matcher::regnum_to_fpu_offset(int regnum) {
2072   // No user for this method?
2073   Unimplemented();
2074   return 999;
2075 }
2076 
2077 const bool Matcher::convL2FSupported(void) {
2078   // fcfids can do the conversion (>= Power7).
2079   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2080   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2081 }
2082 
2083 // Vector width in bytes.
2084 const int Matcher::vector_width_in_bytes(BasicType bt) {
2085   assert(MaxVectorSize == 8, "");
2086   return 8;
2087 }
2088 
2089 // Vector ideal reg.
2090 const int Matcher::vector_ideal_reg(int size) {
2091   assert(MaxVectorSize == 8 && size == 8, "");
2092   return Op_RegL;
2093 }
2094 
2095 const int Matcher::vector_shift_count_ideal_reg(int size) {
2096   fatal("vector shift is not supported");
2097   return Node::NotAMachineReg;
2098 }
2099 
2100 // Limits on vector size (number of elements) loaded into vector.
2101 const int Matcher::max_vector_size(const BasicType bt) {
2102   assert(is_java_primitive(bt), "only primitive type vectors");
2103   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2104 }
2105 
2106 const int Matcher::min_vector_size(const BasicType bt) {
2107   return max_vector_size(bt); // Same as max.
2108 }
2109 
2110 // PPC doesn't support misaligned vectors store/load.
2111 const bool Matcher::misaligned_vectors_ok() {
2112   return false;
2113 }
2114 
2115 // PPC AES support not yet implemented
2116 const bool Matcher::pass_original_key_for_aes() {
2117   return false;
2118 }
2119 
2120 // RETURNS: whether this branch offset is short enough that a short
2121 // branch can be used.
2122 //
2123 // If the platform does not provide any short branch variants, then
2124 // this method should return `false' for offset 0.
2125 //
2126 // `Compile::Fill_buffer' will decide on basis of this information
2127 // whether to do the pass `Compile::Shorten_branches' at all.
2128 //
2129 // And `Compile::Shorten_branches' will decide on basis of this
2130 // information whether to replace particular branch sites by short
2131 // ones.
2132 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2133   // Is the offset within the range of a ppc64 pc relative branch?
2134   bool b;
2135 
2136   const int safety_zone = 3 * BytesPerInstWord;
2137   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2138                          29 - 16 + 1 + 2);
2139   return b;
2140 }
2141 
2142 const bool Matcher::isSimpleConstant64(jlong value) {
2143   // Probably always true, even if a temp register is required.
2144   return true;
2145 }
2146 /* TODO: PPC port
2147 // Make a new machine dependent decode node (with its operands).
2148 MachTypeNode *Matcher::make_decode_node() {
2149   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2150          "This method is only implemented for unscaled cOops mode so far");
2151   MachTypeNode *decode = new decodeN_unscaledNode();
2152   decode->set_opnd_array(0, new iRegPdstOper());
2153   decode->set_opnd_array(1, new iRegNsrcOper());
2154   return decode;
2155 }
2156 */
2157 // Threshold size for cleararray.
2158 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2159 
2160 // false => size gets scaled to BytesPerLong, ok.
2161 const bool Matcher::init_array_count_is_in_bytes = false;
2162 
2163 // Use conditional move (CMOVL) on Power7.
2164 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2165 
2166 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2167 // fsel doesn't accept a condition register as input, so this would be slightly different.
2168 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2169 
2170 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2171 const bool Matcher::require_postalloc_expand = true;
2172 
2173 // Should the Matcher clone shifts on addressing modes, expecting them to
2174 // be subsumed into complex addressing expressions or compute them into
2175 // registers? True for Intel but false for most RISCs.
2176 const bool Matcher::clone_shift_expressions = false;
2177 
2178 // Do we need to mask the count passed to shift instructions or does
2179 // the cpu only look at the lower 5/6 bits anyway?
2180 // PowerPC requires masked shift counts.
2181 const bool Matcher::need_masked_shift_count = true;
2182 
2183 // This affects two different things:
2184 //  - how Decode nodes are matched
2185 //  - how ImplicitNullCheck opportunities are recognized
2186 // If true, the matcher will try to remove all Decodes and match them
2187 // (as operands) into nodes. NullChecks are not prepared to deal with
2188 // Decodes by final_graph_reshaping().
2189 // If false, final_graph_reshaping() forces the decode behind the Cmp
2190 // for a NullCheck. The matcher matches the Decode node into a register.
2191 // Implicit_null_check optimization moves the Decode along with the
2192 // memory operation back up before the NullCheck.
2193 bool Matcher::narrow_oop_use_complex_address() {
2194   // TODO: PPC port if (MatchDecodeNodes) return true;
2195   return false;
2196 }
2197 
2198 bool Matcher::narrow_klass_use_complex_address() {
2199   NOT_LP64(ShouldNotCallThis());
2200   assert(UseCompressedClassPointers, "only for compressed klass code");
2201   // TODO: PPC port if (MatchDecodeNodes) return true;
2202   return false;
2203 }
2204 
2205 // Is it better to copy float constants, or load them directly from memory?
2206 // Intel can load a float constant from a direct address, requiring no
2207 // extra registers. Most RISCs will have to materialize an address into a
2208 // register first, so they would do better to copy the constant from stack.
2209 const bool Matcher::rematerialize_float_constants = false;
2210 
2211 // If CPU can load and store mis-aligned doubles directly then no fixup is
2212 // needed. Else we split the double into 2 integer pieces and move it
2213 // piece-by-piece. Only happens when passing doubles into C code as the
2214 // Java calling convention forces doubles to be aligned.
2215 const bool Matcher::misaligned_doubles_ok = true;
2216 
2217 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2218  Unimplemented();
2219 }
2220 
2221 // Advertise here if the CPU requires explicit rounding operations
2222 // to implement the UseStrictFP mode.
2223 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2224 
2225 // Do floats take an entire double register or just half?
2226 //
2227 // A float occupies a ppc64 double register. For the allocator, a
2228 // ppc64 double register appears as a pair of float registers.
2229 bool Matcher::float_in_double() { return true; }
2230 
2231 // Do ints take an entire long register or just half?
2232 // The relevant question is how the int is callee-saved:
2233 // the whole long is written but de-opt'ing will have to extract
2234 // the relevant 32 bits.
2235 const bool Matcher::int_in_long = true;
2236 
2237 // Constants for c2c and c calling conventions.
2238 
2239 const MachRegisterNumbers iarg_reg[8] = {
2240   R3_num, R4_num, R5_num, R6_num,
2241   R7_num, R8_num, R9_num, R10_num
2242 };
2243 
2244 const MachRegisterNumbers farg_reg[13] = {
2245   F1_num, F2_num, F3_num, F4_num,
2246   F5_num, F6_num, F7_num, F8_num,
2247   F9_num, F10_num, F11_num, F12_num,
2248   F13_num
2249 };
2250 
2251 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2252 
2253 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2254 
2255 // Return whether or not this register is ever used as an argument. This
2256 // function is used on startup to build the trampoline stubs in generateOptoStub.
2257 // Registers not mentioned will be killed by the VM call in the trampoline, and
2258 // arguments in those registers not be available to the callee.
2259 bool Matcher::can_be_java_arg(int reg) {
2260   // We return true for all registers contained in iarg_reg[] and
2261   // farg_reg[] and their virtual halves.
2262   // We must include the virtual halves in order to get STDs and LDs
2263   // instead of STWs and LWs in the trampoline stubs.
2264 
2265   if (   reg == R3_num  || reg == R3_H_num
2266       || reg == R4_num  || reg == R4_H_num
2267       || reg == R5_num  || reg == R5_H_num
2268       || reg == R6_num  || reg == R6_H_num
2269       || reg == R7_num  || reg == R7_H_num
2270       || reg == R8_num  || reg == R8_H_num
2271       || reg == R9_num  || reg == R9_H_num
2272       || reg == R10_num || reg == R10_H_num)
2273     return true;
2274 
2275   if (   reg == F1_num  || reg == F1_H_num
2276       || reg == F2_num  || reg == F2_H_num
2277       || reg == F3_num  || reg == F3_H_num
2278       || reg == F4_num  || reg == F4_H_num
2279       || reg == F5_num  || reg == F5_H_num
2280       || reg == F6_num  || reg == F6_H_num
2281       || reg == F7_num  || reg == F7_H_num
2282       || reg == F8_num  || reg == F8_H_num
2283       || reg == F9_num  || reg == F9_H_num
2284       || reg == F10_num || reg == F10_H_num
2285       || reg == F11_num || reg == F11_H_num
2286       || reg == F12_num || reg == F12_H_num
2287       || reg == F13_num || reg == F13_H_num)
2288     return true;
2289 
2290   return false;
2291 }
2292 
2293 bool Matcher::is_spillable_arg(int reg) {
2294   return can_be_java_arg(reg);
2295 }
2296 
2297 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2298   return false;
2299 }
2300 
2301 // Register for DIVI projection of divmodI.
2302 RegMask Matcher::divI_proj_mask() {
2303   ShouldNotReachHere();
2304   return RegMask();
2305 }
2306 
2307 // Register for MODI projection of divmodI.
2308 RegMask Matcher::modI_proj_mask() {
2309   ShouldNotReachHere();
2310   return RegMask();
2311 }
2312 
2313 // Register for DIVL projection of divmodL.
2314 RegMask Matcher::divL_proj_mask() {
2315   ShouldNotReachHere();
2316   return RegMask();
2317 }
2318 
2319 // Register for MODL projection of divmodL.
2320 RegMask Matcher::modL_proj_mask() {
2321   ShouldNotReachHere();
2322   return RegMask();
2323 }
2324 
2325 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2326   return RegMask();
2327 }
2328 
2329 %}
2330 
2331 //----------ENCODING BLOCK-----------------------------------------------------
2332 // This block specifies the encoding classes used by the compiler to output
2333 // byte streams. Encoding classes are parameterized macros used by
2334 // Machine Instruction Nodes in order to generate the bit encoding of the
2335 // instruction. Operands specify their base encoding interface with the
2336 // interface keyword. There are currently supported four interfaces,
2337 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2338 // operand to generate a function which returns its register number when
2339 // queried. CONST_INTER causes an operand to generate a function which
2340 // returns the value of the constant when queried. MEMORY_INTER causes an
2341 // operand to generate four functions which return the Base Register, the
2342 // Index Register, the Scale Value, and the Offset Value of the operand when
2343 // queried. COND_INTER causes an operand to generate six functions which
2344 // return the encoding code (ie - encoding bits for the instruction)
2345 // associated with each basic boolean condition for a conditional instruction.
2346 //
2347 // Instructions specify two basic values for encoding. Again, a function
2348 // is available to check if the constant displacement is an oop. They use the
2349 // ins_encode keyword to specify their encoding classes (which must be
2350 // a sequence of enc_class names, and their parameters, specified in
2351 // the encoding block), and they use the
2352 // opcode keyword to specify, in order, their primary, secondary, and
2353 // tertiary opcode. Only the opcode sections which a particular instruction
2354 // needs for encoding need to be specified.
2355 encode %{
2356   enc_class enc_unimplemented %{
2357     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2358     MacroAssembler _masm(&cbuf);
2359     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2360   %}
2361 
2362   enc_class enc_untested %{
2363 #ifdef ASSERT
2364     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2365     MacroAssembler _masm(&cbuf);
2366     __ untested("Untested mach node encoding in AD file.");
2367 #else
2368     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2369 #endif
2370   %}
2371 
2372   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2373     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2374     MacroAssembler _masm(&cbuf);
2375     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2376     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2377   %}
2378 
2379   // Load acquire.
2380   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2381     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2382     MacroAssembler _masm(&cbuf);
2383     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2384     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2385     __ twi_0($dst$$Register);
2386     __ isync();
2387   %}
2388 
2389   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2390     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2391 
2392     MacroAssembler _masm(&cbuf);
2393     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2394     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2395   %}
2396 
2397   // Load acquire.
2398   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2399     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2400 
2401     MacroAssembler _masm(&cbuf);
2402     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2403     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2404     __ twi_0($dst$$Register);
2405     __ isync();
2406   %}
2407 
2408   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2409     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2410 
2411     MacroAssembler _masm(&cbuf);
2412     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2413     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2414   %}
2415 
2416   // Load acquire.
2417   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2418     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2419 
2420     MacroAssembler _masm(&cbuf);
2421     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2422     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2423     __ twi_0($dst$$Register);
2424     __ isync();
2425   %}
2426 
2427   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2428     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2429     MacroAssembler _masm(&cbuf);
2430     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2431     // Operand 'ds' requires 4-alignment.
2432     assert((Idisp & 0x3) == 0, "unaligned offset");
2433     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2434   %}
2435 
2436   // Load acquire.
2437   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2438     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2439     MacroAssembler _masm(&cbuf);
2440     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2441     // Operand 'ds' requires 4-alignment.
2442     assert((Idisp & 0x3) == 0, "unaligned offset");
2443     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2444     __ twi_0($dst$$Register);
2445     __ isync();
2446   %}
2447 
2448   enc_class enc_lfd(RegF dst, memory mem) %{
2449     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2450     MacroAssembler _masm(&cbuf);
2451     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2452     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2453   %}
2454 
2455   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2456     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2457 
2458     MacroAssembler _masm(&cbuf);
2459     int toc_offset = 0;
2460 
2461     if (!ra_->C->in_scratch_emit_size()) {
2462       address const_toc_addr;
2463       // Create a non-oop constant, no relocation needed.
2464       // If it is an IC, it has a virtual_call_Relocation.
2465       const_toc_addr = __ long_constant((jlong)$src$$constant);
2466 
2467       // Get the constant's TOC offset.
2468       toc_offset = __ offset_to_method_toc(const_toc_addr);
2469 
2470       // Keep the current instruction offset in mind.
2471       ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2472     }
2473 
2474     __ ld($dst$$Register, toc_offset, $toc$$Register);
2475   %}
2476 
2477   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2478     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2479 
2480     MacroAssembler _masm(&cbuf);
2481 
2482     if (!ra_->C->in_scratch_emit_size()) {
2483       address const_toc_addr;
2484       // Create a non-oop constant, no relocation needed.
2485       // If it is an IC, it has a virtual_call_Relocation.
2486       const_toc_addr = __ long_constant((jlong)$src$$constant);
2487 
2488       // Get the constant's TOC offset.
2489       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2490       // Store the toc offset of the constant.
2491       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2492 
2493       // Also keep the current instruction offset in mind.
2494       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2495     }
2496 
2497     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2498   %}
2499 
2500 %} // encode
2501 
2502 source %{
2503 
2504 typedef struct {
2505   loadConL_hiNode *_large_hi;
2506   loadConL_loNode *_large_lo;
2507   loadConLNode    *_small;
2508   MachNode        *_last;
2509 } loadConLNodesTuple;
2510 
2511 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2512                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2513   loadConLNodesTuple nodes;
2514 
2515   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2516   if (large_constant_pool) {
2517     // Create new nodes.
2518     loadConL_hiNode *m1 = new loadConL_hiNode();
2519     loadConL_loNode *m2 = new loadConL_loNode();
2520 
2521     // inputs for new nodes
2522     m1->add_req(NULL, toc);
2523     m2->add_req(NULL, m1);
2524 
2525     // operands for new nodes
2526     m1->_opnds[0] = new iRegLdstOper(); // dst
2527     m1->_opnds[1] = immSrc;             // src
2528     m1->_opnds[2] = new iRegPdstOper(); // toc
2529     m2->_opnds[0] = new iRegLdstOper(); // dst
2530     m2->_opnds[1] = immSrc;             // src
2531     m2->_opnds[2] = new iRegLdstOper(); // base
2532 
2533     // Initialize ins_attrib TOC fields.
2534     m1->_const_toc_offset = -1;
2535     m2->_const_toc_offset_hi_node = m1;
2536 
2537     // Initialize ins_attrib instruction offset.
2538     m1->_cbuf_insts_offset = -1;
2539 
2540     // register allocation for new nodes
2541     ra_->set_pair(m1->_idx, reg_second, reg_first);
2542     ra_->set_pair(m2->_idx, reg_second, reg_first);
2543 
2544     // Create result.
2545     nodes._large_hi = m1;
2546     nodes._large_lo = m2;
2547     nodes._small = NULL;
2548     nodes._last = nodes._large_lo;
2549     assert(m2->bottom_type()->isa_long(), "must be long");
2550   } else {
2551     loadConLNode *m2 = new loadConLNode();
2552 
2553     // inputs for new nodes
2554     m2->add_req(NULL, toc);
2555 
2556     // operands for new nodes
2557     m2->_opnds[0] = new iRegLdstOper(); // dst
2558     m2->_opnds[1] = immSrc;             // src
2559     m2->_opnds[2] = new iRegPdstOper(); // toc
2560 
2561     // Initialize ins_attrib instruction offset.
2562     m2->_cbuf_insts_offset = -1;
2563 
2564     // register allocation for new nodes
2565     ra_->set_pair(m2->_idx, reg_second, reg_first);
2566 
2567     // Create result.
2568     nodes._large_hi = NULL;
2569     nodes._large_lo = NULL;
2570     nodes._small = m2;
2571     nodes._last = nodes._small;
2572     assert(m2->bottom_type()->isa_long(), "must be long");
2573   }
2574 
2575   return nodes;
2576 }
2577 
2578 %} // source
2579 
2580 encode %{
2581   // Postalloc expand emitter for loading a long constant from the method's TOC.
2582   // Enc_class needed as consttanttablebase is not supported by postalloc
2583   // expand.
2584   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2585     // Create new nodes.
2586     loadConLNodesTuple loadConLNodes =
2587       loadConLNodesTuple_create(ra_, n_toc, op_src,
2588                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2589 
2590     // Push new nodes.
2591     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2592     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2593 
2594     // some asserts
2595     assert(nodes->length() >= 1, "must have created at least 1 node");
2596     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2597   %}
2598 
2599   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2600     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2601 
2602     MacroAssembler _masm(&cbuf);
2603     int toc_offset = 0;
2604 
2605     if (!ra_->C->in_scratch_emit_size()) {
2606       intptr_t val = $src$$constant;
2607       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2608       address const_toc_addr;
2609       if (constant_reloc == relocInfo::oop_type) {
2610         // Create an oop constant and a corresponding relocation.
2611         AddressLiteral a = __ allocate_oop_address((jobject)val);
2612         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2613         __ relocate(a.rspec());
2614       } else if (constant_reloc == relocInfo::metadata_type) {
2615         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2616         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2617         __ relocate(a.rspec());
2618       } else {
2619         // Create a non-oop constant, no relocation needed.
2620         const_toc_addr = __ long_constant((jlong)$src$$constant);
2621       }
2622 
2623       // Get the constant's TOC offset.
2624       toc_offset = __ offset_to_method_toc(const_toc_addr);
2625     }
2626 
2627     __ ld($dst$$Register, toc_offset, $toc$$Register);
2628   %}
2629 
2630   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2631     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2632 
2633     MacroAssembler _masm(&cbuf);
2634     if (!ra_->C->in_scratch_emit_size()) {
2635       intptr_t val = $src$$constant;
2636       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2637       address const_toc_addr;
2638       if (constant_reloc == relocInfo::oop_type) {
2639         // Create an oop constant and a corresponding relocation.
2640         AddressLiteral a = __ allocate_oop_address((jobject)val);
2641         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2642         __ relocate(a.rspec());
2643       } else if (constant_reloc == relocInfo::metadata_type) {
2644         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2645         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2646         __ relocate(a.rspec());
2647       } else {  // non-oop pointers, e.g. card mark base, heap top
2648         // Create a non-oop constant, no relocation needed.
2649         const_toc_addr = __ long_constant((jlong)$src$$constant);
2650       }
2651 
2652       // Get the constant's TOC offset.
2653       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2654       // Store the toc offset of the constant.
2655       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2656     }
2657 
2658     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2659   %}
2660 
2661   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2662   // Enc_class needed as consttanttablebase is not supported by postalloc
2663   // expand.
2664   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2665     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2666     if (large_constant_pool) {
2667       // Create new nodes.
2668       loadConP_hiNode *m1 = new loadConP_hiNode();
2669       loadConP_loNode *m2 = new loadConP_loNode();
2670 
2671       // inputs for new nodes
2672       m1->add_req(NULL, n_toc);
2673       m2->add_req(NULL, m1);
2674 
2675       // operands for new nodes
2676       m1->_opnds[0] = new iRegPdstOper(); // dst
2677       m1->_opnds[1] = op_src;             // src
2678       m1->_opnds[2] = new iRegPdstOper(); // toc
2679       m2->_opnds[0] = new iRegPdstOper(); // dst
2680       m2->_opnds[1] = op_src;             // src
2681       m2->_opnds[2] = new iRegLdstOper(); // base
2682 
2683       // Initialize ins_attrib TOC fields.
2684       m1->_const_toc_offset = -1;
2685       m2->_const_toc_offset_hi_node = m1;
2686 
2687       // Register allocation for new nodes.
2688       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2689       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2690 
2691       nodes->push(m1);
2692       nodes->push(m2);
2693       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2694     } else {
2695       loadConPNode *m2 = new loadConPNode();
2696 
2697       // inputs for new nodes
2698       m2->add_req(NULL, n_toc);
2699 
2700       // operands for new nodes
2701       m2->_opnds[0] = new iRegPdstOper(); // dst
2702       m2->_opnds[1] = op_src;             // src
2703       m2->_opnds[2] = new iRegPdstOper(); // toc
2704 
2705       // Register allocation for new nodes.
2706       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2707 
2708       nodes->push(m2);
2709       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2710     }
2711   %}
2712 
2713   // Enc_class needed as consttanttablebase is not supported by postalloc
2714   // expand.
2715   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2716     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2717 
2718     MachNode *m2;
2719     if (large_constant_pool) {
2720       m2 = new loadConFCompNode();
2721     } else {
2722       m2 = new loadConFNode();
2723     }
2724     // inputs for new nodes
2725     m2->add_req(NULL, n_toc);
2726 
2727     // operands for new nodes
2728     m2->_opnds[0] = op_dst;
2729     m2->_opnds[1] = op_src;
2730     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2731 
2732     // register allocation for new nodes
2733     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2734     nodes->push(m2);
2735   %}
2736 
2737   // Enc_class needed as consttanttablebase is not supported by postalloc
2738   // expand.
2739   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2740     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2741 
2742     MachNode *m2;
2743     if (large_constant_pool) {
2744       m2 = new loadConDCompNode();
2745     } else {
2746       m2 = new loadConDNode();
2747     }
2748     // inputs for new nodes
2749     m2->add_req(NULL, n_toc);
2750 
2751     // operands for new nodes
2752     m2->_opnds[0] = op_dst;
2753     m2->_opnds[1] = op_src;
2754     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2755 
2756     // register allocation for new nodes
2757     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2758     nodes->push(m2);
2759   %}
2760 
2761   enc_class enc_stw(iRegIsrc src, memory mem) %{
2762     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2763     MacroAssembler _masm(&cbuf);
2764     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2765     __ stw($src$$Register, Idisp, $mem$$base$$Register);
2766   %}
2767 
2768   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2769     // TODO: PPC port $archOpcode(ppc64Opcode_std);
2770     MacroAssembler _masm(&cbuf);
2771     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2772     // Operand 'ds' requires 4-alignment.
2773     assert((Idisp & 0x3) == 0, "unaligned offset");
2774     __ std($src$$Register, Idisp, $mem$$base$$Register);
2775   %}
2776 
2777   enc_class enc_stfs(RegF src, memory mem) %{
2778     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2779     MacroAssembler _masm(&cbuf);
2780     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2781     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2782   %}
2783 
2784   enc_class enc_stfd(RegF src, memory mem) %{
2785     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2786     MacroAssembler _masm(&cbuf);
2787     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2788     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2789   %}
2790 
2791   // Use release_store for card-marking to ensure that previous
2792   // oop-stores are visible before the card-mark change.
2793   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2794     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2795     // FIXME: Implement this as a cmove and use a fixed condition code
2796     // register which is written on every transition to compiled code,
2797     // e.g. in call-stub and when returning from runtime stubs.
2798     //
2799     // Proposed code sequence for the cmove implementation:
2800     //
2801     // Label skip_release;
2802     // __ beq(CCRfixed, skip_release);
2803     // __ release();
2804     // __ bind(skip_release);
2805     // __ stb(card mark);
2806 
2807     MacroAssembler _masm(&cbuf);
2808     Label skip_storestore;
2809 
2810 #if 0 // TODO: PPC port
2811     // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2812     // StoreStore barrier conditionally.
2813     __ lwz(R0, 0, $releaseFieldAddr$$Register);
2814     __ cmpwi($crx$$CondRegister, R0, 0);
2815     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2816 #endif
2817     __ li(R0, 0);
2818     __ membar(Assembler::StoreStore);
2819 #if 0 // TODO: PPC port
2820     __ bind(skip_storestore);
2821 #endif
2822 
2823     // Do the store.
2824     if ($mem$$index == 0) {
2825       __ stb(R0, $mem$$disp, $mem$$base$$Register);
2826     } else {
2827       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2828       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2829     }
2830   %}
2831 
2832   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2833 
2834     if (VM_Version::has_isel()) {
2835       // use isel instruction with Power 7
2836       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2837       encodeP_subNode    *n_sub_base = new encodeP_subNode();
2838       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2839       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2840 
2841       n_compare->add_req(n_region, n_src);
2842       n_compare->_opnds[0] = op_crx;
2843       n_compare->_opnds[1] = op_src;
2844       n_compare->_opnds[2] = new immL16Oper(0);
2845 
2846       n_sub_base->add_req(n_region, n_src);
2847       n_sub_base->_opnds[0] = op_dst;
2848       n_sub_base->_opnds[1] = op_src;
2849       n_sub_base->_bottom_type = _bottom_type;
2850 
2851       n_shift->add_req(n_region, n_sub_base);
2852       n_shift->_opnds[0] = op_dst;
2853       n_shift->_opnds[1] = op_dst;
2854       n_shift->_bottom_type = _bottom_type;
2855 
2856       n_cond_set->add_req(n_region, n_compare, n_shift);
2857       n_cond_set->_opnds[0] = op_dst;
2858       n_cond_set->_opnds[1] = op_crx;
2859       n_cond_set->_opnds[2] = op_dst;
2860       n_cond_set->_bottom_type = _bottom_type;
2861 
2862       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2863       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2864       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2865       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2866 
2867       nodes->push(n_compare);
2868       nodes->push(n_sub_base);
2869       nodes->push(n_shift);
2870       nodes->push(n_cond_set);
2871 
2872     } else {
2873       // before Power 7
2874       moveRegNode        *n_move     = new moveRegNode();
2875       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2876       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2877       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
2878 
2879       n_move->add_req(n_region, n_src);
2880       n_move->_opnds[0] = op_dst;
2881       n_move->_opnds[1] = op_src;
2882       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2883 
2884       n_compare->add_req(n_region, n_src);
2885       n_compare->add_prec(n_move);
2886 
2887       n_compare->_opnds[0] = op_crx;
2888       n_compare->_opnds[1] = op_src;
2889       n_compare->_opnds[2] = new immL16Oper(0);
2890 
2891       n_sub_base->add_req(n_region, n_compare, n_src);
2892       n_sub_base->_opnds[0] = op_dst;
2893       n_sub_base->_opnds[1] = op_crx;
2894       n_sub_base->_opnds[2] = op_src;
2895       n_sub_base->_bottom_type = _bottom_type;
2896 
2897       n_shift->add_req(n_region, n_sub_base);
2898       n_shift->_opnds[0] = op_dst;
2899       n_shift->_opnds[1] = op_dst;
2900       n_shift->_bottom_type = _bottom_type;
2901 
2902       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2903       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2904       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2905       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2906 
2907       nodes->push(n_move);
2908       nodes->push(n_compare);
2909       nodes->push(n_sub_base);
2910       nodes->push(n_shift);
2911     }
2912 
2913     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2914   %}
2915 
2916   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2917 
2918     encodeP_subNode *n1 = new encodeP_subNode();
2919     n1->add_req(n_region, n_src);
2920     n1->_opnds[0] = op_dst;
2921     n1->_opnds[1] = op_src;
2922     n1->_bottom_type = _bottom_type;
2923 
2924     encodeP_shiftNode *n2 = new encodeP_shiftNode();
2925     n2->add_req(n_region, n1);
2926     n2->_opnds[0] = op_dst;
2927     n2->_opnds[1] = op_dst;
2928     n2->_bottom_type = _bottom_type;
2929     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2930     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2931 
2932     nodes->push(n1);
2933     nodes->push(n2);
2934     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2935   %}
2936 
2937   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2938     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
2939     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
2940 
2941     n_compare->add_req(n_region, n_src);
2942     n_compare->_opnds[0] = op_crx;
2943     n_compare->_opnds[1] = op_src;
2944     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2945 
2946     n_shift->add_req(n_region, n_src);
2947     n_shift->_opnds[0] = op_dst;
2948     n_shift->_opnds[1] = op_src;
2949     n_shift->_bottom_type = _bottom_type;
2950 
2951     if (VM_Version::has_isel()) {
2952       // use isel instruction with Power 7
2953 
2954       decodeN_addNode *n_add_base = new decodeN_addNode();
2955       n_add_base->add_req(n_region, n_shift);
2956       n_add_base->_opnds[0] = op_dst;
2957       n_add_base->_opnds[1] = op_dst;
2958       n_add_base->_bottom_type = _bottom_type;
2959 
2960       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2961       n_cond_set->add_req(n_region, n_compare, n_add_base);
2962       n_cond_set->_opnds[0] = op_dst;
2963       n_cond_set->_opnds[1] = op_crx;
2964       n_cond_set->_opnds[2] = op_dst;
2965       n_cond_set->_bottom_type = _bottom_type;
2966 
2967       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2968       ra_->set_oop(n_cond_set, true);
2969 
2970       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2971       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2972       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2973       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2974 
2975       nodes->push(n_compare);
2976       nodes->push(n_shift);
2977       nodes->push(n_add_base);
2978       nodes->push(n_cond_set);
2979 
2980     } else {
2981       // before Power 7
2982       cond_add_baseNode *n_add_base = new cond_add_baseNode();
2983 
2984       n_add_base->add_req(n_region, n_compare, n_shift);
2985       n_add_base->_opnds[0] = op_dst;
2986       n_add_base->_opnds[1] = op_crx;
2987       n_add_base->_opnds[2] = op_dst;
2988       n_add_base->_bottom_type = _bottom_type;
2989 
2990       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2991       ra_->set_oop(n_add_base, true);
2992 
2993       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2994       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2995       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2996 
2997       nodes->push(n_compare);
2998       nodes->push(n_shift);
2999       nodes->push(n_add_base);
3000     }
3001   %}
3002 
3003   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3004     decodeN_shiftNode *n1 = new decodeN_shiftNode();
3005     n1->add_req(n_region, n_src);
3006     n1->_opnds[0] = op_dst;
3007     n1->_opnds[1] = op_src;
3008     n1->_bottom_type = _bottom_type;
3009 
3010     decodeN_addNode *n2 = new decodeN_addNode();
3011     n2->add_req(n_region, n1);
3012     n2->_opnds[0] = op_dst;
3013     n2->_opnds[1] = op_dst;
3014     n2->_bottom_type = _bottom_type;
3015     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3016     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017 
3018     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3019     ra_->set_oop(n2, true);
3020 
3021     nodes->push(n1);
3022     nodes->push(n2);
3023   %}
3024 
3025   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3026     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3027 
3028     MacroAssembler _masm(&cbuf);
3029     int cc        = $cmp$$cmpcode;
3030     int flags_reg = $crx$$reg;
3031     Label done;
3032     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3033     // Branch if not (cmp crx).
3034     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3035     __ mr($dst$$Register, $src$$Register);
3036     // TODO PPC port __ endgroup_if_needed(_size == 12);
3037     __ bind(done);
3038   %}
3039 
3040   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3041     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3042 
3043     MacroAssembler _masm(&cbuf);
3044     Label done;
3045     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3046     // Branch if not (cmp crx).
3047     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3048     __ li($dst$$Register, $src$$constant);
3049     // TODO PPC port __ endgroup_if_needed(_size == 12);
3050     __ bind(done);
3051   %}
3052 
3053   // New atomics.
3054   enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3055     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3056 
3057     MacroAssembler _masm(&cbuf);
3058     Register Rtmp   = R0;
3059     Register Rres   = $res$$Register;
3060     Register Rsrc   = $src$$Register;
3061     Register Rptr   = $mem_ptr$$Register;
3062     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3063     Register Rold   = RegCollision ? Rtmp : Rres;
3064 
3065     Label Lretry;
3066     __ bind(Lretry);
3067     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3068     __ add(Rtmp, Rsrc, Rold);
3069     __ stwcx_(Rtmp, Rptr);
3070     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3071       __ bne_predict_not_taken(CCR0, Lretry);
3072     } else {
3073       __ bne(                  CCR0, Lretry);
3074     }
3075     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3076     __ fence();
3077   %}
3078 
3079   enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3080     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3081 
3082     MacroAssembler _masm(&cbuf);
3083     Register Rtmp   = R0;
3084     Register Rres   = $res$$Register;
3085     Register Rsrc   = $src$$Register;
3086     Register Rptr   = $mem_ptr$$Register;
3087     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3088     Register Rold   = RegCollision ? Rtmp : Rres;
3089 
3090     Label Lretry;
3091     __ bind(Lretry);
3092     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3093     __ add(Rtmp, Rsrc, Rold);
3094     __ stdcx_(Rtmp, Rptr);
3095     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3096       __ bne_predict_not_taken(CCR0, Lretry);
3097     } else {
3098       __ bne(                  CCR0, Lretry);
3099     }
3100     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3101     __ fence();
3102   %}
3103 
3104   enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3105     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3106 
3107     MacroAssembler _masm(&cbuf);
3108     Register Rtmp   = R0;
3109     Register Rres   = $res$$Register;
3110     Register Rsrc   = $src$$Register;
3111     Register Rptr   = $mem_ptr$$Register;
3112     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3113     Register Rold   = RegCollision ? Rtmp : Rres;
3114 
3115     Label Lretry;
3116     __ bind(Lretry);
3117     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3118     __ stwcx_(Rsrc, Rptr);
3119     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3120       __ bne_predict_not_taken(CCR0, Lretry);
3121     } else {
3122       __ bne(                  CCR0, Lretry);
3123     }
3124     if (RegCollision) __ mr(Rres, Rtmp);
3125     __ fence();
3126   %}
3127 
3128   enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3129     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3130 
3131     MacroAssembler _masm(&cbuf);
3132     Register Rtmp   = R0;
3133     Register Rres   = $res$$Register;
3134     Register Rsrc   = $src$$Register;
3135     Register Rptr   = $mem_ptr$$Register;
3136     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3137     Register Rold   = RegCollision ? Rtmp : Rres;
3138 
3139     Label Lretry;
3140     __ bind(Lretry);
3141     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3142     __ stdcx_(Rsrc, Rptr);
3143     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3144       __ bne_predict_not_taken(CCR0, Lretry);
3145     } else {
3146       __ bne(                  CCR0, Lretry);
3147     }
3148     if (RegCollision) __ mr(Rres, Rtmp);
3149     __ fence();
3150   %}
3151 
3152   // This enc_class is needed so that scheduler gets proper
3153   // input mapping for latency computation.
3154   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3155     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3156     MacroAssembler _masm(&cbuf);
3157     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3158   %}
3159 
3160   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3161     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3162 
3163     MacroAssembler _masm(&cbuf);
3164 
3165     Label done;
3166     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3167     __ li($dst$$Register, $zero$$constant);
3168     __ beq($crx$$CondRegister, done);
3169     __ li($dst$$Register, $notzero$$constant);
3170     __ bind(done);
3171   %}
3172 
3173   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3174     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3175 
3176     MacroAssembler _masm(&cbuf);
3177 
3178     Label done;
3179     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3180     __ li($dst$$Register, $zero$$constant);
3181     __ beq($crx$$CondRegister, done);
3182     __ li($dst$$Register, $notzero$$constant);
3183     __ bind(done);
3184   %}
3185 
3186   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3187     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3188 
3189     MacroAssembler _masm(&cbuf);
3190     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3191     Label done;
3192     __ bso($crx$$CondRegister, done);
3193     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3194     // TODO PPC port __ endgroup_if_needed(_size == 12);
3195     __ bind(done);
3196   %}
3197 
3198   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3199     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3200 
3201     MacroAssembler _masm(&cbuf);
3202     Label d;   // dummy
3203     __ bind(d);
3204     Label* p = ($lbl$$label);
3205     // `p' is `NULL' when this encoding class is used only to
3206     // determine the size of the encoded instruction.
3207     Label& l = (NULL == p)? d : *(p);
3208     int cc = $cmp$$cmpcode;
3209     int flags_reg = $crx$$reg;
3210     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3211     int bhint = Assembler::bhintNoHint;
3212 
3213     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3214       if (_prob <= PROB_NEVER) {
3215         bhint = Assembler::bhintIsNotTaken;
3216       } else if (_prob >= PROB_ALWAYS) {
3217         bhint = Assembler::bhintIsTaken;
3218       }
3219     }
3220 
3221     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3222           cc_to_biint(cc, flags_reg),
3223           l);
3224   %}
3225 
3226   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3227     // The scheduler doesn't know about branch shortening, so we set the opcode
3228     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3229     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3230 
3231     MacroAssembler _masm(&cbuf);
3232     Label d;    // dummy
3233     __ bind(d);
3234     Label* p = ($lbl$$label);
3235     // `p' is `NULL' when this encoding class is used only to
3236     // determine the size of the encoded instruction.
3237     Label& l = (NULL == p)? d : *(p);
3238     int cc = $cmp$$cmpcode;
3239     int flags_reg = $crx$$reg;
3240     int bhint = Assembler::bhintNoHint;
3241 
3242     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3243       if (_prob <= PROB_NEVER) {
3244         bhint = Assembler::bhintIsNotTaken;
3245       } else if (_prob >= PROB_ALWAYS) {
3246         bhint = Assembler::bhintIsTaken;
3247       }
3248     }
3249 
3250     // Tell the conditional far branch to optimize itself when being relocated.
3251     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3252                   cc_to_biint(cc, flags_reg),
3253                   l,
3254                   MacroAssembler::bc_far_optimize_on_relocate);
3255   %}
3256 
3257   // Branch used with Power6 scheduling (can be shortened without changing the node).
3258   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3259     // The scheduler doesn't know about branch shortening, so we set the opcode
3260     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3261     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3262 
3263     MacroAssembler _masm(&cbuf);
3264     Label d;   // dummy
3265     __ bind(d);
3266     Label* p = ($lbl$$label);
3267     // `p' is `NULL' when this encoding class is used only to
3268     // determine the size of the encoded instruction.
3269     Label& l = (NULL == p)? d : *(p);
3270     int cc = $cmp$$cmpcode;
3271     int flags_reg = $crx$$reg;
3272     int bhint = Assembler::bhintNoHint;
3273 
3274     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3275       if (_prob <= PROB_NEVER) {
3276         bhint = Assembler::bhintIsNotTaken;
3277       } else if (_prob >= PROB_ALWAYS) {
3278         bhint = Assembler::bhintIsTaken;
3279       }
3280     }
3281 
3282 #if 0 // TODO: PPC port
3283     if (_size == 8) {
3284       // Tell the conditional far branch to optimize itself when being relocated.
3285       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3286                     cc_to_biint(cc, flags_reg),
3287                     l,
3288                     MacroAssembler::bc_far_optimize_on_relocate);
3289     } else {
3290       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3291                     cc_to_biint(cc, flags_reg),
3292                     l);
3293     }
3294 #endif
3295     Unimplemented();
3296   %}
3297 
3298   // Postalloc expand emitter for loading a replicatef float constant from
3299   // the method's TOC.
3300   // Enc_class needed as consttanttablebase is not supported by postalloc
3301   // expand.
3302   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3303     // Create new nodes.
3304 
3305     // Make an operand with the bit pattern to load as float.
3306     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3307 
3308     loadConLNodesTuple loadConLNodes =
3309       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3310                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3311 
3312     // Push new nodes.
3313     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3314     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3315 
3316     assert(nodes->length() >= 1, "must have created at least 1 node");
3317     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3318   %}
3319 
3320   // This enc_class is needed so that scheduler gets proper
3321   // input mapping for latency computation.
3322   enc_class enc_poll(immI dst, iRegLdst poll) %{
3323     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3324     // Fake operand dst needed for PPC scheduler.
3325     assert($dst$$constant == 0x0, "dst must be 0x0");
3326 
3327     MacroAssembler _masm(&cbuf);
3328     // Mark the code position where the load from the safepoint
3329     // polling page was emitted as relocInfo::poll_type.
3330     __ relocate(relocInfo::poll_type);
3331     __ load_from_polling_page($poll$$Register);
3332   %}
3333 
3334   // A Java static call or a runtime call.
3335   //
3336   // Branch-and-link relative to a trampoline.
3337   // The trampoline loads the target address and does a long branch to there.
3338   // In case we call java, the trampoline branches to a interpreter_stub
3339   // which loads the inline cache and the real call target from the constant pool.
3340   //
3341   // This basically looks like this:
3342   //
3343   // >>>> consts      -+  -+
3344   //                   |   |- offset1
3345   // [call target1]    | <-+
3346   // [IC cache]        |- offset2
3347   // [call target2] <--+
3348   //
3349   // <<<< consts
3350   // >>>> insts
3351   //
3352   // bl offset16               -+  -+             ??? // How many bits available?
3353   //                            |   |
3354   // <<<< insts                 |   |
3355   // >>>> stubs                 |   |
3356   //                            |   |- trampoline_stub_Reloc
3357   // trampoline stub:           | <-+
3358   //   r2 = toc                 |
3359   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3360   //   mtctr r2                 |
3361   //   bctr                     |- static_stub_Reloc
3362   // comp_to_interp_stub:   <---+
3363   //   r1 = toc
3364   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3365   //   r1    = [r1 + offset2]           // Load call target2 from const section
3366   //   mtctr r1
3367   //   bctr
3368   //
3369   // <<<< stubs
3370   //
3371   // The call instruction in the code either
3372   // - Branches directly to a compiled method if the offset is encodable in instruction.
3373   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3374   // - Branches to the compiled_to_interp stub if the target is interpreted.
3375   //
3376   // Further there are three relocations from the loads to the constants in
3377   // the constant section.
3378   //
3379   // Usage of r1 and r2 in the stubs allows to distinguish them.
3380   enc_class enc_java_static_call(method meth) %{
3381     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3382 
3383     MacroAssembler _masm(&cbuf);
3384     address entry_point = (address)$meth$$method;
3385 
3386     if (!_method) {
3387       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3388       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3389     } else {
3390       // Remember the offset not the address.
3391       const int start_offset = __ offset();
3392       // The trampoline stub.
3393       if (!Compile::current()->in_scratch_emit_size()) {
3394         // No entry point given, use the current pc.
3395         // Make sure branch fits into
3396         if (entry_point == 0) entry_point = __ pc();
3397 
3398         // Put the entry point as a constant into the constant pool.
3399         const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3400         const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3401 
3402         // Emit the trampoline stub which will be related to the branch-and-link below.
3403         CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3404         if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3405         __ relocate(_optimized_virtual ?
3406                     relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3407       }
3408 
3409       // The real call.
3410       // Note: At this point we do not have the address of the trampoline
3411       // stub, and the entry point might be too far away for bl, so __ pc()
3412       // serves as dummy and the bl will be patched later.
3413       cbuf.set_insts_mark();
3414       __ bl(__ pc());  // Emits a relocation.
3415 
3416       // The stub for call to interpreter.
3417       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3418       if (stub == NULL) {
3419         ciEnv::current()->record_failure("CodeCache is full"); 
3420         return;
3421       }
3422     }
3423   %}
3424 
3425   // Emit a method handle call.
3426   //
3427   // Method handle calls from compiled to compiled are going thru a
3428   // c2i -> i2c adapter, extending the frame for their arguments. The
3429   // caller however, returns directly to the compiled callee, that has
3430   // to cope with the extended frame. We restore the original frame by
3431   // loading the callers sp and adding the calculated framesize.
3432   enc_class enc_java_handle_call(method meth) %{
3433     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3434 
3435     MacroAssembler _masm(&cbuf);
3436     address entry_point = (address)$meth$$method;
3437 
3438     // Remember the offset not the address.
3439     const int start_offset = __ offset();
3440     // The trampoline stub.
3441     if (!ra_->C->in_scratch_emit_size()) {
3442       // No entry point given, use the current pc.
3443       // Make sure branch fits into
3444       if (entry_point == 0) entry_point = __ pc();
3445 
3446       // Put the entry point as a constant into the constant pool.
3447       const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3448       const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3449 
3450       // Emit the trampoline stub which will be related to the branch-and-link below.
3451       CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3452       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3453       assert(_optimized_virtual, "methodHandle call should be a virtual call");
3454       __ relocate(relocInfo::opt_virtual_call_type);
3455     }
3456 
3457     // The real call.
3458     // Note: At this point we do not have the address of the trampoline
3459     // stub, and the entry point might be too far away for bl, so __ pc()
3460     // serves as dummy and the bl will be patched later.
3461     cbuf.set_insts_mark();
3462     __ bl(__ pc());  // Emits a relocation.
3463 
3464     assert(_method, "execute next statement conditionally");
3465     // The stub for call to interpreter.
3466     address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3467     if (stub == NULL) {
3468       ciEnv::current()->record_failure("CodeCache is full"); 
3469       return;
3470     }
3471 
3472     // Restore original sp.
3473     __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3474     const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3475     unsigned int bytes = (unsigned int)framesize;
3476     long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3477     if (Assembler::is_simm(-offset, 16)) {
3478       __ addi(R1_SP, R11_scratch1, -offset);
3479     } else {
3480       __ load_const_optimized(R12_scratch2, -offset);
3481       __ add(R1_SP, R11_scratch1, R12_scratch2);
3482     }
3483 #ifdef ASSERT
3484   __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3485   __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3486   __ asm_assert_eq("backlink changed", 0x8000);
3487 #endif
3488     // If fails should store backlink before unextending.
3489 
3490     if (ra_->C->env()->failing()) {
3491       return;
3492     }
3493   %}
3494 
3495   // Second node of expanded dynamic call - the call.
3496   enc_class enc_java_dynamic_call_sched(method meth) %{
3497     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3498 
3499     MacroAssembler _masm(&cbuf);
3500 
3501     if (!ra_->C->in_scratch_emit_size()) {
3502       // Create a call trampoline stub for the given method.
3503       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3504       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3505       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3506       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3507       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3508 
3509       // Build relocation at call site with ic position as data.
3510       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3511              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3512              "must have one, but can't have both");
3513       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3514              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3515              "must contain instruction offset");
3516       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3517         ? _load_ic_hi_node->_cbuf_insts_offset
3518         : _load_ic_node->_cbuf_insts_offset;
3519       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3520       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3521              "should be load from TOC");
3522 
3523       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3524     }
3525 
3526     // At this point I do not have the address of the trampoline stub,
3527     // and the entry point might be too far away for bl. Pc() serves
3528     // as dummy and bl will be patched later.
3529     __ bl((address) __ pc());
3530   %}
3531 
3532   // postalloc expand emitter for virtual calls.
3533   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3534 
3535     // Create the nodes for loading the IC from the TOC.
3536     loadConLNodesTuple loadConLNodes_IC =
3537       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3538                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3539 
3540     // Create the call node.
3541     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3542     call->_method_handle_invoke = _method_handle_invoke;
3543     call->_vtable_index      = _vtable_index;
3544     call->_method            = _method;
3545     call->_bci               = _bci;
3546     call->_optimized_virtual = _optimized_virtual;
3547     call->_tf                = _tf;
3548     call->_entry_point       = _entry_point;
3549     call->_cnt               = _cnt;
3550     call->_argsize           = _argsize;
3551     call->_oop_map           = _oop_map;
3552     call->_jvms              = _jvms;
3553     call->_jvmadj            = _jvmadj;
3554     call->_in_rms            = _in_rms;
3555     call->_nesting           = _nesting;
3556 
3557     // New call needs all inputs of old call.
3558     // Req...
3559     for (uint i = 0; i < req(); ++i) {
3560       // The expanded node does not need toc any more.
3561       // Add the inline cache constant here instead. This expresses the
3562       // register of the inline cache must be live at the call.
3563       // Else we would have to adapt JVMState by -1.
3564       if (i == mach_constant_base_node_input()) {
3565         call->add_req(loadConLNodes_IC._last);
3566       } else {
3567         call->add_req(in(i));
3568       }
3569     }
3570     // ...as well as prec
3571     for (uint i = req(); i < len(); ++i) {
3572       call->add_prec(in(i));
3573     }
3574 
3575     // Remember nodes loading the inline cache into r19.
3576     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3577     call->_load_ic_node    = loadConLNodes_IC._small;
3578 
3579     // Operands for new nodes.
3580     call->_opnds[0] = _opnds[0];
3581     call->_opnds[1] = _opnds[1];
3582 
3583     // Only the inline cache is associated with a register.
3584     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3585 
3586     // Push new nodes.
3587     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3588     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3589     nodes->push(call);
3590   %}
3591 
3592   // Compound version of call dynamic
3593   // Toc is only passed so that it can be used in ins_encode statement.
3594   // In the code we have to use $constanttablebase.
3595   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3596     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3597     MacroAssembler _masm(&cbuf);
3598     int start_offset = __ offset();
3599 
3600     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3601 #if 0
3602     int vtable_index = this->_vtable_index;
3603     if (_vtable_index < 0) {
3604       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3605       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3606       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3607 
3608       // Virtual call relocation will point to ic load.
3609       address virtual_call_meta_addr = __ pc();
3610       // Load a clear inline cache.
3611       AddressLiteral empty_ic((address) Universe::non_oop_word());
3612       __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3613       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3614       // to determine who we intended to call.
3615       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3616       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3617       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3618              "Fix constant in ret_addr_offset()");
3619     } else {
3620       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3621       // Go thru the vtable. Get receiver klass. Receiver already
3622       // checked for non-null. If we'll go thru a C2I adapter, the
3623       // interpreter expects method in R19_method.
3624 
3625       __ load_klass(R11_scratch1, R3);
3626 
3627       int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3628       int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3629       __ li(R19_method, v_off);
3630       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3631       // NOTE: for vtable dispatches, the vtable entry will never be
3632       // null. However it may very well end up in handle_wrong_method
3633       // if the method is abstract for the particular class.
3634       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3635       // Call target. Either compiled code or C2I adapter.
3636       __ mtctr(R11_scratch1);
3637       __ bctrl();
3638       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3639         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3640       }
3641       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3642              "Fix constant in ret_addr_offset()");
3643     }
3644 #endif
3645     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3646   %}
3647 
3648   // a runtime call
3649   enc_class enc_java_to_runtime_call (method meth) %{
3650     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3651 
3652     MacroAssembler _masm(&cbuf);
3653     const address start_pc = __ pc();
3654 
3655 #if defined(ABI_ELFv2)
3656     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3657     __ call_c(entry, relocInfo::runtime_call_type);
3658 #else
3659     // The function we're going to call.
3660     FunctionDescriptor fdtemp;
3661     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3662 
3663     Register Rtoc = R12_scratch2;
3664     // Calculate the method's TOC.
3665     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3666     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3667     // pool entries; call_c_using_toc will optimize the call.
3668     __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3669 #endif
3670 
3671     // Check the ret_addr_offset.
3672     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3673            "Fix constant in ret_addr_offset()");
3674   %}
3675 
3676   // Move to ctr for leaf call.
3677   // This enc_class is needed so that scheduler gets proper
3678   // input mapping for latency computation.
3679   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3680     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3681     MacroAssembler _masm(&cbuf);
3682     __ mtctr($src$$Register);
3683   %}
3684 
3685   // Postalloc expand emitter for runtime leaf calls.
3686   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3687     loadConLNodesTuple loadConLNodes_Entry;
3688 #if defined(ABI_ELFv2)
3689     jlong entry_address = (jlong) this->entry_point();
3690     assert(entry_address, "need address here");
3691     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3692                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3693 #else
3694     // Get the struct that describes the function we are about to call.
3695     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3696     assert(fd, "need fd here");
3697     jlong entry_address = (jlong) fd->entry();
3698     // new nodes
3699     loadConLNodesTuple loadConLNodes_Env;
3700     loadConLNodesTuple loadConLNodes_Toc;
3701 
3702     // Create nodes and operands for loading the entry point.
3703     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3704                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3705 
3706 
3707     // Create nodes and operands for loading the env pointer.
3708     if (fd->env() != NULL) {
3709       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3710                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3711     } else {
3712       loadConLNodes_Env._large_hi = NULL;
3713       loadConLNodes_Env._large_lo = NULL;
3714       loadConLNodes_Env._small    = NULL;
3715       loadConLNodes_Env._last = new loadConL16Node();
3716       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3717       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3718       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3719     }
3720 
3721     // Create nodes and operands for loading the Toc point.
3722     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3723                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3724 #endif // ABI_ELFv2
3725     // mtctr node
3726     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3727 
3728     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3729     mtctr->add_req(0, loadConLNodes_Entry._last);
3730 
3731     mtctr->_opnds[0] = new iRegLdstOper();
3732     mtctr->_opnds[1] = new iRegLdstOper();
3733 
3734     // call node
3735     MachCallLeafNode *call = new CallLeafDirectNode();
3736 
3737     call->_opnds[0] = _opnds[0];
3738     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3739 
3740     // Make the new call node look like the old one.
3741     call->_name        = _name;
3742     call->_tf          = _tf;
3743     call->_entry_point = _entry_point;
3744     call->_cnt         = _cnt;
3745     call->_argsize     = _argsize;
3746     call->_oop_map     = _oop_map;
3747     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3748     call->_jvms        = NULL;
3749     call->_jvmadj      = _jvmadj;
3750     call->_in_rms      = _in_rms;
3751     call->_nesting     = _nesting;
3752 
3753 
3754     // New call needs all inputs of old call.
3755     // Req...
3756     for (uint i = 0; i < req(); ++i) {
3757       if (i != mach_constant_base_node_input()) {
3758         call->add_req(in(i));
3759       }
3760     }
3761 
3762     // These must be reqired edges, as the registers are live up to
3763     // the call. Else the constants are handled as kills.
3764     call->add_req(mtctr);
3765 #if !defined(ABI_ELFv2)
3766     call->add_req(loadConLNodes_Env._last);
3767     call->add_req(loadConLNodes_Toc._last);
3768 #endif
3769 
3770     // ...as well as prec
3771     for (uint i = req(); i < len(); ++i) {
3772       call->add_prec(in(i));
3773     }
3774 
3775     // registers
3776     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3777 
3778     // Insert the new nodes.
3779     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3780     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
3781 #if !defined(ABI_ELFv2)
3782     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
3783     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
3784     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
3785     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
3786 #endif
3787     nodes->push(mtctr);
3788     nodes->push(call);
3789   %}
3790 %}
3791 
3792 //----------FRAME--------------------------------------------------------------
3793 // Definition of frame structure and management information.
3794 
3795 frame %{
3796   // What direction does stack grow in (assumed to be same for native & Java).
3797   stack_direction(TOWARDS_LOW);
3798 
3799   // These two registers define part of the calling convention between
3800   // compiled code and the interpreter.
3801 
3802   // Inline Cache Register or method for I2C.
3803   inline_cache_reg(R19); // R19_method
3804 
3805   // Method Oop Register when calling interpreter.
3806   interpreter_method_oop_reg(R19); // R19_method
3807 
3808   // Optional: name the operand used by cisc-spilling to access
3809   // [stack_pointer + offset].
3810   cisc_spilling_operand_name(indOffset);
3811 
3812   // Number of stack slots consumed by a Monitor enter.
3813   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3814 
3815   // Compiled code's Frame Pointer.
3816   frame_pointer(R1); // R1_SP
3817 
3818   // Interpreter stores its frame pointer in a register which is
3819   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3820   // interpreted java to compiled java.
3821   //
3822   // R14_state holds pointer to caller's cInterpreter.
3823   interpreter_frame_pointer(R14); // R14_state
3824 
3825   stack_alignment(frame::alignment_in_bytes);
3826 
3827   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3828 
3829   // Number of outgoing stack slots killed above the
3830   // out_preserve_stack_slots for calls to C. Supports the var-args
3831   // backing area for register parms.
3832   //
3833   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3834 
3835   // The after-PROLOG location of the return address. Location of
3836   // return address specifies a type (REG or STACK) and a number
3837   // representing the register number (i.e. - use a register name) or
3838   // stack slot.
3839   //
3840   // A: Link register is stored in stack slot ...
3841   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
3842   // J: Therefore, we make sure that the link register is also in R11_scratch1
3843   //    at the end of the prolog.
3844   // B: We use R20, now.
3845   //return_addr(REG R20);
3846 
3847   // G: After reading the comments made by all the luminaries on their
3848   //    failure to tell the compiler where the return address really is,
3849   //    I hardly dare to try myself.  However, I'm convinced it's in slot
3850   //    4 what apparently works and saves us some spills.
3851   return_addr(STACK 4);
3852 
3853   // This is the body of the function
3854   //
3855   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3856   //                                  uint length,      // length of array
3857   //                                  bool is_outgoing)
3858   //
3859   // The `sig' array is to be updated. sig[j] represents the location
3860   // of the j-th argument, either a register or a stack slot.
3861 
3862   // Comment taken from i486.ad:
3863   // Body of function which returns an integer array locating
3864   // arguments either in registers or in stack slots. Passed an array
3865   // of ideal registers called "sig" and a "length" count. Stack-slot
3866   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3867   // arguments for a CALLEE. Incoming stack arguments are
3868   // automatically biased by the preserve_stack_slots field above.
3869   calling_convention %{
3870     // No difference between ingoing/outgoing. Just pass false.
3871     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3872   %}
3873 
3874   // Comment taken from i486.ad:
3875   // Body of function which returns an integer array locating
3876   // arguments either in registers or in stack slots. Passed an array
3877   // of ideal registers called "sig" and a "length" count. Stack-slot
3878   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3879   // arguments for a CALLEE. Incoming stack arguments are
3880   // automatically biased by the preserve_stack_slots field above.
3881   c_calling_convention %{
3882     // This is obviously always outgoing.
3883     // C argument in register AND stack slot.
3884     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3885   %}
3886 
3887   // Location of native (C/C++) and interpreter return values. This
3888   // is specified to be the same as Java. In the 32-bit VM, long
3889   // values are actually returned from native calls in O0:O1 and
3890   // returned to the interpreter in I0:I1. The copying to and from
3891   // the register pairs is done by the appropriate call and epilog
3892   // opcodes. This simplifies the register allocator.
3893   c_return_value %{
3894     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3895             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3896             "only return normal values");
3897     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3898     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3899     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3900     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3901   %}
3902 
3903   // Location of compiled Java return values.  Same as C
3904   return_value %{
3905     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3906             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3907             "only return normal values");
3908     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3909     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3910     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3911     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3912   %}
3913 %}
3914 
3915 
3916 //----------ATTRIBUTES---------------------------------------------------------
3917 
3918 //----------Operand Attributes-------------------------------------------------
3919 op_attrib op_cost(1);          // Required cost attribute.
3920 
3921 //----------Instruction Attributes---------------------------------------------
3922 
3923 // Cost attribute. required.
3924 ins_attrib ins_cost(DEFAULT_COST);
3925 
3926 // Is this instruction a non-matching short branch variant of some
3927 // long branch? Not required.
3928 ins_attrib ins_short_branch(0);
3929 
3930 ins_attrib ins_is_TrapBasedCheckNode(true);
3931 
3932 // Number of constants.
3933 // This instruction uses the given number of constants
3934 // (optional attribute).
3935 // This is needed to determine in time whether the constant pool will
3936 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3937 // is determined. It's also used to compute the constant pool size
3938 // in Output().
3939 ins_attrib ins_num_consts(0);
3940 
3941 // Required alignment attribute (must be a power of 2) specifies the
3942 // alignment that some part of the instruction (not necessarily the
3943 // start) requires. If > 1, a compute_padding() function must be
3944 // provided for the instruction.
3945 ins_attrib ins_alignment(1);
3946 
3947 // Enforce/prohibit rematerializations.
3948 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3949 //   then rematerialization of that instruction is prohibited and the
3950 //   instruction's value will be spilled if necessary.
3951 //   Causes that MachNode::rematerialize() returns false.
3952 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3953 //   then rematerialization should be enforced and a copy of the instruction
3954 //   should be inserted if possible; rematerialization is not guaranteed.
3955 //   Note: this may result in rematerializations in front of every use.
3956 //   Causes that MachNode::rematerialize() can return true.
3957 // (optional attribute)
3958 ins_attrib ins_cannot_rematerialize(false);
3959 ins_attrib ins_should_rematerialize(false);
3960 
3961 // Instruction has variable size depending on alignment.
3962 ins_attrib ins_variable_size_depending_on_alignment(false);
3963 
3964 // Instruction is a nop.
3965 ins_attrib ins_is_nop(false);
3966 
3967 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3968 ins_attrib ins_use_mach_if_fast_lock_node(false);
3969 
3970 // Field for the toc offset of a constant.
3971 //
3972 // This is needed if the toc offset is not encodable as an immediate in
3973 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3974 // added to the toc, and from this a load with immediate is performed.
3975 // With postalloc expand, we get two nodes that require the same offset
3976 // but which don't know about each other. The offset is only known
3977 // when the constant is added to the constant pool during emitting.
3978 // It is generated in the 'hi'-node adding the upper bits, and saved
3979 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
3980 // the offset from there when it gets encoded.
3981 ins_attrib ins_field_const_toc_offset(0);
3982 ins_attrib ins_field_const_toc_offset_hi_node(0);
3983 
3984 // A field that can hold the instructions offset in the code buffer.
3985 // Set in the nodes emitter.
3986 ins_attrib ins_field_cbuf_insts_offset(-1);
3987 
3988 // Fields for referencing a call's load-IC-node.
3989 // If the toc offset can not be encoded as an immediate in a load, we
3990 // use two nodes.
3991 ins_attrib ins_field_load_ic_hi_node(0);
3992 ins_attrib ins_field_load_ic_node(0);
3993 
3994 //----------OPERANDS-----------------------------------------------------------
3995 // Operand definitions must precede instruction definitions for correct
3996 // parsing in the ADLC because operands constitute user defined types
3997 // which are used in instruction definitions.
3998 //
3999 // Formats are generated automatically for constants and base registers.
4000 
4001 //----------Simple Operands----------------------------------------------------
4002 // Immediate Operands
4003 
4004 // Integer Immediate: 32-bit
4005 operand immI() %{
4006   match(ConI);
4007   op_cost(40);
4008   format %{ %}
4009   interface(CONST_INTER);
4010 %}
4011 
4012 operand immI8() %{
4013   predicate(Assembler::is_simm(n->get_int(), 8));
4014   op_cost(0);
4015   match(ConI);
4016   format %{ %}
4017   interface(CONST_INTER);
4018 %}
4019 
4020 // Integer Immediate: 16-bit
4021 operand immI16() %{
4022   predicate(Assembler::is_simm(n->get_int(), 16));
4023   op_cost(0);
4024   match(ConI);
4025   format %{ %}
4026   interface(CONST_INTER);
4027 %}
4028 
4029 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4030 operand immIhi16() %{
4031   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4032   match(ConI);
4033   op_cost(0);
4034   format %{ %}
4035   interface(CONST_INTER);
4036 %}
4037 
4038 operand immInegpow2() %{
4039   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4040   match(ConI);
4041   op_cost(0);
4042   format %{ %}
4043   interface(CONST_INTER);
4044 %}
4045 
4046 operand immIpow2minus1() %{
4047   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4048   match(ConI);
4049   op_cost(0);
4050   format %{ %}
4051   interface(CONST_INTER);
4052 %}
4053 
4054 operand immIpowerOf2() %{
4055   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4056   match(ConI);
4057   op_cost(0);
4058   format %{ %}
4059   interface(CONST_INTER);
4060 %}
4061 
4062 // Unsigned Integer Immediate: the values 0-31
4063 operand uimmI5() %{
4064   predicate(Assembler::is_uimm(n->get_int(), 5));
4065   match(ConI);
4066   op_cost(0);
4067   format %{ %}
4068   interface(CONST_INTER);
4069 %}
4070 
4071 // Unsigned Integer Immediate: 6-bit
4072 operand uimmI6() %{
4073   predicate(Assembler::is_uimm(n->get_int(), 6));
4074   match(ConI);
4075   op_cost(0);
4076   format %{ %}
4077   interface(CONST_INTER);
4078 %}
4079 
4080 // Unsigned Integer Immediate:  6-bit int, greater than 32
4081 operand uimmI6_ge32() %{
4082   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4083   match(ConI);
4084   op_cost(0);
4085   format %{ %}
4086   interface(CONST_INTER);
4087 %}
4088 
4089 // Unsigned Integer Immediate: 15-bit
4090 operand uimmI15() %{
4091   predicate(Assembler::is_uimm(n->get_int(), 15));
4092   match(ConI);
4093   op_cost(0);
4094   format %{ %}
4095   interface(CONST_INTER);
4096 %}
4097 
4098 // Unsigned Integer Immediate: 16-bit
4099 operand uimmI16() %{
4100   predicate(Assembler::is_uimm(n->get_int(), 16));
4101   match(ConI);
4102   op_cost(0);
4103   format %{ %}
4104   interface(CONST_INTER);
4105 %}
4106 
4107 // constant 'int 0'.
4108 operand immI_0() %{
4109   predicate(n->get_int() == 0);
4110   match(ConI);
4111   op_cost(0);
4112   format %{ %}
4113   interface(CONST_INTER);
4114 %}
4115 
4116 // constant 'int 1'.
4117 operand immI_1() %{
4118   predicate(n->get_int() == 1);
4119   match(ConI);
4120   op_cost(0);
4121   format %{ %}
4122   interface(CONST_INTER);
4123 %}
4124 
4125 // constant 'int -1'.
4126 operand immI_minus1() %{
4127   predicate(n->get_int() == -1);
4128   match(ConI);
4129   op_cost(0);
4130   format %{ %}
4131   interface(CONST_INTER);
4132 %}
4133 
4134 // int value 16.
4135 operand immI_16() %{
4136   predicate(n->get_int() == 16);
4137   match(ConI);
4138   op_cost(0);
4139   format %{ %}
4140   interface(CONST_INTER);
4141 %}
4142 
4143 // int value 24.
4144 operand immI_24() %{
4145   predicate(n->get_int() == 24);
4146   match(ConI);
4147   op_cost(0);
4148   format %{ %}
4149   interface(CONST_INTER);
4150 %}
4151 
4152 // Compressed oops constants
4153 // Pointer Immediate
4154 operand immN() %{
4155   match(ConN);
4156 
4157   op_cost(10);
4158   format %{ %}
4159   interface(CONST_INTER);
4160 %}
4161 
4162 // NULL Pointer Immediate
4163 operand immN_0() %{
4164   predicate(n->get_narrowcon() == 0);
4165   match(ConN);
4166 
4167   op_cost(0);
4168   format %{ %}
4169   interface(CONST_INTER);
4170 %}
4171 
4172 // Compressed klass constants
4173 operand immNKlass() %{
4174   match(ConNKlass);
4175 
4176   op_cost(0);
4177   format %{ %}
4178   interface(CONST_INTER);
4179 %}
4180 
4181 // This operand can be used to avoid matching of an instruct
4182 // with chain rule.
4183 operand immNKlass_NM() %{
4184   match(ConNKlass);
4185   predicate(false);
4186   op_cost(0);
4187   format %{ %}
4188   interface(CONST_INTER);
4189 %}
4190 
4191 // Pointer Immediate: 64-bit
4192 operand immP() %{
4193   match(ConP);
4194   op_cost(0);
4195   format %{ %}
4196   interface(CONST_INTER);
4197 %}
4198 
4199 // Operand to avoid match of loadConP.
4200 // This operand can be used to avoid matching of an instruct
4201 // with chain rule.
4202 operand immP_NM() %{
4203   match(ConP);
4204   predicate(false);
4205   op_cost(0);
4206   format %{ %}
4207   interface(CONST_INTER);
4208 %}
4209 
4210 // costant 'pointer 0'.
4211 operand immP_0() %{
4212   predicate(n->get_ptr() == 0);
4213   match(ConP);
4214   op_cost(0);
4215   format %{ %}
4216   interface(CONST_INTER);
4217 %}
4218 
4219 // pointer 0x0 or 0x1
4220 operand immP_0or1() %{
4221   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4222   match(ConP);
4223   op_cost(0);
4224   format %{ %}
4225   interface(CONST_INTER);
4226 %}
4227 
4228 operand immL() %{
4229   match(ConL);
4230   op_cost(40);
4231   format %{ %}
4232   interface(CONST_INTER);
4233 %}
4234 
4235 // Long Immediate: 16-bit
4236 operand immL16() %{
4237   predicate(Assembler::is_simm(n->get_long(), 16));
4238   match(ConL);
4239   op_cost(0);
4240   format %{ %}
4241   interface(CONST_INTER);
4242 %}
4243 
4244 // Long Immediate: 16-bit, 4-aligned
4245 operand immL16Alg4() %{
4246   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4247   match(ConL);
4248   op_cost(0);
4249   format %{ %}
4250   interface(CONST_INTER);
4251 %}
4252 
4253 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4254 operand immL32hi16() %{
4255   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4256   match(ConL);
4257   op_cost(0);
4258   format %{ %}
4259   interface(CONST_INTER);
4260 %}
4261 
4262 // Long Immediate: 32-bit
4263 operand immL32() %{
4264   predicate(Assembler::is_simm(n->get_long(), 32));
4265   match(ConL);
4266   op_cost(0);
4267   format %{ %}
4268   interface(CONST_INTER);
4269 %}
4270 
4271 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4272 operand immLhighest16() %{
4273   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4274   match(ConL);
4275   op_cost(0);
4276   format %{ %}
4277   interface(CONST_INTER);
4278 %}
4279 
4280 operand immLnegpow2() %{
4281   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4282   match(ConL);
4283   op_cost(0);
4284   format %{ %}
4285   interface(CONST_INTER);
4286 %}
4287 
4288 operand immLpow2minus1() %{
4289   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4290             (n->get_long() != (jlong)0xffffffffffffffffL));
4291   match(ConL);
4292   op_cost(0);
4293   format %{ %}
4294   interface(CONST_INTER);
4295 %}
4296 
4297 // constant 'long 0'.
4298 operand immL_0() %{
4299   predicate(n->get_long() == 0L);
4300   match(ConL);
4301   op_cost(0);
4302   format %{ %}
4303   interface(CONST_INTER);
4304 %}
4305 
4306 // constat ' long -1'.
4307 operand immL_minus1() %{
4308   predicate(n->get_long() == -1L);
4309   match(ConL);
4310   op_cost(0);
4311   format %{ %}
4312   interface(CONST_INTER);
4313 %}
4314 
4315 // Long Immediate: low 32-bit mask
4316 operand immL_32bits() %{
4317   predicate(n->get_long() == 0xFFFFFFFFL);
4318   match(ConL);
4319   op_cost(0);
4320   format %{ %}
4321   interface(CONST_INTER);
4322 %}
4323 
4324 // Unsigned Long Immediate: 16-bit
4325 operand uimmL16() %{
4326   predicate(Assembler::is_uimm(n->get_long(), 16));
4327   match(ConL);
4328   op_cost(0);
4329   format %{ %}
4330   interface(CONST_INTER);
4331 %}
4332 
4333 // Float Immediate
4334 operand immF() %{
4335   match(ConF);
4336   op_cost(40);
4337   format %{ %}
4338   interface(CONST_INTER);
4339 %}
4340 
4341 // Float Immediate: +0.0f.
4342 operand immF_0() %{
4343   predicate(jint_cast(n->getf()) == 0);
4344   match(ConF);
4345 
4346   op_cost(0);
4347   format %{ %}
4348   interface(CONST_INTER);
4349 %}
4350 
4351 // Double Immediate
4352 operand immD() %{
4353   match(ConD);
4354   op_cost(40);
4355   format %{ %}
4356   interface(CONST_INTER);
4357 %}
4358 
4359 // Integer Register Operands
4360 // Integer Destination Register
4361 // See definition of reg_class bits32_reg_rw.
4362 operand iRegIdst() %{
4363   constraint(ALLOC_IN_RC(bits32_reg_rw));
4364   match(RegI);
4365   match(rscratch1RegI);
4366   match(rscratch2RegI);
4367   match(rarg1RegI);
4368   match(rarg2RegI);
4369   match(rarg3RegI);
4370   match(rarg4RegI);
4371   format %{ %}
4372   interface(REG_INTER);
4373 %}
4374 
4375 // Integer Source Register
4376 // See definition of reg_class bits32_reg_ro.
4377 operand iRegIsrc() %{
4378   constraint(ALLOC_IN_RC(bits32_reg_ro));
4379   match(RegI);
4380   match(rscratch1RegI);
4381   match(rscratch2RegI);
4382   match(rarg1RegI);
4383   match(rarg2RegI);
4384   match(rarg3RegI);
4385   match(rarg4RegI);
4386   format %{ %}
4387   interface(REG_INTER);
4388 %}
4389 
4390 operand rscratch1RegI() %{
4391   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4392   match(iRegIdst);
4393   format %{ %}
4394   interface(REG_INTER);
4395 %}
4396 
4397 operand rscratch2RegI() %{
4398   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4399   match(iRegIdst);
4400   format %{ %}
4401   interface(REG_INTER);
4402 %}
4403 
4404 operand rarg1RegI() %{
4405   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4406   match(iRegIdst);
4407   format %{ %}
4408   interface(REG_INTER);
4409 %}
4410 
4411 operand rarg2RegI() %{
4412   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4413   match(iRegIdst);
4414   format %{ %}
4415   interface(REG_INTER);
4416 %}
4417 
4418 operand rarg3RegI() %{
4419   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4420   match(iRegIdst);
4421   format %{ %}
4422   interface(REG_INTER);
4423 %}
4424 
4425 operand rarg4RegI() %{
4426   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4427   match(iRegIdst);
4428   format %{ %}
4429   interface(REG_INTER);
4430 %}
4431 
4432 operand rarg1RegL() %{
4433   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4434   match(iRegLdst);
4435   format %{ %}
4436   interface(REG_INTER);
4437 %}
4438 
4439 operand rarg2RegL() %{
4440   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4441   match(iRegLdst);
4442   format %{ %}
4443   interface(REG_INTER);
4444 %}
4445 
4446 operand rarg3RegL() %{
4447   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4448   match(iRegLdst);
4449   format %{ %}
4450   interface(REG_INTER);
4451 %}
4452 
4453 operand rarg4RegL() %{
4454   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4455   match(iRegLdst);
4456   format %{ %}
4457   interface(REG_INTER);
4458 %}
4459 
4460 // Pointer Destination Register
4461 // See definition of reg_class bits64_reg_rw.
4462 operand iRegPdst() %{
4463   constraint(ALLOC_IN_RC(bits64_reg_rw));
4464   match(RegP);
4465   match(rscratch1RegP);
4466   match(rscratch2RegP);
4467   match(rarg1RegP);
4468   match(rarg2RegP);
4469   match(rarg3RegP);
4470   match(rarg4RegP);
4471   format %{ %}
4472   interface(REG_INTER);
4473 %}
4474 
4475 // Pointer Destination Register
4476 // Operand not using r11 and r12 (killed in epilog).
4477 operand iRegPdstNoScratch() %{
4478   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4479   match(RegP);
4480   match(rarg1RegP);
4481   match(rarg2RegP);
4482   match(rarg3RegP);
4483   match(rarg4RegP);
4484   format %{ %}
4485   interface(REG_INTER);
4486 %}
4487 
4488 // Pointer Source Register
4489 // See definition of reg_class bits64_reg_ro.
4490 operand iRegPsrc() %{
4491   constraint(ALLOC_IN_RC(bits64_reg_ro));
4492   match(RegP);
4493   match(iRegPdst);
4494   match(rscratch1RegP);
4495   match(rscratch2RegP);
4496   match(rarg1RegP);
4497   match(rarg2RegP);
4498   match(rarg3RegP);
4499   match(rarg4RegP);
4500   match(threadRegP);
4501   format %{ %}
4502   interface(REG_INTER);
4503 %}
4504 
4505 // Thread operand.
4506 operand threadRegP() %{
4507   constraint(ALLOC_IN_RC(thread_bits64_reg));
4508   match(iRegPdst);
4509   format %{ "R16" %}
4510   interface(REG_INTER);
4511 %}
4512 
4513 operand rscratch1RegP() %{
4514   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4515   match(iRegPdst);
4516   format %{ "R11" %}
4517   interface(REG_INTER);
4518 %}
4519 
4520 operand rscratch2RegP() %{
4521   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4522   match(iRegPdst);
4523   format %{ %}
4524   interface(REG_INTER);
4525 %}
4526 
4527 operand rarg1RegP() %{
4528   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4529   match(iRegPdst);
4530   format %{ %}
4531   interface(REG_INTER);
4532 %}
4533 
4534 operand rarg2RegP() %{
4535   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4536   match(iRegPdst);
4537   format %{ %}
4538   interface(REG_INTER);
4539 %}
4540 
4541 operand rarg3RegP() %{
4542   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4543   match(iRegPdst);
4544   format %{ %}
4545   interface(REG_INTER);
4546 %}
4547 
4548 operand rarg4RegP() %{
4549   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4550   match(iRegPdst);
4551   format %{ %}
4552   interface(REG_INTER);
4553 %}
4554 
4555 operand iRegNsrc() %{
4556   constraint(ALLOC_IN_RC(bits32_reg_ro));
4557   match(RegN);
4558   match(iRegNdst);
4559 
4560   format %{ %}
4561   interface(REG_INTER);
4562 %}
4563 
4564 operand iRegNdst() %{
4565   constraint(ALLOC_IN_RC(bits32_reg_rw));
4566   match(RegN);
4567 
4568   format %{ %}
4569   interface(REG_INTER);
4570 %}
4571 
4572 // Long Destination Register
4573 // See definition of reg_class bits64_reg_rw.
4574 operand iRegLdst() %{
4575   constraint(ALLOC_IN_RC(bits64_reg_rw));
4576   match(RegL);
4577   match(rscratch1RegL);
4578   match(rscratch2RegL);
4579   format %{ %}
4580   interface(REG_INTER);
4581 %}
4582 
4583 // Long Source Register
4584 // See definition of reg_class bits64_reg_ro.
4585 operand iRegLsrc() %{
4586   constraint(ALLOC_IN_RC(bits64_reg_ro));
4587   match(RegL);
4588   match(iRegLdst);
4589   match(rscratch1RegL);
4590   match(rscratch2RegL);
4591   format %{ %}
4592   interface(REG_INTER);
4593 %}
4594 
4595 // Special operand for ConvL2I.
4596 operand iRegL2Isrc(iRegLsrc reg) %{
4597   constraint(ALLOC_IN_RC(bits64_reg_ro));
4598   match(ConvL2I reg);
4599   format %{ "ConvL2I($reg)" %}
4600   interface(REG_INTER)
4601 %}
4602 
4603 operand rscratch1RegL() %{
4604   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4605   match(RegL);
4606   format %{ %}
4607   interface(REG_INTER);
4608 %}
4609 
4610 operand rscratch2RegL() %{
4611   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4612   match(RegL);
4613   format %{ %}
4614   interface(REG_INTER);
4615 %}
4616 
4617 // Condition Code Flag Registers
4618 operand flagsReg() %{
4619   constraint(ALLOC_IN_RC(int_flags));
4620   match(RegFlags);
4621   format %{ %}
4622   interface(REG_INTER);
4623 %}
4624 
4625 operand flagsRegSrc() %{
4626   constraint(ALLOC_IN_RC(int_flags_ro));
4627   match(RegFlags);
4628   match(flagsReg);
4629   match(flagsRegCR0);
4630   format %{ %}
4631   interface(REG_INTER);
4632 %}
4633 
4634 // Condition Code Flag Register CR0
4635 operand flagsRegCR0() %{
4636   constraint(ALLOC_IN_RC(int_flags_CR0));
4637   match(RegFlags);
4638   format %{ "CR0" %}
4639   interface(REG_INTER);
4640 %}
4641 
4642 operand flagsRegCR1() %{
4643   constraint(ALLOC_IN_RC(int_flags_CR1));
4644   match(RegFlags);
4645   format %{ "CR1" %}
4646   interface(REG_INTER);
4647 %}
4648 
4649 operand flagsRegCR6() %{
4650   constraint(ALLOC_IN_RC(int_flags_CR6));
4651   match(RegFlags);
4652   format %{ "CR6" %}
4653   interface(REG_INTER);
4654 %}
4655 
4656 operand regCTR() %{
4657   constraint(ALLOC_IN_RC(ctr_reg));
4658   // RegFlags should work. Introducing a RegSpecial type would cause a
4659   // lot of changes.
4660   match(RegFlags);
4661   format %{"SR_CTR" %}
4662   interface(REG_INTER);
4663 %}
4664 
4665 operand regD() %{
4666   constraint(ALLOC_IN_RC(dbl_reg));
4667   match(RegD);
4668   format %{ %}
4669   interface(REG_INTER);
4670 %}
4671 
4672 operand regF() %{
4673   constraint(ALLOC_IN_RC(flt_reg));
4674   match(RegF);
4675   format %{ %}
4676   interface(REG_INTER);
4677 %}
4678 
4679 // Special Registers
4680 
4681 // Method Register
4682 operand inline_cache_regP(iRegPdst reg) %{
4683   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4684   match(reg);
4685   format %{ %}
4686   interface(REG_INTER);
4687 %}
4688 
4689 operand compiler_method_oop_regP(iRegPdst reg) %{
4690   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4691   match(reg);
4692   format %{ %}
4693   interface(REG_INTER);
4694 %}
4695 
4696 operand interpreter_method_oop_regP(iRegPdst reg) %{
4697   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4698   match(reg);
4699   format %{ %}
4700   interface(REG_INTER);
4701 %}
4702 
4703 // Operands to remove register moves in unscaled mode.
4704 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4705 operand iRegP2N(iRegPsrc reg) %{
4706   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4707   constraint(ALLOC_IN_RC(bits64_reg_ro));
4708   match(EncodeP reg);
4709   format %{ "$reg" %}
4710   interface(REG_INTER)
4711 %}
4712 
4713 operand iRegN2P(iRegNsrc reg) %{
4714   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4715   constraint(ALLOC_IN_RC(bits32_reg_ro));
4716   match(DecodeN reg);
4717   format %{ "$reg" %}
4718   interface(REG_INTER)
4719 %}
4720 
4721 operand iRegN2P_klass(iRegNsrc reg) %{
4722   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4723   constraint(ALLOC_IN_RC(bits32_reg_ro));
4724   match(DecodeNKlass reg);
4725   format %{ "$reg" %}
4726   interface(REG_INTER)
4727 %}
4728 
4729 //----------Complex Operands---------------------------------------------------
4730 // Indirect Memory Reference
4731 operand indirect(iRegPsrc reg) %{
4732   constraint(ALLOC_IN_RC(bits64_reg_ro));
4733   match(reg);
4734   op_cost(100);
4735   format %{ "[$reg]" %}
4736   interface(MEMORY_INTER) %{
4737     base($reg);
4738     index(0x0);
4739     scale(0x0);
4740     disp(0x0);
4741   %}
4742 %}
4743 
4744 // Indirect with Offset
4745 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4746   constraint(ALLOC_IN_RC(bits64_reg_ro));
4747   match(AddP reg offset);
4748   op_cost(100);
4749   format %{ "[$reg + $offset]" %}
4750   interface(MEMORY_INTER) %{
4751     base($reg);
4752     index(0x0);
4753     scale(0x0);
4754     disp($offset);
4755   %}
4756 %}
4757 
4758 // Indirect with 4-aligned Offset
4759 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4760   constraint(ALLOC_IN_RC(bits64_reg_ro));
4761   match(AddP reg offset);
4762   op_cost(100);
4763   format %{ "[$reg + $offset]" %}
4764   interface(MEMORY_INTER) %{
4765     base($reg);
4766     index(0x0);
4767     scale(0x0);
4768     disp($offset);
4769   %}
4770 %}
4771 
4772 //----------Complex Operands for Compressed OOPs-------------------------------
4773 // Compressed OOPs with narrow_oop_shift == 0.
4774 
4775 // Indirect Memory Reference, compressed OOP
4776 operand indirectNarrow(iRegNsrc reg) %{
4777   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4778   constraint(ALLOC_IN_RC(bits64_reg_ro));
4779   match(DecodeN reg);
4780   op_cost(100);
4781   format %{ "[$reg]" %}
4782   interface(MEMORY_INTER) %{
4783     base($reg);
4784     index(0x0);
4785     scale(0x0);
4786     disp(0x0);
4787   %}
4788 %}
4789 
4790 operand indirectNarrow_klass(iRegNsrc reg) %{
4791   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4792   constraint(ALLOC_IN_RC(bits64_reg_ro));
4793   match(DecodeNKlass reg);
4794   op_cost(100);
4795   format %{ "[$reg]" %}
4796   interface(MEMORY_INTER) %{
4797     base($reg);
4798     index(0x0);
4799     scale(0x0);
4800     disp(0x0);
4801   %}
4802 %}
4803 
4804 // Indirect with Offset, compressed OOP
4805 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4806   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4807   constraint(ALLOC_IN_RC(bits64_reg_ro));
4808   match(AddP (DecodeN reg) offset);
4809   op_cost(100);
4810   format %{ "[$reg + $offset]" %}
4811   interface(MEMORY_INTER) %{
4812     base($reg);
4813     index(0x0);
4814     scale(0x0);
4815     disp($offset);
4816   %}
4817 %}
4818 
4819 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4820   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4821   constraint(ALLOC_IN_RC(bits64_reg_ro));
4822   match(AddP (DecodeNKlass reg) offset);
4823   op_cost(100);
4824   format %{ "[$reg + $offset]" %}
4825   interface(MEMORY_INTER) %{
4826     base($reg);
4827     index(0x0);
4828     scale(0x0);
4829     disp($offset);
4830   %}
4831 %}
4832 
4833 // Indirect with 4-aligned Offset, compressed OOP
4834 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4835   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4836   constraint(ALLOC_IN_RC(bits64_reg_ro));
4837   match(AddP (DecodeN reg) offset);
4838   op_cost(100);
4839   format %{ "[$reg + $offset]" %}
4840   interface(MEMORY_INTER) %{
4841     base($reg);
4842     index(0x0);
4843     scale(0x0);
4844     disp($offset);
4845   %}
4846 %}
4847 
4848 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4849   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4850   constraint(ALLOC_IN_RC(bits64_reg_ro));
4851   match(AddP (DecodeNKlass reg) offset);
4852   op_cost(100);
4853   format %{ "[$reg + $offset]" %}
4854   interface(MEMORY_INTER) %{
4855     base($reg);
4856     index(0x0);
4857     scale(0x0);
4858     disp($offset);
4859   %}
4860 %}
4861 
4862 //----------Special Memory Operands--------------------------------------------
4863 // Stack Slot Operand
4864 //
4865 // This operand is used for loading and storing temporary values on
4866 // the stack where a match requires a value to flow through memory.
4867 operand stackSlotI(sRegI reg) %{
4868   constraint(ALLOC_IN_RC(stack_slots));
4869   op_cost(100);
4870   //match(RegI);
4871   format %{ "[sp+$reg]" %}
4872   interface(MEMORY_INTER) %{
4873     base(0x1);   // R1_SP
4874     index(0x0);
4875     scale(0x0);
4876     disp($reg);  // Stack Offset
4877   %}
4878 %}
4879 
4880 operand stackSlotL(sRegL reg) %{
4881   constraint(ALLOC_IN_RC(stack_slots));
4882   op_cost(100);
4883   //match(RegL);
4884   format %{ "[sp+$reg]" %}
4885   interface(MEMORY_INTER) %{
4886     base(0x1);   // R1_SP
4887     index(0x0);
4888     scale(0x0);
4889     disp($reg);  // Stack Offset
4890   %}
4891 %}
4892 
4893 operand stackSlotP(sRegP reg) %{
4894   constraint(ALLOC_IN_RC(stack_slots));
4895   op_cost(100);
4896   //match(RegP);
4897   format %{ "[sp+$reg]" %}
4898   interface(MEMORY_INTER) %{
4899     base(0x1);   // R1_SP
4900     index(0x0);
4901     scale(0x0);
4902     disp($reg);  // Stack Offset
4903   %}
4904 %}
4905 
4906 operand stackSlotF(sRegF reg) %{
4907   constraint(ALLOC_IN_RC(stack_slots));
4908   op_cost(100);
4909   //match(RegF);
4910   format %{ "[sp+$reg]" %}
4911   interface(MEMORY_INTER) %{
4912     base(0x1);   // R1_SP
4913     index(0x0);
4914     scale(0x0);
4915     disp($reg);  // Stack Offset
4916   %}
4917 %}
4918 
4919 operand stackSlotD(sRegD reg) %{
4920   constraint(ALLOC_IN_RC(stack_slots));
4921   op_cost(100);
4922   //match(RegD);
4923   format %{ "[sp+$reg]" %}
4924   interface(MEMORY_INTER) %{
4925     base(0x1);   // R1_SP
4926     index(0x0);
4927     scale(0x0);
4928     disp($reg);  // Stack Offset
4929   %}
4930 %}
4931 
4932 // Operands for expressing Control Flow
4933 // NOTE: Label is a predefined operand which should not be redefined in
4934 //       the AD file. It is generically handled within the ADLC.
4935 
4936 //----------Conditional Branch Operands----------------------------------------
4937 // Comparison Op
4938 //
4939 // This is the operation of the comparison, and is limited to the
4940 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4941 // (!=).
4942 //
4943 // Other attributes of the comparison, such as unsignedness, are specified
4944 // by the comparison instruction that sets a condition code flags register.
4945 // That result is represented by a flags operand whose subtype is appropriate
4946 // to the unsignedness (etc.) of the comparison.
4947 //
4948 // Later, the instruction which matches both the Comparison Op (a Bool) and
4949 // the flags (produced by the Cmp) specifies the coding of the comparison op
4950 // by matching a specific subtype of Bool operand below.
4951 
4952 // When used for floating point comparisons: unordered same as less.
4953 operand cmpOp() %{
4954   match(Bool);
4955   format %{ "" %}
4956   interface(COND_INTER) %{
4957                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4958                            //           BO          &  BI
4959     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
4960     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
4961     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
4962     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
4963     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
4964     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
4965     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
4966     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
4967   %}
4968 %}
4969 
4970 //----------OPERAND CLASSES----------------------------------------------------
4971 // Operand Classes are groups of operands that are used to simplify
4972 // instruction definitions by not requiring the AD writer to specify
4973 // seperate instructions for every form of operand when the
4974 // instruction accepts multiple operand types with the same basic
4975 // encoding and format. The classic case of this is memory operands.
4976 // Indirect is not included since its use is limited to Compare & Swap.
4977 
4978 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4979 // Memory operand where offsets are 4-aligned. Required for ld, std.
4980 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4981 opclass indirectMemory(indirect, indirectNarrow);
4982 
4983 // Special opclass for I and ConvL2I.
4984 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4985 
4986 // Operand classes to match encode and decode. iRegN_P2N is only used
4987 // for storeN. I have never seen an encode node elsewhere.
4988 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4989 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4990 
4991 //----------PIPELINE-----------------------------------------------------------
4992 
4993 pipeline %{
4994 
4995 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4996 // J. Res. & Dev., No. 1, Jan. 2002.
4997 
4998 //----------ATTRIBUTES---------------------------------------------------------
4999 attributes %{
5000 
5001   // Power4 instructions are of fixed length.
5002   fixed_size_instructions;
5003 
5004   // TODO: if `bundle' means number of instructions fetched
5005   // per cycle, this is 8. If `bundle' means Power4 `group', that is
5006   // max instructions issued per cycle, this is 5.
5007   max_instructions_per_bundle = 8;
5008 
5009   // A Power4 instruction is 4 bytes long.
5010   instruction_unit_size = 4;
5011 
5012   // The Power4 processor fetches 64 bytes...
5013   instruction_fetch_unit_size = 64;
5014 
5015   // ...in one line
5016   instruction_fetch_units = 1
5017 
5018   // Unused, list one so that array generated by adlc is not empty.
5019   // Aix compiler chokes if _nop_count = 0.
5020   nops(fxNop);
5021 %}
5022 
5023 //----------RESOURCES----------------------------------------------------------
5024 // Resources are the functional units available to the machine
5025 resources(
5026    PPC_BR,         // branch unit
5027    PPC_CR,         // condition unit
5028    PPC_FX1,        // integer arithmetic unit 1
5029    PPC_FX2,        // integer arithmetic unit 2
5030    PPC_LDST1,      // load/store unit 1
5031    PPC_LDST2,      // load/store unit 2
5032    PPC_FP1,        // float arithmetic unit 1
5033    PPC_FP2,        // float arithmetic unit 2
5034    PPC_LDST = PPC_LDST1 | PPC_LDST2,
5035    PPC_FX = PPC_FX1 | PPC_FX2,
5036    PPC_FP = PPC_FP1 | PPC_FP2
5037  );
5038 
5039 //----------PIPELINE DESCRIPTION-----------------------------------------------
5040 // Pipeline Description specifies the stages in the machine's pipeline
5041 pipe_desc(
5042    // Power4 longest pipeline path
5043    PPC_IF,   // instruction fetch
5044    PPC_IC,
5045    //PPC_BP, // branch prediction
5046    PPC_D0,   // decode
5047    PPC_D1,   // decode
5048    PPC_D2,   // decode
5049    PPC_D3,   // decode
5050    PPC_Xfer1,
5051    PPC_GD,   // group definition
5052    PPC_MP,   // map
5053    PPC_ISS,  // issue
5054    PPC_RF,   // resource fetch
5055    PPC_EX1,  // execute (all units)
5056    PPC_EX2,  // execute (FP, LDST)
5057    PPC_EX3,  // execute (FP, LDST)
5058    PPC_EX4,  // execute (FP)
5059    PPC_EX5,  // execute (FP)
5060    PPC_EX6,  // execute (FP)
5061    PPC_WB,   // write back
5062    PPC_Xfer2,
5063    PPC_CP
5064  );
5065 
5066 //----------PIPELINE CLASSES---------------------------------------------------
5067 // Pipeline Classes describe the stages in which input and output are
5068 // referenced by the hardware pipeline.
5069 
5070 // Simple pipeline classes.
5071 
5072 // Default pipeline class.
5073 pipe_class pipe_class_default() %{
5074   single_instruction;
5075   fixed_latency(2);
5076 %}
5077 
5078 // Pipeline class for empty instructions.
5079 pipe_class pipe_class_empty() %{
5080   single_instruction;
5081   fixed_latency(0);
5082 %}
5083 
5084 // Pipeline class for compares.
5085 pipe_class pipe_class_compare() %{
5086   single_instruction;
5087   fixed_latency(16);
5088 %}
5089 
5090 // Pipeline class for traps.
5091 pipe_class pipe_class_trap() %{
5092   single_instruction;
5093   fixed_latency(100);
5094 %}
5095 
5096 // Pipeline class for memory operations.
5097 pipe_class pipe_class_memory() %{
5098   single_instruction;
5099   fixed_latency(16);
5100 %}
5101 
5102 // Pipeline class for call.
5103 pipe_class pipe_class_call() %{
5104   single_instruction;
5105   fixed_latency(100);
5106 %}
5107 
5108 // Define the class for the Nop node.
5109 define %{
5110    MachNop = pipe_class_default;
5111 %}
5112 
5113 %}
5114 
5115 //----------INSTRUCTIONS-------------------------------------------------------
5116 
5117 // Naming of instructions:
5118 //   opA_operB / opA_operB_operC:
5119 //     Operation 'op' with one or two source operands 'oper'. Result
5120 //     type is A, source operand types are B and C.
5121 //     Iff A == B == C, B and C are left out.
5122 //
5123 // The instructions are ordered according to the following scheme:
5124 //  - loads
5125 //  - load constants
5126 //  - prefetch
5127 //  - store
5128 //  - encode/decode
5129 //  - membar
5130 //  - conditional moves
5131 //  - compare & swap
5132 //  - arithmetic and logic operations
5133 //    * int: Add, Sub, Mul, Div, Mod
5134 //    * int: lShift, arShift, urShift, rot
5135 //    * float: Add, Sub, Mul, Div
5136 //    * and, or, xor ...
5137 //  - register moves: float <-> int, reg <-> stack, repl
5138 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5139 //  - conv (low level type cast requiring bit changes (sign extend etc)
5140 //  - compares, range & zero checks.
5141 //  - branches
5142 //  - complex operations, intrinsics, min, max, replicate
5143 //  - lock
5144 //  - Calls
5145 //
5146 // If there are similar instructions with different types they are sorted:
5147 // int before float
5148 // small before big
5149 // signed before unsigned
5150 // e.g., loadS before loadUS before loadI before loadF.
5151 
5152 
5153 //----------Load/Store Instructions--------------------------------------------
5154 
5155 //----------Load Instructions--------------------------------------------------
5156 
5157 // Converts byte to int.
5158 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5159 // reuses the 'amount' operand, but adlc expects that operand specification
5160 // and operands in match rule are equivalent.
5161 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5162   effect(DEF dst, USE src);
5163   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5164   size(4);
5165   ins_encode %{
5166     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5167     __ extsb($dst$$Register, $src$$Register);
5168   %}
5169   ins_pipe(pipe_class_default);
5170 %}
5171 
5172 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5173   // match-rule, false predicate
5174   match(Set dst (LoadB mem));
5175   predicate(false);
5176 
5177   format %{ "LBZ     $dst, $mem" %}
5178   size(4);
5179   ins_encode( enc_lbz(dst, mem) );
5180   ins_pipe(pipe_class_memory);
5181 %}
5182 
5183 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5184   // match-rule, false predicate
5185   match(Set dst (LoadB mem));
5186   predicate(false);
5187 
5188   format %{ "LBZ     $dst, $mem\n\t"
5189             "TWI     $dst\n\t"
5190             "ISYNC" %}
5191   size(12);
5192   ins_encode( enc_lbz_ac(dst, mem) );
5193   ins_pipe(pipe_class_memory);
5194 %}
5195 
5196 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5197 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5198   match(Set dst (LoadB mem));
5199   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5200   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5201   expand %{
5202     iRegIdst tmp;
5203     loadUB_indirect(tmp, mem);
5204     convB2I_reg_2(dst, tmp);
5205   %}
5206 %}
5207 
5208 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5209   match(Set dst (LoadB mem));
5210   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5211   expand %{
5212     iRegIdst tmp;
5213     loadUB_indirect_ac(tmp, mem);
5214     convB2I_reg_2(dst, tmp);
5215   %}
5216 %}
5217 
5218 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5219   // match-rule, false predicate
5220   match(Set dst (LoadB mem));
5221   predicate(false);
5222 
5223   format %{ "LBZ     $dst, $mem" %}
5224   size(4);
5225   ins_encode( enc_lbz(dst, mem) );
5226   ins_pipe(pipe_class_memory);
5227 %}
5228 
5229 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5230   // match-rule, false predicate
5231   match(Set dst (LoadB mem));
5232   predicate(false);
5233 
5234   format %{ "LBZ     $dst, $mem\n\t"
5235             "TWI     $dst\n\t"
5236             "ISYNC" %}
5237   size(12);
5238   ins_encode( enc_lbz_ac(dst, mem) );
5239   ins_pipe(pipe_class_memory);
5240 %}
5241 
5242 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5243 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5244   match(Set dst (LoadB mem));
5245   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5246   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5247 
5248   expand %{
5249     iRegIdst tmp;
5250     loadUB_indOffset16(tmp, mem);
5251     convB2I_reg_2(dst, tmp);
5252   %}
5253 %}
5254 
5255 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5256   match(Set dst (LoadB mem));
5257   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5258 
5259   expand %{
5260     iRegIdst tmp;
5261     loadUB_indOffset16_ac(tmp, mem);
5262     convB2I_reg_2(dst, tmp);
5263   %}
5264 %}
5265 
5266 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5267 instruct loadUB(iRegIdst dst, memory mem) %{
5268   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5269   match(Set dst (LoadUB mem));
5270   ins_cost(MEMORY_REF_COST);
5271 
5272   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5273   size(4);
5274   ins_encode( enc_lbz(dst, mem) );
5275   ins_pipe(pipe_class_memory);
5276 %}
5277 
5278 // Load  Unsigned Byte (8bit UNsigned) acquire.
5279 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5280   match(Set dst (LoadUB mem));
5281   ins_cost(3*MEMORY_REF_COST);
5282 
5283   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5284             "TWI     $dst\n\t"
5285             "ISYNC" %}
5286   size(12);
5287   ins_encode( enc_lbz_ac(dst, mem) );
5288   ins_pipe(pipe_class_memory);
5289 %}
5290 
5291 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5292 instruct loadUB2L(iRegLdst dst, memory mem) %{
5293   match(Set dst (ConvI2L (LoadUB mem)));
5294   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5295   ins_cost(MEMORY_REF_COST);
5296 
5297   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5298   size(4);
5299   ins_encode( enc_lbz(dst, mem) );
5300   ins_pipe(pipe_class_memory);
5301 %}
5302 
5303 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5304   match(Set dst (ConvI2L (LoadUB mem)));
5305   ins_cost(3*MEMORY_REF_COST);
5306 
5307   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5308             "TWI     $dst\n\t"
5309             "ISYNC" %}
5310   size(12);
5311   ins_encode( enc_lbz_ac(dst, mem) );
5312   ins_pipe(pipe_class_memory);
5313 %}
5314 
5315 // Load Short (16bit signed)
5316 instruct loadS(iRegIdst dst, memory mem) %{
5317   match(Set dst (LoadS mem));
5318   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5319   ins_cost(MEMORY_REF_COST);
5320 
5321   format %{ "LHA     $dst, $mem" %}
5322   size(4);
5323   ins_encode %{
5324     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5325     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5326     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5327   %}
5328   ins_pipe(pipe_class_memory);
5329 %}
5330 
5331 // Load Short (16bit signed) acquire.
5332 instruct loadS_ac(iRegIdst dst, memory mem) %{
5333   match(Set dst (LoadS mem));
5334   ins_cost(3*MEMORY_REF_COST);
5335 
5336   format %{ "LHA     $dst, $mem\t acquire\n\t"
5337             "TWI     $dst\n\t"
5338             "ISYNC" %}
5339   size(12);
5340   ins_encode %{
5341     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5342     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5343     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5344     __ twi_0($dst$$Register);
5345     __ isync();
5346   %}
5347   ins_pipe(pipe_class_memory);
5348 %}
5349 
5350 // Load Char (16bit unsigned)
5351 instruct loadUS(iRegIdst dst, memory mem) %{
5352   match(Set dst (LoadUS mem));
5353   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5354   ins_cost(MEMORY_REF_COST);
5355 
5356   format %{ "LHZ     $dst, $mem" %}
5357   size(4);
5358   ins_encode( enc_lhz(dst, mem) );
5359   ins_pipe(pipe_class_memory);
5360 %}
5361 
5362 // Load Char (16bit unsigned) acquire.
5363 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5364   match(Set dst (LoadUS mem));
5365   ins_cost(3*MEMORY_REF_COST);
5366 
5367   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5368             "TWI     $dst\n\t"
5369             "ISYNC" %}
5370   size(12);
5371   ins_encode( enc_lhz_ac(dst, mem) );
5372   ins_pipe(pipe_class_memory);
5373 %}
5374 
5375 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5376 instruct loadUS2L(iRegLdst dst, memory mem) %{
5377   match(Set dst (ConvI2L (LoadUS mem)));
5378   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5379   ins_cost(MEMORY_REF_COST);
5380 
5381   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5382   size(4);
5383   ins_encode( enc_lhz(dst, mem) );
5384   ins_pipe(pipe_class_memory);
5385 %}
5386 
5387 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5388 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5389   match(Set dst (ConvI2L (LoadUS mem)));
5390   ins_cost(3*MEMORY_REF_COST);
5391 
5392   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5393             "TWI     $dst\n\t"
5394             "ISYNC" %}
5395   size(12);
5396   ins_encode( enc_lhz_ac(dst, mem) );
5397   ins_pipe(pipe_class_memory);
5398 %}
5399 
5400 // Load Integer.
5401 instruct loadI(iRegIdst dst, memory mem) %{
5402   match(Set dst (LoadI mem));
5403   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5404   ins_cost(MEMORY_REF_COST);
5405 
5406   format %{ "LWZ     $dst, $mem" %}
5407   size(4);
5408   ins_encode( enc_lwz(dst, mem) );
5409   ins_pipe(pipe_class_memory);
5410 %}
5411 
5412 // Load Integer acquire.
5413 instruct loadI_ac(iRegIdst dst, memory mem) %{
5414   match(Set dst (LoadI mem));
5415   ins_cost(3*MEMORY_REF_COST);
5416 
5417   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5418             "TWI     $dst\n\t"
5419             "ISYNC" %}
5420   size(12);
5421   ins_encode( enc_lwz_ac(dst, mem) );
5422   ins_pipe(pipe_class_memory);
5423 %}
5424 
5425 // Match loading integer and casting it to unsigned int in
5426 // long register.
5427 // LoadI + ConvI2L + AndL 0xffffffff.
5428 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5429   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5430   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5431   ins_cost(MEMORY_REF_COST);
5432 
5433   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5434   size(4);
5435   ins_encode( enc_lwz(dst, mem) );
5436   ins_pipe(pipe_class_memory);
5437 %}
5438 
5439 // Match loading integer and casting it to long.
5440 instruct loadI2L(iRegLdst dst, memory mem) %{
5441   match(Set dst (ConvI2L (LoadI mem)));
5442   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5443   ins_cost(MEMORY_REF_COST);
5444 
5445   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5446   size(4);
5447   ins_encode %{
5448     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5449     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5450     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5451   %}
5452   ins_pipe(pipe_class_memory);
5453 %}
5454 
5455 // Match loading integer and casting it to long - acquire.
5456 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5457   match(Set dst (ConvI2L (LoadI mem)));
5458   ins_cost(3*MEMORY_REF_COST);
5459 
5460   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5461             "TWI     $dst\n\t"
5462             "ISYNC" %}
5463   size(12);
5464   ins_encode %{
5465     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5466     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5467     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5468     __ twi_0($dst$$Register);
5469     __ isync();
5470   %}
5471   ins_pipe(pipe_class_memory);
5472 %}
5473 
5474 // Load Long - aligned
5475 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5476   match(Set dst (LoadL mem));
5477   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5478   ins_cost(MEMORY_REF_COST);
5479 
5480   format %{ "LD      $dst, $mem \t// long" %}
5481   size(4);
5482   ins_encode( enc_ld(dst, mem) );
5483   ins_pipe(pipe_class_memory);
5484 %}
5485 
5486 // Load Long - aligned acquire.
5487 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5488   match(Set dst (LoadL mem));
5489   ins_cost(3*MEMORY_REF_COST);
5490 
5491   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5492             "TWI     $dst\n\t"
5493             "ISYNC" %}
5494   size(12);
5495   ins_encode( enc_ld_ac(dst, mem) );
5496   ins_pipe(pipe_class_memory);
5497 %}
5498 
5499 // Load Long - UNaligned
5500 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5501   match(Set dst (LoadL_unaligned mem));
5502   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5503   ins_cost(MEMORY_REF_COST);
5504 
5505   format %{ "LD      $dst, $mem \t// unaligned long" %}
5506   size(4);
5507   ins_encode( enc_ld(dst, mem) );
5508   ins_pipe(pipe_class_memory);
5509 %}
5510 
5511 // Load nodes for superwords
5512 
5513 // Load Aligned Packed Byte
5514 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5515   predicate(n->as_LoadVector()->memory_size() == 8);
5516   match(Set dst (LoadVector mem));
5517   ins_cost(MEMORY_REF_COST);
5518 
5519   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5520   size(4);
5521   ins_encode( enc_ld(dst, mem) );
5522   ins_pipe(pipe_class_memory);
5523 %}
5524 
5525 // Load Range, range = array length (=jint)
5526 instruct loadRange(iRegIdst dst, memory mem) %{
5527   match(Set dst (LoadRange mem));
5528   ins_cost(MEMORY_REF_COST);
5529 
5530   format %{ "LWZ     $dst, $mem \t// range" %}
5531   size(4);
5532   ins_encode( enc_lwz(dst, mem) );
5533   ins_pipe(pipe_class_memory);
5534 %}
5535 
5536 // Load Compressed Pointer
5537 instruct loadN(iRegNdst dst, memory mem) %{
5538   match(Set dst (LoadN mem));
5539   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5540   ins_cost(MEMORY_REF_COST);
5541 
5542   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5543   size(4);
5544   ins_encode( enc_lwz(dst, mem) );
5545   ins_pipe(pipe_class_memory);
5546 %}
5547 
5548 // Load Compressed Pointer acquire.
5549 instruct loadN_ac(iRegNdst dst, memory mem) %{
5550   match(Set dst (LoadN mem));
5551   ins_cost(3*MEMORY_REF_COST);
5552 
5553   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5554             "TWI     $dst\n\t"
5555             "ISYNC" %}
5556   size(12);
5557   ins_encode( enc_lwz_ac(dst, mem) );
5558   ins_pipe(pipe_class_memory);
5559 %}
5560 
5561 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5562 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5563   match(Set dst (DecodeN (LoadN mem)));
5564   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5565   ins_cost(MEMORY_REF_COST);
5566 
5567   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5568   size(4);
5569   ins_encode( enc_lwz(dst, mem) );
5570   ins_pipe(pipe_class_memory);
5571 %}
5572 
5573 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5574   match(Set dst (DecodeNKlass (LoadNKlass mem)));

5575   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5576             _kids[0]->_leaf->as_Load()->is_unordered());
5577   ins_cost(MEMORY_REF_COST);
5578 
5579   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5580   size(4);
5581   ins_encode( enc_lwz(dst, mem) );
5582   ins_pipe(pipe_class_memory);
5583 %}
5584 
5585 // Load Pointer
5586 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5587   match(Set dst (LoadP mem));
5588   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5589   ins_cost(MEMORY_REF_COST);
5590 
5591   format %{ "LD      $dst, $mem \t// ptr" %}
5592   size(4);
5593   ins_encode( enc_ld(dst, mem) );
5594   ins_pipe(pipe_class_memory);
5595 %}
5596 
5597 // Load Pointer acquire.
5598 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5599   match(Set dst (LoadP mem));
5600   ins_cost(3*MEMORY_REF_COST);
5601 
5602   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5603             "TWI     $dst\n\t"
5604             "ISYNC" %}
5605   size(12);
5606   ins_encode( enc_ld_ac(dst, mem) );
5607   ins_pipe(pipe_class_memory);
5608 %}
5609 
5610 // LoadP + CastP2L
5611 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5612   match(Set dst (CastP2X (LoadP mem)));
5613   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5614   ins_cost(MEMORY_REF_COST);
5615 
5616   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5617   size(4);
5618   ins_encode( enc_ld(dst, mem) );
5619   ins_pipe(pipe_class_memory);
5620 %}
5621 
5622 // Load compressed klass pointer.
5623 instruct loadNKlass(iRegNdst dst, memory mem) %{
5624   match(Set dst (LoadNKlass mem));
5625   ins_cost(MEMORY_REF_COST);
5626 
5627   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5628   size(4);
5629   ins_encode( enc_lwz(dst, mem) );
5630   ins_pipe(pipe_class_memory);
5631 %}
5632 
5633 // Load Klass Pointer
5634 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5635   match(Set dst (LoadKlass mem));
5636   ins_cost(MEMORY_REF_COST);
5637 
5638   format %{ "LD      $dst, $mem \t// klass ptr" %}
5639   size(4);
5640   ins_encode( enc_ld(dst, mem) );
5641   ins_pipe(pipe_class_memory);
5642 %}
5643 
5644 // Load Float
5645 instruct loadF(regF dst, memory mem) %{
5646   match(Set dst (LoadF mem));
5647   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5648   ins_cost(MEMORY_REF_COST);
5649 
5650   format %{ "LFS     $dst, $mem" %}
5651   size(4);
5652   ins_encode %{
5653     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5654     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5655     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5656   %}
5657   ins_pipe(pipe_class_memory);
5658 %}
5659 
5660 // Load Float acquire.
5661 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5662   match(Set dst (LoadF mem));
5663   effect(TEMP cr0);
5664   ins_cost(3*MEMORY_REF_COST);
5665 
5666   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5667             "FCMPU   cr0, $dst, $dst\n\t"
5668             "BNE     cr0, next\n"
5669             "next:\n\t"
5670             "ISYNC" %}
5671   size(16);
5672   ins_encode %{
5673     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5674     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5675     Label next;
5676     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5677     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5678     __ bne(CCR0, next);
5679     __ bind(next);
5680     __ isync();
5681   %}
5682   ins_pipe(pipe_class_memory);
5683 %}
5684 
5685 // Load Double - aligned
5686 instruct loadD(regD dst, memory mem) %{
5687   match(Set dst (LoadD mem));
5688   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5689   ins_cost(MEMORY_REF_COST);
5690 
5691   format %{ "LFD     $dst, $mem" %}
5692   size(4);
5693   ins_encode( enc_lfd(dst, mem) );
5694   ins_pipe(pipe_class_memory);
5695 %}
5696 
5697 // Load Double - aligned acquire.
5698 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5699   match(Set dst (LoadD mem));
5700   effect(TEMP cr0);
5701   ins_cost(3*MEMORY_REF_COST);
5702 
5703   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5704             "FCMPU   cr0, $dst, $dst\n\t"
5705             "BNE     cr0, next\n"
5706             "next:\n\t"
5707             "ISYNC" %}
5708   size(16);
5709   ins_encode %{
5710     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5711     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5712     Label next;
5713     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5714     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5715     __ bne(CCR0, next);
5716     __ bind(next);
5717     __ isync();
5718   %}
5719   ins_pipe(pipe_class_memory);
5720 %}
5721 
5722 // Load Double - UNaligned
5723 instruct loadD_unaligned(regD dst, memory mem) %{
5724   match(Set dst (LoadD_unaligned mem));
5725   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5726   ins_cost(MEMORY_REF_COST);
5727 
5728   format %{ "LFD     $dst, $mem" %}
5729   size(4);
5730   ins_encode( enc_lfd(dst, mem) );
5731   ins_pipe(pipe_class_memory);
5732 %}
5733 
5734 //----------Constants--------------------------------------------------------
5735 
5736 // Load MachConstantTableBase: add hi offset to global toc.
5737 // TODO: Handle hidden register r29 in bundler!
5738 instruct loadToc_hi(iRegLdst dst) %{
5739   effect(DEF dst);
5740   ins_cost(DEFAULT_COST);
5741 
5742   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
5743   size(4);
5744   ins_encode %{
5745     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5746     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5747   %}
5748   ins_pipe(pipe_class_default);
5749 %}
5750 
5751 // Load MachConstantTableBase: add lo offset to global toc.
5752 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5753   effect(DEF dst, USE src);
5754   ins_cost(DEFAULT_COST);
5755 
5756   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
5757   size(4);
5758   ins_encode %{
5759     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5760     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5761   %}
5762   ins_pipe(pipe_class_default);
5763 %}
5764 
5765 // Load 16-bit integer constant 0xssss????
5766 instruct loadConI16(iRegIdst dst, immI16 src) %{
5767   match(Set dst src);
5768 
5769   format %{ "LI      $dst, $src" %}
5770   size(4);
5771   ins_encode %{
5772     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5773     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5774   %}
5775   ins_pipe(pipe_class_default);
5776 %}
5777 
5778 // Load integer constant 0x????0000
5779 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5780   match(Set dst src);
5781   ins_cost(DEFAULT_COST);
5782 
5783   format %{ "LIS     $dst, $src.hi" %}
5784   size(4);
5785   ins_encode %{
5786     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5787     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5788     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5789   %}
5790   ins_pipe(pipe_class_default);
5791 %}
5792 
5793 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5794 // and sign extended), this adds the low 16 bits.
5795 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5796   // no match-rule, false predicate
5797   effect(DEF dst, USE src1, USE src2);
5798   predicate(false);
5799 
5800   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
5801   size(4);
5802   ins_encode %{
5803     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5804     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5805   %}
5806   ins_pipe(pipe_class_default);
5807 %}
5808 
5809 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5810   match(Set dst src);
5811   ins_cost(DEFAULT_COST*2);
5812 
5813   expand %{
5814     // Would like to use $src$$constant.
5815     immI16 srcLo %{ _opnds[1]->constant() %}
5816     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5817     immIhi16 srcHi %{ _opnds[1]->constant() %}
5818     iRegIdst tmpI;
5819     loadConIhi16(tmpI, srcHi);
5820     loadConI32_lo16(dst, tmpI, srcLo);
5821   %}
5822 %}
5823 
5824 // No constant pool entries required.
5825 instruct loadConL16(iRegLdst dst, immL16 src) %{
5826   match(Set dst src);
5827 
5828   format %{ "LI      $dst, $src \t// long" %}
5829   size(4);
5830   ins_encode %{
5831     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5832     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5833   %}
5834   ins_pipe(pipe_class_default);
5835 %}
5836 
5837 // Load long constant 0xssssssss????0000
5838 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5839   match(Set dst src);
5840   ins_cost(DEFAULT_COST);
5841 
5842   format %{ "LIS     $dst, $src.hi \t// long" %}
5843   size(4);
5844   ins_encode %{
5845     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5846     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5847   %}
5848   ins_pipe(pipe_class_default);
5849 %}
5850 
5851 // To load a 32 bit constant: merge lower 16 bits into already loaded
5852 // high 16 bits.
5853 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5854   // no match-rule, false predicate
5855   effect(DEF dst, USE src1, USE src2);
5856   predicate(false);
5857 
5858   format %{ "ORI     $dst, $src1, $src2.lo" %}
5859   size(4);
5860   ins_encode %{
5861     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5862     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5863   %}
5864   ins_pipe(pipe_class_default);
5865 %}
5866 
5867 // Load 32-bit long constant
5868 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5869   match(Set dst src);
5870   ins_cost(DEFAULT_COST*2);
5871 
5872   expand %{
5873     // Would like to use $src$$constant.
5874     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5875     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5876     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5877     iRegLdst tmpL;
5878     loadConL32hi16(tmpL, srcHi);
5879     loadConL32_lo16(dst, tmpL, srcLo);
5880   %}
5881 %}
5882 
5883 // Load long constant 0x????000000000000.
5884 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5885   match(Set dst src);
5886   ins_cost(DEFAULT_COST);
5887 
5888   expand %{
5889     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5890     immI shift32 %{ 32 %}
5891     iRegLdst tmpL;
5892     loadConL32hi16(tmpL, srcHi);
5893     lshiftL_regL_immI(dst, tmpL, shift32);
5894   %}
5895 %}
5896 
5897 // Expand node for constant pool load: small offset.
5898 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5899   effect(DEF dst, USE src, USE toc);
5900   ins_cost(MEMORY_REF_COST);
5901 
5902   ins_num_consts(1);
5903   // Needed so that CallDynamicJavaDirect can compute the address of this
5904   // instruction for relocation.
5905   ins_field_cbuf_insts_offset(int);
5906 
5907   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
5908   size(4);
5909   ins_encode( enc_load_long_constL(dst, src, toc) );
5910   ins_pipe(pipe_class_memory);
5911 %}
5912 
5913 // Expand node for constant pool load: large offset.
5914 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5915   effect(DEF dst, USE src, USE toc);
5916   predicate(false);
5917 
5918   ins_num_consts(1);
5919   ins_field_const_toc_offset(int);
5920   // Needed so that CallDynamicJavaDirect can compute the address of this
5921   // instruction for relocation.
5922   ins_field_cbuf_insts_offset(int);
5923 
5924   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5925   size(4);
5926   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5927   ins_pipe(pipe_class_default);
5928 %}
5929 
5930 // Expand node for constant pool load: large offset.
5931 // No constant pool entries required.
5932 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5933   effect(DEF dst, USE src, USE base);
5934   predicate(false);
5935 
5936   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5937 
5938   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
5939   size(4);
5940   ins_encode %{
5941     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5942     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5943     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5944   %}
5945   ins_pipe(pipe_class_memory);
5946 %}
5947 
5948 // Load long constant from constant table. Expand in case of
5949 // offset > 16 bit is needed.
5950 // Adlc adds toc node MachConstantTableBase.
5951 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5952   match(Set dst src);
5953   ins_cost(MEMORY_REF_COST);
5954 
5955   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5956   // We can not inline the enc_class for the expand as that does not support constanttablebase.
5957   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5958 %}
5959 
5960 // Load NULL as compressed oop.
5961 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5962   match(Set dst src);
5963   ins_cost(DEFAULT_COST);
5964 
5965   format %{ "LI      $dst, $src \t// compressed ptr" %}
5966   size(4);
5967   ins_encode %{
5968     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5969     __ li($dst$$Register, 0);
5970   %}
5971   ins_pipe(pipe_class_default);
5972 %}
5973 
5974 // Load hi part of compressed oop constant.
5975 instruct loadConN_hi(iRegNdst dst, immN src) %{
5976   effect(DEF dst, USE src);
5977   ins_cost(DEFAULT_COST);
5978 
5979   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
5980   size(4);
5981   ins_encode %{
5982     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5983     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5984   %}
5985   ins_pipe(pipe_class_default);
5986 %}
5987 
5988 // Add lo part of compressed oop constant to already loaded hi part.
5989 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5990   effect(DEF dst, USE src1, USE src2);
5991   ins_cost(DEFAULT_COST);
5992 
5993   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
5994   size(4);
5995   ins_encode %{
5996     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5997     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5998     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5999     RelocationHolder rspec = oop_Relocation::spec(oop_index);
6000     __ relocate(rspec, 1);
6001     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6002   %}
6003   ins_pipe(pipe_class_default);
6004 %}
6005 
6006 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6007 // leaving the upper 32 bits with sign-extension bits.
6008 // This clears these bits: dst = src & 0xFFFFFFFF.
6009 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6010 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6011   effect(DEF dst, USE src);
6012   predicate(false);
6013 
6014   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
6015   size(4);
6016   ins_encode %{
6017     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6018     __ clrldi($dst$$Register, $src$$Register, 0x20);
6019   %}
6020   ins_pipe(pipe_class_default);
6021 %}
6022 
6023 // Optimize DecodeN for disjoint base.
6024 // Load base of compressed oops into a register
6025 instruct loadBase(iRegLdst dst) %{
6026   effect(DEF dst);
6027 
6028   format %{ "LoadConst $dst, heapbase" %}
6029   ins_encode %{
6030     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6031     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6032   %}
6033   ins_pipe(pipe_class_default);
6034 %}
6035 
6036 // Loading ConN must be postalloc expanded so that edges between
6037 // the nodes are safe. They may not interfere with a safepoint.
6038 // GL TODO: This needs three instructions: better put this into the constant pool.
6039 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6040   match(Set dst src);
6041   ins_cost(DEFAULT_COST*2);
6042 
6043   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6044   postalloc_expand %{
6045     MachNode *m1 = new loadConN_hiNode();
6046     MachNode *m2 = new loadConN_loNode();
6047     MachNode *m3 = new clearMs32bNode();
6048     m1->add_req(NULL);
6049     m2->add_req(NULL, m1);
6050     m3->add_req(NULL, m2);
6051     m1->_opnds[0] = op_dst;
6052     m1->_opnds[1] = op_src;
6053     m2->_opnds[0] = op_dst;
6054     m2->_opnds[1] = op_dst;
6055     m2->_opnds[2] = op_src;
6056     m3->_opnds[0] = op_dst;
6057     m3->_opnds[1] = op_dst;
6058     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6059     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6060     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6061     nodes->push(m1);
6062     nodes->push(m2);
6063     nodes->push(m3);
6064   %}
6065 %}
6066 
6067 // We have seen a safepoint between the hi and lo parts, and this node was handled
6068 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6069 // not a narrow oop.
6070 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6071   match(Set dst src);
6072   effect(DEF dst, USE src);
6073   ins_cost(DEFAULT_COST);
6074 
6075   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
6076   size(4);
6077   ins_encode %{
6078     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6079     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6080     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6081   %}
6082   ins_pipe(pipe_class_default);
6083 %}
6084 
6085 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6086 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6087   match(Set dst src1);
6088   effect(TEMP src2);
6089   ins_cost(DEFAULT_COST);
6090 
6091   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
6092   size(4);
6093   ins_encode %{
6094     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6095     __ clrldi($dst$$Register, $src2$$Register, 0x20);
6096   %}
6097   ins_pipe(pipe_class_default);
6098 %}
6099 
6100 // This needs a match rule so that build_oop_map knows this is
6101 // not a narrow oop.
6102 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6103   match(Set dst src1);
6104   effect(TEMP src2);
6105   ins_cost(DEFAULT_COST);
6106 
6107   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
6108   size(4);
6109   ins_encode %{
6110     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6111     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6112     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6113     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6114     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6115 
6116     __ relocate(rspec, 1);
6117     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6118   %}
6119   ins_pipe(pipe_class_default);
6120 %}
6121 
6122 // Loading ConNKlass must be postalloc expanded so that edges between
6123 // the nodes are safe. They may not interfere with a safepoint.
6124 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6125   match(Set dst src);
6126   ins_cost(DEFAULT_COST*2);
6127 
6128   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6129   postalloc_expand %{
6130     // Load high bits into register. Sign extended.
6131     MachNode *m1 = new loadConNKlass_hiNode();
6132     m1->add_req(NULL);
6133     m1->_opnds[0] = op_dst;
6134     m1->_opnds[1] = op_src;
6135     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6136     nodes->push(m1);
6137 
6138     MachNode *m2 = m1;
6139     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6140       // Value might be 1-extended. Mask out these bits.
6141       m2 = new loadConNKlass_maskNode();
6142       m2->add_req(NULL, m1);
6143       m2->_opnds[0] = op_dst;
6144       m2->_opnds[1] = op_src;
6145       m2->_opnds[2] = op_dst;
6146       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6147       nodes->push(m2);
6148     }
6149 
6150     MachNode *m3 = new loadConNKlass_loNode();
6151     m3->add_req(NULL, m2);
6152     m3->_opnds[0] = op_dst;
6153     m3->_opnds[1] = op_src;
6154     m3->_opnds[2] = op_dst;
6155     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6156     nodes->push(m3);
6157   %}
6158 %}
6159 
6160 // 0x1 is used in object initialization (initial object header).
6161 // No constant pool entries required.
6162 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6163   match(Set dst src);
6164 
6165   format %{ "LI      $dst, $src \t// ptr" %}
6166   size(4);
6167   ins_encode %{
6168     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6169     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6170   %}
6171   ins_pipe(pipe_class_default);
6172 %}
6173 
6174 // Expand node for constant pool load: small offset.
6175 // The match rule is needed to generate the correct bottom_type(),
6176 // however this node should never match. The use of predicate is not
6177 // possible since ADLC forbids predicates for chain rules. The higher
6178 // costs do not prevent matching in this case. For that reason the
6179 // operand immP_NM with predicate(false) is used.
6180 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6181   match(Set dst src);
6182   effect(TEMP toc);
6183 
6184   ins_num_consts(1);
6185 
6186   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6187   size(4);
6188   ins_encode( enc_load_long_constP(dst, src, toc) );
6189   ins_pipe(pipe_class_memory);
6190 %}
6191 
6192 // Expand node for constant pool load: large offset.
6193 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6194   effect(DEF dst, USE src, USE toc);
6195   predicate(false);
6196 
6197   ins_num_consts(1);
6198   ins_field_const_toc_offset(int);
6199 
6200   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6201   size(4);
6202   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6203   ins_pipe(pipe_class_default);
6204 %}
6205 
6206 // Expand node for constant pool load: large offset.
6207 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6208   match(Set dst src);
6209   effect(TEMP base);
6210 
6211   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6212 
6213   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6214   size(4);
6215   ins_encode %{
6216     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6217     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6218     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6219   %}
6220   ins_pipe(pipe_class_memory);
6221 %}
6222 
6223 // Load pointer constant from constant table. Expand in case an
6224 // offset > 16 bit is needed.
6225 // Adlc adds toc node MachConstantTableBase.
6226 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6227   match(Set dst src);
6228   ins_cost(MEMORY_REF_COST);
6229 
6230   // This rule does not use "expand" because then
6231   // the result type is not known to be an Oop.  An ADLC
6232   // enhancement will be needed to make that work - not worth it!
6233 
6234   // If this instruction rematerializes, it prolongs the live range
6235   // of the toc node, causing illegal graphs.
6236   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6237   ins_cannot_rematerialize(true);
6238 
6239   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6240   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6241 %}
6242 
6243 // Expand node for constant pool load: small offset.
6244 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6245   effect(DEF dst, USE src, USE toc);
6246   ins_cost(MEMORY_REF_COST);
6247 
6248   ins_num_consts(1);
6249 
6250   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6251   size(4);
6252   ins_encode %{
6253     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6254     address float_address = __ float_constant($src$$constant);
6255     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6256   %}
6257   ins_pipe(pipe_class_memory);
6258 %}
6259 
6260 // Expand node for constant pool load: large offset.
6261 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6262   effect(DEF dst, USE src, USE toc);
6263   ins_cost(MEMORY_REF_COST);
6264 
6265   ins_num_consts(1);
6266 
6267   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6268             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6269             "ADDIS   $toc, $toc, -offset_hi"%}
6270   size(12);
6271   ins_encode %{
6272     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6273     FloatRegister Rdst    = $dst$$FloatRegister;
6274     Register Rtoc         = $toc$$Register;
6275     address float_address = __ float_constant($src$$constant);
6276     int offset            = __ offset_to_method_toc(float_address);
6277     int hi = (offset + (1<<15))>>16;
6278     int lo = offset - hi * (1<<16);
6279 
6280     __ addis(Rtoc, Rtoc, hi);
6281     __ lfs(Rdst, lo, Rtoc);
6282     __ addis(Rtoc, Rtoc, -hi);
6283   %}
6284   ins_pipe(pipe_class_memory);
6285 %}
6286 
6287 // Adlc adds toc node MachConstantTableBase.
6288 instruct loadConF_Ex(regF dst, immF src) %{
6289   match(Set dst src);
6290   ins_cost(MEMORY_REF_COST);
6291 
6292   // See loadConP.
6293   ins_cannot_rematerialize(true);
6294 
6295   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6296   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6297 %}
6298 
6299 // Expand node for constant pool load: small offset.
6300 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6301   effect(DEF dst, USE src, USE toc);
6302   ins_cost(MEMORY_REF_COST);
6303 
6304   ins_num_consts(1);
6305 
6306   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6307   size(4);
6308   ins_encode %{
6309     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6310     int offset =  __ offset_to_method_toc(__ double_constant($src$$constant));
6311     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6312   %}
6313   ins_pipe(pipe_class_memory);
6314 %}
6315 
6316 // Expand node for constant pool load: large offset.
6317 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6318   effect(DEF dst, USE src, USE toc);
6319   ins_cost(MEMORY_REF_COST);
6320 
6321   ins_num_consts(1);
6322 
6323   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6324             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6325             "ADDIS   $toc, $toc, -offset_hi" %}
6326   size(12);
6327   ins_encode %{
6328     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6329     FloatRegister Rdst    = $dst$$FloatRegister;
6330     Register      Rtoc    = $toc$$Register;
6331     address float_address = __ double_constant($src$$constant);
6332     int offset            = __ offset_to_method_toc(float_address);
6333     int hi = (offset + (1<<15))>>16;
6334     int lo = offset - hi * (1<<16);
6335 
6336     __ addis(Rtoc, Rtoc, hi);
6337     __ lfd(Rdst, lo, Rtoc);
6338     __ addis(Rtoc, Rtoc, -hi);
6339   %}
6340   ins_pipe(pipe_class_memory);
6341 %}
6342 
6343 // Adlc adds toc node MachConstantTableBase.
6344 instruct loadConD_Ex(regD dst, immD src) %{
6345   match(Set dst src);
6346   ins_cost(MEMORY_REF_COST);
6347 
6348   // See loadConP.
6349   ins_cannot_rematerialize(true);
6350 
6351   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6352   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6353 %}
6354 
6355 // Prefetch instructions.
6356 // Must be safe to execute with invalid address (cannot fault).
6357 
6358 // Special prefetch versions which use the dcbz instruction.
6359 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6360   match(PrefetchAllocation (AddP mem src));
6361   predicate(AllocatePrefetchStyle == 3);
6362   ins_cost(MEMORY_REF_COST);
6363 
6364   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6365   size(4);
6366   ins_encode %{
6367     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6368     __ dcbz($src$$Register, $mem$$base$$Register);
6369   %}
6370   ins_pipe(pipe_class_memory);
6371 %}
6372 
6373 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6374   match(PrefetchAllocation mem);
6375   predicate(AllocatePrefetchStyle == 3);
6376   ins_cost(MEMORY_REF_COST);
6377 
6378   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6379   size(4);
6380   ins_encode %{
6381     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6382     __ dcbz($mem$$base$$Register);
6383   %}
6384   ins_pipe(pipe_class_memory);
6385 %}
6386 
6387 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6388   match(PrefetchAllocation (AddP mem src));
6389   predicate(AllocatePrefetchStyle != 3);
6390   ins_cost(MEMORY_REF_COST);
6391 
6392   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6393   size(4);
6394   ins_encode %{
6395     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6396     __ dcbtst($src$$Register, $mem$$base$$Register);
6397   %}
6398   ins_pipe(pipe_class_memory);
6399 %}
6400 
6401 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6402   match(PrefetchAllocation mem);
6403   predicate(AllocatePrefetchStyle != 3);
6404   ins_cost(MEMORY_REF_COST);
6405 
6406   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6407   size(4);
6408   ins_encode %{
6409     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6410     __ dcbtst($mem$$base$$Register);
6411   %}
6412   ins_pipe(pipe_class_memory);
6413 %}
6414 
6415 //----------Store Instructions-------------------------------------------------
6416 
6417 // Store Byte
6418 instruct storeB(memory mem, iRegIsrc src) %{
6419   match(Set mem (StoreB mem src));
6420   ins_cost(MEMORY_REF_COST);
6421 
6422   format %{ "STB     $src, $mem \t// byte" %}
6423   size(4);
6424   ins_encode %{
6425     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6426     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6427     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6428   %}
6429   ins_pipe(pipe_class_memory);
6430 %}
6431 
6432 // Store Char/Short
6433 instruct storeC(memory mem, iRegIsrc src) %{
6434   match(Set mem (StoreC mem src));
6435   ins_cost(MEMORY_REF_COST);
6436 
6437   format %{ "STH     $src, $mem \t// short" %}
6438   size(4);
6439   ins_encode %{
6440     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6441     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6442     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6443   %}
6444   ins_pipe(pipe_class_memory);
6445 %}
6446 
6447 // Store Integer
6448 instruct storeI(memory mem, iRegIsrc src) %{
6449   match(Set mem (StoreI mem src));
6450   ins_cost(MEMORY_REF_COST);
6451 
6452   format %{ "STW     $src, $mem" %}
6453   size(4);
6454   ins_encode( enc_stw(src, mem) );
6455   ins_pipe(pipe_class_memory);
6456 %}
6457 
6458 // ConvL2I + StoreI.
6459 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6460   match(Set mem (StoreI mem (ConvL2I src)));
6461   ins_cost(MEMORY_REF_COST);
6462 
6463   format %{ "STW     l2i($src), $mem" %}
6464   size(4);
6465   ins_encode( enc_stw(src, mem) );
6466   ins_pipe(pipe_class_memory);
6467 %}
6468 
6469 // Store Long
6470 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6471   match(Set mem (StoreL mem src));
6472   ins_cost(MEMORY_REF_COST);
6473 
6474   format %{ "STD     $src, $mem \t// long" %}
6475   size(4);
6476   ins_encode( enc_std(src, mem) );
6477   ins_pipe(pipe_class_memory);
6478 %}
6479 
6480 // Store super word nodes.
6481 
6482 // Store Aligned Packed Byte long register to memory
6483 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6484   predicate(n->as_StoreVector()->memory_size() == 8);
6485   match(Set mem (StoreVector mem src));
6486   ins_cost(MEMORY_REF_COST);
6487 
6488   format %{ "STD     $mem, $src \t// packed8B" %}
6489   size(4);
6490   ins_encode( enc_std(src, mem) );
6491   ins_pipe(pipe_class_memory);
6492 %}
6493 
6494 // Store Compressed Oop
6495 instruct storeN(memory dst, iRegN_P2N src) %{
6496   match(Set dst (StoreN dst src));
6497   ins_cost(MEMORY_REF_COST);
6498 
6499   format %{ "STW     $src, $dst \t// compressed oop" %}
6500   size(4);
6501   ins_encode( enc_stw(src, dst) );
6502   ins_pipe(pipe_class_memory);
6503 %}
6504 
6505 // Store Compressed KLass
6506 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6507   match(Set dst (StoreNKlass dst src));
6508   ins_cost(MEMORY_REF_COST);
6509 
6510   format %{ "STW     $src, $dst \t// compressed klass" %}
6511   size(4);
6512   ins_encode( enc_stw(src, dst) );
6513   ins_pipe(pipe_class_memory);
6514 %}
6515 
6516 // Store Pointer
6517 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6518   match(Set dst (StoreP dst src));
6519   ins_cost(MEMORY_REF_COST);
6520 
6521   format %{ "STD     $src, $dst \t// ptr" %}
6522   size(4);
6523   ins_encode( enc_std(src, dst) );
6524   ins_pipe(pipe_class_memory);
6525 %}
6526 
6527 // Store Float
6528 instruct storeF(memory mem, regF src) %{
6529   match(Set mem (StoreF mem src));
6530   ins_cost(MEMORY_REF_COST);
6531 
6532   format %{ "STFS    $src, $mem" %}
6533   size(4);
6534   ins_encode( enc_stfs(src, mem) );
6535   ins_pipe(pipe_class_memory);
6536 %}
6537 
6538 // Store Double
6539 instruct storeD(memory mem, regD src) %{
6540   match(Set mem (StoreD mem src));
6541   ins_cost(MEMORY_REF_COST);
6542 
6543   format %{ "STFD    $src, $mem" %}
6544   size(4);
6545   ins_encode( enc_stfd(src, mem) );
6546   ins_pipe(pipe_class_memory);
6547 %}
6548 
6549 //----------Store Instructions With Zeros--------------------------------------
6550 
6551 // Card-mark for CMS garbage collection.
6552 // This cardmark does an optimization so that it must not always
6553 // do a releasing store. For this, it gets the address of
6554 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6555 // (Using releaseFieldAddr in the match rule is a hack.)
6556 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6557   match(Set mem (StoreCM mem releaseFieldAddr));
6558   effect(TEMP crx);
6559   predicate(false);
6560   ins_cost(MEMORY_REF_COST);
6561 
6562   // See loadConP.
6563   ins_cannot_rematerialize(true);
6564 
6565   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6566   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6567   ins_pipe(pipe_class_memory);
6568 %}
6569 
6570 // Card-mark for CMS garbage collection.
6571 // This cardmark does an optimization so that it must not always
6572 // do a releasing store. For this, it needs the constant address of
6573 // CMSCollectorCardTableModRefBSExt::_requires_release.
6574 // This constant address is split off here by expand so we can use
6575 // adlc / matcher functionality to load it from the constant section.
6576 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6577   match(Set mem (StoreCM mem zero));
6578   predicate(UseConcMarkSweepGC);
6579 
6580   expand %{
6581     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6582     iRegLdst releaseFieldAddress;
6583     flagsReg crx;
6584     loadConL_Ex(releaseFieldAddress, baseImm);
6585     storeCM_CMS(mem, releaseFieldAddress, crx);
6586   %}
6587 %}
6588 
6589 instruct storeCM_G1(memory mem, immI_0 zero) %{
6590   match(Set mem (StoreCM mem zero));
6591   predicate(UseG1GC);
6592   ins_cost(MEMORY_REF_COST);
6593 
6594   ins_cannot_rematerialize(true);
6595 
6596   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6597   size(8);
6598   ins_encode %{
6599     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6600     __ li(R0, 0);
6601     //__ release(); // G1: oops are allowed to get visible after dirty marking
6602     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6603     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6604   %}
6605   ins_pipe(pipe_class_memory);
6606 %}
6607 
6608 // Convert oop pointer into compressed form.
6609 
6610 // Nodes for postalloc expand.
6611 
6612 // Shift node for expand.
6613 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6614   // The match rule is needed to make it a 'MachTypeNode'!
6615   match(Set dst (EncodeP src));
6616   predicate(false);
6617 
6618   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6619   size(4);
6620   ins_encode %{
6621     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6622     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6623   %}
6624   ins_pipe(pipe_class_default);
6625 %}
6626 
6627 // Add node for expand.
6628 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6629   // The match rule is needed to make it a 'MachTypeNode'!
6630   match(Set dst (EncodeP src));
6631   predicate(false);
6632 
6633   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6634   ins_encode %{
6635     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6636     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6637   %}
6638   ins_pipe(pipe_class_default);
6639 %}
6640 
6641 // Conditional sub base.
6642 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6643   // The match rule is needed to make it a 'MachTypeNode'!
6644   match(Set dst (EncodeP (Binary crx src1)));
6645   predicate(false);
6646 
6647   format %{ "BEQ     $crx, done\n\t"
6648             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6649             "done:" %}
6650   ins_encode %{
6651     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6652     Label done;
6653     __ beq($crx$$CondRegister, done);
6654     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6655     __ bind(done);
6656   %}
6657   ins_pipe(pipe_class_default);
6658 %}
6659 
6660 // Power 7 can use isel instruction
6661 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6662   // The match rule is needed to make it a 'MachTypeNode'!
6663   match(Set dst (EncodeP (Binary crx src1)));
6664   predicate(false);
6665 
6666   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6667   size(4);
6668   ins_encode %{
6669     // This is a Power7 instruction for which no machine description exists.
6670     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6671     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6672   %}
6673   ins_pipe(pipe_class_default);
6674 %}
6675 
6676 // Disjoint narrow oop base.
6677 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6678   match(Set dst (EncodeP src));
6679   predicate(Universe::narrow_oop_base_disjoint());
6680 
6681   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6682   size(4);
6683   ins_encode %{
6684     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6685     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6686   %}
6687   ins_pipe(pipe_class_default);
6688 %}
6689 
6690 // shift != 0, base != 0
6691 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6692   match(Set dst (EncodeP src));
6693   effect(TEMP crx);
6694   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6695             Universe::narrow_oop_shift() != 0 &&
6696             Universe::narrow_oop_base_overlaps());
6697 
6698   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6699   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6700 %}
6701 
6702 // shift != 0, base != 0
6703 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6704   match(Set dst (EncodeP src));
6705   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6706             Universe::narrow_oop_shift() != 0 &&
6707             Universe::narrow_oop_base_overlaps());
6708 
6709   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6710   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6711 %}
6712 
6713 // shift != 0, base == 0
6714 // TODO: This is the same as encodeP_shift. Merge!
6715 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6716   match(Set dst (EncodeP src));
6717   predicate(Universe::narrow_oop_shift() != 0 &&
6718             Universe::narrow_oop_base() ==0);
6719 
6720   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
6721   size(4);
6722   ins_encode %{
6723     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6724     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6725   %}
6726   ins_pipe(pipe_class_default);
6727 %}
6728 
6729 // Compressed OOPs with narrow_oop_shift == 0.
6730 // shift == 0, base == 0
6731 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6732   match(Set dst (EncodeP src));
6733   predicate(Universe::narrow_oop_shift() == 0);
6734 
6735   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
6736   // variable size, 0 or 4.
6737   ins_encode %{
6738     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6739     __ mr_if_needed($dst$$Register, $src$$Register);
6740   %}
6741   ins_pipe(pipe_class_default);
6742 %}
6743 
6744 // Decode nodes.
6745 
6746 // Shift node for expand.
6747 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6748   // The match rule is needed to make it a 'MachTypeNode'!
6749   match(Set dst (DecodeN src));
6750   predicate(false);
6751 
6752   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
6753   size(4);
6754   ins_encode %{
6755     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6756     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6757   %}
6758   ins_pipe(pipe_class_default);
6759 %}
6760 
6761 // Add node for expand.
6762 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6763   // The match rule is needed to make it a 'MachTypeNode'!
6764   match(Set dst (DecodeN src));
6765   predicate(false);
6766 
6767   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
6768   ins_encode %{
6769     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6770     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6771   %}
6772   ins_pipe(pipe_class_default);
6773 %}
6774 
6775 // conditianal add base for expand
6776 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6777   // The match rule is needed to make it a 'MachTypeNode'!
6778   // NOTICE that the rule is nonsense - we just have to make sure that:
6779   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6780   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6781   match(Set dst (DecodeN (Binary crx src)));
6782   predicate(false);
6783 
6784   format %{ "BEQ     $crx, done\n\t"
6785             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6786             "done:" %}
6787   ins_encode %{
6788     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6789     Label done;
6790     __ beq($crx$$CondRegister, done);
6791     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6792     __ bind(done);
6793   %}
6794   ins_pipe(pipe_class_default);
6795 %}
6796 
6797 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6798   // The match rule is needed to make it a 'MachTypeNode'!
6799   // NOTICE that the rule is nonsense - we just have to make sure that:
6800   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6801   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6802   match(Set dst (DecodeN (Binary crx src1)));
6803   predicate(false);
6804 
6805   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6806   size(4);
6807   ins_encode %{
6808     // This is a Power7 instruction for which no machine description exists.
6809     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6810     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6811   %}
6812   ins_pipe(pipe_class_default);
6813 %}
6814 
6815 //  shift != 0, base != 0
6816 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6817   match(Set dst (DecodeN src));
6818   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6819              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6820             Universe::narrow_oop_shift() != 0 &&
6821             Universe::narrow_oop_base() != 0);
6822   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6823   effect(TEMP crx);
6824 
6825   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6826   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6827 %}
6828 
6829 // shift != 0, base == 0
6830 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6831   match(Set dst (DecodeN src));
6832   predicate(Universe::narrow_oop_shift() != 0 &&
6833             Universe::narrow_oop_base() == 0);
6834 
6835   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
6836   size(4);
6837   ins_encode %{
6838     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6839     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6840   %}
6841   ins_pipe(pipe_class_default);
6842 %}
6843 
6844 // Optimize DecodeN for disjoint base.
6845 // Shift narrow oop and or it into register that already contains the heap base.
6846 // Base == dst must hold, and is assured by construction in postaloc_expand.
6847 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6848   match(Set dst (DecodeN src));
6849   effect(TEMP base);
6850   predicate(false);
6851 
6852   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6853   size(4);
6854   ins_encode %{
6855     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6856     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6857   %}
6858   ins_pipe(pipe_class_default);
6859 %}
6860 
6861 // Optimize DecodeN for disjoint base.
6862 // This node requires only one cycle on the critical path.
6863 // We must postalloc_expand as we can not express use_def effects where
6864 // the used register is L and the def'ed register P.
6865 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6866   match(Set dst (DecodeN src));
6867   effect(TEMP_DEF dst);
6868   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6869              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6870             Universe::narrow_oop_base_disjoint());
6871   ins_cost(DEFAULT_COST);
6872 
6873   format %{ "MOV     $dst, heapbase \t\n"
6874             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6875   postalloc_expand %{
6876     loadBaseNode *n1 = new loadBaseNode();
6877     n1->add_req(NULL);
6878     n1->_opnds[0] = op_dst;
6879 
6880     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6881     n2->add_req(n_region, n_src, n1);
6882     n2->_opnds[0] = op_dst;
6883     n2->_opnds[1] = op_src;
6884     n2->_opnds[2] = op_dst;
6885     n2->_bottom_type = _bottom_type;
6886 
6887     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6888     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6889 
6890     nodes->push(n1);
6891     nodes->push(n2);
6892   %}
6893 %}
6894 
6895 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6896   match(Set dst (DecodeN src));
6897   effect(TEMP_DEF dst, TEMP crx);
6898   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6899              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6900             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6901   ins_cost(3 * DEFAULT_COST);
6902 
6903   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
6904   postalloc_expand %{
6905     loadBaseNode *n1 = new loadBaseNode();
6906     n1->add_req(NULL);
6907     n1->_opnds[0] = op_dst;
6908 
6909     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
6910     n_compare->add_req(n_region, n_src);
6911     n_compare->_opnds[0] = op_crx;
6912     n_compare->_opnds[1] = op_src;
6913     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6914     
6915     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6916     n2->add_req(n_region, n_src, n1);
6917     n2->_opnds[0] = op_dst;
6918     n2->_opnds[1] = op_src;
6919     n2->_opnds[2] = op_dst;
6920     n2->_bottom_type = _bottom_type;
6921 
6922     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6923     n_cond_set->add_req(n_region, n_compare, n2);
6924     n_cond_set->_opnds[0] = op_dst;
6925     n_cond_set->_opnds[1] = op_crx;
6926     n_cond_set->_opnds[2] = op_dst;
6927     n_cond_set->_bottom_type = _bottom_type;
6928 
6929     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6930     ra_->set_oop(n_cond_set, true);
6931 
6932     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6933     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6934     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6935     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6936 
6937     nodes->push(n1);
6938     nodes->push(n_compare);
6939     nodes->push(n2);
6940     nodes->push(n_cond_set);
6941   %}
6942 %}
6943 
6944 // src != 0, shift != 0, base != 0
6945 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6946   match(Set dst (DecodeN src));
6947   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6948              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6949             Universe::narrow_oop_shift() != 0 &&
6950             Universe::narrow_oop_base() != 0);
6951   ins_cost(2 * DEFAULT_COST);
6952 
6953   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6954   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6955 %}
6956 
6957 // Compressed OOPs with narrow_oop_shift == 0.
6958 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6959   match(Set dst (DecodeN src));
6960   predicate(Universe::narrow_oop_shift() == 0);
6961   ins_cost(DEFAULT_COST);
6962 
6963   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
6964   // variable size, 0 or 4.
6965   ins_encode %{
6966     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6967     __ mr_if_needed($dst$$Register, $src$$Register);
6968   %}
6969   ins_pipe(pipe_class_default);
6970 %}
6971 
6972 // Convert compressed oop into int for vectors alignment masking.
6973 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6974   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6975   predicate(Universe::narrow_oop_shift() == 0);
6976   ins_cost(DEFAULT_COST);
6977 
6978   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
6979   // variable size, 0 or 4.
6980   ins_encode %{
6981     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6982     __ mr_if_needed($dst$$Register, $src$$Register);
6983   %}
6984   ins_pipe(pipe_class_default);
6985 %}
6986 
6987 // Convert klass pointer into compressed form.
6988 
6989 // Nodes for postalloc expand.
6990 
6991 // Shift node for expand.
6992 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6993   // The match rule is needed to make it a 'MachTypeNode'!
6994   match(Set dst (EncodePKlass src));
6995   predicate(false);
6996 
6997   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6998   size(4);
6999   ins_encode %{
7000     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7001     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7002   %}
7003   ins_pipe(pipe_class_default);
7004 %}
7005 
7006 // Add node for expand.
7007 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7008   // The match rule is needed to make it a 'MachTypeNode'!
7009   match(Set dst (EncodePKlass (Binary base src)));
7010   predicate(false);
7011 
7012   format %{ "SUB     $dst, $base, $src \t// encode" %}
7013   size(4);
7014   ins_encode %{
7015     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7016     __ subf($dst$$Register, $base$$Register, $src$$Register);
7017   %}
7018   ins_pipe(pipe_class_default);
7019 %}
7020 
7021 // Disjoint narrow oop base.
7022 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7023   match(Set dst (EncodePKlass src));
7024   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7025 
7026   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
7027   size(4);
7028   ins_encode %{
7029     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7030     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7031   %}
7032   ins_pipe(pipe_class_default);
7033 %}
7034 
7035 // shift != 0, base != 0
7036 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7037   match(Set dst (EncodePKlass (Binary base src)));
7038   predicate(false);
7039 
7040   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7041   postalloc_expand %{
7042     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7043     n1->add_req(n_region, n_base, n_src);
7044     n1->_opnds[0] = op_dst;
7045     n1->_opnds[1] = op_base;
7046     n1->_opnds[2] = op_src;
7047     n1->_bottom_type = _bottom_type;
7048 
7049     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7050     n2->add_req(n_region, n1);
7051     n2->_opnds[0] = op_dst;
7052     n2->_opnds[1] = op_dst;
7053     n2->_bottom_type = _bottom_type;
7054     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7055     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7056 
7057     nodes->push(n1);
7058     nodes->push(n2);
7059   %}
7060 %}
7061 
7062 // shift != 0, base != 0
7063 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7064   match(Set dst (EncodePKlass src));
7065   //predicate(Universe::narrow_klass_shift() != 0 &&
7066   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7067 
7068   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7069   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7070   expand %{
7071     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7072     iRegLdst base;
7073     loadConL_Ex(base, baseImm);
7074     encodePKlass_not_null_Ex(dst, base, src);
7075   %}
7076 %}
7077 
7078 // Decode nodes.
7079 
7080 // Shift node for expand.
7081 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7082   // The match rule is needed to make it a 'MachTypeNode'!
7083   match(Set dst (DecodeNKlass src));
7084   predicate(false);
7085 
7086   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
7087   size(4);
7088   ins_encode %{
7089     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7090     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7091   %}
7092   ins_pipe(pipe_class_default);
7093 %}
7094 
7095 // Add node for expand.
7096 
7097 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7098   // The match rule is needed to make it a 'MachTypeNode'!
7099   match(Set dst (DecodeNKlass (Binary base src)));
7100   predicate(false);
7101 
7102   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7103   size(4);
7104   ins_encode %{
7105     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7106     __ add($dst$$Register, $base$$Register, $src$$Register);
7107   %}
7108   ins_pipe(pipe_class_default);
7109 %}
7110 
7111 // src != 0, shift != 0, base != 0
7112 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7113   match(Set dst (DecodeNKlass (Binary base src)));
7114   //effect(kill src); // We need a register for the immediate result after shifting.
7115   predicate(false);
7116 
7117   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7118   postalloc_expand %{
7119     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7120     n1->add_req(n_region, n_base, n_src);
7121     n1->_opnds[0] = op_dst;
7122     n1->_opnds[1] = op_base;
7123     n1->_opnds[2] = op_src;
7124     n1->_bottom_type = _bottom_type;
7125 
7126     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7127     n2->add_req(n_region, n1);
7128     n2->_opnds[0] = op_dst;
7129     n2->_opnds[1] = op_dst;
7130     n2->_bottom_type = _bottom_type;
7131 
7132     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7133     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7134 
7135     nodes->push(n1);
7136     nodes->push(n2);
7137   %}
7138 %}
7139 
7140 // src != 0, shift != 0, base != 0
7141 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7142   match(Set dst (DecodeNKlass src));
7143   // predicate(Universe::narrow_klass_shift() != 0 &&
7144   //           Universe::narrow_klass_base() != 0);
7145 
7146   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7147 
7148   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7149   expand %{
7150     // We add first, then we shift. Like this, we can get along with one register less.
7151     // But we have to load the base pre-shifted.
7152     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7153     iRegLdst base;
7154     loadConL_Ex(base, baseImm);
7155     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7156   %}
7157 %}
7158 
7159 //----------MemBar Instructions-----------------------------------------------
7160 // Memory barrier flavors
7161 
7162 instruct membar_acquire() %{
7163   match(LoadFence);
7164   ins_cost(4*MEMORY_REF_COST);
7165 
7166   format %{ "MEMBAR-acquire" %}
7167   size(4);
7168   ins_encode %{
7169     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7170     __ acquire();
7171   %}
7172   ins_pipe(pipe_class_default);
7173 %}
7174 
7175 instruct unnecessary_membar_acquire() %{
7176   match(MemBarAcquire);
7177   ins_cost(0);
7178 
7179   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7180   size(0);
7181   ins_encode( /*empty*/ );
7182   ins_pipe(pipe_class_default);
7183 %}
7184 
7185 instruct membar_acquire_lock() %{
7186   match(MemBarAcquireLock);
7187   ins_cost(0);
7188 
7189   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7190   size(0);
7191   ins_encode( /*empty*/ );
7192   ins_pipe(pipe_class_default);
7193 %}
7194 
7195 instruct membar_release() %{
7196   match(MemBarRelease);
7197   match(StoreFence);
7198   ins_cost(4*MEMORY_REF_COST);
7199 
7200   format %{ "MEMBAR-release" %}
7201   size(4);
7202   ins_encode %{
7203     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7204     __ release();
7205   %}
7206   ins_pipe(pipe_class_default);
7207 %}
7208 
7209 instruct membar_storestore() %{
7210   match(MemBarStoreStore);
7211   ins_cost(4*MEMORY_REF_COST);
7212 
7213   format %{ "MEMBAR-store-store" %}
7214   size(4);
7215   ins_encode %{
7216     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7217     __ membar(Assembler::StoreStore);
7218   %}
7219   ins_pipe(pipe_class_default);
7220 %}
7221 
7222 instruct membar_release_lock() %{
7223   match(MemBarReleaseLock);
7224   ins_cost(0);
7225 
7226   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7227   size(0);
7228   ins_encode( /*empty*/ );
7229   ins_pipe(pipe_class_default);
7230 %}
7231 
7232 instruct membar_volatile() %{
7233   match(MemBarVolatile);
7234   ins_cost(4*MEMORY_REF_COST);
7235 
7236   format %{ "MEMBAR-volatile" %}
7237   size(4);
7238   ins_encode %{
7239     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7240     __ fence();
7241   %}
7242   ins_pipe(pipe_class_default);
7243 %}
7244 
7245 // This optimization is wrong on PPC. The following pattern is not supported:
7246 //  MemBarVolatile
7247 //   ^        ^
7248 //   |        |
7249 //  CtrlProj MemProj
7250 //   ^        ^
7251 //   |        |
7252 //   |       Load
7253 //   |
7254 //  MemBarVolatile
7255 //
7256 //  The first MemBarVolatile could get optimized out! According to
7257 //  Vladimir, this pattern can not occur on Oracle platforms.
7258 //  However, it does occur on PPC64 (because of membars in
7259 //  inline_unsafe_load_store).
7260 //
7261 // Add this node again if we found a good solution for inline_unsafe_load_store().
7262 // Don't forget to look at the implementation of post_store_load_barrier again,
7263 // we did other fixes in that method.
7264 //instruct unnecessary_membar_volatile() %{
7265 //  match(MemBarVolatile);
7266 //  predicate(Matcher::post_store_load_barrier(n));
7267 //  ins_cost(0);
7268 //
7269 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7270 //  size(0);
7271 //  ins_encode( /*empty*/ );
7272 //  ins_pipe(pipe_class_default);
7273 //%}
7274 
7275 instruct membar_CPUOrder() %{
7276   match(MemBarCPUOrder);
7277   ins_cost(0);
7278 
7279   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7280   size(0);
7281   ins_encode( /*empty*/ );
7282   ins_pipe(pipe_class_default);
7283 %}
7284 
7285 //----------Conditional Move---------------------------------------------------
7286 
7287 // Cmove using isel.
7288 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7289   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7290   predicate(VM_Version::has_isel());
7291   ins_cost(DEFAULT_COST);
7292 
7293   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7294   size(4);
7295   ins_encode %{
7296     // This is a Power7 instruction for which no machine description
7297     // exists. Anyways, the scheduler should be off on Power7.
7298     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7299     int cc        = $cmp$$cmpcode;
7300     __ isel($dst$$Register, $crx$$CondRegister,
7301             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7302   %}
7303   ins_pipe(pipe_class_default);
7304 %}
7305 
7306 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7307   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7308   predicate(!VM_Version::has_isel());
7309   ins_cost(DEFAULT_COST+BRANCH_COST);
7310 
7311   ins_variable_size_depending_on_alignment(true);
7312 
7313   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7314   // Worst case is branch + move + stop, no stop without scheduler
7315   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7316   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7317   ins_pipe(pipe_class_default);
7318 %}
7319 
7320 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7321   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7322   ins_cost(DEFAULT_COST+BRANCH_COST);
7323 
7324   ins_variable_size_depending_on_alignment(true);
7325 
7326   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7327   // Worst case is branch + move + stop, no stop without scheduler
7328   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7329   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7330   ins_pipe(pipe_class_default);
7331 %}
7332 
7333 // Cmove using isel.
7334 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7335   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7336   predicate(VM_Version::has_isel());
7337   ins_cost(DEFAULT_COST);
7338 
7339   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7340   size(4);
7341   ins_encode %{
7342     // This is a Power7 instruction for which no machine description
7343     // exists. Anyways, the scheduler should be off on Power7.
7344     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7345     int cc        = $cmp$$cmpcode;
7346     __ isel($dst$$Register, $crx$$CondRegister,
7347             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7348   %}
7349   ins_pipe(pipe_class_default);
7350 %}
7351 
7352 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7353   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7354   predicate(!VM_Version::has_isel());
7355   ins_cost(DEFAULT_COST+BRANCH_COST);
7356 
7357   ins_variable_size_depending_on_alignment(true);
7358 
7359   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7360   // Worst case is branch + move + stop, no stop without scheduler.
7361   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7362   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7363   ins_pipe(pipe_class_default);
7364 %}
7365 
7366 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7367   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7368   ins_cost(DEFAULT_COST+BRANCH_COST);
7369 
7370   ins_variable_size_depending_on_alignment(true);
7371 
7372   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7373   // Worst case is branch + move + stop, no stop without scheduler.
7374   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7375   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7376   ins_pipe(pipe_class_default);
7377 %}
7378 
7379 // Cmove using isel.
7380 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7381   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7382   predicate(VM_Version::has_isel());
7383   ins_cost(DEFAULT_COST);
7384 
7385   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7386   size(4);
7387   ins_encode %{
7388     // This is a Power7 instruction for which no machine description
7389     // exists. Anyways, the scheduler should be off on Power7.
7390     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7391     int cc        = $cmp$$cmpcode;
7392     __ isel($dst$$Register, $crx$$CondRegister,
7393             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7394   %}
7395   ins_pipe(pipe_class_default);
7396 %}
7397 
7398 // Conditional move for RegN. Only cmov(reg, reg).
7399 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7400   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7401   predicate(!VM_Version::has_isel());
7402   ins_cost(DEFAULT_COST+BRANCH_COST);
7403 
7404   ins_variable_size_depending_on_alignment(true);
7405 
7406   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7407   // Worst case is branch + move + stop, no stop without scheduler.
7408   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7409   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7410   ins_pipe(pipe_class_default);
7411 %}
7412 
7413 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7414   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7415   ins_cost(DEFAULT_COST+BRANCH_COST);
7416 
7417   ins_variable_size_depending_on_alignment(true);
7418 
7419   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7420   // Worst case is branch + move + stop, no stop without scheduler.
7421   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7422   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7423   ins_pipe(pipe_class_default);
7424 %}
7425 
7426 // Cmove using isel.
7427 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7428   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7429   predicate(VM_Version::has_isel());
7430   ins_cost(DEFAULT_COST);
7431 
7432   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7433   size(4);
7434   ins_encode %{
7435     // This is a Power7 instruction for which no machine description
7436     // exists. Anyways, the scheduler should be off on Power7.
7437     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7438     int cc        = $cmp$$cmpcode;
7439     __ isel($dst$$Register, $crx$$CondRegister,
7440             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7441   %}
7442   ins_pipe(pipe_class_default);
7443 %}
7444 
7445 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7446   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7447   predicate(!VM_Version::has_isel());
7448   ins_cost(DEFAULT_COST+BRANCH_COST);
7449 
7450   ins_variable_size_depending_on_alignment(true);
7451 
7452   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7453   // Worst case is branch + move + stop, no stop without scheduler.
7454   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7455   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7456   ins_pipe(pipe_class_default);
7457 %}
7458 
7459 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7460   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7461   ins_cost(DEFAULT_COST+BRANCH_COST);
7462 
7463   ins_variable_size_depending_on_alignment(true);
7464 
7465   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7466   // Worst case is branch + move + stop, no stop without scheduler.
7467   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7468   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7469   ins_pipe(pipe_class_default);
7470 %}
7471 
7472 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7473   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7474   ins_cost(DEFAULT_COST+BRANCH_COST);
7475 
7476   ins_variable_size_depending_on_alignment(true);
7477 
7478   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7479   // Worst case is branch + move + stop, no stop without scheduler.
7480   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7481   ins_encode %{
7482     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7483     Label done;
7484     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7485     // Branch if not (cmp crx).
7486     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7487     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7488     // TODO PPC port __ endgroup_if_needed(_size == 12);
7489     __ bind(done);
7490   %}
7491   ins_pipe(pipe_class_default);
7492 %}
7493 
7494 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7495   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7496   ins_cost(DEFAULT_COST+BRANCH_COST);
7497 
7498   ins_variable_size_depending_on_alignment(true);
7499 
7500   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7501   // Worst case is branch + move + stop, no stop without scheduler.
7502   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7503   ins_encode %{
7504     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7505     Label done;
7506     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7507     // Branch if not (cmp crx).
7508     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7509     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7510     // TODO PPC port __ endgroup_if_needed(_size == 12);
7511     __ bind(done);
7512   %}
7513   ins_pipe(pipe_class_default);
7514 %}
7515 
7516 //----------Conditional_store--------------------------------------------------
7517 // Conditional-store of the updated heap-top.
7518 // Used during allocation of the shared heap.
7519 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7520 
7521 // As compareAndSwapL, but return flag register instead of boolean value in
7522 // int register.
7523 // Used by sun/misc/AtomicLongCSImpl.java.
7524 // Mem_ptr must be a memory operand, else this node does not get
7525 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7526 // can be rematerialized which leads to errors.
7527 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7528   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7529   effect(TEMP cr0);
7530   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7531   ins_encode %{
7532     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7533     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7534                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7535                 noreg, NULL, true);
7536   %}
7537   ins_pipe(pipe_class_default);
7538 %}
7539 
7540 // As compareAndSwapP, but return flag register instead of boolean value in
7541 // int register.
7542 // This instruction is matched if UseTLAB is off.
7543 // Mem_ptr must be a memory operand, else this node does not get
7544 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7545 // can be rematerialized which leads to errors.
7546 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7547   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7548   ins_cost(2*MEMORY_REF_COST);
7549 
7550   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7551   ins_encode %{
7552     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7553     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7554   %}
7555   ins_pipe(pipe_class_memory);
7556 %}
7557 
7558 // Implement LoadPLocked. Must be ordered against changes of the memory location
7559 // by storePConditional.
7560 // Don't know whether this is ever used.
7561 instruct loadPLocked(iRegPdst dst, memory mem) %{
7562   match(Set dst (LoadPLocked mem));
7563   ins_cost(2*MEMORY_REF_COST);
7564 
7565   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7566   size(4);
7567   ins_encode %{
7568     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7569     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7570   %}
7571   ins_pipe(pipe_class_memory);
7572 %}
7573 
7574 //----------Compare-And-Swap---------------------------------------------------
7575 
7576 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7577 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7578 // matched.
7579 
7580 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7581   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7582   effect(TEMP cr0);
7583   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7584   // Variable size: instruction count smaller if regs are disjoint.
7585   ins_encode %{
7586     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7587     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7588     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7589                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7590                 $res$$Register, true);
7591   %}
7592   ins_pipe(pipe_class_default);
7593 %}
7594 
7595 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7596   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7597   effect(TEMP cr0);
7598   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7599   // Variable size: instruction count smaller if regs are disjoint.
7600   ins_encode %{
7601     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7602     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7603     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7604                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7605                 $res$$Register, true);
7606   %}
7607   ins_pipe(pipe_class_default);
7608 %}
7609 
7610 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7611   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7612   effect(TEMP cr0);
7613   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7614   // Variable size: instruction count smaller if regs are disjoint.
7615   ins_encode %{
7616     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7617     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7618     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7619                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7620                 $res$$Register, NULL, true);
7621   %}
7622   ins_pipe(pipe_class_default);
7623 %}
7624 
7625 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7626   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7627   effect(TEMP cr0);
7628   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7629   // Variable size: instruction count smaller if regs are disjoint.
7630   ins_encode %{
7631     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7632     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7633     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7634                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7635                 $res$$Register, NULL, true);
7636   %}
7637   ins_pipe(pipe_class_default);
7638 %}
7639 
7640 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7641   match(Set res (GetAndAddI mem_ptr src));
7642   effect(TEMP cr0);
7643   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7644   // Variable size: instruction count smaller if regs are disjoint.
7645   ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7646   ins_pipe(pipe_class_default);
7647 %}
7648 
7649 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7650   match(Set res (GetAndAddL mem_ptr src));
7651   effect(TEMP cr0);
7652   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7653   // Variable size: instruction count smaller if regs are disjoint.
7654   ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7655   ins_pipe(pipe_class_default);
7656 %}
7657 
7658 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7659   match(Set res (GetAndSetI mem_ptr src));
7660   effect(TEMP cr0);
7661   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7662   // Variable size: instruction count smaller if regs are disjoint.
7663   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7664   ins_pipe(pipe_class_default);
7665 %}
7666 
7667 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7668   match(Set res (GetAndSetL mem_ptr src));
7669   effect(TEMP cr0);
7670   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7671   // Variable size: instruction count smaller if regs are disjoint.
7672   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7673   ins_pipe(pipe_class_default);
7674 %}
7675 
7676 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7677   match(Set res (GetAndSetP mem_ptr src));
7678   effect(TEMP cr0);
7679   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7680   // Variable size: instruction count smaller if regs are disjoint.
7681   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7682   ins_pipe(pipe_class_default);
7683 %}
7684 
7685 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7686   match(Set res (GetAndSetN mem_ptr src));
7687   effect(TEMP cr0);
7688   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7689   // Variable size: instruction count smaller if regs are disjoint.
7690   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7691   ins_pipe(pipe_class_default);
7692 %}
7693 
7694 //----------Arithmetic Instructions--------------------------------------------
7695 // Addition Instructions
7696 
7697 // Register Addition
7698 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7699   match(Set dst (AddI src1 src2));
7700   format %{ "ADD     $dst, $src1, $src2" %}
7701   size(4);
7702   ins_encode %{
7703     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7704     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7705   %}
7706   ins_pipe(pipe_class_default);
7707 %}
7708 
7709 // Expand does not work with above instruct. (??)
7710 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7711   // no match-rule
7712   effect(DEF dst, USE src1, USE src2);
7713   format %{ "ADD     $dst, $src1, $src2" %}
7714   size(4);
7715   ins_encode %{
7716     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7717     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7718   %}
7719   ins_pipe(pipe_class_default);
7720 %}
7721 
7722 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7723   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7724   ins_cost(DEFAULT_COST*3);
7725 
7726   expand %{
7727     // FIXME: we should do this in the ideal world.
7728     iRegIdst tmp1;
7729     iRegIdst tmp2;
7730     addI_reg_reg(tmp1, src1, src2);
7731     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7732     addI_reg_reg(dst, tmp1, tmp2);
7733   %}
7734 %}
7735 
7736 // Immediate Addition
7737 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7738   match(Set dst (AddI src1 src2));
7739   format %{ "ADDI    $dst, $src1, $src2" %}
7740   size(4);
7741   ins_encode %{
7742     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7743     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7744   %}
7745   ins_pipe(pipe_class_default);
7746 %}
7747 
7748 // Immediate Addition with 16-bit shifted operand
7749 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7750   match(Set dst (AddI src1 src2));
7751   format %{ "ADDIS   $dst, $src1, $src2" %}
7752   size(4);
7753   ins_encode %{
7754     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7755     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7756   %}
7757   ins_pipe(pipe_class_default);
7758 %}
7759 
7760 // Long Addition
7761 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7762   match(Set dst (AddL src1 src2));
7763   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7764   size(4);
7765   ins_encode %{
7766     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7767     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7768   %}
7769   ins_pipe(pipe_class_default);
7770 %}
7771 
7772 // Expand does not work with above instruct. (??)
7773 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7774   // no match-rule
7775   effect(DEF dst, USE src1, USE src2);
7776   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7777   size(4);
7778   ins_encode %{
7779     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7780     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7781   %}
7782   ins_pipe(pipe_class_default);
7783 %}
7784 
7785 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7786   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7787   ins_cost(DEFAULT_COST*3);
7788 
7789   expand %{
7790     // FIXME: we should do this in the ideal world.
7791     iRegLdst tmp1;
7792     iRegLdst tmp2;
7793     addL_reg_reg(tmp1, src1, src2);
7794     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7795     addL_reg_reg(dst, tmp1, tmp2);
7796   %}
7797 %}
7798 
7799 // AddL + ConvL2I.
7800 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7801   match(Set dst (ConvL2I (AddL src1 src2)));
7802 
7803   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
7804   size(4);
7805   ins_encode %{
7806     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7807     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7808   %}
7809   ins_pipe(pipe_class_default);
7810 %}
7811 
7812 // No constant pool entries required.
7813 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7814   match(Set dst (AddL src1 src2));
7815 
7816   format %{ "ADDI    $dst, $src1, $src2" %}
7817   size(4);
7818   ins_encode %{
7819     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7820     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7821   %}
7822   ins_pipe(pipe_class_default);
7823 %}
7824 
7825 // Long Immediate Addition with 16-bit shifted operand.
7826 // No constant pool entries required.
7827 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7828   match(Set dst (AddL src1 src2));
7829 
7830   format %{ "ADDIS   $dst, $src1, $src2" %}
7831   size(4);
7832   ins_encode %{
7833     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7834     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7835   %}
7836   ins_pipe(pipe_class_default);
7837 %}
7838 
7839 // Pointer Register Addition
7840 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7841   match(Set dst (AddP src1 src2));
7842   format %{ "ADD     $dst, $src1, $src2" %}
7843   size(4);
7844   ins_encode %{
7845     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7846     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7847   %}
7848   ins_pipe(pipe_class_default);
7849 %}
7850 
7851 // Pointer Immediate Addition
7852 // No constant pool entries required.
7853 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7854   match(Set dst (AddP src1 src2));
7855 
7856   format %{ "ADDI    $dst, $src1, $src2" %}
7857   size(4);
7858   ins_encode %{
7859     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7860     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7861   %}
7862   ins_pipe(pipe_class_default);
7863 %}
7864 
7865 // Pointer Immediate Addition with 16-bit shifted operand.
7866 // No constant pool entries required.
7867 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7868   match(Set dst (AddP src1 src2));
7869 
7870   format %{ "ADDIS   $dst, $src1, $src2" %}
7871   size(4);
7872   ins_encode %{
7873     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7874     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7875   %}
7876   ins_pipe(pipe_class_default);
7877 %}
7878 
7879 //---------------------
7880 // Subtraction Instructions
7881 
7882 // Register Subtraction
7883 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7884   match(Set dst (SubI src1 src2));
7885   format %{ "SUBF    $dst, $src2, $src1" %}
7886   size(4);
7887   ins_encode %{
7888     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7889     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7890   %}
7891   ins_pipe(pipe_class_default);
7892 %}
7893 
7894 // Immediate Subtraction
7895 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7896 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7897 
7898 // SubI from constant (using subfic).
7899 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7900   match(Set dst (SubI src1 src2));
7901   format %{ "SUBI    $dst, $src1, $src2" %}
7902 
7903   size(4);
7904   ins_encode %{
7905     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7906     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7907   %}
7908   ins_pipe(pipe_class_default);
7909 %}
7910 
7911 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7912 // positive integers and 0xF...F for negative ones.
7913 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7914   // no match-rule, false predicate
7915   effect(DEF dst, USE src);
7916   predicate(false);
7917 
7918   format %{ "SRAWI   $dst, $src, #31" %}
7919   size(4);
7920   ins_encode %{
7921     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7922     __ srawi($dst$$Register, $src$$Register, 0x1f);
7923   %}
7924   ins_pipe(pipe_class_default);
7925 %}
7926 
7927 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7928   match(Set dst (AbsI src));
7929   ins_cost(DEFAULT_COST*3);
7930 
7931   expand %{
7932     iRegIdst tmp1;
7933     iRegIdst tmp2;
7934     signmask32I_regI(tmp1, src);
7935     xorI_reg_reg(tmp2, tmp1, src);
7936     subI_reg_reg(dst, tmp2, tmp1);
7937   %}
7938 %}
7939 
7940 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7941   match(Set dst (SubI zero src2));
7942   format %{ "NEG     $dst, $src2" %}
7943   size(4);
7944   ins_encode %{
7945     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7946     __ neg($dst$$Register, $src2$$Register);
7947   %}
7948   ins_pipe(pipe_class_default);
7949 %}
7950 
7951 // Long subtraction
7952 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7953   match(Set dst (SubL src1 src2));
7954   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
7955   size(4);
7956   ins_encode %{
7957     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7958     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7959   %}
7960   ins_pipe(pipe_class_default);
7961 %}
7962 
7963 // SubL + convL2I.
7964 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7965   match(Set dst (ConvL2I (SubL src1 src2)));
7966 
7967   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
7968   size(4);
7969   ins_encode %{
7970     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7971     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7972   %}
7973   ins_pipe(pipe_class_default);
7974 %}
7975 
7976 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7977 // positive longs and 0xF...F for negative ones.
7978 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7979   // no match-rule, false predicate
7980   effect(DEF dst, USE src);
7981   predicate(false);
7982 
7983   format %{ "SRADI   $dst, $src, #63" %}
7984   size(4);
7985   ins_encode %{
7986     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7987     __ sradi($dst$$Register, $src$$Register, 0x3f);
7988   %}
7989   ins_pipe(pipe_class_default);
7990 %}
7991 
7992 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7993 // positive longs and 0xF...F for negative ones.
7994 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7995   // no match-rule, false predicate
7996   effect(DEF dst, USE src);
7997   predicate(false);
7998 
7999   format %{ "SRADI   $dst, $src, #63" %}
8000   size(4);
8001   ins_encode %{
8002     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8003     __ sradi($dst$$Register, $src$$Register, 0x3f);
8004   %}
8005   ins_pipe(pipe_class_default);
8006 %}
8007 
8008 // Long negation
8009 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8010   match(Set dst (SubL zero src2));
8011   format %{ "NEG     $dst, $src2 \t// long" %}
8012   size(4);
8013   ins_encode %{
8014     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8015     __ neg($dst$$Register, $src2$$Register);
8016   %}
8017   ins_pipe(pipe_class_default);
8018 %}
8019 
8020 // NegL + ConvL2I.
8021 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8022   match(Set dst (ConvL2I (SubL zero src2)));
8023 
8024   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
8025   size(4);
8026   ins_encode %{
8027     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8028     __ neg($dst$$Register, $src2$$Register);
8029   %}
8030   ins_pipe(pipe_class_default);
8031 %}
8032 
8033 // Multiplication Instructions
8034 // Integer Multiplication
8035 
8036 // Register Multiplication
8037 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8038   match(Set dst (MulI src1 src2));
8039   ins_cost(DEFAULT_COST);
8040 
8041   format %{ "MULLW   $dst, $src1, $src2" %}
8042   size(4);
8043   ins_encode %{
8044     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8045     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8046   %}
8047   ins_pipe(pipe_class_default);
8048 %}
8049 
8050 // Immediate Multiplication
8051 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8052   match(Set dst (MulI src1 src2));
8053   ins_cost(DEFAULT_COST);
8054 
8055   format %{ "MULLI   $dst, $src1, $src2" %}
8056   size(4);
8057   ins_encode %{
8058     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8059     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8060   %}
8061   ins_pipe(pipe_class_default);
8062 %}
8063 
8064 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8065   match(Set dst (MulL src1 src2));
8066   ins_cost(DEFAULT_COST);
8067 
8068   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
8069   size(4);
8070   ins_encode %{
8071     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8072     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8073   %}
8074   ins_pipe(pipe_class_default);
8075 %}
8076 
8077 // Multiply high for optimized long division by constant.
8078 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8079   match(Set dst (MulHiL src1 src2));
8080   ins_cost(DEFAULT_COST);
8081 
8082   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
8083   size(4);
8084   ins_encode %{
8085     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8086     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8087   %}
8088   ins_pipe(pipe_class_default);
8089 %}
8090 
8091 // Immediate Multiplication
8092 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8093   match(Set dst (MulL src1 src2));
8094   ins_cost(DEFAULT_COST);
8095 
8096   format %{ "MULLI   $dst, $src1, $src2" %}
8097   size(4);
8098   ins_encode %{
8099     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8100     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8101   %}
8102   ins_pipe(pipe_class_default);
8103 %}
8104 
8105 // Integer Division with Immediate -1: Negate.
8106 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8107   match(Set dst (DivI src1 src2));
8108   ins_cost(DEFAULT_COST);
8109 
8110   format %{ "NEG     $dst, $src1 \t// /-1" %}
8111   size(4);
8112   ins_encode %{
8113     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8114     __ neg($dst$$Register, $src1$$Register);
8115   %}
8116   ins_pipe(pipe_class_default);
8117 %}
8118 
8119 // Integer Division with constant, but not -1.
8120 // We should be able to improve this by checking the type of src2.
8121 // It might well be that src2 is known to be positive.
8122 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8123   match(Set dst (DivI src1 src2));
8124   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8125   ins_cost(2*DEFAULT_COST);
8126 
8127   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
8128   size(4);
8129   ins_encode %{
8130     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8131     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8132   %}
8133   ins_pipe(pipe_class_default);
8134 %}
8135 
8136 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8137   effect(USE_DEF dst, USE src1, USE crx);
8138   predicate(false);
8139 
8140   ins_variable_size_depending_on_alignment(true);
8141 
8142   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8143   // Worst case is branch + move + stop, no stop without scheduler.
8144   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8145   ins_encode %{
8146     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8147     Label done;
8148     __ bne($crx$$CondRegister, done);
8149     __ neg($dst$$Register, $src1$$Register);
8150     // TODO PPC port __ endgroup_if_needed(_size == 12);
8151     __ bind(done);
8152   %}
8153   ins_pipe(pipe_class_default);
8154 %}
8155 
8156 // Integer Division with Registers not containing constants.
8157 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8158   match(Set dst (DivI src1 src2));
8159   ins_cost(10*DEFAULT_COST);
8160 
8161   expand %{
8162     immI16 imm %{ (int)-1 %}
8163     flagsReg tmp1;
8164     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8165     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8166     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8167   %}
8168 %}
8169 
8170 // Long Division with Immediate -1: Negate.
8171 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8172   match(Set dst (DivL src1 src2));
8173   ins_cost(DEFAULT_COST);
8174 
8175   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
8176   size(4);
8177   ins_encode %{
8178     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8179     __ neg($dst$$Register, $src1$$Register);
8180   %}
8181   ins_pipe(pipe_class_default);
8182 %}
8183 
8184 // Long Division with constant, but not -1.
8185 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8186   match(Set dst (DivL src1 src2));
8187   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8188   ins_cost(2*DEFAULT_COST);
8189 
8190   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
8191   size(4);
8192   ins_encode %{
8193     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8194     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8195   %}
8196   ins_pipe(pipe_class_default);
8197 %}
8198 
8199 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8200   effect(USE_DEF dst, USE src1, USE crx);
8201   predicate(false);
8202 
8203   ins_variable_size_depending_on_alignment(true);
8204 
8205   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8206   // Worst case is branch + move + stop, no stop without scheduler.
8207   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8208   ins_encode %{
8209     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8210     Label done;
8211     __ bne($crx$$CondRegister, done);
8212     __ neg($dst$$Register, $src1$$Register);
8213     // TODO PPC port __ endgroup_if_needed(_size == 12);
8214     __ bind(done);
8215   %}
8216   ins_pipe(pipe_class_default);
8217 %}
8218 
8219 // Long Division with Registers not containing constants.
8220 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8221   match(Set dst (DivL src1 src2));
8222   ins_cost(10*DEFAULT_COST);
8223 
8224   expand %{
8225     immL16 imm %{ (int)-1 %}
8226     flagsReg tmp1;
8227     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8228     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8229     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8230   %}
8231 %}
8232 
8233 // Integer Remainder with registers.
8234 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8235   match(Set dst (ModI src1 src2));
8236   ins_cost(10*DEFAULT_COST);
8237 
8238   expand %{
8239     immI16 imm %{ (int)-1 %}
8240     flagsReg tmp1;
8241     iRegIdst tmp2;
8242     iRegIdst tmp3;
8243     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
8244     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
8245     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
8246     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
8247     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
8248   %}
8249 %}
8250 
8251 // Long Remainder with registers
8252 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8253   match(Set dst (ModL src1 src2));
8254   ins_cost(10*DEFAULT_COST);
8255 
8256   expand %{
8257     immL16 imm %{ (int)-1 %}
8258     flagsReg tmp1;
8259     iRegLdst tmp2;
8260     iRegLdst tmp3;
8261     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
8262     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
8263     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
8264     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
8265     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
8266   %}
8267 %}
8268 
8269 // Integer Shift Instructions
8270 
8271 // Register Shift Left
8272 
8273 // Clear all but the lowest #mask bits.
8274 // Used to normalize shift amounts in registers.
8275 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8276   // no match-rule, false predicate
8277   effect(DEF dst, USE src, USE mask);
8278   predicate(false);
8279 
8280   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
8281   size(4);
8282   ins_encode %{
8283     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8284     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8285   %}
8286   ins_pipe(pipe_class_default);
8287 %}
8288 
8289 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8290   // no match-rule, false predicate
8291   effect(DEF dst, USE src1, USE src2);
8292   predicate(false);
8293 
8294   format %{ "SLW     $dst, $src1, $src2" %}
8295   size(4);
8296   ins_encode %{
8297     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8298     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8299   %}
8300   ins_pipe(pipe_class_default);
8301 %}
8302 
8303 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8304   match(Set dst (LShiftI src1 src2));
8305   ins_cost(DEFAULT_COST*2);
8306   expand %{
8307     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8308     iRegIdst tmpI;
8309     maskI_reg_imm(tmpI, src2, mask);
8310     lShiftI_reg_reg(dst, src1, tmpI);
8311   %}
8312 %}
8313 
8314 // Register Shift Left Immediate
8315 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8316   match(Set dst (LShiftI src1 src2));
8317 
8318   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
8319   size(4);
8320   ins_encode %{
8321     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8322     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8323   %}
8324   ins_pipe(pipe_class_default);
8325 %}
8326 
8327 // AndI with negpow2-constant + LShiftI
8328 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8329   match(Set dst (LShiftI (AndI src1 src2) src3));
8330   predicate(UseRotateAndMaskInstructionsPPC64);
8331 
8332   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8333   size(4);
8334   ins_encode %{
8335     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8336     long src2      = $src2$$constant;
8337     long src3      = $src3$$constant;
8338     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8339     if (maskbits >= 32) {
8340       __ li($dst$$Register, 0); // addi
8341     } else {
8342       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8343     }
8344   %}
8345   ins_pipe(pipe_class_default);
8346 %}
8347 
8348 // RShiftI + AndI with negpow2-constant + LShiftI
8349 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8350   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8351   predicate(UseRotateAndMaskInstructionsPPC64);
8352 
8353   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8354   size(4);
8355   ins_encode %{
8356     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8357     long src2      = $src2$$constant;
8358     long src3      = $src3$$constant;
8359     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8360     if (maskbits >= 32) {
8361       __ li($dst$$Register, 0); // addi
8362     } else {
8363       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8364     }
8365   %}
8366   ins_pipe(pipe_class_default);
8367 %}
8368 
8369 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8370   // no match-rule, false predicate
8371   effect(DEF dst, USE src1, USE src2);
8372   predicate(false);
8373 
8374   format %{ "SLD     $dst, $src1, $src2" %}
8375   size(4);
8376   ins_encode %{
8377     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8378     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8379   %}
8380   ins_pipe(pipe_class_default);
8381 %}
8382 
8383 // Register Shift Left
8384 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8385   match(Set dst (LShiftL src1 src2));
8386   ins_cost(DEFAULT_COST*2);
8387   expand %{
8388     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8389     iRegIdst tmpI;
8390     maskI_reg_imm(tmpI, src2, mask);
8391     lShiftL_regL_regI(dst, src1, tmpI);
8392   %}
8393 %}
8394 
8395 // Register Shift Left Immediate
8396 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8397   match(Set dst (LShiftL src1 src2));
8398   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
8399   size(4);
8400   ins_encode %{
8401     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8402     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8403   %}
8404   ins_pipe(pipe_class_default);
8405 %}
8406 
8407 // If we shift more than 32 bits, we need not convert I2L.
8408 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8409   match(Set dst (LShiftL (ConvI2L src1) src2));
8410   ins_cost(DEFAULT_COST);
8411 
8412   size(4);
8413   format %{ "SLDI    $dst, i2l($src1), $src2" %}
8414   ins_encode %{
8415     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8416     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8417   %}
8418   ins_pipe(pipe_class_default);
8419 %}
8420 
8421 // Shift a postivie int to the left.
8422 // Clrlsldi clears the upper 32 bits and shifts.
8423 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8424   match(Set dst (LShiftL (ConvI2L src1) src2));
8425   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8426 
8427   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
8428   size(4);
8429   ins_encode %{
8430     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8431     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8432   %}
8433   ins_pipe(pipe_class_default);
8434 %}
8435 
8436 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8437   // no match-rule, false predicate
8438   effect(DEF dst, USE src1, USE src2);
8439   predicate(false);
8440 
8441   format %{ "SRAW    $dst, $src1, $src2" %}
8442   size(4);
8443   ins_encode %{
8444     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8445     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8446   %}
8447   ins_pipe(pipe_class_default);
8448 %}
8449 
8450 // Register Arithmetic Shift Right
8451 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8452   match(Set dst (RShiftI src1 src2));
8453   ins_cost(DEFAULT_COST*2);
8454   expand %{
8455     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8456     iRegIdst tmpI;
8457     maskI_reg_imm(tmpI, src2, mask);
8458     arShiftI_reg_reg(dst, src1, tmpI);
8459   %}
8460 %}
8461 
8462 // Register Arithmetic Shift Right Immediate
8463 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8464   match(Set dst (RShiftI src1 src2));
8465 
8466   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
8467   size(4);
8468   ins_encode %{
8469     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8470     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8471   %}
8472   ins_pipe(pipe_class_default);
8473 %}
8474 
8475 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8476   // no match-rule, false predicate
8477   effect(DEF dst, USE src1, USE src2);
8478   predicate(false);
8479 
8480   format %{ "SRAD    $dst, $src1, $src2" %}
8481   size(4);
8482   ins_encode %{
8483     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8484     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8485   %}
8486   ins_pipe(pipe_class_default);
8487 %}
8488 
8489 // Register Shift Right Arithmetic Long
8490 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8491   match(Set dst (RShiftL src1 src2));
8492   ins_cost(DEFAULT_COST*2);
8493 
8494   expand %{
8495     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8496     iRegIdst tmpI;
8497     maskI_reg_imm(tmpI, src2, mask);
8498     arShiftL_regL_regI(dst, src1, tmpI);
8499   %}
8500 %}
8501 
8502 // Register Shift Right Immediate
8503 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8504   match(Set dst (RShiftL src1 src2));
8505 
8506   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
8507   size(4);
8508   ins_encode %{
8509     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8510     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8511   %}
8512   ins_pipe(pipe_class_default);
8513 %}
8514 
8515 // RShiftL + ConvL2I
8516 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8517   match(Set dst (ConvL2I (RShiftL src1 src2)));
8518 
8519   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8520   size(4);
8521   ins_encode %{
8522     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8523     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8524   %}
8525   ins_pipe(pipe_class_default);
8526 %}
8527 
8528 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8529   // no match-rule, false predicate
8530   effect(DEF dst, USE src1, USE src2);
8531   predicate(false);
8532 
8533   format %{ "SRW     $dst, $src1, $src2" %}
8534   size(4);
8535   ins_encode %{
8536     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8537     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8538   %}
8539   ins_pipe(pipe_class_default);
8540 %}
8541 
8542 // Register Shift Right
8543 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8544   match(Set dst (URShiftI src1 src2));
8545   ins_cost(DEFAULT_COST*2);
8546 
8547   expand %{
8548     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8549     iRegIdst tmpI;
8550     maskI_reg_imm(tmpI, src2, mask);
8551     urShiftI_reg_reg(dst, src1, tmpI);
8552   %}
8553 %}
8554 
8555 // Register Shift Right Immediate
8556 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8557   match(Set dst (URShiftI src1 src2));
8558 
8559   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
8560   size(4);
8561   ins_encode %{
8562     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8563     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8564   %}
8565   ins_pipe(pipe_class_default);
8566 %}
8567 
8568 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8569   // no match-rule, false predicate
8570   effect(DEF dst, USE src1, USE src2);
8571   predicate(false);
8572 
8573   format %{ "SRD     $dst, $src1, $src2" %}
8574   size(4);
8575   ins_encode %{
8576     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8577     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8578   %}
8579   ins_pipe(pipe_class_default);
8580 %}
8581 
8582 // Register Shift Right
8583 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8584   match(Set dst (URShiftL src1 src2));
8585   ins_cost(DEFAULT_COST*2);
8586 
8587   expand %{
8588     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8589     iRegIdst tmpI;
8590     maskI_reg_imm(tmpI, src2, mask);
8591     urShiftL_regL_regI(dst, src1, tmpI);
8592   %}
8593 %}
8594 
8595 // Register Shift Right Immediate
8596 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8597   match(Set dst (URShiftL src1 src2));
8598 
8599   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
8600   size(4);
8601   ins_encode %{
8602     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8603     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8604   %}
8605   ins_pipe(pipe_class_default);
8606 %}
8607 
8608 // URShiftL + ConvL2I.
8609 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8610   match(Set dst (ConvL2I (URShiftL src1 src2)));
8611 
8612   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8613   size(4);
8614   ins_encode %{
8615     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8616     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8617   %}
8618   ins_pipe(pipe_class_default);
8619 %}
8620 
8621 // Register Shift Right Immediate with a CastP2X
8622 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8623   match(Set dst (URShiftL (CastP2X src1) src2));
8624 
8625   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8626   size(4);
8627   ins_encode %{
8628     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8629     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8630   %}
8631   ins_pipe(pipe_class_default);
8632 %}
8633 
8634 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8635   match(Set dst (ConvL2I (ConvI2L src)));
8636 
8637   format %{ "EXTSW   $dst, $src \t// int->int" %}
8638   size(4);
8639   ins_encode %{
8640     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8641     __ extsw($dst$$Register, $src$$Register);
8642   %}
8643   ins_pipe(pipe_class_default);
8644 %}
8645 
8646 //----------Rotate Instructions------------------------------------------------
8647 
8648 // Rotate Left by 8-bit immediate
8649 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8650   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8651   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8652 
8653   format %{ "ROTLWI  $dst, $src, $lshift" %}
8654   size(4);
8655   ins_encode %{
8656     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8657     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8658   %}
8659   ins_pipe(pipe_class_default);
8660 %}
8661 
8662 // Rotate Right by 8-bit immediate
8663 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8664   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8665   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8666 
8667   format %{ "ROTRWI  $dst, $rshift" %}
8668   size(4);
8669   ins_encode %{
8670     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8671     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8672   %}
8673   ins_pipe(pipe_class_default);
8674 %}
8675 
8676 //----------Floating Point Arithmetic Instructions-----------------------------
8677 
8678 // Add float single precision
8679 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8680   match(Set dst (AddF src1 src2));
8681 
8682   format %{ "FADDS   $dst, $src1, $src2" %}
8683   size(4);
8684   ins_encode %{
8685     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8686     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8687   %}
8688   ins_pipe(pipe_class_default);
8689 %}
8690 
8691 // Add float double precision
8692 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8693   match(Set dst (AddD src1 src2));
8694 
8695   format %{ "FADD    $dst, $src1, $src2" %}
8696   size(4);
8697   ins_encode %{
8698     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8699     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8700   %}
8701   ins_pipe(pipe_class_default);
8702 %}
8703 
8704 // Sub float single precision
8705 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8706   match(Set dst (SubF src1 src2));
8707 
8708   format %{ "FSUBS   $dst, $src1, $src2" %}
8709   size(4);
8710   ins_encode %{
8711     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8712     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8713   %}
8714   ins_pipe(pipe_class_default);
8715 %}
8716 
8717 // Sub float double precision
8718 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8719   match(Set dst (SubD src1 src2));
8720   format %{ "FSUB    $dst, $src1, $src2" %}
8721   size(4);
8722   ins_encode %{
8723     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8724     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8725   %}
8726   ins_pipe(pipe_class_default);
8727 %}
8728 
8729 // Mul float single precision
8730 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8731   match(Set dst (MulF src1 src2));
8732   format %{ "FMULS   $dst, $src1, $src2" %}
8733   size(4);
8734   ins_encode %{
8735     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8736     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8737   %}
8738   ins_pipe(pipe_class_default);
8739 %}
8740 
8741 // Mul float double precision
8742 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8743   match(Set dst (MulD src1 src2));
8744   format %{ "FMUL    $dst, $src1, $src2" %}
8745   size(4);
8746   ins_encode %{
8747     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8748     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8749   %}
8750   ins_pipe(pipe_class_default);
8751 %}
8752 
8753 // Div float single precision
8754 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8755   match(Set dst (DivF src1 src2));
8756   format %{ "FDIVS   $dst, $src1, $src2" %}
8757   size(4);
8758   ins_encode %{
8759     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8760     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8761   %}
8762   ins_pipe(pipe_class_default);
8763 %}
8764 
8765 // Div float double precision
8766 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8767   match(Set dst (DivD src1 src2));
8768   format %{ "FDIV    $dst, $src1, $src2" %}
8769   size(4);
8770   ins_encode %{
8771     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8772     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8773   %}
8774   ins_pipe(pipe_class_default);
8775 %}
8776 
8777 // Absolute float single precision
8778 instruct absF_reg(regF dst, regF src) %{
8779   match(Set dst (AbsF src));
8780   format %{ "FABS    $dst, $src \t// float" %}
8781   size(4);
8782   ins_encode %{
8783     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8784     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8785   %}
8786   ins_pipe(pipe_class_default);
8787 %}
8788 
8789 // Absolute float double precision
8790 instruct absD_reg(regD dst, regD src) %{
8791   match(Set dst (AbsD src));
8792   format %{ "FABS    $dst, $src \t// double" %}
8793   size(4);
8794   ins_encode %{
8795     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8796     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8797   %}
8798   ins_pipe(pipe_class_default);
8799 %}
8800 
8801 instruct negF_reg(regF dst, regF src) %{
8802   match(Set dst (NegF src));
8803   format %{ "FNEG    $dst, $src \t// float" %}
8804   size(4);
8805   ins_encode %{
8806     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8807     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8808   %}
8809   ins_pipe(pipe_class_default);
8810 %}
8811 
8812 instruct negD_reg(regD dst, regD src) %{
8813   match(Set dst (NegD src));
8814   format %{ "FNEG    $dst, $src \t// double" %}
8815   size(4);
8816   ins_encode %{
8817     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8818     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8819   %}
8820   ins_pipe(pipe_class_default);
8821 %}
8822 
8823 // AbsF + NegF.
8824 instruct negF_absF_reg(regF dst, regF src) %{
8825   match(Set dst (NegF (AbsF src)));
8826   format %{ "FNABS   $dst, $src \t// float" %}
8827   size(4);
8828   ins_encode %{
8829     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8830     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8831   %}
8832   ins_pipe(pipe_class_default);
8833 %}
8834 
8835 // AbsD + NegD.
8836 instruct negD_absD_reg(regD dst, regD src) %{
8837   match(Set dst (NegD (AbsD src)));
8838   format %{ "FNABS   $dst, $src \t// double" %}
8839   size(4);
8840   ins_encode %{
8841     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8842     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8843   %}
8844   ins_pipe(pipe_class_default);
8845 %}
8846 
8847 // VM_Version::has_fsqrt() decides if this node will be used.
8848 // Sqrt float double precision
8849 instruct sqrtD_reg(regD dst, regD src) %{
8850   match(Set dst (SqrtD src));
8851   format %{ "FSQRT   $dst, $src" %}
8852   size(4);
8853   ins_encode %{
8854     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8855     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8856   %}
8857   ins_pipe(pipe_class_default);
8858 %}
8859 
8860 // Single-precision sqrt.
8861 instruct sqrtF_reg(regF dst, regF src) %{
8862   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8863   predicate(VM_Version::has_fsqrts());
8864   ins_cost(DEFAULT_COST);
8865 
8866   format %{ "FSQRTS  $dst, $src" %}
8867   size(4);
8868   ins_encode %{
8869     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8870     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8871   %}
8872   ins_pipe(pipe_class_default);
8873 %}
8874 
8875 instruct roundDouble_nop(regD dst) %{
8876   match(Set dst (RoundDouble dst));
8877   ins_cost(0);
8878 
8879   format %{ " -- \t// RoundDouble not needed - empty" %}
8880   size(0);
8881   // PPC results are already "rounded" (i.e., normal-format IEEE).
8882   ins_encode( /*empty*/ );
8883   ins_pipe(pipe_class_default);
8884 %}
8885 
8886 instruct roundFloat_nop(regF dst) %{
8887   match(Set dst (RoundFloat dst));
8888   ins_cost(0);
8889 
8890   format %{ " -- \t// RoundFloat not needed - empty" %}
8891   size(0);
8892   // PPC results are already "rounded" (i.e., normal-format IEEE).
8893   ins_encode( /*empty*/ );
8894   ins_pipe(pipe_class_default);
8895 %}
8896 
8897 //----------Logical Instructions-----------------------------------------------
8898 
8899 // And Instructions
8900 
8901 // Register And
8902 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8903   match(Set dst (AndI src1 src2));
8904   format %{ "AND     $dst, $src1, $src2" %}
8905   size(4);
8906   ins_encode %{
8907     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8908     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8909   %}
8910   ins_pipe(pipe_class_default);
8911 %}
8912 
8913 // Immediate And
8914 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8915   match(Set dst (AndI src1 src2));
8916   effect(KILL cr0);
8917 
8918   format %{ "ANDI    $dst, $src1, $src2" %}
8919   size(4);
8920   ins_encode %{
8921     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8922     // FIXME: avoid andi_ ?
8923     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8924   %}
8925   ins_pipe(pipe_class_default);
8926 %}
8927 
8928 // Immediate And where the immediate is a negative power of 2.
8929 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8930   match(Set dst (AndI src1 src2));
8931   format %{ "ANDWI   $dst, $src1, $src2" %}
8932   size(4);
8933   ins_encode %{
8934     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8935     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8936   %}
8937   ins_pipe(pipe_class_default);
8938 %}
8939 
8940 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8941   match(Set dst (AndI src1 src2));
8942   format %{ "ANDWI   $dst, $src1, $src2" %}
8943   size(4);
8944   ins_encode %{
8945     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8946     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8947   %}
8948   ins_pipe(pipe_class_default);
8949 %}
8950 
8951 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8952   match(Set dst (AndI src1 src2));
8953   predicate(UseRotateAndMaskInstructionsPPC64);
8954   format %{ "ANDWI   $dst, $src1, $src2" %}
8955   size(4);
8956   ins_encode %{
8957     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8958     __ rlwinm($dst$$Register, $src1$$Register, 0,
8959               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8960   %}
8961   ins_pipe(pipe_class_default);
8962 %}
8963 
8964 // Register And Long
8965 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8966   match(Set dst (AndL src1 src2));
8967   ins_cost(DEFAULT_COST);
8968 
8969   format %{ "AND     $dst, $src1, $src2 \t// long" %}
8970   size(4);
8971   ins_encode %{
8972     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8973     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8974   %}
8975   ins_pipe(pipe_class_default);
8976 %}
8977 
8978 // Immediate And long
8979 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8980   match(Set dst (AndL src1 src2));
8981   effect(KILL cr0);
8982 
8983   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
8984   size(4);
8985   ins_encode %{
8986     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8987     // FIXME: avoid andi_ ?
8988     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8989   %}
8990   ins_pipe(pipe_class_default);
8991 %}
8992 
8993 // Immediate And Long where the immediate is a negative power of 2.
8994 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8995   match(Set dst (AndL src1 src2));
8996   format %{ "ANDDI   $dst, $src1, $src2" %}
8997   size(4);
8998   ins_encode %{
8999     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9000     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9001   %}
9002   ins_pipe(pipe_class_default);
9003 %}
9004 
9005 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9006   match(Set dst (AndL src1 src2));
9007   format %{ "ANDDI   $dst, $src1, $src2" %}
9008   size(4);
9009   ins_encode %{
9010     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9011     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9012   %}
9013   ins_pipe(pipe_class_default);
9014 %}
9015 
9016 // AndL + ConvL2I.
9017 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9018   match(Set dst (ConvL2I (AndL src1 src2)));
9019   ins_cost(DEFAULT_COST);
9020 
9021   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
9022   size(4);
9023   ins_encode %{
9024     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9025     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9026   %}
9027   ins_pipe(pipe_class_default);
9028 %}
9029 
9030 // Or Instructions
9031 
9032 // Register Or
9033 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9034   match(Set dst (OrI src1 src2));
9035   format %{ "OR      $dst, $src1, $src2" %}
9036   size(4);
9037   ins_encode %{
9038     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9039     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9040   %}
9041   ins_pipe(pipe_class_default);
9042 %}
9043 
9044 // Expand does not work with above instruct. (??)
9045 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9046   // no match-rule
9047   effect(DEF dst, USE src1, USE src2);
9048   format %{ "OR      $dst, $src1, $src2" %}
9049   size(4);
9050   ins_encode %{
9051     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9052     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9053   %}
9054   ins_pipe(pipe_class_default);
9055 %}
9056 
9057 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9058   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9059   ins_cost(DEFAULT_COST*3);
9060 
9061   expand %{
9062     // FIXME: we should do this in the ideal world.
9063     iRegIdst tmp1;
9064     iRegIdst tmp2;
9065     orI_reg_reg(tmp1, src1, src2);
9066     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9067     orI_reg_reg(dst, tmp1, tmp2);
9068   %}
9069 %}
9070 
9071 // Immediate Or
9072 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9073   match(Set dst (OrI src1 src2));
9074   format %{ "ORI     $dst, $src1, $src2" %}
9075   size(4);
9076   ins_encode %{
9077     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9078     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9079   %}
9080   ins_pipe(pipe_class_default);
9081 %}
9082 
9083 // Register Or Long
9084 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9085   match(Set dst (OrL src1 src2));
9086   ins_cost(DEFAULT_COST);
9087 
9088   size(4);
9089   format %{ "OR      $dst, $src1, $src2 \t// long" %}
9090   ins_encode %{
9091     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9092     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9093   %}
9094   ins_pipe(pipe_class_default);
9095 %}
9096 
9097 // OrL + ConvL2I.
9098 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9099   match(Set dst (ConvL2I (OrL src1 src2)));
9100   ins_cost(DEFAULT_COST);
9101 
9102   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
9103   size(4);
9104   ins_encode %{
9105     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9106     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9107   %}
9108   ins_pipe(pipe_class_default);
9109 %}
9110 
9111 // Immediate Or long
9112 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9113   match(Set dst (OrL src1 con));
9114   ins_cost(DEFAULT_COST);
9115 
9116   format %{ "ORI     $dst, $src1, $con \t// long" %}
9117   size(4);
9118   ins_encode %{
9119     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9120     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9121   %}
9122   ins_pipe(pipe_class_default);
9123 %}
9124 
9125 // Xor Instructions
9126 
9127 // Register Xor
9128 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9129   match(Set dst (XorI src1 src2));
9130   format %{ "XOR     $dst, $src1, $src2" %}
9131   size(4);
9132   ins_encode %{
9133     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9134     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9135   %}
9136   ins_pipe(pipe_class_default);
9137 %}
9138 
9139 // Expand does not work with above instruct. (??)
9140 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9141   // no match-rule
9142   effect(DEF dst, USE src1, USE src2);
9143   format %{ "XOR     $dst, $src1, $src2" %}
9144   size(4);
9145   ins_encode %{
9146     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9147     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9148   %}
9149   ins_pipe(pipe_class_default);
9150 %}
9151 
9152 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9153   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9154   ins_cost(DEFAULT_COST*3);
9155 
9156   expand %{
9157     // FIXME: we should do this in the ideal world.
9158     iRegIdst tmp1;
9159     iRegIdst tmp2;
9160     xorI_reg_reg(tmp1, src1, src2);
9161     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9162     xorI_reg_reg(dst, tmp1, tmp2);
9163   %}
9164 %}
9165 
9166 // Immediate Xor
9167 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9168   match(Set dst (XorI src1 src2));
9169   format %{ "XORI    $dst, $src1, $src2" %}
9170   size(4);
9171   ins_encode %{
9172     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9173     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9174   %}
9175   ins_pipe(pipe_class_default);
9176 %}
9177 
9178 // Register Xor Long
9179 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9180   match(Set dst (XorL src1 src2));
9181   ins_cost(DEFAULT_COST);
9182 
9183   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
9184   size(4);
9185   ins_encode %{
9186     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9187     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9188   %}
9189   ins_pipe(pipe_class_default);
9190 %}
9191 
9192 // XorL + ConvL2I.
9193 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9194   match(Set dst (ConvL2I (XorL src1 src2)));
9195   ins_cost(DEFAULT_COST);
9196 
9197   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
9198   size(4);
9199   ins_encode %{
9200     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9201     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9202   %}
9203   ins_pipe(pipe_class_default);
9204 %}
9205 
9206 // Immediate Xor Long
9207 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9208   match(Set dst (XorL src1 src2));
9209   ins_cost(DEFAULT_COST);
9210 
9211   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
9212   size(4);
9213   ins_encode %{
9214     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9215     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9216   %}
9217   ins_pipe(pipe_class_default);
9218 %}
9219 
9220 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9221   match(Set dst (XorI src1 src2));
9222   ins_cost(DEFAULT_COST);
9223 
9224   format %{ "NOT     $dst, $src1 ($src2)" %}
9225   size(4);
9226   ins_encode %{
9227     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9228     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9229   %}
9230   ins_pipe(pipe_class_default);
9231 %}
9232 
9233 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9234   match(Set dst (XorL src1 src2));
9235   ins_cost(DEFAULT_COST);
9236 
9237   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
9238   size(4);
9239   ins_encode %{
9240     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9241     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9242   %}
9243   ins_pipe(pipe_class_default);
9244 %}
9245 
9246 // And-complement
9247 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9248   match(Set dst (AndI (XorI src1 src2) src3));
9249   ins_cost(DEFAULT_COST);
9250 
9251   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
9252   size(4);
9253   ins_encode( enc_andc(dst, src3, src1) );
9254   ins_pipe(pipe_class_default);
9255 %}
9256 
9257 // And-complement
9258 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9259   // no match-rule, false predicate
9260   effect(DEF dst, USE src1, USE src2);
9261   predicate(false);
9262 
9263   format %{ "ANDC    $dst, $src1, $src2" %}
9264   size(4);
9265   ins_encode %{
9266     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9267     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9268   %}
9269   ins_pipe(pipe_class_default);
9270 %}
9271 
9272 //----------Moves between int/long and float/double----------------------------
9273 //
9274 // The following rules move values from int/long registers/stack-locations
9275 // to float/double registers/stack-locations and vice versa, without doing any
9276 // conversions. These rules are used to implement the bit-conversion methods
9277 // of java.lang.Float etc., e.g.
9278 //   int   floatToIntBits(float value)
9279 //   float intBitsToFloat(int bits)
9280 //
9281 // Notes on the implementation on ppc64:
9282 // We only provide rules which move between a register and a stack-location,
9283 // because we always have to go through memory when moving between a float
9284 // register and an integer register.
9285 
9286 //---------- Chain stack slots between similar types --------
9287 
9288 // These are needed so that the rules below can match.
9289 
9290 // Load integer from stack slot
9291 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9292   match(Set dst src);
9293   ins_cost(MEMORY_REF_COST);
9294 
9295   format %{ "LWZ     $dst, $src" %}
9296   size(4);
9297   ins_encode( enc_lwz(dst, src) );
9298   ins_pipe(pipe_class_memory);
9299 %}
9300 
9301 // Store integer to stack slot
9302 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9303   match(Set dst src);
9304   ins_cost(MEMORY_REF_COST);
9305 
9306   format %{ "STW     $src, $dst \t// stk" %}
9307   size(4);
9308   ins_encode( enc_stw(src, dst) ); // rs=rt
9309   ins_pipe(pipe_class_memory);
9310 %}
9311 
9312 // Load long from stack slot
9313 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9314   match(Set dst src);
9315   ins_cost(MEMORY_REF_COST);
9316 
9317   format %{ "LD      $dst, $src \t// long" %}
9318   size(4);
9319   ins_encode( enc_ld(dst, src) );
9320   ins_pipe(pipe_class_memory);
9321 %}
9322 
9323 // Store long to stack slot
9324 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9325   match(Set dst src);
9326   ins_cost(MEMORY_REF_COST);
9327 
9328   format %{ "STD     $src, $dst \t// long" %}
9329   size(4);
9330   ins_encode( enc_std(src, dst) ); // rs=rt
9331   ins_pipe(pipe_class_memory);
9332 %}
9333 
9334 //----------Moves between int and float
9335 
9336 // Move float value from float stack-location to integer register.
9337 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9338   match(Set dst (MoveF2I src));
9339   ins_cost(MEMORY_REF_COST);
9340 
9341   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
9342   size(4);
9343   ins_encode( enc_lwz(dst, src) );
9344   ins_pipe(pipe_class_memory);
9345 %}
9346 
9347 // Move float value from float register to integer stack-location.
9348 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9349   match(Set dst (MoveF2I src));
9350   ins_cost(MEMORY_REF_COST);
9351 
9352   format %{ "STFS    $src, $dst \t// MoveF2I" %}
9353   size(4);
9354   ins_encode( enc_stfs(src, dst) );
9355   ins_pipe(pipe_class_memory);
9356 %}
9357 
9358 // Move integer value from integer stack-location to float register.
9359 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9360   match(Set dst (MoveI2F src));
9361   ins_cost(MEMORY_REF_COST);
9362 
9363   format %{ "LFS     $dst, $src \t// MoveI2F" %}
9364   size(4);
9365   ins_encode %{
9366     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9367     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9368     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9369   %}
9370   ins_pipe(pipe_class_memory);
9371 %}
9372 
9373 // Move integer value from integer register to float stack-location.
9374 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9375   match(Set dst (MoveI2F src));
9376   ins_cost(MEMORY_REF_COST);
9377 
9378   format %{ "STW     $src, $dst \t// MoveI2F" %}
9379   size(4);
9380   ins_encode( enc_stw(src, dst) );
9381   ins_pipe(pipe_class_memory);
9382 %}
9383 
9384 //----------Moves between long and float
9385 
9386 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9387   // no match-rule, false predicate
9388   effect(DEF dst, USE src);
9389   predicate(false);
9390 
9391   format %{ "storeD  $src, $dst \t// STACK" %}
9392   size(4);
9393   ins_encode( enc_stfd(src, dst) );
9394   ins_pipe(pipe_class_default);
9395 %}
9396 
9397 //----------Moves between long and double
9398 
9399 // Move double value from double stack-location to long register.
9400 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9401   match(Set dst (MoveD2L src));
9402   ins_cost(MEMORY_REF_COST);
9403   size(4);
9404   format %{ "LD      $dst, $src \t// MoveD2L" %}
9405   ins_encode( enc_ld(dst, src) );
9406   ins_pipe(pipe_class_memory);
9407 %}
9408 
9409 // Move double value from double register to long stack-location.
9410 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9411   match(Set dst (MoveD2L src));
9412   effect(DEF dst, USE src);
9413   ins_cost(MEMORY_REF_COST);
9414 
9415   format %{ "STFD    $src, $dst \t// MoveD2L" %}
9416   size(4);
9417   ins_encode( enc_stfd(src, dst) );
9418   ins_pipe(pipe_class_memory);
9419 %}
9420 
9421 // Move long value from long stack-location to double register.
9422 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9423   match(Set dst (MoveL2D src));
9424   ins_cost(MEMORY_REF_COST);
9425 
9426   format %{ "LFD     $dst, $src \t// MoveL2D" %}
9427   size(4);
9428   ins_encode( enc_lfd(dst, src) );
9429   ins_pipe(pipe_class_memory);
9430 %}
9431 
9432 // Move long value from long register to double stack-location.
9433 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9434   match(Set dst (MoveL2D src));
9435   ins_cost(MEMORY_REF_COST);
9436 
9437   format %{ "STD     $src, $dst \t// MoveL2D" %}
9438   size(4);
9439   ins_encode( enc_std(src, dst) );
9440   ins_pipe(pipe_class_memory);
9441 %}
9442 
9443 //----------Register Move Instructions-----------------------------------------
9444 
9445 // Replicate for Superword
9446 
9447 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9448   predicate(false);
9449   effect(DEF dst, USE src);
9450 
9451   format %{ "MR      $dst, $src \t// replicate " %}
9452   // variable size, 0 or 4.
9453   ins_encode %{
9454     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9455     __ mr_if_needed($dst$$Register, $src$$Register);
9456   %}
9457   ins_pipe(pipe_class_default);
9458 %}
9459 
9460 //----------Cast instructions (Java-level type cast)---------------------------
9461 
9462 // Cast Long to Pointer for unsafe natives.
9463 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9464   match(Set dst (CastX2P src));
9465 
9466   format %{ "MR      $dst, $src \t// Long->Ptr" %}
9467   // variable size, 0 or 4.
9468   ins_encode %{
9469     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9470     __ mr_if_needed($dst$$Register, $src$$Register);
9471   %}
9472  ins_pipe(pipe_class_default);
9473 %}
9474 
9475 // Cast Pointer to Long for unsafe natives.
9476 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9477   match(Set dst (CastP2X src));
9478 
9479   format %{ "MR      $dst, $src \t// Ptr->Long" %}
9480   // variable size, 0 or 4.
9481   ins_encode %{
9482     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9483     __ mr_if_needed($dst$$Register, $src$$Register);
9484   %}
9485   ins_pipe(pipe_class_default);
9486 %}
9487 
9488 instruct castPP(iRegPdst dst) %{
9489   match(Set dst (CastPP dst));
9490   format %{ " -- \t// castPP of $dst" %}
9491   size(0);
9492   ins_encode( /*empty*/ );
9493   ins_pipe(pipe_class_default);
9494 %}
9495 
9496 instruct castII(iRegIdst dst) %{
9497   match(Set dst (CastII dst));
9498   format %{ " -- \t// castII of $dst" %}
9499   size(0);
9500   ins_encode( /*empty*/ );
9501   ins_pipe(pipe_class_default);
9502 %}
9503 
9504 instruct checkCastPP(iRegPdst dst) %{
9505   match(Set dst (CheckCastPP dst));
9506   format %{ " -- \t// checkcastPP of $dst" %}
9507   size(0);
9508   ins_encode( /*empty*/ );
9509   ins_pipe(pipe_class_default);
9510 %}
9511 
9512 //----------Convert instructions-----------------------------------------------
9513 
9514 // Convert to boolean.
9515 
9516 // int_to_bool(src) : { 1   if src != 0
9517 //                    { 0   else
9518 //
9519 // strategy:
9520 // 1) Count leading zeros of 32 bit-value src,
9521 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9522 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9523 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9524 
9525 // convI2Bool
9526 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9527   match(Set dst (Conv2B src));
9528   predicate(UseCountLeadingZerosInstructionsPPC64);
9529   ins_cost(DEFAULT_COST);
9530 
9531   expand %{
9532     immI shiftAmount %{ 0x5 %}
9533     uimmI16 mask %{ 0x1 %}
9534     iRegIdst tmp1;
9535     iRegIdst tmp2;
9536     countLeadingZerosI(tmp1, src);
9537     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9538     xorI_reg_uimm16(dst, tmp2, mask);
9539   %}
9540 %}
9541 
9542 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9543   match(Set dst (Conv2B src));
9544   effect(TEMP crx);
9545   predicate(!UseCountLeadingZerosInstructionsPPC64);
9546   ins_cost(DEFAULT_COST);
9547 
9548   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
9549             "LI      $dst, #0\n\t"
9550             "BEQ     $crx, done\n\t"
9551             "LI      $dst, #1\n"
9552             "done:" %}
9553   size(16);
9554   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9555   ins_pipe(pipe_class_compare);
9556 %}
9557 
9558 // ConvI2B + XorI
9559 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9560   match(Set dst (XorI (Conv2B src) mask));
9561   predicate(UseCountLeadingZerosInstructionsPPC64);
9562   ins_cost(DEFAULT_COST);
9563 
9564   expand %{
9565     immI shiftAmount %{ 0x5 %}
9566     iRegIdst tmp1;
9567     countLeadingZerosI(tmp1, src);
9568     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9569   %}
9570 %}
9571 
9572 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9573   match(Set dst (XorI (Conv2B src) mask));
9574   effect(TEMP crx);
9575   predicate(!UseCountLeadingZerosInstructionsPPC64);
9576   ins_cost(DEFAULT_COST);
9577 
9578   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9579             "LI      $dst, #1\n\t"
9580             "BEQ     $crx, done\n\t"
9581             "LI      $dst, #0\n"
9582             "done:" %}
9583   size(16);
9584   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9585   ins_pipe(pipe_class_compare);
9586 %}
9587 
9588 // AndI 0b0..010..0 + ConvI2B
9589 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9590   match(Set dst (Conv2B (AndI src mask)));
9591   predicate(UseRotateAndMaskInstructionsPPC64);
9592   ins_cost(DEFAULT_COST);
9593 
9594   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9595   size(4);
9596   ins_encode %{
9597     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9598     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9599   %}
9600   ins_pipe(pipe_class_default);
9601 %}
9602 
9603 // Convert pointer to boolean.
9604 //
9605 // ptr_to_bool(src) : { 1   if src != 0
9606 //                    { 0   else
9607 //
9608 // strategy:
9609 // 1) Count leading zeros of 64 bit-value src,
9610 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9611 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9612 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9613 
9614 // ConvP2B
9615 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9616   match(Set dst (Conv2B src));
9617   predicate(UseCountLeadingZerosInstructionsPPC64);
9618   ins_cost(DEFAULT_COST);
9619 
9620   expand %{
9621     immI shiftAmount %{ 0x6 %}
9622     uimmI16 mask %{ 0x1 %}
9623     iRegIdst tmp1;
9624     iRegIdst tmp2;
9625     countLeadingZerosP(tmp1, src);
9626     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9627     xorI_reg_uimm16(dst, tmp2, mask);
9628   %}
9629 %}
9630 
9631 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9632   match(Set dst (Conv2B src));
9633   effect(TEMP crx);
9634   predicate(!UseCountLeadingZerosInstructionsPPC64);
9635   ins_cost(DEFAULT_COST);
9636 
9637   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
9638             "LI      $dst, #0\n\t"
9639             "BEQ     $crx, done\n\t"
9640             "LI      $dst, #1\n"
9641             "done:" %}
9642   size(16);
9643   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9644   ins_pipe(pipe_class_compare);
9645 %}
9646 
9647 // ConvP2B + XorI
9648 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9649   match(Set dst (XorI (Conv2B src) mask));
9650   predicate(UseCountLeadingZerosInstructionsPPC64);
9651   ins_cost(DEFAULT_COST);
9652 
9653   expand %{
9654     immI shiftAmount %{ 0x6 %}
9655     iRegIdst tmp1;
9656     countLeadingZerosP(tmp1, src);
9657     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9658   %}
9659 %}
9660 
9661 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9662   match(Set dst (XorI (Conv2B src) mask));
9663   effect(TEMP crx);
9664   predicate(!UseCountLeadingZerosInstructionsPPC64);
9665   ins_cost(DEFAULT_COST);
9666 
9667   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9668             "LI      $dst, #1\n\t"
9669             "BEQ     $crx, done\n\t"
9670             "LI      $dst, #0\n"
9671             "done:" %}
9672   size(16);
9673   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9674   ins_pipe(pipe_class_compare);
9675 %}
9676 
9677 // if src1 < src2, return -1 else return 0
9678 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9679   match(Set dst (CmpLTMask src1 src2));
9680   ins_cost(DEFAULT_COST*4);
9681 
9682   expand %{
9683     iRegLdst src1s;
9684     iRegLdst src2s;
9685     iRegLdst diff;
9686     convI2L_reg(src1s, src1); // Ensure proper sign extension.
9687     convI2L_reg(src2s, src2); // Ensure proper sign extension.
9688     subL_reg_reg(diff, src1s, src2s);
9689     // Need to consider >=33 bit result, therefore we need signmaskL.
9690     signmask64I_regL(dst, diff);
9691   %}
9692 %}
9693 
9694 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9695   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9696   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
9697   size(4);
9698   ins_encode %{
9699     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9700     __ srawi($dst$$Register, $src1$$Register, 0x1f);
9701   %}
9702   ins_pipe(pipe_class_default);
9703 %}
9704 
9705 //----------Arithmetic Conversion Instructions---------------------------------
9706 
9707 // Convert to Byte  -- nop
9708 // Convert to Short -- nop
9709 
9710 // Convert to Int
9711 
9712 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9713   match(Set dst (RShiftI (LShiftI src amount) amount));
9714   format %{ "EXTSB   $dst, $src \t// byte->int" %}
9715   size(4);
9716   ins_encode %{
9717     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9718     __ extsb($dst$$Register, $src$$Register);
9719   %}
9720   ins_pipe(pipe_class_default);
9721 %}
9722 
9723 // LShiftI 16 + RShiftI 16 converts short to int.
9724 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9725   match(Set dst (RShiftI (LShiftI src amount) amount));
9726   format %{ "EXTSH   $dst, $src \t// short->int" %}
9727   size(4);
9728   ins_encode %{
9729     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9730     __ extsh($dst$$Register, $src$$Register);
9731   %}
9732   ins_pipe(pipe_class_default);
9733 %}
9734 
9735 // ConvL2I + ConvI2L: Sign extend int in long register.
9736 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9737   match(Set dst (ConvI2L (ConvL2I src)));
9738 
9739   format %{ "EXTSW   $dst, $src \t// long->long" %}
9740   size(4);
9741   ins_encode %{
9742     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9743     __ extsw($dst$$Register, $src$$Register);
9744   %}
9745   ins_pipe(pipe_class_default);
9746 %}
9747 
9748 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9749   match(Set dst (ConvL2I src));
9750   format %{ "MR      $dst, $src \t// long->int" %}
9751   // variable size, 0 or 4
9752   ins_encode %{
9753     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9754     __ mr_if_needed($dst$$Register, $src$$Register);
9755   %}
9756   ins_pipe(pipe_class_default);
9757 %}
9758 
9759 instruct convD2IRaw_regD(regD dst, regD src) %{
9760   // no match-rule, false predicate
9761   effect(DEF dst, USE src);
9762   predicate(false);
9763 
9764   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9765   size(4);
9766   ins_encode %{
9767     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9768     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9769   %}
9770   ins_pipe(pipe_class_default);
9771 %}
9772 
9773 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9774   // no match-rule, false predicate
9775   effect(DEF dst, USE crx, USE src);
9776   predicate(false);
9777 
9778   ins_variable_size_depending_on_alignment(true);
9779 
9780   format %{ "cmovI   $crx, $dst, $src" %}
9781   // Worst case is branch + move + stop, no stop without scheduler.
9782   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9783   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9784   ins_pipe(pipe_class_default);
9785 %}
9786 
9787 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9788   // no match-rule, false predicate
9789   effect(DEF dst, USE crx, USE mem);
9790   predicate(false);
9791 
9792   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
9793   postalloc_expand %{
9794     //
9795     // replaces
9796     //
9797     //   region  dst  crx  mem
9798     //    \       |    |   /
9799     //     dst=cmovI_bso_stackSlotL_conLvalue0
9800     //
9801     // with
9802     //
9803     //   region  dst
9804     //    \       /
9805     //     dst=loadConI16(0)
9806     //      |
9807     //      ^  region  dst  crx  mem
9808     //      |   \       |    |    /
9809     //      dst=cmovI_bso_stackSlotL
9810     //
9811 
9812     // Create new nodes.
9813     MachNode *m1 = new loadConI16Node();
9814     MachNode *m2 = new cmovI_bso_stackSlotLNode();
9815 
9816     // inputs for new nodes
9817     m1->add_req(n_region);
9818     m2->add_req(n_region, n_crx, n_mem);
9819 
9820     // precedences for new nodes
9821     m2->add_prec(m1);
9822 
9823     // operands for new nodes
9824     m1->_opnds[0] = op_dst;
9825     m1->_opnds[1] = new immI16Oper(0);
9826 
9827     m2->_opnds[0] = op_dst;
9828     m2->_opnds[1] = op_crx;
9829     m2->_opnds[2] = op_mem;
9830 
9831     // registers for new nodes
9832     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9833     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9834 
9835     // Insert new nodes.
9836     nodes->push(m1);
9837     nodes->push(m2);
9838   %}
9839 %}
9840 
9841 // Double to Int conversion, NaN is mapped to 0.
9842 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9843   match(Set dst (ConvD2I src));
9844   ins_cost(DEFAULT_COST);
9845 
9846   expand %{
9847     regD tmpD;
9848     stackSlotL tmpS;
9849     flagsReg crx;
9850     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9851     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
9852     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
9853     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9854   %}
9855 %}
9856 
9857 instruct convF2IRaw_regF(regF dst, regF src) %{
9858   // no match-rule, false predicate
9859   effect(DEF dst, USE src);
9860   predicate(false);
9861 
9862   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9863   size(4);
9864   ins_encode %{
9865     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9866     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9867   %}
9868   ins_pipe(pipe_class_default);
9869 %}
9870 
9871 // Float to Int conversion, NaN is mapped to 0.
9872 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9873   match(Set dst (ConvF2I src));
9874   ins_cost(DEFAULT_COST);
9875 
9876   expand %{
9877     regF tmpF;
9878     stackSlotL tmpS;
9879     flagsReg crx;
9880     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9881     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
9882     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
9883     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9884   %}
9885 %}
9886 
9887 // Convert to Long
9888 
9889 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9890   match(Set dst (ConvI2L src));
9891   format %{ "EXTSW   $dst, $src \t// int->long" %}
9892   size(4);
9893   ins_encode %{
9894     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9895     __ extsw($dst$$Register, $src$$Register);
9896   %}
9897   ins_pipe(pipe_class_default);
9898 %}
9899 
9900 // Zero-extend: convert unsigned int to long (convUI2L).
9901 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9902   match(Set dst (AndL (ConvI2L src) mask));
9903   ins_cost(DEFAULT_COST);
9904 
9905   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9906   size(4);
9907   ins_encode %{
9908     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9909     __ clrldi($dst$$Register, $src$$Register, 32);
9910   %}
9911   ins_pipe(pipe_class_default);
9912 %}
9913 
9914 // Zero-extend: convert unsigned int to long in long register.
9915 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9916   match(Set dst (AndL src mask));
9917   ins_cost(DEFAULT_COST);
9918 
9919   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9920   size(4);
9921   ins_encode %{
9922     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9923     __ clrldi($dst$$Register, $src$$Register, 32);
9924   %}
9925   ins_pipe(pipe_class_default);
9926 %}
9927 
9928 instruct convF2LRaw_regF(regF dst, regF src) %{
9929   // no match-rule, false predicate
9930   effect(DEF dst, USE src);
9931   predicate(false);
9932 
9933   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9934   size(4);
9935   ins_encode %{
9936     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9937     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9938   %}
9939   ins_pipe(pipe_class_default);
9940 %}
9941 
9942 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9943   // no match-rule, false predicate
9944   effect(DEF dst, USE crx, USE src);
9945   predicate(false);
9946 
9947   ins_variable_size_depending_on_alignment(true);
9948 
9949   format %{ "cmovL   $crx, $dst, $src" %}
9950   // Worst case is branch + move + stop, no stop without scheduler.
9951   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9952   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9953   ins_pipe(pipe_class_default);
9954 %}
9955 
9956 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9957   // no match-rule, false predicate
9958   effect(DEF dst, USE crx, USE mem);
9959   predicate(false);
9960 
9961   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
9962   postalloc_expand %{
9963     //
9964     // replaces
9965     //
9966     //   region  dst  crx  mem
9967     //    \       |    |   /
9968     //     dst=cmovL_bso_stackSlotL_conLvalue0
9969     //
9970     // with
9971     //
9972     //   region  dst
9973     //    \       /
9974     //     dst=loadConL16(0)
9975     //      |
9976     //      ^  region  dst  crx  mem
9977     //      |   \       |    |    /
9978     //      dst=cmovL_bso_stackSlotL
9979     //
9980 
9981     // Create new nodes.
9982     MachNode *m1 = new loadConL16Node();
9983     MachNode *m2 = new cmovL_bso_stackSlotLNode();
9984 
9985     // inputs for new nodes
9986     m1->add_req(n_region);
9987     m2->add_req(n_region, n_crx, n_mem);
9988     m2->add_prec(m1);
9989 
9990     // operands for new nodes
9991     m1->_opnds[0] = op_dst;
9992     m1->_opnds[1] = new immL16Oper(0);
9993     m2->_opnds[0] = op_dst;
9994     m2->_opnds[1] = op_crx;
9995     m2->_opnds[2] = op_mem;
9996 
9997     // registers for new nodes
9998     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9999     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10000 
10001     // Insert new nodes.
10002     nodes->push(m1);
10003     nodes->push(m2);
10004   %}
10005 %}
10006 
10007 // Float to Long conversion, NaN is mapped to 0.
10008 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10009   match(Set dst (ConvF2L src));
10010   ins_cost(DEFAULT_COST);
10011 
10012   expand %{
10013     regF tmpF;
10014     stackSlotL tmpS;
10015     flagsReg crx;
10016     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10017     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
10018     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10019     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10020   %}
10021 %}
10022 
10023 instruct convD2LRaw_regD(regD dst, regD src) %{
10024   // no match-rule, false predicate
10025   effect(DEF dst, USE src);
10026   predicate(false);
10027 
10028   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10029   size(4);
10030   ins_encode %{
10031     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10032     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10033   %}
10034   ins_pipe(pipe_class_default);
10035 %}
10036 
10037 // Double to Long conversion, NaN is mapped to 0.
10038 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10039   match(Set dst (ConvD2L src));
10040   ins_cost(DEFAULT_COST);
10041 
10042   expand %{
10043     regD tmpD;
10044     stackSlotL tmpS;
10045     flagsReg crx;
10046     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10047     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
10048     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10049     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10050   %}
10051 %}
10052 
10053 // Convert to Float
10054 
10055 // Placed here as needed in expand.
10056 instruct convL2DRaw_regD(regD dst, regD src) %{
10057   // no match-rule, false predicate
10058   effect(DEF dst, USE src);
10059   predicate(false);
10060 
10061   format %{ "FCFID $dst, $src \t// convL2D" %}
10062   size(4);
10063   ins_encode %{
10064     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10065     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10066   %}
10067   ins_pipe(pipe_class_default);
10068 %}
10069 
10070 // Placed here as needed in expand.
10071 instruct convD2F_reg(regF dst, regD src) %{
10072   match(Set dst (ConvD2F src));
10073   format %{ "FRSP    $dst, $src \t// convD2F" %}
10074   size(4);
10075   ins_encode %{
10076     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10077     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10078   %}
10079   ins_pipe(pipe_class_default);
10080 %}
10081 
10082 // Integer to Float conversion.
10083 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10084   match(Set dst (ConvI2F src));
10085   predicate(!VM_Version::has_fcfids());
10086   ins_cost(DEFAULT_COST);
10087 
10088   expand %{
10089     iRegLdst tmpL;
10090     stackSlotL tmpS;
10091     regD tmpD;
10092     regD tmpD2;
10093     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10094     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10095     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10096     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
10097     convD2F_reg(dst, tmpD2);             // Convert double to float.
10098   %}
10099 %}
10100 
10101 instruct convL2FRaw_regF(regF dst, regD src) %{
10102   // no match-rule, false predicate
10103   effect(DEF dst, USE src);
10104   predicate(false);
10105 
10106   format %{ "FCFIDS $dst, $src \t// convL2F" %}
10107   size(4);
10108   ins_encode %{
10109     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10110     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10111   %}
10112   ins_pipe(pipe_class_default);
10113 %}
10114 
10115 // Integer to Float conversion. Special version for Power7.
10116 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10117   match(Set dst (ConvI2F src));
10118   predicate(VM_Version::has_fcfids());
10119   ins_cost(DEFAULT_COST);
10120 
10121   expand %{
10122     iRegLdst tmpL;
10123     stackSlotL tmpS;
10124     regD tmpD;
10125     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10126     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10127     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10128     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10129   %}
10130 %}
10131 
10132 // L2F to avoid runtime call.
10133 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10134   match(Set dst (ConvL2F src));
10135   predicate(VM_Version::has_fcfids());
10136   ins_cost(DEFAULT_COST);
10137 
10138   expand %{
10139     stackSlotL tmpS;
10140     regD tmpD;
10141     regL_to_stkL(tmpS, src);             // Store long to stack.
10142     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10143     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10144   %}
10145 %}
10146 
10147 // Moved up as used in expand.
10148 //instruct convD2F_reg(regF dst, regD src) %{%}
10149 
10150 // Convert to Double
10151 
10152 // Integer to Double conversion.
10153 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10154   match(Set dst (ConvI2D src));
10155   ins_cost(DEFAULT_COST);
10156 
10157   expand %{
10158     iRegLdst tmpL;
10159     stackSlotL tmpS;
10160     regD tmpD;
10161     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10162     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10163     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10164     convL2DRaw_regD(dst, tmpD);          // Convert to double.
10165   %}
10166 %}
10167 
10168 // Long to Double conversion
10169 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10170   match(Set dst (ConvL2D src));
10171   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10172 
10173   expand %{
10174     regD tmpD;
10175     moveL2D_stack_reg(tmpD, src);
10176     convL2DRaw_regD(dst, tmpD);
10177   %}
10178 %}
10179 
10180 instruct convF2D_reg(regD dst, regF src) %{
10181   match(Set dst (ConvF2D src));
10182   format %{ "FMR     $dst, $src \t// float->double" %}
10183   // variable size, 0 or 4
10184   ins_encode %{
10185     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10186     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10187   %}
10188   ins_pipe(pipe_class_default);
10189 %}
10190 
10191 //----------Control Flow Instructions------------------------------------------
10192 // Compare Instructions
10193 
10194 // Compare Integers
10195 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10196   match(Set crx (CmpI src1 src2));
10197   size(4);
10198   format %{ "CMPW    $crx, $src1, $src2" %}
10199   ins_encode %{
10200     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10201     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10202   %}
10203   ins_pipe(pipe_class_compare);
10204 %}
10205 
10206 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10207   match(Set crx (CmpI src1 src2));
10208   format %{ "CMPWI   $crx, $src1, $src2" %}
10209   size(4);
10210   ins_encode %{
10211     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10212     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10213   %}
10214   ins_pipe(pipe_class_compare);
10215 %}
10216 
10217 // (src1 & src2) == 0?
10218 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10219   match(Set cr0 (CmpI (AndI src1 src2) zero));
10220   // r0 is killed
10221   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
10222   size(4);
10223   ins_encode %{
10224     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10225     __ andi_(R0, $src1$$Register, $src2$$constant);
10226   %}
10227   ins_pipe(pipe_class_compare);
10228 %}
10229 
10230 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10231   match(Set crx (CmpL src1 src2));
10232   format %{ "CMPD    $crx, $src1, $src2" %}
10233   size(4);
10234   ins_encode %{
10235     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10236     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10237   %}
10238   ins_pipe(pipe_class_compare);
10239 %}
10240 
10241 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10242   match(Set crx (CmpL src1 src2));
10243   format %{ "CMPDI   $crx, $src1, $src2" %}
10244   size(4);
10245   ins_encode %{
10246     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10247     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10248   %}
10249   ins_pipe(pipe_class_compare);
10250 %}
10251 
10252 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10253   match(Set cr0 (CmpL (AndL src1 src2) zero));
10254   // r0 is killed
10255   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
10256   size(4);
10257   ins_encode %{
10258     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10259     __ and_(R0, $src1$$Register, $src2$$Register);
10260   %}
10261   ins_pipe(pipe_class_compare);
10262 %}
10263 
10264 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10265   match(Set cr0 (CmpL (AndL src1 src2) zero));
10266   // r0 is killed
10267   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
10268   size(4);
10269   ins_encode %{
10270     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10271     __ andi_(R0, $src1$$Register, $src2$$constant);
10272   %}
10273   ins_pipe(pipe_class_compare);
10274 %}
10275 
10276 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10277   // no match-rule, false predicate
10278   effect(DEF dst, USE crx);
10279   predicate(false);
10280 
10281   ins_variable_size_depending_on_alignment(true);
10282 
10283   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
10284   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10285   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10286   ins_encode %{
10287     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10288     Label done;
10289     // li(Rdst, 0);              // equal -> 0
10290     __ beq($crx$$CondRegister, done);
10291     __ li($dst$$Register, 1);    // greater -> +1
10292     __ bgt($crx$$CondRegister, done);
10293     __ li($dst$$Register, -1);   // unordered or less -> -1
10294     // TODO: PPC port__ endgroup_if_needed(_size == 20);
10295     __ bind(done);
10296   %}
10297   ins_pipe(pipe_class_compare);
10298 %}
10299 
10300 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10301   // no match-rule, false predicate
10302   effect(DEF dst, USE crx);
10303   predicate(false);
10304 
10305   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10306   postalloc_expand %{
10307     //
10308     // replaces
10309     //
10310     //   region  crx
10311     //    \       |
10312     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10313     //
10314     // with
10315     //
10316     //   region
10317     //    \
10318     //     dst=loadConI16(0)
10319     //      |
10320     //      ^  region  crx
10321     //      |   \       |
10322     //      dst=cmovI_conIvalueMinus1_conIvalue1
10323     //
10324 
10325     // Create new nodes.
10326     MachNode *m1 = new loadConI16Node();
10327     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10328 
10329     // inputs for new nodes
10330     m1->add_req(n_region);
10331     m2->add_req(n_region, n_crx);
10332     m2->add_prec(m1);
10333 
10334     // operands for new nodes
10335     m1->_opnds[0] = op_dst;
10336     m1->_opnds[1] = new immI16Oper(0);
10337     m2->_opnds[0] = op_dst;
10338     m2->_opnds[1] = op_crx;
10339 
10340     // registers for new nodes
10341     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10342     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10343 
10344     // Insert new nodes.
10345     nodes->push(m1);
10346     nodes->push(m2);
10347   %}
10348 %}
10349 
10350 // Manifest a CmpL3 result in an integer register. Very painful.
10351 // This is the test to avoid.
10352 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10353 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10354   match(Set dst (CmpL3 src1 src2));
10355   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10356 
10357   expand %{
10358     flagsReg tmp1;
10359     cmpL_reg_reg(tmp1, src1, src2);
10360     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10361   %}
10362 %}
10363 
10364 // Implicit range checks.
10365 // A range check in the ideal world has one of the following shapes:
10366 //  - (If le (CmpU length index)), (IfTrue  throw exception)
10367 //  - (If lt (CmpU index length)), (IfFalse throw exception)
10368 //
10369 // Match range check 'If le (CmpU length index)'.
10370 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10371   match(If cmp (CmpU src_length index));
10372   effect(USE labl);
10373   predicate(TrapBasedRangeChecks &&
10374             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10375             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10376             (Matcher::branches_to_uncommon_trap(_leaf)));
10377 
10378   ins_is_TrapBasedCheckNode(true);
10379 
10380   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10381   size(4);
10382   ins_encode %{
10383     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10384     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10385       __ trap_range_check_le($src_length$$Register, $index$$constant);
10386     } else {
10387       // Both successors are uncommon traps, probability is 0.
10388       // Node got flipped during fixup flow.
10389       assert($cmp$$cmpcode == 0x9, "must be greater");
10390       __ trap_range_check_g($src_length$$Register, $index$$constant);
10391     }
10392   %}
10393   ins_pipe(pipe_class_trap);
10394 %}
10395 
10396 // Match range check 'If lt (CmpU index length)'.
10397 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10398   match(If cmp (CmpU src_index src_length));
10399   effect(USE labl);
10400   predicate(TrapBasedRangeChecks &&
10401             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10402             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10403             (Matcher::branches_to_uncommon_trap(_leaf)));
10404 
10405   ins_is_TrapBasedCheckNode(true);
10406 
10407   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10408   size(4);
10409   ins_encode %{
10410     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10411     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10412       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10413     } else {
10414       // Both successors are uncommon traps, probability is 0.
10415       // Node got flipped during fixup flow.
10416       assert($cmp$$cmpcode == 0x8, "must be less");
10417       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10418     }
10419   %}
10420   ins_pipe(pipe_class_trap);
10421 %}
10422 
10423 // Match range check 'If lt (CmpU index length)'.
10424 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10425   match(If cmp (CmpU src_index length));
10426   effect(USE labl);
10427   predicate(TrapBasedRangeChecks &&
10428             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10429             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10430             (Matcher::branches_to_uncommon_trap(_leaf)));
10431 
10432   ins_is_TrapBasedCheckNode(true);
10433 
10434   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10435   size(4);
10436   ins_encode %{
10437     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10438     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10439       __ trap_range_check_ge($src_index$$Register, $length$$constant);
10440     } else {
10441       // Both successors are uncommon traps, probability is 0.
10442       // Node got flipped during fixup flow.
10443       assert($cmp$$cmpcode == 0x8, "must be less");
10444       __ trap_range_check_l($src_index$$Register, $length$$constant);
10445     }
10446   %}
10447   ins_pipe(pipe_class_trap);
10448 %}
10449 
10450 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10451   match(Set crx (CmpU src1 src2));
10452   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
10453   size(4);
10454   ins_encode %{
10455     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10456     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10457   %}
10458   ins_pipe(pipe_class_compare);
10459 %}
10460 
10461 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10462   match(Set crx (CmpU src1 src2));
10463   size(4);
10464   format %{ "CMPLWI  $crx, $src1, $src2" %}
10465   ins_encode %{
10466     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10467     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10468   %}
10469   ins_pipe(pipe_class_compare);
10470 %}
10471 
10472 // Implicit zero checks (more implicit null checks).
10473 // No constant pool entries required.
10474 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10475   match(If cmp (CmpN value zero));
10476   effect(USE labl);
10477   predicate(TrapBasedNullChecks &&
10478             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10479             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10480             Matcher::branches_to_uncommon_trap(_leaf));
10481   ins_cost(1);
10482 
10483   ins_is_TrapBasedCheckNode(true);
10484 
10485   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10486   size(4);
10487   ins_encode %{
10488     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10489     if ($cmp$$cmpcode == 0xA) {
10490       __ trap_null_check($value$$Register);
10491     } else {
10492       // Both successors are uncommon traps, probability is 0.
10493       // Node got flipped during fixup flow.
10494       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10495       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10496     }
10497   %}
10498   ins_pipe(pipe_class_trap);
10499 %}
10500 
10501 // Compare narrow oops.
10502 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10503   match(Set crx (CmpN src1 src2));
10504 
10505   size(4);
10506   ins_cost(2);
10507   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
10508   ins_encode %{
10509     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10510     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10511   %}
10512   ins_pipe(pipe_class_compare);
10513 %}
10514 
10515 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10516   match(Set crx (CmpN src1 src2));
10517   // Make this more expensive than zeroCheckN_iReg_imm0.
10518   ins_cost(2);
10519 
10520   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
10521   size(4);
10522   ins_encode %{
10523     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10524     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10525   %}
10526   ins_pipe(pipe_class_compare);
10527 %}
10528 
10529 // Implicit zero checks (more implicit null checks).
10530 // No constant pool entries required.
10531 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10532   match(If cmp (CmpP value zero));
10533   effect(USE labl);
10534   predicate(TrapBasedNullChecks &&
10535             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10536             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10537             Matcher::branches_to_uncommon_trap(_leaf));
10538   ins_cost(1); // Should not be cheaper than zeroCheckN.
10539 
10540   ins_is_TrapBasedCheckNode(true);
10541 
10542   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10543   size(4);
10544   ins_encode %{
10545     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10546     if ($cmp$$cmpcode == 0xA) {
10547       __ trap_null_check($value$$Register);
10548     } else {
10549       // Both successors are uncommon traps, probability is 0.
10550       // Node got flipped during fixup flow.
10551       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10552       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10553     }
10554   %}
10555   ins_pipe(pipe_class_trap);
10556 %}
10557 
10558 // Compare Pointers
10559 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10560   match(Set crx (CmpP src1 src2));
10561   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
10562   size(4);
10563   ins_encode %{
10564     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10565     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10566   %}
10567   ins_pipe(pipe_class_compare);
10568 %}
10569 
10570 // Used in postalloc expand.
10571 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10572   // This match rule prevents reordering of node before a safepoint.
10573   // This only makes sense if this instructions is used exclusively
10574   // for the expansion of EncodeP!
10575   match(Set crx (CmpP src1 src2));
10576   predicate(false);
10577 
10578   format %{ "CMPDI   $crx, $src1, $src2" %}
10579   size(4);
10580   ins_encode %{
10581     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10582     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10583   %}
10584   ins_pipe(pipe_class_compare);
10585 %}
10586 
10587 //----------Float Compares----------------------------------------------------
10588 
10589 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10590   // Needs matchrule, see cmpDUnordered.
10591   match(Set crx (CmpF src1 src2)); 
10592   // no match-rule, false predicate
10593   predicate(false);
10594 
10595   format %{ "cmpFUrd $crx, $src1, $src2" %}
10596   size(4);
10597   ins_encode %{
10598     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10599     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10600   %}
10601   ins_pipe(pipe_class_default);
10602 %}
10603 
10604 instruct cmov_bns_less(flagsReg crx) %{
10605   // no match-rule, false predicate
10606   effect(DEF crx);
10607   predicate(false);
10608 
10609   ins_variable_size_depending_on_alignment(true);
10610 
10611   format %{ "cmov    $crx" %}
10612   // Worst case is branch + move + stop, no stop without scheduler.
10613   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10614   ins_encode %{
10615     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10616     Label done;
10617     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
10618     __ li(R0, 0);
10619     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
10620     // TODO PPC port __ endgroup_if_needed(_size == 16);
10621     __ bind(done);
10622   %}
10623   ins_pipe(pipe_class_default);
10624 %}
10625 
10626 // Compare floating, generate condition code.
10627 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10628   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10629   //
10630   // The following code sequence occurs a lot in mpegaudio:
10631   //
10632   // block BXX:
10633   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10634   //    cmpFUrd CCR6, F11, F9
10635   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10636   //    cmov CCR6
10637   // 8: instruct branchConSched:
10638   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
10639   match(Set crx (CmpF src1 src2));
10640   ins_cost(DEFAULT_COST+BRANCH_COST);
10641 
10642   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
10643   postalloc_expand %{
10644     //
10645     // replaces
10646     //
10647     //   region  src1  src2
10648     //    \       |     |
10649     //     crx=cmpF_reg_reg
10650     //
10651     // with
10652     //
10653     //   region  src1  src2
10654     //    \       |     |
10655     //     crx=cmpFUnordered_reg_reg
10656     //      |
10657     //      ^  region
10658     //      |   \
10659     //      crx=cmov_bns_less
10660     //
10661 
10662     // Create new nodes.
10663     MachNode *m1 = new cmpFUnordered_reg_regNode();
10664     MachNode *m2 = new cmov_bns_lessNode();
10665 
10666     // inputs for new nodes
10667     m1->add_req(n_region, n_src1, n_src2);
10668     m2->add_req(n_region);
10669     m2->add_prec(m1);
10670 
10671     // operands for new nodes
10672     m1->_opnds[0] = op_crx;
10673     m1->_opnds[1] = op_src1;
10674     m1->_opnds[2] = op_src2;
10675     m2->_opnds[0] = op_crx;
10676 
10677     // registers for new nodes
10678     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10679     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10680 
10681     // Insert new nodes.
10682     nodes->push(m1);
10683     nodes->push(m2);
10684   %}
10685 %}
10686 
10687 // Compare float, generate -1,0,1
10688 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10689   match(Set dst (CmpF3 src1 src2));
10690   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10691 
10692   expand %{
10693     flagsReg tmp1;
10694     cmpFUnordered_reg_reg(tmp1, src1, src2);
10695     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10696   %}
10697 %}
10698 
10699 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10700   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the 
10701   // node right before the conditional move using it. 
10702   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10703   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10704   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10705   // conditional move was supposed to be spilled.
10706   match(Set crx (CmpD src1 src2)); 
10707   // False predicate, shall not be matched.
10708   predicate(false);
10709 
10710   format %{ "cmpFUrd $crx, $src1, $src2" %}
10711   size(4);
10712   ins_encode %{
10713     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10714     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10715   %}
10716   ins_pipe(pipe_class_default);
10717 %}
10718 
10719 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10720   match(Set crx (CmpD src1 src2));
10721   ins_cost(DEFAULT_COST+BRANCH_COST);
10722 
10723   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
10724   postalloc_expand %{
10725     //
10726     // replaces
10727     //
10728     //   region  src1  src2
10729     //    \       |     |
10730     //     crx=cmpD_reg_reg
10731     //
10732     // with
10733     //
10734     //   region  src1  src2
10735     //    \       |     |
10736     //     crx=cmpDUnordered_reg_reg
10737     //      |
10738     //      ^  region
10739     //      |   \
10740     //      crx=cmov_bns_less
10741     //
10742 
10743     // create new nodes
10744     MachNode *m1 = new cmpDUnordered_reg_regNode();
10745     MachNode *m2 = new cmov_bns_lessNode();
10746 
10747     // inputs for new nodes
10748     m1->add_req(n_region, n_src1, n_src2);
10749     m2->add_req(n_region);
10750     m2->add_prec(m1);
10751 
10752     // operands for new nodes
10753     m1->_opnds[0] = op_crx;
10754     m1->_opnds[1] = op_src1;
10755     m1->_opnds[2] = op_src2;
10756     m2->_opnds[0] = op_crx;
10757 
10758     // registers for new nodes
10759     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10760     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10761 
10762     // Insert new nodes.
10763     nodes->push(m1);
10764     nodes->push(m2);
10765   %}
10766 %}
10767 
10768 // Compare double, generate -1,0,1
10769 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10770   match(Set dst (CmpD3 src1 src2));
10771   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10772 
10773   expand %{
10774     flagsReg tmp1;
10775     cmpDUnordered_reg_reg(tmp1, src1, src2);
10776     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10777   %}
10778 %}
10779 
10780 //----------Branches---------------------------------------------------------
10781 // Jump
10782 
10783 // Direct Branch.
10784 instruct branch(label labl) %{
10785   match(Goto);
10786   effect(USE labl);
10787   ins_cost(BRANCH_COST);
10788 
10789   format %{ "B       $labl" %}
10790   size(4);
10791   ins_encode %{
10792     // TODO: PPC port $archOpcode(ppc64Opcode_b);
10793      Label d;    // dummy
10794      __ bind(d);
10795      Label* p = $labl$$label;
10796      // `p' is `NULL' when this encoding class is used only to
10797      // determine the size of the encoded instruction.
10798      Label& l = (NULL == p)? d : *(p);
10799      __ b(l);
10800   %}
10801   ins_pipe(pipe_class_default);
10802 %}
10803 
10804 // Conditional Near Branch
10805 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10806   // Same match rule as `branchConFar'.
10807   match(If cmp crx);
10808   effect(USE lbl);
10809   ins_cost(BRANCH_COST);
10810 
10811   // If set to 1 this indicates that the current instruction is a
10812   // short variant of a long branch. This avoids using this
10813   // instruction in first-pass matching. It will then only be used in
10814   // the `Shorten_branches' pass.
10815   ins_short_branch(1);
10816 
10817   format %{ "B$cmp     $crx, $lbl" %}
10818   size(4);
10819   ins_encode( enc_bc(crx, cmp, lbl) );
10820   ins_pipe(pipe_class_default);
10821 %}
10822 
10823 // This is for cases when the ppc64 `bc' instruction does not
10824 // reach far enough. So we emit a far branch here, which is more
10825 // expensive.
10826 //
10827 // Conditional Far Branch
10828 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10829   // Same match rule as `branchCon'.
10830   match(If cmp crx);
10831   effect(USE crx, USE lbl);
10832   predicate(!false /* TODO: PPC port HB_Schedule*/);
10833   // Higher cost than `branchCon'.
10834   ins_cost(5*BRANCH_COST);
10835 
10836   // This is not a short variant of a branch, but the long variant.
10837   ins_short_branch(0);
10838 
10839   format %{ "B_FAR$cmp $crx, $lbl" %}
10840   size(8);
10841   ins_encode( enc_bc_far(crx, cmp, lbl) );
10842   ins_pipe(pipe_class_default);
10843 %}
10844 
10845 // Conditional Branch used with Power6 scheduler (can be far or short).
10846 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10847   // Same match rule as `branchCon'.
10848   match(If cmp crx);
10849   effect(USE crx, USE lbl);
10850   predicate(false /* TODO: PPC port HB_Schedule*/);
10851   // Higher cost than `branchCon'.
10852   ins_cost(5*BRANCH_COST);
10853 
10854   // Actually size doesn't depend on alignment but on shortening.
10855   ins_variable_size_depending_on_alignment(true);
10856   // long variant.
10857   ins_short_branch(0);
10858 
10859   format %{ "B_FAR$cmp $crx, $lbl" %}
10860   size(8); // worst case
10861   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10862   ins_pipe(pipe_class_default);
10863 %}
10864 
10865 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10866   match(CountedLoopEnd cmp crx);
10867   effect(USE labl);
10868   ins_cost(BRANCH_COST);
10869 
10870   // short variant.
10871   ins_short_branch(1);
10872 
10873   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
10874   size(4);
10875   ins_encode( enc_bc(crx, cmp, labl) );
10876   ins_pipe(pipe_class_default);
10877 %}
10878 
10879 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10880   match(CountedLoopEnd cmp crx);
10881   effect(USE labl);
10882   predicate(!false /* TODO: PPC port HB_Schedule */);
10883   ins_cost(BRANCH_COST);
10884 
10885   // Long variant.
10886   ins_short_branch(0);
10887 
10888   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10889   size(8);
10890   ins_encode( enc_bc_far(crx, cmp, labl) );
10891   ins_pipe(pipe_class_default);
10892 %}
10893 
10894 // Conditional Branch used with Power6 scheduler (can be far or short).
10895 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10896   match(CountedLoopEnd cmp crx);
10897   effect(USE labl);
10898   predicate(false /* TODO: PPC port HB_Schedule */);
10899   // Higher cost than `branchCon'.
10900   ins_cost(5*BRANCH_COST);
10901 
10902   // Actually size doesn't depend on alignment but on shortening.
10903   ins_variable_size_depending_on_alignment(true);
10904   // Long variant.
10905   ins_short_branch(0);
10906 
10907   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10908   size(8); // worst case
10909   ins_encode( enc_bc_short_far(crx, cmp, labl) );
10910   ins_pipe(pipe_class_default);
10911 %}
10912 
10913 // ============================================================================
10914 // Java runtime operations, intrinsics and other complex operations.
10915 
10916 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10917 // array for an instance of the superklass. Set a hidden internal cache on a
10918 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10919 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10920 //
10921 // GL TODO: Improve this.
10922 // - result should not be a TEMP
10923 // - Add match rule as on sparc avoiding additional Cmp.
10924 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10925                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10926   match(Set result (PartialSubtypeCheck subklass superklass));
10927   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10928   ins_cost(DEFAULT_COST*10);
10929 
10930   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10931   ins_encode %{
10932     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10933     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10934                                      $tmp_klass$$Register, NULL, $result$$Register);
10935   %}
10936   ins_pipe(pipe_class_default);
10937 %}
10938 
10939 // inlined locking and unlocking
10940 
10941 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10942   match(Set crx (FastLock oop box));
10943   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10944   predicate(!Compile::current()->use_rtm());
10945 
10946   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3" %}
10947   ins_encode %{
10948     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10949     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10950                                  $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10951                                  UseBiasedLocking && !UseOptoBiasInlining);
10952     // If locking was successfull, crx should indicate 'EQ'.
10953     // The compiler generates a branch to the runtime call to
10954     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10955   %}
10956   ins_pipe(pipe_class_compare);
10957 %}
10958 
10959 // Separate version for TM. Use bound register for box to enable USE_KILL.
10960 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10961   match(Set crx (FastLock oop box));
10962   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10963   predicate(Compile::current()->use_rtm());
10964 
10965   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10966   ins_encode %{
10967     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10968     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10969                                  $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10970                                  /*Biased Locking*/ false,
10971                                  _rtm_counters, _stack_rtm_counters,
10972                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10973                                  /*TM*/ true, ra_->C->profile_rtm());
10974     // If locking was successfull, crx should indicate 'EQ'.
10975     // The compiler generates a branch to the runtime call to
10976     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10977   %}
10978   ins_pipe(pipe_class_compare);
10979 %}
10980 
10981 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10982   match(Set crx (FastUnlock oop box));
10983   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10984   predicate(!Compile::current()->use_rtm());
10985 
10986   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
10987   ins_encode %{
10988     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10989     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10990                                    $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10991                                    UseBiasedLocking && !UseOptoBiasInlining,
10992                                    false);
10993     // If unlocking was successfull, crx should indicate 'EQ'.
10994     // The compiler generates a branch to the runtime call to
10995     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10996   %}
10997   ins_pipe(pipe_class_compare);
10998 %}
10999 
11000 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
11001   match(Set crx (FastUnlock oop box));
11002   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11003   predicate(Compile::current()->use_rtm());
11004 
11005   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
11006   ins_encode %{
11007     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11008     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11009                                    $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11010                                    /*Biased Locking*/ false, /*TM*/ true);
11011     // If unlocking was successfull, crx should indicate 'EQ'.
11012     // The compiler generates a branch to the runtime call to
11013     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11014   %}
11015   ins_pipe(pipe_class_compare);
11016 %}
11017 
11018 // Align address.
11019 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11020   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11021 
11022   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
11023   size(4);
11024   ins_encode %{
11025     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11026     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11027   %}
11028   ins_pipe(pipe_class_default);
11029 %}
11030 
11031 // Array size computation.
11032 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11033   match(Set dst (SubL (CastP2X end) (CastP2X start)));
11034 
11035   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
11036   size(4);
11037   ins_encode %{
11038     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11039     __ subf($dst$$Register, $start$$Register, $end$$Register);
11040   %}
11041   ins_pipe(pipe_class_default);
11042 %}
11043 
11044 // Clear-array with dynamic array-size.
11045 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11046   match(Set dummy (ClearArray cnt base));
11047   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11048   ins_cost(MEMORY_REF_COST);
11049 
11050   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11051 
11052   format %{ "ClearArray $cnt, $base" %}
11053   ins_encode %{
11054     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11055     __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11056   %}
11057   ins_pipe(pipe_class_default);
11058 %}
11059 
11060 // String_IndexOf for needle of length 1.
11061 //
11062 // Match needle into immediate operands: no loadConP node needed. Saves one
11063 // register and two instructions over string_indexOf_imm1Node.
11064 //
11065 // Assumes register result differs from all input registers.
11066 //
11067 // Preserves registers haystack, haycnt
11068 // Kills     registers tmp1, tmp2
11069 // Defines   registers result
11070 //
11071 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11072 //
11073 // Unfortunately this does not match too often. In many situations the AddP is used
11074 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11075 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11076                                   immP needleImm, immL offsetImm, immI_1 needlecntImm,
11077                                   iRegIdst tmp1, iRegIdst tmp2,
11078                                   flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11079   predicate(SpecialStringIndexOf);  // type check implicit by parameter type, See Matcher::match_rule_supported
11080   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11081 
11082   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11083 
11084   ins_cost(150);
11085   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11086             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11087 
11088   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11089   ins_encode %{
11090     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11091     immPOper *needleOper = (immPOper *)$needleImm;
11092     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11093     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11094 
11095     __ string_indexof_1($result$$Register,
11096                         $haystack$$Register, $haycnt$$Register,
11097                         R0, needle_values->char_at(0),
11098                         $tmp1$$Register, $tmp2$$Register);
11099   %}
11100   ins_pipe(pipe_class_compare);
11101 %}
11102 
11103 // String_IndexOf for needle of length 1.
11104 //
11105 // Special case requires less registers and emits less instructions.
11106 //
11107 // Assumes register result differs from all input registers.
11108 //
11109 // Preserves registers haystack, haycnt
11110 // Kills     registers tmp1, tmp2, needle
11111 // Defines   registers result
11112 //
11113 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11114 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11115                              rscratch2RegP needle, immI_1 needlecntImm,
11116                              iRegIdst tmp1, iRegIdst tmp2,
11117                              flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11118   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11119   effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11120          TEMP tmp1, TEMP tmp2);
11121   // Required for EA: check if it is still a type_array.
11122   predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11123             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11124   ins_cost(180);
11125 
11126   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11127 
11128   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11129             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11130   ins_encode %{
11131     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11132     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11133     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11134     guarantee(needle_values, "sanity");
11135     if (needle_values != NULL) {
11136       __ string_indexof_1($result$$Register,
11137                           $haystack$$Register, $haycnt$$Register,
11138                           R0, needle_values->char_at(0),
11139                           $tmp1$$Register, $tmp2$$Register);
11140     } else {
11141       __ string_indexof_1($result$$Register,
11142                           $haystack$$Register, $haycnt$$Register,
11143                           $needle$$Register, 0,
11144                           $tmp1$$Register, $tmp2$$Register);
11145     }
11146   %}
11147   ins_pipe(pipe_class_compare);
11148 %}
11149 
11150 // String_IndexOf.
11151 //
11152 // Length of needle as immediate. This saves instruction loading constant needle
11153 // length.
11154 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11155 // completely or do it in vector instruction. This should save registers for
11156 // needlecnt and needle.
11157 //
11158 // Assumes register result differs from all input registers.
11159 // Overwrites haycnt, needlecnt.
11160 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11161 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11162                             iRegPsrc needle, uimmI15 needlecntImm,
11163                             iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11164                             flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11165   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11166   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11167          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11168   // Required for EA: check if it is still a type_array.
11169   predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11170             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11171   ins_cost(250);
11172 
11173   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11174 
11175   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11176             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11177   ins_encode %{
11178     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11179     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11180     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11181 
11182     __ string_indexof($result$$Register,
11183                       $haystack$$Register, $haycnt$$Register,
11184                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11185                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11186   %}
11187   ins_pipe(pipe_class_compare);
11188 %}
11189 
11190 // StrIndexOf node.
11191 //
11192 // Assumes register result differs from all input registers.
11193 // Overwrites haycnt, needlecnt.
11194 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11195 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11196                         iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11197                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11198   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11199   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11200          TEMP_DEF result,
11201          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11202   predicate(SpecialStringIndexOf);  // See Matcher::match_rule_supported.
11203   ins_cost(300);
11204 
11205   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11206 
11207   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11208              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11209   ins_encode %{
11210     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11211     __ string_indexof($result$$Register,
11212                       $haystack$$Register, $haycnt$$Register,
11213                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11214                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11215   %}
11216   ins_pipe(pipe_class_compare);
11217 %}
11218 
11219 // String equals with immediate.
11220 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11221                            iRegPdst tmp1, iRegPdst tmp2,
11222                            flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11223   match(Set result (StrEquals (Binary str1 str2) cntImm));
11224   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11225          KILL cr0, KILL cr6, KILL ctr);
11226   predicate(SpecialStringEquals);  // See Matcher::match_rule_supported.
11227   ins_cost(250);
11228 
11229   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11230 
11231   format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11232             " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11233   ins_encode %{
11234     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11235     __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11236                              $result$$Register, $tmp1$$Register, $tmp2$$Register);
11237   %}
11238   ins_pipe(pipe_class_compare);
11239 %}
11240 
11241 // String equals.
11242 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11243 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11244                        iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11245                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11246   match(Set result (StrEquals (Binary str1 str2) cnt));
11247   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11248          KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11249   predicate(SpecialStringEquals);  // See Matcher::match_rule_supported.
11250   ins_cost(300);
11251 
11252   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11253 
11254   format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11255             " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11256   ins_encode %{
11257     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11258     __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11259                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11260   %}
11261   ins_pipe(pipe_class_compare);
11262 %}
11263 
11264 // String compare.
11265 // Char[] pointers are passed in.
11266 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11267 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11268                         iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11269   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11270   effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11271   ins_cost(300);
11272 
11273   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11274 
11275   format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11276             " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11277   ins_encode %{
11278     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11279     __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11280                       $result$$Register, $tmp$$Register);
11281   %}
11282   ins_pipe(pipe_class_compare);
11283 %}
11284 
11285 //---------- Min/Max Instructions ---------------------------------------------
11286 
11287 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11288   match(Set dst (MinI src1 src2));
11289   ins_cost(DEFAULT_COST*6);
11290 
11291   expand %{
11292     iRegLdst src1s;
11293     iRegLdst src2s;
11294     iRegLdst diff;
11295     iRegLdst sm;
11296     iRegLdst doz; // difference or zero
11297     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11298     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11299     subL_reg_reg(diff, src2s, src1s);
11300     // Need to consider >=33 bit result, therefore we need signmaskL.
11301     signmask64L_regL(sm, diff);
11302     andL_reg_reg(doz, diff, sm); // <=0
11303     addI_regL_regL(dst, doz, src1s);
11304   %}
11305 %}
11306 
11307 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11308   match(Set dst (MaxI src1 src2));
11309   ins_cost(DEFAULT_COST*6);
11310 
11311   expand %{
11312     iRegLdst src1s;
11313     iRegLdst src2s;
11314     iRegLdst diff;
11315     iRegLdst sm;
11316     iRegLdst doz; // difference or zero
11317     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11318     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11319     subL_reg_reg(diff, src2s, src1s);
11320     // Need to consider >=33 bit result, therefore we need signmaskL.
11321     signmask64L_regL(sm, diff);
11322     andcL_reg_reg(doz, diff, sm); // >=0
11323     addI_regL_regL(dst, doz, src1s);
11324   %}
11325 %}
11326 
11327 //---------- Population Count Instructions ------------------------------------
11328 
11329 // Popcnt for Power7.
11330 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11331   match(Set dst (PopCountI src));
11332   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11333   ins_cost(DEFAULT_COST);
11334 
11335   format %{ "POPCNTW $dst, $src" %}
11336   size(4);
11337   ins_encode %{
11338     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11339     __ popcntw($dst$$Register, $src$$Register);
11340   %}
11341   ins_pipe(pipe_class_default);
11342 %}
11343 
11344 // Popcnt for Power7.
11345 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11346   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11347   match(Set dst (PopCountL src));
11348   ins_cost(DEFAULT_COST);
11349 
11350   format %{ "POPCNTD $dst, $src" %}
11351   size(4);
11352   ins_encode %{
11353     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11354     __ popcntd($dst$$Register, $src$$Register);
11355   %}
11356   ins_pipe(pipe_class_default);
11357 %}
11358 
11359 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11360   match(Set dst (CountLeadingZerosI src));
11361   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
11362   ins_cost(DEFAULT_COST);
11363 
11364   format %{ "CNTLZW  $dst, $src" %}
11365   size(4);
11366   ins_encode %{
11367     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11368     __ cntlzw($dst$$Register, $src$$Register);
11369   %}
11370   ins_pipe(pipe_class_default);
11371 %}
11372 
11373 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11374   match(Set dst (CountLeadingZerosL src));
11375   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
11376   ins_cost(DEFAULT_COST);
11377 
11378   format %{ "CNTLZD  $dst, $src" %}
11379   size(4);
11380   ins_encode %{
11381     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11382     __ cntlzd($dst$$Register, $src$$Register);
11383   %}
11384   ins_pipe(pipe_class_default);
11385 %}
11386 
11387 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11388   // no match-rule, false predicate
11389   effect(DEF dst, USE src);
11390   predicate(false);
11391 
11392   format %{ "CNTLZD  $dst, $src" %}
11393   size(4);
11394   ins_encode %{
11395     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11396     __ cntlzd($dst$$Register, $src$$Register);
11397   %}
11398   ins_pipe(pipe_class_default);
11399 %}
11400 
11401 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11402   match(Set dst (CountTrailingZerosI src));
11403   predicate(UseCountLeadingZerosInstructionsPPC64);
11404   ins_cost(DEFAULT_COST);
11405 
11406   expand %{
11407     immI16 imm1 %{ (int)-1 %}
11408     immI16 imm2 %{ (int)32 %}
11409     immI_minus1 m1 %{ -1 %}
11410     iRegIdst tmpI1;
11411     iRegIdst tmpI2;
11412     iRegIdst tmpI3;
11413     addI_reg_imm16(tmpI1, src, imm1);
11414     andcI_reg_reg(tmpI2, src, m1, tmpI1);
11415     countLeadingZerosI(tmpI3, tmpI2);
11416     subI_imm16_reg(dst, imm2, tmpI3);
11417   %}
11418 %}
11419 
11420 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11421   match(Set dst (CountTrailingZerosL src));
11422   predicate(UseCountLeadingZerosInstructionsPPC64);
11423   ins_cost(DEFAULT_COST);
11424 
11425   expand %{
11426     immL16 imm1 %{ (long)-1 %}
11427     immI16 imm2 %{ (int)64 %}
11428     iRegLdst tmpL1;
11429     iRegLdst tmpL2;
11430     iRegIdst tmpL3;
11431     addL_reg_imm16(tmpL1, src, imm1);
11432     andcL_reg_reg(tmpL2, tmpL1, src);
11433     countLeadingZerosL(tmpL3, tmpL2);
11434     subI_imm16_reg(dst, imm2, tmpL3);
11435  %}
11436 %}
11437 
11438 // Expand nodes for byte_reverse_int.
11439 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11440   effect(DEF dst, USE src, USE pos, USE shift);
11441   predicate(false);
11442 
11443   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
11444   size(4);
11445   ins_encode %{
11446     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11447     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11448   %}
11449   ins_pipe(pipe_class_default);
11450 %}
11451 
11452 // As insrwi_a, but with USE_DEF.
11453 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11454   effect(USE_DEF dst, USE src, USE pos, USE shift);
11455   predicate(false);
11456 
11457   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
11458   size(4);
11459   ins_encode %{
11460     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11461     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11462   %}
11463   ins_pipe(pipe_class_default);
11464 %}
11465 
11466 // Just slightly faster than java implementation.
11467 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11468   match(Set dst (ReverseBytesI src));
11469   predicate(UseCountLeadingZerosInstructionsPPC64);
11470   ins_cost(DEFAULT_COST);
11471 
11472   expand %{
11473     immI16 imm24 %{ (int) 24 %}
11474     immI16 imm16 %{ (int) 16 %}
11475     immI16  imm8 %{ (int)  8 %}
11476     immI16  imm4 %{ (int)  4 %}
11477     immI16  imm0 %{ (int)  0 %}
11478     iRegLdst tmpI1;
11479     iRegLdst tmpI2;
11480     iRegLdst tmpI3;
11481 
11482     urShiftI_reg_imm(tmpI1, src, imm24);
11483     insrwi_a(dst, tmpI1, imm24, imm8);
11484     urShiftI_reg_imm(tmpI2, src, imm16);
11485     insrwi(dst, tmpI2, imm8, imm16);
11486     urShiftI_reg_imm(tmpI3, src, imm8);
11487     insrwi(dst, tmpI3, imm8, imm8);
11488     insrwi(dst, src, imm0, imm8);
11489   %}
11490 %}
11491 
11492 //---------- Replicate Vector Instructions ------------------------------------
11493 
11494 // Insrdi does replicate if src == dst.
11495 instruct repl32(iRegLdst dst) %{
11496   predicate(false);
11497   effect(USE_DEF dst);
11498 
11499   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
11500   size(4);
11501   ins_encode %{
11502     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11503     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11504   %}
11505   ins_pipe(pipe_class_default);
11506 %}
11507 
11508 // Insrdi does replicate if src == dst.
11509 instruct repl48(iRegLdst dst) %{
11510   predicate(false);
11511   effect(USE_DEF dst);
11512 
11513   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
11514   size(4);
11515   ins_encode %{
11516     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11517     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11518   %}
11519   ins_pipe(pipe_class_default);
11520 %}
11521 
11522 // Insrdi does replicate if src == dst.
11523 instruct repl56(iRegLdst dst) %{
11524   predicate(false);
11525   effect(USE_DEF dst);
11526 
11527   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
11528   size(4);
11529   ins_encode %{
11530     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11531     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11532   %}
11533   ins_pipe(pipe_class_default);
11534 %}
11535 
11536 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11537   match(Set dst (ReplicateB src));
11538   predicate(n->as_Vector()->length() == 8);
11539   expand %{
11540     moveReg(dst, src);
11541     repl56(dst);
11542     repl48(dst);
11543     repl32(dst);
11544   %}
11545 %}
11546 
11547 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11548   match(Set dst (ReplicateB zero));
11549   predicate(n->as_Vector()->length() == 8);
11550   format %{ "LI      $dst, #0 \t// replicate8B" %}
11551   size(4);
11552   ins_encode %{
11553     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11554     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11555   %}
11556   ins_pipe(pipe_class_default);
11557 %}
11558 
11559 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11560   match(Set dst (ReplicateB src));
11561   predicate(n->as_Vector()->length() == 8);
11562   format %{ "LI      $dst, #-1 \t// replicate8B" %}
11563   size(4);
11564   ins_encode %{
11565     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11566     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11567   %}
11568   ins_pipe(pipe_class_default);
11569 %}
11570 
11571 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11572   match(Set dst (ReplicateS src));
11573   predicate(n->as_Vector()->length() == 4);
11574   expand %{
11575     moveReg(dst, src);
11576     repl48(dst);
11577     repl32(dst);
11578   %}
11579 %}
11580 
11581 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11582   match(Set dst (ReplicateS zero));
11583   predicate(n->as_Vector()->length() == 4);
11584   format %{ "LI      $dst, #0 \t// replicate4C" %}
11585   size(4);
11586   ins_encode %{
11587     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11588     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11589   %}
11590   ins_pipe(pipe_class_default);
11591 %}
11592 
11593 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11594   match(Set dst (ReplicateS src));
11595   predicate(n->as_Vector()->length() == 4);
11596   format %{ "LI      $dst, -1 \t// replicate4C" %}
11597   size(4);
11598   ins_encode %{
11599     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11600     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11601   %}
11602   ins_pipe(pipe_class_default);
11603 %}
11604 
11605 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11606   match(Set dst (ReplicateI src));
11607   predicate(n->as_Vector()->length() == 2);
11608   ins_cost(2 * DEFAULT_COST);
11609   expand %{
11610     moveReg(dst, src);
11611     repl32(dst);
11612   %}
11613 %}
11614 
11615 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11616   match(Set dst (ReplicateI zero));
11617   predicate(n->as_Vector()->length() == 2);
11618   format %{ "LI      $dst, #0 \t// replicate4C" %}
11619   size(4);
11620   ins_encode %{
11621     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11622     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11623   %}
11624   ins_pipe(pipe_class_default);
11625 %}
11626 
11627 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11628   match(Set dst (ReplicateI src));
11629   predicate(n->as_Vector()->length() == 2);
11630   format %{ "LI      $dst, -1 \t// replicate4C" %}
11631   size(4);
11632   ins_encode %{
11633     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11634     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11635   %}
11636   ins_pipe(pipe_class_default);
11637 %}
11638 
11639 // Move float to int register via stack, replicate.
11640 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11641   match(Set dst (ReplicateF src));
11642   predicate(n->as_Vector()->length() == 2);
11643   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11644   expand %{
11645     stackSlotL tmpS;
11646     iRegIdst tmpI;
11647     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
11648     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
11649     moveReg(dst, tmpI);             // Move int to long reg.
11650     repl32(dst);                    // Replicate bitpattern.
11651   %}
11652 %}
11653 
11654 // Replicate scalar constant to packed float values in Double register
11655 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11656   match(Set dst (ReplicateF src));
11657   predicate(n->as_Vector()->length() == 2);
11658   ins_cost(5 * DEFAULT_COST);
11659 
11660   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11661   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11662 %}
11663 
11664 // Replicate scalar zero constant to packed float values in Double register
11665 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11666   match(Set dst (ReplicateF zero));
11667   predicate(n->as_Vector()->length() == 2);
11668 
11669   format %{ "LI      $dst, #0 \t// replicate2F" %}
11670   ins_encode %{
11671     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11672     __ li($dst$$Register, 0x0);
11673   %}
11674   ins_pipe(pipe_class_default);
11675 %}
11676 
11677 
11678 //----------Overflow Math Instructions-----------------------------------------
11679 
11680 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11681 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11682 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11683 
11684 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11685   match(Set cr0 (OverflowAddL op1 op2));
11686 
11687   format %{ "add_    $op1, $op2\t# overflow check long" %}
11688   ins_encode %{
11689     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11690     __ li(R0, 0);
11691     __ mtxer(R0); // clear XER.SO
11692     __ addo_(R0, $op1$$Register, $op2$$Register);
11693   %}
11694   ins_pipe(pipe_class_default);
11695 %}
11696 
11697 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11698   match(Set cr0 (OverflowSubL op1 op2));
11699 
11700   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
11701   ins_encode %{
11702     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11703     __ li(R0, 0);
11704     __ mtxer(R0); // clear XER.SO
11705     __ subfo_(R0, $op2$$Register, $op1$$Register);
11706   %}
11707   ins_pipe(pipe_class_default);
11708 %}
11709 
11710 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11711   match(Set cr0 (OverflowSubL zero op2));
11712 
11713   format %{ "nego_   R0, $op2\t# overflow check long" %}
11714   ins_encode %{
11715     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11716     __ li(R0, 0);
11717     __ mtxer(R0); // clear XER.SO
11718     __ nego_(R0, $op2$$Register);
11719   %}
11720   ins_pipe(pipe_class_default);
11721 %}
11722 
11723 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11724   match(Set cr0 (OverflowMulL op1 op2));
11725 
11726   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11727   ins_encode %{
11728     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11729     __ li(R0, 0);
11730     __ mtxer(R0); // clear XER.SO
11731     __ mulldo_(R0, $op1$$Register, $op2$$Register);
11732   %}
11733   ins_pipe(pipe_class_default);
11734 %}
11735 
11736 
11737 // ============================================================================
11738 // Safepoint Instruction
11739 
11740 instruct safePoint_poll(iRegPdst poll) %{
11741   match(SafePoint poll);
11742   predicate(LoadPollAddressFromThread);
11743 
11744   // It caused problems to add the effect that r0 is killed, but this
11745   // effect no longer needs to be mentioned, since r0 is not contained
11746   // in a reg_class.
11747 
11748   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
11749   size(4);
11750   ins_encode( enc_poll(0x0, poll) );
11751   ins_pipe(pipe_class_default);
11752 %}
11753 
11754 // Safepoint without per-thread support. Load address of page to poll
11755 // as constant.
11756 // Rscratch2RegP is R12.
11757 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11758 // a seperate node so that the oop map is at the right location.
11759 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11760   match(SafePoint poll);
11761   predicate(!LoadPollAddressFromThread);
11762 
11763   // It caused problems to add the effect that r0 is killed, but this
11764   // effect no longer needs to be mentioned, since r0 is not contained
11765   // in a reg_class.
11766 
11767   format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
11768   ins_encode( enc_poll(0x0, poll) );
11769   ins_pipe(pipe_class_default);
11770 %}
11771 
11772 // ============================================================================
11773 // Call Instructions
11774 
11775 // Call Java Static Instruction
11776 
11777 // Schedulable version of call static node.
11778 instruct CallStaticJavaDirect(method meth) %{
11779   match(CallStaticJava);
11780   effect(USE meth);
11781   predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11782   ins_cost(CALL_COST);
11783 
11784   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11785 
11786   format %{ "CALL,static $meth \t// ==> " %}
11787   size(4);
11788   ins_encode( enc_java_static_call(meth) );
11789   ins_pipe(pipe_class_call);
11790 %}
11791 
11792 // Schedulable version of call static node.
11793 instruct CallStaticJavaDirectHandle(method meth) %{
11794   match(CallStaticJava);
11795   effect(USE meth);
11796   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11797   ins_cost(CALL_COST);
11798 
11799   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11800 
11801   format %{ "CALL,static $meth \t// ==> " %}
11802   ins_encode( enc_java_handle_call(meth) );
11803   ins_pipe(pipe_class_call);
11804 %}
11805 
11806 // Call Java Dynamic Instruction
11807 
11808 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11809 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11810 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11811 // The call destination must still be placed in the constant pool.
11812 instruct CallDynamicJavaDirectSched(method meth) %{
11813   match(CallDynamicJava); // To get all the data fields we need ...
11814   effect(USE meth);
11815   predicate(false);       // ... but never match.
11816 
11817   ins_field_load_ic_hi_node(loadConL_hiNode*);
11818   ins_field_load_ic_node(loadConLNode*);
11819   ins_num_consts(1 /* 1 patchable constant: call destination */);
11820 
11821   format %{ "BL        \t// dynamic $meth ==> " %}
11822   size(4);
11823   ins_encode( enc_java_dynamic_call_sched(meth) );
11824   ins_pipe(pipe_class_call);
11825 %}
11826 
11827 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11828 // We use postalloc expanded calls if we use inline caches
11829 // and do not update method data.
11830 //
11831 // This instruction has two constants: inline cache (IC) and call destination.
11832 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11833 // one constant.
11834 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11835   match(CallDynamicJava);
11836   effect(USE meth);
11837   predicate(UseInlineCaches);
11838   ins_cost(CALL_COST);
11839 
11840   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11841 
11842   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11843   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11844 %}
11845 
11846 // Compound version of call dynamic java
11847 // We use postalloc expanded calls if we use inline caches
11848 // and do not update method data.
11849 instruct CallDynamicJavaDirect(method meth) %{
11850   match(CallDynamicJava);
11851   effect(USE meth);
11852   predicate(!UseInlineCaches);
11853   ins_cost(CALL_COST);
11854 
11855   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11856   ins_num_consts(4);
11857 
11858   format %{ "CALL,dynamic $meth \t// ==> " %}
11859   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11860   ins_pipe(pipe_class_call);
11861 %}
11862 
11863 // Call Runtime Instruction
11864 
11865 instruct CallRuntimeDirect(method meth) %{
11866   match(CallRuntime);
11867   effect(USE meth);
11868   ins_cost(CALL_COST);
11869 
11870   // Enc_java_to_runtime_call needs up to 3 constants: call target,
11871   // env for callee, C-toc.
11872   ins_num_consts(3);
11873 
11874   format %{ "CALL,runtime" %}
11875   ins_encode( enc_java_to_runtime_call(meth) );
11876   ins_pipe(pipe_class_call);
11877 %}
11878 
11879 // Call Leaf
11880 
11881 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11882 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11883   effect(DEF dst, USE src);
11884 
11885   ins_num_consts(1);
11886 
11887   format %{ "MTCTR   $src" %}
11888   size(4);
11889   ins_encode( enc_leaf_call_mtctr(src) );
11890   ins_pipe(pipe_class_default);
11891 %}
11892 
11893 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11894 instruct CallLeafDirect(method meth) %{
11895   match(CallLeaf);   // To get the data all the data fields we need ...
11896   effect(USE meth);
11897   predicate(false);  // but never match.
11898 
11899   format %{ "BCTRL     \t// leaf call $meth ==> " %}
11900   size(4);
11901   ins_encode %{
11902     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11903     __ bctrl();
11904   %}
11905   ins_pipe(pipe_class_call);
11906 %}
11907 
11908 // postalloc expand of CallLeafDirect.
11909 // Load adress to call from TOC, then bl to it.
11910 instruct CallLeafDirect_Ex(method meth) %{
11911   match(CallLeaf);
11912   effect(USE meth);
11913   ins_cost(CALL_COST);
11914 
11915   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11916   // env for callee, C-toc.
11917   ins_num_consts(3);
11918 
11919   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11920   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11921 %}
11922 
11923 // Call runtime without safepoint - same as CallLeaf.
11924 // postalloc expand of CallLeafNoFPDirect.
11925 // Load adress to call from TOC, then bl to it.
11926 instruct CallLeafNoFPDirect_Ex(method meth) %{
11927   match(CallLeafNoFP);
11928   effect(USE meth);
11929   ins_cost(CALL_COST);
11930 
11931   // Enc_java_to_runtime_call needs up to 3 constants: call target,
11932   // env for callee, C-toc.
11933   ins_num_consts(3);
11934 
11935   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11936   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11937 %}
11938 
11939 // Tail Call; Jump from runtime stub to Java code.
11940 // Also known as an 'interprocedural jump'.
11941 // Target of jump will eventually return to caller.
11942 // TailJump below removes the return address.
11943 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11944   match(TailCall jump_target method_oop);
11945   ins_cost(CALL_COST);
11946 
11947   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
11948             "BCTR         \t// tail call" %}
11949   size(8);
11950   ins_encode %{
11951     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11952     __ mtctr($jump_target$$Register);
11953     __ bctr();
11954   %}
11955   ins_pipe(pipe_class_call);
11956 %}
11957 
11958 // Return Instruction
11959 instruct Ret() %{
11960   match(Return);
11961   format %{ "BLR      \t// branch to link register" %}
11962   size(4);
11963   ins_encode %{
11964     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11965     // LR is restored in MachEpilogNode. Just do the RET here.
11966     __ blr();
11967   %}
11968   ins_pipe(pipe_class_default);
11969 %}
11970 
11971 // Tail Jump; remove the return address; jump to target.
11972 // TailCall above leaves the return address around.
11973 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11974 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11975 // "restore" before this instruction (in Epilogue), we need to materialize it
11976 // in %i0.
11977 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11978   match(TailJump jump_target ex_oop);
11979   ins_cost(CALL_COST);
11980 
11981   format %{ "LD      R4_ARG2 = LR\n\t"
11982             "MTCTR   $jump_target\n\t"
11983             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
11984   size(12);
11985   ins_encode %{
11986     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11987     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11988     __ mtctr($jump_target$$Register);
11989     __ bctr();
11990   %}
11991   ins_pipe(pipe_class_call);
11992 %}
11993 
11994 // Create exception oop: created by stack-crawling runtime code.
11995 // Created exception is now available to this handler, and is setup
11996 // just prior to jumping to this handler. No code emitted.
11997 instruct CreateException(rarg1RegP ex_oop) %{
11998   match(Set ex_oop (CreateEx));
11999   ins_cost(0);
12000 
12001   format %{ " -- \t// exception oop; no code emitted" %}
12002   size(0);
12003   ins_encode( /*empty*/ );
12004   ins_pipe(pipe_class_default);
12005 %}
12006 
12007 // Rethrow exception: The exception oop will come in the first
12008 // argument position. Then JUMP (not call) to the rethrow stub code.
12009 instruct RethrowException() %{
12010   match(Rethrow);
12011   ins_cost(CALL_COST);
12012 
12013   format %{ "Jmp     rethrow_stub" %}
12014   ins_encode %{
12015     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12016     cbuf.set_insts_mark();
12017     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12018   %}
12019   ins_pipe(pipe_class_call);
12020 %}
12021 
12022 // Die now.
12023 instruct ShouldNotReachHere() %{
12024   match(Halt);
12025   ins_cost(CALL_COST);
12026 
12027   format %{ "ShouldNotReachHere" %}
12028   size(4);
12029   ins_encode %{
12030     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12031     __ trap_should_not_reach_here();
12032   %}
12033   ins_pipe(pipe_class_default);
12034 %}
12035 
12036 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
12037 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12038 // Get a DEF on threadRegP, no costs, no encoding, use
12039 // 'ins_should_rematerialize(true)' to avoid spilling.
12040 instruct tlsLoadP(threadRegP dst) %{
12041   match(Set dst (ThreadLocal));
12042   ins_cost(0);
12043 
12044   ins_should_rematerialize(true);
12045 
12046   format %{ " -- \t// $dst=Thread::current(), empty" %}
12047   size(0);
12048   ins_encode( /*empty*/ );
12049   ins_pipe(pipe_class_empty);
12050 %}
12051 
12052 //---Some PPC specific nodes---------------------------------------------------
12053 
12054 // Stop a group.
12055 instruct endGroup() %{
12056   ins_cost(0);
12057 
12058   ins_is_nop(true);
12059 
12060   format %{ "End Bundle (ori r1, r1, 0)" %}
12061   size(4);
12062   ins_encode %{
12063     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12064     __ endgroup();
12065   %}
12066   ins_pipe(pipe_class_default);
12067 %}
12068 
12069 // Nop instructions
12070 
12071 instruct fxNop() %{
12072   ins_cost(0);
12073 
12074   ins_is_nop(true);
12075 
12076   format %{ "fxNop" %}
12077   size(4);
12078   ins_encode %{
12079     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12080     __ nop();
12081   %}
12082   ins_pipe(pipe_class_default);
12083 %}
12084 
12085 instruct fpNop0() %{
12086   ins_cost(0);
12087 
12088   ins_is_nop(true);
12089 
12090   format %{ "fpNop0" %}
12091   size(4);
12092   ins_encode %{
12093     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12094     __ fpnop0();
12095   %}
12096   ins_pipe(pipe_class_default);
12097 %}
12098 
12099 instruct fpNop1() %{
12100   ins_cost(0);
12101 
12102   ins_is_nop(true);
12103 
12104   format %{ "fpNop1" %}
12105   size(4);
12106   ins_encode %{
12107     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12108     __ fpnop1();
12109   %}
12110   ins_pipe(pipe_class_default);
12111 %}
12112 
12113 instruct brNop0() %{
12114   ins_cost(0);
12115   size(4);
12116   format %{ "brNop0" %}
12117   ins_encode %{
12118     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12119     __ brnop0();
12120   %}
12121   ins_is_nop(true);
12122   ins_pipe(pipe_class_default);
12123 %}
12124 
12125 instruct brNop1() %{
12126   ins_cost(0);
12127 
12128   ins_is_nop(true);
12129 
12130   format %{ "brNop1" %}
12131   size(4);
12132   ins_encode %{
12133     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12134     __ brnop1();
12135   %}
12136   ins_pipe(pipe_class_default);
12137 %}
12138 
12139 instruct brNop2() %{
12140   ins_cost(0);
12141 
12142   ins_is_nop(true);
12143 
12144   format %{ "brNop2" %}
12145   size(4);
12146   ins_encode %{
12147     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12148     __ brnop2();
12149   %}
12150   ins_pipe(pipe_class_default);
12151 %}
12152 
12153 //----------PEEPHOLE RULES-----------------------------------------------------
12154 // These must follow all instruction definitions as they use the names
12155 // defined in the instructions definitions.
12156 //
12157 // peepmatch ( root_instr_name [preceeding_instruction]* );
12158 //
12159 // peepconstraint %{
12160 // (instruction_number.operand_name relational_op instruction_number.operand_name
12161 //  [, ...] );
12162 // // instruction numbers are zero-based using left to right order in peepmatch
12163 //
12164 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12165 // // provide an instruction_number.operand_name for each operand that appears
12166 // // in the replacement instruction's match rule
12167 //
12168 // ---------VM FLAGS---------------------------------------------------------
12169 //
12170 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12171 //
12172 // Each peephole rule is given an identifying number starting with zero and
12173 // increasing by one in the order seen by the parser. An individual peephole
12174 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12175 // on the command-line.
12176 //
12177 // ---------CURRENT LIMITATIONS----------------------------------------------
12178 //
12179 // Only match adjacent instructions in same basic block
12180 // Only equality constraints
12181 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12182 // Only one replacement instruction
12183 //
12184 // ---------EXAMPLE----------------------------------------------------------
12185 //
12186 // // pertinent parts of existing instructions in architecture description
12187 // instruct movI(eRegI dst, eRegI src) %{
12188 //   match(Set dst (CopyI src));
12189 // %}
12190 //
12191 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12192 //   match(Set dst (AddI dst src));
12193 //   effect(KILL cr);
12194 // %}
12195 //
12196 // // Change (inc mov) to lea
12197 // peephole %{
12198 //   // increment preceeded by register-register move
12199 //   peepmatch ( incI_eReg movI );
12200 //   // require that the destination register of the increment
12201 //   // match the destination register of the move
12202 //   peepconstraint ( 0.dst == 1.dst );
12203 //   // construct a replacement instruction that sets
12204 //   // the destination to ( move's source register + one )
12205 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12206 // %}
12207 //
12208 // Implementation no longer uses movX instructions since
12209 // machine-independent system no longer uses CopyX nodes.
12210 //
12211 // peephole %{
12212 //   peepmatch ( incI_eReg movI );
12213 //   peepconstraint ( 0.dst == 1.dst );
12214 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12215 // %}
12216 //
12217 // peephole %{
12218 //   peepmatch ( decI_eReg movI );
12219 //   peepconstraint ( 0.dst == 1.dst );
12220 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12221 // %}
12222 //
12223 // peephole %{
12224 //   peepmatch ( addI_eReg_imm movI );
12225 //   peepconstraint ( 0.dst == 1.dst );
12226 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12227 // %}
12228 //
12229 // peephole %{
12230 //   peepmatch ( addP_eReg_imm movP );
12231 //   peepconstraint ( 0.dst == 1.dst );
12232 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12233 // %}
12234 
12235 // // Change load of spilled value to only a spill
12236 // instruct storeI(memory mem, eRegI src) %{
12237 //   match(Set mem (StoreI mem src));
12238 // %}
12239 //
12240 // instruct loadI(eRegI dst, memory mem) %{
12241 //   match(Set dst (LoadI mem));
12242 // %}
12243 //
12244 peephole %{
12245   peepmatch ( loadI storeI );
12246   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12247   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12248 %}
12249 
12250 peephole %{
12251   peepmatch ( loadL storeL );
12252   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12253   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12254 %}
12255 
12256 peephole %{
12257   peepmatch ( loadP storeP );
12258   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12259   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12260 %}
12261 
12262 //----------SMARTSPILL RULES---------------------------------------------------
12263 // These must follow all instruction definitions as they use the names
12264 // defined in the instructions definitions.
--- EOF ---