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src/hotspot/cpu/x86/assembler_x86.cpp

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7758   int src_enc = src->encoding();
7759   if (UseAVX > 0) {
7760     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7761     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7762   } else {
7763     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7764     return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7765   }
7766 }
7767 
7768 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7769   assert(VM_Version::supports_avx(), "");
7770   assert(!VM_Version::supports_evex(), "");
7771   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7772   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7773   emit_int8((unsigned char)0xC2);
7774   emit_int8((unsigned char)(0xC0 | encode));
7775   emit_int8((unsigned char)(0xF & cop));
7776 }
7777 


































7778 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7779   assert(VM_Version::supports_avx(), "");
7780   assert(!VM_Version::supports_evex(), "");
7781   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7782   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7783   emit_int8((unsigned char)0x4B);
7784   emit_int8((unsigned char)(0xC0 | encode));
7785   int src2_enc = src2->encoding();
7786   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7787 }
7788 
7789 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7790   assert(VM_Version::supports_avx(), "");
7791   assert(!VM_Version::supports_evex(), "");
7792   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7793   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7794   emit_int8((unsigned char)0xC2);
7795   emit_int8((unsigned char)(0xC0 | encode));
7796   emit_int8((unsigned char)(0xF & cop));
7797 }






7758   int src_enc = src->encoding();
7759   if (UseAVX > 0) {
7760     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7761     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7762   } else {
7763     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7764     return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7765   }
7766 }
7767 
7768 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7769   assert(VM_Version::supports_avx(), "");
7770   assert(!VM_Version::supports_evex(), "");
7771   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7772   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7773   emit_int8((unsigned char)0xC2);
7774   emit_int8((unsigned char)(0xC0 | encode));
7775   emit_int8((unsigned char)(0xF & cop));
7776 }
7777 
7778 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7779   assert(VM_Version::supports_avx(), "");
7780   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7781   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7782   emit_int8(0x5F);
7783   emit_int8((unsigned char)(0xC0 | encode));
7784 }
7785 
7786 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7787   assert(VM_Version::supports_avx(), "");
7788   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7789   attributes.set_rex_vex_w_reverted();
7790   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7791   emit_int8(0x5F);
7792   emit_int8((unsigned char)(0xC0 | encode));
7793 }
7794 
7795 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7796   assert(VM_Version::supports_avx(), "");
7797   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7798   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7799   emit_int8(0x5D);
7800   emit_int8((unsigned char)(0xC0 | encode));
7801 }
7802 
7803 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7804   assert(VM_Version::supports_avx(), "");
7805   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7806   attributes.set_rex_vex_w_reverted();
7807   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7808   emit_int8(0x5D);
7809   emit_int8((unsigned char)(0xC0 | encode));
7810 }
7811 
7812 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7813   assert(VM_Version::supports_avx(), "");
7814   assert(!VM_Version::supports_evex(), "");
7815   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7816   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7817   emit_int8((unsigned char)0x4B);
7818   emit_int8((unsigned char)(0xC0 | encode));
7819   int src2_enc = src2->encoding();
7820   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7821 }
7822 
7823 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7824   assert(VM_Version::supports_avx(), "");
7825   assert(!VM_Version::supports_evex(), "");
7826   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7827   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7828   emit_int8((unsigned char)0xC2);
7829   emit_int8((unsigned char)(0xC0 | encode));
7830   emit_int8((unsigned char)(0xF & cop));
7831 }







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