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src/hotspot/cpu/x86/x86_64.ad
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@@ -3661,10 +3661,20 @@
format %{ %}
interface(REG_INTER);
%}
+
+// Float register operands
+operand legRegF() %{
+ constraint(ALLOC_IN_RC(float_reg_legacy));
+ match(RegF);
+
+ format %{ %}
+ interface(REG_INTER);
+%}
+
// Float register operands
operand vlRegF() %{
constraint(ALLOC_IN_RC(float_reg_vl));
match(RegF);
@@ -3680,10 +3690,19 @@
format %{ %}
interface(REG_INTER);
%}
// Double register operands
+operand legRegD() %{
+ constraint(ALLOC_IN_RC(double_reg_legacy));
+ match(RegD);
+
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+// Double register operands
operand vlRegD() %{
constraint(ALLOC_IN_RC(double_reg_vl));
match(RegD);
format %{ %}
@@ -5407,10 +5426,11 @@
__ movflt($dst$$XMMRegister, $mem$$Address);
%}
ins_pipe(pipe_slow); // XXX
%}
+
// Load Float
instruct MoveF2VL(vlRegF dst, regF src) %{
match(Set dst src);
format %{ "movss $dst,$src\t! load float (4 bytes)" %}
ins_encode %{
@@ -5418,19 +5438,39 @@
%}
ins_pipe( fpu_reg_reg );
%}
// Load Float
+instruct MoveF2LEG(legRegF dst, regF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t! load float (4 bytes)" %}
+ ins_encode %{
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Float
instruct MoveVL2F(regF dst, vlRegF src) %{
match(Set dst src);
format %{ "movss $dst,$src\t! load float (4 bytes)" %}
ins_encode %{
__ movflt($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe( fpu_reg_reg );
%}
+// Load Float
+instruct MoveLEG2F(regF dst, legRegF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t! load float (4 bytes)" %}
+ ins_encode %{
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
// Load Double
instruct loadD_partial(regD dst, memory mem)
%{
predicate(!UseXmmLoadAndClearUpper);
match(Set dst (LoadD mem));
@@ -5441,10 +5481,11 @@
__ movdbl($dst$$XMMRegister, $mem$$Address);
%}
ins_pipe(pipe_slow); // XXX
%}
+
instruct loadD(regD dst, memory mem)
%{
predicate(UseXmmLoadAndClearUpper);
match(Set dst (LoadD mem));
@@ -5465,16 +5506,36 @@
%}
ins_pipe( fpu_reg_reg );
%}
// Load Double
+instruct MoveD2LEG(legRegD dst, regD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
+ ins_encode %{
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Double
instruct MoveVL2D(regD dst, vlRegD src) %{
match(Set dst src);
format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
ins_encode %{
__ movdbl($dst$$XMMRegister, $src$$XMMRegister);
%}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Double
+instruct MoveLEG2D(regD dst, legRegD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
+ ins_encode %{
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ %}
ins_pipe( fpu_reg_reg );
%}
// Load Effective Address
instruct leaP8(rRegP dst, indOffset8 mem)
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