1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "runtime/vm_version.hpp"
  36 #include "utilities/virtualizationSupport.hpp"
  37 
  38 #include OS_HEADER_INLINE(os)
  39 
  40 int VM_Version::_cpu;
  41 int VM_Version::_model;
  42 int VM_Version::_stepping;
  43 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  44 
  45 // Address of instruction which causes SEGV
  46 address VM_Version::_cpuinfo_segv_addr = 0;
  47 // Address of instruction after the one which causes SEGV
  48 address VM_Version::_cpuinfo_cont_addr = 0;
  49 
  50 static BufferBlob* stub_blob;
  51 static const int stub_size = 1100;
  52 
  53 extern "C" {
  54   typedef void (*get_cpu_info_stub_t)(void*);
  55 }
  56 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  57 
  58 
  59 class VM_Version_StubGenerator: public StubCodeGenerator {
  60  public:
  61 
  62   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  63 
  64   address generate_get_cpu_info() {
  65     // Flags to test CPU type.
  66     const uint32_t HS_EFL_AC = 0x40000;
  67     const uint32_t HS_EFL_ID = 0x200000;
  68     // Values for when we don't have a CPUID instruction.
  69     const int      CPU_FAMILY_SHIFT = 8;
  70     const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
  71     const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
  72     bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
  73 
  74     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  75     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
  76     Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
  77 
  78     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
  79 #   define __ _masm->
  80 
  81     address start = __ pc();
  82 
  83     //
  84     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
  85     //
  86     // LP64: rcx and rdx are first and second argument registers on windows
  87 
  88     __ push(rbp);
  89 #ifdef _LP64
  90     __ mov(rbp, c_rarg0); // cpuid_info address
  91 #else
  92     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  93 #endif
  94     __ push(rbx);
  95     __ push(rsi);
  96     __ pushf();          // preserve rbx, and flags
  97     __ pop(rax);
  98     __ push(rax);
  99     __ mov(rcx, rax);
 100     //
 101     // if we are unable to change the AC flag, we have a 386
 102     //
 103     __ xorl(rax, HS_EFL_AC);
 104     __ push(rax);
 105     __ popf();
 106     __ pushf();
 107     __ pop(rax);
 108     __ cmpptr(rax, rcx);
 109     __ jccb(Assembler::notEqual, detect_486);
 110 
 111     __ movl(rax, CPU_FAMILY_386);
 112     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 113     __ jmp(done);
 114 
 115     //
 116     // If we are unable to change the ID flag, we have a 486 which does
 117     // not support the "cpuid" instruction.
 118     //
 119     __ bind(detect_486);
 120     __ mov(rax, rcx);
 121     __ xorl(rax, HS_EFL_ID);
 122     __ push(rax);
 123     __ popf();
 124     __ pushf();
 125     __ pop(rax);
 126     __ cmpptr(rcx, rax);
 127     __ jccb(Assembler::notEqual, detect_586);
 128 
 129     __ bind(cpu486);
 130     __ movl(rax, CPU_FAMILY_486);
 131     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 132     __ jmp(done);
 133 
 134     //
 135     // At this point, we have a chip which supports the "cpuid" instruction
 136     //
 137     __ bind(detect_586);
 138     __ xorl(rax, rax);
 139     __ cpuid();
 140     __ orl(rax, rax);
 141     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 142                                         // value of at least 1, we give up and
 143                                         // assume a 486
 144     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 145     __ movl(Address(rsi, 0), rax);
 146     __ movl(Address(rsi, 4), rbx);
 147     __ movl(Address(rsi, 8), rcx);
 148     __ movl(Address(rsi,12), rdx);
 149 
 150     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 151     __ jccb(Assembler::belowEqual, std_cpuid4);
 152 
 153     //
 154     // cpuid(0xB) Processor Topology
 155     //
 156     __ movl(rax, 0xb);
 157     __ xorl(rcx, rcx);   // Threads level
 158     __ cpuid();
 159 
 160     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 161     __ movl(Address(rsi, 0), rax);
 162     __ movl(Address(rsi, 4), rbx);
 163     __ movl(Address(rsi, 8), rcx);
 164     __ movl(Address(rsi,12), rdx);
 165 
 166     __ movl(rax, 0xb);
 167     __ movl(rcx, 1);     // Cores level
 168     __ cpuid();
 169     __ push(rax);
 170     __ andl(rax, 0x1f);  // Determine if valid topology level
 171     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 172     __ andl(rax, 0xffff);
 173     __ pop(rax);
 174     __ jccb(Assembler::equal, std_cpuid4);
 175 
 176     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 177     __ movl(Address(rsi, 0), rax);
 178     __ movl(Address(rsi, 4), rbx);
 179     __ movl(Address(rsi, 8), rcx);
 180     __ movl(Address(rsi,12), rdx);
 181 
 182     __ movl(rax, 0xb);
 183     __ movl(rcx, 2);     // Packages level
 184     __ cpuid();
 185     __ push(rax);
 186     __ andl(rax, 0x1f);  // Determine if valid topology level
 187     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 188     __ andl(rax, 0xffff);
 189     __ pop(rax);
 190     __ jccb(Assembler::equal, std_cpuid4);
 191 
 192     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 193     __ movl(Address(rsi, 0), rax);
 194     __ movl(Address(rsi, 4), rbx);
 195     __ movl(Address(rsi, 8), rcx);
 196     __ movl(Address(rsi,12), rdx);
 197 
 198     //
 199     // cpuid(0x4) Deterministic cache params
 200     //
 201     __ bind(std_cpuid4);
 202     __ movl(rax, 4);
 203     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 204     __ jccb(Assembler::greater, std_cpuid1);
 205 
 206     __ xorl(rcx, rcx);   // L1 cache
 207     __ cpuid();
 208     __ push(rax);
 209     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 210     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 211     __ pop(rax);
 212     __ jccb(Assembler::equal, std_cpuid1);
 213 
 214     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 215     __ movl(Address(rsi, 0), rax);
 216     __ movl(Address(rsi, 4), rbx);
 217     __ movl(Address(rsi, 8), rcx);
 218     __ movl(Address(rsi,12), rdx);
 219 
 220     //
 221     // Standard cpuid(0x1)
 222     //
 223     __ bind(std_cpuid1);
 224     __ movl(rax, 1);
 225     __ cpuid();
 226     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 227     __ movl(Address(rsi, 0), rax);
 228     __ movl(Address(rsi, 4), rbx);
 229     __ movl(Address(rsi, 8), rcx);
 230     __ movl(Address(rsi,12), rdx);
 231 
 232     //
 233     // Check if OS has enabled XGETBV instruction to access XCR0
 234     // (OSXSAVE feature flag) and CPU supports AVX
 235     //
 236     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 237     __ cmpl(rcx, 0x18000000);
 238     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 239 
 240     //
 241     // XCR0, XFEATURE_ENABLED_MASK register
 242     //
 243     __ xorl(rcx, rcx);   // zero for XCR0 register
 244     __ xgetbv();
 245     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 246     __ movl(Address(rsi, 0), rax);
 247     __ movl(Address(rsi, 4), rdx);
 248 
 249     //
 250     // cpuid(0x7) Structured Extended Features
 251     //
 252     __ bind(sef_cpuid);
 253     __ movl(rax, 7);
 254     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 255     __ jccb(Assembler::greater, ext_cpuid);
 256 
 257     __ xorl(rcx, rcx);
 258     __ cpuid();
 259     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 260     __ movl(Address(rsi, 0), rax);
 261     __ movl(Address(rsi, 4), rbx);
 262     __ movl(Address(rsi, 8), rcx);
 263     __ movl(Address(rsi, 12), rdx);
 264 
 265     //
 266     // Extended cpuid(0x80000000)
 267     //
 268     __ bind(ext_cpuid);
 269     __ movl(rax, 0x80000000);
 270     __ cpuid();
 271     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 272     __ jcc(Assembler::belowEqual, done);
 273     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 274     __ jcc(Assembler::belowEqual, ext_cpuid1);
 275     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 276     __ jccb(Assembler::belowEqual, ext_cpuid5);
 277     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 278     __ jccb(Assembler::belowEqual, ext_cpuid7);
 279     __ cmpl(rax, 0x80000008);     // Is cpuid(0x80000009 and above) supported?
 280     __ jccb(Assembler::belowEqual, ext_cpuid8);
 281     __ cmpl(rax, 0x8000001E);     // Is cpuid(0x8000001E) supported?
 282     __ jccb(Assembler::below, ext_cpuid8);
 283     //
 284     // Extended cpuid(0x8000001E)
 285     //
 286     __ movl(rax, 0x8000001E);
 287     __ cpuid();
 288     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
 289     __ movl(Address(rsi, 0), rax);
 290     __ movl(Address(rsi, 4), rbx);
 291     __ movl(Address(rsi, 8), rcx);
 292     __ movl(Address(rsi,12), rdx);
 293 
 294     //
 295     // Extended cpuid(0x80000008)
 296     //
 297     __ bind(ext_cpuid8);
 298     __ movl(rax, 0x80000008);
 299     __ cpuid();
 300     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 301     __ movl(Address(rsi, 0), rax);
 302     __ movl(Address(rsi, 4), rbx);
 303     __ movl(Address(rsi, 8), rcx);
 304     __ movl(Address(rsi,12), rdx);
 305 
 306     //
 307     // Extended cpuid(0x80000007)
 308     //
 309     __ bind(ext_cpuid7);
 310     __ movl(rax, 0x80000007);
 311     __ cpuid();
 312     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 313     __ movl(Address(rsi, 0), rax);
 314     __ movl(Address(rsi, 4), rbx);
 315     __ movl(Address(rsi, 8), rcx);
 316     __ movl(Address(rsi,12), rdx);
 317 
 318     //
 319     // Extended cpuid(0x80000005)
 320     //
 321     __ bind(ext_cpuid5);
 322     __ movl(rax, 0x80000005);
 323     __ cpuid();
 324     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 325     __ movl(Address(rsi, 0), rax);
 326     __ movl(Address(rsi, 4), rbx);
 327     __ movl(Address(rsi, 8), rcx);
 328     __ movl(Address(rsi,12), rdx);
 329 
 330     //
 331     // Extended cpuid(0x80000001)
 332     //
 333     __ bind(ext_cpuid1);
 334     __ movl(rax, 0x80000001);
 335     __ cpuid();
 336     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 337     __ movl(Address(rsi, 0), rax);
 338     __ movl(Address(rsi, 4), rbx);
 339     __ movl(Address(rsi, 8), rcx);
 340     __ movl(Address(rsi,12), rdx);
 341 
 342     //
 343     // Check if OS has enabled XGETBV instruction to access XCR0
 344     // (OSXSAVE feature flag) and CPU supports AVX
 345     //
 346     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 347     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 348     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
 349     __ cmpl(rcx, 0x18000000);
 350     __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
 351 
 352     __ movl(rax, 0x6);
 353     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 354     __ cmpl(rax, 0x6);
 355     __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
 356 
 357     // we need to bridge farther than imm8, so we use this island as a thunk
 358     __ bind(done);
 359     __ jmp(wrapup);
 360 
 361     __ bind(start_simd_check);
 362     //
 363     // Some OSs have a bug when upper 128/256bits of YMM/ZMM
 364     // registers are not restored after a signal processing.
 365     // Generate SEGV here (reference through NULL)
 366     // and check upper YMM/ZMM bits after it.
 367     //
 368     intx saved_useavx = UseAVX;
 369     intx saved_usesse = UseSSE;
 370 
 371     // If UseAVX is unitialized or is set by the user to include EVEX
 372     if (use_evex) {
 373       // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 374       __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 375       __ movl(rax, 0x10000);
 376       __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
 377       __ cmpl(rax, 0x10000);
 378       __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 379       // check _cpuid_info.xem_xcr0_eax.bits.opmask
 380       // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 381       // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 382       __ movl(rax, 0xE0);
 383       __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 384       __ cmpl(rax, 0xE0);
 385       __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 386 
 387       if (FLAG_IS_DEFAULT(UseAVX)) {
 388         __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 389         __ movl(rax, Address(rsi, 0));
 390         __ cmpl(rax, 0x50654);              // If it is Skylake
 391         __ jcc(Assembler::equal, legacy_setup);
 392       }
 393       // EVEX setup: run in lowest evex mode
 394       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 395       UseAVX = 3;
 396       UseSSE = 2;
 397 #ifdef _WINDOWS
 398       // xmm5-xmm15 are not preserved by caller on windows
 399       // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
 400       __ subptr(rsp, 64);
 401       __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
 402 #ifdef _LP64
 403       __ subptr(rsp, 64);
 404       __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
 405       __ subptr(rsp, 64);
 406       __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
 407 #endif // _LP64
 408 #endif // _WINDOWS
 409 
 410       // load value into all 64 bytes of zmm7 register
 411       __ movl(rcx, VM_Version::ymm_test_value());
 412       __ movdl(xmm0, rcx);
 413       __ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
 414       __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
 415 #ifdef _LP64
 416       __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
 417       __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
 418 #endif
 419       VM_Version::clean_cpuFeatures();
 420       __ jmp(save_restore_except);
 421     }
 422 
 423     __ bind(legacy_setup);
 424     // AVX setup
 425     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 426     UseAVX = 1;
 427     UseSSE = 2;
 428 #ifdef _WINDOWS
 429     __ subptr(rsp, 32);
 430     __ vmovdqu(Address(rsp, 0), xmm7);
 431 #ifdef _LP64
 432     __ subptr(rsp, 32);
 433     __ vmovdqu(Address(rsp, 0), xmm8);
 434     __ subptr(rsp, 32);
 435     __ vmovdqu(Address(rsp, 0), xmm15);
 436 #endif // _LP64
 437 #endif // _WINDOWS
 438 
 439     // load value into all 32 bytes of ymm7 register
 440     __ movl(rcx, VM_Version::ymm_test_value());
 441 
 442     __ movdl(xmm0, rcx);
 443     __ pshufd(xmm0, xmm0, 0x00);
 444     __ vinsertf128_high(xmm0, xmm0);
 445     __ vmovdqu(xmm7, xmm0);
 446 #ifdef _LP64
 447     __ vmovdqu(xmm8, xmm0);
 448     __ vmovdqu(xmm15, xmm0);
 449 #endif
 450     VM_Version::clean_cpuFeatures();
 451 
 452     __ bind(save_restore_except);
 453     __ xorl(rsi, rsi);
 454     VM_Version::set_cpuinfo_segv_addr(__ pc());
 455     // Generate SEGV
 456     __ movl(rax, Address(rsi, 0));
 457 
 458     VM_Version::set_cpuinfo_cont_addr(__ pc());
 459     // Returns here after signal. Save xmm0 to check it later.
 460 
 461     // If UseAVX is unitialized or is set by the user to include EVEX
 462     if (use_evex) {
 463       // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 464       __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 465       __ movl(rax, 0x10000);
 466       __ andl(rax, Address(rsi, 4));
 467       __ cmpl(rax, 0x10000);
 468       __ jcc(Assembler::notEqual, legacy_save_restore);
 469       // check _cpuid_info.xem_xcr0_eax.bits.opmask
 470       // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 471       // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 472       __ movl(rax, 0xE0);
 473       __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 474       __ cmpl(rax, 0xE0);
 475       __ jcc(Assembler::notEqual, legacy_save_restore);
 476 
 477       if (FLAG_IS_DEFAULT(UseAVX)) {
 478         __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 479         __ movl(rax, Address(rsi, 0));
 480         __ cmpl(rax, 0x50654);              // If it is Skylake
 481         __ jcc(Assembler::equal, legacy_save_restore);
 482       }
 483       // EVEX check: run in lowest evex mode
 484       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 485       UseAVX = 3;
 486       UseSSE = 2;
 487       __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
 488       __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
 489       __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
 490 #ifdef _LP64
 491       __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
 492       __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
 493 #endif
 494 
 495 #ifdef _WINDOWS
 496 #ifdef _LP64
 497       __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
 498       __ addptr(rsp, 64);
 499       __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
 500       __ addptr(rsp, 64);
 501 #endif // _LP64
 502       __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
 503       __ addptr(rsp, 64);
 504 #endif // _WINDOWS
 505       generate_vzeroupper(wrapup);
 506       VM_Version::clean_cpuFeatures();
 507       UseAVX = saved_useavx;
 508       UseSSE = saved_usesse;
 509       __ jmp(wrapup);
 510    }
 511 
 512     __ bind(legacy_save_restore);
 513     // AVX check
 514     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 515     UseAVX = 1;
 516     UseSSE = 2;
 517     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 518     __ vmovdqu(Address(rsi, 0), xmm0);
 519     __ vmovdqu(Address(rsi, 32), xmm7);
 520 #ifdef _LP64
 521     __ vmovdqu(Address(rsi, 64), xmm8);
 522     __ vmovdqu(Address(rsi, 96), xmm15);
 523 #endif
 524 
 525 #ifdef _WINDOWS
 526 #ifdef _LP64
 527     __ vmovdqu(xmm15, Address(rsp, 0));
 528     __ addptr(rsp, 32);
 529     __ vmovdqu(xmm8, Address(rsp, 0));
 530     __ addptr(rsp, 32);
 531 #endif // _LP64
 532     __ vmovdqu(xmm7, Address(rsp, 0));
 533     __ addptr(rsp, 32);
 534 #endif // _WINDOWS
 535     generate_vzeroupper(wrapup);
 536     VM_Version::clean_cpuFeatures();
 537     UseAVX = saved_useavx;
 538     UseSSE = saved_usesse;
 539 
 540     __ bind(wrapup);
 541     __ popf();
 542     __ pop(rsi);
 543     __ pop(rbx);
 544     __ pop(rbp);
 545     __ ret(0);
 546 
 547 #   undef __
 548 
 549     return start;
 550   };
 551   void generate_vzeroupper(Label& L_wrapup) {
 552 #   define __ _masm->
 553     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 554     __ cmpl(Address(rsi, 4), 0x756e6547);  // 'uneG'
 555     __ jcc(Assembler::notEqual, L_wrapup);
 556     __ movl(rcx, 0x0FFF0FF0);
 557     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 558     __ andl(rcx, Address(rsi, 0));
 559     __ cmpl(rcx, 0x00050670);              // If it is Xeon Phi 3200/5200/7200
 560     __ jcc(Assembler::equal, L_wrapup);
 561     __ cmpl(rcx, 0x00080650);              // If it is Future Xeon Phi
 562     __ jcc(Assembler::equal, L_wrapup);
 563     __ vzeroupper();
 564 #   undef __
 565   }
 566 };
 567 
 568 void VM_Version::get_processor_features() {
 569 
 570   _cpu = 4; // 486 by default
 571   _model = 0;
 572   _stepping = 0;
 573   _features = 0;
 574   _logical_processors_per_package = 1;
 575   // i486 internal cache is both I&D and has a 16-byte line size
 576   _L1_data_cache_line_size = 16;
 577 
 578   // Get raw processor info
 579 
 580   get_cpu_info_stub(&_cpuid_info);
 581 
 582   assert_is_initialized();
 583   _cpu = extended_cpu_family();
 584   _model = extended_cpu_model();
 585   _stepping = cpu_stepping();
 586 
 587   if (cpu_family() > 4) { // it supports CPUID
 588     _features = feature_flags();
 589     // Logical processors are only available on P4s and above,
 590     // and only if hyperthreading is available.
 591     _logical_processors_per_package = logical_processor_count();
 592     _L1_data_cache_line_size = L1_line_size();
 593   }
 594 
 595   _supports_cx8 = supports_cmpxchg8();
 596   // xchg and xadd instructions
 597   _supports_atomic_getset4 = true;
 598   _supports_atomic_getadd4 = true;
 599   LP64_ONLY(_supports_atomic_getset8 = true);
 600   LP64_ONLY(_supports_atomic_getadd8 = true);
 601 
 602 #ifdef _LP64
 603   // OS should support SSE for x64 and hardware should support at least SSE2.
 604   if (!VM_Version::supports_sse2()) {
 605     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 606   }
 607   // in 64 bit the use of SSE2 is the minimum
 608   if (UseSSE < 2) UseSSE = 2;
 609 #endif
 610 
 611 #ifdef AMD64
 612   // flush_icache_stub have to be generated first.
 613   // That is why Icache line size is hard coded in ICache class,
 614   // see icache_x86.hpp. It is also the reason why we can't use
 615   // clflush instruction in 32-bit VM since it could be running
 616   // on CPU which does not support it.
 617   //
 618   // The only thing we can do is to verify that flushed
 619   // ICache::line_size has correct value.
 620   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 621   // clflush_size is size in quadwords (8 bytes).
 622   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 623 #endif
 624 
 625 #ifdef _LP64
 626   // assigning this field effectively enables Unsafe.writebackMemory()
 627   // by initing UnsafeConstant.DATA_CACHE_LINE_FLUSH_SIZE to non-zero
 628   // that is only implemented on x86_64 and only if the OS plays ball
 629   if (os::supports_map_sync()) {
 630     // publish data cache line flush size to generic field, otherwise
 631     // let if default to zero thereby disabling writeback
 632     _data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
 633   }
 634 #endif
 635   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 636   if (!os::supports_sse())
 637     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 638 
 639   if (UseSSE < 4) {
 640     _features &= ~CPU_SSE4_1;
 641     _features &= ~CPU_SSE4_2;
 642   }
 643 
 644   if (UseSSE < 3) {
 645     _features &= ~CPU_SSE3;
 646     _features &= ~CPU_SSSE3;
 647     _features &= ~CPU_SSE4A;
 648   }
 649 
 650   if (UseSSE < 2)
 651     _features &= ~CPU_SSE2;
 652 
 653   if (UseSSE < 1)
 654     _features &= ~CPU_SSE;
 655 
 656   //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
 657   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
 658     UseAVX = 0;
 659   }
 660 
 661   // first try initial setting and detect what we can support
 662   int use_avx_limit = 0;
 663   if (UseAVX > 0) {
 664     if (UseAVX > 2 && supports_evex()) {
 665       use_avx_limit = 3;
 666     } else if (UseAVX > 1 && supports_avx2()) {
 667       use_avx_limit = 2;
 668     } else if (UseAVX > 0 && supports_avx()) {
 669       use_avx_limit = 1;
 670     } else {
 671       use_avx_limit = 0;
 672     }
 673   }
 674   if (FLAG_IS_DEFAULT(UseAVX)) {
 675     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 676     if (is_intel_family_core() && _model == CPU_MODEL_SKYLAKE && _stepping < 5) {
 677       FLAG_SET_DEFAULT(UseAVX, 2);  //Set UseAVX=2 for Skylake
 678     }
 679   } else if (UseAVX > use_avx_limit) {
 680     warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
 681     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 682   } else if (UseAVX < 0) {
 683     warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
 684     FLAG_SET_DEFAULT(UseAVX, 0);
 685   }
 686 
 687   if (UseAVX < 3) {
 688     _features &= ~CPU_AVX512F;
 689     _features &= ~CPU_AVX512DQ;
 690     _features &= ~CPU_AVX512CD;
 691     _features &= ~CPU_AVX512BW;
 692     _features &= ~CPU_AVX512VL;
 693     _features &= ~CPU_AVX512_VPOPCNTDQ;
 694     _features &= ~CPU_AVX512_VPCLMULQDQ;
 695     _features &= ~CPU_VAES;
 696     _features &= ~CPU_VNNI;
 697   }
 698 
 699   if (UseAVX < 2)
 700     _features &= ~CPU_AVX2;
 701 
 702   if (UseAVX < 1) {
 703     _features &= ~CPU_AVX;
 704     _features &= ~CPU_VZEROUPPER;
 705   }
 706 
 707   if (logical_processors_per_package() == 1) {
 708     // HT processor could be installed on a system which doesn't support HT.
 709     _features &= ~CPU_HT;
 710   }
 711 
 712   if (is_intel()) { // Intel cpus specific settings
 713     if (is_knights_family()) {
 714       _features &= ~CPU_VZEROUPPER;
 715     }
 716   }
 717 
 718   char buf[256];
 719   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 720                cores_per_cpu(), threads_per_core(),
 721                cpu_family(), _model, _stepping,
 722                (supports_cmov() ? ", cmov" : ""),
 723                (supports_cmpxchg8() ? ", cx8" : ""),
 724                (supports_fxsr() ? ", fxsr" : ""),
 725                (supports_mmx()  ? ", mmx"  : ""),
 726                (supports_sse()  ? ", sse"  : ""),
 727                (supports_sse2() ? ", sse2" : ""),
 728                (supports_sse3() ? ", sse3" : ""),
 729                (supports_ssse3()? ", ssse3": ""),
 730                (supports_sse4_1() ? ", sse4.1" : ""),
 731                (supports_sse4_2() ? ", sse4.2" : ""),
 732                (supports_popcnt() ? ", popcnt" : ""),
 733                (supports_avx()    ? ", avx" : ""),
 734                (supports_avx2()   ? ", avx2" : ""),
 735                (supports_aes()    ? ", aes" : ""),
 736                (supports_clmul()  ? ", clmul" : ""),
 737                (supports_erms()   ? ", erms" : ""),
 738                (supports_rtm()    ? ", rtm" : ""),
 739                (supports_mmx_ext() ? ", mmxext" : ""),
 740                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 741                (supports_lzcnt()   ? ", lzcnt": ""),
 742                (supports_sse4a()   ? ", sse4a": ""),
 743                (supports_ht() ? ", ht": ""),
 744                (supports_tsc() ? ", tsc": ""),
 745                (supports_tscinv_bit() ? ", tscinvbit": ""),
 746                (supports_tscinv() ? ", tscinv": ""),
 747                (supports_bmi1() ? ", bmi1" : ""),
 748                (supports_bmi2() ? ", bmi2" : ""),
 749                (supports_adx() ? ", adx" : ""),
 750                (supports_evex() ? ", evex" : ""),
 751                (supports_sha() ? ", sha" : ""),
 752                (supports_fma() ? ", fma" : ""));
 753   _features_string = os::strdup(buf);
 754 
 755   // UseSSE is set to the smaller of what hardware supports and what
 756   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 757   // older Pentiums which do not support it.
 758   int use_sse_limit = 0;
 759   if (UseSSE > 0) {
 760     if (UseSSE > 3 && supports_sse4_1()) {
 761       use_sse_limit = 4;
 762     } else if (UseSSE > 2 && supports_sse3()) {
 763       use_sse_limit = 3;
 764     } else if (UseSSE > 1 && supports_sse2()) {
 765       use_sse_limit = 2;
 766     } else if (UseSSE > 0 && supports_sse()) {
 767       use_sse_limit = 1;
 768     } else {
 769       use_sse_limit = 0;
 770     }
 771   }
 772   if (FLAG_IS_DEFAULT(UseSSE)) {
 773     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 774   } else if (UseSSE > use_sse_limit) {
 775     warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
 776     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 777   } else if (UseSSE < 0) {
 778     warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
 779     FLAG_SET_DEFAULT(UseSSE, 0);
 780   }
 781 
 782   // Use AES instructions if available.
 783   if (supports_aes()) {
 784     if (FLAG_IS_DEFAULT(UseAES)) {
 785       FLAG_SET_DEFAULT(UseAES, true);
 786     }
 787     if (!UseAES) {
 788       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 789         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 790       }
 791       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 792     } else {
 793       if (UseSSE > 2) {
 794         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 795           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 796         }
 797       } else {
 798         // The AES intrinsic stubs require AES instruction support (of course)
 799         // but also require sse3 mode or higher for instructions it use.
 800         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 801           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 802         }
 803         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 804       }
 805 
 806       // --AES-CTR begins--
 807       if (!UseAESIntrinsics) {
 808         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 809           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
 810           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 811         }
 812       } else {
 813         if (supports_sse4_1()) {
 814           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 815             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
 816           }
 817         } else {
 818            // The AES-CTR intrinsic stubs require AES instruction support (of course)
 819            // but also require sse4.1 mode or higher for instructions it use.
 820           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 821              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
 822            }
 823            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 824         }
 825       }
 826       // --AES-CTR ends--
 827     }
 828   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
 829     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 830       warning("AES instructions are not available on this CPU");
 831       FLAG_SET_DEFAULT(UseAES, false);
 832     }
 833     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 834       warning("AES intrinsics are not available on this CPU");
 835       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 836     }
 837     if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 838       warning("AES-CTR intrinsics are not available on this CPU");
 839       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 840     }
 841   }
 842 
 843   // Use CLMUL instructions if available.
 844   if (supports_clmul()) {
 845     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 846       UseCLMUL = true;
 847     }
 848   } else if (UseCLMUL) {
 849     if (!FLAG_IS_DEFAULT(UseCLMUL))
 850       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 851     FLAG_SET_DEFAULT(UseCLMUL, false);
 852   }
 853 
 854   if (UseCLMUL && (UseSSE > 2)) {
 855     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 856       UseCRC32Intrinsics = true;
 857     }
 858   } else if (UseCRC32Intrinsics) {
 859     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 860       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
 861     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 862   }
 863 
 864   if (supports_sse4_2() && supports_clmul()) {
 865     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 866       UseCRC32CIntrinsics = true;
 867     }
 868   } else if (UseCRC32CIntrinsics) {
 869     if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 870       warning("CRC32C intrinsics are not available on this CPU");
 871     }
 872     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 873   }
 874 
 875   // GHASH/GCM intrinsics
 876   if (UseCLMUL && (UseSSE > 2)) {
 877     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 878       UseGHASHIntrinsics = true;
 879     }
 880   } else if (UseGHASHIntrinsics) {
 881     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 882       warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
 883     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 884   }
 885 
 886   // Base64 Intrinsics (Check the condition for which the intrinsic will be active)
 887   if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) {
 888     if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
 889       UseBASE64Intrinsics = true;
 890     }
 891   } else if (UseBASE64Intrinsics) {
 892      if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
 893       warning("Base64 intrinsic requires EVEX instructions on this CPU");
 894     FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
 895   }
 896 
 897   if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
 898     if (FLAG_IS_DEFAULT(UseFMA)) {
 899       UseFMA = true;
 900     }
 901   } else if (UseFMA) {
 902     warning("FMA instructions are not available on this CPU");
 903     FLAG_SET_DEFAULT(UseFMA, false);
 904   }
 905 
 906   if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
 907     if (FLAG_IS_DEFAULT(UseSHA)) {
 908       UseSHA = true;
 909     }
 910   } else if (UseSHA) {
 911     warning("SHA instructions are not available on this CPU");
 912     FLAG_SET_DEFAULT(UseSHA, false);
 913   }
 914 
 915   if (supports_sha() && supports_sse4_1() && UseSHA) {
 916     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 917       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 918     }
 919   } else if (UseSHA1Intrinsics) {
 920     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 921     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 922   }
 923 
 924   if (supports_sse4_1() && UseSHA) {
 925     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 926       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 927     }
 928   } else if (UseSHA256Intrinsics) {
 929     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 930     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 931   }
 932 
 933 #ifdef _LP64
 934   // These are only supported on 64-bit
 935   if (UseSHA && supports_avx2() && supports_bmi2()) {
 936     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 937       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 938     }
 939   } else
 940 #endif
 941   if (UseSHA512Intrinsics) {
 942     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 943     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 944   }
 945 
 946   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 947     FLAG_SET_DEFAULT(UseSHA, false);
 948   }
 949 
 950   if (UseAdler32Intrinsics) {
 951     warning("Adler32Intrinsics not available on this CPU.");
 952     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 953   }
 954 
 955   if (!supports_rtm() && UseRTMLocking) {
 956     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 957     // setting during arguments processing. See use_biased_locking().
 958     // VM_Version_init() is executed after UseBiasedLocking is used
 959     // in Thread::allocate().
 960     vm_exit_during_initialization("RTM instructions are not available on this CPU");
 961   }
 962 
 963 #if INCLUDE_RTM_OPT
 964   if (UseRTMLocking) {
 965     if (is_client_compilation_mode_vm()) {
 966       // Only C2 does RTM locking optimization.
 967       // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 968       // setting during arguments processing. See use_biased_locking().
 969       vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 970     }
 971     if (is_intel_family_core()) {
 972       if ((_model == CPU_MODEL_HASWELL_E3) ||
 973           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
 974           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
 975         // currently a collision between SKL and HSW_E3
 976         if (!UnlockExperimentalVMOptions && UseAVX < 3) {
 977           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
 978                                         "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 979         } else {
 980           warning("UseRTMLocking is only available as experimental option on this platform.");
 981         }
 982       }
 983     }
 984     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 985       // RTM locking should be used only for applications with
 986       // high lock contention. For now we do not use it by default.
 987       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 988     }
 989   } else { // !UseRTMLocking
 990     if (UseRTMForStackLocks) {
 991       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 992         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 993       }
 994       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 995     }
 996     if (UseRTMDeopt) {
 997       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 998     }
 999     if (PrintPreciseRTMLockingStatistics) {
1000       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
1001     }
1002   }
1003 #else
1004   if (UseRTMLocking) {
1005     // Only C2 does RTM locking optimization.
1006     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
1007     // setting during arguments processing. See use_biased_locking().
1008     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1009   }
1010 #endif
1011 
1012 #ifdef COMPILER2
1013   if (UseFPUForSpilling) {
1014     if (UseSSE < 2) {
1015       // Only supported with SSE2+
1016       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
1017     }
1018   }
1019 #endif
1020 
1021 #if COMPILER2_OR_JVMCI
1022   int max_vector_size = 0;
1023   if (UseSSE < 2) {
1024     // Vectors (in XMM) are only supported with SSE2+
1025     // SSE is always 2 on x64.
1026     max_vector_size = 0;
1027   } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1028     // 16 byte vectors (in XMM) are supported with SSE2+
1029     max_vector_size = 16;
1030   } else if (UseAVX == 1 || UseAVX == 2) {
1031     // 32 bytes vectors (in YMM) are only supported with AVX+
1032     max_vector_size = 32;
1033   } else if (UseAVX > 2) {
1034     // 64 bytes vectors (in ZMM) are only supported with AVX 3
1035     max_vector_size = 64;
1036   }
1037 
1038 #ifdef _LP64
1039   int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1040 #else
1041   int min_vector_size = 0;
1042 #endif
1043 
1044   if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1045     if (MaxVectorSize < min_vector_size) {
1046       warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1047       FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1048     }
1049     if (MaxVectorSize > max_vector_size) {
1050       warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1051       FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1052     }
1053     if (!is_power_of_2(MaxVectorSize)) {
1054       warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1055       FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1056     }
1057   } else {
1058     // If default, use highest supported configuration
1059     FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1060   }
1061 
1062 #if defined(COMPILER2) && defined(ASSERT)
1063   if (MaxVectorSize > 0) {
1064     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1065       tty->print_cr("State of YMM registers after signal handle:");
1066       int nreg = 2 LP64_ONLY(+2);
1067       const char* ymm_name[4] = {"0", "7", "8", "15"};
1068       for (int i = 0; i < nreg; i++) {
1069         tty->print("YMM%s:", ymm_name[i]);
1070         for (int j = 7; j >=0; j--) {
1071           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1072         }
1073         tty->cr();
1074       }
1075     }
1076   }
1077 #endif // COMPILER2 && ASSERT
1078 
1079   if (!FLAG_IS_DEFAULT(AVX3Threshold)) {
1080     if (!is_power_of_2(AVX3Threshold)) {
1081       warning("AVX3Threshold must be a power of 2");
1082       FLAG_SET_DEFAULT(AVX3Threshold, 4096);
1083     }
1084   }
1085 
1086 #ifdef _LP64
1087   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1088     UseMultiplyToLenIntrinsic = true;
1089   }
1090   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1091     UseSquareToLenIntrinsic = true;
1092   }
1093   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1094     UseMulAddIntrinsic = true;
1095   }
1096   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1097     UseMontgomeryMultiplyIntrinsic = true;
1098   }
1099   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1100     UseMontgomerySquareIntrinsic = true;
1101   }
1102 #else
1103   if (UseMultiplyToLenIntrinsic) {
1104     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1105       warning("multiplyToLen intrinsic is not available in 32-bit VM");
1106     }
1107     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1108   }
1109   if (UseMontgomeryMultiplyIntrinsic) {
1110     if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1111       warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1112     }
1113     FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1114   }
1115   if (UseMontgomerySquareIntrinsic) {
1116     if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1117       warning("montgomerySquare intrinsic is not available in 32-bit VM");
1118     }
1119     FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1120   }
1121   if (UseSquareToLenIntrinsic) {
1122     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1123       warning("squareToLen intrinsic is not available in 32-bit VM");
1124     }
1125     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1126   }
1127   if (UseMulAddIntrinsic) {
1128     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1129       warning("mulAdd intrinsic is not available in 32-bit VM");
1130     }
1131     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1132   }
1133 #endif // _LP64
1134 #endif // COMPILER2_OR_JVMCI
1135 
1136   // On new cpus instructions which update whole XMM register should be used
1137   // to prevent partial register stall due to dependencies on high half.
1138   //
1139   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
1140   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1141   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
1142   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
1143 
1144 
1145   if (is_zx()) { // ZX cpus specific settings
1146     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1147       UseStoreImmI16 = false; // don't use it on ZX cpus
1148     }
1149     if ((cpu_family() == 6) || (cpu_family() == 7)) {
1150       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1151         // Use it on all ZX cpus
1152         UseAddressNop = true;
1153       }
1154     }
1155     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1156       UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1157     }
1158     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1159       if (supports_sse3()) {
1160         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1161       } else {
1162         UseXmmRegToRegMoveAll = false;
1163       }
1164     }
1165     if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1166 #ifdef COMPILER2
1167       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1168         // For new ZX cpus do the next optimization:
1169         // don't align the beginning of a loop if there are enough instructions
1170         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1171         // in current fetch line (OptoLoopAlignment) or the padding
1172         // is big (> MaxLoopPad).
1173         // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1174         // generated NOP instructions. 11 is the largest size of one
1175         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1176         MaxLoopPad = 11;
1177       }
1178 #endif // COMPILER2
1179       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1180         UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1181       }
1182       if (supports_sse4_2()) { // new ZX cpus
1183         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1184           UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1185         }
1186       }
1187       if (supports_sse4_2()) {
1188         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1189           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1190         }
1191       } else {
1192         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1193           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1194         }
1195         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1196       }
1197     }
1198 
1199     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1200       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1201     }
1202   }
1203 
1204   if (is_amd_family()) { // AMD cpus specific settings
1205     if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
1206       // Use it on new AMD cpus starting from Opteron.
1207       UseAddressNop = true;
1208     }
1209     if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
1210       // Use it on new AMD cpus starting from Opteron.
1211       UseNewLongLShift = true;
1212     }
1213     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1214       if (supports_sse4a()) {
1215         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1216       } else {
1217         UseXmmLoadAndClearUpper = false;
1218       }
1219     }
1220     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1221       if (supports_sse4a()) {
1222         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1223       } else {
1224         UseXmmRegToRegMoveAll = false;
1225       }
1226     }
1227     if (FLAG_IS_DEFAULT(UseXmmI2F)) {
1228       if (supports_sse4a()) {
1229         UseXmmI2F = true;
1230       } else {
1231         UseXmmI2F = false;
1232       }
1233     }
1234     if (FLAG_IS_DEFAULT(UseXmmI2D)) {
1235       if (supports_sse4a()) {
1236         UseXmmI2D = true;
1237       } else {
1238         UseXmmI2D = false;
1239       }
1240     }
1241     if (supports_sse4_2()) {
1242       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1243         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1244       }
1245     } else {
1246       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1247         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1248       }
1249       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1250     }
1251 
1252     // some defaults for AMD family 15h
1253     if (cpu_family() == 0x15) {
1254       // On family 15h processors default is no sw prefetch
1255       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1256         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1257       }
1258       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1259       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1260         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1261       }
1262       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1263       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1264         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1265       }
1266       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1267         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1268       }
1269     }
1270 
1271 #ifdef COMPILER2
1272     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1273       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1274       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1275     }
1276 #endif // COMPILER2
1277 
1278     // Some defaults for AMD family 17h || Hygon family 18h
1279     if (cpu_family() == 0x17 || cpu_family() == 0x18) {
1280       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1281       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1282         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1283       }
1284       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1285         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1286       }
1287 #ifdef COMPILER2
1288       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1289         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1290       }
1291 #endif
1292     }
1293   }
1294 
1295   if (is_intel()) { // Intel cpus specific settings
1296     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1297       UseStoreImmI16 = false; // don't use it on Intel cpus
1298     }
1299     if (cpu_family() == 6 || cpu_family() == 15) {
1300       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1301         // Use it on all Intel cpus starting from PentiumPro
1302         UseAddressNop = true;
1303       }
1304     }
1305     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1306       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1307     }
1308     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1309       if (supports_sse3()) {
1310         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1311       } else {
1312         UseXmmRegToRegMoveAll = false;
1313       }
1314     }
1315     if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
1316 #ifdef COMPILER2
1317       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1318         // For new Intel cpus do the next optimization:
1319         // don't align the beginning of a loop if there are enough instructions
1320         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1321         // in current fetch line (OptoLoopAlignment) or the padding
1322         // is big (> MaxLoopPad).
1323         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1324         // generated NOP instructions. 11 is the largest size of one
1325         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1326         MaxLoopPad = 11;
1327       }
1328 #endif // COMPILER2
1329       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1330         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1331       }
1332       if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1333         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1334           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1335         }
1336       }
1337       if (supports_sse4_2()) {
1338         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1339           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1340         }
1341       } else {
1342         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1343           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1344         }
1345         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1346       }
1347     }
1348     if (is_atom_family() || is_knights_family()) {
1349 #ifdef COMPILER2
1350       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1351         OptoScheduling = true;
1352       }
1353 #endif
1354       if (supports_sse4_2()) { // Silvermont
1355         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1356           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1357         }
1358       }
1359       if (FLAG_IS_DEFAULT(UseIncDec)) {
1360         FLAG_SET_DEFAULT(UseIncDec, false);
1361       }
1362     }
1363     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1364       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1365     }
1366   }
1367 
1368 #ifdef _LP64
1369   if (UseSSE42Intrinsics) {
1370     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1371       UseVectorizedMismatchIntrinsic = true;
1372     }
1373   } else if (UseVectorizedMismatchIntrinsic) {
1374     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1375       warning("vectorizedMismatch intrinsics are not available on this CPU");
1376     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1377   }
1378 #else
1379   if (UseVectorizedMismatchIntrinsic) {
1380     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1381       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1382     }
1383     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1384   }
1385 #endif // _LP64
1386 
1387   // Use count leading zeros count instruction if available.
1388   if (supports_lzcnt()) {
1389     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1390       UseCountLeadingZerosInstruction = true;
1391     }
1392    } else if (UseCountLeadingZerosInstruction) {
1393     warning("lzcnt instruction is not available on this CPU");
1394     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1395   }
1396 
1397   // Use count trailing zeros instruction if available
1398   if (supports_bmi1()) {
1399     // tzcnt does not require VEX prefix
1400     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1401       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1402         // Don't use tzcnt if BMI1 is switched off on command line.
1403         UseCountTrailingZerosInstruction = false;
1404       } else {
1405         UseCountTrailingZerosInstruction = true;
1406       }
1407     }
1408   } else if (UseCountTrailingZerosInstruction) {
1409     warning("tzcnt instruction is not available on this CPU");
1410     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1411   }
1412 
1413   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1414   // VEX prefix is generated only when AVX > 0.
1415   if (supports_bmi1() && supports_avx()) {
1416     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1417       UseBMI1Instructions = true;
1418     }
1419   } else if (UseBMI1Instructions) {
1420     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1421     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1422   }
1423 
1424   if (supports_bmi2() && supports_avx()) {
1425     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1426       UseBMI2Instructions = true;
1427     }
1428   } else if (UseBMI2Instructions) {
1429     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1430     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1431   }
1432 
1433   // Use population count instruction if available.
1434   if (supports_popcnt()) {
1435     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1436       UsePopCountInstruction = true;
1437     }
1438   } else if (UsePopCountInstruction) {
1439     warning("POPCNT instruction is not available on this CPU");
1440     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1441   }
1442 
1443   // Use fast-string operations if available.
1444   if (supports_erms()) {
1445     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1446       UseFastStosb = true;
1447     }
1448   } else if (UseFastStosb) {
1449     warning("fast-string operations are not available on this CPU");
1450     FLAG_SET_DEFAULT(UseFastStosb, false);
1451   }
1452 
1453   // Use XMM/YMM MOVDQU instruction for Object Initialization
1454   if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
1455     if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1456       UseXMMForObjInit = true;
1457     }
1458   } else if (UseXMMForObjInit) {
1459     warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1460     FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1461   }
1462 
1463 #ifdef COMPILER2
1464   if (FLAG_IS_DEFAULT(AlignVector)) {
1465     // Modern processors allow misaligned memory operations for vectors.
1466     AlignVector = !UseUnalignedLoadStores;
1467   }
1468 #endif // COMPILER2
1469 
1470   if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1471     if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1472       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1473     } else if (!supports_sse() && supports_3dnow_prefetch()) {
1474       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1475     }
1476   }
1477 
1478   // Allocation prefetch settings
1479   intx cache_line_size = prefetch_data_size();
1480   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1481       (cache_line_size > AllocatePrefetchStepSize)) {
1482     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1483   }
1484 
1485   if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1486     assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1487     if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1488       warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1489     }
1490     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1491   }
1492 
1493   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1494     bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1495     FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1496   }
1497 
1498   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1499     if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1500         supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1501       FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1502     }
1503 #ifdef COMPILER2
1504     if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1505       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1506     }
1507 #endif
1508   }
1509 
1510   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1511 #ifdef COMPILER2
1512     if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1513       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1514     }
1515 #endif
1516   }
1517 
1518 #ifdef _LP64
1519   // Prefetch settings
1520 
1521   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
1522   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1523   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1524   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1525 
1526   // gc copy/scan is disabled if prefetchw isn't supported, because
1527   // Prefetch::write emits an inlined prefetchw on Linux.
1528   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
1529   // The used prefetcht0 instruction works for both amd64 and em64t.
1530 
1531   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1532     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1533   }
1534   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1535     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1536   }
1537   if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1538     FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1539   }
1540 #endif
1541 
1542   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1543      (cache_line_size > ContendedPaddingWidth))
1544      ContendedPaddingWidth = cache_line_size;
1545 
1546   // This machine allows unaligned memory accesses
1547   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1548     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1549   }
1550 
1551 #ifndef PRODUCT
1552   if (log_is_enabled(Info, os, cpu)) {
1553     LogStream ls(Log(os, cpu)::info());
1554     outputStream* log = &ls;
1555     log->print_cr("Logical CPUs per core: %u",
1556                   logical_processors_per_package());
1557     log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1558     log->print("UseSSE=%d", (int) UseSSE);
1559     if (UseAVX > 0) {
1560       log->print("  UseAVX=%d", (int) UseAVX);
1561     }
1562     if (UseAES) {
1563       log->print("  UseAES=1");
1564     }
1565 #ifdef COMPILER2
1566     if (MaxVectorSize > 0) {
1567       log->print("  MaxVectorSize=%d", (int) MaxVectorSize);
1568     }
1569 #endif
1570     log->cr();
1571     log->print("Allocation");
1572     if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1573       log->print_cr(": no prefetching");
1574     } else {
1575       log->print(" prefetching: ");
1576       if (UseSSE == 0 && supports_3dnow_prefetch()) {
1577         log->print("PREFETCHW");
1578       } else if (UseSSE >= 1) {
1579         if (AllocatePrefetchInstr == 0) {
1580           log->print("PREFETCHNTA");
1581         } else if (AllocatePrefetchInstr == 1) {
1582           log->print("PREFETCHT0");
1583         } else if (AllocatePrefetchInstr == 2) {
1584           log->print("PREFETCHT2");
1585         } else if (AllocatePrefetchInstr == 3) {
1586           log->print("PREFETCHW");
1587         }
1588       }
1589       if (AllocatePrefetchLines > 1) {
1590         log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1591       } else {
1592         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1593       }
1594     }
1595 
1596     if (PrefetchCopyIntervalInBytes > 0) {
1597       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1598     }
1599     if (PrefetchScanIntervalInBytes > 0) {
1600       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1601     }
1602     if (PrefetchFieldsAhead > 0) {
1603       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1604     }
1605     if (ContendedPaddingWidth > 0) {
1606       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1607     }
1608   }
1609 #endif // !PRODUCT
1610 }
1611 
1612 void VM_Version::print_platform_virtualization_info(outputStream* st) {
1613   VirtualizationType vrt = VM_Version::get_detected_virtualization();
1614   if (vrt == XenHVM) {
1615     st->print_cr("Xen hardware-assisted virtualization detected");
1616   } else if (vrt == KVM) {
1617     st->print_cr("KVM virtualization detected");
1618   } else if (vrt == VMWare) {
1619     st->print_cr("VMWare virtualization detected");
1620     VirtualizationSupport::print_virtualization_info(st);
1621   } else if (vrt == HyperV) {
1622     st->print_cr("HyperV virtualization detected");
1623   }
1624 }
1625 
1626 void VM_Version::check_virt_cpuid(uint32_t idx, uint32_t *regs) {
1627 // TODO support 32 bit
1628 #if defined(_LP64)
1629 #if defined(_MSC_VER)
1630   // Allocate space for the code
1631   const int code_size = 100;
1632   ResourceMark rm;
1633   CodeBuffer cb("detect_virt", code_size, 0);
1634   MacroAssembler* a = new MacroAssembler(&cb);
1635   address code = a->pc();
1636   void (*test)(uint32_t idx, uint32_t *regs) = (void(*)(uint32_t idx, uint32_t *regs))code;
1637 
1638   a->movq(r9, rbx); // save nonvolatile register
1639 
1640   // next line would not work on 32-bit
1641   a->movq(rax, c_rarg0 /* rcx */);
1642   a->movq(r8, c_rarg1 /* rdx */);
1643   a->cpuid();
1644   a->movl(Address(r8,  0), rax);
1645   a->movl(Address(r8,  4), rbx);
1646   a->movl(Address(r8,  8), rcx);
1647   a->movl(Address(r8, 12), rdx);
1648 
1649   a->movq(rbx, r9); // restore nonvolatile register
1650   a->ret(0);
1651 
1652   uint32_t *code_end = (uint32_t *)a->pc();
1653   a->flush();
1654 
1655   // execute code
1656   (*test)(idx, regs);
1657 #elif defined(__GNUC__)
1658   __asm__ volatile (
1659      "        cpuid;"
1660      "        mov %%eax,(%1);"
1661      "        mov %%ebx,4(%1);"
1662      "        mov %%ecx,8(%1);"
1663      "        mov %%edx,12(%1);"
1664      : "+a" (idx)
1665      : "S" (regs)
1666      : "ebx", "ecx", "edx", "memory" );
1667 #endif
1668 #endif
1669 }
1670 
1671 
1672 bool VM_Version::use_biased_locking() {
1673 #if INCLUDE_RTM_OPT
1674   // RTM locking is most useful when there is high lock contention and
1675   // low data contention.  With high lock contention the lock is usually
1676   // inflated and biased locking is not suitable for that case.
1677   // RTM locking code requires that biased locking is off.
1678   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1679   // because it is used by Thread::allocate() which is called before
1680   // VM_Version::initialize().
1681   if (UseRTMLocking && UseBiasedLocking) {
1682     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1683       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1684     } else {
1685       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1686       UseBiasedLocking = false;
1687     }
1688   }
1689 #endif
1690   return UseBiasedLocking;
1691 }
1692 
1693 // On Xen, the cpuid instruction returns
1694 //  eax / registers[0]: Version of Xen
1695 //  ebx / registers[1]: chars 'XenV'
1696 //  ecx / registers[2]: chars 'MMXe'
1697 //  edx / registers[3]: chars 'nVMM'
1698 //
1699 // On KVM / VMWare / MS Hyper-V, the cpuid instruction returns
1700 //  ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr'
1701 //  ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof'
1702 //  edx / registers[3]: chars 'M'    / 'ware' / 't Hv'
1703 //
1704 // more information :
1705 // https://kb.vmware.com/s/article/1009458
1706 //
1707 void VM_Version::check_virtualizations() {
1708 #if defined(_LP64)
1709   uint32_t registers[4];
1710   char signature[13];
1711   uint32_t base;
1712   signature[12] = '\0';
1713   memset((void*)registers, 0, 4*sizeof(uint32_t));
1714 
1715   for (base = 0x40000000; base < 0x40010000; base += 0x100) {
1716     check_virt_cpuid(base, registers);
1717 
1718     *(uint32_t *)(signature + 0) = registers[1];
1719     *(uint32_t *)(signature + 4) = registers[2];
1720     *(uint32_t *)(signature + 8) = registers[3];
1721 
1722     if (strncmp("VMwareVMware", signature, 12) == 0) {
1723       Abstract_VM_Version::_detected_virtualization = VMWare;
1724       // check for extended metrics from guestlib
1725       VirtualizationSupport::initialize();
1726     }
1727 
1728     if (strncmp("Microsoft Hv", signature, 12) == 0) {
1729       Abstract_VM_Version::_detected_virtualization = HyperV;
1730     }
1731 
1732     if (strncmp("KVMKVMKVM", signature, 9) == 0) {
1733       Abstract_VM_Version::_detected_virtualization = KVM;
1734     }
1735 
1736     if (strncmp("XenVMMXenVMM", signature, 12) == 0) {
1737       Abstract_VM_Version::_detected_virtualization = XenHVM;
1738     }
1739   }
1740 #endif
1741 }
1742 
1743 void VM_Version::initialize() {
1744   ResourceMark rm;
1745   // Making this stub must be FIRST use of assembler
1746 
1747   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1748   if (stub_blob == NULL) {
1749     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1750   }
1751   CodeBuffer c(stub_blob);
1752   VM_Version_StubGenerator g(&c);
1753   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1754                                      g.generate_get_cpu_info());
1755 
1756   get_processor_features();
1757   if (cpu_family() > 4) { // it supports CPUID
1758     check_virtualizations();
1759   }
1760 }