1 /* 2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "gc/shared/cardTableBarrierSet.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "prims/methodHandles.hpp" 33 #include "runtime/biasedLocking.hpp" 34 #include "runtime/objectMonitor.hpp" 35 #include "runtime/os.hpp" 36 #include "runtime/sharedRuntime.hpp" 37 #include "runtime/stubRoutines.hpp" 38 #include "utilities/macros.hpp" 39 40 #ifdef PRODUCT 41 #define BLOCK_COMMENT(str) /* nothing */ 42 #define STOP(error) stop(error) 43 #else 44 #define BLOCK_COMMENT(str) block_comment(str) 45 #define STOP(error) block_comment(error); stop(error) 46 #endif 47 48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 49 // Implementation of AddressLiteral 50 51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. 52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { 53 // -----------------Table 4.5 -------------------- // 54 16, 32, 64, // EVEX_FV(0) 55 4, 4, 4, // EVEX_FV(1) - with Evex.b 56 16, 32, 64, // EVEX_FV(2) - with Evex.w 57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b 58 8, 16, 32, // EVEX_HV(0) 59 4, 4, 4, // EVEX_HV(1) - with Evex.b 60 // -----------------Table 4.6 -------------------- // 61 16, 32, 64, // EVEX_FVM(0) 62 1, 1, 1, // EVEX_T1S(0) 63 2, 2, 2, // EVEX_T1S(1) 64 4, 4, 4, // EVEX_T1S(2) 65 8, 8, 8, // EVEX_T1S(3) 66 4, 4, 4, // EVEX_T1F(0) 67 8, 8, 8, // EVEX_T1F(1) 68 8, 8, 8, // EVEX_T2(0) 69 0, 16, 16, // EVEX_T2(1) 70 0, 16, 16, // EVEX_T4(0) 71 0, 0, 32, // EVEX_T4(1) 72 0, 0, 32, // EVEX_T8(0) 73 8, 16, 32, // EVEX_HVM(0) 74 4, 8, 16, // EVEX_QVM(0) 75 2, 4, 8, // EVEX_OVM(0) 76 16, 16, 16, // EVEX_M128(0) 77 8, 32, 64, // EVEX_DUP(0) 78 0, 0, 0 // EVEX_NTUP 79 }; 80 81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 82 _is_lval = false; 83 _target = target; 84 switch (rtype) { 85 case relocInfo::oop_type: 86 case relocInfo::metadata_type: 87 // Oops are a special case. Normally they would be their own section 88 // but in cases like icBuffer they are literals in the code stream that 89 // we don't have a section for. We use none so that we get a literal address 90 // which is always patchable. 91 break; 92 case relocInfo::external_word_type: 93 _rspec = external_word_Relocation::spec(target); 94 break; 95 case relocInfo::internal_word_type: 96 _rspec = internal_word_Relocation::spec(target); 97 break; 98 case relocInfo::opt_virtual_call_type: 99 _rspec = opt_virtual_call_Relocation::spec(); 100 break; 101 case relocInfo::static_call_type: 102 _rspec = static_call_Relocation::spec(); 103 break; 104 case relocInfo::runtime_call_type: 105 _rspec = runtime_call_Relocation::spec(); 106 break; 107 case relocInfo::poll_type: 108 case relocInfo::poll_return_type: 109 _rspec = Relocation::spec_simple(rtype); 110 break; 111 case relocInfo::none: 112 break; 113 default: 114 ShouldNotReachHere(); 115 break; 116 } 117 } 118 119 // Implementation of Address 120 121 #ifdef _LP64 122 123 Address Address::make_array(ArrayAddress adr) { 124 // Not implementable on 64bit machines 125 // Should have been handled higher up the call chain. 126 ShouldNotReachHere(); 127 return Address(); 128 } 129 130 // exceedingly dangerous constructor 131 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 132 _base = noreg; 133 _index = noreg; 134 _scale = no_scale; 135 _disp = disp; 136 _xmmindex = xnoreg; 137 _isxmmindex = false; 138 switch (rtype) { 139 case relocInfo::external_word_type: 140 _rspec = external_word_Relocation::spec(loc); 141 break; 142 case relocInfo::internal_word_type: 143 _rspec = internal_word_Relocation::spec(loc); 144 break; 145 case relocInfo::runtime_call_type: 146 // HMM 147 _rspec = runtime_call_Relocation::spec(); 148 break; 149 case relocInfo::poll_type: 150 case relocInfo::poll_return_type: 151 _rspec = Relocation::spec_simple(rtype); 152 break; 153 case relocInfo::none: 154 break; 155 default: 156 ShouldNotReachHere(); 157 } 158 } 159 #else // LP64 160 161 Address Address::make_array(ArrayAddress adr) { 162 AddressLiteral base = adr.base(); 163 Address index = adr.index(); 164 assert(index._disp == 0, "must not have disp"); // maybe it can? 165 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 166 array._rspec = base._rspec; 167 return array; 168 } 169 170 // exceedingly dangerous constructor 171 Address::Address(address loc, RelocationHolder spec) { 172 _base = noreg; 173 _index = noreg; 174 _scale = no_scale; 175 _disp = (intptr_t) loc; 176 _rspec = spec; 177 _xmmindex = xnoreg; 178 _isxmmindex = false; 179 } 180 181 #endif // _LP64 182 183 184 185 // Convert the raw encoding form into the form expected by the constructor for 186 // Address. An index of 4 (rsp) corresponds to having no index, so convert 187 // that to noreg for the Address constructor. 188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 189 RelocationHolder rspec; 190 if (disp_reloc != relocInfo::none) { 191 rspec = Relocation::spec_simple(disp_reloc); 192 } 193 bool valid_index = index != rsp->encoding(); 194 if (valid_index) { 195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 196 madr._rspec = rspec; 197 return madr; 198 } else { 199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 200 madr._rspec = rspec; 201 return madr; 202 } 203 } 204 205 // Implementation of Assembler 206 207 int AbstractAssembler::code_fill_byte() { 208 return (u_char)'\xF4'; // hlt 209 } 210 211 // make this go away someday 212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 213 if (rtype == relocInfo::none) 214 emit_int32(data); 215 else 216 emit_data(data, Relocation::spec_simple(rtype), format); 217 } 218 219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 220 assert(imm_operand == 0, "default format must be immediate in this file"); 221 assert(inst_mark() != NULL, "must be inside InstructionMark"); 222 if (rspec.type() != relocInfo::none) { 223 #ifdef ASSERT 224 check_relocation(rspec, format); 225 #endif 226 // Do not use AbstractAssembler::relocate, which is not intended for 227 // embedded words. Instead, relocate to the enclosing instruction. 228 229 // hack. call32 is too wide for mask so use disp32 230 if (format == call32_operand) 231 code_section()->relocate(inst_mark(), rspec, disp32_operand); 232 else 233 code_section()->relocate(inst_mark(), rspec, format); 234 } 235 emit_int32(data); 236 } 237 238 static int encode(Register r) { 239 int enc = r->encoding(); 240 if (enc >= 8) { 241 enc -= 8; 242 } 243 return enc; 244 } 245 246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 247 assert(dst->has_byte_register(), "must have byte register"); 248 assert(isByte(op1) && isByte(op2), "wrong opcode"); 249 assert(isByte(imm8), "not a byte"); 250 assert((op1 & 0x01) == 0, "should be 8bit operation"); 251 emit_int8(op1); 252 emit_int8(op2 | encode(dst)); 253 emit_int8(imm8); 254 } 255 256 257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 258 assert(isByte(op1) && isByte(op2), "wrong opcode"); 259 assert((op1 & 0x01) == 1, "should be 32bit operation"); 260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 261 if (is8bit(imm32)) { 262 emit_int8(op1 | 0x02); // set sign bit 263 emit_int8(op2 | encode(dst)); 264 emit_int8(imm32 & 0xFF); 265 } else { 266 emit_int8(op1); 267 emit_int8(op2 | encode(dst)); 268 emit_int32(imm32); 269 } 270 } 271 272 // Force generation of a 4 byte immediate value even if it fits into 8bit 273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { 274 assert(isByte(op1) && isByte(op2), "wrong opcode"); 275 assert((op1 & 0x01) == 1, "should be 32bit operation"); 276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 277 emit_int8(op1); 278 emit_int8(op2 | encode(dst)); 279 emit_int32(imm32); 280 } 281 282 // immediate-to-memory forms 283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 284 assert((op1 & 0x01) == 1, "should be 32bit operation"); 285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 286 if (is8bit(imm32)) { 287 emit_int8(op1 | 0x02); // set sign bit 288 emit_operand(rm, adr, 1); 289 emit_int8(imm32 & 0xFF); 290 } else { 291 emit_int8(op1); 292 emit_operand(rm, adr, 4); 293 emit_int32(imm32); 294 } 295 } 296 297 298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 299 assert(isByte(op1) && isByte(op2), "wrong opcode"); 300 emit_int8(op1); 301 emit_int8(op2 | encode(dst) << 3 | encode(src)); 302 } 303 304 305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) { 307 int mod_idx = 0; 308 // We will test if the displacement fits the compressed format and if so 309 // apply the compression to the displacment iff the result is8bit. 310 if (VM_Version::supports_evex() && is_evex_inst) { 311 switch (cur_tuple_type) { 312 case EVEX_FV: 313 if ((cur_encoding & VEX_W) == VEX_W) { 314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 315 } else { 316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 317 } 318 break; 319 320 case EVEX_HV: 321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 322 break; 323 324 case EVEX_FVM: 325 break; 326 327 case EVEX_T1S: 328 switch (in_size_in_bits) { 329 case EVEX_8bit: 330 break; 331 332 case EVEX_16bit: 333 mod_idx = 1; 334 break; 335 336 case EVEX_32bit: 337 mod_idx = 2; 338 break; 339 340 case EVEX_64bit: 341 mod_idx = 3; 342 break; 343 } 344 break; 345 346 case EVEX_T1F: 347 case EVEX_T2: 348 case EVEX_T4: 349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; 350 break; 351 352 case EVEX_T8: 353 break; 354 355 case EVEX_HVM: 356 break; 357 358 case EVEX_QVM: 359 break; 360 361 case EVEX_OVM: 362 break; 363 364 case EVEX_M128: 365 break; 366 367 case EVEX_DUP: 368 break; 369 370 default: 371 assert(0, "no valid evex tuple_table entry"); 372 break; 373 } 374 375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; 377 if ((disp % disp_factor) == 0) { 378 int new_disp = disp / disp_factor; 379 if ((-0x80 <= new_disp && new_disp < 0x80)) { 380 disp = new_disp; 381 } 382 } else { 383 return false; 384 } 385 } 386 } 387 return (-0x80 <= disp && disp < 0x80); 388 } 389 390 391 bool Assembler::emit_compressed_disp_byte(int &disp) { 392 int mod_idx = 0; 393 // We will test if the displacement fits the compressed format and if so 394 // apply the compression to the displacment iff the result is8bit. 395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) { 396 int evex_encoding = _attributes->get_evex_encoding(); 397 int tuple_type = _attributes->get_tuple_type(); 398 switch (tuple_type) { 399 case EVEX_FV: 400 if ((evex_encoding & VEX_W) == VEX_W) { 401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 402 } else { 403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 404 } 405 break; 406 407 case EVEX_HV: 408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 409 break; 410 411 case EVEX_FVM: 412 break; 413 414 case EVEX_T1S: 415 switch (_attributes->get_input_size()) { 416 case EVEX_8bit: 417 break; 418 419 case EVEX_16bit: 420 mod_idx = 1; 421 break; 422 423 case EVEX_32bit: 424 mod_idx = 2; 425 break; 426 427 case EVEX_64bit: 428 mod_idx = 3; 429 break; 430 } 431 break; 432 433 case EVEX_T1F: 434 case EVEX_T2: 435 case EVEX_T4: 436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0; 437 break; 438 439 case EVEX_T8: 440 break; 441 442 case EVEX_HVM: 443 break; 444 445 case EVEX_QVM: 446 break; 447 448 case EVEX_OVM: 449 break; 450 451 case EVEX_M128: 452 break; 453 454 case EVEX_DUP: 455 break; 456 457 default: 458 assert(0, "no valid evex tuple_table entry"); 459 break; 460 } 461 462 int vector_len = _attributes->get_vector_len(); 463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len]; 465 if ((disp % disp_factor) == 0) { 466 int new_disp = disp / disp_factor; 467 if (is8bit(new_disp)) { 468 disp = new_disp; 469 } 470 } else { 471 return false; 472 } 473 } 474 } 475 return is8bit(disp); 476 } 477 478 479 void Assembler::emit_operand(Register reg, Register base, Register index, 480 Address::ScaleFactor scale, int disp, 481 RelocationHolder const& rspec, 482 int rip_relative_correction) { 483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 484 485 // Encode the registers as needed in the fields they are used in 486 487 int regenc = encode(reg) << 3; 488 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 489 int baseenc = base->is_valid() ? encode(base) : 0; 490 491 if (base->is_valid()) { 492 if (index->is_valid()) { 493 assert(scale != Address::no_scale, "inconsistent address"); 494 // [base + index*scale + disp] 495 if (disp == 0 && rtype == relocInfo::none && 496 base != rbp LP64_ONLY(&& base != r13)) { 497 // [base + index*scale] 498 // [00 reg 100][ss index base] 499 assert(index != rsp, "illegal addressing mode"); 500 emit_int8(0x04 | regenc); 501 emit_int8(scale << 6 | indexenc | baseenc); 502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 503 // [base + index*scale + imm8] 504 // [01 reg 100][ss index base] imm8 505 assert(index != rsp, "illegal addressing mode"); 506 emit_int8(0x44 | regenc); 507 emit_int8(scale << 6 | indexenc | baseenc); 508 emit_int8(disp & 0xFF); 509 } else { 510 // [base + index*scale + disp32] 511 // [10 reg 100][ss index base] disp32 512 assert(index != rsp, "illegal addressing mode"); 513 emit_int8(0x84 | regenc); 514 emit_int8(scale << 6 | indexenc | baseenc); 515 emit_data(disp, rspec, disp32_operand); 516 } 517 } else if (base == rsp LP64_ONLY(|| base == r12)) { 518 // [rsp + disp] 519 if (disp == 0 && rtype == relocInfo::none) { 520 // [rsp] 521 // [00 reg 100][00 100 100] 522 emit_int8(0x04 | regenc); 523 emit_int8(0x24); 524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 525 // [rsp + imm8] 526 // [01 reg 100][00 100 100] disp8 527 emit_int8(0x44 | regenc); 528 emit_int8(0x24); 529 emit_int8(disp & 0xFF); 530 } else { 531 // [rsp + imm32] 532 // [10 reg 100][00 100 100] disp32 533 emit_int8(0x84 | regenc); 534 emit_int8(0x24); 535 emit_data(disp, rspec, disp32_operand); 536 } 537 } else { 538 // [base + disp] 539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 540 if (disp == 0 && rtype == relocInfo::none && 541 base != rbp LP64_ONLY(&& base != r13)) { 542 // [base] 543 // [00 reg base] 544 emit_int8(0x00 | regenc | baseenc); 545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 546 // [base + disp8] 547 // [01 reg base] disp8 548 emit_int8(0x40 | regenc | baseenc); 549 emit_int8(disp & 0xFF); 550 } else { 551 // [base + disp32] 552 // [10 reg base] disp32 553 emit_int8(0x80 | regenc | baseenc); 554 emit_data(disp, rspec, disp32_operand); 555 } 556 } 557 } else { 558 if (index->is_valid()) { 559 assert(scale != Address::no_scale, "inconsistent address"); 560 // [index*scale + disp] 561 // [00 reg 100][ss index 101] disp32 562 assert(index != rsp, "illegal addressing mode"); 563 emit_int8(0x04 | regenc); 564 emit_int8(scale << 6 | indexenc | 0x05); 565 emit_data(disp, rspec, disp32_operand); 566 } else if (rtype != relocInfo::none ) { 567 // [disp] (64bit) RIP-RELATIVE (32bit) abs 568 // [00 000 101] disp32 569 570 emit_int8(0x05 | regenc); 571 // Note that the RIP-rel. correction applies to the generated 572 // disp field, but _not_ to the target address in the rspec. 573 574 // disp was created by converting the target address minus the pc 575 // at the start of the instruction. That needs more correction here. 576 // intptr_t disp = target - next_ip; 577 assert(inst_mark() != NULL, "must be inside InstructionMark"); 578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 579 int64_t adjusted = disp; 580 // Do rip-rel adjustment for 64bit 581 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 582 assert(is_simm32(adjusted), 583 "must be 32bit offset (RIP relative address)"); 584 emit_data((int32_t) adjusted, rspec, disp32_operand); 585 586 } else { 587 // 32bit never did this, did everything as the rip-rel/disp code above 588 // [disp] ABSOLUTE 589 // [00 reg 100][00 100 101] disp32 590 emit_int8(0x04 | regenc); 591 emit_int8(0x25); 592 emit_data(disp, rspec, disp32_operand); 593 } 594 } 595 } 596 597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 598 Address::ScaleFactor scale, int disp, 599 RelocationHolder const& rspec) { 600 if (UseAVX > 2) { 601 int xreg_enc = reg->encoding(); 602 if (xreg_enc > 15) { 603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 604 emit_operand((Register)new_reg, base, index, scale, disp, rspec); 605 return; 606 } 607 } 608 emit_operand((Register)reg, base, index, scale, disp, rspec); 609 } 610 611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index, 612 Address::ScaleFactor scale, int disp, 613 RelocationHolder const& rspec) { 614 if (UseAVX > 2) { 615 int xreg_enc = reg->encoding(); 616 int xmmindex_enc = index->encoding(); 617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf); 619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec); 620 } else { 621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec); 622 } 623 } 624 625 626 // Secret local extension to Assembler::WhichOperand: 627 #define end_pc_operand (_WhichOperand_limit) 628 629 address Assembler::locate_operand(address inst, WhichOperand which) { 630 // Decode the given instruction, and return the address of 631 // an embedded 32-bit operand word. 632 633 // If "which" is disp32_operand, selects the displacement portion 634 // of an effective address specifier. 635 // If "which" is imm64_operand, selects the trailing immediate constant. 636 // If "which" is call32_operand, selects the displacement of a call or jump. 637 // Caller is responsible for ensuring that there is such an operand, 638 // and that it is 32/64 bits wide. 639 640 // If "which" is end_pc_operand, find the end of the instruction. 641 642 address ip = inst; 643 bool is_64bit = false; 644 645 debug_only(bool has_disp32 = false); 646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 647 648 again_after_prefix: 649 switch (0xFF & *ip++) { 650 651 // These convenience macros generate groups of "case" labels for the switch. 652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 654 case (x)+4: case (x)+5: case (x)+6: case (x)+7 655 #define REP16(x) REP8((x)+0): \ 656 case REP8((x)+8) 657 658 case CS_segment: 659 case SS_segment: 660 case DS_segment: 661 case ES_segment: 662 case FS_segment: 663 case GS_segment: 664 // Seems dubious 665 LP64_ONLY(assert(false, "shouldn't have that prefix")); 666 assert(ip == inst+1, "only one prefix allowed"); 667 goto again_after_prefix; 668 669 case 0x67: 670 case REX: 671 case REX_B: 672 case REX_X: 673 case REX_XB: 674 case REX_R: 675 case REX_RB: 676 case REX_RX: 677 case REX_RXB: 678 NOT_LP64(assert(false, "64bit prefixes")); 679 goto again_after_prefix; 680 681 case REX_W: 682 case REX_WB: 683 case REX_WX: 684 case REX_WXB: 685 case REX_WR: 686 case REX_WRB: 687 case REX_WRX: 688 case REX_WRXB: 689 NOT_LP64(assert(false, "64bit prefixes")); 690 is_64bit = true; 691 goto again_after_prefix; 692 693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 694 case 0x88: // movb a, r 695 case 0x89: // movl a, r 696 case 0x8A: // movb r, a 697 case 0x8B: // movl r, a 698 case 0x8F: // popl a 699 debug_only(has_disp32 = true); 700 break; 701 702 case 0x68: // pushq #32 703 if (which == end_pc_operand) { 704 return ip + 4; 705 } 706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 707 return ip; // not produced by emit_operand 708 709 case 0x66: // movw ... (size prefix) 710 again_after_size_prefix2: 711 switch (0xFF & *ip++) { 712 case REX: 713 case REX_B: 714 case REX_X: 715 case REX_XB: 716 case REX_R: 717 case REX_RB: 718 case REX_RX: 719 case REX_RXB: 720 case REX_W: 721 case REX_WB: 722 case REX_WX: 723 case REX_WXB: 724 case REX_WR: 725 case REX_WRB: 726 case REX_WRX: 727 case REX_WRXB: 728 NOT_LP64(assert(false, "64bit prefix found")); 729 goto again_after_size_prefix2; 730 case 0x8B: // movw r, a 731 case 0x89: // movw a, r 732 debug_only(has_disp32 = true); 733 break; 734 case 0xC7: // movw a, #16 735 debug_only(has_disp32 = true); 736 tail_size = 2; // the imm16 737 break; 738 case 0x0F: // several SSE/SSE2 variants 739 ip--; // reparse the 0x0F 740 goto again_after_prefix; 741 default: 742 ShouldNotReachHere(); 743 } 744 break; 745 746 case REP8(0xB8): // movl/q r, #32/#64(oop?) 747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 748 // these asserts are somewhat nonsensical 749 #ifndef _LP64 750 assert(which == imm_operand || which == disp32_operand, 751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 752 #else 753 assert((which == call32_operand || which == imm_operand) && is_64bit || 754 which == narrow_oop_operand && !is_64bit, 755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 756 #endif // _LP64 757 return ip; 758 759 case 0x69: // imul r, a, #32 760 case 0xC7: // movl a, #32(oop?) 761 tail_size = 4; 762 debug_only(has_disp32 = true); // has both kinds of operands! 763 break; 764 765 case 0x0F: // movx..., etc. 766 switch (0xFF & *ip++) { 767 case 0x3A: // pcmpestri 768 tail_size = 1; 769 case 0x38: // ptest, pmovzxbw 770 ip++; // skip opcode 771 debug_only(has_disp32 = true); // has both kinds of operands! 772 break; 773 774 case 0x70: // pshufd r, r/a, #8 775 debug_only(has_disp32 = true); // has both kinds of operands! 776 case 0x73: // psrldq r, #8 777 tail_size = 1; 778 break; 779 780 case 0x12: // movlps 781 case 0x28: // movaps 782 case 0x2E: // ucomiss 783 case 0x2F: // comiss 784 case 0x54: // andps 785 case 0x55: // andnps 786 case 0x56: // orps 787 case 0x57: // xorps 788 case 0x58: // addpd 789 case 0x59: // mulpd 790 case 0x6E: // movd 791 case 0x7E: // movd 792 case 0x6F: // movdq 793 case 0x7F: // movdq 794 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 795 case 0xFE: // paddd 796 debug_only(has_disp32 = true); 797 break; 798 799 case 0xAD: // shrd r, a, %cl 800 case 0xAF: // imul r, a 801 case 0xBE: // movsbl r, a (movsxb) 802 case 0xBF: // movswl r, a (movsxw) 803 case 0xB6: // movzbl r, a (movzxb) 804 case 0xB7: // movzwl r, a (movzxw) 805 case REP16(0x40): // cmovl cc, r, a 806 case 0xB0: // cmpxchgb 807 case 0xB1: // cmpxchg 808 case 0xC1: // xaddl 809 case 0xC7: // cmpxchg8 810 case REP16(0x90): // setcc a 811 debug_only(has_disp32 = true); 812 // fall out of the switch to decode the address 813 break; 814 815 case 0xC4: // pinsrw r, a, #8 816 debug_only(has_disp32 = true); 817 case 0xC5: // pextrw r, r, #8 818 tail_size = 1; // the imm8 819 break; 820 821 case 0xAC: // shrd r, a, #8 822 debug_only(has_disp32 = true); 823 tail_size = 1; // the imm8 824 break; 825 826 case REP16(0x80): // jcc rdisp32 827 if (which == end_pc_operand) return ip + 4; 828 assert(which == call32_operand, "jcc has no disp32 or imm"); 829 return ip; 830 default: 831 ShouldNotReachHere(); 832 } 833 break; 834 835 case 0x81: // addl a, #32; addl r, #32 836 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 837 // on 32bit in the case of cmpl, the imm might be an oop 838 tail_size = 4; 839 debug_only(has_disp32 = true); // has both kinds of operands! 840 break; 841 842 case 0x83: // addl a, #8; addl r, #8 843 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 844 debug_only(has_disp32 = true); // has both kinds of operands! 845 tail_size = 1; 846 break; 847 848 case 0x9B: 849 switch (0xFF & *ip++) { 850 case 0xD9: // fnstcw a 851 debug_only(has_disp32 = true); 852 break; 853 default: 854 ShouldNotReachHere(); 855 } 856 break; 857 858 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 859 case REP4(0x10): // adc... 860 case REP4(0x20): // and... 861 case REP4(0x30): // xor... 862 case REP4(0x08): // or... 863 case REP4(0x18): // sbb... 864 case REP4(0x28): // sub... 865 case 0xF7: // mull a 866 case 0x8D: // lea r, a 867 case 0x87: // xchg r, a 868 case REP4(0x38): // cmp... 869 case 0x85: // test r, a 870 debug_only(has_disp32 = true); // has both kinds of operands! 871 break; 872 873 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 874 case 0xC6: // movb a, #8 875 case 0x80: // cmpb a, #8 876 case 0x6B: // imul r, a, #8 877 debug_only(has_disp32 = true); // has both kinds of operands! 878 tail_size = 1; // the imm8 879 break; 880 881 case 0xC4: // VEX_3bytes 882 case 0xC5: // VEX_2bytes 883 assert((UseAVX > 0), "shouldn't have VEX prefix"); 884 assert(ip == inst+1, "no prefixes allowed"); 885 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 886 // but they have prefix 0x0F and processed when 0x0F processed above. 887 // 888 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 889 // instructions (these instructions are not supported in 64-bit mode). 890 // To distinguish them bits [7:6] are set in the VEX second byte since 891 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 892 // those VEX bits REX and vvvv bits are inverted. 893 // 894 // Fortunately C2 doesn't generate these instructions so we don't need 895 // to check for them in product version. 896 897 // Check second byte 898 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 899 900 int vex_opcode; 901 // First byte 902 if ((0xFF & *inst) == VEX_3bytes) { 903 vex_opcode = VEX_OPCODE_MASK & *ip; 904 ip++; // third byte 905 is_64bit = ((VEX_W & *ip) == VEX_W); 906 } else { 907 vex_opcode = VEX_OPCODE_0F; 908 } 909 ip++; // opcode 910 // To find the end of instruction (which == end_pc_operand). 911 switch (vex_opcode) { 912 case VEX_OPCODE_0F: 913 switch (0xFF & *ip) { 914 case 0x70: // pshufd r, r/a, #8 915 case 0x71: // ps[rl|ra|ll]w r, #8 916 case 0x72: // ps[rl|ra|ll]d r, #8 917 case 0x73: // ps[rl|ra|ll]q r, #8 918 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 919 case 0xC4: // pinsrw r, r, r/a, #8 920 case 0xC5: // pextrw r/a, r, #8 921 case 0xC6: // shufp[s|d] r, r, r/a, #8 922 tail_size = 1; // the imm8 923 break; 924 } 925 break; 926 case VEX_OPCODE_0F_3A: 927 tail_size = 1; 928 break; 929 } 930 ip++; // skip opcode 931 debug_only(has_disp32 = true); // has both kinds of operands! 932 break; 933 934 case 0x62: // EVEX_4bytes 935 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix"); 936 assert(ip == inst+1, "no prefixes allowed"); 937 // no EVEX collisions, all instructions that have 0x62 opcodes 938 // have EVEX versions and are subopcodes of 0x66 939 ip++; // skip P0 and exmaine W in P1 940 is_64bit = ((VEX_W & *ip) == VEX_W); 941 ip++; // move to P2 942 ip++; // skip P2, move to opcode 943 // To find the end of instruction (which == end_pc_operand). 944 switch (0xFF & *ip) { 945 case 0x22: // pinsrd r, r/a, #8 946 case 0x61: // pcmpestri r, r/a, #8 947 case 0x70: // pshufd r, r/a, #8 948 case 0x73: // psrldq r, #8 949 tail_size = 1; // the imm8 950 break; 951 default: 952 break; 953 } 954 ip++; // skip opcode 955 debug_only(has_disp32 = true); // has both kinds of operands! 956 break; 957 958 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 959 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 960 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 961 case 0xDD: // fld_d a; fst_d a; fstp_d a 962 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 963 case 0xDF: // fild_d a; fistp_d a 964 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 965 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 966 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 967 debug_only(has_disp32 = true); 968 break; 969 970 case 0xE8: // call rdisp32 971 case 0xE9: // jmp rdisp32 972 if (which == end_pc_operand) return ip + 4; 973 assert(which == call32_operand, "call has no disp32 or imm"); 974 return ip; 975 976 case 0xF0: // Lock 977 goto again_after_prefix; 978 979 case 0xF3: // For SSE 980 case 0xF2: // For SSE2 981 switch (0xFF & *ip++) { 982 case REX: 983 case REX_B: 984 case REX_X: 985 case REX_XB: 986 case REX_R: 987 case REX_RB: 988 case REX_RX: 989 case REX_RXB: 990 case REX_W: 991 case REX_WB: 992 case REX_WX: 993 case REX_WXB: 994 case REX_WR: 995 case REX_WRB: 996 case REX_WRX: 997 case REX_WRXB: 998 NOT_LP64(assert(false, "found 64bit prefix")); 999 ip++; 1000 default: 1001 ip++; 1002 } 1003 debug_only(has_disp32 = true); // has both kinds of operands! 1004 break; 1005 1006 default: 1007 ShouldNotReachHere(); 1008 1009 #undef REP8 1010 #undef REP16 1011 } 1012 1013 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 1014 #ifdef _LP64 1015 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 1016 #else 1017 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 1018 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 1019 #endif // LP64 1020 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 1021 1022 // parse the output of emit_operand 1023 int op2 = 0xFF & *ip++; 1024 int base = op2 & 0x07; 1025 int op3 = -1; 1026 const int b100 = 4; 1027 const int b101 = 5; 1028 if (base == b100 && (op2 >> 6) != 3) { 1029 op3 = 0xFF & *ip++; 1030 base = op3 & 0x07; // refetch the base 1031 } 1032 // now ip points at the disp (if any) 1033 1034 switch (op2 >> 6) { 1035 case 0: 1036 // [00 reg 100][ss index base] 1037 // [00 reg 100][00 100 esp] 1038 // [00 reg base] 1039 // [00 reg 100][ss index 101][disp32] 1040 // [00 reg 101] [disp32] 1041 1042 if (base == b101) { 1043 if (which == disp32_operand) 1044 return ip; // caller wants the disp32 1045 ip += 4; // skip the disp32 1046 } 1047 break; 1048 1049 case 1: 1050 // [01 reg 100][ss index base][disp8] 1051 // [01 reg 100][00 100 esp][disp8] 1052 // [01 reg base] [disp8] 1053 ip += 1; // skip the disp8 1054 break; 1055 1056 case 2: 1057 // [10 reg 100][ss index base][disp32] 1058 // [10 reg 100][00 100 esp][disp32] 1059 // [10 reg base] [disp32] 1060 if (which == disp32_operand) 1061 return ip; // caller wants the disp32 1062 ip += 4; // skip the disp32 1063 break; 1064 1065 case 3: 1066 // [11 reg base] (not a memory addressing mode) 1067 break; 1068 } 1069 1070 if (which == end_pc_operand) { 1071 return ip + tail_size; 1072 } 1073 1074 #ifdef _LP64 1075 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 1076 #else 1077 assert(which == imm_operand, "instruction has only an imm field"); 1078 #endif // LP64 1079 return ip; 1080 } 1081 1082 address Assembler::locate_next_instruction(address inst) { 1083 // Secretly share code with locate_operand: 1084 return locate_operand(inst, end_pc_operand); 1085 } 1086 1087 1088 #ifdef ASSERT 1089 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 1090 address inst = inst_mark(); 1091 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 1092 address opnd; 1093 1094 Relocation* r = rspec.reloc(); 1095 if (r->type() == relocInfo::none) { 1096 return; 1097 } else if (r->is_call() || format == call32_operand) { 1098 // assert(format == imm32_operand, "cannot specify a nonzero format"); 1099 opnd = locate_operand(inst, call32_operand); 1100 } else if (r->is_data()) { 1101 assert(format == imm_operand || format == disp32_operand 1102 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 1103 opnd = locate_operand(inst, (WhichOperand)format); 1104 } else { 1105 assert(format == imm_operand, "cannot specify a format"); 1106 return; 1107 } 1108 assert(opnd == pc(), "must put operand where relocs can find it"); 1109 } 1110 #endif // ASSERT 1111 1112 void Assembler::emit_operand32(Register reg, Address adr) { 1113 assert(reg->encoding() < 8, "no extended registers"); 1114 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1115 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1116 adr._rspec); 1117 } 1118 1119 void Assembler::emit_operand(Register reg, Address adr, 1120 int rip_relative_correction) { 1121 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1122 adr._rspec, 1123 rip_relative_correction); 1124 } 1125 1126 void Assembler::emit_operand(XMMRegister reg, Address adr) { 1127 if (adr.isxmmindex()) { 1128 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec); 1129 } else { 1130 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1131 adr._rspec); 1132 } 1133 } 1134 1135 // MMX operations 1136 void Assembler::emit_operand(MMXRegister reg, Address adr) { 1137 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1138 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1139 } 1140 1141 // work around gcc (3.2.1-7a) bug 1142 void Assembler::emit_operand(Address adr, MMXRegister reg) { 1143 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1144 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1145 } 1146 1147 1148 void Assembler::emit_farith(int b1, int b2, int i) { 1149 assert(isByte(b1) && isByte(b2), "wrong opcode"); 1150 assert(0 <= i && i < 8, "illegal stack offset"); 1151 emit_int8(b1); 1152 emit_int8(b2 + i); 1153 } 1154 1155 1156 // Now the Assembler instructions (identical for 32/64 bits) 1157 1158 void Assembler::adcl(Address dst, int32_t imm32) { 1159 InstructionMark im(this); 1160 prefix(dst); 1161 emit_arith_operand(0x81, rdx, dst, imm32); 1162 } 1163 1164 void Assembler::adcl(Address dst, Register src) { 1165 InstructionMark im(this); 1166 prefix(dst, src); 1167 emit_int8(0x11); 1168 emit_operand(src, dst); 1169 } 1170 1171 void Assembler::adcl(Register dst, int32_t imm32) { 1172 prefix(dst); 1173 emit_arith(0x81, 0xD0, dst, imm32); 1174 } 1175 1176 void Assembler::adcl(Register dst, Address src) { 1177 InstructionMark im(this); 1178 prefix(src, dst); 1179 emit_int8(0x13); 1180 emit_operand(dst, src); 1181 } 1182 1183 void Assembler::adcl(Register dst, Register src) { 1184 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1185 emit_arith(0x13, 0xC0, dst, src); 1186 } 1187 1188 void Assembler::addl(Address dst, int32_t imm32) { 1189 InstructionMark im(this); 1190 prefix(dst); 1191 emit_arith_operand(0x81, rax, dst, imm32); 1192 } 1193 1194 void Assembler::addb(Address dst, int imm8) { 1195 InstructionMark im(this); 1196 prefix(dst); 1197 emit_int8((unsigned char)0x80); 1198 emit_operand(rax, dst, 1); 1199 emit_int8(imm8); 1200 } 1201 1202 void Assembler::addw(Address dst, int imm16) { 1203 InstructionMark im(this); 1204 emit_int8(0x66); 1205 prefix(dst); 1206 emit_int8((unsigned char)0x81); 1207 emit_operand(rax, dst, 2); 1208 emit_int16(imm16); 1209 } 1210 1211 void Assembler::addl(Address dst, Register src) { 1212 InstructionMark im(this); 1213 prefix(dst, src); 1214 emit_int8(0x01); 1215 emit_operand(src, dst); 1216 } 1217 1218 void Assembler::addl(Register dst, int32_t imm32) { 1219 prefix(dst); 1220 emit_arith(0x81, 0xC0, dst, imm32); 1221 } 1222 1223 void Assembler::addl(Register dst, Address src) { 1224 InstructionMark im(this); 1225 prefix(src, dst); 1226 emit_int8(0x03); 1227 emit_operand(dst, src); 1228 } 1229 1230 void Assembler::addl(Register dst, Register src) { 1231 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1232 emit_arith(0x03, 0xC0, dst, src); 1233 } 1234 1235 void Assembler::addr_nop_4() { 1236 assert(UseAddressNop, "no CPU support"); 1237 // 4 bytes: NOP DWORD PTR [EAX+0] 1238 emit_int8(0x0F); 1239 emit_int8(0x1F); 1240 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 1241 emit_int8(0); // 8-bits offset (1 byte) 1242 } 1243 1244 void Assembler::addr_nop_5() { 1245 assert(UseAddressNop, "no CPU support"); 1246 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 1247 emit_int8(0x0F); 1248 emit_int8(0x1F); 1249 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 1250 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1251 emit_int8(0); // 8-bits offset (1 byte) 1252 } 1253 1254 void Assembler::addr_nop_7() { 1255 assert(UseAddressNop, "no CPU support"); 1256 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 1257 emit_int8(0x0F); 1258 emit_int8(0x1F); 1259 emit_int8((unsigned char)0x80); 1260 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 1261 emit_int32(0); // 32-bits offset (4 bytes) 1262 } 1263 1264 void Assembler::addr_nop_8() { 1265 assert(UseAddressNop, "no CPU support"); 1266 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 1267 emit_int8(0x0F); 1268 emit_int8(0x1F); 1269 emit_int8((unsigned char)0x84); 1270 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 1271 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1272 emit_int32(0); // 32-bits offset (4 bytes) 1273 } 1274 1275 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 1276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1277 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1278 attributes.set_rex_vex_w_reverted(); 1279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1280 emit_int8(0x58); 1281 emit_int8((unsigned char)(0xC0 | encode)); 1282 } 1283 1284 void Assembler::addsd(XMMRegister dst, Address src) { 1285 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1286 InstructionMark im(this); 1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1288 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1289 attributes.set_rex_vex_w_reverted(); 1290 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1291 emit_int8(0x58); 1292 emit_operand(dst, src); 1293 } 1294 1295 void Assembler::addss(XMMRegister dst, XMMRegister src) { 1296 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1299 emit_int8(0x58); 1300 emit_int8((unsigned char)(0xC0 | encode)); 1301 } 1302 1303 void Assembler::addss(XMMRegister dst, Address src) { 1304 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1305 InstructionMark im(this); 1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1307 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1308 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1309 emit_int8(0x58); 1310 emit_operand(dst, src); 1311 } 1312 1313 void Assembler::aesdec(XMMRegister dst, Address src) { 1314 assert(VM_Version::supports_aes(), ""); 1315 InstructionMark im(this); 1316 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1317 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1318 emit_int8((unsigned char)0xDE); 1319 emit_operand(dst, src); 1320 } 1321 1322 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { 1323 assert(VM_Version::supports_aes(), ""); 1324 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1325 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1326 emit_int8((unsigned char)0xDE); 1327 emit_int8(0xC0 | encode); 1328 } 1329 1330 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1331 assert(VM_Version::supports_vaes(), ""); 1332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1333 attributes.set_is_evex_instruction(); 1334 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1335 emit_int8((unsigned char)0xDE); 1336 emit_int8((unsigned char)(0xC0 | encode)); 1337 } 1338 1339 1340 void Assembler::aesdeclast(XMMRegister dst, Address src) { 1341 assert(VM_Version::supports_aes(), ""); 1342 InstructionMark im(this); 1343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1344 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1345 emit_int8((unsigned char)0xDF); 1346 emit_operand(dst, src); 1347 } 1348 1349 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { 1350 assert(VM_Version::supports_aes(), ""); 1351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1352 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1353 emit_int8((unsigned char)0xDF); 1354 emit_int8((unsigned char)(0xC0 | encode)); 1355 } 1356 1357 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1358 assert(VM_Version::supports_vaes(), ""); 1359 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1360 attributes.set_is_evex_instruction(); 1361 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1362 emit_int8((unsigned char)0xDF); 1363 emit_int8((unsigned char)(0xC0 | encode)); 1364 } 1365 1366 void Assembler::aesenc(XMMRegister dst, Address src) { 1367 assert(VM_Version::supports_aes(), ""); 1368 InstructionMark im(this); 1369 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1370 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1371 emit_int8((unsigned char)0xDC); 1372 emit_operand(dst, src); 1373 } 1374 1375 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { 1376 assert(VM_Version::supports_aes(), ""); 1377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1378 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1379 emit_int8((unsigned char)0xDC); 1380 emit_int8(0xC0 | encode); 1381 } 1382 1383 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1384 assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); 1385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1386 attributes.set_is_evex_instruction(); 1387 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1388 emit_int8((unsigned char)0xDC); 1389 emit_int8((unsigned char)(0xC0 | encode)); 1390 } 1391 1392 void Assembler::aesenclast(XMMRegister dst, Address src) { 1393 assert(VM_Version::supports_aes(), ""); 1394 InstructionMark im(this); 1395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1396 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1397 emit_int8((unsigned char)0xDD); 1398 emit_operand(dst, src); 1399 } 1400 1401 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { 1402 assert(VM_Version::supports_aes(), ""); 1403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1404 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1405 emit_int8((unsigned char)0xDD); 1406 emit_int8((unsigned char)(0xC0 | encode)); 1407 } 1408 1409 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1410 assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); 1411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1412 attributes.set_is_evex_instruction(); 1413 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1414 emit_int8((unsigned char)0xDD); 1415 emit_int8((unsigned char)(0xC0 | encode)); 1416 } 1417 1418 void Assembler::andl(Address dst, int32_t imm32) { 1419 InstructionMark im(this); 1420 prefix(dst); 1421 emit_int8((unsigned char)0x81); 1422 emit_operand(rsp, dst, 4); 1423 emit_int32(imm32); 1424 } 1425 1426 void Assembler::andl(Register dst, int32_t imm32) { 1427 prefix(dst); 1428 emit_arith(0x81, 0xE0, dst, imm32); 1429 } 1430 1431 void Assembler::andl(Register dst, Address src) { 1432 InstructionMark im(this); 1433 prefix(src, dst); 1434 emit_int8(0x23); 1435 emit_operand(dst, src); 1436 } 1437 1438 void Assembler::andl(Register dst, Register src) { 1439 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1440 emit_arith(0x23, 0xC0, dst, src); 1441 } 1442 1443 void Assembler::andnl(Register dst, Register src1, Register src2) { 1444 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1446 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1447 emit_int8((unsigned char)0xF2); 1448 emit_int8((unsigned char)(0xC0 | encode)); 1449 } 1450 1451 void Assembler::andnl(Register dst, Register src1, Address src2) { 1452 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1453 InstructionMark im(this); 1454 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1455 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1456 emit_int8((unsigned char)0xF2); 1457 emit_operand(dst, src2); 1458 } 1459 1460 void Assembler::bsfl(Register dst, Register src) { 1461 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1462 emit_int8(0x0F); 1463 emit_int8((unsigned char)0xBC); 1464 emit_int8((unsigned char)(0xC0 | encode)); 1465 } 1466 1467 void Assembler::bsrl(Register dst, Register src) { 1468 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1469 emit_int8(0x0F); 1470 emit_int8((unsigned char)0xBD); 1471 emit_int8((unsigned char)(0xC0 | encode)); 1472 } 1473 1474 void Assembler::bswapl(Register reg) { // bswap 1475 int encode = prefix_and_encode(reg->encoding()); 1476 emit_int8(0x0F); 1477 emit_int8((unsigned char)(0xC8 | encode)); 1478 } 1479 1480 void Assembler::blsil(Register dst, Register src) { 1481 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1482 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1483 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1484 emit_int8((unsigned char)0xF3); 1485 emit_int8((unsigned char)(0xC0 | encode)); 1486 } 1487 1488 void Assembler::blsil(Register dst, Address src) { 1489 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1490 InstructionMark im(this); 1491 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1492 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1493 emit_int8((unsigned char)0xF3); 1494 emit_operand(rbx, src); 1495 } 1496 1497 void Assembler::blsmskl(Register dst, Register src) { 1498 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1499 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1500 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1501 emit_int8((unsigned char)0xF3); 1502 emit_int8((unsigned char)(0xC0 | encode)); 1503 } 1504 1505 void Assembler::blsmskl(Register dst, Address src) { 1506 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1507 InstructionMark im(this); 1508 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1509 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1510 emit_int8((unsigned char)0xF3); 1511 emit_operand(rdx, src); 1512 } 1513 1514 void Assembler::blsrl(Register dst, Register src) { 1515 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1516 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1517 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1518 emit_int8((unsigned char)0xF3); 1519 emit_int8((unsigned char)(0xC0 | encode)); 1520 } 1521 1522 void Assembler::blsrl(Register dst, Address src) { 1523 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1524 InstructionMark im(this); 1525 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 1526 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1527 emit_int8((unsigned char)0xF3); 1528 emit_operand(rcx, src); 1529 } 1530 1531 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1532 // suspect disp32 is always good 1533 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1534 1535 if (L.is_bound()) { 1536 const int long_size = 5; 1537 int offs = (int)( target(L) - pc() ); 1538 assert(offs <= 0, "assembler error"); 1539 InstructionMark im(this); 1540 // 1110 1000 #32-bit disp 1541 emit_int8((unsigned char)0xE8); 1542 emit_data(offs - long_size, rtype, operand); 1543 } else { 1544 InstructionMark im(this); 1545 // 1110 1000 #32-bit disp 1546 L.add_patch_at(code(), locator()); 1547 1548 emit_int8((unsigned char)0xE8); 1549 emit_data(int(0), rtype, operand); 1550 } 1551 } 1552 1553 void Assembler::call(Register dst) { 1554 int encode = prefix_and_encode(dst->encoding()); 1555 emit_int8((unsigned char)0xFF); 1556 emit_int8((unsigned char)(0xD0 | encode)); 1557 } 1558 1559 1560 void Assembler::call(Address adr) { 1561 InstructionMark im(this); 1562 prefix(adr); 1563 emit_int8((unsigned char)0xFF); 1564 emit_operand(rdx, adr); 1565 } 1566 1567 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1568 InstructionMark im(this); 1569 emit_int8((unsigned char)0xE8); 1570 intptr_t disp = entry - (pc() + sizeof(int32_t)); 1571 // Entry is NULL in case of a scratch emit. 1572 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp); 1573 // Technically, should use call32_operand, but this format is 1574 // implied by the fact that we're emitting a call instruction. 1575 1576 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1577 emit_data((int) disp, rspec, operand); 1578 } 1579 1580 void Assembler::cdql() { 1581 emit_int8((unsigned char)0x99); 1582 } 1583 1584 void Assembler::cld() { 1585 emit_int8((unsigned char)0xFC); 1586 } 1587 1588 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1589 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1590 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1591 emit_int8(0x0F); 1592 emit_int8(0x40 | cc); 1593 emit_int8((unsigned char)(0xC0 | encode)); 1594 } 1595 1596 1597 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1598 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1599 prefix(src, dst); 1600 emit_int8(0x0F); 1601 emit_int8(0x40 | cc); 1602 emit_operand(dst, src); 1603 } 1604 1605 void Assembler::cmpb(Address dst, int imm8) { 1606 InstructionMark im(this); 1607 prefix(dst); 1608 emit_int8((unsigned char)0x80); 1609 emit_operand(rdi, dst, 1); 1610 emit_int8(imm8); 1611 } 1612 1613 void Assembler::cmpl(Address dst, int32_t imm32) { 1614 InstructionMark im(this); 1615 prefix(dst); 1616 emit_int8((unsigned char)0x81); 1617 emit_operand(rdi, dst, 4); 1618 emit_int32(imm32); 1619 } 1620 1621 void Assembler::cmpl(Register dst, int32_t imm32) { 1622 prefix(dst); 1623 emit_arith(0x81, 0xF8, dst, imm32); 1624 } 1625 1626 void Assembler::cmpl(Register dst, Register src) { 1627 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1628 emit_arith(0x3B, 0xC0, dst, src); 1629 } 1630 1631 void Assembler::cmpl(Register dst, Address src) { 1632 InstructionMark im(this); 1633 prefix(src, dst); 1634 emit_int8((unsigned char)0x3B); 1635 emit_operand(dst, src); 1636 } 1637 1638 void Assembler::cmpw(Address dst, int imm16) { 1639 InstructionMark im(this); 1640 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1641 emit_int8(0x66); 1642 emit_int8((unsigned char)0x81); 1643 emit_operand(rdi, dst, 2); 1644 emit_int16(imm16); 1645 } 1646 1647 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1648 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1649 // The ZF is set if the compared values were equal, and cleared otherwise. 1650 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1651 InstructionMark im(this); 1652 prefix(adr, reg); 1653 emit_int8(0x0F); 1654 emit_int8((unsigned char)0xB1); 1655 emit_operand(reg, adr); 1656 } 1657 1658 // The 8-bit cmpxchg compares the value at adr with the contents of rax, 1659 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1660 // The ZF is set if the compared values were equal, and cleared otherwise. 1661 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg 1662 InstructionMark im(this); 1663 prefix(adr, reg, true); 1664 emit_int8(0x0F); 1665 emit_int8((unsigned char)0xB0); 1666 emit_operand(reg, adr); 1667 } 1668 1669 void Assembler::comisd(XMMRegister dst, Address src) { 1670 // NOTE: dbx seems to decode this as comiss even though the 1671 // 0x66 is there. Strangly ucomisd comes out correct 1672 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1673 InstructionMark im(this); 1674 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);; 1675 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1676 attributes.set_rex_vex_w_reverted(); 1677 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1678 emit_int8(0x2F); 1679 emit_operand(dst, src); 1680 } 1681 1682 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1683 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1684 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1685 attributes.set_rex_vex_w_reverted(); 1686 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1687 emit_int8(0x2F); 1688 emit_int8((unsigned char)(0xC0 | encode)); 1689 } 1690 1691 void Assembler::comiss(XMMRegister dst, Address src) { 1692 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1693 InstructionMark im(this); 1694 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1695 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1696 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1697 emit_int8(0x2F); 1698 emit_operand(dst, src); 1699 } 1700 1701 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1702 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1704 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1705 emit_int8(0x2F); 1706 emit_int8((unsigned char)(0xC0 | encode)); 1707 } 1708 1709 void Assembler::cpuid() { 1710 emit_int8(0x0F); 1711 emit_int8((unsigned char)0xA2); 1712 } 1713 1714 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented 1715 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v 1716 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. - 1717 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. - 1718 // 1719 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v 1720 // 1721 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v 1722 // 1723 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v 1724 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { 1725 assert(VM_Version::supports_sse4_2(), ""); 1726 int8_t w = 0x01; 1727 Prefix p = Prefix_EMPTY; 1728 1729 emit_int8((int8_t)0xF2); 1730 switch (sizeInBytes) { 1731 case 1: 1732 w = 0; 1733 break; 1734 case 2: 1735 case 4: 1736 break; 1737 LP64_ONLY(case 8:) 1738 // This instruction is not valid in 32 bits 1739 // Note: 1740 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf 1741 // 1742 // Page B - 72 Vol. 2C says 1743 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2 1744 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m 1745 // F0!!! 1746 // while 3 - 208 Vol. 2A 1747 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64. 1748 // 1749 // the 0 on a last bit is reserved for a different flavor of this instruction : 1750 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8. 1751 p = REX_W; 1752 break; 1753 default: 1754 assert(0, "Unsupported value for a sizeInBytes argument"); 1755 break; 1756 } 1757 LP64_ONLY(prefix(crc, v, p);) 1758 emit_int8((int8_t)0x0F); 1759 emit_int8(0x38); 1760 emit_int8((int8_t)(0xF0 | w)); 1761 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7)); 1762 } 1763 1764 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { 1765 assert(VM_Version::supports_sse4_2(), ""); 1766 InstructionMark im(this); 1767 int8_t w = 0x01; 1768 Prefix p = Prefix_EMPTY; 1769 1770 emit_int8((int8_t)0xF2); 1771 switch (sizeInBytes) { 1772 case 1: 1773 w = 0; 1774 break; 1775 case 2: 1776 case 4: 1777 break; 1778 LP64_ONLY(case 8:) 1779 // This instruction is not valid in 32 bits 1780 p = REX_W; 1781 break; 1782 default: 1783 assert(0, "Unsupported value for a sizeInBytes argument"); 1784 break; 1785 } 1786 LP64_ONLY(prefix(crc, adr, p);) 1787 emit_int8((int8_t)0x0F); 1788 emit_int8(0x38); 1789 emit_int8((int8_t)(0xF0 | w)); 1790 emit_operand(crc, adr); 1791 } 1792 1793 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1794 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1796 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1797 emit_int8((unsigned char)0xE6); 1798 emit_int8((unsigned char)(0xC0 | encode)); 1799 } 1800 1801 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1802 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1804 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1805 emit_int8(0x5B); 1806 emit_int8((unsigned char)(0xC0 | encode)); 1807 } 1808 1809 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1810 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1812 attributes.set_rex_vex_w_reverted(); 1813 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1814 emit_int8(0x5A); 1815 emit_int8((unsigned char)(0xC0 | encode)); 1816 } 1817 1818 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1819 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1820 InstructionMark im(this); 1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1822 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1823 attributes.set_rex_vex_w_reverted(); 1824 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1825 emit_int8(0x5A); 1826 emit_operand(dst, src); 1827 } 1828 1829 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1830 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1831 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1832 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1833 emit_int8(0x2A); 1834 emit_int8((unsigned char)(0xC0 | encode)); 1835 } 1836 1837 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1839 InstructionMark im(this); 1840 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1841 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1842 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1843 emit_int8(0x2A); 1844 emit_operand(dst, src); 1845 } 1846 1847 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1848 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1850 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1851 emit_int8(0x2A); 1852 emit_int8((unsigned char)(0xC0 | encode)); 1853 } 1854 1855 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1856 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1857 InstructionMark im(this); 1858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1859 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1860 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1861 emit_int8(0x2A); 1862 emit_operand(dst, src); 1863 } 1864 1865 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 1866 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1867 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1868 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1869 emit_int8(0x2A); 1870 emit_int8((unsigned char)(0xC0 | encode)); 1871 } 1872 1873 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1874 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1876 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1877 emit_int8(0x5A); 1878 emit_int8((unsigned char)(0xC0 | encode)); 1879 } 1880 1881 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1883 InstructionMark im(this); 1884 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1885 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1886 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1887 emit_int8(0x5A); 1888 emit_operand(dst, src); 1889 } 1890 1891 1892 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1893 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1894 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1895 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1896 emit_int8(0x2C); 1897 emit_int8((unsigned char)(0xC0 | encode)); 1898 } 1899 1900 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1901 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1903 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1904 emit_int8(0x2C); 1905 emit_int8((unsigned char)(0xC0 | encode)); 1906 } 1907 1908 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) { 1909 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1910 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 1911 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1912 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1913 emit_int8((unsigned char)0xE6); 1914 emit_int8((unsigned char)(0xC0 | encode)); 1915 } 1916 1917 void Assembler::pabsb(XMMRegister dst, XMMRegister src) { 1918 assert(VM_Version::supports_ssse3(), ""); 1919 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 1920 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1921 emit_int8(0x1C); 1922 emit_int8((unsigned char)(0xC0 | encode)); 1923 } 1924 1925 void Assembler::pabsw(XMMRegister dst, XMMRegister src) { 1926 assert(VM_Version::supports_ssse3(), ""); 1927 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 1928 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1929 emit_int8(0x1D); 1930 emit_int8((unsigned char)(0xC0 | encode)); 1931 } 1932 1933 void Assembler::pabsd(XMMRegister dst, XMMRegister src) { 1934 assert(VM_Version::supports_ssse3(), ""); 1935 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1936 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1937 emit_int8(0x1E); 1938 emit_int8((unsigned char)(0xC0 | encode)); 1939 } 1940 1941 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) { 1942 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 1943 vector_len == AVX_256bit? VM_Version::supports_avx2() : 1944 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); 1945 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 1946 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1947 emit_int8((unsigned char)0x1C); 1948 emit_int8((unsigned char)(0xC0 | encode)); 1949 } 1950 1951 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) { 1952 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 1953 vector_len == AVX_256bit? VM_Version::supports_avx2() : 1954 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); 1955 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 1956 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1957 emit_int8((unsigned char)0x1D); 1958 emit_int8((unsigned char)(0xC0 | encode)); 1959 } 1960 1961 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) { 1962 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 1963 vector_len == AVX_256bit? VM_Version::supports_avx2() : 1964 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, ""); 1965 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1966 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1967 emit_int8((unsigned char)0x1E); 1968 emit_int8((unsigned char)(0xC0 | encode)); 1969 } 1970 1971 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) { 1972 assert(UseAVX > 2, ""); 1973 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 1974 attributes.set_is_evex_instruction(); 1975 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1976 emit_int8((unsigned char)0x1F); 1977 emit_int8((unsigned char)(0xC0 | encode)); 1978 } 1979 1980 void Assembler::decl(Address dst) { 1981 // Don't use it directly. Use MacroAssembler::decrement() instead. 1982 InstructionMark im(this); 1983 prefix(dst); 1984 emit_int8((unsigned char)0xFF); 1985 emit_operand(rcx, dst); 1986 } 1987 1988 void Assembler::divsd(XMMRegister dst, Address src) { 1989 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1990 InstructionMark im(this); 1991 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1992 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1993 attributes.set_rex_vex_w_reverted(); 1994 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1995 emit_int8(0x5E); 1996 emit_operand(dst, src); 1997 } 1998 1999 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 2000 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2001 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2002 attributes.set_rex_vex_w_reverted(); 2003 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2004 emit_int8(0x5E); 2005 emit_int8((unsigned char)(0xC0 | encode)); 2006 } 2007 2008 void Assembler::divss(XMMRegister dst, Address src) { 2009 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2010 InstructionMark im(this); 2011 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2012 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2013 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2014 emit_int8(0x5E); 2015 emit_operand(dst, src); 2016 } 2017 2018 void Assembler::divss(XMMRegister dst, XMMRegister src) { 2019 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2021 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2022 emit_int8(0x5E); 2023 emit_int8((unsigned char)(0xC0 | encode)); 2024 } 2025 2026 void Assembler::emms() { 2027 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 2028 emit_int8(0x0F); 2029 emit_int8(0x77); 2030 } 2031 2032 void Assembler::hlt() { 2033 emit_int8((unsigned char)0xF4); 2034 } 2035 2036 void Assembler::idivl(Register src) { 2037 int encode = prefix_and_encode(src->encoding()); 2038 emit_int8((unsigned char)0xF7); 2039 emit_int8((unsigned char)(0xF8 | encode)); 2040 } 2041 2042 void Assembler::divl(Register src) { // Unsigned 2043 int encode = prefix_and_encode(src->encoding()); 2044 emit_int8((unsigned char)0xF7); 2045 emit_int8((unsigned char)(0xF0 | encode)); 2046 } 2047 2048 void Assembler::imull(Register src) { 2049 int encode = prefix_and_encode(src->encoding()); 2050 emit_int8((unsigned char)0xF7); 2051 emit_int8((unsigned char)(0xE8 | encode)); 2052 } 2053 2054 void Assembler::imull(Register dst, Register src) { 2055 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2056 emit_int8(0x0F); 2057 emit_int8((unsigned char)0xAF); 2058 emit_int8((unsigned char)(0xC0 | encode)); 2059 } 2060 2061 2062 void Assembler::imull(Register dst, Register src, int value) { 2063 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2064 if (is8bit(value)) { 2065 emit_int8(0x6B); 2066 emit_int8((unsigned char)(0xC0 | encode)); 2067 emit_int8(value & 0xFF); 2068 } else { 2069 emit_int8(0x69); 2070 emit_int8((unsigned char)(0xC0 | encode)); 2071 emit_int32(value); 2072 } 2073 } 2074 2075 void Assembler::imull(Register dst, Address src) { 2076 InstructionMark im(this); 2077 prefix(src, dst); 2078 emit_int8(0x0F); 2079 emit_int8((unsigned char) 0xAF); 2080 emit_operand(dst, src); 2081 } 2082 2083 2084 void Assembler::incl(Address dst) { 2085 // Don't use it directly. Use MacroAssembler::increment() instead. 2086 InstructionMark im(this); 2087 prefix(dst); 2088 emit_int8((unsigned char)0xFF); 2089 emit_operand(rax, dst); 2090 } 2091 2092 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 2093 InstructionMark im(this); 2094 assert((0 <= cc) && (cc < 16), "illegal cc"); 2095 if (L.is_bound()) { 2096 address dst = target(L); 2097 assert(dst != NULL, "jcc most probably wrong"); 2098 2099 const int short_size = 2; 2100 const int long_size = 6; 2101 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); 2102 if (maybe_short && is8bit(offs - short_size)) { 2103 // 0111 tttn #8-bit disp 2104 emit_int8(0x70 | cc); 2105 emit_int8((offs - short_size) & 0xFF); 2106 } else { 2107 // 0000 1111 1000 tttn #32-bit disp 2108 assert(is_simm32(offs - long_size), 2109 "must be 32bit offset (call4)"); 2110 emit_int8(0x0F); 2111 emit_int8((unsigned char)(0x80 | cc)); 2112 emit_int32(offs - long_size); 2113 } 2114 } else { 2115 // Note: could eliminate cond. jumps to this jump if condition 2116 // is the same however, seems to be rather unlikely case. 2117 // Note: use jccb() if label to be bound is very close to get 2118 // an 8-bit displacement 2119 L.add_patch_at(code(), locator()); 2120 emit_int8(0x0F); 2121 emit_int8((unsigned char)(0x80 | cc)); 2122 emit_int32(0); 2123 } 2124 } 2125 2126 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) { 2127 if (L.is_bound()) { 2128 const int short_size = 2; 2129 address entry = target(L); 2130 #ifdef ASSERT 2131 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2132 intptr_t delta = short_branch_delta(); 2133 if (delta != 0) { 2134 dist += (dist < 0 ? (-delta) :delta); 2135 } 2136 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line); 2137 #endif 2138 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); 2139 // 0111 tttn #8-bit disp 2140 emit_int8(0x70 | cc); 2141 emit_int8((offs - short_size) & 0xFF); 2142 } else { 2143 InstructionMark im(this); 2144 L.add_patch_at(code(), locator(), file, line); 2145 emit_int8(0x70 | cc); 2146 emit_int8(0); 2147 } 2148 } 2149 2150 void Assembler::jmp(Address adr) { 2151 InstructionMark im(this); 2152 prefix(adr); 2153 emit_int8((unsigned char)0xFF); 2154 emit_operand(rsp, adr); 2155 } 2156 2157 void Assembler::jmp(Label& L, bool maybe_short) { 2158 if (L.is_bound()) { 2159 address entry = target(L); 2160 assert(entry != NULL, "jmp most probably wrong"); 2161 InstructionMark im(this); 2162 const int short_size = 2; 2163 const int long_size = 5; 2164 intptr_t offs = entry - pc(); 2165 if (maybe_short && is8bit(offs - short_size)) { 2166 emit_int8((unsigned char)0xEB); 2167 emit_int8((offs - short_size) & 0xFF); 2168 } else { 2169 emit_int8((unsigned char)0xE9); 2170 emit_int32(offs - long_size); 2171 } 2172 } else { 2173 // By default, forward jumps are always 32-bit displacements, since 2174 // we can't yet know where the label will be bound. If you're sure that 2175 // the forward jump will not run beyond 256 bytes, use jmpb to 2176 // force an 8-bit displacement. 2177 InstructionMark im(this); 2178 L.add_patch_at(code(), locator()); 2179 emit_int8((unsigned char)0xE9); 2180 emit_int32(0); 2181 } 2182 } 2183 2184 void Assembler::jmp(Register entry) { 2185 int encode = prefix_and_encode(entry->encoding()); 2186 emit_int8((unsigned char)0xFF); 2187 emit_int8((unsigned char)(0xE0 | encode)); 2188 } 2189 2190 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 2191 InstructionMark im(this); 2192 emit_int8((unsigned char)0xE9); 2193 assert(dest != NULL, "must have a target"); 2194 intptr_t disp = dest - (pc() + sizeof(int32_t)); 2195 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 2196 emit_data(disp, rspec.reloc(), call32_operand); 2197 } 2198 2199 void Assembler::jmpb_0(Label& L, const char* file, int line) { 2200 if (L.is_bound()) { 2201 const int short_size = 2; 2202 address entry = target(L); 2203 assert(entry != NULL, "jmp most probably wrong"); 2204 #ifdef ASSERT 2205 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2206 intptr_t delta = short_branch_delta(); 2207 if (delta != 0) { 2208 dist += (dist < 0 ? (-delta) :delta); 2209 } 2210 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line); 2211 #endif 2212 intptr_t offs = entry - pc(); 2213 emit_int8((unsigned char)0xEB); 2214 emit_int8((offs - short_size) & 0xFF); 2215 } else { 2216 InstructionMark im(this); 2217 L.add_patch_at(code(), locator(), file, line); 2218 emit_int8((unsigned char)0xEB); 2219 emit_int8(0); 2220 } 2221 } 2222 2223 void Assembler::ldmxcsr( Address src) { 2224 if (UseAVX > 0 ) { 2225 InstructionMark im(this); 2226 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2227 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2228 emit_int8((unsigned char)0xAE); 2229 emit_operand(as_Register(2), src); 2230 } else { 2231 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2232 InstructionMark im(this); 2233 prefix(src); 2234 emit_int8(0x0F); 2235 emit_int8((unsigned char)0xAE); 2236 emit_operand(as_Register(2), src); 2237 } 2238 } 2239 2240 void Assembler::leal(Register dst, Address src) { 2241 InstructionMark im(this); 2242 #ifdef _LP64 2243 emit_int8(0x67); // addr32 2244 prefix(src, dst); 2245 #endif // LP64 2246 emit_int8((unsigned char)0x8D); 2247 emit_operand(dst, src); 2248 } 2249 2250 void Assembler::lfence() { 2251 emit_int8(0x0F); 2252 emit_int8((unsigned char)0xAE); 2253 emit_int8((unsigned char)0xE8); 2254 } 2255 2256 void Assembler::lock() { 2257 emit_int8((unsigned char)0xF0); 2258 } 2259 2260 void Assembler::lzcntl(Register dst, Register src) { 2261 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 2262 emit_int8((unsigned char)0xF3); 2263 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2264 emit_int8(0x0F); 2265 emit_int8((unsigned char)0xBD); 2266 emit_int8((unsigned char)(0xC0 | encode)); 2267 } 2268 2269 // Emit mfence instruction 2270 void Assembler::mfence() { 2271 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 2272 emit_int8(0x0F); 2273 emit_int8((unsigned char)0xAE); 2274 emit_int8((unsigned char)0xF0); 2275 } 2276 2277 // Emit sfence instruction 2278 void Assembler::sfence() { 2279 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 2280 emit_int8(0x0F); 2281 emit_int8((unsigned char)0xAE); 2282 emit_int8((unsigned char)0xF8); 2283 } 2284 2285 void Assembler::mov(Register dst, Register src) { 2286 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2287 } 2288 2289 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 2290 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2291 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2292 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2293 attributes.set_rex_vex_w_reverted(); 2294 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2295 emit_int8(0x28); 2296 emit_int8((unsigned char)(0xC0 | encode)); 2297 } 2298 2299 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 2300 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2301 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2302 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2303 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2304 emit_int8(0x28); 2305 emit_int8((unsigned char)(0xC0 | encode)); 2306 } 2307 2308 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { 2309 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2311 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2312 emit_int8(0x16); 2313 emit_int8((unsigned char)(0xC0 | encode)); 2314 } 2315 2316 void Assembler::movb(Register dst, Address src) { 2317 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2318 InstructionMark im(this); 2319 prefix(src, dst, true); 2320 emit_int8((unsigned char)0x8A); 2321 emit_operand(dst, src); 2322 } 2323 2324 void Assembler::movddup(XMMRegister dst, XMMRegister src) { 2325 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 2326 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2327 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2328 attributes.set_rex_vex_w_reverted(); 2329 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2330 emit_int8(0x12); 2331 emit_int8(0xC0 | encode); 2332 } 2333 2334 void Assembler::kmovbl(KRegister dst, Register src) { 2335 assert(VM_Version::supports_avx512dq(), ""); 2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2337 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2338 emit_int8((unsigned char)0x92); 2339 emit_int8((unsigned char)(0xC0 | encode)); 2340 } 2341 2342 void Assembler::kmovbl(Register dst, KRegister src) { 2343 assert(VM_Version::supports_avx512dq(), ""); 2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2345 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2346 emit_int8((unsigned char)0x93); 2347 emit_int8((unsigned char)(0xC0 | encode)); 2348 } 2349 2350 void Assembler::kmovwl(KRegister dst, Register src) { 2351 assert(VM_Version::supports_evex(), ""); 2352 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2353 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2354 emit_int8((unsigned char)0x92); 2355 emit_int8((unsigned char)(0xC0 | encode)); 2356 } 2357 2358 void Assembler::kmovwl(Register dst, KRegister src) { 2359 assert(VM_Version::supports_evex(), ""); 2360 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2361 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2362 emit_int8((unsigned char)0x93); 2363 emit_int8((unsigned char)(0xC0 | encode)); 2364 } 2365 2366 void Assembler::kmovwl(KRegister dst, Address src) { 2367 assert(VM_Version::supports_evex(), ""); 2368 InstructionMark im(this); 2369 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2370 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2371 emit_int8((unsigned char)0x90); 2372 emit_operand((Register)dst, src); 2373 } 2374 2375 void Assembler::kmovdl(KRegister dst, Register src) { 2376 assert(VM_Version::supports_avx512bw(), ""); 2377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2378 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2379 emit_int8((unsigned char)0x92); 2380 emit_int8((unsigned char)(0xC0 | encode)); 2381 } 2382 2383 void Assembler::kmovdl(Register dst, KRegister src) { 2384 assert(VM_Version::supports_avx512bw(), ""); 2385 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2387 emit_int8((unsigned char)0x93); 2388 emit_int8((unsigned char)(0xC0 | encode)); 2389 } 2390 2391 void Assembler::kmovql(KRegister dst, KRegister src) { 2392 assert(VM_Version::supports_avx512bw(), ""); 2393 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2394 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2395 emit_int8((unsigned char)0x90); 2396 emit_int8((unsigned char)(0xC0 | encode)); 2397 } 2398 2399 void Assembler::kmovql(KRegister dst, Address src) { 2400 assert(VM_Version::supports_avx512bw(), ""); 2401 InstructionMark im(this); 2402 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2403 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2404 emit_int8((unsigned char)0x90); 2405 emit_operand((Register)dst, src); 2406 } 2407 2408 void Assembler::kmovql(Address dst, KRegister src) { 2409 assert(VM_Version::supports_avx512bw(), ""); 2410 InstructionMark im(this); 2411 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2412 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2413 emit_int8((unsigned char)0x90); 2414 emit_operand((Register)src, dst); 2415 } 2416 2417 void Assembler::kmovql(KRegister dst, Register src) { 2418 assert(VM_Version::supports_avx512bw(), ""); 2419 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2420 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2421 emit_int8((unsigned char)0x92); 2422 emit_int8((unsigned char)(0xC0 | encode)); 2423 } 2424 2425 void Assembler::kmovql(Register dst, KRegister src) { 2426 assert(VM_Version::supports_avx512bw(), ""); 2427 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2428 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2429 emit_int8((unsigned char)0x93); 2430 emit_int8((unsigned char)(0xC0 | encode)); 2431 } 2432 2433 void Assembler::knotwl(KRegister dst, KRegister src) { 2434 assert(VM_Version::supports_evex(), ""); 2435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2436 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2437 emit_int8((unsigned char)0x44); 2438 emit_int8((unsigned char)(0xC0 | encode)); 2439 } 2440 2441 // This instruction produces ZF or CF flags 2442 void Assembler::kortestbl(KRegister src1, KRegister src2) { 2443 assert(VM_Version::supports_avx512dq(), ""); 2444 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2445 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2446 emit_int8((unsigned char)0x98); 2447 emit_int8((unsigned char)(0xC0 | encode)); 2448 } 2449 2450 // This instruction produces ZF or CF flags 2451 void Assembler::kortestwl(KRegister src1, KRegister src2) { 2452 assert(VM_Version::supports_evex(), ""); 2453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2454 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2455 emit_int8((unsigned char)0x98); 2456 emit_int8((unsigned char)(0xC0 | encode)); 2457 } 2458 2459 // This instruction produces ZF or CF flags 2460 void Assembler::kortestdl(KRegister src1, KRegister src2) { 2461 assert(VM_Version::supports_avx512bw(), ""); 2462 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2463 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2464 emit_int8((unsigned char)0x98); 2465 emit_int8((unsigned char)(0xC0 | encode)); 2466 } 2467 2468 // This instruction produces ZF or CF flags 2469 void Assembler::kortestql(KRegister src1, KRegister src2) { 2470 assert(VM_Version::supports_avx512bw(), ""); 2471 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2472 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2473 emit_int8((unsigned char)0x98); 2474 emit_int8((unsigned char)(0xC0 | encode)); 2475 } 2476 2477 // This instruction produces ZF or CF flags 2478 void Assembler::ktestql(KRegister src1, KRegister src2) { 2479 assert(VM_Version::supports_avx512bw(), ""); 2480 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2481 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2482 emit_int8((unsigned char)0x99); 2483 emit_int8((unsigned char)(0xC0 | encode)); 2484 } 2485 2486 void Assembler::ktestq(KRegister src1, KRegister src2) { 2487 assert(VM_Version::supports_avx512bw(), ""); 2488 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2489 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2490 emit_int8((unsigned char)0x99); 2491 emit_int8((unsigned char)(0xC0 | encode)); 2492 } 2493 2494 void Assembler::ktestd(KRegister src1, KRegister src2) { 2495 assert(VM_Version::supports_avx512bw(), ""); 2496 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2497 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2498 emit_int8((unsigned char)0x99); 2499 emit_int8((unsigned char)(0xC0 | encode)); 2500 } 2501 2502 void Assembler::movb(Address dst, int imm8) { 2503 InstructionMark im(this); 2504 prefix(dst); 2505 emit_int8((unsigned char)0xC6); 2506 emit_operand(rax, dst, 1); 2507 emit_int8(imm8); 2508 } 2509 2510 2511 void Assembler::movb(Address dst, Register src) { 2512 assert(src->has_byte_register(), "must have byte register"); 2513 InstructionMark im(this); 2514 prefix(dst, src, true); 2515 emit_int8((unsigned char)0x88); 2516 emit_operand(src, dst); 2517 } 2518 2519 void Assembler::movdl(XMMRegister dst, Register src) { 2520 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2521 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2522 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2523 emit_int8(0x6E); 2524 emit_int8((unsigned char)(0xC0 | encode)); 2525 } 2526 2527 void Assembler::movdl(Register dst, XMMRegister src) { 2528 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2529 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2530 // swap src/dst to get correct prefix 2531 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2532 emit_int8(0x7E); 2533 emit_int8((unsigned char)(0xC0 | encode)); 2534 } 2535 2536 void Assembler::movdl(XMMRegister dst, Address src) { 2537 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2538 InstructionMark im(this); 2539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2540 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2541 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2542 emit_int8(0x6E); 2543 emit_operand(dst, src); 2544 } 2545 2546 void Assembler::movdl(Address dst, XMMRegister src) { 2547 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2548 InstructionMark im(this); 2549 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2550 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2551 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2552 emit_int8(0x7E); 2553 emit_operand(src, dst); 2554 } 2555 2556 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 2557 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2558 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2559 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2560 emit_int8(0x6F); 2561 emit_int8((unsigned char)(0xC0 | encode)); 2562 } 2563 2564 void Assembler::movdqa(XMMRegister dst, Address src) { 2565 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2566 InstructionMark im(this); 2567 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2568 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2569 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2570 emit_int8(0x6F); 2571 emit_operand(dst, src); 2572 } 2573 2574 void Assembler::movdqu(XMMRegister dst, Address src) { 2575 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2576 InstructionMark im(this); 2577 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2578 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2579 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2580 emit_int8(0x6F); 2581 emit_operand(dst, src); 2582 } 2583 2584 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 2585 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2586 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2587 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2588 emit_int8(0x6F); 2589 emit_int8((unsigned char)(0xC0 | encode)); 2590 } 2591 2592 void Assembler::movdqu(Address dst, XMMRegister src) { 2593 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2594 InstructionMark im(this); 2595 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2597 attributes.reset_is_clear_context(); 2598 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2599 emit_int8(0x7F); 2600 emit_operand(src, dst); 2601 } 2602 2603 // Move Unaligned 256bit Vector 2604 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2605 assert(UseAVX > 0, ""); 2606 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2607 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2608 emit_int8(0x6F); 2609 emit_int8((unsigned char)(0xC0 | encode)); 2610 } 2611 2612 void Assembler::vmovdqu(XMMRegister dst, Address src) { 2613 assert(UseAVX > 0, ""); 2614 InstructionMark im(this); 2615 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2616 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2617 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2618 emit_int8(0x6F); 2619 emit_operand(dst, src); 2620 } 2621 2622 void Assembler::vmovdqu(Address dst, XMMRegister src) { 2623 assert(UseAVX > 0, ""); 2624 InstructionMark im(this); 2625 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2626 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2627 attributes.reset_is_clear_context(); 2628 // swap src<->dst for encoding 2629 assert(src != xnoreg, "sanity"); 2630 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2631 emit_int8(0x7F); 2632 emit_operand(src, dst); 2633 } 2634 2635 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) 2636 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { 2637 assert(VM_Version::supports_evex(), ""); 2638 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2639 attributes.set_is_evex_instruction(); 2640 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2641 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2642 emit_int8(0x6F); 2643 emit_int8((unsigned char)(0xC0 | encode)); 2644 } 2645 2646 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) { 2647 assert(VM_Version::supports_evex(), ""); 2648 InstructionMark im(this); 2649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2650 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2651 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2652 attributes.set_is_evex_instruction(); 2653 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2654 emit_int8(0x6F); 2655 emit_operand(dst, src); 2656 } 2657 2658 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) { 2659 assert(VM_Version::supports_evex(), ""); 2660 assert(src != xnoreg, "sanity"); 2661 InstructionMark im(this); 2662 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2663 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2664 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2665 attributes.set_is_evex_instruction(); 2666 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2667 emit_int8(0x7F); 2668 emit_operand(src, dst); 2669 } 2670 2671 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2672 assert(VM_Version::supports_avx512vlbw(), ""); 2673 InstructionMark im(this); 2674 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2675 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2676 attributes.set_embedded_opmask_register_specifier(mask); 2677 attributes.set_is_evex_instruction(); 2678 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2679 emit_int8(0x6F); 2680 emit_operand(dst, src); 2681 } 2682 2683 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) { 2684 assert(VM_Version::supports_evex(), ""); 2685 InstructionMark im(this); 2686 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2687 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2688 attributes.set_is_evex_instruction(); 2689 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2690 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2691 emit_int8(0x6F); 2692 emit_operand(dst, src); 2693 } 2694 2695 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2696 assert(VM_Version::supports_avx512vlbw(), ""); 2697 InstructionMark im(this); 2698 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2699 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2700 attributes.set_embedded_opmask_register_specifier(mask); 2701 attributes.set_is_evex_instruction(); 2702 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2703 emit_int8(0x6F); 2704 emit_operand(dst, src); 2705 } 2706 2707 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) { 2708 assert(VM_Version::supports_evex(), ""); 2709 assert(src != xnoreg, "sanity"); 2710 InstructionMark im(this); 2711 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2712 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2713 attributes.set_is_evex_instruction(); 2714 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2715 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2716 emit_int8(0x7F); 2717 emit_operand(src, dst); 2718 } 2719 2720 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) { 2721 assert(VM_Version::supports_avx512vlbw(), ""); 2722 assert(src != xnoreg, "sanity"); 2723 InstructionMark im(this); 2724 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2725 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2726 attributes.reset_is_clear_context(); 2727 attributes.set_embedded_opmask_register_specifier(mask); 2728 attributes.set_is_evex_instruction(); 2729 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2730 emit_int8(0x7F); 2731 emit_operand(src, dst); 2732 } 2733 2734 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { 2735 assert(VM_Version::supports_evex(), ""); 2736 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2737 attributes.set_is_evex_instruction(); 2738 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2739 emit_int8(0x6F); 2740 emit_int8((unsigned char)(0xC0 | encode)); 2741 } 2742 2743 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) { 2744 assert(VM_Version::supports_evex(), ""); 2745 InstructionMark im(this); 2746 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true); 2747 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2748 attributes.set_is_evex_instruction(); 2749 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2750 emit_int8(0x6F); 2751 emit_operand(dst, src); 2752 } 2753 2754 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) { 2755 assert(VM_Version::supports_evex(), ""); 2756 assert(src != xnoreg, "sanity"); 2757 InstructionMark im(this); 2758 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2759 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2760 attributes.reset_is_clear_context(); 2761 attributes.set_is_evex_instruction(); 2762 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2763 emit_int8(0x7F); 2764 emit_operand(src, dst); 2765 } 2766 2767 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { 2768 assert(VM_Version::supports_evex(), ""); 2769 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2770 attributes.set_is_evex_instruction(); 2771 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2772 emit_int8(0x6F); 2773 emit_int8((unsigned char)(0xC0 | encode)); 2774 } 2775 2776 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) { 2777 assert(VM_Version::supports_evex(), ""); 2778 InstructionMark im(this); 2779 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2780 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2781 attributes.set_is_evex_instruction(); 2782 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2783 emit_int8(0x6F); 2784 emit_operand(dst, src); 2785 } 2786 2787 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) { 2788 assert(VM_Version::supports_evex(), ""); 2789 assert(src != xnoreg, "sanity"); 2790 InstructionMark im(this); 2791 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2792 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2793 attributes.reset_is_clear_context(); 2794 attributes.set_is_evex_instruction(); 2795 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2796 emit_int8(0x7F); 2797 emit_operand(src, dst); 2798 } 2799 2800 // Uses zero extension on 64bit 2801 2802 void Assembler::movl(Register dst, int32_t imm32) { 2803 int encode = prefix_and_encode(dst->encoding()); 2804 emit_int8((unsigned char)(0xB8 | encode)); 2805 emit_int32(imm32); 2806 } 2807 2808 void Assembler::movl(Register dst, Register src) { 2809 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2810 emit_int8((unsigned char)0x8B); 2811 emit_int8((unsigned char)(0xC0 | encode)); 2812 } 2813 2814 void Assembler::movl(Register dst, Address src) { 2815 InstructionMark im(this); 2816 prefix(src, dst); 2817 emit_int8((unsigned char)0x8B); 2818 emit_operand(dst, src); 2819 } 2820 2821 void Assembler::movl(Address dst, int32_t imm32) { 2822 InstructionMark im(this); 2823 prefix(dst); 2824 emit_int8((unsigned char)0xC7); 2825 emit_operand(rax, dst, 4); 2826 emit_int32(imm32); 2827 } 2828 2829 void Assembler::movl(Address dst, Register src) { 2830 InstructionMark im(this); 2831 prefix(dst, src); 2832 emit_int8((unsigned char)0x89); 2833 emit_operand(src, dst); 2834 } 2835 2836 // New cpus require to use movsd and movss to avoid partial register stall 2837 // when loading from memory. But for old Opteron use movlpd instead of movsd. 2838 // The selection is done in MacroAssembler::movdbl() and movflt(). 2839 void Assembler::movlpd(XMMRegister dst, Address src) { 2840 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2841 InstructionMark im(this); 2842 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 2843 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2844 attributes.set_rex_vex_w_reverted(); 2845 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2846 emit_int8(0x12); 2847 emit_operand(dst, src); 2848 } 2849 2850 void Assembler::movq( MMXRegister dst, Address src ) { 2851 assert( VM_Version::supports_mmx(), "" ); 2852 emit_int8(0x0F); 2853 emit_int8(0x6F); 2854 emit_operand(dst, src); 2855 } 2856 2857 void Assembler::movq( Address dst, MMXRegister src ) { 2858 assert( VM_Version::supports_mmx(), "" ); 2859 emit_int8(0x0F); 2860 emit_int8(0x7F); 2861 // workaround gcc (3.2.1-7a) bug 2862 // In that version of gcc with only an emit_operand(MMX, Address) 2863 // gcc will tail jump and try and reverse the parameters completely 2864 // obliterating dst in the process. By having a version available 2865 // that doesn't need to swap the args at the tail jump the bug is 2866 // avoided. 2867 emit_operand(dst, src); 2868 } 2869 2870 void Assembler::movq(XMMRegister dst, Address src) { 2871 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2872 InstructionMark im(this); 2873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2875 attributes.set_rex_vex_w_reverted(); 2876 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2877 emit_int8(0x7E); 2878 emit_operand(dst, src); 2879 } 2880 2881 void Assembler::movq(Address dst, XMMRegister src) { 2882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2883 InstructionMark im(this); 2884 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2885 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2886 attributes.set_rex_vex_w_reverted(); 2887 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2888 emit_int8((unsigned char)0xD6); 2889 emit_operand(src, dst); 2890 } 2891 2892 void Assembler::movsbl(Register dst, Address src) { // movsxb 2893 InstructionMark im(this); 2894 prefix(src, dst); 2895 emit_int8(0x0F); 2896 emit_int8((unsigned char)0xBE); 2897 emit_operand(dst, src); 2898 } 2899 2900 void Assembler::movsbl(Register dst, Register src) { // movsxb 2901 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2902 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2903 emit_int8(0x0F); 2904 emit_int8((unsigned char)0xBE); 2905 emit_int8((unsigned char)(0xC0 | encode)); 2906 } 2907 2908 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2909 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2910 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2911 attributes.set_rex_vex_w_reverted(); 2912 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2913 emit_int8(0x10); 2914 emit_int8((unsigned char)(0xC0 | encode)); 2915 } 2916 2917 void Assembler::movsd(XMMRegister dst, Address src) { 2918 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2919 InstructionMark im(this); 2920 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2921 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2922 attributes.set_rex_vex_w_reverted(); 2923 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2924 emit_int8(0x10); 2925 emit_operand(dst, src); 2926 } 2927 2928 void Assembler::movsd(Address dst, XMMRegister src) { 2929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2930 InstructionMark im(this); 2931 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2932 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2933 attributes.reset_is_clear_context(); 2934 attributes.set_rex_vex_w_reverted(); 2935 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2936 emit_int8(0x11); 2937 emit_operand(src, dst); 2938 } 2939 2940 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2941 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2943 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2944 emit_int8(0x10); 2945 emit_int8((unsigned char)(0xC0 | encode)); 2946 } 2947 2948 void Assembler::movss(XMMRegister dst, Address src) { 2949 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2950 InstructionMark im(this); 2951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2952 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2953 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2954 emit_int8(0x10); 2955 emit_operand(dst, src); 2956 } 2957 2958 void Assembler::movss(Address dst, XMMRegister src) { 2959 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2960 InstructionMark im(this); 2961 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2962 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2963 attributes.reset_is_clear_context(); 2964 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2965 emit_int8(0x11); 2966 emit_operand(src, dst); 2967 } 2968 2969 void Assembler::movswl(Register dst, Address src) { // movsxw 2970 InstructionMark im(this); 2971 prefix(src, dst); 2972 emit_int8(0x0F); 2973 emit_int8((unsigned char)0xBF); 2974 emit_operand(dst, src); 2975 } 2976 2977 void Assembler::movswl(Register dst, Register src) { // movsxw 2978 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2979 emit_int8(0x0F); 2980 emit_int8((unsigned char)0xBF); 2981 emit_int8((unsigned char)(0xC0 | encode)); 2982 } 2983 2984 void Assembler::movw(Address dst, int imm16) { 2985 InstructionMark im(this); 2986 2987 emit_int8(0x66); // switch to 16-bit mode 2988 prefix(dst); 2989 emit_int8((unsigned char)0xC7); 2990 emit_operand(rax, dst, 2); 2991 emit_int16(imm16); 2992 } 2993 2994 void Assembler::movw(Register dst, Address src) { 2995 InstructionMark im(this); 2996 emit_int8(0x66); 2997 prefix(src, dst); 2998 emit_int8((unsigned char)0x8B); 2999 emit_operand(dst, src); 3000 } 3001 3002 void Assembler::movw(Address dst, Register src) { 3003 InstructionMark im(this); 3004 emit_int8(0x66); 3005 prefix(dst, src); 3006 emit_int8((unsigned char)0x89); 3007 emit_operand(src, dst); 3008 } 3009 3010 void Assembler::movzbl(Register dst, Address src) { // movzxb 3011 InstructionMark im(this); 3012 prefix(src, dst); 3013 emit_int8(0x0F); 3014 emit_int8((unsigned char)0xB6); 3015 emit_operand(dst, src); 3016 } 3017 3018 void Assembler::movzbl(Register dst, Register src) { // movzxb 3019 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 3020 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 3021 emit_int8(0x0F); 3022 emit_int8((unsigned char)0xB6); 3023 emit_int8(0xC0 | encode); 3024 } 3025 3026 void Assembler::movzwl(Register dst, Address src) { // movzxw 3027 InstructionMark im(this); 3028 prefix(src, dst); 3029 emit_int8(0x0F); 3030 emit_int8((unsigned char)0xB7); 3031 emit_operand(dst, src); 3032 } 3033 3034 void Assembler::movzwl(Register dst, Register src) { // movzxw 3035 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3036 emit_int8(0x0F); 3037 emit_int8((unsigned char)0xB7); 3038 emit_int8(0xC0 | encode); 3039 } 3040 3041 void Assembler::mull(Address src) { 3042 InstructionMark im(this); 3043 prefix(src); 3044 emit_int8((unsigned char)0xF7); 3045 emit_operand(rsp, src); 3046 } 3047 3048 void Assembler::mull(Register src) { 3049 int encode = prefix_and_encode(src->encoding()); 3050 emit_int8((unsigned char)0xF7); 3051 emit_int8((unsigned char)(0xE0 | encode)); 3052 } 3053 3054 void Assembler::mulsd(XMMRegister dst, Address src) { 3055 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3056 InstructionMark im(this); 3057 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3058 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3059 attributes.set_rex_vex_w_reverted(); 3060 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3061 emit_int8(0x59); 3062 emit_operand(dst, src); 3063 } 3064 3065 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 3066 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3067 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3068 attributes.set_rex_vex_w_reverted(); 3069 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3070 emit_int8(0x59); 3071 emit_int8((unsigned char)(0xC0 | encode)); 3072 } 3073 3074 void Assembler::mulss(XMMRegister dst, Address src) { 3075 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3076 InstructionMark im(this); 3077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3078 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3079 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 3080 emit_int8(0x59); 3081 emit_operand(dst, src); 3082 } 3083 3084 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 3085 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 3088 emit_int8(0x59); 3089 emit_int8((unsigned char)(0xC0 | encode)); 3090 } 3091 3092 void Assembler::negl(Register dst) { 3093 int encode = prefix_and_encode(dst->encoding()); 3094 emit_int8((unsigned char)0xF7); 3095 emit_int8((unsigned char)(0xD8 | encode)); 3096 } 3097 3098 void Assembler::nop(int i) { 3099 #ifdef ASSERT 3100 assert(i > 0, " "); 3101 // The fancy nops aren't currently recognized by debuggers making it a 3102 // pain to disassemble code while debugging. If asserts are on clearly 3103 // speed is not an issue so simply use the single byte traditional nop 3104 // to do alignment. 3105 3106 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); 3107 return; 3108 3109 #endif // ASSERT 3110 3111 if (UseAddressNop && VM_Version::is_intel()) { 3112 // 3113 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 3114 // 1: 0x90 3115 // 2: 0x66 0x90 3116 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3117 // 4: 0x0F 0x1F 0x40 0x00 3118 // 5: 0x0F 0x1F 0x44 0x00 0x00 3119 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3120 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3121 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3122 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3123 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3124 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3125 3126 // The rest coding is Intel specific - don't use consecutive address nops 3127 3128 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3129 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3130 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3131 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3132 3133 while(i >= 15) { 3134 // For Intel don't generate consecutive addess nops (mix with regular nops) 3135 i -= 15; 3136 emit_int8(0x66); // size prefix 3137 emit_int8(0x66); // size prefix 3138 emit_int8(0x66); // size prefix 3139 addr_nop_8(); 3140 emit_int8(0x66); // size prefix 3141 emit_int8(0x66); // size prefix 3142 emit_int8(0x66); // size prefix 3143 emit_int8((unsigned char)0x90); 3144 // nop 3145 } 3146 switch (i) { 3147 case 14: 3148 emit_int8(0x66); // size prefix 3149 case 13: 3150 emit_int8(0x66); // size prefix 3151 case 12: 3152 addr_nop_8(); 3153 emit_int8(0x66); // size prefix 3154 emit_int8(0x66); // size prefix 3155 emit_int8(0x66); // size prefix 3156 emit_int8((unsigned char)0x90); 3157 // nop 3158 break; 3159 case 11: 3160 emit_int8(0x66); // size prefix 3161 case 10: 3162 emit_int8(0x66); // size prefix 3163 case 9: 3164 emit_int8(0x66); // size prefix 3165 case 8: 3166 addr_nop_8(); 3167 break; 3168 case 7: 3169 addr_nop_7(); 3170 break; 3171 case 6: 3172 emit_int8(0x66); // size prefix 3173 case 5: 3174 addr_nop_5(); 3175 break; 3176 case 4: 3177 addr_nop_4(); 3178 break; 3179 case 3: 3180 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3181 emit_int8(0x66); // size prefix 3182 case 2: 3183 emit_int8(0x66); // size prefix 3184 case 1: 3185 emit_int8((unsigned char)0x90); 3186 // nop 3187 break; 3188 default: 3189 assert(i == 0, " "); 3190 } 3191 return; 3192 } 3193 if (UseAddressNop && VM_Version::is_amd_family()) { 3194 // 3195 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 3196 // 1: 0x90 3197 // 2: 0x66 0x90 3198 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3199 // 4: 0x0F 0x1F 0x40 0x00 3200 // 5: 0x0F 0x1F 0x44 0x00 0x00 3201 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3202 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3203 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3204 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3205 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3206 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3207 3208 // The rest coding is AMD specific - use consecutive address nops 3209 3210 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3211 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3212 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3213 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3214 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3215 // Size prefixes (0x66) are added for larger sizes 3216 3217 while(i >= 22) { 3218 i -= 11; 3219 emit_int8(0x66); // size prefix 3220 emit_int8(0x66); // size prefix 3221 emit_int8(0x66); // size prefix 3222 addr_nop_8(); 3223 } 3224 // Generate first nop for size between 21-12 3225 switch (i) { 3226 case 21: 3227 i -= 1; 3228 emit_int8(0x66); // size prefix 3229 case 20: 3230 case 19: 3231 i -= 1; 3232 emit_int8(0x66); // size prefix 3233 case 18: 3234 case 17: 3235 i -= 1; 3236 emit_int8(0x66); // size prefix 3237 case 16: 3238 case 15: 3239 i -= 8; 3240 addr_nop_8(); 3241 break; 3242 case 14: 3243 case 13: 3244 i -= 7; 3245 addr_nop_7(); 3246 break; 3247 case 12: 3248 i -= 6; 3249 emit_int8(0x66); // size prefix 3250 addr_nop_5(); 3251 break; 3252 default: 3253 assert(i < 12, " "); 3254 } 3255 3256 // Generate second nop for size between 11-1 3257 switch (i) { 3258 case 11: 3259 emit_int8(0x66); // size prefix 3260 case 10: 3261 emit_int8(0x66); // size prefix 3262 case 9: 3263 emit_int8(0x66); // size prefix 3264 case 8: 3265 addr_nop_8(); 3266 break; 3267 case 7: 3268 addr_nop_7(); 3269 break; 3270 case 6: 3271 emit_int8(0x66); // size prefix 3272 case 5: 3273 addr_nop_5(); 3274 break; 3275 case 4: 3276 addr_nop_4(); 3277 break; 3278 case 3: 3279 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3280 emit_int8(0x66); // size prefix 3281 case 2: 3282 emit_int8(0x66); // size prefix 3283 case 1: 3284 emit_int8((unsigned char)0x90); 3285 // nop 3286 break; 3287 default: 3288 assert(i == 0, " "); 3289 } 3290 return; 3291 } 3292 3293 if (UseAddressNop && VM_Version::is_zx()) { 3294 // 3295 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX 3296 // 1: 0x90 3297 // 2: 0x66 0x90 3298 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3299 // 4: 0x0F 0x1F 0x40 0x00 3300 // 5: 0x0F 0x1F 0x44 0x00 0x00 3301 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3302 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3303 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3304 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3305 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3306 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3307 3308 // The rest coding is ZX specific - don't use consecutive address nops 3309 3310 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3311 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3312 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3313 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 3314 3315 while (i >= 15) { 3316 // For ZX don't generate consecutive addess nops (mix with regular nops) 3317 i -= 15; 3318 emit_int8(0x66); // size prefix 3319 emit_int8(0x66); // size prefix 3320 emit_int8(0x66); // size prefix 3321 addr_nop_8(); 3322 emit_int8(0x66); // size prefix 3323 emit_int8(0x66); // size prefix 3324 emit_int8(0x66); // size prefix 3325 emit_int8((unsigned char)0x90); 3326 // nop 3327 } 3328 switch (i) { 3329 case 14: 3330 emit_int8(0x66); // size prefix 3331 case 13: 3332 emit_int8(0x66); // size prefix 3333 case 12: 3334 addr_nop_8(); 3335 emit_int8(0x66); // size prefix 3336 emit_int8(0x66); // size prefix 3337 emit_int8(0x66); // size prefix 3338 emit_int8((unsigned char)0x90); 3339 // nop 3340 break; 3341 case 11: 3342 emit_int8(0x66); // size prefix 3343 case 10: 3344 emit_int8(0x66); // size prefix 3345 case 9: 3346 emit_int8(0x66); // size prefix 3347 case 8: 3348 addr_nop_8(); 3349 break; 3350 case 7: 3351 addr_nop_7(); 3352 break; 3353 case 6: 3354 emit_int8(0x66); // size prefix 3355 case 5: 3356 addr_nop_5(); 3357 break; 3358 case 4: 3359 addr_nop_4(); 3360 break; 3361 case 3: 3362 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3363 emit_int8(0x66); // size prefix 3364 case 2: 3365 emit_int8(0x66); // size prefix 3366 case 1: 3367 emit_int8((unsigned char)0x90); 3368 // nop 3369 break; 3370 default: 3371 assert(i == 0, " "); 3372 } 3373 return; 3374 } 3375 3376 // Using nops with size prefixes "0x66 0x90". 3377 // From AMD Optimization Guide: 3378 // 1: 0x90 3379 // 2: 0x66 0x90 3380 // 3: 0x66 0x66 0x90 3381 // 4: 0x66 0x66 0x66 0x90 3382 // 5: 0x66 0x66 0x90 0x66 0x90 3383 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 3384 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 3385 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 3386 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3387 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3388 // 3389 while(i > 12) { 3390 i -= 4; 3391 emit_int8(0x66); // size prefix 3392 emit_int8(0x66); 3393 emit_int8(0x66); 3394 emit_int8((unsigned char)0x90); 3395 // nop 3396 } 3397 // 1 - 12 nops 3398 if(i > 8) { 3399 if(i > 9) { 3400 i -= 1; 3401 emit_int8(0x66); 3402 } 3403 i -= 3; 3404 emit_int8(0x66); 3405 emit_int8(0x66); 3406 emit_int8((unsigned char)0x90); 3407 } 3408 // 1 - 8 nops 3409 if(i > 4) { 3410 if(i > 6) { 3411 i -= 1; 3412 emit_int8(0x66); 3413 } 3414 i -= 3; 3415 emit_int8(0x66); 3416 emit_int8(0x66); 3417 emit_int8((unsigned char)0x90); 3418 } 3419 switch (i) { 3420 case 4: 3421 emit_int8(0x66); 3422 case 3: 3423 emit_int8(0x66); 3424 case 2: 3425 emit_int8(0x66); 3426 case 1: 3427 emit_int8((unsigned char)0x90); 3428 break; 3429 default: 3430 assert(i == 0, " "); 3431 } 3432 } 3433 3434 void Assembler::notl(Register dst) { 3435 int encode = prefix_and_encode(dst->encoding()); 3436 emit_int8((unsigned char)0xF7); 3437 emit_int8((unsigned char)(0xD0 | encode)); 3438 } 3439 3440 void Assembler::orl(Address dst, int32_t imm32) { 3441 InstructionMark im(this); 3442 prefix(dst); 3443 emit_arith_operand(0x81, rcx, dst, imm32); 3444 } 3445 3446 void Assembler::orl(Register dst, int32_t imm32) { 3447 prefix(dst); 3448 emit_arith(0x81, 0xC8, dst, imm32); 3449 } 3450 3451 void Assembler::orl(Register dst, Address src) { 3452 InstructionMark im(this); 3453 prefix(src, dst); 3454 emit_int8(0x0B); 3455 emit_operand(dst, src); 3456 } 3457 3458 void Assembler::orl(Register dst, Register src) { 3459 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3460 emit_arith(0x0B, 0xC0, dst, src); 3461 } 3462 3463 void Assembler::orl(Address dst, Register src) { 3464 InstructionMark im(this); 3465 prefix(dst, src); 3466 emit_int8(0x09); 3467 emit_operand(src, dst); 3468 } 3469 3470 void Assembler::orb(Address dst, int imm8) { 3471 InstructionMark im(this); 3472 prefix(dst); 3473 emit_int8((unsigned char)0x80); 3474 emit_operand(rcx, dst, 1); 3475 emit_int8(imm8); 3476 } 3477 3478 void Assembler::packuswb(XMMRegister dst, Address src) { 3479 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3480 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3481 InstructionMark im(this); 3482 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3483 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3484 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3485 emit_int8(0x67); 3486 emit_operand(dst, src); 3487 } 3488 3489 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 3490 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3491 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3492 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3493 emit_int8(0x67); 3494 emit_int8((unsigned char)(0xC0 | encode)); 3495 } 3496 3497 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3498 assert(UseAVX > 0, "some form of AVX must be enabled"); 3499 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3500 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3501 emit_int8(0x67); 3502 emit_int8((unsigned char)(0xC0 | encode)); 3503 } 3504 3505 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { 3506 assert(VM_Version::supports_avx2(), ""); 3507 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3508 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3509 emit_int8(0x00); 3510 emit_int8((unsigned char)(0xC0 | encode)); 3511 emit_int8(imm8); 3512 } 3513 3514 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3515 assert(UseAVX > 2, "requires AVX512F"); 3516 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3517 attributes.set_is_evex_instruction(); 3518 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3519 emit_int8((unsigned char)0x36); 3520 emit_int8((unsigned char)(0xC0 | encode)); 3521 } 3522 3523 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3524 assert(VM_Version::supports_avx2(), ""); 3525 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3526 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3527 emit_int8(0x46); 3528 emit_int8(0xC0 | encode); 3529 emit_int8(imm8); 3530 } 3531 3532 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3533 assert(VM_Version::supports_avx(), ""); 3534 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3535 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3536 emit_int8(0x06); 3537 emit_int8(0xC0 | encode); 3538 emit_int8(imm8); 3539 } 3540 3541 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3542 assert(VM_Version::supports_evex(), ""); 3543 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3544 attributes.set_is_evex_instruction(); 3545 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3546 emit_int8(0x76); 3547 emit_int8((unsigned char)(0xC0 | encode)); 3548 } 3549 3550 3551 void Assembler::pause() { 3552 emit_int8((unsigned char)0xF3); 3553 emit_int8((unsigned char)0x90); 3554 } 3555 3556 void Assembler::ud2() { 3557 emit_int8(0x0F); 3558 emit_int8(0x0B); 3559 } 3560 3561 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3562 assert(VM_Version::supports_sse4_2(), ""); 3563 InstructionMark im(this); 3564 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3565 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3566 emit_int8(0x61); 3567 emit_operand(dst, src); 3568 emit_int8(imm8); 3569 } 3570 3571 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3572 assert(VM_Version::supports_sse4_2(), ""); 3573 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3574 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3575 emit_int8(0x61); 3576 emit_int8((unsigned char)(0xC0 | encode)); 3577 emit_int8(imm8); 3578 } 3579 3580 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3581 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3582 assert(VM_Version::supports_sse2(), ""); 3583 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3584 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3585 emit_int8(0x74); 3586 emit_int8((unsigned char)(0xC0 | encode)); 3587 } 3588 3589 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3590 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3591 assert(VM_Version::supports_avx(), ""); 3592 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3593 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3594 emit_int8(0x74); 3595 emit_int8((unsigned char)(0xC0 | encode)); 3596 } 3597 3598 // In this context, kdst is written the mask used to process the equal components 3599 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3600 assert(VM_Version::supports_avx512bw(), ""); 3601 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3602 attributes.set_is_evex_instruction(); 3603 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3604 emit_int8(0x74); 3605 emit_int8((unsigned char)(0xC0 | encode)); 3606 } 3607 3608 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3609 assert(VM_Version::supports_avx512vlbw(), ""); 3610 InstructionMark im(this); 3611 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3612 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3613 attributes.set_is_evex_instruction(); 3614 int dst_enc = kdst->encoding(); 3615 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3616 emit_int8(0x64); 3617 emit_operand(as_Register(dst_enc), src); 3618 } 3619 3620 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3621 assert(VM_Version::supports_avx512vlbw(), ""); 3622 InstructionMark im(this); 3623 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3624 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3625 attributes.reset_is_clear_context(); 3626 attributes.set_embedded_opmask_register_specifier(mask); 3627 attributes.set_is_evex_instruction(); 3628 int dst_enc = kdst->encoding(); 3629 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3630 emit_int8(0x64); 3631 emit_operand(as_Register(dst_enc), src); 3632 } 3633 3634 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3635 assert(VM_Version::supports_avx512vlbw(), ""); 3636 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3637 attributes.set_is_evex_instruction(); 3638 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3639 emit_int8(0x3E); 3640 emit_int8((unsigned char)(0xC0 | encode)); 3641 emit_int8(vcc); 3642 } 3643 3644 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3645 assert(VM_Version::supports_avx512vlbw(), ""); 3646 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3647 attributes.reset_is_clear_context(); 3648 attributes.set_embedded_opmask_register_specifier(mask); 3649 attributes.set_is_evex_instruction(); 3650 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3651 emit_int8(0x3E); 3652 emit_int8((unsigned char)(0xC0 | encode)); 3653 emit_int8(vcc); 3654 } 3655 3656 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) { 3657 assert(VM_Version::supports_avx512vlbw(), ""); 3658 InstructionMark im(this); 3659 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3660 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3661 attributes.set_is_evex_instruction(); 3662 int dst_enc = kdst->encoding(); 3663 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3664 emit_int8(0x3E); 3665 emit_operand(as_Register(dst_enc), src); 3666 emit_int8(vcc); 3667 } 3668 3669 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3670 assert(VM_Version::supports_avx512bw(), ""); 3671 InstructionMark im(this); 3672 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3673 attributes.set_is_evex_instruction(); 3674 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3675 int dst_enc = kdst->encoding(); 3676 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3677 emit_int8(0x74); 3678 emit_operand(as_Register(dst_enc), src); 3679 } 3680 3681 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3682 assert(VM_Version::supports_avx512vlbw(), ""); 3683 InstructionMark im(this); 3684 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true); 3685 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3686 attributes.reset_is_clear_context(); 3687 attributes.set_embedded_opmask_register_specifier(mask); 3688 attributes.set_is_evex_instruction(); 3689 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3690 emit_int8(0x74); 3691 emit_operand(as_Register(kdst->encoding()), src); 3692 } 3693 3694 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3695 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3696 assert(VM_Version::supports_sse2(), ""); 3697 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3698 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3699 emit_int8(0x75); 3700 emit_int8((unsigned char)(0xC0 | encode)); 3701 } 3702 3703 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3704 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3705 assert(VM_Version::supports_avx(), ""); 3706 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3707 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3708 emit_int8(0x75); 3709 emit_int8((unsigned char)(0xC0 | encode)); 3710 } 3711 3712 // In this context, kdst is written the mask used to process the equal components 3713 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3714 assert(VM_Version::supports_avx512bw(), ""); 3715 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3716 attributes.set_is_evex_instruction(); 3717 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3718 emit_int8(0x75); 3719 emit_int8((unsigned char)(0xC0 | encode)); 3720 } 3721 3722 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3723 assert(VM_Version::supports_avx512bw(), ""); 3724 InstructionMark im(this); 3725 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3726 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3727 attributes.set_is_evex_instruction(); 3728 int dst_enc = kdst->encoding(); 3729 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3730 emit_int8(0x75); 3731 emit_operand(as_Register(dst_enc), src); 3732 } 3733 3734 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3735 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { 3736 assert(VM_Version::supports_sse2(), ""); 3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3738 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3739 emit_int8(0x76); 3740 emit_int8((unsigned char)(0xC0 | encode)); 3741 } 3742 3743 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3744 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3745 assert(VM_Version::supports_avx(), ""); 3746 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3747 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3748 emit_int8(0x76); 3749 emit_int8((unsigned char)(0xC0 | encode)); 3750 } 3751 3752 // In this context, kdst is written the mask used to process the equal components 3753 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3754 assert(VM_Version::supports_evex(), ""); 3755 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3756 attributes.set_is_evex_instruction(); 3757 attributes.reset_is_clear_context(); 3758 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3759 emit_int8(0x76); 3760 emit_int8((unsigned char)(0xC0 | encode)); 3761 } 3762 3763 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3764 assert(VM_Version::supports_evex(), ""); 3765 InstructionMark im(this); 3766 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3767 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3768 attributes.reset_is_clear_context(); 3769 attributes.set_is_evex_instruction(); 3770 int dst_enc = kdst->encoding(); 3771 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3772 emit_int8(0x76); 3773 emit_operand(as_Register(dst_enc), src); 3774 } 3775 3776 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3777 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) { 3778 assert(VM_Version::supports_sse4_1(), ""); 3779 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3780 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3781 emit_int8(0x29); 3782 emit_int8((unsigned char)(0xC0 | encode)); 3783 } 3784 3785 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3786 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3787 assert(VM_Version::supports_avx(), ""); 3788 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3789 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3790 emit_int8(0x29); 3791 emit_int8((unsigned char)(0xC0 | encode)); 3792 } 3793 3794 // In this context, kdst is written the mask used to process the equal components 3795 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3796 assert(VM_Version::supports_evex(), ""); 3797 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3798 attributes.reset_is_clear_context(); 3799 attributes.set_is_evex_instruction(); 3800 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3801 emit_int8(0x29); 3802 emit_int8((unsigned char)(0xC0 | encode)); 3803 } 3804 3805 // In this context, kdst is written the mask used to process the equal components 3806 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3807 assert(VM_Version::supports_evex(), ""); 3808 InstructionMark im(this); 3809 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3810 attributes.reset_is_clear_context(); 3811 attributes.set_is_evex_instruction(); 3812 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 3813 int dst_enc = kdst->encoding(); 3814 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3815 emit_int8(0x29); 3816 emit_operand(as_Register(dst_enc), src); 3817 } 3818 3819 void Assembler::pmovmskb(Register dst, XMMRegister src) { 3820 assert(VM_Version::supports_sse2(), ""); 3821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3822 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3823 emit_int8((unsigned char)0xD7); 3824 emit_int8((unsigned char)(0xC0 | encode)); 3825 } 3826 3827 void Assembler::vpmovmskb(Register dst, XMMRegister src) { 3828 assert(VM_Version::supports_avx2(), ""); 3829 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 3830 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3831 emit_int8((unsigned char)0xD7); 3832 emit_int8((unsigned char)(0xC0 | encode)); 3833 } 3834 3835 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { 3836 assert(VM_Version::supports_sse4_1(), ""); 3837 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3838 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3839 emit_int8(0x16); 3840 emit_int8((unsigned char)(0xC0 | encode)); 3841 emit_int8(imm8); 3842 } 3843 3844 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) { 3845 assert(VM_Version::supports_sse4_1(), ""); 3846 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3847 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3848 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3849 emit_int8(0x16); 3850 emit_operand(src, dst); 3851 emit_int8(imm8); 3852 } 3853 3854 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { 3855 assert(VM_Version::supports_sse4_1(), ""); 3856 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3857 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3858 emit_int8(0x16); 3859 emit_int8((unsigned char)(0xC0 | encode)); 3860 emit_int8(imm8); 3861 } 3862 3863 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) { 3864 assert(VM_Version::supports_sse4_1(), ""); 3865 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3866 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3867 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3868 emit_int8(0x16); 3869 emit_operand(src, dst); 3870 emit_int8(imm8); 3871 } 3872 3873 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { 3874 assert(VM_Version::supports_sse2(), ""); 3875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3876 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3877 emit_int8((unsigned char)0xC5); 3878 emit_int8((unsigned char)(0xC0 | encode)); 3879 emit_int8(imm8); 3880 } 3881 3882 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) { 3883 assert(VM_Version::supports_sse4_1(), ""); 3884 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3885 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3886 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3887 emit_int8((unsigned char)0x15); 3888 emit_operand(src, dst); 3889 emit_int8(imm8); 3890 } 3891 3892 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) { 3893 assert(VM_Version::supports_sse4_1(), ""); 3894 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3895 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3896 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3897 emit_int8(0x14); 3898 emit_operand(src, dst); 3899 emit_int8(imm8); 3900 } 3901 3902 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { 3903 assert(VM_Version::supports_sse4_1(), ""); 3904 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3905 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3906 emit_int8(0x22); 3907 emit_int8((unsigned char)(0xC0 | encode)); 3908 emit_int8(imm8); 3909 } 3910 3911 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) { 3912 assert(VM_Version::supports_sse4_1(), ""); 3913 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3914 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3915 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3916 emit_int8(0x22); 3917 emit_operand(dst,src); 3918 emit_int8(imm8); 3919 } 3920 3921 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { 3922 assert(VM_Version::supports_sse4_1(), ""); 3923 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3924 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3925 emit_int8(0x22); 3926 emit_int8((unsigned char)(0xC0 | encode)); 3927 emit_int8(imm8); 3928 } 3929 3930 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) { 3931 assert(VM_Version::supports_sse4_1(), ""); 3932 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 3933 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3934 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3935 emit_int8(0x22); 3936 emit_operand(dst, src); 3937 emit_int8(imm8); 3938 } 3939 3940 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) { 3941 assert(VM_Version::supports_sse2(), ""); 3942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3943 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3944 emit_int8((unsigned char)0xC4); 3945 emit_int8((unsigned char)(0xC0 | encode)); 3946 emit_int8(imm8); 3947 } 3948 3949 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) { 3950 assert(VM_Version::supports_sse2(), ""); 3951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3952 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3953 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3954 emit_int8((unsigned char)0xC4); 3955 emit_operand(dst, src); 3956 emit_int8(imm8); 3957 } 3958 3959 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) { 3960 assert(VM_Version::supports_sse4_1(), ""); 3961 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3962 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3963 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3964 emit_int8(0x20); 3965 emit_operand(dst, src); 3966 emit_int8(imm8); 3967 } 3968 3969 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 3970 assert(VM_Version::supports_sse4_1(), ""); 3971 InstructionMark im(this); 3972 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3973 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3974 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3975 emit_int8(0x30); 3976 emit_operand(dst, src); 3977 } 3978 3979 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3980 assert(VM_Version::supports_sse4_1(), ""); 3981 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3982 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3983 emit_int8(0x30); 3984 emit_int8((unsigned char)(0xC0 | encode)); 3985 } 3986 3987 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) { 3988 assert(VM_Version::supports_sse4_1(), ""); 3989 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3990 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3991 emit_int8(0x20); 3992 emit_int8((unsigned char)(0xC0 | encode)); 3993 } 3994 3995 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3996 assert(VM_Version::supports_avx(), ""); 3997 InstructionMark im(this); 3998 assert(dst != xnoreg, "sanity"); 3999 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4000 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 4001 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4002 emit_int8(0x30); 4003 emit_operand(dst, src); 4004 } 4005 4006 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { 4007 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4008 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4009 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); 4010 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4011 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4012 emit_int8(0x30); 4013 emit_int8((unsigned char) (0xC0 | encode)); 4014 } 4015 4016 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) { 4017 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4018 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4019 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); 4020 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4022 emit_int8(0x20); 4023 emit_int8((unsigned char)(0xC0 | encode)); 4024 } 4025 4026 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 4027 assert(VM_Version::supports_avx512vlbw(), ""); 4028 assert(dst != xnoreg, "sanity"); 4029 InstructionMark im(this); 4030 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4031 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 4032 attributes.set_embedded_opmask_register_specifier(mask); 4033 attributes.set_is_evex_instruction(); 4034 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4035 emit_int8(0x30); 4036 emit_operand(dst, src); 4037 } 4038 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) { 4039 assert(VM_Version::supports_avx512vlbw(), ""); 4040 assert(src != xnoreg, "sanity"); 4041 InstructionMark im(this); 4042 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4043 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 4044 attributes.set_is_evex_instruction(); 4045 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 4046 emit_int8(0x30); 4047 emit_operand(src, dst); 4048 } 4049 4050 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) { 4051 assert(VM_Version::supports_avx512vlbw(), ""); 4052 assert(src != xnoreg, "sanity"); 4053 InstructionMark im(this); 4054 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4055 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 4056 attributes.reset_is_clear_context(); 4057 attributes.set_embedded_opmask_register_specifier(mask); 4058 attributes.set_is_evex_instruction(); 4059 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 4060 emit_int8(0x30); 4061 emit_operand(src, dst); 4062 } 4063 4064 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) { 4065 assert(VM_Version::supports_evex(), ""); 4066 assert(src != xnoreg, "sanity"); 4067 InstructionMark im(this); 4068 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4069 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit); 4070 attributes.set_is_evex_instruction(); 4071 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 4072 emit_int8(0x31); 4073 emit_operand(src, dst); 4074 } 4075 4076 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) { 4077 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4078 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4079 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " "); 4080 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4081 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4082 emit_int8(0x33); 4083 emit_int8((unsigned char)(0xC0 | encode)); 4084 } 4085 4086 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) { 4087 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4089 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4090 emit_int8((unsigned char)0xF5); 4091 emit_int8((unsigned char)(0xC0 | encode)); 4092 } 4093 4094 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4095 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : 4096 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : 4097 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), ""); 4098 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4099 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4100 emit_int8((unsigned char)0xF5); 4101 emit_int8((unsigned char)(0xC0 | encode)); 4102 } 4103 4104 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4105 assert(VM_Version::supports_evex(), ""); 4106 assert(VM_Version::supports_vnni(), "must support vnni"); 4107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4108 attributes.set_is_evex_instruction(); 4109 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4110 emit_int8(0x52); 4111 emit_int8((unsigned char)(0xC0 | encode)); 4112 } 4113 4114 // generic 4115 void Assembler::pop(Register dst) { 4116 int encode = prefix_and_encode(dst->encoding()); 4117 emit_int8(0x58 | encode); 4118 } 4119 4120 void Assembler::popcntl(Register dst, Address src) { 4121 assert(VM_Version::supports_popcnt(), "must support"); 4122 InstructionMark im(this); 4123 emit_int8((unsigned char)0xF3); 4124 prefix(src, dst); 4125 emit_int8(0x0F); 4126 emit_int8((unsigned char)0xB8); 4127 emit_operand(dst, src); 4128 } 4129 4130 void Assembler::popcntl(Register dst, Register src) { 4131 assert(VM_Version::supports_popcnt(), "must support"); 4132 emit_int8((unsigned char)0xF3); 4133 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4134 emit_int8(0x0F); 4135 emit_int8((unsigned char)0xB8); 4136 emit_int8((unsigned char)(0xC0 | encode)); 4137 } 4138 4139 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) { 4140 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature"); 4141 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4142 attributes.set_is_evex_instruction(); 4143 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4144 emit_int8(0x55); 4145 emit_int8((unsigned char)(0xC0 | encode)); 4146 } 4147 4148 void Assembler::popf() { 4149 emit_int8((unsigned char)0x9D); 4150 } 4151 4152 #ifndef _LP64 // no 32bit push/pop on amd64 4153 void Assembler::popl(Address dst) { 4154 // NOTE: this will adjust stack by 8byte on 64bits 4155 InstructionMark im(this); 4156 prefix(dst); 4157 emit_int8((unsigned char)0x8F); 4158 emit_operand(rax, dst); 4159 } 4160 #endif 4161 4162 void Assembler::prefetch_prefix(Address src) { 4163 prefix(src); 4164 emit_int8(0x0F); 4165 } 4166 4167 void Assembler::prefetchnta(Address src) { 4168 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4169 InstructionMark im(this); 4170 prefetch_prefix(src); 4171 emit_int8(0x18); 4172 emit_operand(rax, src); // 0, src 4173 } 4174 4175 void Assembler::prefetchr(Address src) { 4176 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 4177 InstructionMark im(this); 4178 prefetch_prefix(src); 4179 emit_int8(0x0D); 4180 emit_operand(rax, src); // 0, src 4181 } 4182 4183 void Assembler::prefetcht0(Address src) { 4184 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4185 InstructionMark im(this); 4186 prefetch_prefix(src); 4187 emit_int8(0x18); 4188 emit_operand(rcx, src); // 1, src 4189 } 4190 4191 void Assembler::prefetcht1(Address src) { 4192 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4193 InstructionMark im(this); 4194 prefetch_prefix(src); 4195 emit_int8(0x18); 4196 emit_operand(rdx, src); // 2, src 4197 } 4198 4199 void Assembler::prefetcht2(Address src) { 4200 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 4201 InstructionMark im(this); 4202 prefetch_prefix(src); 4203 emit_int8(0x18); 4204 emit_operand(rbx, src); // 3, src 4205 } 4206 4207 void Assembler::prefetchw(Address src) { 4208 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 4209 InstructionMark im(this); 4210 prefetch_prefix(src); 4211 emit_int8(0x0D); 4212 emit_operand(rcx, src); // 1, src 4213 } 4214 4215 void Assembler::prefix(Prefix p) { 4216 emit_int8(p); 4217 } 4218 4219 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { 4220 assert(VM_Version::supports_ssse3(), ""); 4221 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4222 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4223 emit_int8(0x00); 4224 emit_int8((unsigned char)(0xC0 | encode)); 4225 } 4226 4227 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4228 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4229 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4230 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, ""); 4231 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4232 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4233 emit_int8(0x00); 4234 emit_int8((unsigned char)(0xC0 | encode)); 4235 } 4236 4237 void Assembler::pshufb(XMMRegister dst, Address src) { 4238 assert(VM_Version::supports_ssse3(), ""); 4239 InstructionMark im(this); 4240 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4241 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4242 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4243 emit_int8(0x00); 4244 emit_operand(dst, src); 4245 } 4246 4247 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 4248 assert(isByte(mode), "invalid value"); 4249 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4250 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 4251 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4252 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4253 emit_int8(0x70); 4254 emit_int8((unsigned char)(0xC0 | encode)); 4255 emit_int8(mode & 0xFF); 4256 } 4257 4258 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) { 4259 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4260 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4261 0, ""); 4262 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4263 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4264 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4265 emit_int8(0x70); 4266 emit_int8((unsigned char)(0xC0 | encode)); 4267 emit_int8(mode & 0xFF); 4268 } 4269 4270 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 4271 assert(isByte(mode), "invalid value"); 4272 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4273 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4274 InstructionMark im(this); 4275 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4276 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4277 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4278 emit_int8(0x70); 4279 emit_operand(dst, src); 4280 emit_int8(mode & 0xFF); 4281 } 4282 4283 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4284 assert(isByte(mode), "invalid value"); 4285 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4287 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4288 emit_int8(0x70); 4289 emit_int8((unsigned char)(0xC0 | encode)); 4290 emit_int8(mode & 0xFF); 4291 } 4292 4293 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 4294 assert(isByte(mode), "invalid value"); 4295 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4296 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4297 InstructionMark im(this); 4298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4299 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4300 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4301 emit_int8(0x70); 4302 emit_operand(dst, src); 4303 emit_int8(mode & 0xFF); 4304 } 4305 4306 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4307 assert(VM_Version::supports_evex(), "requires EVEX support"); 4308 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, ""); 4309 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4310 attributes.set_is_evex_instruction(); 4311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4312 emit_int8(0x43); 4313 emit_int8((unsigned char)(0xC0 | encode)); 4314 emit_int8(imm8 & 0xFF); 4315 } 4316 4317 void Assembler::psrldq(XMMRegister dst, int shift) { 4318 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 4319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4320 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4321 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4322 emit_int8(0x73); 4323 emit_int8((unsigned char)(0xC0 | encode)); 4324 emit_int8(shift); 4325 } 4326 4327 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4328 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : 4329 vector_len == AVX_256bit ? VM_Version::supports_avx2() : 4330 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, ""); 4331 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4332 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4333 emit_int8(0x73); 4334 emit_int8((unsigned char)(0xC0 | encode)); 4335 emit_int8(shift & 0xFF); 4336 } 4337 4338 void Assembler::pslldq(XMMRegister dst, int shift) { 4339 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 4340 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4342 // XMM7 is for /7 encoding: 66 0F 73 /7 ib 4343 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4344 emit_int8(0x73); 4345 emit_int8((unsigned char)(0xC0 | encode)); 4346 emit_int8(shift); 4347 } 4348 4349 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4350 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : 4351 vector_len == AVX_256bit ? VM_Version::supports_avx2() : 4352 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, ""); 4353 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4354 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4355 emit_int8(0x73); 4356 emit_int8((unsigned char)(0xC0 | encode)); 4357 emit_int8(shift & 0xFF); 4358 } 4359 4360 void Assembler::ptest(XMMRegister dst, Address src) { 4361 assert(VM_Version::supports_sse4_1(), ""); 4362 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4363 InstructionMark im(this); 4364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4365 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4366 emit_int8(0x17); 4367 emit_operand(dst, src); 4368 } 4369 4370 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 4371 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), ""); 4372 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4373 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4374 emit_int8(0x17); 4375 emit_int8((unsigned char)(0xC0 | encode)); 4376 } 4377 4378 void Assembler::vptest(XMMRegister dst, Address src) { 4379 assert(VM_Version::supports_avx(), ""); 4380 InstructionMark im(this); 4381 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4382 assert(dst != xnoreg, "sanity"); 4383 // swap src<->dst for encoding 4384 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4385 emit_int8(0x17); 4386 emit_operand(dst, src); 4387 } 4388 4389 void Assembler::vptest(XMMRegister dst, XMMRegister src) { 4390 assert(VM_Version::supports_avx(), ""); 4391 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4392 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4393 emit_int8(0x17); 4394 emit_int8((unsigned char)(0xC0 | encode)); 4395 } 4396 4397 void Assembler::punpcklbw(XMMRegister dst, Address src) { 4398 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4399 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4400 InstructionMark im(this); 4401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true); 4402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4403 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4404 emit_int8(0x60); 4405 emit_operand(dst, src); 4406 } 4407 4408 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4409 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4410 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true); 4411 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4412 emit_int8(0x60); 4413 emit_int8((unsigned char)(0xC0 | encode)); 4414 } 4415 4416 void Assembler::punpckldq(XMMRegister dst, Address src) { 4417 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4418 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4419 InstructionMark im(this); 4420 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4421 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4422 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4423 emit_int8(0x62); 4424 emit_operand(dst, src); 4425 } 4426 4427 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 4428 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4429 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4430 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4431 emit_int8(0x62); 4432 emit_int8((unsigned char)(0xC0 | encode)); 4433 } 4434 4435 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { 4436 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4437 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4438 attributes.set_rex_vex_w_reverted(); 4439 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4440 emit_int8(0x6C); 4441 emit_int8((unsigned char)(0xC0 | encode)); 4442 } 4443 4444 void Assembler::push(int32_t imm32) { 4445 // in 64bits we push 64bits onto the stack but only 4446 // take a 32bit immediate 4447 emit_int8(0x68); 4448 emit_int32(imm32); 4449 } 4450 4451 void Assembler::push(Register src) { 4452 int encode = prefix_and_encode(src->encoding()); 4453 4454 emit_int8(0x50 | encode); 4455 } 4456 4457 void Assembler::pushf() { 4458 emit_int8((unsigned char)0x9C); 4459 } 4460 4461 #ifndef _LP64 // no 32bit push/pop on amd64 4462 void Assembler::pushl(Address src) { 4463 // Note this will push 64bit on 64bit 4464 InstructionMark im(this); 4465 prefix(src); 4466 emit_int8((unsigned char)0xFF); 4467 emit_operand(rsi, src); 4468 } 4469 #endif 4470 4471 void Assembler::rcll(Register dst, int imm8) { 4472 assert(isShiftCount(imm8), "illegal shift count"); 4473 int encode = prefix_and_encode(dst->encoding()); 4474 if (imm8 == 1) { 4475 emit_int8((unsigned char)0xD1); 4476 emit_int8((unsigned char)(0xD0 | encode)); 4477 } else { 4478 emit_int8((unsigned char)0xC1); 4479 emit_int8((unsigned char)0xD0 | encode); 4480 emit_int8(imm8); 4481 } 4482 } 4483 4484 void Assembler::rcpps(XMMRegister dst, XMMRegister src) { 4485 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4487 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4488 emit_int8(0x53); 4489 emit_int8((unsigned char)(0xC0 | encode)); 4490 } 4491 4492 void Assembler::rcpss(XMMRegister dst, XMMRegister src) { 4493 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4495 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4496 emit_int8(0x53); 4497 emit_int8((unsigned char)(0xC0 | encode)); 4498 } 4499 4500 void Assembler::rdtsc() { 4501 emit_int8((unsigned char)0x0F); 4502 emit_int8((unsigned char)0x31); 4503 } 4504 4505 // copies data from [esi] to [edi] using rcx pointer sized words 4506 // generic 4507 void Assembler::rep_mov() { 4508 emit_int8((unsigned char)0xF3); 4509 // MOVSQ 4510 LP64_ONLY(prefix(REX_W)); 4511 emit_int8((unsigned char)0xA5); 4512 } 4513 4514 // sets rcx bytes with rax, value at [edi] 4515 void Assembler::rep_stosb() { 4516 emit_int8((unsigned char)0xF3); // REP 4517 LP64_ONLY(prefix(REX_W)); 4518 emit_int8((unsigned char)0xAA); // STOSB 4519 } 4520 4521 // sets rcx pointer sized words with rax, value at [edi] 4522 // generic 4523 void Assembler::rep_stos() { 4524 emit_int8((unsigned char)0xF3); // REP 4525 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD 4526 emit_int8((unsigned char)0xAB); 4527 } 4528 4529 // scans rcx pointer sized words at [edi] for occurance of rax, 4530 // generic 4531 void Assembler::repne_scan() { // repne_scan 4532 emit_int8((unsigned char)0xF2); 4533 // SCASQ 4534 LP64_ONLY(prefix(REX_W)); 4535 emit_int8((unsigned char)0xAF); 4536 } 4537 4538 #ifdef _LP64 4539 // scans rcx 4 byte words at [edi] for occurance of rax, 4540 // generic 4541 void Assembler::repne_scanl() { // repne_scan 4542 emit_int8((unsigned char)0xF2); 4543 // SCASL 4544 emit_int8((unsigned char)0xAF); 4545 } 4546 #endif 4547 4548 void Assembler::ret(int imm16) { 4549 if (imm16 == 0) { 4550 emit_int8((unsigned char)0xC3); 4551 } else { 4552 emit_int8((unsigned char)0xC2); 4553 emit_int16(imm16); 4554 } 4555 } 4556 4557 void Assembler::sahf() { 4558 #ifdef _LP64 4559 // Not supported in 64bit mode 4560 ShouldNotReachHere(); 4561 #endif 4562 emit_int8((unsigned char)0x9E); 4563 } 4564 4565 void Assembler::sarl(Register dst, int imm8) { 4566 int encode = prefix_and_encode(dst->encoding()); 4567 assert(isShiftCount(imm8), "illegal shift count"); 4568 if (imm8 == 1) { 4569 emit_int8((unsigned char)0xD1); 4570 emit_int8((unsigned char)(0xF8 | encode)); 4571 } else { 4572 emit_int8((unsigned char)0xC1); 4573 emit_int8((unsigned char)(0xF8 | encode)); 4574 emit_int8(imm8); 4575 } 4576 } 4577 4578 void Assembler::sarl(Register dst) { 4579 int encode = prefix_and_encode(dst->encoding()); 4580 emit_int8((unsigned char)0xD3); 4581 emit_int8((unsigned char)(0xF8 | encode)); 4582 } 4583 4584 void Assembler::sbbl(Address dst, int32_t imm32) { 4585 InstructionMark im(this); 4586 prefix(dst); 4587 emit_arith_operand(0x81, rbx, dst, imm32); 4588 } 4589 4590 void Assembler::sbbl(Register dst, int32_t imm32) { 4591 prefix(dst); 4592 emit_arith(0x81, 0xD8, dst, imm32); 4593 } 4594 4595 4596 void Assembler::sbbl(Register dst, Address src) { 4597 InstructionMark im(this); 4598 prefix(src, dst); 4599 emit_int8(0x1B); 4600 emit_operand(dst, src); 4601 } 4602 4603 void Assembler::sbbl(Register dst, Register src) { 4604 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4605 emit_arith(0x1B, 0xC0, dst, src); 4606 } 4607 4608 void Assembler::setb(Condition cc, Register dst) { 4609 assert(0 <= cc && cc < 16, "illegal cc"); 4610 int encode = prefix_and_encode(dst->encoding(), true); 4611 emit_int8(0x0F); 4612 emit_int8((unsigned char)0x90 | cc); 4613 emit_int8((unsigned char)(0xC0 | encode)); 4614 } 4615 4616 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) { 4617 assert(VM_Version::supports_ssse3(), ""); 4618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4619 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4620 emit_int8((unsigned char)0x0F); 4621 emit_int8((unsigned char)(0xC0 | encode)); 4622 emit_int8(imm8); 4623 } 4624 4625 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4626 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4627 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4628 0, ""); 4629 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 4630 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4631 emit_int8((unsigned char)0x0F); 4632 emit_int8((unsigned char)(0xC0 | encode)); 4633 emit_int8(imm8); 4634 } 4635 4636 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 4637 assert(VM_Version::supports_evex(), ""); 4638 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 4639 attributes.set_is_evex_instruction(); 4640 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4641 emit_int8(0x3); 4642 emit_int8((unsigned char)(0xC0 | encode)); 4643 emit_int8(imm8); 4644 } 4645 4646 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) { 4647 assert(VM_Version::supports_sse4_1(), ""); 4648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4649 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4650 emit_int8((unsigned char)0x0E); 4651 emit_int8((unsigned char)(0xC0 | encode)); 4652 emit_int8(imm8); 4653 } 4654 4655 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) { 4656 assert(VM_Version::supports_sha(), ""); 4657 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false); 4658 emit_int8((unsigned char)0xCC); 4659 emit_int8((unsigned char)(0xC0 | encode)); 4660 emit_int8((unsigned char)imm8); 4661 } 4662 4663 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) { 4664 assert(VM_Version::supports_sha(), ""); 4665 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4666 emit_int8((unsigned char)0xC8); 4667 emit_int8((unsigned char)(0xC0 | encode)); 4668 } 4669 4670 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) { 4671 assert(VM_Version::supports_sha(), ""); 4672 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4673 emit_int8((unsigned char)0xC9); 4674 emit_int8((unsigned char)(0xC0 | encode)); 4675 } 4676 4677 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) { 4678 assert(VM_Version::supports_sha(), ""); 4679 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4680 emit_int8((unsigned char)0xCA); 4681 emit_int8((unsigned char)(0xC0 | encode)); 4682 } 4683 4684 // xmm0 is implicit additional source to this instruction. 4685 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) { 4686 assert(VM_Version::supports_sha(), ""); 4687 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4688 emit_int8((unsigned char)0xCB); 4689 emit_int8((unsigned char)(0xC0 | encode)); 4690 } 4691 4692 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) { 4693 assert(VM_Version::supports_sha(), ""); 4694 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4695 emit_int8((unsigned char)0xCC); 4696 emit_int8((unsigned char)(0xC0 | encode)); 4697 } 4698 4699 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) { 4700 assert(VM_Version::supports_sha(), ""); 4701 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); 4702 emit_int8((unsigned char)0xCD); 4703 emit_int8((unsigned char)(0xC0 | encode)); 4704 } 4705 4706 4707 void Assembler::shll(Register dst, int imm8) { 4708 assert(isShiftCount(imm8), "illegal shift count"); 4709 int encode = prefix_and_encode(dst->encoding()); 4710 if (imm8 == 1 ) { 4711 emit_int8((unsigned char)0xD1); 4712 emit_int8((unsigned char)(0xE0 | encode)); 4713 } else { 4714 emit_int8((unsigned char)0xC1); 4715 emit_int8((unsigned char)(0xE0 | encode)); 4716 emit_int8(imm8); 4717 } 4718 } 4719 4720 void Assembler::shll(Register dst) { 4721 int encode = prefix_and_encode(dst->encoding()); 4722 emit_int8((unsigned char)0xD3); 4723 emit_int8((unsigned char)(0xE0 | encode)); 4724 } 4725 4726 void Assembler::shrl(Register dst, int imm8) { 4727 assert(isShiftCount(imm8), "illegal shift count"); 4728 int encode = prefix_and_encode(dst->encoding()); 4729 emit_int8((unsigned char)0xC1); 4730 emit_int8((unsigned char)(0xE8 | encode)); 4731 emit_int8(imm8); 4732 } 4733 4734 void Assembler::shrl(Register dst) { 4735 int encode = prefix_and_encode(dst->encoding()); 4736 emit_int8((unsigned char)0xD3); 4737 emit_int8((unsigned char)(0xE8 | encode)); 4738 } 4739 4740 // copies a single word from [esi] to [edi] 4741 void Assembler::smovl() { 4742 emit_int8((unsigned char)0xA5); 4743 } 4744 4745 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { 4746 assert(VM_Version::supports_sse4_1(), ""); 4747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4748 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4749 emit_int8(0x0B); 4750 emit_int8((unsigned char)(0xC0 | encode)); 4751 emit_int8((unsigned char)rmode); 4752 } 4753 4754 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) { 4755 assert(VM_Version::supports_sse4_1(), ""); 4756 InstructionMark im(this); 4757 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4758 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4759 emit_int8(0x0B); 4760 emit_operand(dst, src); 4761 emit_int8((unsigned char)rmode); 4762 } 4763 4764 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 4765 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4767 attributes.set_rex_vex_w_reverted(); 4768 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4769 emit_int8(0x51); 4770 emit_int8((unsigned char)(0xC0 | encode)); 4771 } 4772 4773 void Assembler::sqrtsd(XMMRegister dst, Address src) { 4774 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4775 InstructionMark im(this); 4776 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4777 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4778 attributes.set_rex_vex_w_reverted(); 4779 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4780 emit_int8(0x51); 4781 emit_operand(dst, src); 4782 } 4783 4784 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 4785 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4787 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4788 emit_int8(0x51); 4789 emit_int8((unsigned char)(0xC0 | encode)); 4790 } 4791 4792 void Assembler::std() { 4793 emit_int8((unsigned char)0xFD); 4794 } 4795 4796 void Assembler::sqrtss(XMMRegister dst, Address src) { 4797 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4798 InstructionMark im(this); 4799 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4800 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4801 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4802 emit_int8(0x51); 4803 emit_operand(dst, src); 4804 } 4805 4806 void Assembler::stmxcsr( Address dst) { 4807 if (UseAVX > 0 ) { 4808 assert(VM_Version::supports_avx(), ""); 4809 InstructionMark im(this); 4810 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 4811 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4812 emit_int8((unsigned char)0xAE); 4813 emit_operand(as_Register(3), dst); 4814 } else { 4815 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4816 InstructionMark im(this); 4817 prefix(dst); 4818 emit_int8(0x0F); 4819 emit_int8((unsigned char)0xAE); 4820 emit_operand(as_Register(3), dst); 4821 } 4822 } 4823 4824 void Assembler::subl(Address dst, int32_t imm32) { 4825 InstructionMark im(this); 4826 prefix(dst); 4827 emit_arith_operand(0x81, rbp, dst, imm32); 4828 } 4829 4830 void Assembler::subl(Address dst, Register src) { 4831 InstructionMark im(this); 4832 prefix(dst, src); 4833 emit_int8(0x29); 4834 emit_operand(src, dst); 4835 } 4836 4837 void Assembler::subl(Register dst, int32_t imm32) { 4838 prefix(dst); 4839 emit_arith(0x81, 0xE8, dst, imm32); 4840 } 4841 4842 // Force generation of a 4 byte immediate value even if it fits into 8bit 4843 void Assembler::subl_imm32(Register dst, int32_t imm32) { 4844 prefix(dst); 4845 emit_arith_imm32(0x81, 0xE8, dst, imm32); 4846 } 4847 4848 void Assembler::subl(Register dst, Address src) { 4849 InstructionMark im(this); 4850 prefix(src, dst); 4851 emit_int8(0x2B); 4852 emit_operand(dst, src); 4853 } 4854 4855 void Assembler::subl(Register dst, Register src) { 4856 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4857 emit_arith(0x2B, 0xC0, dst, src); 4858 } 4859 4860 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 4861 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4862 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4863 attributes.set_rex_vex_w_reverted(); 4864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4865 emit_int8(0x5C); 4866 emit_int8((unsigned char)(0xC0 | encode)); 4867 } 4868 4869 void Assembler::subsd(XMMRegister dst, Address src) { 4870 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4871 InstructionMark im(this); 4872 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4873 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4874 attributes.set_rex_vex_w_reverted(); 4875 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4876 emit_int8(0x5C); 4877 emit_operand(dst, src); 4878 } 4879 4880 void Assembler::subss(XMMRegister dst, XMMRegister src) { 4881 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false); 4883 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4884 emit_int8(0x5C); 4885 emit_int8((unsigned char)(0xC0 | encode)); 4886 } 4887 4888 void Assembler::subss(XMMRegister dst, Address src) { 4889 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4890 InstructionMark im(this); 4891 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4892 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4893 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4894 emit_int8(0x5C); 4895 emit_operand(dst, src); 4896 } 4897 4898 void Assembler::testb(Register dst, int imm8) { 4899 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 4900 (void) prefix_and_encode(dst->encoding(), true); 4901 emit_arith_b(0xF6, 0xC0, dst, imm8); 4902 } 4903 4904 void Assembler::testb(Address dst, int imm8) { 4905 InstructionMark im(this); 4906 prefix(dst); 4907 emit_int8((unsigned char)0xF6); 4908 emit_operand(rax, dst, 1); 4909 emit_int8(imm8); 4910 } 4911 4912 void Assembler::testl(Register dst, int32_t imm32) { 4913 // not using emit_arith because test 4914 // doesn't support sign-extension of 4915 // 8bit operands 4916 int encode = dst->encoding(); 4917 if (encode == 0) { 4918 emit_int8((unsigned char)0xA9); 4919 } else { 4920 encode = prefix_and_encode(encode); 4921 emit_int8((unsigned char)0xF7); 4922 emit_int8((unsigned char)(0xC0 | encode)); 4923 } 4924 emit_int32(imm32); 4925 } 4926 4927 void Assembler::testl(Register dst, Register src) { 4928 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4929 emit_arith(0x85, 0xC0, dst, src); 4930 } 4931 4932 void Assembler::testl(Register dst, Address src) { 4933 InstructionMark im(this); 4934 prefix(src, dst); 4935 emit_int8((unsigned char)0x85); 4936 emit_operand(dst, src); 4937 } 4938 4939 void Assembler::tzcntl(Register dst, Register src) { 4940 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4941 emit_int8((unsigned char)0xF3); 4942 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4943 emit_int8(0x0F); 4944 emit_int8((unsigned char)0xBC); 4945 emit_int8((unsigned char)0xC0 | encode); 4946 } 4947 4948 void Assembler::tzcntq(Register dst, Register src) { 4949 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4950 emit_int8((unsigned char)0xF3); 4951 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4952 emit_int8(0x0F); 4953 emit_int8((unsigned char)0xBC); 4954 emit_int8((unsigned char)(0xC0 | encode)); 4955 } 4956 4957 void Assembler::ucomisd(XMMRegister dst, Address src) { 4958 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4959 InstructionMark im(this); 4960 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4961 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4962 attributes.set_rex_vex_w_reverted(); 4963 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4964 emit_int8(0x2E); 4965 emit_operand(dst, src); 4966 } 4967 4968 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 4969 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4970 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4971 attributes.set_rex_vex_w_reverted(); 4972 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4973 emit_int8(0x2E); 4974 emit_int8((unsigned char)(0xC0 | encode)); 4975 } 4976 4977 void Assembler::ucomiss(XMMRegister dst, Address src) { 4978 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4979 InstructionMark im(this); 4980 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4981 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4982 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4983 emit_int8(0x2E); 4984 emit_operand(dst, src); 4985 } 4986 4987 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 4988 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4989 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4990 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4991 emit_int8(0x2E); 4992 emit_int8((unsigned char)(0xC0 | encode)); 4993 } 4994 4995 void Assembler::xabort(int8_t imm8) { 4996 emit_int8((unsigned char)0xC6); 4997 emit_int8((unsigned char)0xF8); 4998 emit_int8((unsigned char)(imm8 & 0xFF)); 4999 } 5000 5001 void Assembler::xaddb(Address dst, Register src) { 5002 InstructionMark im(this); 5003 prefix(dst, src, true); 5004 emit_int8(0x0F); 5005 emit_int8((unsigned char)0xC0); 5006 emit_operand(src, dst); 5007 } 5008 5009 void Assembler::xaddw(Address dst, Register src) { 5010 InstructionMark im(this); 5011 emit_int8(0x66); 5012 prefix(dst, src); 5013 emit_int8(0x0F); 5014 emit_int8((unsigned char)0xC1); 5015 emit_operand(src, dst); 5016 } 5017 5018 void Assembler::xaddl(Address dst, Register src) { 5019 InstructionMark im(this); 5020 prefix(dst, src); 5021 emit_int8(0x0F); 5022 emit_int8((unsigned char)0xC1); 5023 emit_operand(src, dst); 5024 } 5025 5026 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { 5027 InstructionMark im(this); 5028 relocate(rtype); 5029 if (abort.is_bound()) { 5030 address entry = target(abort); 5031 assert(entry != NULL, "abort entry NULL"); 5032 intptr_t offset = entry - pc(); 5033 emit_int8((unsigned char)0xC7); 5034 emit_int8((unsigned char)0xF8); 5035 emit_int32(offset - 6); // 2 opcode + 4 address 5036 } else { 5037 abort.add_patch_at(code(), locator()); 5038 emit_int8((unsigned char)0xC7); 5039 emit_int8((unsigned char)0xF8); 5040 emit_int32(0); 5041 } 5042 } 5043 5044 void Assembler::xchgb(Register dst, Address src) { // xchg 5045 InstructionMark im(this); 5046 prefix(src, dst, true); 5047 emit_int8((unsigned char)0x86); 5048 emit_operand(dst, src); 5049 } 5050 5051 void Assembler::xchgw(Register dst, Address src) { // xchg 5052 InstructionMark im(this); 5053 emit_int8(0x66); 5054 prefix(src, dst); 5055 emit_int8((unsigned char)0x87); 5056 emit_operand(dst, src); 5057 } 5058 5059 void Assembler::xchgl(Register dst, Address src) { // xchg 5060 InstructionMark im(this); 5061 prefix(src, dst); 5062 emit_int8((unsigned char)0x87); 5063 emit_operand(dst, src); 5064 } 5065 5066 void Assembler::xchgl(Register dst, Register src) { 5067 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 5068 emit_int8((unsigned char)0x87); 5069 emit_int8((unsigned char)(0xC0 | encode)); 5070 } 5071 5072 void Assembler::xend() { 5073 emit_int8((unsigned char)0x0F); 5074 emit_int8((unsigned char)0x01); 5075 emit_int8((unsigned char)0xD5); 5076 } 5077 5078 void Assembler::xgetbv() { 5079 emit_int8(0x0F); 5080 emit_int8(0x01); 5081 emit_int8((unsigned char)0xD0); 5082 } 5083 5084 void Assembler::xorl(Register dst, int32_t imm32) { 5085 prefix(dst); 5086 emit_arith(0x81, 0xF0, dst, imm32); 5087 } 5088 5089 void Assembler::xorl(Register dst, Address src) { 5090 InstructionMark im(this); 5091 prefix(src, dst); 5092 emit_int8(0x33); 5093 emit_operand(dst, src); 5094 } 5095 5096 void Assembler::xorl(Register dst, Register src) { 5097 (void) prefix_and_encode(dst->encoding(), src->encoding()); 5098 emit_arith(0x33, 0xC0, dst, src); 5099 } 5100 5101 void Assembler::xorb(Register dst, Address src) { 5102 InstructionMark im(this); 5103 prefix(src, dst); 5104 emit_int8(0x32); 5105 emit_operand(dst, src); 5106 } 5107 5108 // AVX 3-operands scalar float-point arithmetic instructions 5109 5110 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 5111 assert(VM_Version::supports_avx(), ""); 5112 InstructionMark im(this); 5113 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5114 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 5115 attributes.set_rex_vex_w_reverted(); 5116 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5117 emit_int8(0x58); 5118 emit_operand(dst, src); 5119 } 5120 5121 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5122 assert(VM_Version::supports_avx(), ""); 5123 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5124 attributes.set_rex_vex_w_reverted(); 5125 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5126 emit_int8(0x58); 5127 emit_int8((unsigned char)(0xC0 | encode)); 5128 } 5129 5130 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 5131 assert(VM_Version::supports_avx(), ""); 5132 InstructionMark im(this); 5133 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5134 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 5135 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5136 emit_int8(0x58); 5137 emit_operand(dst, src); 5138 } 5139 5140 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5141 assert(VM_Version::supports_avx(), ""); 5142 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5143 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5144 emit_int8(0x58); 5145 emit_int8((unsigned char)(0xC0 | encode)); 5146 } 5147 5148 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 5149 assert(VM_Version::supports_avx(), ""); 5150 InstructionMark im(this); 5151 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5152 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 5153 attributes.set_rex_vex_w_reverted(); 5154 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5155 emit_int8(0x5E); 5156 emit_operand(dst, src); 5157 } 5158 5159 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5160 assert(VM_Version::supports_avx(), ""); 5161 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5162 attributes.set_rex_vex_w_reverted(); 5163 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5164 emit_int8(0x5E); 5165 emit_int8((unsigned char)(0xC0 | encode)); 5166 } 5167 5168 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 5169 assert(VM_Version::supports_avx(), ""); 5170 InstructionMark im(this); 5171 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5172 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 5173 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5174 emit_int8(0x5E); 5175 emit_operand(dst, src); 5176 } 5177 5178 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5179 assert(VM_Version::supports_avx(), ""); 5180 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5181 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5182 emit_int8(0x5E); 5183 emit_int8((unsigned char)(0xC0 | encode)); 5184 } 5185 5186 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 5187 assert(VM_Version::supports_fma(), ""); 5188 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5189 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5190 emit_int8((unsigned char)0xB9); 5191 emit_int8((unsigned char)(0xC0 | encode)); 5192 } 5193 5194 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 5195 assert(VM_Version::supports_fma(), ""); 5196 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5197 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5198 emit_int8((unsigned char)0xB9); 5199 emit_int8((unsigned char)(0xC0 | encode)); 5200 } 5201 5202 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 5203 assert(VM_Version::supports_avx(), ""); 5204 InstructionMark im(this); 5205 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5206 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 5207 attributes.set_rex_vex_w_reverted(); 5208 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5209 emit_int8(0x59); 5210 emit_operand(dst, src); 5211 } 5212 5213 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5214 assert(VM_Version::supports_avx(), ""); 5215 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5216 attributes.set_rex_vex_w_reverted(); 5217 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5218 emit_int8(0x59); 5219 emit_int8((unsigned char)(0xC0 | encode)); 5220 } 5221 5222 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 5223 assert(VM_Version::supports_avx(), ""); 5224 InstructionMark im(this); 5225 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5226 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 5227 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5228 emit_int8(0x59); 5229 emit_operand(dst, src); 5230 } 5231 5232 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5233 assert(VM_Version::supports_avx(), ""); 5234 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5235 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5236 emit_int8(0x59); 5237 emit_int8((unsigned char)(0xC0 | encode)); 5238 } 5239 5240 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 5241 assert(VM_Version::supports_avx(), ""); 5242 InstructionMark im(this); 5243 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5244 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 5245 attributes.set_rex_vex_w_reverted(); 5246 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5247 emit_int8(0x5C); 5248 emit_operand(dst, src); 5249 } 5250 5251 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5252 assert(VM_Version::supports_avx(), ""); 5253 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5254 attributes.set_rex_vex_w_reverted(); 5255 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 5256 emit_int8(0x5C); 5257 emit_int8((unsigned char)(0xC0 | encode)); 5258 } 5259 5260 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 5261 assert(VM_Version::supports_avx(), ""); 5262 InstructionMark im(this); 5263 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5264 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 5265 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5266 emit_int8(0x5C); 5267 emit_operand(dst, src); 5268 } 5269 5270 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 5271 assert(VM_Version::supports_avx(), ""); 5272 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 5273 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 5274 emit_int8(0x5C); 5275 emit_int8((unsigned char)(0xC0 | encode)); 5276 } 5277 5278 //====================VECTOR ARITHMETIC===================================== 5279 5280 // Float-point vector arithmetic 5281 5282 void Assembler::addpd(XMMRegister dst, XMMRegister src) { 5283 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5284 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5285 attributes.set_rex_vex_w_reverted(); 5286 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5287 emit_int8(0x58); 5288 emit_int8((unsigned char)(0xC0 | encode)); 5289 } 5290 5291 void Assembler::addpd(XMMRegister dst, Address src) { 5292 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5293 InstructionMark im(this); 5294 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5295 attributes.set_rex_vex_w_reverted(); 5296 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5297 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5298 emit_int8(0x58); 5299 emit_operand(dst, src); 5300 } 5301 5302 5303 void Assembler::addps(XMMRegister dst, XMMRegister src) { 5304 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5306 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5307 emit_int8(0x58); 5308 emit_int8((unsigned char)(0xC0 | encode)); 5309 } 5310 5311 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5312 assert(VM_Version::supports_avx(), ""); 5313 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5314 attributes.set_rex_vex_w_reverted(); 5315 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5316 emit_int8(0x58); 5317 emit_int8((unsigned char)(0xC0 | encode)); 5318 } 5319 5320 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5321 assert(VM_Version::supports_avx(), ""); 5322 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5323 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5324 emit_int8(0x58); 5325 emit_int8((unsigned char)(0xC0 | encode)); 5326 } 5327 5328 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5329 assert(VM_Version::supports_avx(), ""); 5330 InstructionMark im(this); 5331 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5332 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5333 attributes.set_rex_vex_w_reverted(); 5334 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5335 emit_int8(0x58); 5336 emit_operand(dst, src); 5337 } 5338 5339 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5340 assert(VM_Version::supports_avx(), ""); 5341 InstructionMark im(this); 5342 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5343 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5344 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5345 emit_int8(0x58); 5346 emit_operand(dst, src); 5347 } 5348 5349 void Assembler::subpd(XMMRegister dst, XMMRegister src) { 5350 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5351 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5352 attributes.set_rex_vex_w_reverted(); 5353 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5354 emit_int8(0x5C); 5355 emit_int8((unsigned char)(0xC0 | encode)); 5356 } 5357 5358 void Assembler::subps(XMMRegister dst, XMMRegister src) { 5359 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5360 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5361 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5362 emit_int8(0x5C); 5363 emit_int8((unsigned char)(0xC0 | encode)); 5364 } 5365 5366 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5367 assert(VM_Version::supports_avx(), ""); 5368 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5369 attributes.set_rex_vex_w_reverted(); 5370 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5371 emit_int8(0x5C); 5372 emit_int8((unsigned char)(0xC0 | encode)); 5373 } 5374 5375 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5376 assert(VM_Version::supports_avx(), ""); 5377 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5378 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5379 emit_int8(0x5C); 5380 emit_int8((unsigned char)(0xC0 | encode)); 5381 } 5382 5383 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5384 assert(VM_Version::supports_avx(), ""); 5385 InstructionMark im(this); 5386 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5387 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5388 attributes.set_rex_vex_w_reverted(); 5389 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5390 emit_int8(0x5C); 5391 emit_operand(dst, src); 5392 } 5393 5394 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5395 assert(VM_Version::supports_avx(), ""); 5396 InstructionMark im(this); 5397 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5398 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5399 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5400 emit_int8(0x5C); 5401 emit_operand(dst, src); 5402 } 5403 5404 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { 5405 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5406 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5407 attributes.set_rex_vex_w_reverted(); 5408 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5409 emit_int8(0x59); 5410 emit_int8((unsigned char)(0xC0 | encode)); 5411 } 5412 5413 void Assembler::mulpd(XMMRegister dst, Address src) { 5414 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5415 InstructionMark im(this); 5416 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5417 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5418 attributes.set_rex_vex_w_reverted(); 5419 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5420 emit_int8(0x59); 5421 emit_operand(dst, src); 5422 } 5423 5424 void Assembler::mulps(XMMRegister dst, XMMRegister src) { 5425 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5426 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5427 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5428 emit_int8(0x59); 5429 emit_int8((unsigned char)(0xC0 | encode)); 5430 } 5431 5432 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5433 assert(VM_Version::supports_avx(), ""); 5434 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5435 attributes.set_rex_vex_w_reverted(); 5436 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5437 emit_int8(0x59); 5438 emit_int8((unsigned char)(0xC0 | encode)); 5439 } 5440 5441 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5442 assert(VM_Version::supports_avx(), ""); 5443 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5444 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5445 emit_int8(0x59); 5446 emit_int8((unsigned char)(0xC0 | encode)); 5447 } 5448 5449 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5450 assert(VM_Version::supports_avx(), ""); 5451 InstructionMark im(this); 5452 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5453 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5454 attributes.set_rex_vex_w_reverted(); 5455 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5456 emit_int8(0x59); 5457 emit_operand(dst, src); 5458 } 5459 5460 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5461 assert(VM_Version::supports_avx(), ""); 5462 InstructionMark im(this); 5463 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5464 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5465 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5466 emit_int8(0x59); 5467 emit_operand(dst, src); 5468 } 5469 5470 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5471 assert(VM_Version::supports_fma(), ""); 5472 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5473 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5474 emit_int8((unsigned char)0xB8); 5475 emit_int8((unsigned char)(0xC0 | encode)); 5476 } 5477 5478 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { 5479 assert(VM_Version::supports_fma(), ""); 5480 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5481 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5482 emit_int8((unsigned char)0xB8); 5483 emit_int8((unsigned char)(0xC0 | encode)); 5484 } 5485 5486 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5487 assert(VM_Version::supports_fma(), ""); 5488 InstructionMark im(this); 5489 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5490 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5491 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5492 emit_int8((unsigned char)0xB8); 5493 emit_operand(dst, src2); 5494 } 5495 5496 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { 5497 assert(VM_Version::supports_fma(), ""); 5498 InstructionMark im(this); 5499 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5500 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5501 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5502 emit_int8((unsigned char)0xB8); 5503 emit_operand(dst, src2); 5504 } 5505 5506 void Assembler::divpd(XMMRegister dst, XMMRegister src) { 5507 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5508 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5509 attributes.set_rex_vex_w_reverted(); 5510 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5511 emit_int8(0x5E); 5512 emit_int8((unsigned char)(0xC0 | encode)); 5513 } 5514 5515 void Assembler::divps(XMMRegister dst, XMMRegister src) { 5516 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5517 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5518 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5519 emit_int8(0x5E); 5520 emit_int8((unsigned char)(0xC0 | encode)); 5521 } 5522 5523 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5524 assert(VM_Version::supports_avx(), ""); 5525 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5526 attributes.set_rex_vex_w_reverted(); 5527 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5528 emit_int8(0x5E); 5529 emit_int8((unsigned char)(0xC0 | encode)); 5530 } 5531 5532 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5533 assert(VM_Version::supports_avx(), ""); 5534 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5535 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5536 emit_int8(0x5E); 5537 emit_int8((unsigned char)(0xC0 | encode)); 5538 } 5539 5540 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5541 assert(VM_Version::supports_avx(), ""); 5542 InstructionMark im(this); 5543 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5544 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5545 attributes.set_rex_vex_w_reverted(); 5546 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5547 emit_int8(0x5E); 5548 emit_operand(dst, src); 5549 } 5550 5551 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5552 assert(VM_Version::supports_avx(), ""); 5553 InstructionMark im(this); 5554 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5555 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5556 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5557 emit_int8(0x5E); 5558 emit_operand(dst, src); 5559 } 5560 5561 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { 5562 assert(VM_Version::supports_avx(), ""); 5563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 5564 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 5565 emit_int8(0x09); 5566 emit_int8((unsigned char)(0xC0 | encode)); 5567 emit_int8((unsigned char)(rmode)); 5568 } 5569 5570 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { 5571 assert(VM_Version::supports_avx(), ""); 5572 InstructionMark im(this); 5573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 5574 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 5575 emit_int8(0x09); 5576 emit_operand(dst, src); 5577 emit_int8((unsigned char)(rmode)); 5578 } 5579 5580 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { 5581 assert(VM_Version::supports_evex(), "requires EVEX support"); 5582 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5583 attributes.set_is_evex_instruction(); 5584 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 5585 emit_int8((unsigned char)0x09); 5586 emit_int8((unsigned char)(0xC0 | encode)); 5587 emit_int8((unsigned char)(rmode)); 5588 } 5589 5590 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { 5591 assert(VM_Version::supports_evex(), "requires EVEX support"); 5592 assert(dst != xnoreg, "sanity"); 5593 InstructionMark im(this); 5594 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5595 attributes.set_is_evex_instruction(); 5596 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5597 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 5598 emit_int8((unsigned char)0x09); 5599 emit_operand(dst, src); 5600 emit_int8((unsigned char)(rmode)); 5601 } 5602 5603 5604 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { 5605 assert(VM_Version::supports_avx(), ""); 5606 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5607 attributes.set_rex_vex_w_reverted(); 5608 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5609 emit_int8(0x51); 5610 emit_int8((unsigned char)(0xC0 | encode)); 5611 } 5612 5613 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { 5614 assert(VM_Version::supports_avx(), ""); 5615 InstructionMark im(this); 5616 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5617 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5618 attributes.set_rex_vex_w_reverted(); 5619 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5620 emit_int8(0x51); 5621 emit_operand(dst, src); 5622 } 5623 5624 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) { 5625 assert(VM_Version::supports_avx(), ""); 5626 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5627 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5628 emit_int8(0x51); 5629 emit_int8((unsigned char)(0xC0 | encode)); 5630 } 5631 5632 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) { 5633 assert(VM_Version::supports_avx(), ""); 5634 InstructionMark im(this); 5635 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5636 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5637 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5638 emit_int8(0x51); 5639 emit_operand(dst, src); 5640 } 5641 5642 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 5643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5644 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5645 attributes.set_rex_vex_w_reverted(); 5646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5647 emit_int8(0x54); 5648 emit_int8((unsigned char)(0xC0 | encode)); 5649 } 5650 5651 void Assembler::andps(XMMRegister dst, XMMRegister src) { 5652 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5653 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5654 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5655 emit_int8(0x54); 5656 emit_int8((unsigned char)(0xC0 | encode)); 5657 } 5658 5659 void Assembler::andps(XMMRegister dst, Address src) { 5660 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5661 InstructionMark im(this); 5662 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5663 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5664 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5665 emit_int8(0x54); 5666 emit_operand(dst, src); 5667 } 5668 5669 void Assembler::andpd(XMMRegister dst, Address src) { 5670 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5671 InstructionMark im(this); 5672 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5673 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5674 attributes.set_rex_vex_w_reverted(); 5675 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5676 emit_int8(0x54); 5677 emit_operand(dst, src); 5678 } 5679 5680 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5681 assert(VM_Version::supports_avx(), ""); 5682 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5683 attributes.set_rex_vex_w_reverted(); 5684 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5685 emit_int8(0x54); 5686 emit_int8((unsigned char)(0xC0 | encode)); 5687 } 5688 5689 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5690 assert(VM_Version::supports_avx(), ""); 5691 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5692 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5693 emit_int8(0x54); 5694 emit_int8((unsigned char)(0xC0 | encode)); 5695 } 5696 5697 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5698 assert(VM_Version::supports_avx(), ""); 5699 InstructionMark im(this); 5700 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5701 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5702 attributes.set_rex_vex_w_reverted(); 5703 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5704 emit_int8(0x54); 5705 emit_operand(dst, src); 5706 } 5707 5708 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5709 assert(VM_Version::supports_avx(), ""); 5710 InstructionMark im(this); 5711 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5712 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5713 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5714 emit_int8(0x54); 5715 emit_operand(dst, src); 5716 } 5717 5718 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) { 5719 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5720 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5721 attributes.set_rex_vex_w_reverted(); 5722 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5723 emit_int8(0x15); 5724 emit_int8((unsigned char)(0xC0 | encode)); 5725 } 5726 5727 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) { 5728 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5729 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5730 attributes.set_rex_vex_w_reverted(); 5731 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5732 emit_int8(0x14); 5733 emit_int8((unsigned char)(0xC0 | encode)); 5734 } 5735 5736 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 5737 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5738 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5739 attributes.set_rex_vex_w_reverted(); 5740 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5741 emit_int8(0x57); 5742 emit_int8((unsigned char)(0xC0 | encode)); 5743 } 5744 5745 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 5746 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5748 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5749 emit_int8(0x57); 5750 emit_int8((unsigned char)(0xC0 | encode)); 5751 } 5752 5753 void Assembler::xorpd(XMMRegister dst, Address src) { 5754 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5755 InstructionMark im(this); 5756 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5757 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5758 attributes.set_rex_vex_w_reverted(); 5759 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5760 emit_int8(0x57); 5761 emit_operand(dst, src); 5762 } 5763 5764 void Assembler::xorps(XMMRegister dst, Address src) { 5765 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5766 InstructionMark im(this); 5767 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5768 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5769 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5770 emit_int8(0x57); 5771 emit_operand(dst, src); 5772 } 5773 5774 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5775 assert(VM_Version::supports_avx(), ""); 5776 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5777 attributes.set_rex_vex_w_reverted(); 5778 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5779 emit_int8(0x57); 5780 emit_int8((unsigned char)(0xC0 | encode)); 5781 } 5782 5783 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5784 assert(VM_Version::supports_avx(), ""); 5785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5786 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5787 emit_int8(0x57); 5788 emit_int8((unsigned char)(0xC0 | encode)); 5789 } 5790 5791 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5792 assert(VM_Version::supports_avx(), ""); 5793 InstructionMark im(this); 5794 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5795 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5796 attributes.set_rex_vex_w_reverted(); 5797 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5798 emit_int8(0x57); 5799 emit_operand(dst, src); 5800 } 5801 5802 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5803 assert(VM_Version::supports_avx(), ""); 5804 InstructionMark im(this); 5805 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 5806 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5807 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5808 emit_int8(0x57); 5809 emit_operand(dst, src); 5810 } 5811 5812 // Integer vector arithmetic 5813 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5814 assert(VM_Version::supports_avx() && (vector_len == 0) || 5815 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5816 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 5817 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5818 emit_int8(0x01); 5819 emit_int8((unsigned char)(0xC0 | encode)); 5820 } 5821 5822 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5823 assert(VM_Version::supports_avx() && (vector_len == 0) || 5824 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5825 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 5826 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5827 emit_int8(0x02); 5828 emit_int8((unsigned char)(0xC0 | encode)); 5829 } 5830 5831 void Assembler::paddb(XMMRegister dst, XMMRegister src) { 5832 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5833 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5834 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5835 emit_int8((unsigned char)0xFC); 5836 emit_int8((unsigned char)(0xC0 | encode)); 5837 } 5838 5839 void Assembler::paddw(XMMRegister dst, XMMRegister src) { 5840 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5841 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5842 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5843 emit_int8((unsigned char)0xFD); 5844 emit_int8((unsigned char)(0xC0 | encode)); 5845 } 5846 5847 void Assembler::paddd(XMMRegister dst, XMMRegister src) { 5848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5850 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5851 emit_int8((unsigned char)0xFE); 5852 emit_int8((unsigned char)(0xC0 | encode)); 5853 } 5854 5855 void Assembler::paddd(XMMRegister dst, Address src) { 5856 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5857 InstructionMark im(this); 5858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5859 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5860 emit_int8((unsigned char)0xFE); 5861 emit_operand(dst, src); 5862 } 5863 5864 void Assembler::paddq(XMMRegister dst, XMMRegister src) { 5865 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5866 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5867 attributes.set_rex_vex_w_reverted(); 5868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5869 emit_int8((unsigned char)0xD4); 5870 emit_int8((unsigned char)(0xC0 | encode)); 5871 } 5872 5873 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { 5874 assert(VM_Version::supports_sse3(), ""); 5875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 5876 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5877 emit_int8(0x01); 5878 emit_int8((unsigned char)(0xC0 | encode)); 5879 } 5880 5881 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { 5882 assert(VM_Version::supports_sse3(), ""); 5883 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 5884 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5885 emit_int8(0x02); 5886 emit_int8((unsigned char)(0xC0 | encode)); 5887 } 5888 5889 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5890 assert(UseAVX > 0, "requires some form of AVX"); 5891 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5892 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5893 emit_int8((unsigned char)0xFC); 5894 emit_int8((unsigned char)(0xC0 | encode)); 5895 } 5896 5897 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5898 assert(UseAVX > 0, "requires some form of AVX"); 5899 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5900 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5901 emit_int8((unsigned char)0xFD); 5902 emit_int8((unsigned char)(0xC0 | encode)); 5903 } 5904 5905 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5906 assert(UseAVX > 0, "requires some form of AVX"); 5907 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5908 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5909 emit_int8((unsigned char)0xFE); 5910 emit_int8((unsigned char)(0xC0 | encode)); 5911 } 5912 5913 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5914 assert(UseAVX > 0, "requires some form of AVX"); 5915 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5916 attributes.set_rex_vex_w_reverted(); 5917 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5918 emit_int8((unsigned char)0xD4); 5919 emit_int8((unsigned char)(0xC0 | encode)); 5920 } 5921 5922 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5923 assert(UseAVX > 0, "requires some form of AVX"); 5924 InstructionMark im(this); 5925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5926 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5927 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5928 emit_int8((unsigned char)0xFC); 5929 emit_operand(dst, src); 5930 } 5931 5932 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5933 assert(UseAVX > 0, "requires some form of AVX"); 5934 InstructionMark im(this); 5935 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5936 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5937 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5938 emit_int8((unsigned char)0xFD); 5939 emit_operand(dst, src); 5940 } 5941 5942 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5943 assert(UseAVX > 0, "requires some form of AVX"); 5944 InstructionMark im(this); 5945 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5946 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5947 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5948 emit_int8((unsigned char)0xFE); 5949 emit_operand(dst, src); 5950 } 5951 5952 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5953 assert(UseAVX > 0, "requires some form of AVX"); 5954 InstructionMark im(this); 5955 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5956 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5957 attributes.set_rex_vex_w_reverted(); 5958 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5959 emit_int8((unsigned char)0xD4); 5960 emit_operand(dst, src); 5961 } 5962 5963 void Assembler::psubb(XMMRegister dst, XMMRegister src) { 5964 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5965 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5966 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5967 emit_int8((unsigned char)0xF8); 5968 emit_int8((unsigned char)(0xC0 | encode)); 5969 } 5970 5971 void Assembler::psubw(XMMRegister dst, XMMRegister src) { 5972 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5973 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5974 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5975 emit_int8((unsigned char)0xF9); 5976 emit_int8((unsigned char)(0xC0 | encode)); 5977 } 5978 5979 void Assembler::psubd(XMMRegister dst, XMMRegister src) { 5980 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5981 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5982 emit_int8((unsigned char)0xFA); 5983 emit_int8((unsigned char)(0xC0 | encode)); 5984 } 5985 5986 void Assembler::psubq(XMMRegister dst, XMMRegister src) { 5987 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5988 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 5989 attributes.set_rex_vex_w_reverted(); 5990 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5991 emit_int8((unsigned char)0xFB); 5992 emit_int8((unsigned char)(0xC0 | encode)); 5993 } 5994 5995 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5996 assert(UseAVX > 0, "requires some form of AVX"); 5997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5998 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5999 emit_int8((unsigned char)0xF8); 6000 emit_int8((unsigned char)(0xC0 | encode)); 6001 } 6002 6003 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6004 assert(UseAVX > 0, "requires some form of AVX"); 6005 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6006 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6007 emit_int8((unsigned char)0xF9); 6008 emit_int8((unsigned char)(0xC0 | encode)); 6009 } 6010 6011 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6012 assert(UseAVX > 0, "requires some form of AVX"); 6013 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6014 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6015 emit_int8((unsigned char)0xFA); 6016 emit_int8((unsigned char)(0xC0 | encode)); 6017 } 6018 6019 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6020 assert(UseAVX > 0, "requires some form of AVX"); 6021 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6022 attributes.set_rex_vex_w_reverted(); 6023 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6024 emit_int8((unsigned char)0xFB); 6025 emit_int8((unsigned char)(0xC0 | encode)); 6026 } 6027 6028 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6029 assert(UseAVX > 0, "requires some form of AVX"); 6030 InstructionMark im(this); 6031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6032 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 6033 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6034 emit_int8((unsigned char)0xF8); 6035 emit_operand(dst, src); 6036 } 6037 6038 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6039 assert(UseAVX > 0, "requires some form of AVX"); 6040 InstructionMark im(this); 6041 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6042 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 6043 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6044 emit_int8((unsigned char)0xF9); 6045 emit_operand(dst, src); 6046 } 6047 6048 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6049 assert(UseAVX > 0, "requires some form of AVX"); 6050 InstructionMark im(this); 6051 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6052 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6053 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6054 emit_int8((unsigned char)0xFA); 6055 emit_operand(dst, src); 6056 } 6057 6058 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6059 assert(UseAVX > 0, "requires some form of AVX"); 6060 InstructionMark im(this); 6061 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6062 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 6063 attributes.set_rex_vex_w_reverted(); 6064 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6065 emit_int8((unsigned char)0xFB); 6066 emit_operand(dst, src); 6067 } 6068 6069 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { 6070 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6071 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6072 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6073 emit_int8((unsigned char)0xD5); 6074 emit_int8((unsigned char)(0xC0 | encode)); 6075 } 6076 6077 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { 6078 assert(VM_Version::supports_sse4_1(), ""); 6079 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6080 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6081 emit_int8(0x40); 6082 emit_int8((unsigned char)(0xC0 | encode)); 6083 } 6084 6085 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6086 assert(UseAVX > 0, "requires some form of AVX"); 6087 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6088 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6089 emit_int8((unsigned char)0xD5); 6090 emit_int8((unsigned char)(0xC0 | encode)); 6091 } 6092 6093 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6094 assert(UseAVX > 0, "requires some form of AVX"); 6095 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6096 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6097 emit_int8(0x40); 6098 emit_int8((unsigned char)(0xC0 | encode)); 6099 } 6100 6101 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6102 assert(UseAVX > 2, "requires some form of EVEX"); 6103 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 6104 attributes.set_is_evex_instruction(); 6105 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6106 emit_int8(0x40); 6107 emit_int8((unsigned char)(0xC0 | encode)); 6108 } 6109 6110 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6111 assert(UseAVX > 0, "requires some form of AVX"); 6112 InstructionMark im(this); 6113 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6114 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 6115 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6116 emit_int8((unsigned char)0xD5); 6117 emit_operand(dst, src); 6118 } 6119 6120 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6121 assert(UseAVX > 0, "requires some form of AVX"); 6122 InstructionMark im(this); 6123 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6124 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6125 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6126 emit_int8(0x40); 6127 emit_operand(dst, src); 6128 } 6129 6130 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6131 assert(UseAVX > 2, "requires some form of EVEX"); 6132 InstructionMark im(this); 6133 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); 6134 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 6135 attributes.set_is_evex_instruction(); 6136 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6137 emit_int8(0x40); 6138 emit_operand(dst, src); 6139 } 6140 6141 // Shift packed integers left by specified number of bits. 6142 void Assembler::psllw(XMMRegister dst, int shift) { 6143 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6144 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6145 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 6146 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6147 emit_int8(0x71); 6148 emit_int8((unsigned char)(0xC0 | encode)); 6149 emit_int8(shift & 0xFF); 6150 } 6151 6152 void Assembler::pslld(XMMRegister dst, int shift) { 6153 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6154 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6155 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 6156 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6157 emit_int8(0x72); 6158 emit_int8((unsigned char)(0xC0 | encode)); 6159 emit_int8(shift & 0xFF); 6160 } 6161 6162 void Assembler::psllq(XMMRegister dst, int shift) { 6163 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6164 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6165 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 6166 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6167 emit_int8(0x73); 6168 emit_int8((unsigned char)(0xC0 | encode)); 6169 emit_int8(shift & 0xFF); 6170 } 6171 6172 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { 6173 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6175 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6176 emit_int8((unsigned char)0xF1); 6177 emit_int8((unsigned char)(0xC0 | encode)); 6178 } 6179 6180 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { 6181 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6183 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6184 emit_int8((unsigned char)0xF2); 6185 emit_int8((unsigned char)(0xC0 | encode)); 6186 } 6187 6188 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { 6189 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6190 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6191 attributes.set_rex_vex_w_reverted(); 6192 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6193 emit_int8((unsigned char)0xF3); 6194 emit_int8((unsigned char)(0xC0 | encode)); 6195 } 6196 6197 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6198 assert(UseAVX > 0, "requires some form of AVX"); 6199 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6200 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 6201 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6202 emit_int8(0x71); 6203 emit_int8((unsigned char)(0xC0 | encode)); 6204 emit_int8(shift & 0xFF); 6205 } 6206 6207 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6208 assert(UseAVX > 0, "requires some form of AVX"); 6209 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6210 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6211 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 6212 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6213 emit_int8(0x72); 6214 emit_int8((unsigned char)(0xC0 | encode)); 6215 emit_int8(shift & 0xFF); 6216 } 6217 6218 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6219 assert(UseAVX > 0, "requires some form of AVX"); 6220 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6221 attributes.set_rex_vex_w_reverted(); 6222 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 6223 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6224 emit_int8(0x73); 6225 emit_int8((unsigned char)(0xC0 | encode)); 6226 emit_int8(shift & 0xFF); 6227 } 6228 6229 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6230 assert(UseAVX > 0, "requires some form of AVX"); 6231 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6232 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6233 emit_int8((unsigned char)0xF1); 6234 emit_int8((unsigned char)(0xC0 | encode)); 6235 } 6236 6237 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6238 assert(UseAVX > 0, "requires some form of AVX"); 6239 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6240 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6241 emit_int8((unsigned char)0xF2); 6242 emit_int8((unsigned char)(0xC0 | encode)); 6243 } 6244 6245 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6246 assert(UseAVX > 0, "requires some form of AVX"); 6247 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6248 attributes.set_rex_vex_w_reverted(); 6249 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6250 emit_int8((unsigned char)0xF3); 6251 emit_int8((unsigned char)(0xC0 | encode)); 6252 } 6253 6254 // Shift packed integers logically right by specified number of bits. 6255 void Assembler::psrlw(XMMRegister dst, int shift) { 6256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6258 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 6259 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6260 emit_int8(0x71); 6261 emit_int8((unsigned char)(0xC0 | encode)); 6262 emit_int8(shift & 0xFF); 6263 } 6264 6265 void Assembler::psrld(XMMRegister dst, int shift) { 6266 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6268 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 6269 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6270 emit_int8(0x72); 6271 emit_int8((unsigned char)(0xC0 | encode)); 6272 emit_int8(shift & 0xFF); 6273 } 6274 6275 void Assembler::psrlq(XMMRegister dst, int shift) { 6276 // Do not confuse it with psrldq SSE2 instruction which 6277 // shifts 128 bit value in xmm register by number of bytes. 6278 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6279 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6280 attributes.set_rex_vex_w_reverted(); 6281 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 6282 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6283 emit_int8(0x73); 6284 emit_int8((unsigned char)(0xC0 | encode)); 6285 emit_int8(shift & 0xFF); 6286 } 6287 6288 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { 6289 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6290 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6291 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6292 emit_int8((unsigned char)0xD1); 6293 emit_int8((unsigned char)(0xC0 | encode)); 6294 } 6295 6296 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { 6297 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6299 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6300 emit_int8((unsigned char)0xD2); 6301 emit_int8((unsigned char)(0xC0 | encode)); 6302 } 6303 6304 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { 6305 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6306 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6307 attributes.set_rex_vex_w_reverted(); 6308 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6309 emit_int8((unsigned char)0xD3); 6310 emit_int8((unsigned char)(0xC0 | encode)); 6311 } 6312 6313 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6314 assert(UseAVX > 0, "requires some form of AVX"); 6315 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6316 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 6317 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6318 emit_int8(0x71); 6319 emit_int8((unsigned char)(0xC0 | encode)); 6320 emit_int8(shift & 0xFF); 6321 } 6322 6323 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6324 assert(UseAVX > 0, "requires some form of AVX"); 6325 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6326 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 6327 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6328 emit_int8(0x72); 6329 emit_int8((unsigned char)(0xC0 | encode)); 6330 emit_int8(shift & 0xFF); 6331 } 6332 6333 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6334 assert(UseAVX > 0, "requires some form of AVX"); 6335 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6336 attributes.set_rex_vex_w_reverted(); 6337 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 6338 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6339 emit_int8(0x73); 6340 emit_int8((unsigned char)(0xC0 | encode)); 6341 emit_int8(shift & 0xFF); 6342 } 6343 6344 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6345 assert(UseAVX > 0, "requires some form of AVX"); 6346 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6347 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6348 emit_int8((unsigned char)0xD1); 6349 emit_int8((unsigned char)(0xC0 | encode)); 6350 } 6351 6352 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6353 assert(UseAVX > 0, "requires some form of AVX"); 6354 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6355 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6356 emit_int8((unsigned char)0xD2); 6357 emit_int8((unsigned char)(0xC0 | encode)); 6358 } 6359 6360 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6361 assert(UseAVX > 0, "requires some form of AVX"); 6362 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6363 attributes.set_rex_vex_w_reverted(); 6364 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6365 emit_int8((unsigned char)0xD3); 6366 emit_int8((unsigned char)(0xC0 | encode)); 6367 } 6368 6369 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6370 assert(VM_Version::supports_avx512bw(), ""); 6371 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6372 attributes.set_is_evex_instruction(); 6373 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6374 emit_int8(0x10); 6375 emit_int8((unsigned char)(0xC0 | encode)); 6376 } 6377 6378 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6379 assert(VM_Version::supports_avx512bw(), ""); 6380 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6381 attributes.set_is_evex_instruction(); 6382 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6383 emit_int8(0x12); 6384 emit_int8((unsigned char)(0xC0 | encode)); 6385 } 6386 6387 // Shift packed integers arithmetically right by specified number of bits. 6388 void Assembler::psraw(XMMRegister dst, int shift) { 6389 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6391 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 6392 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6393 emit_int8(0x71); 6394 emit_int8((unsigned char)(0xC0 | encode)); 6395 emit_int8(shift & 0xFF); 6396 } 6397 6398 void Assembler::psrad(XMMRegister dst, int shift) { 6399 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6401 // XMM4 is for /4 encoding: 66 0F 72 /4 ib 6402 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6403 emit_int8(0x72); 6404 emit_int8((unsigned char)(0xC0 | encode)); 6405 emit_int8(shift & 0xFF); 6406 } 6407 6408 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { 6409 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6410 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6411 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6412 emit_int8((unsigned char)0xE1); 6413 emit_int8((unsigned char)(0xC0 | encode)); 6414 } 6415 6416 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { 6417 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6418 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6419 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6420 emit_int8((unsigned char)0xE2); 6421 emit_int8((unsigned char)(0xC0 | encode)); 6422 } 6423 6424 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6425 assert(UseAVX > 0, "requires some form of AVX"); 6426 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6427 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 6428 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6429 emit_int8(0x71); 6430 emit_int8((unsigned char)(0xC0 | encode)); 6431 emit_int8(shift & 0xFF); 6432 } 6433 6434 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6435 assert(UseAVX > 0, "requires some form of AVX"); 6436 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6437 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 6438 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6439 emit_int8(0x72); 6440 emit_int8((unsigned char)(0xC0 | encode)); 6441 emit_int8(shift & 0xFF); 6442 } 6443 6444 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6445 assert(UseAVX > 0, "requires some form of AVX"); 6446 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6447 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6448 emit_int8((unsigned char)0xE1); 6449 emit_int8((unsigned char)(0xC0 | encode)); 6450 } 6451 6452 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6453 assert(UseAVX > 0, "requires some form of AVX"); 6454 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6455 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6456 emit_int8((unsigned char)0xE2); 6457 emit_int8((unsigned char)(0xC0 | encode)); 6458 } 6459 6460 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 6461 assert(UseAVX > 2, "requires AVX512"); 6462 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl"); 6463 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6464 attributes.set_is_evex_instruction(); 6465 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6466 emit_int8((unsigned char)0x72); 6467 emit_int8((unsigned char)(0xC0 | encode)); 6468 emit_int8(shift & 0xFF); 6469 } 6470 6471 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 6472 assert(UseAVX > 2, "requires AVX512"); 6473 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl"); 6474 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6475 attributes.set_is_evex_instruction(); 6476 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6477 emit_int8((unsigned char)0xE2); 6478 emit_int8((unsigned char)(0xC0 | encode)); 6479 } 6480 6481 // logical operations packed integers 6482 void Assembler::pand(XMMRegister dst, XMMRegister src) { 6483 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6484 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6485 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6486 emit_int8((unsigned char)0xDB); 6487 emit_int8((unsigned char)(0xC0 | encode)); 6488 } 6489 6490 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6491 assert(UseAVX > 0, "requires some form of AVX"); 6492 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6493 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6494 emit_int8((unsigned char)0xDB); 6495 emit_int8((unsigned char)(0xC0 | encode)); 6496 } 6497 6498 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6499 assert(UseAVX > 0, "requires some form of AVX"); 6500 InstructionMark im(this); 6501 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6502 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6503 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6504 emit_int8((unsigned char)0xDB); 6505 emit_operand(dst, src); 6506 } 6507 6508 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6509 assert(VM_Version::supports_evex(), ""); 6510 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6511 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6512 emit_int8((unsigned char)0xDB); 6513 emit_int8((unsigned char)(0xC0 | encode)); 6514 } 6515 6516 6517 void Assembler::pandn(XMMRegister dst, XMMRegister src) { 6518 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6519 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6520 attributes.set_rex_vex_w_reverted(); 6521 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6522 emit_int8((unsigned char)0xDF); 6523 emit_int8((unsigned char)(0xC0 | encode)); 6524 } 6525 6526 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6527 assert(UseAVX > 0, "requires some form of AVX"); 6528 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6529 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6530 emit_int8((unsigned char)0xDF); 6531 emit_int8((unsigned char)(0xC0 | encode)); 6532 } 6533 6534 6535 void Assembler::por(XMMRegister dst, XMMRegister src) { 6536 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6537 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6538 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6539 emit_int8((unsigned char)0xEB); 6540 emit_int8((unsigned char)(0xC0 | encode)); 6541 } 6542 6543 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6544 assert(UseAVX > 0, "requires some form of AVX"); 6545 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6546 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6547 emit_int8((unsigned char)0xEB); 6548 emit_int8((unsigned char)(0xC0 | encode)); 6549 } 6550 6551 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6552 assert(UseAVX > 0, "requires some form of AVX"); 6553 InstructionMark im(this); 6554 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6555 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6556 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6557 emit_int8((unsigned char)0xEB); 6558 emit_operand(dst, src); 6559 } 6560 6561 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6562 assert(VM_Version::supports_evex(), ""); 6563 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6564 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6565 emit_int8((unsigned char)0xEB); 6566 emit_int8((unsigned char)(0xC0 | encode)); 6567 } 6568 6569 6570 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 6571 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6572 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6573 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6574 emit_int8((unsigned char)0xEF); 6575 emit_int8((unsigned char)(0xC0 | encode)); 6576 } 6577 6578 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6579 assert(UseAVX > 0, "requires some form of AVX"); 6580 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6581 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6582 emit_int8((unsigned char)0xEF); 6583 emit_int8((unsigned char)(0xC0 | encode)); 6584 } 6585 6586 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6587 assert(UseAVX > 0, "requires some form of AVX"); 6588 InstructionMark im(this); 6589 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6590 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6591 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6592 emit_int8((unsigned char)0xEF); 6593 emit_operand(dst, src); 6594 } 6595 6596 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 6597 assert(VM_Version::supports_evex(), "requires EVEX support"); 6598 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6599 attributes.set_is_evex_instruction(); 6600 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6601 emit_int8((unsigned char)0xEF); 6602 emit_int8((unsigned char)(0xC0 | encode)); 6603 } 6604 6605 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6606 assert(VM_Version::supports_evex(), "requires EVEX support"); 6607 assert(dst != xnoreg, "sanity"); 6608 InstructionMark im(this); 6609 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6610 attributes.set_is_evex_instruction(); 6611 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 6612 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6613 emit_int8((unsigned char)0xEF); 6614 emit_operand(dst, src); 6615 } 6616 6617 6618 // vinserti forms 6619 6620 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6621 assert(VM_Version::supports_avx2(), ""); 6622 assert(imm8 <= 0x01, "imm8: %u", imm8); 6623 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6624 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6625 emit_int8(0x38); 6626 emit_int8((unsigned char)(0xC0 | encode)); 6627 // 0x00 - insert into lower 128 bits 6628 // 0x01 - insert into upper 128 bits 6629 emit_int8(imm8 & 0x01); 6630 } 6631 6632 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6633 assert(VM_Version::supports_avx2(), ""); 6634 assert(dst != xnoreg, "sanity"); 6635 assert(imm8 <= 0x01, "imm8: %u", imm8); 6636 InstructionMark im(this); 6637 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6638 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6639 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6640 emit_int8(0x38); 6641 emit_operand(dst, src); 6642 // 0x00 - insert into lower 128 bits 6643 // 0x01 - insert into upper 128 bits 6644 emit_int8(imm8 & 0x01); 6645 } 6646 6647 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6648 assert(VM_Version::supports_evex(), ""); 6649 assert(imm8 <= 0x03, "imm8: %u", imm8); 6650 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6651 attributes.set_is_evex_instruction(); 6652 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6653 emit_int8(0x38); 6654 emit_int8((unsigned char)(0xC0 | encode)); 6655 // 0x00 - insert into q0 128 bits (0..127) 6656 // 0x01 - insert into q1 128 bits (128..255) 6657 // 0x02 - insert into q2 128 bits (256..383) 6658 // 0x03 - insert into q3 128 bits (384..511) 6659 emit_int8(imm8 & 0x03); 6660 } 6661 6662 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6663 assert(VM_Version::supports_avx(), ""); 6664 assert(dst != xnoreg, "sanity"); 6665 assert(imm8 <= 0x03, "imm8: %u", imm8); 6666 InstructionMark im(this); 6667 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6668 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6669 attributes.set_is_evex_instruction(); 6670 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6671 emit_int8(0x18); 6672 emit_operand(dst, src); 6673 // 0x00 - insert into q0 128 bits (0..127) 6674 // 0x01 - insert into q1 128 bits (128..255) 6675 // 0x02 - insert into q2 128 bits (256..383) 6676 // 0x03 - insert into q3 128 bits (384..511) 6677 emit_int8(imm8 & 0x03); 6678 } 6679 6680 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6681 assert(VM_Version::supports_evex(), ""); 6682 assert(imm8 <= 0x01, "imm8: %u", imm8); 6683 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6684 attributes.set_is_evex_instruction(); 6685 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6686 emit_int8(0x3A); 6687 emit_int8((unsigned char)(0xC0 | encode)); 6688 // 0x00 - insert into lower 256 bits 6689 // 0x01 - insert into upper 256 bits 6690 emit_int8(imm8 & 0x01); 6691 } 6692 6693 6694 // vinsertf forms 6695 6696 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6697 assert(VM_Version::supports_avx(), ""); 6698 assert(imm8 <= 0x01, "imm8: %u", imm8); 6699 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6700 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6701 emit_int8(0x18); 6702 emit_int8((unsigned char)(0xC0 | encode)); 6703 // 0x00 - insert into lower 128 bits 6704 // 0x01 - insert into upper 128 bits 6705 emit_int8(imm8 & 0x01); 6706 } 6707 6708 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6709 assert(VM_Version::supports_avx(), ""); 6710 assert(dst != xnoreg, "sanity"); 6711 assert(imm8 <= 0x01, "imm8: %u", imm8); 6712 InstructionMark im(this); 6713 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6714 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6715 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6716 emit_int8(0x18); 6717 emit_operand(dst, src); 6718 // 0x00 - insert into lower 128 bits 6719 // 0x01 - insert into upper 128 bits 6720 emit_int8(imm8 & 0x01); 6721 } 6722 6723 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6724 assert(VM_Version::supports_avx2(), ""); 6725 assert(imm8 <= 0x03, "imm8: %u", imm8); 6726 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6727 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6728 emit_int8(0x18); 6729 emit_int8((unsigned char)(0xC0 | encode)); 6730 // 0x00 - insert into q0 128 bits (0..127) 6731 // 0x01 - insert into q1 128 bits (128..255) 6732 // 0x02 - insert into q0 128 bits (256..383) 6733 // 0x03 - insert into q1 128 bits (384..512) 6734 emit_int8(imm8 & 0x03); 6735 } 6736 6737 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6738 assert(VM_Version::supports_avx(), ""); 6739 assert(dst != xnoreg, "sanity"); 6740 assert(imm8 <= 0x03, "imm8: %u", imm8); 6741 InstructionMark im(this); 6742 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6743 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6744 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6745 emit_int8(0x18); 6746 emit_operand(dst, src); 6747 // 0x00 - insert into q0 128 bits (0..127) 6748 // 0x01 - insert into q1 128 bits (128..255) 6749 // 0x02 - insert into q0 128 bits (256..383) 6750 // 0x03 - insert into q1 128 bits (384..512) 6751 emit_int8(imm8 & 0x03); 6752 } 6753 6754 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6755 assert(VM_Version::supports_evex(), ""); 6756 assert(imm8 <= 0x01, "imm8: %u", imm8); 6757 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6758 attributes.set_is_evex_instruction(); 6759 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6760 emit_int8(0x1A); 6761 emit_int8((unsigned char)(0xC0 | encode)); 6762 // 0x00 - insert into lower 256 bits 6763 // 0x01 - insert into upper 256 bits 6764 emit_int8(imm8 & 0x01); 6765 } 6766 6767 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6768 assert(VM_Version::supports_evex(), ""); 6769 assert(dst != xnoreg, "sanity"); 6770 assert(imm8 <= 0x01, "imm8: %u", imm8); 6771 InstructionMark im(this); 6772 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6773 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6774 attributes.set_is_evex_instruction(); 6775 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6776 emit_int8(0x1A); 6777 emit_operand(dst, src); 6778 // 0x00 - insert into lower 256 bits 6779 // 0x01 - insert into upper 256 bits 6780 emit_int8(imm8 & 0x01); 6781 } 6782 6783 6784 // vextracti forms 6785 6786 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6787 assert(VM_Version::supports_avx2(), ""); 6788 assert(imm8 <= 0x01, "imm8: %u", imm8); 6789 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6790 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6791 emit_int8(0x39); 6792 emit_int8((unsigned char)(0xC0 | encode)); 6793 // 0x00 - extract from lower 128 bits 6794 // 0x01 - extract from upper 128 bits 6795 emit_int8(imm8 & 0x01); 6796 } 6797 6798 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 6799 assert(VM_Version::supports_avx2(), ""); 6800 assert(src != xnoreg, "sanity"); 6801 assert(imm8 <= 0x01, "imm8: %u", imm8); 6802 InstructionMark im(this); 6803 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6804 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6805 attributes.reset_is_clear_context(); 6806 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6807 emit_int8(0x39); 6808 emit_operand(src, dst); 6809 // 0x00 - extract from lower 128 bits 6810 // 0x01 - extract from upper 128 bits 6811 emit_int8(imm8 & 0x01); 6812 } 6813 6814 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6815 assert(VM_Version::supports_evex(), ""); 6816 assert(imm8 <= 0x03, "imm8: %u", imm8); 6817 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6818 attributes.set_is_evex_instruction(); 6819 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6820 emit_int8(0x39); 6821 emit_int8((unsigned char)(0xC0 | encode)); 6822 // 0x00 - extract from bits 127:0 6823 // 0x01 - extract from bits 255:128 6824 // 0x02 - extract from bits 383:256 6825 // 0x03 - extract from bits 511:384 6826 emit_int8(imm8 & 0x03); 6827 } 6828 6829 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) { 6830 assert(VM_Version::supports_evex(), ""); 6831 assert(src != xnoreg, "sanity"); 6832 assert(imm8 <= 0x03, "imm8: %u", imm8); 6833 InstructionMark im(this); 6834 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6835 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6836 attributes.reset_is_clear_context(); 6837 attributes.set_is_evex_instruction(); 6838 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6839 emit_int8(0x39); 6840 emit_operand(src, dst); 6841 // 0x00 - extract from bits 127:0 6842 // 0x01 - extract from bits 255:128 6843 // 0x02 - extract from bits 383:256 6844 // 0x03 - extract from bits 511:384 6845 emit_int8(imm8 & 0x03); 6846 } 6847 6848 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6849 assert(VM_Version::supports_avx512dq(), ""); 6850 assert(imm8 <= 0x03, "imm8: %u", imm8); 6851 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6852 attributes.set_is_evex_instruction(); 6853 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6854 emit_int8(0x39); 6855 emit_int8((unsigned char)(0xC0 | encode)); 6856 // 0x00 - extract from bits 127:0 6857 // 0x01 - extract from bits 255:128 6858 // 0x02 - extract from bits 383:256 6859 // 0x03 - extract from bits 511:384 6860 emit_int8(imm8 & 0x03); 6861 } 6862 6863 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6864 assert(VM_Version::supports_evex(), ""); 6865 assert(imm8 <= 0x01, "imm8: %u", imm8); 6866 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6867 attributes.set_is_evex_instruction(); 6868 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6869 emit_int8(0x3B); 6870 emit_int8((unsigned char)(0xC0 | encode)); 6871 // 0x00 - extract from lower 256 bits 6872 // 0x01 - extract from upper 256 bits 6873 emit_int8(imm8 & 0x01); 6874 } 6875 6876 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) { 6877 assert(VM_Version::supports_evex(), ""); 6878 assert(src != xnoreg, "sanity"); 6879 assert(imm8 <= 0x01, "imm8: %u", imm8); 6880 InstructionMark im(this); 6881 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6882 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6883 attributes.reset_is_clear_context(); 6884 attributes.set_is_evex_instruction(); 6885 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6886 emit_int8(0x38); 6887 emit_operand(src, dst); 6888 // 0x00 - extract from lower 256 bits 6889 // 0x01 - extract from upper 256 bits 6890 emit_int8(imm8 & 0x01); 6891 } 6892 // vextractf forms 6893 6894 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6895 assert(VM_Version::supports_avx(), ""); 6896 assert(imm8 <= 0x01, "imm8: %u", imm8); 6897 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6898 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6899 emit_int8(0x19); 6900 emit_int8((unsigned char)(0xC0 | encode)); 6901 // 0x00 - extract from lower 128 bits 6902 // 0x01 - extract from upper 128 bits 6903 emit_int8(imm8 & 0x01); 6904 } 6905 6906 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) { 6907 assert(VM_Version::supports_avx(), ""); 6908 assert(src != xnoreg, "sanity"); 6909 assert(imm8 <= 0x01, "imm8: %u", imm8); 6910 InstructionMark im(this); 6911 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6912 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6913 attributes.reset_is_clear_context(); 6914 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6915 emit_int8(0x19); 6916 emit_operand(src, dst); 6917 // 0x00 - extract from lower 128 bits 6918 // 0x01 - extract from upper 128 bits 6919 emit_int8(imm8 & 0x01); 6920 } 6921 6922 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6923 assert(VM_Version::supports_evex(), ""); 6924 assert(imm8 <= 0x03, "imm8: %u", imm8); 6925 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6926 attributes.set_is_evex_instruction(); 6927 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6928 emit_int8(0x19); 6929 emit_int8((unsigned char)(0xC0 | encode)); 6930 // 0x00 - extract from bits 127:0 6931 // 0x01 - extract from bits 255:128 6932 // 0x02 - extract from bits 383:256 6933 // 0x03 - extract from bits 511:384 6934 emit_int8(imm8 & 0x03); 6935 } 6936 6937 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) { 6938 assert(VM_Version::supports_evex(), ""); 6939 assert(src != xnoreg, "sanity"); 6940 assert(imm8 <= 0x03, "imm8: %u", imm8); 6941 InstructionMark im(this); 6942 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6943 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6944 attributes.reset_is_clear_context(); 6945 attributes.set_is_evex_instruction(); 6946 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6947 emit_int8(0x19); 6948 emit_operand(src, dst); 6949 // 0x00 - extract from bits 127:0 6950 // 0x01 - extract from bits 255:128 6951 // 0x02 - extract from bits 383:256 6952 // 0x03 - extract from bits 511:384 6953 emit_int8(imm8 & 0x03); 6954 } 6955 6956 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6957 assert(VM_Version::supports_avx512dq(), ""); 6958 assert(imm8 <= 0x03, "imm8: %u", imm8); 6959 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6960 attributes.set_is_evex_instruction(); 6961 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6962 emit_int8(0x19); 6963 emit_int8((unsigned char)(0xC0 | encode)); 6964 // 0x00 - extract from bits 127:0 6965 // 0x01 - extract from bits 255:128 6966 // 0x02 - extract from bits 383:256 6967 // 0x03 - extract from bits 511:384 6968 emit_int8(imm8 & 0x03); 6969 } 6970 6971 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6972 assert(VM_Version::supports_evex(), ""); 6973 assert(imm8 <= 0x01, "imm8: %u", imm8); 6974 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6975 attributes.set_is_evex_instruction(); 6976 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6977 emit_int8(0x1B); 6978 emit_int8((unsigned char)(0xC0 | encode)); 6979 // 0x00 - extract from lower 256 bits 6980 // 0x01 - extract from upper 256 bits 6981 emit_int8(imm8 & 0x01); 6982 } 6983 6984 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) { 6985 assert(VM_Version::supports_evex(), ""); 6986 assert(src != xnoreg, "sanity"); 6987 assert(imm8 <= 0x01, "imm8: %u", imm8); 6988 InstructionMark im(this); 6989 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 6990 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit); 6991 attributes.reset_is_clear_context(); 6992 attributes.set_is_evex_instruction(); 6993 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6994 emit_int8(0x1B); 6995 emit_operand(src, dst); 6996 // 0x00 - extract from lower 256 bits 6997 // 0x01 - extract from upper 256 bits 6998 emit_int8(imm8 & 0x01); 6999 } 7000 7001 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 7002 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) { 7003 assert(VM_Version::supports_avx2(), ""); 7004 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 7005 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7006 emit_int8(0x78); 7007 emit_int8((unsigned char)(0xC0 | encode)); 7008 } 7009 7010 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) { 7011 assert(VM_Version::supports_avx2(), ""); 7012 assert(dst != xnoreg, "sanity"); 7013 InstructionMark im(this); 7014 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 7015 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 7016 // swap src<->dst for encoding 7017 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7018 emit_int8(0x78); 7019 emit_operand(dst, src); 7020 } 7021 7022 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 7023 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 7024 assert(VM_Version::supports_avx2(), ""); 7025 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 7026 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7027 emit_int8(0x79); 7028 emit_int8((unsigned char)(0xC0 | encode)); 7029 } 7030 7031 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) { 7032 assert(VM_Version::supports_avx2(), ""); 7033 assert(dst != xnoreg, "sanity"); 7034 InstructionMark im(this); 7035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 7036 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 7037 // swap src<->dst for encoding 7038 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7039 emit_int8(0x79); 7040 emit_operand(dst, src); 7041 } 7042 7043 // xmm/mem sourced byte/word/dword/qword replicate 7044 7045 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 7046 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { 7047 assert(UseAVX >= 2, ""); 7048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7049 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7050 emit_int8(0x58); 7051 emit_int8((unsigned char)(0xC0 | encode)); 7052 } 7053 7054 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) { 7055 assert(VM_Version::supports_avx2(), ""); 7056 assert(dst != xnoreg, "sanity"); 7057 InstructionMark im(this); 7058 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7059 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 7060 // swap src<->dst for encoding 7061 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7062 emit_int8(0x58); 7063 emit_operand(dst, src); 7064 } 7065 7066 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 7067 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) { 7068 assert(VM_Version::supports_avx2(), ""); 7069 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7070 attributes.set_rex_vex_w_reverted(); 7071 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7072 emit_int8(0x59); 7073 emit_int8((unsigned char)(0xC0 | encode)); 7074 } 7075 7076 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) { 7077 assert(VM_Version::supports_avx2(), ""); 7078 assert(dst != xnoreg, "sanity"); 7079 InstructionMark im(this); 7080 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7081 attributes.set_rex_vex_w_reverted(); 7082 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 7083 // swap src<->dst for encoding 7084 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7085 emit_int8(0x59); 7086 emit_operand(dst, src); 7087 } 7088 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) { 7089 assert(vector_len != Assembler::AVX_128bit, ""); 7090 assert(VM_Version::supports_avx512dq(), ""); 7091 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7092 attributes.set_rex_vex_w_reverted(); 7093 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7094 emit_int8(0x5A); 7095 emit_int8((unsigned char)(0xC0 | encode)); 7096 } 7097 7098 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) { 7099 assert(vector_len != Assembler::AVX_128bit, ""); 7100 assert(VM_Version::supports_avx512dq(), ""); 7101 assert(dst != xnoreg, "sanity"); 7102 InstructionMark im(this); 7103 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7104 attributes.set_rex_vex_w_reverted(); 7105 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit); 7106 // swap src<->dst for encoding 7107 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7108 emit_int8(0x5A); 7109 emit_operand(dst, src); 7110 } 7111 7112 // scalar single/double precision replicate 7113 7114 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL 7115 void Assembler::vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) { 7116 assert(VM_Version::supports_avx(), ""); 7117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7118 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7119 emit_int8(0x18); 7120 emit_int8((unsigned char)(0xC0 | encode)); 7121 } 7122 7123 void Assembler::vpbroadcastss(XMMRegister dst, Address src, int vector_len) { 7124 assert(VM_Version::supports_avx(), ""); 7125 assert(dst != xnoreg, "sanity"); 7126 InstructionMark im(this); 7127 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7128 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 7129 // swap src<->dst for encoding 7130 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7131 emit_int8(0x18); 7132 emit_operand(dst, src); 7133 } 7134 7135 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL 7136 void Assembler::vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) { 7137 assert(VM_Version::supports_avx(), ""); 7138 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7139 attributes.set_rex_vex_w_reverted(); 7140 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7141 emit_int8(0x19); 7142 emit_int8((unsigned char)(0xC0 | encode)); 7143 } 7144 7145 void Assembler::vpbroadcastsd(XMMRegister dst, Address src, int vector_len) { 7146 assert(VM_Version::supports_avx(), ""); 7147 assert(dst != xnoreg, "sanity"); 7148 InstructionMark im(this); 7149 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7150 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 7151 attributes.set_rex_vex_w_reverted(); 7152 // swap src<->dst for encoding 7153 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7154 emit_int8(0x19); 7155 emit_operand(dst, src); 7156 } 7157 7158 7159 // gpr source broadcast forms 7160 7161 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 7162 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) { 7163 assert(VM_Version::supports_avx512bw(), ""); 7164 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 7165 attributes.set_is_evex_instruction(); 7166 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7167 emit_int8(0x7A); 7168 emit_int8((unsigned char)(0xC0 | encode)); 7169 } 7170 7171 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 7172 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) { 7173 assert(VM_Version::supports_avx512bw(), ""); 7174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 7175 attributes.set_is_evex_instruction(); 7176 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7177 emit_int8(0x7B); 7178 emit_int8((unsigned char)(0xC0 | encode)); 7179 } 7180 7181 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 7182 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) { 7183 assert(VM_Version::supports_evex(), ""); 7184 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7185 attributes.set_is_evex_instruction(); 7186 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7187 emit_int8(0x7C); 7188 emit_int8((unsigned char)(0xC0 | encode)); 7189 } 7190 7191 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 7192 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) { 7193 assert(VM_Version::supports_evex(), ""); 7194 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7195 attributes.set_is_evex_instruction(); 7196 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7197 emit_int8(0x7C); 7198 emit_int8((unsigned char)(0xC0 | encode)); 7199 } 7200 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) { 7201 assert(VM_Version::supports_evex(), ""); 7202 assert(dst != xnoreg, "sanity"); 7203 InstructionMark im(this); 7204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 7205 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 7206 attributes.reset_is_clear_context(); 7207 attributes.set_embedded_opmask_register_specifier(mask); 7208 attributes.set_is_evex_instruction(); 7209 // swap src<->dst for encoding 7210 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7211 emit_int8((unsigned char)0x90); 7212 emit_operand(dst, src); 7213 } 7214 // Carry-Less Multiplication Quadword 7215 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { 7216 assert(VM_Version::supports_clmul(), ""); 7217 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 7218 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7219 emit_int8(0x44); 7220 emit_int8((unsigned char)(0xC0 | encode)); 7221 emit_int8((unsigned char)mask); 7222 } 7223 7224 // Carry-Less Multiplication Quadword 7225 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { 7226 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); 7227 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 7228 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7229 emit_int8(0x44); 7230 emit_int8((unsigned char)(0xC0 | encode)); 7231 emit_int8((unsigned char)mask); 7232 } 7233 7234 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) { 7235 assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support"); 7236 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 7237 attributes.set_is_evex_instruction(); 7238 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7239 emit_int8(0x44); 7240 emit_int8((unsigned char)(0xC0 | encode)); 7241 emit_int8((unsigned char)mask); 7242 } 7243 7244 void Assembler::vzeroupper() { 7245 if (VM_Version::supports_vzeroupper()) { 7246 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 7247 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 7248 emit_int8(0x77); 7249 } 7250 } 7251 7252 #ifndef _LP64 7253 // 32bit only pieces of the assembler 7254 7255 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 7256 // NO PREFIX AS NEVER 64BIT 7257 InstructionMark im(this); 7258 emit_int8((unsigned char)0x81); 7259 emit_int8((unsigned char)(0xF8 | src1->encoding())); 7260 emit_data(imm32, rspec, 0); 7261 } 7262 7263 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 7264 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 7265 InstructionMark im(this); 7266 emit_int8((unsigned char)0x81); 7267 emit_operand(rdi, src1); 7268 emit_data(imm32, rspec, 0); 7269 } 7270 7271 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 7272 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 7273 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 7274 void Assembler::cmpxchg8(Address adr) { 7275 InstructionMark im(this); 7276 emit_int8(0x0F); 7277 emit_int8((unsigned char)0xC7); 7278 emit_operand(rcx, adr); 7279 } 7280 7281 void Assembler::decl(Register dst) { 7282 // Don't use it directly. Use MacroAssembler::decrementl() instead. 7283 emit_int8(0x48 | dst->encoding()); 7284 } 7285 7286 #endif // _LP64 7287 7288 // 64bit typically doesn't use the x87 but needs to for the trig funcs 7289 7290 void Assembler::fabs() { 7291 emit_int8((unsigned char)0xD9); 7292 emit_int8((unsigned char)0xE1); 7293 } 7294 7295 void Assembler::fadd(int i) { 7296 emit_farith(0xD8, 0xC0, i); 7297 } 7298 7299 void Assembler::fadd_d(Address src) { 7300 InstructionMark im(this); 7301 emit_int8((unsigned char)0xDC); 7302 emit_operand32(rax, src); 7303 } 7304 7305 void Assembler::fadd_s(Address src) { 7306 InstructionMark im(this); 7307 emit_int8((unsigned char)0xD8); 7308 emit_operand32(rax, src); 7309 } 7310 7311 void Assembler::fadda(int i) { 7312 emit_farith(0xDC, 0xC0, i); 7313 } 7314 7315 void Assembler::faddp(int i) { 7316 emit_farith(0xDE, 0xC0, i); 7317 } 7318 7319 void Assembler::fchs() { 7320 emit_int8((unsigned char)0xD9); 7321 emit_int8((unsigned char)0xE0); 7322 } 7323 7324 void Assembler::fcom(int i) { 7325 emit_farith(0xD8, 0xD0, i); 7326 } 7327 7328 void Assembler::fcomp(int i) { 7329 emit_farith(0xD8, 0xD8, i); 7330 } 7331 7332 void Assembler::fcomp_d(Address src) { 7333 InstructionMark im(this); 7334 emit_int8((unsigned char)0xDC); 7335 emit_operand32(rbx, src); 7336 } 7337 7338 void Assembler::fcomp_s(Address src) { 7339 InstructionMark im(this); 7340 emit_int8((unsigned char)0xD8); 7341 emit_operand32(rbx, src); 7342 } 7343 7344 void Assembler::fcompp() { 7345 emit_int8((unsigned char)0xDE); 7346 emit_int8((unsigned char)0xD9); 7347 } 7348 7349 void Assembler::fcos() { 7350 emit_int8((unsigned char)0xD9); 7351 emit_int8((unsigned char)0xFF); 7352 } 7353 7354 void Assembler::fdecstp() { 7355 emit_int8((unsigned char)0xD9); 7356 emit_int8((unsigned char)0xF6); 7357 } 7358 7359 void Assembler::fdiv(int i) { 7360 emit_farith(0xD8, 0xF0, i); 7361 } 7362 7363 void Assembler::fdiv_d(Address src) { 7364 InstructionMark im(this); 7365 emit_int8((unsigned char)0xDC); 7366 emit_operand32(rsi, src); 7367 } 7368 7369 void Assembler::fdiv_s(Address src) { 7370 InstructionMark im(this); 7371 emit_int8((unsigned char)0xD8); 7372 emit_operand32(rsi, src); 7373 } 7374 7375 void Assembler::fdiva(int i) { 7376 emit_farith(0xDC, 0xF8, i); 7377 } 7378 7379 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 7380 // is erroneous for some of the floating-point instructions below. 7381 7382 void Assembler::fdivp(int i) { 7383 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 7384 } 7385 7386 void Assembler::fdivr(int i) { 7387 emit_farith(0xD8, 0xF8, i); 7388 } 7389 7390 void Assembler::fdivr_d(Address src) { 7391 InstructionMark im(this); 7392 emit_int8((unsigned char)0xDC); 7393 emit_operand32(rdi, src); 7394 } 7395 7396 void Assembler::fdivr_s(Address src) { 7397 InstructionMark im(this); 7398 emit_int8((unsigned char)0xD8); 7399 emit_operand32(rdi, src); 7400 } 7401 7402 void Assembler::fdivra(int i) { 7403 emit_farith(0xDC, 0xF0, i); 7404 } 7405 7406 void Assembler::fdivrp(int i) { 7407 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 7408 } 7409 7410 void Assembler::ffree(int i) { 7411 emit_farith(0xDD, 0xC0, i); 7412 } 7413 7414 void Assembler::fild_d(Address adr) { 7415 InstructionMark im(this); 7416 emit_int8((unsigned char)0xDF); 7417 emit_operand32(rbp, adr); 7418 } 7419 7420 void Assembler::fild_s(Address adr) { 7421 InstructionMark im(this); 7422 emit_int8((unsigned char)0xDB); 7423 emit_operand32(rax, adr); 7424 } 7425 7426 void Assembler::fincstp() { 7427 emit_int8((unsigned char)0xD9); 7428 emit_int8((unsigned char)0xF7); 7429 } 7430 7431 void Assembler::finit() { 7432 emit_int8((unsigned char)0x9B); 7433 emit_int8((unsigned char)0xDB); 7434 emit_int8((unsigned char)0xE3); 7435 } 7436 7437 void Assembler::fist_s(Address adr) { 7438 InstructionMark im(this); 7439 emit_int8((unsigned char)0xDB); 7440 emit_operand32(rdx, adr); 7441 } 7442 7443 void Assembler::fistp_d(Address adr) { 7444 InstructionMark im(this); 7445 emit_int8((unsigned char)0xDF); 7446 emit_operand32(rdi, adr); 7447 } 7448 7449 void Assembler::fistp_s(Address adr) { 7450 InstructionMark im(this); 7451 emit_int8((unsigned char)0xDB); 7452 emit_operand32(rbx, adr); 7453 } 7454 7455 void Assembler::fld1() { 7456 emit_int8((unsigned char)0xD9); 7457 emit_int8((unsigned char)0xE8); 7458 } 7459 7460 void Assembler::fld_d(Address adr) { 7461 InstructionMark im(this); 7462 emit_int8((unsigned char)0xDD); 7463 emit_operand32(rax, adr); 7464 } 7465 7466 void Assembler::fld_s(Address adr) { 7467 InstructionMark im(this); 7468 emit_int8((unsigned char)0xD9); 7469 emit_operand32(rax, adr); 7470 } 7471 7472 7473 void Assembler::fld_s(int index) { 7474 emit_farith(0xD9, 0xC0, index); 7475 } 7476 7477 void Assembler::fld_x(Address adr) { 7478 InstructionMark im(this); 7479 emit_int8((unsigned char)0xDB); 7480 emit_operand32(rbp, adr); 7481 } 7482 7483 void Assembler::fldcw(Address src) { 7484 InstructionMark im(this); 7485 emit_int8((unsigned char)0xD9); 7486 emit_operand32(rbp, src); 7487 } 7488 7489 void Assembler::fldenv(Address src) { 7490 InstructionMark im(this); 7491 emit_int8((unsigned char)0xD9); 7492 emit_operand32(rsp, src); 7493 } 7494 7495 void Assembler::fldlg2() { 7496 emit_int8((unsigned char)0xD9); 7497 emit_int8((unsigned char)0xEC); 7498 } 7499 7500 void Assembler::fldln2() { 7501 emit_int8((unsigned char)0xD9); 7502 emit_int8((unsigned char)0xED); 7503 } 7504 7505 void Assembler::fldz() { 7506 emit_int8((unsigned char)0xD9); 7507 emit_int8((unsigned char)0xEE); 7508 } 7509 7510 void Assembler::flog() { 7511 fldln2(); 7512 fxch(); 7513 fyl2x(); 7514 } 7515 7516 void Assembler::flog10() { 7517 fldlg2(); 7518 fxch(); 7519 fyl2x(); 7520 } 7521 7522 void Assembler::fmul(int i) { 7523 emit_farith(0xD8, 0xC8, i); 7524 } 7525 7526 void Assembler::fmul_d(Address src) { 7527 InstructionMark im(this); 7528 emit_int8((unsigned char)0xDC); 7529 emit_operand32(rcx, src); 7530 } 7531 7532 void Assembler::fmul_s(Address src) { 7533 InstructionMark im(this); 7534 emit_int8((unsigned char)0xD8); 7535 emit_operand32(rcx, src); 7536 } 7537 7538 void Assembler::fmula(int i) { 7539 emit_farith(0xDC, 0xC8, i); 7540 } 7541 7542 void Assembler::fmulp(int i) { 7543 emit_farith(0xDE, 0xC8, i); 7544 } 7545 7546 void Assembler::fnsave(Address dst) { 7547 InstructionMark im(this); 7548 emit_int8((unsigned char)0xDD); 7549 emit_operand32(rsi, dst); 7550 } 7551 7552 void Assembler::fnstcw(Address src) { 7553 InstructionMark im(this); 7554 emit_int8((unsigned char)0x9B); 7555 emit_int8((unsigned char)0xD9); 7556 emit_operand32(rdi, src); 7557 } 7558 7559 void Assembler::fnstsw_ax() { 7560 emit_int8((unsigned char)0xDF); 7561 emit_int8((unsigned char)0xE0); 7562 } 7563 7564 void Assembler::fprem() { 7565 emit_int8((unsigned char)0xD9); 7566 emit_int8((unsigned char)0xF8); 7567 } 7568 7569 void Assembler::fprem1() { 7570 emit_int8((unsigned char)0xD9); 7571 emit_int8((unsigned char)0xF5); 7572 } 7573 7574 void Assembler::frstor(Address src) { 7575 InstructionMark im(this); 7576 emit_int8((unsigned char)0xDD); 7577 emit_operand32(rsp, src); 7578 } 7579 7580 void Assembler::fsin() { 7581 emit_int8((unsigned char)0xD9); 7582 emit_int8((unsigned char)0xFE); 7583 } 7584 7585 void Assembler::fsqrt() { 7586 emit_int8((unsigned char)0xD9); 7587 emit_int8((unsigned char)0xFA); 7588 } 7589 7590 void Assembler::fst_d(Address adr) { 7591 InstructionMark im(this); 7592 emit_int8((unsigned char)0xDD); 7593 emit_operand32(rdx, adr); 7594 } 7595 7596 void Assembler::fst_s(Address adr) { 7597 InstructionMark im(this); 7598 emit_int8((unsigned char)0xD9); 7599 emit_operand32(rdx, adr); 7600 } 7601 7602 void Assembler::fstp_d(Address adr) { 7603 InstructionMark im(this); 7604 emit_int8((unsigned char)0xDD); 7605 emit_operand32(rbx, adr); 7606 } 7607 7608 void Assembler::fstp_d(int index) { 7609 emit_farith(0xDD, 0xD8, index); 7610 } 7611 7612 void Assembler::fstp_s(Address adr) { 7613 InstructionMark im(this); 7614 emit_int8((unsigned char)0xD9); 7615 emit_operand32(rbx, adr); 7616 } 7617 7618 void Assembler::fstp_x(Address adr) { 7619 InstructionMark im(this); 7620 emit_int8((unsigned char)0xDB); 7621 emit_operand32(rdi, adr); 7622 } 7623 7624 void Assembler::fsub(int i) { 7625 emit_farith(0xD8, 0xE0, i); 7626 } 7627 7628 void Assembler::fsub_d(Address src) { 7629 InstructionMark im(this); 7630 emit_int8((unsigned char)0xDC); 7631 emit_operand32(rsp, src); 7632 } 7633 7634 void Assembler::fsub_s(Address src) { 7635 InstructionMark im(this); 7636 emit_int8((unsigned char)0xD8); 7637 emit_operand32(rsp, src); 7638 } 7639 7640 void Assembler::fsuba(int i) { 7641 emit_farith(0xDC, 0xE8, i); 7642 } 7643 7644 void Assembler::fsubp(int i) { 7645 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 7646 } 7647 7648 void Assembler::fsubr(int i) { 7649 emit_farith(0xD8, 0xE8, i); 7650 } 7651 7652 void Assembler::fsubr_d(Address src) { 7653 InstructionMark im(this); 7654 emit_int8((unsigned char)0xDC); 7655 emit_operand32(rbp, src); 7656 } 7657 7658 void Assembler::fsubr_s(Address src) { 7659 InstructionMark im(this); 7660 emit_int8((unsigned char)0xD8); 7661 emit_operand32(rbp, src); 7662 } 7663 7664 void Assembler::fsubra(int i) { 7665 emit_farith(0xDC, 0xE0, i); 7666 } 7667 7668 void Assembler::fsubrp(int i) { 7669 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 7670 } 7671 7672 void Assembler::ftan() { 7673 emit_int8((unsigned char)0xD9); 7674 emit_int8((unsigned char)0xF2); 7675 emit_int8((unsigned char)0xDD); 7676 emit_int8((unsigned char)0xD8); 7677 } 7678 7679 void Assembler::ftst() { 7680 emit_int8((unsigned char)0xD9); 7681 emit_int8((unsigned char)0xE4); 7682 } 7683 7684 void Assembler::fucomi(int i) { 7685 // make sure the instruction is supported (introduced for P6, together with cmov) 7686 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7687 emit_farith(0xDB, 0xE8, i); 7688 } 7689 7690 void Assembler::fucomip(int i) { 7691 // make sure the instruction is supported (introduced for P6, together with cmov) 7692 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7693 emit_farith(0xDF, 0xE8, i); 7694 } 7695 7696 void Assembler::fwait() { 7697 emit_int8((unsigned char)0x9B); 7698 } 7699 7700 void Assembler::fxch(int i) { 7701 emit_farith(0xD9, 0xC8, i); 7702 } 7703 7704 void Assembler::fyl2x() { 7705 emit_int8((unsigned char)0xD9); 7706 emit_int8((unsigned char)0xF1); 7707 } 7708 7709 void Assembler::frndint() { 7710 emit_int8((unsigned char)0xD9); 7711 emit_int8((unsigned char)0xFC); 7712 } 7713 7714 void Assembler::f2xm1() { 7715 emit_int8((unsigned char)0xD9); 7716 emit_int8((unsigned char)0xF0); 7717 } 7718 7719 void Assembler::fldl2e() { 7720 emit_int8((unsigned char)0xD9); 7721 emit_int8((unsigned char)0xEA); 7722 } 7723 7724 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 7725 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 7726 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 7727 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 7728 7729 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 7730 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7731 if (pre > 0) { 7732 emit_int8(simd_pre[pre]); 7733 } 7734 if (rex_w) { 7735 prefixq(adr, xreg); 7736 } else { 7737 prefix(adr, xreg); 7738 } 7739 if (opc > 0) { 7740 emit_int8(0x0F); 7741 int opc2 = simd_opc[opc]; 7742 if (opc2 > 0) { 7743 emit_int8(opc2); 7744 } 7745 } 7746 } 7747 7748 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7749 if (pre > 0) { 7750 emit_int8(simd_pre[pre]); 7751 } 7752 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); 7753 if (opc > 0) { 7754 emit_int8(0x0F); 7755 int opc2 = simd_opc[opc]; 7756 if (opc2 > 0) { 7757 emit_int8(opc2); 7758 } 7759 } 7760 return encode; 7761 } 7762 7763 7764 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) { 7765 int vector_len = _attributes->get_vector_len(); 7766 bool vex_w = _attributes->is_rex_vex_w(); 7767 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 7768 prefix(VEX_3bytes); 7769 7770 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 7771 byte1 = (~byte1) & 0xE0; 7772 byte1 |= opc; 7773 emit_int8(byte1); 7774 7775 int byte2 = ((~nds_enc) & 0xf) << 3; 7776 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; 7777 emit_int8(byte2); 7778 } else { 7779 prefix(VEX_2bytes); 7780 7781 int byte1 = vex_r ? VEX_R : 0; 7782 byte1 = (~byte1) & 0x80; 7783 byte1 |= ((~nds_enc) & 0xf) << 3; 7784 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; 7785 emit_int8(byte1); 7786 } 7787 } 7788 7789 // This is a 4 byte encoding 7790 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){ 7791 // EVEX 0x62 prefix 7792 prefix(EVEX_4bytes); 7793 bool vex_w = _attributes->is_rex_vex_w(); 7794 int evex_encoding = (vex_w ? VEX_W : 0); 7795 // EVEX.b is not currently used for broadcast of single element or data rounding modes 7796 _attributes->set_evex_encoding(evex_encoding); 7797 7798 // P0: byte 2, initialized to RXBR`00mm 7799 // instead of not'd 7800 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); 7801 byte2 = (~byte2) & 0xF0; 7802 // confine opc opcode extensions in mm bits to lower two bits 7803 // of form {0F, 0F_38, 0F_3A} 7804 byte2 |= opc; 7805 emit_int8(byte2); 7806 7807 // P1: byte 3 as Wvvvv1pp 7808 int byte3 = ((~nds_enc) & 0xf) << 3; 7809 // p[10] is always 1 7810 byte3 |= EVEX_F; 7811 byte3 |= (vex_w & 1) << 7; 7812 // confine pre opcode extensions in pp bits to lower two bits 7813 // of form {66, F3, F2} 7814 byte3 |= pre; 7815 emit_int8(byte3); 7816 7817 // P2: byte 4 as zL'Lbv'aaa 7818 // kregs are implemented in the low 3 bits as aaa 7819 int byte4 = (_attributes->is_no_reg_mask()) ? 7820 0 : 7821 _attributes->get_embedded_opmask_register_specifier(); 7822 // EVEX.v` for extending EVEX.vvvv or VIDX 7823 byte4 |= (evex_v ? 0: EVEX_V); 7824 // third EXEC.b for broadcast actions 7825 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0); 7826 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 7827 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5; 7828 // last is EVEX.z for zero/merge actions 7829 if (_attributes->is_no_reg_mask() == false) { 7830 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0); 7831 } 7832 emit_int8(byte4); 7833 } 7834 7835 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7836 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0; 7837 bool vex_b = adr.base_needs_rex(); 7838 bool vex_x; 7839 if (adr.isxmmindex()) { 7840 vex_x = adr.xmmindex_needs_rex(); 7841 } else { 7842 vex_x = adr.index_needs_rex(); 7843 } 7844 set_attributes(attributes); 7845 attributes->set_current_assembler(this); 7846 7847 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction 7848 // is allowed in legacy mode and has resources which will fit in it. 7849 // Pure EVEX instructions will have is_evex_instruction set in their definition. 7850 if (!attributes->is_legacy_mode()) { 7851 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) { 7852 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) { 7853 attributes->set_is_legacy_mode(); 7854 } 7855 } 7856 } 7857 7858 if (UseAVX > 2) { 7859 assert(((!attributes->uses_vl()) || 7860 (attributes->get_vector_len() == AVX_512bit) || 7861 (!_legacy_mode_vl) || 7862 (attributes->is_legacy_mode())),"XMM register should be 0-15"); 7863 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15"); 7864 } 7865 7866 _is_managed = false; 7867 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7868 { 7869 bool evex_r = (xreg_enc >= 16); 7870 bool evex_v; 7871 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31) 7872 if (adr.isxmmindex()) { 7873 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false); 7874 } else { 7875 evex_v = (nds_enc >= 16); 7876 } 7877 attributes->set_is_evex_instruction(); 7878 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7879 } else { 7880 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7881 attributes->set_rex_vex_w(false); 7882 } 7883 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7884 } 7885 } 7886 7887 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7888 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0; 7889 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0; 7890 bool vex_x = false; 7891 set_attributes(attributes); 7892 attributes->set_current_assembler(this); 7893 7894 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction 7895 // is allowed in legacy mode and has resources which will fit in it. 7896 // Pure EVEX instructions will have is_evex_instruction set in their definition. 7897 if (!attributes->is_legacy_mode()) { 7898 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) { 7899 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) && 7900 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) { 7901 attributes->set_is_legacy_mode(); 7902 } 7903 } 7904 } 7905 7906 if (UseAVX > 2) { 7907 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false 7908 // Instruction with uses_vl true are vector instructions 7909 // All the vector instructions with AVX_512bit length can have legacy_mode as false 7910 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported 7911 // Rest all should have legacy_mode set as true 7912 assert(((!attributes->uses_vl()) || 7913 (attributes->get_vector_len() == AVX_512bit) || 7914 (!_legacy_mode_vl) || 7915 (attributes->is_legacy_mode())),"XMM register should be 0-15"); 7916 // Instruction with legacy_mode true should have dst, nds and src < 15 7917 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15"); 7918 } 7919 7920 _is_managed = false; 7921 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7922 { 7923 bool evex_r = (dst_enc >= 16); 7924 bool evex_v = (nds_enc >= 16); 7925 // can use vex_x as bank extender on rm encoding 7926 vex_x = (src_enc >= 16); 7927 attributes->set_is_evex_instruction(); 7928 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7929 } else { 7930 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7931 attributes->set_rex_vex_w(false); 7932 } 7933 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7934 } 7935 7936 // return modrm byte components for operands 7937 return (((dst_enc & 7) << 3) | (src_enc & 7)); 7938 } 7939 7940 7941 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 7942 VexOpcode opc, InstructionAttr *attributes) { 7943 if (UseAVX > 0) { 7944 int xreg_enc = xreg->encoding(); 7945 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7946 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes); 7947 } else { 7948 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 7949 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w()); 7950 } 7951 } 7952 7953 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 7954 VexOpcode opc, InstructionAttr *attributes) { 7955 int dst_enc = dst->encoding(); 7956 int src_enc = src->encoding(); 7957 if (UseAVX > 0) { 7958 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7959 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes); 7960 } else { 7961 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 7962 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w()); 7963 } 7964 } 7965 7966 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 7967 assert(VM_Version::supports_avx(), ""); 7968 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 7969 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 7970 emit_int8(0x5F); 7971 emit_int8((unsigned char)(0xC0 | encode)); 7972 } 7973 7974 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 7975 assert(VM_Version::supports_avx(), ""); 7976 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 7977 attributes.set_rex_vex_w_reverted(); 7978 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 7979 emit_int8(0x5F); 7980 emit_int8((unsigned char)(0xC0 | encode)); 7981 } 7982 7983 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 7984 assert(VM_Version::supports_avx(), ""); 7985 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 7986 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 7987 emit_int8(0x5D); 7988 emit_int8((unsigned char)(0xC0 | encode)); 7989 } 7990 7991 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 7992 assert(VM_Version::supports_avx(), ""); 7993 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 7994 attributes.set_rex_vex_w_reverted(); 7995 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 7996 emit_int8(0x5D); 7997 emit_int8((unsigned char)(0xC0 | encode)); 7998 } 7999 8000 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 8001 assert(VM_Version::supports_avx(), ""); 8002 assert(vector_len <= AVX_256bit, ""); 8003 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8004 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8005 emit_int8((unsigned char)0xC2); 8006 emit_int8((unsigned char)(0xC0 | encode)); 8007 emit_int8((unsigned char)(0xF & cop)); 8008 } 8009 8010 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 8011 assert(VM_Version::supports_avx(), ""); 8012 assert(vector_len <= AVX_256bit, ""); 8013 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8014 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 8015 emit_int8((unsigned char)0x4B); 8016 emit_int8((unsigned char)(0xC0 | encode)); 8017 int src2_enc = src2->encoding(); 8018 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 8019 } 8020 8021 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 8022 assert(VM_Version::supports_avx(), ""); 8023 assert(vector_len <= AVX_256bit, ""); 8024 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8025 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 8026 emit_int8((unsigned char)0xC2); 8027 emit_int8((unsigned char)(0xC0 | encode)); 8028 emit_int8((unsigned char)(0xF & cop)); 8029 } 8030 8031 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 8032 assert(VM_Version::supports_avx(), ""); 8033 assert(vector_len <= AVX_256bit, ""); 8034 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8035 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 8036 emit_int8((unsigned char)0x4A); 8037 emit_int8((unsigned char)(0xC0 | encode)); 8038 int src2_enc = src2->encoding(); 8039 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 8040 } 8041 8042 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 8043 assert(VM_Version::supports_avx2(), ""); 8044 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8045 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 8046 emit_int8((unsigned char)0x02); 8047 emit_int8((unsigned char)(0xC0 | encode)); 8048 emit_int8((unsigned char)imm8); 8049 } 8050 8051 void Assembler::shlxl(Register dst, Register src1, Register src2) { 8052 assert(VM_Version::supports_bmi2(), ""); 8053 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8054 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 8055 emit_int8((unsigned char)0xF7); 8056 emit_int8((unsigned char)(0xC0 | encode)); 8057 } 8058 8059 void Assembler::shlxq(Register dst, Register src1, Register src2) { 8060 assert(VM_Version::supports_bmi2(), ""); 8061 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); 8062 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 8063 emit_int8((unsigned char)0xF7); 8064 emit_int8((unsigned char)(0xC0 | encode)); 8065 } 8066 8067 #ifndef _LP64 8068 8069 void Assembler::incl(Register dst) { 8070 // Don't use it directly. Use MacroAssembler::incrementl() instead. 8071 emit_int8(0x40 | dst->encoding()); 8072 } 8073 8074 void Assembler::lea(Register dst, Address src) { 8075 leal(dst, src); 8076 } 8077 8078 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 8079 InstructionMark im(this); 8080 emit_int8((unsigned char)0xC7); 8081 emit_operand(rax, dst); 8082 emit_data((int)imm32, rspec, 0); 8083 } 8084 8085 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 8086 InstructionMark im(this); 8087 int encode = prefix_and_encode(dst->encoding()); 8088 emit_int8((unsigned char)(0xB8 | encode)); 8089 emit_data((int)imm32, rspec, 0); 8090 } 8091 8092 void Assembler::popa() { // 32bit 8093 emit_int8(0x61); 8094 } 8095 8096 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 8097 InstructionMark im(this); 8098 emit_int8(0x68); 8099 emit_data(imm32, rspec, 0); 8100 } 8101 8102 void Assembler::pusha() { // 32bit 8103 emit_int8(0x60); 8104 } 8105 8106 void Assembler::set_byte_if_not_zero(Register dst) { 8107 emit_int8(0x0F); 8108 emit_int8((unsigned char)0x95); 8109 emit_int8((unsigned char)(0xE0 | dst->encoding())); 8110 } 8111 8112 void Assembler::shldl(Register dst, Register src) { 8113 emit_int8(0x0F); 8114 emit_int8((unsigned char)0xA5); 8115 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 8116 } 8117 8118 // 0F A4 / r ib 8119 void Assembler::shldl(Register dst, Register src, int8_t imm8) { 8120 emit_int8(0x0F); 8121 emit_int8((unsigned char)0xA4); 8122 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 8123 emit_int8(imm8); 8124 } 8125 8126 void Assembler::shrdl(Register dst, Register src) { 8127 emit_int8(0x0F); 8128 emit_int8((unsigned char)0xAD); 8129 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 8130 } 8131 8132 #else // LP64 8133 8134 void Assembler::set_byte_if_not_zero(Register dst) { 8135 int enc = prefix_and_encode(dst->encoding(), true); 8136 emit_int8(0x0F); 8137 emit_int8((unsigned char)0x95); 8138 emit_int8((unsigned char)(0xE0 | enc)); 8139 } 8140 8141 // 64bit only pieces of the assembler 8142 // This should only be used by 64bit instructions that can use rip-relative 8143 // it cannot be used by instructions that want an immediate value. 8144 8145 bool Assembler::reachable(AddressLiteral adr) { 8146 int64_t disp; 8147 // None will force a 64bit literal to the code stream. Likely a placeholder 8148 // for something that will be patched later and we need to certain it will 8149 // always be reachable. 8150 if (adr.reloc() == relocInfo::none) { 8151 return false; 8152 } 8153 if (adr.reloc() == relocInfo::internal_word_type) { 8154 // This should be rip relative and easily reachable. 8155 return true; 8156 } 8157 if (adr.reloc() == relocInfo::virtual_call_type || 8158 adr.reloc() == relocInfo::opt_virtual_call_type || 8159 adr.reloc() == relocInfo::static_call_type || 8160 adr.reloc() == relocInfo::static_stub_type ) { 8161 // This should be rip relative within the code cache and easily 8162 // reachable until we get huge code caches. (At which point 8163 // ic code is going to have issues). 8164 return true; 8165 } 8166 if (adr.reloc() != relocInfo::external_word_type && 8167 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 8168 adr.reloc() != relocInfo::poll_type && // relocs to identify them 8169 adr.reloc() != relocInfo::runtime_call_type ) { 8170 return false; 8171 } 8172 8173 // Stress the correction code 8174 if (ForceUnreachable) { 8175 // Must be runtimecall reloc, see if it is in the codecache 8176 // Flipping stuff in the codecache to be unreachable causes issues 8177 // with things like inline caches where the additional instructions 8178 // are not handled. 8179 if (CodeCache::find_blob(adr._target) == NULL) { 8180 return false; 8181 } 8182 } 8183 // For external_word_type/runtime_call_type if it is reachable from where we 8184 // are now (possibly a temp buffer) and where we might end up 8185 // anywhere in the codeCache then we are always reachable. 8186 // This would have to change if we ever save/restore shared code 8187 // to be more pessimistic. 8188 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 8189 if (!is_simm32(disp)) return false; 8190 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 8191 if (!is_simm32(disp)) return false; 8192 8193 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); 8194 8195 // Because rip relative is a disp + address_of_next_instruction and we 8196 // don't know the value of address_of_next_instruction we apply a fudge factor 8197 // to make sure we will be ok no matter the size of the instruction we get placed into. 8198 // We don't have to fudge the checks above here because they are already worst case. 8199 8200 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 8201 // + 4 because better safe than sorry. 8202 const int fudge = 12 + 4; 8203 if (disp < 0) { 8204 disp -= fudge; 8205 } else { 8206 disp += fudge; 8207 } 8208 return is_simm32(disp); 8209 } 8210 8211 // Check if the polling page is not reachable from the code cache using rip-relative 8212 // addressing. 8213 bool Assembler::is_polling_page_far() { 8214 intptr_t addr = (intptr_t)os::get_polling_page(); 8215 return ForceUnreachable || 8216 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 8217 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 8218 } 8219 8220 void Assembler::emit_data64(jlong data, 8221 relocInfo::relocType rtype, 8222 int format) { 8223 if (rtype == relocInfo::none) { 8224 emit_int64(data); 8225 } else { 8226 emit_data64(data, Relocation::spec_simple(rtype), format); 8227 } 8228 } 8229 8230 void Assembler::emit_data64(jlong data, 8231 RelocationHolder const& rspec, 8232 int format) { 8233 assert(imm_operand == 0, "default format must be immediate in this file"); 8234 assert(imm_operand == format, "must be immediate"); 8235 assert(inst_mark() != NULL, "must be inside InstructionMark"); 8236 // Do not use AbstractAssembler::relocate, which is not intended for 8237 // embedded words. Instead, relocate to the enclosing instruction. 8238 code_section()->relocate(inst_mark(), rspec, format); 8239 #ifdef ASSERT 8240 check_relocation(rspec, format); 8241 #endif 8242 emit_int64(data); 8243 } 8244 8245 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 8246 if (reg_enc >= 8) { 8247 prefix(REX_B); 8248 reg_enc -= 8; 8249 } else if (byteinst && reg_enc >= 4) { 8250 prefix(REX); 8251 } 8252 return reg_enc; 8253 } 8254 8255 int Assembler::prefixq_and_encode(int reg_enc) { 8256 if (reg_enc < 8) { 8257 prefix(REX_W); 8258 } else { 8259 prefix(REX_WB); 8260 reg_enc -= 8; 8261 } 8262 return reg_enc; 8263 } 8264 8265 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { 8266 if (dst_enc < 8) { 8267 if (src_enc >= 8) { 8268 prefix(REX_B); 8269 src_enc -= 8; 8270 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { 8271 prefix(REX); 8272 } 8273 } else { 8274 if (src_enc < 8) { 8275 prefix(REX_R); 8276 } else { 8277 prefix(REX_RB); 8278 src_enc -= 8; 8279 } 8280 dst_enc -= 8; 8281 } 8282 return dst_enc << 3 | src_enc; 8283 } 8284 8285 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 8286 if (dst_enc < 8) { 8287 if (src_enc < 8) { 8288 prefix(REX_W); 8289 } else { 8290 prefix(REX_WB); 8291 src_enc -= 8; 8292 } 8293 } else { 8294 if (src_enc < 8) { 8295 prefix(REX_WR); 8296 } else { 8297 prefix(REX_WRB); 8298 src_enc -= 8; 8299 } 8300 dst_enc -= 8; 8301 } 8302 return dst_enc << 3 | src_enc; 8303 } 8304 8305 void Assembler::prefix(Register reg) { 8306 if (reg->encoding() >= 8) { 8307 prefix(REX_B); 8308 } 8309 } 8310 8311 void Assembler::prefix(Register dst, Register src, Prefix p) { 8312 if (src->encoding() >= 8) { 8313 p = (Prefix)(p | REX_B); 8314 } 8315 if (dst->encoding() >= 8) { 8316 p = (Prefix)( p | REX_R); 8317 } 8318 if (p != Prefix_EMPTY) { 8319 // do not generate an empty prefix 8320 prefix(p); 8321 } 8322 } 8323 8324 void Assembler::prefix(Register dst, Address adr, Prefix p) { 8325 if (adr.base_needs_rex()) { 8326 if (adr.index_needs_rex()) { 8327 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 8328 } else { 8329 prefix(REX_B); 8330 } 8331 } else { 8332 if (adr.index_needs_rex()) { 8333 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 8334 } 8335 } 8336 if (dst->encoding() >= 8) { 8337 p = (Prefix)(p | REX_R); 8338 } 8339 if (p != Prefix_EMPTY) { 8340 // do not generate an empty prefix 8341 prefix(p); 8342 } 8343 } 8344 8345 void Assembler::prefix(Address adr) { 8346 if (adr.base_needs_rex()) { 8347 if (adr.index_needs_rex()) { 8348 prefix(REX_XB); 8349 } else { 8350 prefix(REX_B); 8351 } 8352 } else { 8353 if (adr.index_needs_rex()) { 8354 prefix(REX_X); 8355 } 8356 } 8357 } 8358 8359 void Assembler::prefixq(Address adr) { 8360 if (adr.base_needs_rex()) { 8361 if (adr.index_needs_rex()) { 8362 prefix(REX_WXB); 8363 } else { 8364 prefix(REX_WB); 8365 } 8366 } else { 8367 if (adr.index_needs_rex()) { 8368 prefix(REX_WX); 8369 } else { 8370 prefix(REX_W); 8371 } 8372 } 8373 } 8374 8375 8376 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 8377 if (reg->encoding() < 8) { 8378 if (adr.base_needs_rex()) { 8379 if (adr.index_needs_rex()) { 8380 prefix(REX_XB); 8381 } else { 8382 prefix(REX_B); 8383 } 8384 } else { 8385 if (adr.index_needs_rex()) { 8386 prefix(REX_X); 8387 } else if (byteinst && reg->encoding() >= 4 ) { 8388 prefix(REX); 8389 } 8390 } 8391 } else { 8392 if (adr.base_needs_rex()) { 8393 if (adr.index_needs_rex()) { 8394 prefix(REX_RXB); 8395 } else { 8396 prefix(REX_RB); 8397 } 8398 } else { 8399 if (adr.index_needs_rex()) { 8400 prefix(REX_RX); 8401 } else { 8402 prefix(REX_R); 8403 } 8404 } 8405 } 8406 } 8407 8408 void Assembler::prefixq(Address adr, Register src) { 8409 if (src->encoding() < 8) { 8410 if (adr.base_needs_rex()) { 8411 if (adr.index_needs_rex()) { 8412 prefix(REX_WXB); 8413 } else { 8414 prefix(REX_WB); 8415 } 8416 } else { 8417 if (adr.index_needs_rex()) { 8418 prefix(REX_WX); 8419 } else { 8420 prefix(REX_W); 8421 } 8422 } 8423 } else { 8424 if (adr.base_needs_rex()) { 8425 if (adr.index_needs_rex()) { 8426 prefix(REX_WRXB); 8427 } else { 8428 prefix(REX_WRB); 8429 } 8430 } else { 8431 if (adr.index_needs_rex()) { 8432 prefix(REX_WRX); 8433 } else { 8434 prefix(REX_WR); 8435 } 8436 } 8437 } 8438 } 8439 8440 void Assembler::prefix(Address adr, XMMRegister reg) { 8441 if (reg->encoding() < 8) { 8442 if (adr.base_needs_rex()) { 8443 if (adr.index_needs_rex()) { 8444 prefix(REX_XB); 8445 } else { 8446 prefix(REX_B); 8447 } 8448 } else { 8449 if (adr.index_needs_rex()) { 8450 prefix(REX_X); 8451 } 8452 } 8453 } else { 8454 if (adr.base_needs_rex()) { 8455 if (adr.index_needs_rex()) { 8456 prefix(REX_RXB); 8457 } else { 8458 prefix(REX_RB); 8459 } 8460 } else { 8461 if (adr.index_needs_rex()) { 8462 prefix(REX_RX); 8463 } else { 8464 prefix(REX_R); 8465 } 8466 } 8467 } 8468 } 8469 8470 void Assembler::prefixq(Address adr, XMMRegister src) { 8471 if (src->encoding() < 8) { 8472 if (adr.base_needs_rex()) { 8473 if (adr.index_needs_rex()) { 8474 prefix(REX_WXB); 8475 } else { 8476 prefix(REX_WB); 8477 } 8478 } else { 8479 if (adr.index_needs_rex()) { 8480 prefix(REX_WX); 8481 } else { 8482 prefix(REX_W); 8483 } 8484 } 8485 } else { 8486 if (adr.base_needs_rex()) { 8487 if (adr.index_needs_rex()) { 8488 prefix(REX_WRXB); 8489 } else { 8490 prefix(REX_WRB); 8491 } 8492 } else { 8493 if (adr.index_needs_rex()) { 8494 prefix(REX_WRX); 8495 } else { 8496 prefix(REX_WR); 8497 } 8498 } 8499 } 8500 } 8501 8502 void Assembler::adcq(Register dst, int32_t imm32) { 8503 (void) prefixq_and_encode(dst->encoding()); 8504 emit_arith(0x81, 0xD0, dst, imm32); 8505 } 8506 8507 void Assembler::adcq(Register dst, Address src) { 8508 InstructionMark im(this); 8509 prefixq(src, dst); 8510 emit_int8(0x13); 8511 emit_operand(dst, src); 8512 } 8513 8514 void Assembler::adcq(Register dst, Register src) { 8515 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8516 emit_arith(0x13, 0xC0, dst, src); 8517 } 8518 8519 void Assembler::addq(Address dst, int32_t imm32) { 8520 InstructionMark im(this); 8521 prefixq(dst); 8522 emit_arith_operand(0x81, rax, dst,imm32); 8523 } 8524 8525 void Assembler::addq(Address dst, Register src) { 8526 InstructionMark im(this); 8527 prefixq(dst, src); 8528 emit_int8(0x01); 8529 emit_operand(src, dst); 8530 } 8531 8532 void Assembler::addq(Register dst, int32_t imm32) { 8533 (void) prefixq_and_encode(dst->encoding()); 8534 emit_arith(0x81, 0xC0, dst, imm32); 8535 } 8536 8537 void Assembler::addq(Register dst, Address src) { 8538 InstructionMark im(this); 8539 prefixq(src, dst); 8540 emit_int8(0x03); 8541 emit_operand(dst, src); 8542 } 8543 8544 void Assembler::addq(Register dst, Register src) { 8545 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8546 emit_arith(0x03, 0xC0, dst, src); 8547 } 8548 8549 void Assembler::adcxq(Register dst, Register src) { 8550 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 8551 emit_int8((unsigned char)0x66); 8552 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8553 emit_int8(0x0F); 8554 emit_int8(0x38); 8555 emit_int8((unsigned char)0xF6); 8556 emit_int8((unsigned char)(0xC0 | encode)); 8557 } 8558 8559 void Assembler::adoxq(Register dst, Register src) { 8560 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 8561 emit_int8((unsigned char)0xF3); 8562 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8563 emit_int8(0x0F); 8564 emit_int8(0x38); 8565 emit_int8((unsigned char)0xF6); 8566 emit_int8((unsigned char)(0xC0 | encode)); 8567 } 8568 8569 void Assembler::andq(Address dst, int32_t imm32) { 8570 InstructionMark im(this); 8571 prefixq(dst); 8572 emit_int8((unsigned char)0x81); 8573 emit_operand(rsp, dst, 4); 8574 emit_int32(imm32); 8575 } 8576 8577 void Assembler::andq(Register dst, int32_t imm32) { 8578 (void) prefixq_and_encode(dst->encoding()); 8579 emit_arith(0x81, 0xE0, dst, imm32); 8580 } 8581 8582 void Assembler::andq(Register dst, Address src) { 8583 InstructionMark im(this); 8584 prefixq(src, dst); 8585 emit_int8(0x23); 8586 emit_operand(dst, src); 8587 } 8588 8589 void Assembler::andq(Register dst, Register src) { 8590 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8591 emit_arith(0x23, 0xC0, dst, src); 8592 } 8593 8594 void Assembler::andnq(Register dst, Register src1, Register src2) { 8595 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8596 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8597 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8598 emit_int8((unsigned char)0xF2); 8599 emit_int8((unsigned char)(0xC0 | encode)); 8600 } 8601 8602 void Assembler::andnq(Register dst, Register src1, Address src2) { 8603 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8604 InstructionMark im(this); 8605 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8606 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8607 emit_int8((unsigned char)0xF2); 8608 emit_operand(dst, src2); 8609 } 8610 8611 void Assembler::bsfq(Register dst, Register src) { 8612 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8613 emit_int8(0x0F); 8614 emit_int8((unsigned char)0xBC); 8615 emit_int8((unsigned char)(0xC0 | encode)); 8616 } 8617 8618 void Assembler::bsrq(Register dst, Register src) { 8619 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8620 emit_int8(0x0F); 8621 emit_int8((unsigned char)0xBD); 8622 emit_int8((unsigned char)(0xC0 | encode)); 8623 } 8624 8625 void Assembler::bswapq(Register reg) { 8626 int encode = prefixq_and_encode(reg->encoding()); 8627 emit_int8(0x0F); 8628 emit_int8((unsigned char)(0xC8 | encode)); 8629 } 8630 8631 void Assembler::blsiq(Register dst, Register src) { 8632 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8633 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8634 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8635 emit_int8((unsigned char)0xF3); 8636 emit_int8((unsigned char)(0xC0 | encode)); 8637 } 8638 8639 void Assembler::blsiq(Register dst, Address src) { 8640 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8641 InstructionMark im(this); 8642 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8643 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8644 emit_int8((unsigned char)0xF3); 8645 emit_operand(rbx, src); 8646 } 8647 8648 void Assembler::blsmskq(Register dst, Register src) { 8649 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8650 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8651 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8652 emit_int8((unsigned char)0xF3); 8653 emit_int8((unsigned char)(0xC0 | encode)); 8654 } 8655 8656 void Assembler::blsmskq(Register dst, Address src) { 8657 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8658 InstructionMark im(this); 8659 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8660 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8661 emit_int8((unsigned char)0xF3); 8662 emit_operand(rdx, src); 8663 } 8664 8665 void Assembler::blsrq(Register dst, Register src) { 8666 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8667 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8668 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8669 emit_int8((unsigned char)0xF3); 8670 emit_int8((unsigned char)(0xC0 | encode)); 8671 } 8672 8673 void Assembler::blsrq(Register dst, Address src) { 8674 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 8675 InstructionMark im(this); 8676 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 8677 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 8678 emit_int8((unsigned char)0xF3); 8679 emit_operand(rcx, src); 8680 } 8681 8682 void Assembler::cdqq() { 8683 prefix(REX_W); 8684 emit_int8((unsigned char)0x99); 8685 } 8686 8687 void Assembler::clflush(Address adr) { 8688 assert(VM_Version::supports_clflush(), "should do"); 8689 prefix(adr); 8690 emit_int8(0x0F); 8691 emit_int8((unsigned char)0xAE); 8692 emit_operand(rdi, adr); 8693 } 8694 8695 void Assembler::clflushopt(Address adr) { 8696 assert(VM_Version::supports_clflushopt(), "should do!"); 8697 // adr should be base reg only with no index or offset 8698 assert(adr.index() == noreg, "index should be noreg"); 8699 assert(adr.scale() == Address::no_scale, "scale should be no_scale"); 8700 assert(adr.disp() == 0, "displacement should be 0"); 8701 // instruction prefix is 0x66 8702 emit_int8(0x66); 8703 prefix(adr); 8704 // opcode family is 0x0f 0xAE 8705 emit_int8(0x0F); 8706 emit_int8((unsigned char)0xAE); 8707 // extended opcode byte is 7 == rdi 8708 emit_operand(rdi, adr); 8709 } 8710 8711 void Assembler::clwb(Address adr) { 8712 assert(VM_Version::supports_clwb(), "should do!"); 8713 // adr should be base reg only with no index or offset 8714 assert(adr.index() == noreg, "index should be noreg"); 8715 assert(adr.scale() == Address::no_scale, "scale should be no_scale"); 8716 assert(adr.disp() == 0, "displacement should be 0"); 8717 // instruction prefix is 0x66 8718 emit_int8(0x66); 8719 prefix(adr); 8720 // opcode family is 0x0f 0xAE 8721 emit_int8(0x0F); 8722 emit_int8((unsigned char)0xAE); 8723 // extended opcode byte is 6 == rsi 8724 emit_operand(rsi, adr); 8725 } 8726 8727 void Assembler::cmovq(Condition cc, Register dst, Register src) { 8728 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8729 emit_int8(0x0F); 8730 emit_int8(0x40 | cc); 8731 emit_int8((unsigned char)(0xC0 | encode)); 8732 } 8733 8734 void Assembler::cmovq(Condition cc, Register dst, Address src) { 8735 InstructionMark im(this); 8736 prefixq(src, dst); 8737 emit_int8(0x0F); 8738 emit_int8(0x40 | cc); 8739 emit_operand(dst, src); 8740 } 8741 8742 void Assembler::cmpq(Address dst, int32_t imm32) { 8743 InstructionMark im(this); 8744 prefixq(dst); 8745 emit_int8((unsigned char)0x81); 8746 emit_operand(rdi, dst, 4); 8747 emit_int32(imm32); 8748 } 8749 8750 void Assembler::cmpq(Register dst, int32_t imm32) { 8751 (void) prefixq_and_encode(dst->encoding()); 8752 emit_arith(0x81, 0xF8, dst, imm32); 8753 } 8754 8755 void Assembler::cmpq(Address dst, Register src) { 8756 InstructionMark im(this); 8757 prefixq(dst, src); 8758 emit_int8(0x3B); 8759 emit_operand(src, dst); 8760 } 8761 8762 void Assembler::cmpq(Register dst, Register src) { 8763 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8764 emit_arith(0x3B, 0xC0, dst, src); 8765 } 8766 8767 void Assembler::cmpq(Register dst, Address src) { 8768 InstructionMark im(this); 8769 prefixq(src, dst); 8770 emit_int8(0x3B); 8771 emit_operand(dst, src); 8772 } 8773 8774 void Assembler::cmpxchgq(Register reg, Address adr) { 8775 InstructionMark im(this); 8776 prefixq(adr, reg); 8777 emit_int8(0x0F); 8778 emit_int8((unsigned char)0xB1); 8779 emit_operand(reg, adr); 8780 } 8781 8782 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 8783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8784 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8785 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8786 emit_int8(0x2A); 8787 emit_int8((unsigned char)(0xC0 | encode)); 8788 } 8789 8790 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 8791 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8792 InstructionMark im(this); 8793 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8794 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8795 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8796 emit_int8(0x2A); 8797 emit_operand(dst, src); 8798 } 8799 8800 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 8801 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8802 InstructionMark im(this); 8803 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8806 emit_int8(0x2A); 8807 emit_operand(dst, src); 8808 } 8809 8810 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 8811 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8812 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8813 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8814 emit_int8(0x2C); 8815 emit_int8((unsigned char)(0xC0 | encode)); 8816 } 8817 8818 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 8819 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8820 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8821 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8822 emit_int8(0x2C); 8823 emit_int8((unsigned char)(0xC0 | encode)); 8824 } 8825 8826 void Assembler::decl(Register dst) { 8827 // Don't use it directly. Use MacroAssembler::decrementl() instead. 8828 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 8829 int encode = prefix_and_encode(dst->encoding()); 8830 emit_int8((unsigned char)0xFF); 8831 emit_int8((unsigned char)(0xC8 | encode)); 8832 } 8833 8834 void Assembler::decq(Register dst) { 8835 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8836 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8837 int encode = prefixq_and_encode(dst->encoding()); 8838 emit_int8((unsigned char)0xFF); 8839 emit_int8(0xC8 | encode); 8840 } 8841 8842 void Assembler::decq(Address dst) { 8843 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8844 InstructionMark im(this); 8845 prefixq(dst); 8846 emit_int8((unsigned char)0xFF); 8847 emit_operand(rcx, dst); 8848 } 8849 8850 void Assembler::fxrstor(Address src) { 8851 prefixq(src); 8852 emit_int8(0x0F); 8853 emit_int8((unsigned char)0xAE); 8854 emit_operand(as_Register(1), src); 8855 } 8856 8857 void Assembler::xrstor(Address src) { 8858 prefixq(src); 8859 emit_int8(0x0F); 8860 emit_int8((unsigned char)0xAE); 8861 emit_operand(as_Register(5), src); 8862 } 8863 8864 void Assembler::fxsave(Address dst) { 8865 prefixq(dst); 8866 emit_int8(0x0F); 8867 emit_int8((unsigned char)0xAE); 8868 emit_operand(as_Register(0), dst); 8869 } 8870 8871 void Assembler::xsave(Address dst) { 8872 prefixq(dst); 8873 emit_int8(0x0F); 8874 emit_int8((unsigned char)0xAE); 8875 emit_operand(as_Register(4), dst); 8876 } 8877 8878 void Assembler::idivq(Register src) { 8879 int encode = prefixq_and_encode(src->encoding()); 8880 emit_int8((unsigned char)0xF7); 8881 emit_int8((unsigned char)(0xF8 | encode)); 8882 } 8883 8884 void Assembler::imulq(Register dst, Register src) { 8885 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8886 emit_int8(0x0F); 8887 emit_int8((unsigned char)0xAF); 8888 emit_int8((unsigned char)(0xC0 | encode)); 8889 } 8890 8891 void Assembler::imulq(Register dst, Register src, int value) { 8892 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8893 if (is8bit(value)) { 8894 emit_int8(0x6B); 8895 emit_int8((unsigned char)(0xC0 | encode)); 8896 emit_int8(value & 0xFF); 8897 } else { 8898 emit_int8(0x69); 8899 emit_int8((unsigned char)(0xC0 | encode)); 8900 emit_int32(value); 8901 } 8902 } 8903 8904 void Assembler::imulq(Register dst, Address src) { 8905 InstructionMark im(this); 8906 prefixq(src, dst); 8907 emit_int8(0x0F); 8908 emit_int8((unsigned char) 0xAF); 8909 emit_operand(dst, src); 8910 } 8911 8912 void Assembler::incl(Register dst) { 8913 // Don't use it directly. Use MacroAssembler::incrementl() instead. 8914 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8915 int encode = prefix_and_encode(dst->encoding()); 8916 emit_int8((unsigned char)0xFF); 8917 emit_int8((unsigned char)(0xC0 | encode)); 8918 } 8919 8920 void Assembler::incq(Register dst) { 8921 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8922 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8923 int encode = prefixq_and_encode(dst->encoding()); 8924 emit_int8((unsigned char)0xFF); 8925 emit_int8((unsigned char)(0xC0 | encode)); 8926 } 8927 8928 void Assembler::incq(Address dst) { 8929 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8930 InstructionMark im(this); 8931 prefixq(dst); 8932 emit_int8((unsigned char)0xFF); 8933 emit_operand(rax, dst); 8934 } 8935 8936 void Assembler::lea(Register dst, Address src) { 8937 leaq(dst, src); 8938 } 8939 8940 void Assembler::leaq(Register dst, Address src) { 8941 InstructionMark im(this); 8942 prefixq(src, dst); 8943 emit_int8((unsigned char)0x8D); 8944 emit_operand(dst, src); 8945 } 8946 8947 void Assembler::mov64(Register dst, int64_t imm64) { 8948 InstructionMark im(this); 8949 int encode = prefixq_and_encode(dst->encoding()); 8950 emit_int8((unsigned char)(0xB8 | encode)); 8951 emit_int64(imm64); 8952 } 8953 8954 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 8955 InstructionMark im(this); 8956 int encode = prefixq_and_encode(dst->encoding()); 8957 emit_int8(0xB8 | encode); 8958 emit_data64(imm64, rspec); 8959 } 8960 8961 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 8962 InstructionMark im(this); 8963 int encode = prefix_and_encode(dst->encoding()); 8964 emit_int8((unsigned char)(0xB8 | encode)); 8965 emit_data((int)imm32, rspec, narrow_oop_operand); 8966 } 8967 8968 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 8969 InstructionMark im(this); 8970 prefix(dst); 8971 emit_int8((unsigned char)0xC7); 8972 emit_operand(rax, dst, 4); 8973 emit_data((int)imm32, rspec, narrow_oop_operand); 8974 } 8975 8976 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 8977 InstructionMark im(this); 8978 int encode = prefix_and_encode(src1->encoding()); 8979 emit_int8((unsigned char)0x81); 8980 emit_int8((unsigned char)(0xF8 | encode)); 8981 emit_data((int)imm32, rspec, narrow_oop_operand); 8982 } 8983 8984 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 8985 InstructionMark im(this); 8986 prefix(src1); 8987 emit_int8((unsigned char)0x81); 8988 emit_operand(rax, src1, 4); 8989 emit_data((int)imm32, rspec, narrow_oop_operand); 8990 } 8991 8992 void Assembler::lzcntq(Register dst, Register src) { 8993 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 8994 emit_int8((unsigned char)0xF3); 8995 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8996 emit_int8(0x0F); 8997 emit_int8((unsigned char)0xBD); 8998 emit_int8((unsigned char)(0xC0 | encode)); 8999 } 9000 9001 void Assembler::movdq(XMMRegister dst, Register src) { 9002 // table D-1 says MMX/SSE2 9003 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 9004 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 9005 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 9006 emit_int8(0x6E); 9007 emit_int8((unsigned char)(0xC0 | encode)); 9008 } 9009 9010 void Assembler::movdq(Register dst, XMMRegister src) { 9011 // table D-1 says MMX/SSE2 9012 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 9013 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 9014 // swap src/dst to get correct prefix 9015 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 9016 emit_int8(0x7E); 9017 emit_int8((unsigned char)(0xC0 | encode)); 9018 } 9019 9020 void Assembler::movq(Register dst, Register src) { 9021 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9022 emit_int8((unsigned char)0x8B); 9023 emit_int8((unsigned char)(0xC0 | encode)); 9024 } 9025 9026 void Assembler::movq(Register dst, Address src) { 9027 InstructionMark im(this); 9028 prefixq(src, dst); 9029 emit_int8((unsigned char)0x8B); 9030 emit_operand(dst, src); 9031 } 9032 9033 void Assembler::movq(Address dst, Register src) { 9034 InstructionMark im(this); 9035 prefixq(dst, src); 9036 emit_int8((unsigned char)0x89); 9037 emit_operand(src, dst); 9038 } 9039 9040 void Assembler::movsbq(Register dst, Address src) { 9041 InstructionMark im(this); 9042 prefixq(src, dst); 9043 emit_int8(0x0F); 9044 emit_int8((unsigned char)0xBE); 9045 emit_operand(dst, src); 9046 } 9047 9048 void Assembler::movsbq(Register dst, Register src) { 9049 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9050 emit_int8(0x0F); 9051 emit_int8((unsigned char)0xBE); 9052 emit_int8((unsigned char)(0xC0 | encode)); 9053 } 9054 9055 void Assembler::movslq(Register dst, int32_t imm32) { 9056 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 9057 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 9058 // as a result we shouldn't use until tested at runtime... 9059 ShouldNotReachHere(); 9060 InstructionMark im(this); 9061 int encode = prefixq_and_encode(dst->encoding()); 9062 emit_int8((unsigned char)(0xC7 | encode)); 9063 emit_int32(imm32); 9064 } 9065 9066 void Assembler::movslq(Address dst, int32_t imm32) { 9067 assert(is_simm32(imm32), "lost bits"); 9068 InstructionMark im(this); 9069 prefixq(dst); 9070 emit_int8((unsigned char)0xC7); 9071 emit_operand(rax, dst, 4); 9072 emit_int32(imm32); 9073 } 9074 9075 void Assembler::movslq(Register dst, Address src) { 9076 InstructionMark im(this); 9077 prefixq(src, dst); 9078 emit_int8(0x63); 9079 emit_operand(dst, src); 9080 } 9081 9082 void Assembler::movslq(Register dst, Register src) { 9083 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9084 emit_int8(0x63); 9085 emit_int8((unsigned char)(0xC0 | encode)); 9086 } 9087 9088 void Assembler::movswq(Register dst, Address src) { 9089 InstructionMark im(this); 9090 prefixq(src, dst); 9091 emit_int8(0x0F); 9092 emit_int8((unsigned char)0xBF); 9093 emit_operand(dst, src); 9094 } 9095 9096 void Assembler::movswq(Register dst, Register src) { 9097 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9098 emit_int8((unsigned char)0x0F); 9099 emit_int8((unsigned char)0xBF); 9100 emit_int8((unsigned char)(0xC0 | encode)); 9101 } 9102 9103 void Assembler::movzbq(Register dst, Address src) { 9104 InstructionMark im(this); 9105 prefixq(src, dst); 9106 emit_int8((unsigned char)0x0F); 9107 emit_int8((unsigned char)0xB6); 9108 emit_operand(dst, src); 9109 } 9110 9111 void Assembler::movzbq(Register dst, Register src) { 9112 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9113 emit_int8(0x0F); 9114 emit_int8((unsigned char)0xB6); 9115 emit_int8(0xC0 | encode); 9116 } 9117 9118 void Assembler::movzwq(Register dst, Address src) { 9119 InstructionMark im(this); 9120 prefixq(src, dst); 9121 emit_int8((unsigned char)0x0F); 9122 emit_int8((unsigned char)0xB7); 9123 emit_operand(dst, src); 9124 } 9125 9126 void Assembler::movzwq(Register dst, Register src) { 9127 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9128 emit_int8((unsigned char)0x0F); 9129 emit_int8((unsigned char)0xB7); 9130 emit_int8((unsigned char)(0xC0 | encode)); 9131 } 9132 9133 void Assembler::mulq(Address src) { 9134 InstructionMark im(this); 9135 prefixq(src); 9136 emit_int8((unsigned char)0xF7); 9137 emit_operand(rsp, src); 9138 } 9139 9140 void Assembler::mulq(Register src) { 9141 int encode = prefixq_and_encode(src->encoding()); 9142 emit_int8((unsigned char)0xF7); 9143 emit_int8((unsigned char)(0xE0 | encode)); 9144 } 9145 9146 void Assembler::mulxq(Register dst1, Register dst2, Register src) { 9147 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 9148 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 9149 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); 9150 emit_int8((unsigned char)0xF6); 9151 emit_int8((unsigned char)(0xC0 | encode)); 9152 } 9153 9154 void Assembler::negq(Register dst) { 9155 int encode = prefixq_and_encode(dst->encoding()); 9156 emit_int8((unsigned char)0xF7); 9157 emit_int8((unsigned char)(0xD8 | encode)); 9158 } 9159 9160 void Assembler::notq(Register dst) { 9161 int encode = prefixq_and_encode(dst->encoding()); 9162 emit_int8((unsigned char)0xF7); 9163 emit_int8((unsigned char)(0xD0 | encode)); 9164 } 9165 9166 void Assembler::btsq(Address dst, int imm8) { 9167 assert(isByte(imm8), "not a byte"); 9168 InstructionMark im(this); 9169 prefixq(dst); 9170 emit_int8((unsigned char)0x0F); 9171 emit_int8((unsigned char)0xBA); 9172 emit_operand(rbp /* 5 */, dst, 1); 9173 emit_int8(imm8); 9174 } 9175 9176 void Assembler::btrq(Address dst, int imm8) { 9177 assert(isByte(imm8), "not a byte"); 9178 InstructionMark im(this); 9179 prefixq(dst); 9180 emit_int8((unsigned char)0x0F); 9181 emit_int8((unsigned char)0xBA); 9182 emit_operand(rsi /* 6 */, dst, 1); 9183 emit_int8(imm8); 9184 } 9185 9186 void Assembler::orq(Address dst, int32_t imm32) { 9187 InstructionMark im(this); 9188 prefixq(dst); 9189 emit_int8((unsigned char)0x81); 9190 emit_operand(rcx, dst, 4); 9191 emit_int32(imm32); 9192 } 9193 9194 void Assembler::orq(Register dst, int32_t imm32) { 9195 (void) prefixq_and_encode(dst->encoding()); 9196 emit_arith(0x81, 0xC8, dst, imm32); 9197 } 9198 9199 void Assembler::orq(Register dst, Address src) { 9200 InstructionMark im(this); 9201 prefixq(src, dst); 9202 emit_int8(0x0B); 9203 emit_operand(dst, src); 9204 } 9205 9206 void Assembler::orq(Register dst, Register src) { 9207 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9208 emit_arith(0x0B, 0xC0, dst, src); 9209 } 9210 9211 void Assembler::popa() { // 64bit 9212 movq(r15, Address(rsp, 0)); 9213 movq(r14, Address(rsp, wordSize)); 9214 movq(r13, Address(rsp, 2 * wordSize)); 9215 movq(r12, Address(rsp, 3 * wordSize)); 9216 movq(r11, Address(rsp, 4 * wordSize)); 9217 movq(r10, Address(rsp, 5 * wordSize)); 9218 movq(r9, Address(rsp, 6 * wordSize)); 9219 movq(r8, Address(rsp, 7 * wordSize)); 9220 movq(rdi, Address(rsp, 8 * wordSize)); 9221 movq(rsi, Address(rsp, 9 * wordSize)); 9222 movq(rbp, Address(rsp, 10 * wordSize)); 9223 // skip rsp 9224 movq(rbx, Address(rsp, 12 * wordSize)); 9225 movq(rdx, Address(rsp, 13 * wordSize)); 9226 movq(rcx, Address(rsp, 14 * wordSize)); 9227 movq(rax, Address(rsp, 15 * wordSize)); 9228 9229 addq(rsp, 16 * wordSize); 9230 } 9231 9232 void Assembler::popcntq(Register dst, Address src) { 9233 assert(VM_Version::supports_popcnt(), "must support"); 9234 InstructionMark im(this); 9235 emit_int8((unsigned char)0xF3); 9236 prefixq(src, dst); 9237 emit_int8((unsigned char)0x0F); 9238 emit_int8((unsigned char)0xB8); 9239 emit_operand(dst, src); 9240 } 9241 9242 void Assembler::popcntq(Register dst, Register src) { 9243 assert(VM_Version::supports_popcnt(), "must support"); 9244 emit_int8((unsigned char)0xF3); 9245 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9246 emit_int8((unsigned char)0x0F); 9247 emit_int8((unsigned char)0xB8); 9248 emit_int8((unsigned char)(0xC0 | encode)); 9249 } 9250 9251 void Assembler::popq(Address dst) { 9252 InstructionMark im(this); 9253 prefixq(dst); 9254 emit_int8((unsigned char)0x8F); 9255 emit_operand(rax, dst); 9256 } 9257 9258 void Assembler::pusha() { // 64bit 9259 // we have to store original rsp. ABI says that 128 bytes 9260 // below rsp are local scratch. 9261 movq(Address(rsp, -5 * wordSize), rsp); 9262 9263 subq(rsp, 16 * wordSize); 9264 9265 movq(Address(rsp, 15 * wordSize), rax); 9266 movq(Address(rsp, 14 * wordSize), rcx); 9267 movq(Address(rsp, 13 * wordSize), rdx); 9268 movq(Address(rsp, 12 * wordSize), rbx); 9269 // skip rsp 9270 movq(Address(rsp, 10 * wordSize), rbp); 9271 movq(Address(rsp, 9 * wordSize), rsi); 9272 movq(Address(rsp, 8 * wordSize), rdi); 9273 movq(Address(rsp, 7 * wordSize), r8); 9274 movq(Address(rsp, 6 * wordSize), r9); 9275 movq(Address(rsp, 5 * wordSize), r10); 9276 movq(Address(rsp, 4 * wordSize), r11); 9277 movq(Address(rsp, 3 * wordSize), r12); 9278 movq(Address(rsp, 2 * wordSize), r13); 9279 movq(Address(rsp, wordSize), r14); 9280 movq(Address(rsp, 0), r15); 9281 } 9282 9283 void Assembler::pushq(Address src) { 9284 InstructionMark im(this); 9285 prefixq(src); 9286 emit_int8((unsigned char)0xFF); 9287 emit_operand(rsi, src); 9288 } 9289 9290 void Assembler::rclq(Register dst, int imm8) { 9291 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9292 int encode = prefixq_and_encode(dst->encoding()); 9293 if (imm8 == 1) { 9294 emit_int8((unsigned char)0xD1); 9295 emit_int8((unsigned char)(0xD0 | encode)); 9296 } else { 9297 emit_int8((unsigned char)0xC1); 9298 emit_int8((unsigned char)(0xD0 | encode)); 9299 emit_int8(imm8); 9300 } 9301 } 9302 9303 void Assembler::rcrq(Register dst, int imm8) { 9304 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9305 int encode = prefixq_and_encode(dst->encoding()); 9306 if (imm8 == 1) { 9307 emit_int8((unsigned char)0xD1); 9308 emit_int8((unsigned char)(0xD8 | encode)); 9309 } else { 9310 emit_int8((unsigned char)0xC1); 9311 emit_int8((unsigned char)(0xD8 | encode)); 9312 emit_int8(imm8); 9313 } 9314 } 9315 9316 void Assembler::rorq(Register dst, int imm8) { 9317 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9318 int encode = prefixq_and_encode(dst->encoding()); 9319 if (imm8 == 1) { 9320 emit_int8((unsigned char)0xD1); 9321 emit_int8((unsigned char)(0xC8 | encode)); 9322 } else { 9323 emit_int8((unsigned char)0xC1); 9324 emit_int8((unsigned char)(0xc8 | encode)); 9325 emit_int8(imm8); 9326 } 9327 } 9328 9329 void Assembler::rorxq(Register dst, Register src, int imm8) { 9330 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 9331 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 9332 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 9333 emit_int8((unsigned char)0xF0); 9334 emit_int8((unsigned char)(0xC0 | encode)); 9335 emit_int8(imm8); 9336 } 9337 9338 void Assembler::rorxd(Register dst, Register src, int imm8) { 9339 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 9340 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 9341 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 9342 emit_int8((unsigned char)0xF0); 9343 emit_int8((unsigned char)(0xC0 | encode)); 9344 emit_int8(imm8); 9345 } 9346 9347 void Assembler::sarq(Register dst, int imm8) { 9348 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9349 int encode = prefixq_and_encode(dst->encoding()); 9350 if (imm8 == 1) { 9351 emit_int8((unsigned char)0xD1); 9352 emit_int8((unsigned char)(0xF8 | encode)); 9353 } else { 9354 emit_int8((unsigned char)0xC1); 9355 emit_int8((unsigned char)(0xF8 | encode)); 9356 emit_int8(imm8); 9357 } 9358 } 9359 9360 void Assembler::sarq(Register dst) { 9361 int encode = prefixq_and_encode(dst->encoding()); 9362 emit_int8((unsigned char)0xD3); 9363 emit_int8((unsigned char)(0xF8 | encode)); 9364 } 9365 9366 void Assembler::sbbq(Address dst, int32_t imm32) { 9367 InstructionMark im(this); 9368 prefixq(dst); 9369 emit_arith_operand(0x81, rbx, dst, imm32); 9370 } 9371 9372 void Assembler::sbbq(Register dst, int32_t imm32) { 9373 (void) prefixq_and_encode(dst->encoding()); 9374 emit_arith(0x81, 0xD8, dst, imm32); 9375 } 9376 9377 void Assembler::sbbq(Register dst, Address src) { 9378 InstructionMark im(this); 9379 prefixq(src, dst); 9380 emit_int8(0x1B); 9381 emit_operand(dst, src); 9382 } 9383 9384 void Assembler::sbbq(Register dst, Register src) { 9385 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9386 emit_arith(0x1B, 0xC0, dst, src); 9387 } 9388 9389 void Assembler::shlq(Register dst, int imm8) { 9390 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9391 int encode = prefixq_and_encode(dst->encoding()); 9392 if (imm8 == 1) { 9393 emit_int8((unsigned char)0xD1); 9394 emit_int8((unsigned char)(0xE0 | encode)); 9395 } else { 9396 emit_int8((unsigned char)0xC1); 9397 emit_int8((unsigned char)(0xE0 | encode)); 9398 emit_int8(imm8); 9399 } 9400 } 9401 9402 void Assembler::shlq(Register dst) { 9403 int encode = prefixq_and_encode(dst->encoding()); 9404 emit_int8((unsigned char)0xD3); 9405 emit_int8((unsigned char)(0xE0 | encode)); 9406 } 9407 9408 void Assembler::shrq(Register dst, int imm8) { 9409 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 9410 int encode = prefixq_and_encode(dst->encoding()); 9411 emit_int8((unsigned char)0xC1); 9412 emit_int8((unsigned char)(0xE8 | encode)); 9413 emit_int8(imm8); 9414 } 9415 9416 void Assembler::shrq(Register dst) { 9417 int encode = prefixq_and_encode(dst->encoding()); 9418 emit_int8((unsigned char)0xD3); 9419 emit_int8(0xE8 | encode); 9420 } 9421 9422 void Assembler::subq(Address dst, int32_t imm32) { 9423 InstructionMark im(this); 9424 prefixq(dst); 9425 emit_arith_operand(0x81, rbp, dst, imm32); 9426 } 9427 9428 void Assembler::subq(Address dst, Register src) { 9429 InstructionMark im(this); 9430 prefixq(dst, src); 9431 emit_int8(0x29); 9432 emit_operand(src, dst); 9433 } 9434 9435 void Assembler::subq(Register dst, int32_t imm32) { 9436 (void) prefixq_and_encode(dst->encoding()); 9437 emit_arith(0x81, 0xE8, dst, imm32); 9438 } 9439 9440 // Force generation of a 4 byte immediate value even if it fits into 8bit 9441 void Assembler::subq_imm32(Register dst, int32_t imm32) { 9442 (void) prefixq_and_encode(dst->encoding()); 9443 emit_arith_imm32(0x81, 0xE8, dst, imm32); 9444 } 9445 9446 void Assembler::subq(Register dst, Address src) { 9447 InstructionMark im(this); 9448 prefixq(src, dst); 9449 emit_int8(0x2B); 9450 emit_operand(dst, src); 9451 } 9452 9453 void Assembler::subq(Register dst, Register src) { 9454 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9455 emit_arith(0x2B, 0xC0, dst, src); 9456 } 9457 9458 void Assembler::testq(Register dst, int32_t imm32) { 9459 // not using emit_arith because test 9460 // doesn't support sign-extension of 9461 // 8bit operands 9462 int encode = dst->encoding(); 9463 if (encode == 0) { 9464 prefix(REX_W); 9465 emit_int8((unsigned char)0xA9); 9466 } else { 9467 encode = prefixq_and_encode(encode); 9468 emit_int8((unsigned char)0xF7); 9469 emit_int8((unsigned char)(0xC0 | encode)); 9470 } 9471 emit_int32(imm32); 9472 } 9473 9474 void Assembler::testq(Register dst, Register src) { 9475 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9476 emit_arith(0x85, 0xC0, dst, src); 9477 } 9478 9479 void Assembler::testq(Register dst, Address src) { 9480 InstructionMark im(this); 9481 prefixq(src, dst); 9482 emit_int8((unsigned char)0x85); 9483 emit_operand(dst, src); 9484 } 9485 9486 void Assembler::xaddq(Address dst, Register src) { 9487 InstructionMark im(this); 9488 prefixq(dst, src); 9489 emit_int8(0x0F); 9490 emit_int8((unsigned char)0xC1); 9491 emit_operand(src, dst); 9492 } 9493 9494 void Assembler::xchgq(Register dst, Address src) { 9495 InstructionMark im(this); 9496 prefixq(src, dst); 9497 emit_int8((unsigned char)0x87); 9498 emit_operand(dst, src); 9499 } 9500 9501 void Assembler::xchgq(Register dst, Register src) { 9502 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 9503 emit_int8((unsigned char)0x87); 9504 emit_int8((unsigned char)(0xc0 | encode)); 9505 } 9506 9507 void Assembler::xorq(Register dst, Register src) { 9508 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 9509 emit_arith(0x33, 0xC0, dst, src); 9510 } 9511 9512 void Assembler::xorq(Register dst, Address src) { 9513 InstructionMark im(this); 9514 prefixq(src, dst); 9515 emit_int8(0x33); 9516 emit_operand(dst, src); 9517 } 9518 9519 #endif // !LP64