src/hotspot/cpu/x86/assembler_x86.cpp

*** 4255,4266 ****
    emit_int8(mode & 0xFF);
  }
  
  void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
    assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
!          vector_len == AVX_256bit? VM_Version::supports_avx2() :
!          0, "");
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
    emit_int8(0x70);
    emit_int8((unsigned char)(0xC0 | encode));
--- 4255,4266 ----
    emit_int8(mode & 0xFF);
  }
  
  void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
    assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
!          (vector_len == AVX_256bit? VM_Version::supports_avx2() :
!          (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
    emit_int8(0x70);
    emit_int8((unsigned char)(0xC0 | encode));
*** 4735,4744 ****
--- 4735,4774 ----
    int encode = prefix_and_encode(dst->encoding());
    emit_int8((unsigned char)0xD3);
    emit_int8((unsigned char)(0xE8 | encode));
  }
  
+ void Assembler::shldl(Register dst, Register src) {
+   int encode = prefix_and_encode(src->encoding(), dst->encoding());
+   emit_int8(0x0F);
+   emit_int8((unsigned char)0xA5);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::shldl(Register dst, Register src, int8_t imm8) {
+   int encode = prefix_and_encode(src->encoding(), dst->encoding());
+   emit_int8(0x0F);
+   emit_int8((unsigned char)0xA4);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(imm8);
+ }
+ 
+ void Assembler::shrdl(Register dst, Register src) {
+   int encode = prefix_and_encode(src->encoding(), dst->encoding());
+   emit_int8(0x0F);
+   emit_int8((unsigned char)0xAD);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
+   int encode = prefix_and_encode(src->encoding(), dst->encoding());
+   emit_int8(0x0F);
+   emit_int8((unsigned char)0xAC);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(imm8);
+ }
+ 
  // copies a single word from [esi] to [edi]
  void Assembler::smovl() {
    emit_int8((unsigned char)0xA5);
  }
  
*** 6511,6520 ****
--- 6541,6567 ----
    int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
    emit_int8((unsigned char)0xDB);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
+   assert(VM_Version::support_vbmi2(), "requires vbmi2");
+   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x71);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
+   assert(VM_Version::supports_vbmi2(), "requires vbmi2");
+   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x73);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
  
  void Assembler::pandn(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
    attributes.set_rex_vex_w_reverted();
*** 8107,8136 ****
    emit_int8(0x0F);
    emit_int8((unsigned char)0x95);
    emit_int8((unsigned char)(0xE0 | dst->encoding()));
  }
  
- void Assembler::shldl(Register dst, Register src) {
-   emit_int8(0x0F);
-   emit_int8((unsigned char)0xA5);
-   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
- }
- 
- // 0F A4 / r ib
- void Assembler::shldl(Register dst, Register src, int8_t imm8) {
-   emit_int8(0x0F);
-   emit_int8((unsigned char)0xA4);
-   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
-   emit_int8(imm8);
- }
- 
- void Assembler::shrdl(Register dst, Register src) {
-   emit_int8(0x0F);
-   emit_int8((unsigned char)0xAD);
-   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
- }
- 
  #else // LP64
  
  void Assembler::set_byte_if_not_zero(Register dst) {
    int enc = prefix_and_encode(dst->encoding(), true);
    emit_int8(0x0F);
--- 8154,8163 ----