src/hotspot/cpu/x86/assembler_x86.cpp

*** 4176,4185 ****
--- 4176,4196 ----
    emit_int8(0x73);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(shift);
  }
  
+ void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
+   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
+          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
+          vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
+   InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
+   emit_int8(0x73);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(shift & 0xFF);
+ }
+ 
  void Assembler::pslldq(XMMRegister dst, int shift) {
    // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
    // XMM7 is for /7 encoding: 66 0F 73 /7 ib
*** 4187,4196 ****
--- 4198,4218 ----
    emit_int8(0x73);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(shift);
  }
  
+ void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
+   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
+          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
+          vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
+   InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
+   emit_int8(0x73);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(shift & 0xFF);
+ }
+ 
  void Assembler::ptest(XMMRegister dst, Address src) {
    assert(VM_Version::supports_sse4_1(), "");
    assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
    InstructionMark im(this);
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
*** 4198,4208 ****
    emit_int8(0x17);
    emit_operand(dst, src);
  }
  
  void Assembler::ptest(XMMRegister dst, XMMRegister src) {
!   assert(VM_Version::supports_sse4_1(), "");
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x17);
    emit_int8((unsigned char)(0xC0 | encode));
  }
--- 4220,4230 ----
    emit_int8(0x17);
    emit_operand(dst, src);
  }
  
  void Assembler::ptest(XMMRegister dst, XMMRegister src) {
!   assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x17);
    emit_int8((unsigned char)(0xC0 | encode));
  }