1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  public:
  42   // Support for VM calls
  43   //
  44   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  45   // may customize this version by overriding it for its purposes (e.g., to save/restore
  46   // additional registers when doing a VM call).
  47 
  48   virtual void call_VM_leaf_base(
  49     address entry_point,               // the entry point
  50     int     number_of_arguments        // the number of arguments to pop after the call
  51   );
  52 
  53  protected:
  54   // This is the base routine called by the different versions of call_VM. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   //
  58   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  59   // returns the register which contains the thread upon return. If a thread register has been
  60   // specified, the return value will correspond to that register. If no last_java_sp is specified
  61   // (noreg) than rsp will be used instead.
  62   virtual void call_VM_base(           // returns the register containing the thread upon return
  63     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  64     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  65     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  66     address  entry_point,              // the entry point
  67     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  68     bool     check_exceptions          // whether to check for pending exceptions after return
  69   );
  70 
  71   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  72 
  73   // helpers for FPU flag access
  74   // tmp is a temporary register, if none is available use noreg
  75   void save_rax   (Register tmp);
  76   void restore_rax(Register tmp);
  77 
  78  public:
  79   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  80 
  81  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82  // The implementation is only non-empty for the InterpreterMacroAssembler,
  83  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84  virtual void check_and_handle_popframe(Register java_thread);
  85  virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   Address as_Address(AddressLiteral adr);
  88   Address as_Address(ArrayAddress adr);
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99   static bool uses_implicit_null_check(void* address);
 100 
 101   // Required platform-specific helpers for Label::patch_instructions.
 102   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 103   void pd_patch_instruction(address branch, address target, const char* file, int line) {
 104     unsigned char op = branch[0];
 105     assert(op == 0xE8 /* call */ ||
 106         op == 0xE9 /* jmp */ ||
 107         op == 0xEB /* short jmp */ ||
 108         (op & 0xF0) == 0x70 /* short jcc */ ||
 109         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 110         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 111         "Invalid opcode at patch point");
 112 
 113     if (op == 0xEB || (op & 0xF0) == 0x70) {
 114       // short offset operators (jmp and jcc)
 115       char* disp = (char*) &branch[1];
 116       int imm8 = target - (address) &disp[1];
 117       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
 118       *disp = imm8;
 119     } else {
 120       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 121       int imm32 = target - (address) &disp[1];
 122       *disp = imm32;
 123     }
 124   }
 125 
 126   // The following 4 methods return the offset of the appropriate move instruction
 127 
 128   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 129   int load_unsigned_byte(Register dst, Address src);
 130   int load_unsigned_short(Register dst, Address src);
 131 
 132   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 133   int load_signed_byte(Register dst, Address src);
 134   int load_signed_short(Register dst, Address src);
 135 
 136   // Support for sign-extension (hi:lo = extend_sign(lo))
 137   void extend_sign(Register hi, Register lo);
 138 
 139   // Load and store values by size and signed-ness
 140   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 141   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 142 
 143   // Support for inc/dec with optimal instruction selection depending on value
 144 
 145   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 146   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 147 
 148   void decrementl(Address dst, int value = 1);
 149   void decrementl(Register reg, int value = 1);
 150 
 151   void decrementq(Register reg, int value = 1);
 152   void decrementq(Address dst, int value = 1);
 153 
 154   void incrementl(Address dst, int value = 1);
 155   void incrementl(Register reg, int value = 1);
 156 
 157   void incrementq(Register reg, int value = 1);
 158   void incrementq(Address dst, int value = 1);
 159 
 160 #ifdef COMPILER2
 161   // special instructions for EVEX
 162   void setvectmask(Register dst, Register src);
 163   void restorevectmask();
 164 #endif
 165 
 166   // Support optimal SSE move instructions.
 167   void movflt(XMMRegister dst, XMMRegister src) {
 168     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 169     else                       { movss (dst, src); return; }
 170   }
 171   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 172   void movflt(XMMRegister dst, AddressLiteral src);
 173   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 174 
 175   void movdbl(XMMRegister dst, XMMRegister src) {
 176     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 177     else                       { movsd (dst, src); return; }
 178   }
 179 
 180   void movdbl(XMMRegister dst, AddressLiteral src);
 181 
 182   void movdbl(XMMRegister dst, Address src) {
 183     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 184     else                         { movlpd(dst, src); return; }
 185   }
 186   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 187 
 188   void incrementl(AddressLiteral dst);
 189   void incrementl(ArrayAddress dst);
 190 
 191   void incrementq(AddressLiteral dst);
 192 
 193   // Alignment
 194   void align(int modulus);
 195   void align(int modulus, int target);
 196 
 197   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 198   void fat_nop();
 199 
 200   // Stack frame creation/removal
 201   void enter();
 202   void leave();
 203 
 204   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 205   // The pointer will be loaded into the thread register.
 206   void get_thread(Register thread);
 207 
 208 
 209   // Support for VM calls
 210   //
 211   // It is imperative that all calls into the VM are handled via the call_VM macros.
 212   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 213   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 214 
 215 
 216   void call_VM(Register oop_result,
 217                address entry_point,
 218                bool check_exceptions = true);
 219   void call_VM(Register oop_result,
 220                address entry_point,
 221                Register arg_1,
 222                bool check_exceptions = true);
 223   void call_VM(Register oop_result,
 224                address entry_point,
 225                Register arg_1, Register arg_2,
 226                bool check_exceptions = true);
 227   void call_VM(Register oop_result,
 228                address entry_point,
 229                Register arg_1, Register arg_2, Register arg_3,
 230                bool check_exceptions = true);
 231 
 232   // Overloadings with last_Java_sp
 233   void call_VM(Register oop_result,
 234                Register last_java_sp,
 235                address entry_point,
 236                int number_of_arguments = 0,
 237                bool check_exceptions = true);
 238   void call_VM(Register oop_result,
 239                Register last_java_sp,
 240                address entry_point,
 241                Register arg_1, bool
 242                check_exceptions = true);
 243   void call_VM(Register oop_result,
 244                Register last_java_sp,
 245                address entry_point,
 246                Register arg_1, Register arg_2,
 247                bool check_exceptions = true);
 248   void call_VM(Register oop_result,
 249                Register last_java_sp,
 250                address entry_point,
 251                Register arg_1, Register arg_2, Register arg_3,
 252                bool check_exceptions = true);
 253 
 254   void get_vm_result  (Register oop_result, Register thread);
 255   void get_vm_result_2(Register metadata_result, Register thread);
 256 
 257   // These always tightly bind to MacroAssembler::call_VM_base
 258   // bypassing the virtual implementation
 259   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 260   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 261   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 263   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 264 
 265   void call_VM_leaf0(address entry_point);
 266   void call_VM_leaf(address entry_point,
 267                     int number_of_arguments = 0);
 268   void call_VM_leaf(address entry_point,
 269                     Register arg_1);
 270   void call_VM_leaf(address entry_point,
 271                     Register arg_1, Register arg_2);
 272   void call_VM_leaf(address entry_point,
 273                     Register arg_1, Register arg_2, Register arg_3);
 274 
 275   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 276   // bypassing the virtual implementation
 277   void super_call_VM_leaf(address entry_point);
 278   void super_call_VM_leaf(address entry_point, Register arg_1);
 279   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 280   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 281   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 282 
 283   // last Java Frame (fills frame anchor)
 284   void set_last_Java_frame(Register thread,
 285                            Register last_java_sp,
 286                            Register last_java_fp,
 287                            address last_java_pc);
 288 
 289   // thread in the default location (r15_thread on 64bit)
 290   void set_last_Java_frame(Register last_java_sp,
 291                            Register last_java_fp,
 292                            address last_java_pc);
 293 
 294   void reset_last_Java_frame(Register thread, bool clear_fp);
 295 
 296   // thread in the default location (r15_thread on 64bit)
 297   void reset_last_Java_frame(bool clear_fp);
 298 
 299   // jobjects
 300   void clear_jweak_tag(Register possibly_jweak);
 301   void resolve_jobject(Register value, Register thread, Register tmp);
 302 
 303   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 304   void c2bool(Register x);
 305 
 306   // C++ bool manipulation
 307 
 308   void movbool(Register dst, Address src);
 309   void movbool(Address dst, bool boolconst);
 310   void movbool(Address dst, Register src);
 311   void testbool(Register dst);
 312 
 313   void resolve_oop_handle(Register result, Register tmp = rscratch2);
 314   void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
 315 
 316   // oop manipulations
 317   void load_klass(Register dst, Register src);
 318   void store_klass(Register dst, Register src);
 319 
 320   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 321                       Register tmp1, Register thread_tmp);
 322   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 323                        Register tmp1, Register tmp2);
 324 
 325   // Resolves obj access. Result is placed in the same register.
 326   // All other registers are preserved.
 327   void resolve(DecoratorSet decorators, Register obj);
 328 
 329   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 330                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 331   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 332                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 333   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 334                       Register tmp2 = noreg, DecoratorSet decorators = 0);
 335 
 336   // Used for storing NULL. All other oop constants should be
 337   // stored using routines that take a jobject.
 338   void store_heap_oop_null(Address dst);
 339 
 340   void load_prototype_header(Register dst, Register src);
 341 
 342 #ifdef _LP64
 343   void store_klass_gap(Register dst, Register src);
 344 
 345   // This dummy is to prevent a call to store_heap_oop from
 346   // converting a zero (like NULL) into a Register by giving
 347   // the compiler two choices it can't resolve
 348 
 349   void store_heap_oop(Address dst, void* dummy);
 350 
 351   void encode_heap_oop(Register r);
 352   void decode_heap_oop(Register r);
 353   void encode_heap_oop_not_null(Register r);
 354   void decode_heap_oop_not_null(Register r);
 355   void encode_heap_oop_not_null(Register dst, Register src);
 356   void decode_heap_oop_not_null(Register dst, Register src);
 357 
 358   void set_narrow_oop(Register dst, jobject obj);
 359   void set_narrow_oop(Address dst, jobject obj);
 360   void cmp_narrow_oop(Register dst, jobject obj);
 361   void cmp_narrow_oop(Address dst, jobject obj);
 362 
 363   void encode_klass_not_null(Register r);
 364   void decode_klass_not_null(Register r);
 365   void encode_klass_not_null(Register dst, Register src);
 366   void decode_klass_not_null(Register dst, Register src);
 367   void set_narrow_klass(Register dst, Klass* k);
 368   void set_narrow_klass(Address dst, Klass* k);
 369   void cmp_narrow_klass(Register dst, Klass* k);
 370   void cmp_narrow_klass(Address dst, Klass* k);
 371 
 372   // Returns the byte size of the instructions generated by decode_klass_not_null()
 373   // when compressed klass pointers are being used.
 374   static int instr_size_for_decode_klass_not_null();
 375 
 376   // if heap base register is used - reinit it with the correct value
 377   void reinit_heapbase();
 378 
 379   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 380 
 381 #endif // _LP64
 382 
 383   // Int division/remainder for Java
 384   // (as idivl, but checks for special case as described in JVM spec.)
 385   // returns idivl instruction offset for implicit exception handling
 386   int corrected_idivl(Register reg);
 387 
 388   // Long division/remainder for Java
 389   // (as idivq, but checks for special case as described in JVM spec.)
 390   // returns idivq instruction offset for implicit exception handling
 391   int corrected_idivq(Register reg);
 392 
 393   void int3();
 394 
 395   // Long operation macros for a 32bit cpu
 396   // Long negation for Java
 397   void lneg(Register hi, Register lo);
 398 
 399   // Long multiplication for Java
 400   // (destroys contents of eax, ebx, ecx and edx)
 401   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 402 
 403   // Long shifts for Java
 404   // (semantics as described in JVM spec.)
 405   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 406   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 407 
 408   // Long compare for Java
 409   // (semantics as described in JVM spec.)
 410   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 411 
 412 
 413   // misc
 414 
 415   // Sign extension
 416   void sign_extend_short(Register reg);
 417   void sign_extend_byte(Register reg);
 418 
 419   // Division by power of 2, rounding towards 0
 420   void division_with_shift(Register reg, int shift_value);
 421 
 422   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 423   //
 424   // CF (corresponds to C0) if x < y
 425   // PF (corresponds to C2) if unordered
 426   // ZF (corresponds to C3) if x = y
 427   //
 428   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 429   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 430   void fcmp(Register tmp);
 431   // Variant of the above which allows y to be further down the stack
 432   // and which only pops x and y if specified. If pop_right is
 433   // specified then pop_left must also be specified.
 434   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 435 
 436   // Floating-point comparison for Java
 437   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 438   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 439   // (semantics as described in JVM spec.)
 440   void fcmp2int(Register dst, bool unordered_is_less);
 441   // Variant of the above which allows y to be further down the stack
 442   // and which only pops x and y if specified. If pop_right is
 443   // specified then pop_left must also be specified.
 444   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 445 
 446   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 447   // tmp is a temporary register, if none is available use noreg
 448   void fremr(Register tmp);
 449 
 450   // dst = c = a * b + c
 451   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 452   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 453 
 454   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 455   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 456   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 457   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 458 
 459 
 460   // same as fcmp2int, but using SSE2
 461   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 462   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 463 
 464   // branch to L if FPU flag C2 is set/not set
 465   // tmp is a temporary register, if none is available use noreg
 466   void jC2 (Register tmp, Label& L);
 467   void jnC2(Register tmp, Label& L);
 468 
 469   // Pop ST (ffree & fincstp combined)
 470   void fpop();
 471 
 472   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 473   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 474   void load_float(Address src);
 475 
 476   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 477   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 478   void store_float(Address dst);
 479 
 480   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 481   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 482   void load_double(Address src);
 483 
 484   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 485   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 486   void store_double(Address dst);
 487 
 488   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 489   void push_fTOS();
 490 
 491   // pops double TOS element from CPU stack and pushes on FPU stack
 492   void pop_fTOS();
 493 
 494   void empty_FPU_stack();
 495 
 496   void push_IU_state();
 497   void pop_IU_state();
 498 
 499   void push_FPU_state();
 500   void pop_FPU_state();
 501 
 502   void push_CPU_state();
 503   void pop_CPU_state();
 504 
 505   // Round up to a power of two
 506   void round_to(Register reg, int modulus);
 507 
 508   // Callee saved registers handling
 509   void push_callee_saved_registers();
 510   void pop_callee_saved_registers();
 511 
 512   // allocation
 513   void eden_allocate(
 514     Register thread,                   // Current thread
 515     Register obj,                      // result: pointer to object after successful allocation
 516     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 517     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 518     Register t1,                       // temp register
 519     Label&   slow_case                 // continuation point if fast allocation fails
 520   );
 521   void tlab_allocate(
 522     Register thread,                   // Current thread
 523     Register obj,                      // result: pointer to object after successful allocation
 524     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 525     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 526     Register t1,                       // temp register
 527     Register t2,                       // temp register
 528     Label&   slow_case                 // continuation point if fast allocation fails
 529   );
 530   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 531 
 532   // interface method calling
 533   void lookup_interface_method(Register recv_klass,
 534                                Register intf_klass,
 535                                RegisterOrConstant itable_index,
 536                                Register method_result,
 537                                Register scan_temp,
 538                                Label& no_such_interface,
 539                                bool return_method = true);
 540 
 541   // virtual method calling
 542   void lookup_virtual_method(Register recv_klass,
 543                              RegisterOrConstant vtable_index,
 544                              Register method_result);
 545 
 546   // Test sub_klass against super_klass, with fast and slow paths.
 547 
 548   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 549   // One of the three labels can be NULL, meaning take the fall-through.
 550   // If super_check_offset is -1, the value is loaded up from super_klass.
 551   // No registers are killed, except temp_reg.
 552   void check_klass_subtype_fast_path(Register sub_klass,
 553                                      Register super_klass,
 554                                      Register temp_reg,
 555                                      Label* L_success,
 556                                      Label* L_failure,
 557                                      Label* L_slow_path,
 558                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 559 
 560   // The rest of the type check; must be wired to a corresponding fast path.
 561   // It does not repeat the fast path logic, so don't use it standalone.
 562   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 563   // Updates the sub's secondary super cache as necessary.
 564   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 565   void check_klass_subtype_slow_path(Register sub_klass,
 566                                      Register super_klass,
 567                                      Register temp_reg,
 568                                      Register temp2_reg,
 569                                      Label* L_success,
 570                                      Label* L_failure,
 571                                      bool set_cond_codes = false);
 572 
 573   // Simplified, combined version, good for typical uses.
 574   // Falls through on failure.
 575   void check_klass_subtype(Register sub_klass,
 576                            Register super_klass,
 577                            Register temp_reg,
 578                            Label& L_success);
 579 
 580   // method handles (JSR 292)
 581   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 582 
 583   //----
 584   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 585 
 586   // Debugging
 587 
 588   // only if +VerifyOops
 589   // TODO: Make these macros with file and line like sparc version!
 590   void verify_oop(Register reg, const char* s = "broken oop");
 591   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 592 
 593   // TODO: verify method and klass metadata (compare against vptr?)
 594   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 595   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 596 
 597 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 598 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 599 
 600   // only if +VerifyFPU
 601   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 602 
 603   // Verify or restore cpu control state after JNI call
 604   void restore_cpu_control_state_after_jni();
 605 
 606   // prints msg, dumps registers and stops execution
 607   void stop(const char* msg);
 608 
 609   // prints msg and continues
 610   void warn(const char* msg);
 611 
 612   // dumps registers and other state
 613   void print_state();
 614 
 615   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 616   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 617   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 618   static void print_state64(int64_t pc, int64_t regs[]);
 619 
 620   void os_breakpoint();
 621 
 622   void untested()                                { stop("untested"); }
 623 
 624   void unimplemented(const char* what = "");
 625 
 626   void should_not_reach_here()                   { stop("should not reach here"); }
 627 
 628   void print_CPU_state();
 629 
 630   // Stack overflow checking
 631   void bang_stack_with_offset(int offset) {
 632     // stack grows down, caller passes positive offset
 633     assert(offset > 0, "must bang with negative offset");
 634     movl(Address(rsp, (-offset)), rax);
 635   }
 636 
 637   // Writes to stack successive pages until offset reached to check for
 638   // stack overflow + shadow pages.  Also, clobbers tmp
 639   void bang_stack_size(Register size, Register tmp);
 640 
 641   // Check for reserved stack access in method being exited (for JIT)
 642   void reserved_stack_check();
 643 
 644   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 645                                                 Register tmp,
 646                                                 int offset);
 647 
 648   // If thread_reg is != noreg the code assumes the register passed contains
 649   // the thread (required on 64 bit).
 650   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 651 
 652   void verify_tlab();
 653 
 654   // Biased locking support
 655   // lock_reg and obj_reg must be loaded up with the appropriate values.
 656   // swap_reg must be rax, and is killed.
 657   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 658   // be killed; if not supplied, push/pop will be used internally to
 659   // allocate a temporary (inefficient, avoid if possible).
 660   // Optional slow case is for implementations (interpreter and C1) which branch to
 661   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 662   // Returns offset of first potentially-faulting instruction for null
 663   // check info (currently consumed only by C1). If
 664   // swap_reg_contains_mark is true then returns -1 as it is assumed
 665   // the calling code has already passed any potential faults.
 666   int biased_locking_enter(Register lock_reg, Register obj_reg,
 667                            Register swap_reg, Register tmp_reg,
 668                            bool swap_reg_contains_mark,
 669                            Label& done, Label* slow_case = NULL,
 670                            BiasedLockingCounters* counters = NULL);
 671   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 672 #ifdef COMPILER2
 673   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 674   // See full desription in macroAssembler_x86.cpp.
 675   void fast_lock(Register obj, Register box, Register tmp,
 676                  Register scr, Register cx1, Register cx2,
 677                  BiasedLockingCounters* counters,
 678                  RTMLockingCounters* rtm_counters,
 679                  RTMLockingCounters* stack_rtm_counters,
 680                  Metadata* method_data,
 681                  bool use_rtm, bool profile_rtm);
 682   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 683 #if INCLUDE_RTM_OPT
 684   void rtm_counters_update(Register abort_status, Register rtm_counters);
 685   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 686   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 687                                    RTMLockingCounters* rtm_counters,
 688                                    Metadata* method_data);
 689   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 690                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 691   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 692   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 693   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 694                          Register retry_on_abort_count,
 695                          RTMLockingCounters* stack_rtm_counters,
 696                          Metadata* method_data, bool profile_rtm,
 697                          Label& DONE_LABEL, Label& IsInflated);
 698   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 699                             Register scr, Register retry_on_busy_count,
 700                             Register retry_on_abort_count,
 701                             RTMLockingCounters* rtm_counters,
 702                             Metadata* method_data, bool profile_rtm,
 703                             Label& DONE_LABEL);
 704 #endif
 705 #endif
 706 
 707   Condition negate_condition(Condition cond);
 708 
 709   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 710   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 711   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 712   // here in MacroAssembler. The major exception to this rule is call
 713 
 714   // Arithmetics
 715 
 716 
 717   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 718   void addptr(Address dst, Register src);
 719 
 720   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 721   void addptr(Register dst, int32_t src);
 722   void addptr(Register dst, Register src);
 723   void addptr(Register dst, RegisterOrConstant src) {
 724     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 725     else                   addptr(dst,       src.as_register());
 726   }
 727 
 728   void andptr(Register dst, int32_t src);
 729   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 730 
 731   void cmp8(AddressLiteral src1, int imm);
 732 
 733   // renamed to drag out the casting of address to int32_t/intptr_t
 734   void cmp32(Register src1, int32_t imm);
 735 
 736   void cmp32(AddressLiteral src1, int32_t imm);
 737   // compare reg - mem, or reg - &mem
 738   void cmp32(Register src1, AddressLiteral src2);
 739 
 740   void cmp32(Register src1, Address src2);
 741 
 742 #ifndef _LP64
 743   void cmpklass(Address dst, Metadata* obj);
 744   void cmpklass(Register dst, Metadata* obj);
 745   void cmpoop(Address dst, jobject obj);
 746   void cmpoop_raw(Address dst, jobject obj);
 747 #endif // _LP64
 748 
 749   void cmpoop(Register src1, Register src2);
 750   void cmpoop(Register src1, Address src2);
 751   void cmpoop(Register dst, jobject obj);
 752   void cmpoop_raw(Register dst, jobject obj);
 753 
 754   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 755   void cmpptr(Address src1, AddressLiteral src2);
 756 
 757   void cmpptr(Register src1, AddressLiteral src2);
 758 
 759   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 760   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 761   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 762 
 763   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 764   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 765 
 766   // cmp64 to avoild hiding cmpq
 767   void cmp64(Register src1, AddressLiteral src);
 768 
 769   void cmpxchgptr(Register reg, Address adr);
 770 
 771   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 772 
 773 
 774   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 775   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 776 
 777 
 778   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 779 
 780   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 781 
 782   void shlptr(Register dst, int32_t shift);
 783   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 784 
 785   void shrptr(Register dst, int32_t shift);
 786   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 787 
 788   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 789   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 790 
 791   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 792 
 793   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 794   void subptr(Register dst, int32_t src);
 795   // Force generation of a 4 byte immediate value even if it fits into 8bit
 796   void subptr_imm32(Register dst, int32_t src);
 797   void subptr(Register dst, Register src);
 798   void subptr(Register dst, RegisterOrConstant src) {
 799     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 800     else                   subptr(dst,       src.as_register());
 801   }
 802 
 803   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 804   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 805 
 806   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 807   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 808 
 809   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 810 
 811 
 812 
 813   // Helper functions for statistics gathering.
 814   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 815   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 816   // Unconditional atomic increment.
 817   void atomic_incl(Address counter_addr);
 818   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 819 #ifdef _LP64
 820   void atomic_incq(Address counter_addr);
 821   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 822 #endif
 823   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 824   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 825 
 826   void lea(Register dst, AddressLiteral adr);
 827   void lea(Address dst, AddressLiteral adr);
 828   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 829 
 830   void leal32(Register dst, Address src) { leal(dst, src); }
 831 
 832   // Import other testl() methods from the parent class or else
 833   // they will be hidden by the following overriding declaration.
 834   using Assembler::testl;
 835   void testl(Register dst, AddressLiteral src);
 836 
 837   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 838   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 839   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 840   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 841 
 842   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 843   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 844   void testptr(Register src1, Register src2);
 845 
 846   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 847   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 848 
 849   // Calls
 850 
 851   void call(Label& L, relocInfo::relocType rtype);
 852   void call(Register entry);
 853 
 854   // NOTE: this call transfers to the effective address of entry NOT
 855   // the address contained by entry. This is because this is more natural
 856   // for jumps/calls.
 857   void call(AddressLiteral entry);
 858 
 859   // Emit the CompiledIC call idiom
 860   void ic_call(address entry, jint method_index = 0);
 861 
 862   // Jumps
 863 
 864   // NOTE: these jumps tranfer to the effective address of dst NOT
 865   // the address contained by dst. This is because this is more natural
 866   // for jumps/calls.
 867   void jump(AddressLiteral dst);
 868   void jump_cc(Condition cc, AddressLiteral dst);
 869 
 870   // 32bit can do a case table jump in one instruction but we no longer allow the base
 871   // to be installed in the Address class. This jump will tranfers to the address
 872   // contained in the location described by entry (not the address of entry)
 873   void jump(ArrayAddress entry);
 874 
 875   // Floating
 876 
 877   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 878   void andpd(XMMRegister dst, AddressLiteral src);
 879   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 880 
 881   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 882   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 883   void andps(XMMRegister dst, AddressLiteral src);
 884 
 885   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 886   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 887   void comiss(XMMRegister dst, AddressLiteral src);
 888 
 889   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 890   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 891   void comisd(XMMRegister dst, AddressLiteral src);
 892 
 893   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 894   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 895 
 896   void fldcw(Address src) { Assembler::fldcw(src); }
 897   void fldcw(AddressLiteral src);
 898 
 899   void fld_s(int index)   { Assembler::fld_s(index); }
 900   void fld_s(Address src) { Assembler::fld_s(src); }
 901   void fld_s(AddressLiteral src);
 902 
 903   void fld_d(Address src) { Assembler::fld_d(src); }
 904   void fld_d(AddressLiteral src);
 905 
 906   void fld_x(Address src) { Assembler::fld_x(src); }
 907   void fld_x(AddressLiteral src);
 908 
 909   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 910   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 911 
 912   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 913   void ldmxcsr(AddressLiteral src);
 914 
 915 #ifdef _LP64
 916  private:
 917   void sha256_AVX2_one_round_compute(
 918     Register  reg_old_h,
 919     Register  reg_a,
 920     Register  reg_b,
 921     Register  reg_c,
 922     Register  reg_d,
 923     Register  reg_e,
 924     Register  reg_f,
 925     Register  reg_g,
 926     Register  reg_h,
 927     int iter);
 928   void sha256_AVX2_four_rounds_compute_first(int start);
 929   void sha256_AVX2_four_rounds_compute_last(int start);
 930   void sha256_AVX2_one_round_and_sched(
 931         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 932         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 933         XMMRegister xmm_2,     /* ymm6 */
 934         XMMRegister xmm_3,     /* ymm7 */
 935         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 936         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 937         Register    reg_c,      /* edi */
 938         Register    reg_d,      /* esi */
 939         Register    reg_e,      /* r8d */
 940         Register    reg_f,      /* r9d */
 941         Register    reg_g,      /* r10d */
 942         Register    reg_h,      /* r11d */
 943         int iter);
 944 
 945   void addm(int disp, Register r1, Register r2);




 946 
 947  public:
 948   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 949                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 950                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 951                    bool multi_block, XMMRegister shuf_mask);

 952 #endif
 953 
 954 #ifdef _LP64
 955  private:
 956   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 957                                      Register e, Register f, Register g, Register h, int iteration);
 958 
 959   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 960                                           Register a, Register b, Register c, Register d, Register e, Register f,
 961                                           Register g, Register h, int iteration);
 962 
 963   void addmq(int disp, Register r1, Register r2);
 964  public:
 965   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 966                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 967                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 968                    XMMRegister shuf_mask);
 969 #endif
 970 
 971   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 972                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 973                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 974                  bool multi_block);
 975 
 976 #ifdef _LP64
 977   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 978                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 979                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 980                    bool multi_block, XMMRegister shuf_mask);
 981 #else
 982   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 983                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 984                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 985                    bool multi_block);
 986 #endif
 987 
 988   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 989                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 990                 Register rax, Register rcx, Register rdx, Register tmp);
 991 
 992 #ifdef _LP64
 993   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 994                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 995                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
 996 
 997   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 998                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 999                   Register rax, Register rcx, Register rdx, Register r11);
1000 
1001   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1002                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1003                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1004 
1005   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1006                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1007                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1008                 Register tmp3, Register tmp4);
1009 
1010   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1011                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1012                 Register rax, Register rcx, Register rdx, Register tmp1,
1013                 Register tmp2, Register tmp3, Register tmp4);
1014   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1015                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1016                 Register rax, Register rcx, Register rdx, Register tmp1,
1017                 Register tmp2, Register tmp3, Register tmp4);
1018 #else
1019   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1020                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1021                 Register rax, Register rcx, Register rdx, Register tmp1);
1022 
1023   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1024                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1025                 Register rax, Register rcx, Register rdx, Register tmp);
1026 
1027   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1028                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1029                 Register rdx, Register tmp);
1030 
1031   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033                 Register rax, Register rbx, Register rdx);
1034 
1035   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1036                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1037                 Register rax, Register rcx, Register rdx, Register tmp);
1038 
1039   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1040                         Register edx, Register ebx, Register esi, Register edi,
1041                         Register ebp, Register esp);
1042 
1043   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1044                          Register esi, Register edi, Register ebp, Register esp);
1045 
1046   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1047                         Register edx, Register ebx, Register esi, Register edi,
1048                         Register ebp, Register esp);
1049 
1050   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1051                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1052                 Register rax, Register rcx, Register rdx, Register tmp);
1053 #endif
1054 
1055   void increase_precision();
1056   void restore_precision();
1057 
1058 private:
1059 
1060   // these are private because users should be doing movflt/movdbl
1061 
1062   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1063   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1064   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1065   void movss(XMMRegister dst, AddressLiteral src);
1066 
1067   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1068   void movlpd(XMMRegister dst, AddressLiteral src);
1069 
1070 public:
1071 
1072   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1073   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1074   void addsd(XMMRegister dst, AddressLiteral src);
1075 
1076   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1077   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1078   void addss(XMMRegister dst, AddressLiteral src);
1079 
1080   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1081   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1082   void addpd(XMMRegister dst, AddressLiteral src);
1083 
1084   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1085   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1086   void divsd(XMMRegister dst, AddressLiteral src);
1087 
1088   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1089   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1090   void divss(XMMRegister dst, AddressLiteral src);
1091 
1092   // Move Unaligned Double Quadword
1093   void movdqu(Address     dst, XMMRegister src);
1094   void movdqu(XMMRegister dst, Address src);
1095   void movdqu(XMMRegister dst, XMMRegister src);
1096   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1097   // AVX Unaligned forms
1098   void vmovdqu(Address     dst, XMMRegister src);
1099   void vmovdqu(XMMRegister dst, Address src);
1100   void vmovdqu(XMMRegister dst, XMMRegister src);
1101   void vmovdqu(XMMRegister dst, AddressLiteral src);
1102   void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1103   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1104   void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1105   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1106 
1107   // Move Aligned Double Quadword
1108   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1109   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1110   void movdqa(XMMRegister dst, AddressLiteral src);
1111 
1112   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1113   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1114   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1115   void movsd(XMMRegister dst, AddressLiteral src);
1116 
1117   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1118   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1119   void mulpd(XMMRegister dst, AddressLiteral src);
1120 
1121   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1122   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1123   void mulsd(XMMRegister dst, AddressLiteral src);
1124 
1125   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1126   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1127   void mulss(XMMRegister dst, AddressLiteral src);
1128 
1129   // Carry-Less Multiplication Quadword
1130   void pclmulldq(XMMRegister dst, XMMRegister src) {
1131     // 0x00 - multiply lower 64 bits [0:63]
1132     Assembler::pclmulqdq(dst, src, 0x00);
1133   }
1134   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1135     // 0x11 - multiply upper 64 bits [64:127]
1136     Assembler::pclmulqdq(dst, src, 0x11);
1137   }
1138 
1139   void pcmpeqb(XMMRegister dst, XMMRegister src);
1140   void pcmpeqw(XMMRegister dst, XMMRegister src);
1141 
1142   void pcmpestri(XMMRegister dst, Address src, int imm8);
1143   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1144 
1145   void pmovzxbw(XMMRegister dst, XMMRegister src);
1146   void pmovzxbw(XMMRegister dst, Address src);
1147 
1148   void pmovmskb(Register dst, XMMRegister src);
1149 
1150   void ptest(XMMRegister dst, XMMRegister src);
1151 
1152   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1153   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1154   void sqrtsd(XMMRegister dst, AddressLiteral src);
1155 
1156   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1157   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1158   void sqrtss(XMMRegister dst, AddressLiteral src);
1159 
1160   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1161   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1162   void subsd(XMMRegister dst, AddressLiteral src);
1163 
1164   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1165   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1166   void subss(XMMRegister dst, AddressLiteral src);
1167 
1168   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1169   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1170   void ucomiss(XMMRegister dst, AddressLiteral src);
1171 
1172   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1173   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1174   void ucomisd(XMMRegister dst, AddressLiteral src);
1175 
1176   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1177   void xorpd(XMMRegister dst, XMMRegister src);
1178   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1179   void xorpd(XMMRegister dst, AddressLiteral src);
1180 
1181   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1182   void xorps(XMMRegister dst, XMMRegister src);
1183   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1184   void xorps(XMMRegister dst, AddressLiteral src);
1185 
1186   // Shuffle Bytes
1187   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1188   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1189   void pshufb(XMMRegister dst, AddressLiteral src);
1190   // AVX 3-operands instructions
1191 
1192   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1193   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1194   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1195 
1196   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1197   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1198   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1199 
1200   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1201   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1202 
1203   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1204   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1205 
1206   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1207   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1208 
1209   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1210   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1211   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1212 
1213   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1214   void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1215 
1216   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1217 
1218   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1219 
1220   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1221   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1222 
1223   void vpmovmskb(Register dst, XMMRegister src);
1224 
1225   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1226   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1227 
1228   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1229   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1230 
1231   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1232   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1233 
1234   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1235   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1236 
1237   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1238   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1239 
1240   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1241   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1242 
1243   void vptest(XMMRegister dst, XMMRegister src);
1244 
1245   void punpcklbw(XMMRegister dst, XMMRegister src);
1246   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1247 
1248   void pshufd(XMMRegister dst, Address src, int mode);
1249   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1250 
1251   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1252   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1253 
1254   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1255   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1256   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1257 
1258   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1259   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1260   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1261 
1262   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1263   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1264   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1265 
1266   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1267   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1268   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1269 
1270   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1271   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1272   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1273 
1274   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1275   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1276   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1277 
1278   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1279   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1280   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1281 
1282   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1283   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1284   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1285 
1286   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1287   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1288 
1289   // AVX Vector instructions
1290 
1291   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1292   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1293   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1294 
1295   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1296   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1297   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1298 
1299   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1300     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1301       Assembler::vpxor(dst, nds, src, vector_len);
1302     else
1303       Assembler::vxorpd(dst, nds, src, vector_len);
1304   }
1305   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1306     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1307       Assembler::vpxor(dst, nds, src, vector_len);
1308     else
1309       Assembler::vxorpd(dst, nds, src, vector_len);
1310   }
1311 
1312   // Simple version for AVX2 256bit vectors
1313   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1314   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1315 
1316   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1317     if (UseAVX > 2) {
1318       Assembler::vinserti32x4(dst, dst, src, imm8);
1319     } else if (UseAVX > 1) {
1320       // vinserti128 is available only in AVX2
1321       Assembler::vinserti128(dst, nds, src, imm8);
1322     } else {
1323       Assembler::vinsertf128(dst, nds, src, imm8);
1324     }
1325   }
1326 
1327   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1328     if (UseAVX > 2) {
1329       Assembler::vinserti32x4(dst, dst, src, imm8);
1330     } else if (UseAVX > 1) {
1331       // vinserti128 is available only in AVX2
1332       Assembler::vinserti128(dst, nds, src, imm8);
1333     } else {
1334       Assembler::vinsertf128(dst, nds, src, imm8);
1335     }
1336   }
1337 
1338   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1339     if (UseAVX > 2) {
1340       Assembler::vextracti32x4(dst, src, imm8);
1341     } else if (UseAVX > 1) {
1342       // vextracti128 is available only in AVX2
1343       Assembler::vextracti128(dst, src, imm8);
1344     } else {
1345       Assembler::vextractf128(dst, src, imm8);
1346     }
1347   }
1348 
1349   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1350     if (UseAVX > 2) {
1351       Assembler::vextracti32x4(dst, src, imm8);
1352     } else if (UseAVX > 1) {
1353       // vextracti128 is available only in AVX2
1354       Assembler::vextracti128(dst, src, imm8);
1355     } else {
1356       Assembler::vextractf128(dst, src, imm8);
1357     }
1358   }
1359 
1360   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1361   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1362     vinserti128(dst, dst, src, 1);
1363   }
1364   void vinserti128_high(XMMRegister dst, Address src) {
1365     vinserti128(dst, dst, src, 1);
1366   }
1367   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1368     vextracti128(dst, src, 1);
1369   }
1370   void vextracti128_high(Address dst, XMMRegister src) {
1371     vextracti128(dst, src, 1);
1372   }
1373 
1374   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1375     if (UseAVX > 2) {
1376       Assembler::vinsertf32x4(dst, dst, src, 1);
1377     } else {
1378       Assembler::vinsertf128(dst, dst, src, 1);
1379     }
1380   }
1381 
1382   void vinsertf128_high(XMMRegister dst, Address src) {
1383     if (UseAVX > 2) {
1384       Assembler::vinsertf32x4(dst, dst, src, 1);
1385     } else {
1386       Assembler::vinsertf128(dst, dst, src, 1);
1387     }
1388   }
1389 
1390   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1391     if (UseAVX > 2) {
1392       Assembler::vextractf32x4(dst, src, 1);
1393     } else {
1394       Assembler::vextractf128(dst, src, 1);
1395     }
1396   }
1397 
1398   void vextractf128_high(Address dst, XMMRegister src) {
1399     if (UseAVX > 2) {
1400       Assembler::vextractf32x4(dst, src, 1);
1401     } else {
1402       Assembler::vextractf128(dst, src, 1);
1403     }
1404   }
1405 
1406   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1407   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1408     Assembler::vinserti64x4(dst, dst, src, 1);
1409   }
1410   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1411     Assembler::vinsertf64x4(dst, dst, src, 1);
1412   }
1413   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1414     Assembler::vextracti64x4(dst, src, 1);
1415   }
1416   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1417     Assembler::vextractf64x4(dst, src, 1);
1418   }
1419   void vextractf64x4_high(Address dst, XMMRegister src) {
1420     Assembler::vextractf64x4(dst, src, 1);
1421   }
1422   void vinsertf64x4_high(XMMRegister dst, Address src) {
1423     Assembler::vinsertf64x4(dst, dst, src, 1);
1424   }
1425 
1426   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1427   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1428     vinserti128(dst, dst, src, 0);
1429   }
1430   void vinserti128_low(XMMRegister dst, Address src) {
1431     vinserti128(dst, dst, src, 0);
1432   }
1433   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1434     vextracti128(dst, src, 0);
1435   }
1436   void vextracti128_low(Address dst, XMMRegister src) {
1437     vextracti128(dst, src, 0);
1438   }
1439 
1440   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1441     if (UseAVX > 2) {
1442       Assembler::vinsertf32x4(dst, dst, src, 0);
1443     } else {
1444       Assembler::vinsertf128(dst, dst, src, 0);
1445     }
1446   }
1447 
1448   void vinsertf128_low(XMMRegister dst, Address src) {
1449     if (UseAVX > 2) {
1450       Assembler::vinsertf32x4(dst, dst, src, 0);
1451     } else {
1452       Assembler::vinsertf128(dst, dst, src, 0);
1453     }
1454   }
1455 
1456   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1457     if (UseAVX > 2) {
1458       Assembler::vextractf32x4(dst, src, 0);
1459     } else {
1460       Assembler::vextractf128(dst, src, 0);
1461     }
1462   }
1463 
1464   void vextractf128_low(Address dst, XMMRegister src) {
1465     if (UseAVX > 2) {
1466       Assembler::vextractf32x4(dst, src, 0);
1467     } else {
1468       Assembler::vextractf128(dst, src, 0);
1469     }
1470   }
1471 
1472   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1473   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1474     Assembler::vinserti64x4(dst, dst, src, 0);
1475   }
1476   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1477     Assembler::vinsertf64x4(dst, dst, src, 0);
1478   }
1479   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1480     Assembler::vextracti64x4(dst, src, 0);
1481   }
1482   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1483     Assembler::vextractf64x4(dst, src, 0);
1484   }
1485   void vextractf64x4_low(Address dst, XMMRegister src) {
1486     Assembler::vextractf64x4(dst, src, 0);
1487   }
1488   void vinsertf64x4_low(XMMRegister dst, Address src) {
1489     Assembler::vinsertf64x4(dst, dst, src, 0);
1490   }
1491 
1492   // Carry-Less Multiplication Quadword
1493   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1494     // 0x00 - multiply lower 64 bits [0:63]
1495     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1496   }
1497   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1498     // 0x11 - multiply upper 64 bits [64:127]
1499     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1500   }









1501   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1502     // 0x00 - multiply lower 64 bits [0:63]
1503     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1504   }
1505   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1506     // 0x11 - multiply upper 64 bits [64:127]
1507     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1508   }
1509 
1510   // Data
1511 
1512   void cmov32( Condition cc, Register dst, Address  src);
1513   void cmov32( Condition cc, Register dst, Register src);
1514 
1515   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1516 
1517   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1518   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1519 
1520   void movoop(Register dst, jobject obj);
1521   void movoop(Address dst, jobject obj);
1522 
1523   void mov_metadata(Register dst, Metadata* obj);
1524   void mov_metadata(Address dst, Metadata* obj);
1525 
1526   void movptr(ArrayAddress dst, Register src);
1527   // can this do an lea?
1528   void movptr(Register dst, ArrayAddress src);
1529 
1530   void movptr(Register dst, Address src);
1531 
1532 #ifdef _LP64
1533   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1534 #else
1535   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1536 #endif
1537 
1538   void movptr(Register dst, intptr_t src);
1539   void movptr(Register dst, Register src);
1540   void movptr(Address dst, intptr_t src);
1541 
1542   void movptr(Address dst, Register src);
1543 
1544   void movptr(Register dst, RegisterOrConstant src) {
1545     if (src.is_constant()) movptr(dst, src.as_constant());
1546     else                   movptr(dst, src.as_register());
1547   }
1548 
1549 #ifdef _LP64
1550   // Generally the next two are only used for moving NULL
1551   // Although there are situations in initializing the mark word where
1552   // they could be used. They are dangerous.
1553 
1554   // They only exist on LP64 so that int32_t and intptr_t are not the same
1555   // and we have ambiguous declarations.
1556 
1557   void movptr(Address dst, int32_t imm32);
1558   void movptr(Register dst, int32_t imm32);
1559 #endif // _LP64
1560 
1561   // to avoid hiding movl
1562   void mov32(AddressLiteral dst, Register src);
1563   void mov32(Register dst, AddressLiteral src);
1564 
1565   // to avoid hiding movb
1566   void movbyte(ArrayAddress dst, int src);
1567 
1568   // Import other mov() methods from the parent class or else
1569   // they will be hidden by the following overriding declaration.
1570   using Assembler::movdl;
1571   using Assembler::movq;
1572   void movdl(XMMRegister dst, AddressLiteral src);
1573   void movq(XMMRegister dst, AddressLiteral src);
1574 
1575   // Can push value or effective address
1576   void pushptr(AddressLiteral src);
1577 
1578   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1579   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1580 
1581   void pushoop(jobject obj);
1582   void pushklass(Metadata* obj);
1583 
1584   // sign extend as need a l to ptr sized element
1585   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1586   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1587 
1588   // C2 compiled method's prolog code.
1589   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub);
1590 
1591   // clear memory of size 'cnt' qwords, starting at 'base';
1592   // if 'is_large' is set, do not try to produce short loop
1593   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1594 
1595   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1596   void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1597 
1598 #ifdef COMPILER2
1599   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1600                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1601 
1602   // IndexOf strings.
1603   // Small strings are loaded through stack if they cross page boundary.
1604   void string_indexof(Register str1, Register str2,
1605                       Register cnt1, Register cnt2,
1606                       int int_cnt2,  Register result,
1607                       XMMRegister vec, Register tmp,
1608                       int ae);
1609 
1610   // IndexOf for constant substrings with size >= 8 elements
1611   // which don't need to be loaded through stack.
1612   void string_indexofC8(Register str1, Register str2,
1613                       Register cnt1, Register cnt2,
1614                       int int_cnt2,  Register result,
1615                       XMMRegister vec, Register tmp,
1616                       int ae);
1617 
1618     // Smallest code: we don't need to load through stack,
1619     // check string tail.
1620 
1621   // helper function for string_compare
1622   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1623                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1624                           Address::ScaleFactor scale2, Register index, int ae);
1625   // Compare strings.
1626   void string_compare(Register str1, Register str2,
1627                       Register cnt1, Register cnt2, Register result,
1628                       XMMRegister vec1, int ae);
1629 
1630   // Search for Non-ASCII character (Negative byte value) in a byte array,
1631   // return true if it has any and false otherwise.
1632   void has_negatives(Register ary1, Register len,
1633                      Register result, Register tmp1,
1634                      XMMRegister vec1, XMMRegister vec2);
1635 
1636   // Compare char[] or byte[] arrays.
1637   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1638                      Register limit, Register result, Register chr,
1639                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1640 
1641 #endif
1642 
1643   // Fill primitive arrays
1644   void generate_fill(BasicType t, bool aligned,
1645                      Register to, Register value, Register count,
1646                      Register rtmp, XMMRegister xtmp);
1647 
1648   void encode_iso_array(Register src, Register dst, Register len,
1649                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1650                         XMMRegister tmp4, Register tmp5, Register result);
1651 
1652 #ifdef _LP64
1653   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1654   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1655                              Register y, Register y_idx, Register z,
1656                              Register carry, Register product,
1657                              Register idx, Register kdx);
1658   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1659                               Register yz_idx, Register idx,
1660                               Register carry, Register product, int offset);
1661   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1662                                     Register carry, Register carry2,
1663                                     Register idx, Register jdx,
1664                                     Register yz_idx1, Register yz_idx2,
1665                                     Register tmp, Register tmp3, Register tmp4);
1666   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1667                                Register yz_idx, Register idx, Register jdx,
1668                                Register carry, Register product,
1669                                Register carry2);
1670   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1671                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1672   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1673                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1674   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1675                             Register tmp2);
1676   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1677                        Register rdxReg, Register raxReg);
1678   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1679   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1680                        Register tmp3, Register tmp4);
1681   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1682                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1683 
1684   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1685                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1686                Register raxReg);
1687   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1688                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1689                Register raxReg);
1690   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1691                            Register result, Register tmp1, Register tmp2,
1692                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1693 #endif
1694 
1695   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1696   void update_byte_crc32(Register crc, Register val, Register table);
1697   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1698   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1699   // Note on a naming convention:
1700   // Prefix w = register only used on a Westmere+ architecture
1701   // Prefix n = register only used on a Nehalem architecture
1702 #ifdef _LP64
1703   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1704                        Register tmp1, Register tmp2, Register tmp3);
1705 #else
1706   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1707                        Register tmp1, Register tmp2, Register tmp3,
1708                        XMMRegister xtmp1, XMMRegister xtmp2);
1709 #endif
1710   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1711                         Register in_out,
1712                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1713                         XMMRegister w_xtmp2,
1714                         Register tmp1,
1715                         Register n_tmp2, Register n_tmp3);
1716   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1717                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1718                        Register tmp1, Register tmp2,
1719                        Register n_tmp3);
1720   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1721                          Register in_out1, Register in_out2, Register in_out3,
1722                          Register tmp1, Register tmp2, Register tmp3,
1723                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1724                          Register tmp4, Register tmp5,
1725                          Register n_tmp6);
1726   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1727                             Register tmp1, Register tmp2, Register tmp3,
1728                             Register tmp4, Register tmp5, Register tmp6,
1729                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1730                             bool is_pclmulqdq_supported);
1731   // Fold 128-bit data chunk
1732   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1733   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1734   // Fold 8-bit data
1735   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1736   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1737   void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1738 
1739   // Compress char[] array to byte[].
1740   void char_array_compress(Register src, Register dst, Register len,
1741                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1742                            XMMRegister tmp4, Register tmp5, Register result);
1743 
1744   // Inflate byte[] array to char[].
1745   void byte_array_inflate(Register src, Register dst, Register len,
1746                           XMMRegister tmp1, Register tmp2);
1747 
1748 };
1749 
1750 /**
1751  * class SkipIfEqual:
1752  *
1753  * Instantiating this class will result in assembly code being output that will
1754  * jump around any code emitted between the creation of the instance and it's
1755  * automatic destruction at the end of a scope block, depending on the value of
1756  * the flag passed to the constructor, which will be checked at run-time.
1757  */
1758 class SkipIfEqual {
1759  private:
1760   MacroAssembler* _masm;
1761   Label _label;
1762 
1763  public:
1764    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1765    ~SkipIfEqual();
1766 };
1767 
1768 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP
--- EOF ---