1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 tail_size = 1; // the imm8
948 break;
949 default:
950 break;
951 }
952 ip++; // skip opcode
953 debug_only(has_disp32 = true); // has both kinds of operands!
954 break;
955
956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
959 case 0xDD: // fld_d a; fst_d a; fstp_d a
960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
961 case 0xDF: // fild_d a; fistp_d a
962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
965 debug_only(has_disp32 = true);
966 break;
967
968 case 0xE8: // call rdisp32
969 case 0xE9: // jmp rdisp32
970 if (which == end_pc_operand) return ip + 4;
971 assert(which == call32_operand, "call has no disp32 or imm");
972 return ip;
973
974 case 0xF0: // Lock
975 goto again_after_prefix;
976
977 case 0xF3: // For SSE
978 case 0xF2: // For SSE2
979 switch (0xFF & *ip++) {
980 case REX:
981 case REX_B:
982 case REX_X:
983 case REX_XB:
984 case REX_R:
985 case REX_RB:
986 case REX_RX:
987 case REX_RXB:
988 case REX_W:
989 case REX_WB:
990 case REX_WX:
991 case REX_WXB:
992 case REX_WR:
993 case REX_WRB:
994 case REX_WRX:
995 case REX_WRXB:
996 NOT_LP64(assert(false, "found 64bit prefix"));
997 ip++;
998 default:
999 ip++;
1000 }
1001 debug_only(has_disp32 = true); // has both kinds of operands!
1002 break;
1003
1004 default:
1005 ShouldNotReachHere();
1006
1007 #undef REP8
1008 #undef REP16
1009 }
1010
1011 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1012 #ifdef _LP64
1013 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1014 #else
1015 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1016 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1017 #endif // LP64
1018 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1019
1020 // parse the output of emit_operand
1021 int op2 = 0xFF & *ip++;
1022 int base = op2 & 0x07;
1023 int op3 = -1;
1024 const int b100 = 4;
1025 const int b101 = 5;
1026 if (base == b100 && (op2 >> 6) != 3) {
1027 op3 = 0xFF & *ip++;
1028 base = op3 & 0x07; // refetch the base
1029 }
1030 // now ip points at the disp (if any)
1031
1032 switch (op2 >> 6) {
1033 case 0:
1034 // [00 reg 100][ss index base]
1035 // [00 reg 100][00 100 esp]
1036 // [00 reg base]
1037 // [00 reg 100][ss index 101][disp32]
1038 // [00 reg 101] [disp32]
1039
1040 if (base == b101) {
1041 if (which == disp32_operand)
1042 return ip; // caller wants the disp32
1043 ip += 4; // skip the disp32
1044 }
1045 break;
1046
1047 case 1:
1048 // [01 reg 100][ss index base][disp8]
1049 // [01 reg 100][00 100 esp][disp8]
1050 // [01 reg base] [disp8]
1051 ip += 1; // skip the disp8
1052 break;
1053
1054 case 2:
1055 // [10 reg 100][ss index base][disp32]
1056 // [10 reg 100][00 100 esp][disp32]
1057 // [10 reg base] [disp32]
1058 if (which == disp32_operand)
1059 return ip; // caller wants the disp32
1060 ip += 4; // skip the disp32
1061 break;
1062
1063 case 3:
1064 // [11 reg base] (not a memory addressing mode)
1065 break;
1066 }
1067
1068 if (which == end_pc_operand) {
1069 return ip + tail_size;
1070 }
1071
1072 #ifdef _LP64
1073 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1074 #else
1075 assert(which == imm_operand, "instruction has only an imm field");
1076 #endif // LP64
1077 return ip;
1078 }
1079
1080 address Assembler::locate_next_instruction(address inst) {
1081 // Secretly share code with locate_operand:
1082 return locate_operand(inst, end_pc_operand);
1083 }
1084
1085
1086 #ifdef ASSERT
1087 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1088 address inst = inst_mark();
1089 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1090 address opnd;
1091
1092 Relocation* r = rspec.reloc();
1093 if (r->type() == relocInfo::none) {
1094 return;
1095 } else if (r->is_call() || format == call32_operand) {
1096 // assert(format == imm32_operand, "cannot specify a nonzero format");
1097 opnd = locate_operand(inst, call32_operand);
1098 } else if (r->is_data()) {
1099 assert(format == imm_operand || format == disp32_operand
1100 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1101 opnd = locate_operand(inst, (WhichOperand)format);
1102 } else {
1103 assert(format == imm_operand, "cannot specify a format");
1104 return;
1105 }
1106 assert(opnd == pc(), "must put operand where relocs can find it");
1107 }
1108 #endif // ASSERT
1109
1110 void Assembler::emit_operand32(Register reg, Address adr) {
1111 assert(reg->encoding() < 8, "no extended registers");
1112 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 void Assembler::emit_operand(Register reg, Address adr,
1118 int rip_relative_correction) {
1119 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1120 adr._rspec,
1121 rip_relative_correction);
1122 }
1123
1124 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1125 if (adr.isxmmindex()) {
1126 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1127 } else {
1128 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1129 adr._rspec);
1130 }
1131 }
1132
1133 // MMX operations
1134 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1135 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1136 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1137 }
1138
1139 // work around gcc (3.2.1-7a) bug
1140 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1141 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1142 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1143 }
1144
1145
1146 void Assembler::emit_farith(int b1, int b2, int i) {
1147 assert(isByte(b1) && isByte(b2), "wrong opcode");
1148 assert(0 <= i && i < 8, "illegal stack offset");
1149 emit_int8(b1);
1150 emit_int8(b2 + i);
1151 }
1152
1153
1154 // Now the Assembler instructions (identical for 32/64 bits)
1155
1156 void Assembler::adcl(Address dst, int32_t imm32) {
1157 InstructionMark im(this);
1158 prefix(dst);
1159 emit_arith_operand(0x81, rdx, dst, imm32);
1160 }
1161
1162 void Assembler::adcl(Address dst, Register src) {
1163 InstructionMark im(this);
1164 prefix(dst, src);
1165 emit_int8(0x11);
1166 emit_operand(src, dst);
1167 }
1168
1169 void Assembler::adcl(Register dst, int32_t imm32) {
1170 prefix(dst);
1171 emit_arith(0x81, 0xD0, dst, imm32);
1172 }
1173
1174 void Assembler::adcl(Register dst, Address src) {
1175 InstructionMark im(this);
1176 prefix(src, dst);
1177 emit_int8(0x13);
1178 emit_operand(dst, src);
1179 }
1180
1181 void Assembler::adcl(Register dst, Register src) {
1182 (void) prefix_and_encode(dst->encoding(), src->encoding());
1183 emit_arith(0x13, 0xC0, dst, src);
1184 }
1185
1186 void Assembler::addl(Address dst, int32_t imm32) {
1187 InstructionMark im(this);
1188 prefix(dst);
1189 emit_arith_operand(0x81, rax, dst, imm32);
1190 }
1191
1192 void Assembler::addb(Address dst, int imm8) {
1193 InstructionMark im(this);
1194 prefix(dst);
1195 emit_int8((unsigned char)0x80);
1196 emit_operand(rax, dst, 1);
1197 emit_int8(imm8);
1198 }
1199
1200 void Assembler::addw(Address dst, int imm16) {
1201 InstructionMark im(this);
1202 emit_int8(0x66);
1203 prefix(dst);
1204 emit_int8((unsigned char)0x81);
1205 emit_operand(rax, dst, 2);
1206 emit_int16(imm16);
1207 }
1208
1209 void Assembler::addl(Address dst, Register src) {
1210 InstructionMark im(this);
1211 prefix(dst, src);
1212 emit_int8(0x01);
1213 emit_operand(src, dst);
1214 }
1215
1216 void Assembler::addl(Register dst, int32_t imm32) {
1217 prefix(dst);
1218 emit_arith(0x81, 0xC0, dst, imm32);
1219 }
1220
1221 void Assembler::addl(Register dst, Address src) {
1222 InstructionMark im(this);
1223 prefix(src, dst);
1224 emit_int8(0x03);
1225 emit_operand(dst, src);
1226 }
1227
1228 void Assembler::addl(Register dst, Register src) {
1229 (void) prefix_and_encode(dst->encoding(), src->encoding());
1230 emit_arith(0x03, 0xC0, dst, src);
1231 }
1232
1233 void Assembler::addr_nop_4() {
1234 assert(UseAddressNop, "no CPU support");
1235 // 4 bytes: NOP DWORD PTR [EAX+0]
1236 emit_int8(0x0F);
1237 emit_int8(0x1F);
1238 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1239 emit_int8(0); // 8-bits offset (1 byte)
1240 }
1241
1242 void Assembler::addr_nop_5() {
1243 assert(UseAddressNop, "no CPU support");
1244 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1245 emit_int8(0x0F);
1246 emit_int8(0x1F);
1247 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1248 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1249 emit_int8(0); // 8-bits offset (1 byte)
1250 }
1251
1252 void Assembler::addr_nop_7() {
1253 assert(UseAddressNop, "no CPU support");
1254 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1255 emit_int8(0x0F);
1256 emit_int8(0x1F);
1257 emit_int8((unsigned char)0x80);
1258 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1259 emit_int32(0); // 32-bits offset (4 bytes)
1260 }
1261
1262 void Assembler::addr_nop_8() {
1263 assert(UseAddressNop, "no CPU support");
1264 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1265 emit_int8(0x0F);
1266 emit_int8(0x1F);
1267 emit_int8((unsigned char)0x84);
1268 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1269 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1270 emit_int32(0); // 32-bits offset (4 bytes)
1271 }
1272
1273 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1274 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1275 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1276 attributes.set_rex_vex_w_reverted();
1277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1278 emit_int8(0x58);
1279 emit_int8((unsigned char)(0xC0 | encode));
1280 }
1281
1282 void Assembler::addsd(XMMRegister dst, Address src) {
1283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1284 InstructionMark im(this);
1285 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1286 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1287 attributes.set_rex_vex_w_reverted();
1288 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1289 emit_int8(0x58);
1290 emit_operand(dst, src);
1291 }
1292
1293 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1294 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1297 emit_int8(0x58);
1298 emit_int8((unsigned char)(0xC0 | encode));
1299 }
1300
1301 void Assembler::addss(XMMRegister dst, Address src) {
1302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1303 InstructionMark im(this);
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1306 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1307 emit_int8(0x58);
1308 emit_operand(dst, src);
1309 }
1310
1311 void Assembler::aesdec(XMMRegister dst, Address src) {
1312 assert(VM_Version::supports_aes(), "");
1313 InstructionMark im(this);
1314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1315 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1316 emit_int8((unsigned char)0xDE);
1317 emit_operand(dst, src);
1318 }
1319
1320 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1324 emit_int8((unsigned char)0xDE);
1325 emit_int8(0xC0 | encode);
1326 }
1327
1328 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1329 assert(VM_Version::supports_vaes(), "");
1330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1331 attributes.set_is_evex_instruction();
1332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1333 emit_int8((unsigned char)0xDE);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1336
1337
1338 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionMark im(this);
1341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1342 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1343 emit_int8((unsigned char)0xDF);
1344 emit_operand(dst, src);
1345 }
1346
1347 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1348 assert(VM_Version::supports_aes(), "");
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDF);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1356 assert(VM_Version::supports_vaes(), "");
1357 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1358 attributes.set_is_evex_instruction();
1359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1360 emit_int8((unsigned char)0xDF);
1361 emit_int8((unsigned char)(0xC0 | encode));
1362 }
1363
1364 void Assembler::aesenc(XMMRegister dst, Address src) {
1365 assert(VM_Version::supports_aes(), "");
1366 InstructionMark im(this);
1367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1368 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1369 emit_int8((unsigned char)0xDC);
1370 emit_operand(dst, src);
1371 }
1372
1373 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1374 assert(VM_Version::supports_aes(), "");
1375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377 emit_int8((unsigned char)0xDC);
1378 emit_int8(0xC0 | encode);
1379 }
1380
1381 void Assembler::aesenclast(XMMRegister dst, Address src) {
1382 assert(VM_Version::supports_aes(), "");
1383 InstructionMark im(this);
1384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1385 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1386 emit_int8((unsigned char)0xDD);
1387 emit_operand(dst, src);
1388 }
1389
1390 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1391 assert(VM_Version::supports_aes(), "");
1392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1393 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1394 emit_int8((unsigned char)0xDD);
1395 emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397
1398 void Assembler::andl(Address dst, int32_t imm32) {
1399 InstructionMark im(this);
1400 prefix(dst);
1401 emit_int8((unsigned char)0x81);
1402 emit_operand(rsp, dst, 4);
1403 emit_int32(imm32);
1404 }
1405
1406 void Assembler::andl(Register dst, int32_t imm32) {
1407 prefix(dst);
1408 emit_arith(0x81, 0xE0, dst, imm32);
1409 }
1410
1411 void Assembler::andl(Register dst, Address src) {
1412 InstructionMark im(this);
1413 prefix(src, dst);
1414 emit_int8(0x23);
1415 emit_operand(dst, src);
1416 }
1417
1418 void Assembler::andl(Register dst, Register src) {
1419 (void) prefix_and_encode(dst->encoding(), src->encoding());
1420 emit_arith(0x23, 0xC0, dst, src);
1421 }
1422
1423 void Assembler::andnl(Register dst, Register src1, Register src2) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF2);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::andnl(Register dst, Register src1, Address src2) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1435 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF2);
1437 emit_operand(dst, src2);
1438 }
1439
1440 void Assembler::bsfl(Register dst, Register src) {
1441 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1442 emit_int8(0x0F);
1443 emit_int8((unsigned char)0xBC);
1444 emit_int8((unsigned char)(0xC0 | encode));
1445 }
1446
1447 void Assembler::bsrl(Register dst, Register src) {
1448 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1449 emit_int8(0x0F);
1450 emit_int8((unsigned char)0xBD);
1451 emit_int8((unsigned char)(0xC0 | encode));
1452 }
1453
1454 void Assembler::bswapl(Register reg) { // bswap
1455 int encode = prefix_and_encode(reg->encoding());
1456 emit_int8(0x0F);
1457 emit_int8((unsigned char)(0xC8 | encode));
1458 }
1459
1460 void Assembler::blsil(Register dst, Register src) {
1461 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1462 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1463 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1464 emit_int8((unsigned char)0xF3);
1465 emit_int8((unsigned char)(0xC0 | encode));
1466 }
1467
1468 void Assembler::blsil(Register dst, Address src) {
1469 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1470 InstructionMark im(this);
1471 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1472 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1473 emit_int8((unsigned char)0xF3);
1474 emit_operand(rbx, src);
1475 }
1476
1477 void Assembler::blsmskl(Register dst, Register src) {
1478 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1479 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1480 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1481 emit_int8((unsigned char)0xF3);
1482 emit_int8((unsigned char)(0xC0 | encode));
1483 }
1484
1485 void Assembler::blsmskl(Register dst, Address src) {
1486 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1487 InstructionMark im(this);
1488 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1489 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1490 emit_int8((unsigned char)0xF3);
1491 emit_operand(rdx, src);
1492 }
1493
1494 void Assembler::blsrl(Register dst, Register src) {
1495 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1496 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1497 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1498 emit_int8((unsigned char)0xF3);
1499 emit_int8((unsigned char)(0xC0 | encode));
1500 }
1501
1502 void Assembler::blsrl(Register dst, Address src) {
1503 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1504 InstructionMark im(this);
1505 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1506 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1507 emit_int8((unsigned char)0xF3);
1508 emit_operand(rcx, src);
1509 }
1510
1511 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1512 // suspect disp32 is always good
1513 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1514
1515 if (L.is_bound()) {
1516 const int long_size = 5;
1517 int offs = (int)( target(L) - pc() );
1518 assert(offs <= 0, "assembler error");
1519 InstructionMark im(this);
1520 // 1110 1000 #32-bit disp
1521 emit_int8((unsigned char)0xE8);
1522 emit_data(offs - long_size, rtype, operand);
1523 } else {
1524 InstructionMark im(this);
1525 // 1110 1000 #32-bit disp
1526 L.add_patch_at(code(), locator());
1527
1528 emit_int8((unsigned char)0xE8);
1529 emit_data(int(0), rtype, operand);
1530 }
1531 }
1532
1533 void Assembler::call(Register dst) {
1534 int encode = prefix_and_encode(dst->encoding());
1535 emit_int8((unsigned char)0xFF);
1536 emit_int8((unsigned char)(0xD0 | encode));
1537 }
1538
1539
1540 void Assembler::call(Address adr) {
1541 InstructionMark im(this);
1542 prefix(adr);
1543 emit_int8((unsigned char)0xFF);
1544 emit_operand(rdx, adr);
1545 }
1546
1547 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1548 InstructionMark im(this);
1549 emit_int8((unsigned char)0xE8);
1550 intptr_t disp = entry - (pc() + sizeof(int32_t));
1551 // Entry is NULL in case of a scratch emit.
1552 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1553 // Technically, should use call32_operand, but this format is
1554 // implied by the fact that we're emitting a call instruction.
1555
1556 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1557 emit_data((int) disp, rspec, operand);
1558 }
1559
1560 void Assembler::cdql() {
1561 emit_int8((unsigned char)0x99);
1562 }
1563
1564 void Assembler::cld() {
1565 emit_int8((unsigned char)0xFC);
1566 }
1567
1568 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1569 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1570 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1571 emit_int8(0x0F);
1572 emit_int8(0x40 | cc);
1573 emit_int8((unsigned char)(0xC0 | encode));
1574 }
1575
1576
1577 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1578 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1579 prefix(src, dst);
1580 emit_int8(0x0F);
1581 emit_int8(0x40 | cc);
1582 emit_operand(dst, src);
1583 }
1584
1585 void Assembler::cmpb(Address dst, int imm8) {
1586 InstructionMark im(this);
1587 prefix(dst);
1588 emit_int8((unsigned char)0x80);
1589 emit_operand(rdi, dst, 1);
1590 emit_int8(imm8);
1591 }
1592
1593 void Assembler::cmpl(Address dst, int32_t imm32) {
1594 InstructionMark im(this);
1595 prefix(dst);
1596 emit_int8((unsigned char)0x81);
1597 emit_operand(rdi, dst, 4);
1598 emit_int32(imm32);
1599 }
1600
1601 void Assembler::cmpl(Register dst, int32_t imm32) {
1602 prefix(dst);
1603 emit_arith(0x81, 0xF8, dst, imm32);
1604 }
1605
1606 void Assembler::cmpl(Register dst, Register src) {
1607 (void) prefix_and_encode(dst->encoding(), src->encoding());
1608 emit_arith(0x3B, 0xC0, dst, src);
1609 }
1610
1611 void Assembler::cmpl(Register dst, Address src) {
1612 InstructionMark im(this);
1613 prefix(src, dst);
1614 emit_int8((unsigned char)0x3B);
1615 emit_operand(dst, src);
1616 }
1617
1618 void Assembler::cmpw(Address dst, int imm16) {
1619 InstructionMark im(this);
1620 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1621 emit_int8(0x66);
1622 emit_int8((unsigned char)0x81);
1623 emit_operand(rdi, dst, 2);
1624 emit_int16(imm16);
1625 }
1626
1627 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1628 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1629 // The ZF is set if the compared values were equal, and cleared otherwise.
1630 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1631 InstructionMark im(this);
1632 prefix(adr, reg);
1633 emit_int8(0x0F);
1634 emit_int8((unsigned char)0xB1);
1635 emit_operand(reg, adr);
1636 }
1637
1638 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1639 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1640 // The ZF is set if the compared values were equal, and cleared otherwise.
1641 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1642 InstructionMark im(this);
1643 prefix(adr, reg, true);
1644 emit_int8(0x0F);
1645 emit_int8((unsigned char)0xB0);
1646 emit_operand(reg, adr);
1647 }
1648
1649 void Assembler::comisd(XMMRegister dst, Address src) {
1650 // NOTE: dbx seems to decode this as comiss even though the
1651 // 0x66 is there. Strangly ucomisd comes out correct
1652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1653 InstructionMark im(this);
1654 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1655 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1656 attributes.set_rex_vex_w_reverted();
1657 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1658 emit_int8(0x2F);
1659 emit_operand(dst, src);
1660 }
1661
1662 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1664 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1665 attributes.set_rex_vex_w_reverted();
1666 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1667 emit_int8(0x2F);
1668 emit_int8((unsigned char)(0xC0 | encode));
1669 }
1670
1671 void Assembler::comiss(XMMRegister dst, Address src) {
1672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1673 InstructionMark im(this);
1674 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1675 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1676 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1677 emit_int8(0x2F);
1678 emit_operand(dst, src);
1679 }
1680
1681 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1682 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1684 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1685 emit_int8(0x2F);
1686 emit_int8((unsigned char)(0xC0 | encode));
1687 }
1688
1689 void Assembler::cpuid() {
1690 emit_int8(0x0F);
1691 emit_int8((unsigned char)0xA2);
1692 }
1693
1694 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1695 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1696 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1697 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1698 //
1699 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1700 //
1701 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1702 //
1703 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1704 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1705 assert(VM_Version::supports_sse4_2(), "");
1706 int8_t w = 0x01;
1707 Prefix p = Prefix_EMPTY;
1708
1709 emit_int8((int8_t)0xF2);
1710 switch (sizeInBytes) {
1711 case 1:
1712 w = 0;
1713 break;
1714 case 2:
1715 case 4:
1716 break;
1717 LP64_ONLY(case 8:)
1718 // This instruction is not valid in 32 bits
1719 // Note:
1720 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1721 //
1722 // Page B - 72 Vol. 2C says
1723 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1724 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1725 // F0!!!
1726 // while 3 - 208 Vol. 2A
1727 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1728 //
1729 // the 0 on a last bit is reserved for a different flavor of this instruction :
1730 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1731 p = REX_W;
1732 break;
1733 default:
1734 assert(0, "Unsupported value for a sizeInBytes argument");
1735 break;
1736 }
1737 LP64_ONLY(prefix(crc, v, p);)
1738 emit_int8((int8_t)0x0F);
1739 emit_int8(0x38);
1740 emit_int8((int8_t)(0xF0 | w));
1741 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1742 }
1743
1744 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1745 assert(VM_Version::supports_sse4_2(), "");
1746 InstructionMark im(this);
1747 int8_t w = 0x01;
1748 Prefix p = Prefix_EMPTY;
1749
1750 emit_int8((int8_t)0xF2);
1751 switch (sizeInBytes) {
1752 case 1:
1753 w = 0;
1754 break;
1755 case 2:
1756 case 4:
1757 break;
1758 LP64_ONLY(case 8:)
1759 // This instruction is not valid in 32 bits
1760 p = REX_W;
1761 break;
1762 default:
1763 assert(0, "Unsupported value for a sizeInBytes argument");
1764 break;
1765 }
1766 LP64_ONLY(prefix(crc, adr, p);)
1767 emit_int8((int8_t)0x0F);
1768 emit_int8(0x38);
1769 emit_int8((int8_t)(0xF0 | w));
1770 emit_operand(crc, adr);
1771 }
1772
1773 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1776 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1777 emit_int8((unsigned char)0xE6);
1778 emit_int8((unsigned char)(0xC0 | encode));
1779 }
1780
1781 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1783 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1784 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1785 emit_int8(0x5B);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 }
1788
1789 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1791 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1792 attributes.set_rex_vex_w_reverted();
1793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1794 emit_int8(0x5A);
1795 emit_int8((unsigned char)(0xC0 | encode));
1796 }
1797
1798 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1799 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1800 InstructionMark im(this);
1801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1803 attributes.set_rex_vex_w_reverted();
1804 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_operand(dst, src);
1807 }
1808
1809 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1813 emit_int8(0x2A);
1814 emit_int8((unsigned char)(0xC0 | encode));
1815 }
1816
1817 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1819 InstructionMark im(this);
1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1822 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x2A);
1824 emit_operand(dst, src);
1825 }
1826
1827 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1828 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1830 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1831 emit_int8(0x2A);
1832 emit_int8((unsigned char)(0xC0 | encode));
1833 }
1834
1835 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1840 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x2A);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x2A);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1857 emit_int8(0x5A);
1858 emit_int8((unsigned char)(0xC0 | encode));
1859 }
1860
1861 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1863 InstructionMark im(this);
1864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1866 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1867 emit_int8(0x5A);
1868 emit_operand(dst, src);
1869 }
1870
1871
1872 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1875 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1876 emit_int8(0x2C);
1877 emit_int8((unsigned char)(0xC0 | encode));
1878 }
1879
1880 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1881 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1883 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1884 emit_int8(0x2C);
1885 emit_int8((unsigned char)(0xC0 | encode));
1886 }
1887
1888 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1889 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1890 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1891 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1892 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1893 emit_int8((unsigned char)0xE6);
1894 emit_int8((unsigned char)(0xC0 | encode));
1895 }
1896
1897 void Assembler::decl(Address dst) {
1898 // Don't use it directly. Use MacroAssembler::decrement() instead.
1899 InstructionMark im(this);
1900 prefix(dst);
1901 emit_int8((unsigned char)0xFF);
1902 emit_operand(rcx, dst);
1903 }
1904
1905 void Assembler::divsd(XMMRegister dst, Address src) {
1906 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1907 InstructionMark im(this);
1908 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1909 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1910 attributes.set_rex_vex_w_reverted();
1911 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1912 emit_int8(0x5E);
1913 emit_operand(dst, src);
1914 }
1915
1916 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1917 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1918 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1919 attributes.set_rex_vex_w_reverted();
1920 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1921 emit_int8(0x5E);
1922 emit_int8((unsigned char)(0xC0 | encode));
1923 }
1924
1925 void Assembler::divss(XMMRegister dst, Address src) {
1926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1927 InstructionMark im(this);
1928 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1929 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1930 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1931 emit_int8(0x5E);
1932 emit_operand(dst, src);
1933 }
1934
1935 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1936 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1937 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1939 emit_int8(0x5E);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943 void Assembler::emms() {
1944 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1945 emit_int8(0x0F);
1946 emit_int8(0x77);
1947 }
1948
1949 void Assembler::hlt() {
1950 emit_int8((unsigned char)0xF4);
1951 }
1952
1953 void Assembler::idivl(Register src) {
1954 int encode = prefix_and_encode(src->encoding());
1955 emit_int8((unsigned char)0xF7);
1956 emit_int8((unsigned char)(0xF8 | encode));
1957 }
1958
1959 void Assembler::divl(Register src) { // Unsigned
1960 int encode = prefix_and_encode(src->encoding());
1961 emit_int8((unsigned char)0xF7);
1962 emit_int8((unsigned char)(0xF0 | encode));
1963 }
1964
1965 void Assembler::imull(Register src) {
1966 int encode = prefix_and_encode(src->encoding());
1967 emit_int8((unsigned char)0xF7);
1968 emit_int8((unsigned char)(0xE8 | encode));
1969 }
1970
1971 void Assembler::imull(Register dst, Register src) {
1972 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1973 emit_int8(0x0F);
1974 emit_int8((unsigned char)0xAF);
1975 emit_int8((unsigned char)(0xC0 | encode));
1976 }
1977
1978
1979 void Assembler::imull(Register dst, Register src, int value) {
1980 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1981 if (is8bit(value)) {
1982 emit_int8(0x6B);
1983 emit_int8((unsigned char)(0xC0 | encode));
1984 emit_int8(value & 0xFF);
1985 } else {
1986 emit_int8(0x69);
1987 emit_int8((unsigned char)(0xC0 | encode));
1988 emit_int32(value);
1989 }
1990 }
1991
1992 void Assembler::imull(Register dst, Address src) {
1993 InstructionMark im(this);
1994 prefix(src, dst);
1995 emit_int8(0x0F);
1996 emit_int8((unsigned char) 0xAF);
1997 emit_operand(dst, src);
1998 }
1999
2000
2001 void Assembler::incl(Address dst) {
2002 // Don't use it directly. Use MacroAssembler::increment() instead.
2003 InstructionMark im(this);
2004 prefix(dst);
2005 emit_int8((unsigned char)0xFF);
2006 emit_operand(rax, dst);
2007 }
2008
2009 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2010 InstructionMark im(this);
2011 assert((0 <= cc) && (cc < 16), "illegal cc");
2012 if (L.is_bound()) {
2013 address dst = target(L);
2014 assert(dst != NULL, "jcc most probably wrong");
2015
2016 const int short_size = 2;
2017 const int long_size = 6;
2018 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2019 if (maybe_short && is8bit(offs - short_size)) {
2020 // 0111 tttn #8-bit disp
2021 emit_int8(0x70 | cc);
2022 emit_int8((offs - short_size) & 0xFF);
2023 } else {
2024 // 0000 1111 1000 tttn #32-bit disp
2025 assert(is_simm32(offs - long_size),
2026 "must be 32bit offset (call4)");
2027 emit_int8(0x0F);
2028 emit_int8((unsigned char)(0x80 | cc));
2029 emit_int32(offs - long_size);
2030 }
2031 } else {
2032 // Note: could eliminate cond. jumps to this jump if condition
2033 // is the same however, seems to be rather unlikely case.
2034 // Note: use jccb() if label to be bound is very close to get
2035 // an 8-bit displacement
2036 L.add_patch_at(code(), locator());
2037 emit_int8(0x0F);
2038 emit_int8((unsigned char)(0x80 | cc));
2039 emit_int32(0);
2040 }
2041 }
2042
2043 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2044 if (L.is_bound()) {
2045 const int short_size = 2;
2046 address entry = target(L);
2047 #ifdef ASSERT
2048 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2049 intptr_t delta = short_branch_delta();
2050 if (delta != 0) {
2051 dist += (dist < 0 ? (-delta) :delta);
2052 }
2053 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2054 #endif
2055 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2056 // 0111 tttn #8-bit disp
2057 emit_int8(0x70 | cc);
2058 emit_int8((offs - short_size) & 0xFF);
2059 } else {
2060 InstructionMark im(this);
2061 L.add_patch_at(code(), locator(), file, line);
2062 emit_int8(0x70 | cc);
2063 emit_int8(0);
2064 }
2065 }
2066
2067 void Assembler::jmp(Address adr) {
2068 InstructionMark im(this);
2069 prefix(adr);
2070 emit_int8((unsigned char)0xFF);
2071 emit_operand(rsp, adr);
2072 }
2073
2074 void Assembler::jmp(Label& L, bool maybe_short) {
2075 if (L.is_bound()) {
2076 address entry = target(L);
2077 assert(entry != NULL, "jmp most probably wrong");
2078 InstructionMark im(this);
2079 const int short_size = 2;
2080 const int long_size = 5;
2081 intptr_t offs = entry - pc();
2082 if (maybe_short && is8bit(offs - short_size)) {
2083 emit_int8((unsigned char)0xEB);
2084 emit_int8((offs - short_size) & 0xFF);
2085 } else {
2086 emit_int8((unsigned char)0xE9);
2087 emit_int32(offs - long_size);
2088 }
2089 } else {
2090 // By default, forward jumps are always 32-bit displacements, since
2091 // we can't yet know where the label will be bound. If you're sure that
2092 // the forward jump will not run beyond 256 bytes, use jmpb to
2093 // force an 8-bit displacement.
2094 InstructionMark im(this);
2095 L.add_patch_at(code(), locator());
2096 emit_int8((unsigned char)0xE9);
2097 emit_int32(0);
2098 }
2099 }
2100
2101 void Assembler::jmp(Register entry) {
2102 int encode = prefix_and_encode(entry->encoding());
2103 emit_int8((unsigned char)0xFF);
2104 emit_int8((unsigned char)(0xE0 | encode));
2105 }
2106
2107 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2108 InstructionMark im(this);
2109 emit_int8((unsigned char)0xE9);
2110 assert(dest != NULL, "must have a target");
2111 intptr_t disp = dest - (pc() + sizeof(int32_t));
2112 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2113 emit_data(disp, rspec.reloc(), call32_operand);
2114 }
2115
2116 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2117 if (L.is_bound()) {
2118 const int short_size = 2;
2119 address entry = target(L);
2120 assert(entry != NULL, "jmp most probably wrong");
2121 #ifdef ASSERT
2122 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2123 intptr_t delta = short_branch_delta();
2124 if (delta != 0) {
2125 dist += (dist < 0 ? (-delta) :delta);
2126 }
2127 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2128 #endif
2129 intptr_t offs = entry - pc();
2130 emit_int8((unsigned char)0xEB);
2131 emit_int8((offs - short_size) & 0xFF);
2132 } else {
2133 InstructionMark im(this);
2134 L.add_patch_at(code(), locator(), file, line);
2135 emit_int8((unsigned char)0xEB);
2136 emit_int8(0);
2137 }
2138 }
2139
2140 void Assembler::ldmxcsr( Address src) {
2141 if (UseAVX > 0 ) {
2142 InstructionMark im(this);
2143 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2144 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2145 emit_int8((unsigned char)0xAE);
2146 emit_operand(as_Register(2), src);
2147 } else {
2148 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2149 InstructionMark im(this);
2150 prefix(src);
2151 emit_int8(0x0F);
2152 emit_int8((unsigned char)0xAE);
2153 emit_operand(as_Register(2), src);
2154 }
2155 }
2156
2157 void Assembler::leal(Register dst, Address src) {
2158 InstructionMark im(this);
2159 #ifdef _LP64
2160 emit_int8(0x67); // addr32
2161 prefix(src, dst);
2162 #endif // LP64
2163 emit_int8((unsigned char)0x8D);
2164 emit_operand(dst, src);
2165 }
2166
2167 void Assembler::lfence() {
2168 emit_int8(0x0F);
2169 emit_int8((unsigned char)0xAE);
2170 emit_int8((unsigned char)0xE8);
2171 }
2172
2173 void Assembler::lock() {
2174 emit_int8((unsigned char)0xF0);
2175 }
2176
2177 void Assembler::lzcntl(Register dst, Register src) {
2178 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2179 emit_int8((unsigned char)0xF3);
2180 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2181 emit_int8(0x0F);
2182 emit_int8((unsigned char)0xBD);
2183 emit_int8((unsigned char)(0xC0 | encode));
2184 }
2185
2186 // Emit mfence instruction
2187 void Assembler::mfence() {
2188 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2189 emit_int8(0x0F);
2190 emit_int8((unsigned char)0xAE);
2191 emit_int8((unsigned char)0xF0);
2192 }
2193
2194 void Assembler::mov(Register dst, Register src) {
2195 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2196 }
2197
2198 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2200 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2201 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2202 attributes.set_rex_vex_w_reverted();
2203 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2204 emit_int8(0x28);
2205 emit_int8((unsigned char)(0xC0 | encode));
2206 }
2207
2208 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2209 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2210 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2211 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2212 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2213 emit_int8(0x28);
2214 emit_int8((unsigned char)(0xC0 | encode));
2215 }
2216
2217 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2218 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2219 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2220 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2221 emit_int8(0x16);
2222 emit_int8((unsigned char)(0xC0 | encode));
2223 }
2224
2225 void Assembler::movb(Register dst, Address src) {
2226 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2227 InstructionMark im(this);
2228 prefix(src, dst, true);
2229 emit_int8((unsigned char)0x8A);
2230 emit_operand(dst, src);
2231 }
2232
2233 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2234 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2235 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2236 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2237 attributes.set_rex_vex_w_reverted();
2238 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2239 emit_int8(0x12);
2240 emit_int8(0xC0 | encode);
2241 }
2242
2243 void Assembler::kmovbl(KRegister dst, Register src) {
2244 assert(VM_Version::supports_avx512dq(), "");
2245 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2246 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2247 emit_int8((unsigned char)0x92);
2248 emit_int8((unsigned char)(0xC0 | encode));
2249 }
2250
2251 void Assembler::kmovbl(Register dst, KRegister src) {
2252 assert(VM_Version::supports_avx512dq(), "");
2253 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2254 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2255 emit_int8((unsigned char)0x93);
2256 emit_int8((unsigned char)(0xC0 | encode));
2257 }
2258
2259 void Assembler::kmovwl(KRegister dst, Register src) {
2260 assert(VM_Version::supports_evex(), "");
2261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2262 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2263 emit_int8((unsigned char)0x92);
2264 emit_int8((unsigned char)(0xC0 | encode));
2265 }
2266
2267 void Assembler::kmovwl(Register dst, KRegister src) {
2268 assert(VM_Version::supports_evex(), "");
2269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2270 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2271 emit_int8((unsigned char)0x93);
2272 emit_int8((unsigned char)(0xC0 | encode));
2273 }
2274
2275 void Assembler::kmovwl(KRegister dst, Address src) {
2276 assert(VM_Version::supports_evex(), "");
2277 InstructionMark im(this);
2278 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2279 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2280 emit_int8((unsigned char)0x90);
2281 emit_operand((Register)dst, src);
2282 }
2283
2284 void Assembler::kmovdl(KRegister dst, Register src) {
2285 assert(VM_Version::supports_avx512bw(), "");
2286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2287 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2288 emit_int8((unsigned char)0x92);
2289 emit_int8((unsigned char)(0xC0 | encode));
2290 }
2291
2292 void Assembler::kmovdl(Register dst, KRegister src) {
2293 assert(VM_Version::supports_avx512bw(), "");
2294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2295 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2296 emit_int8((unsigned char)0x93);
2297 emit_int8((unsigned char)(0xC0 | encode));
2298 }
2299
2300 void Assembler::kmovql(KRegister dst, KRegister src) {
2301 assert(VM_Version::supports_avx512bw(), "");
2302 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x90);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 void Assembler::kmovql(KRegister dst, Address src) {
2309 assert(VM_Version::supports_avx512bw(), "");
2310 InstructionMark im(this);
2311 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2312 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2313 emit_int8((unsigned char)0x90);
2314 emit_operand((Register)dst, src);
2315 }
2316
2317 void Assembler::kmovql(Address dst, KRegister src) {
2318 assert(VM_Version::supports_avx512bw(), "");
2319 InstructionMark im(this);
2320 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2321 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2322 emit_int8((unsigned char)0x90);
2323 emit_operand((Register)src, dst);
2324 }
2325
2326 void Assembler::kmovql(KRegister dst, Register src) {
2327 assert(VM_Version::supports_avx512bw(), "");
2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2329 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2330 emit_int8((unsigned char)0x92);
2331 emit_int8((unsigned char)(0xC0 | encode));
2332 }
2333
2334 void Assembler::kmovql(Register dst, KRegister src) {
2335 assert(VM_Version::supports_avx512bw(), "");
2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2337 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2338 emit_int8((unsigned char)0x93);
2339 emit_int8((unsigned char)(0xC0 | encode));
2340 }
2341
2342 void Assembler::knotwl(KRegister dst, KRegister src) {
2343 assert(VM_Version::supports_evex(), "");
2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2345 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2346 emit_int8((unsigned char)0x44);
2347 emit_int8((unsigned char)(0xC0 | encode));
2348 }
2349
2350 // This instruction produces ZF or CF flags
2351 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2352 assert(VM_Version::supports_avx512dq(), "");
2353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2354 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2355 emit_int8((unsigned char)0x98);
2356 emit_int8((unsigned char)(0xC0 | encode));
2357 }
2358
2359 // This instruction produces ZF or CF flags
2360 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2361 assert(VM_Version::supports_evex(), "");
2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2364 emit_int8((unsigned char)0x98);
2365 emit_int8((unsigned char)(0xC0 | encode));
2366 }
2367
2368 // This instruction produces ZF or CF flags
2369 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2370 assert(VM_Version::supports_avx512bw(), "");
2371 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2372 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2373 emit_int8((unsigned char)0x98);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 }
2376
2377 // This instruction produces ZF or CF flags
2378 void Assembler::kortestql(KRegister src1, KRegister src2) {
2379 assert(VM_Version::supports_avx512bw(), "");
2380 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2381 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2382 emit_int8((unsigned char)0x98);
2383 emit_int8((unsigned char)(0xC0 | encode));
2384 }
2385
2386 // This instruction produces ZF or CF flags
2387 void Assembler::ktestql(KRegister src1, KRegister src2) {
2388 assert(VM_Version::supports_avx512bw(), "");
2389 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2390 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2391 emit_int8((unsigned char)0x99);
2392 emit_int8((unsigned char)(0xC0 | encode));
2393 }
2394
2395 void Assembler::ktestq(KRegister src1, KRegister src2) {
2396 assert(VM_Version::supports_avx512bw(), "");
2397 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2398 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2399 emit_int8((unsigned char)0x99);
2400 emit_int8((unsigned char)(0xC0 | encode));
2401 }
2402
2403 void Assembler::ktestd(KRegister src1, KRegister src2) {
2404 assert(VM_Version::supports_avx512bw(), "");
2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2406 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2407 emit_int8((unsigned char)0x99);
2408 emit_int8((unsigned char)(0xC0 | encode));
2409 }
2410
2411 void Assembler::movb(Address dst, int imm8) {
2412 InstructionMark im(this);
2413 prefix(dst);
2414 emit_int8((unsigned char)0xC6);
2415 emit_operand(rax, dst, 1);
2416 emit_int8(imm8);
2417 }
2418
2419
2420 void Assembler::movb(Address dst, Register src) {
2421 assert(src->has_byte_register(), "must have byte register");
2422 InstructionMark im(this);
2423 prefix(dst, src, true);
2424 emit_int8((unsigned char)0x88);
2425 emit_operand(src, dst);
2426 }
2427
2428 void Assembler::movdl(XMMRegister dst, Register src) {
2429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2430 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2431 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2432 emit_int8(0x6E);
2433 emit_int8((unsigned char)(0xC0 | encode));
2434 }
2435
2436 void Assembler::movdl(Register dst, XMMRegister src) {
2437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2438 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2439 // swap src/dst to get correct prefix
2440 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2441 emit_int8(0x7E);
2442 emit_int8((unsigned char)(0xC0 | encode));
2443 }
2444
2445 void Assembler::movdl(XMMRegister dst, Address src) {
2446 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2447 InstructionMark im(this);
2448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2450 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x6E);
2452 emit_operand(dst, src);
2453 }
2454
2455 void Assembler::movdl(Address dst, XMMRegister src) {
2456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2457 InstructionMark im(this);
2458 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2459 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2460 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2461 emit_int8(0x7E);
2462 emit_operand(src, dst);
2463 }
2464
2465 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2467 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2468 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2469 emit_int8(0x6F);
2470 emit_int8((unsigned char)(0xC0 | encode));
2471 }
2472
2473 void Assembler::movdqa(XMMRegister dst, Address src) {
2474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2475 InstructionMark im(this);
2476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2477 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2478 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2479 emit_int8(0x6F);
2480 emit_operand(dst, src);
2481 }
2482
2483 void Assembler::movdqu(XMMRegister dst, Address src) {
2484 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2485 InstructionMark im(this);
2486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2488 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2489 emit_int8(0x6F);
2490 emit_operand(dst, src);
2491 }
2492
2493 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2496 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2497 emit_int8(0x6F);
2498 emit_int8((unsigned char)(0xC0 | encode));
2499 }
2500
2501 void Assembler::movdqu(Address dst, XMMRegister src) {
2502 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2503 InstructionMark im(this);
2504 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2505 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2506 attributes.reset_is_clear_context();
2507 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2508 emit_int8(0x7F);
2509 emit_operand(src, dst);
2510 }
2511
2512 // Move Unaligned 256bit Vector
2513 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2514 assert(UseAVX > 0, "");
2515 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2516 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2517 emit_int8(0x6F);
2518 emit_int8((unsigned char)(0xC0 | encode));
2519 }
2520
2521 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2522 assert(UseAVX > 0, "");
2523 InstructionMark im(this);
2524 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2525 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2526 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2527 emit_int8(0x6F);
2528 emit_operand(dst, src);
2529 }
2530
2531 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2532 assert(UseAVX > 0, "");
2533 InstructionMark im(this);
2534 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2535 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2536 attributes.reset_is_clear_context();
2537 // swap src<->dst for encoding
2538 assert(src != xnoreg, "sanity");
2539 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2540 emit_int8(0x7F);
2541 emit_operand(src, dst);
2542 }
2543
2544 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2545 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2546 assert(VM_Version::supports_evex(), "");
2547 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2548 attributes.set_is_evex_instruction();
2549 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2550 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2551 emit_int8(0x6F);
2552 emit_int8((unsigned char)(0xC0 | encode));
2553 }
2554
2555 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2556 assert(VM_Version::supports_evex(), "");
2557 InstructionMark im(this);
2558 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2559 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2560 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2561 attributes.set_is_evex_instruction();
2562 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2563 emit_int8(0x6F);
2564 emit_operand(dst, src);
2565 }
2566
2567 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2568 assert(VM_Version::supports_evex(), "");
2569 assert(src != xnoreg, "sanity");
2570 InstructionMark im(this);
2571 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2572 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2573 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2574 attributes.set_is_evex_instruction();
2575 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2576 emit_int8(0x7F);
2577 emit_operand(src, dst);
2578 }
2579
2580 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2581 assert(VM_Version::supports_avx512vlbw(), "");
2582 InstructionMark im(this);
2583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2584 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2585 attributes.set_embedded_opmask_register_specifier(mask);
2586 attributes.set_is_evex_instruction();
2587 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2588 emit_int8(0x6F);
2589 emit_operand(dst, src);
2590 }
2591
2592 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2593 assert(VM_Version::supports_evex(), "");
2594 InstructionMark im(this);
2595 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2597 attributes.set_is_evex_instruction();
2598 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2599 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2600 emit_int8(0x6F);
2601 emit_operand(dst, src);
2602 }
2603
2604 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2605 assert(VM_Version::supports_avx512vlbw(), "");
2606 InstructionMark im(this);
2607 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2608 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2609 attributes.set_embedded_opmask_register_specifier(mask);
2610 attributes.set_is_evex_instruction();
2611 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2612 emit_int8(0x6F);
2613 emit_operand(dst, src);
2614 }
2615
2616 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2617 assert(VM_Version::supports_evex(), "");
2618 assert(src != xnoreg, "sanity");
2619 InstructionMark im(this);
2620 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2621 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2622 attributes.set_is_evex_instruction();
2623 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2624 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2625 emit_int8(0x7F);
2626 emit_operand(src, dst);
2627 }
2628
2629 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2630 assert(VM_Version::supports_avx512vlbw(), "");
2631 assert(src != xnoreg, "sanity");
2632 InstructionMark im(this);
2633 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2634 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2635 attributes.reset_is_clear_context();
2636 attributes.set_embedded_opmask_register_specifier(mask);
2637 attributes.set_is_evex_instruction();
2638 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2639 emit_int8(0x7F);
2640 emit_operand(src, dst);
2641 }
2642
2643 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2644 assert(VM_Version::supports_evex(), "");
2645 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2646 attributes.set_is_evex_instruction();
2647 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2648 emit_int8(0x6F);
2649 emit_int8((unsigned char)(0xC0 | encode));
2650 }
2651
2652 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2653 assert(VM_Version::supports_evex(), "");
2654 InstructionMark im(this);
2655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true);
2656 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2657 attributes.set_is_evex_instruction();
2658 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2659 emit_int8(0x6F);
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2664 assert(VM_Version::supports_evex(), "");
2665 assert(src != xnoreg, "sanity");
2666 InstructionMark im(this);
2667 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2669 attributes.reset_is_clear_context();
2670 attributes.set_is_evex_instruction();
2671 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2672 emit_int8(0x7F);
2673 emit_operand(src, dst);
2674 }
2675
2676 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2677 assert(VM_Version::supports_evex(), "");
2678 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2679 attributes.set_is_evex_instruction();
2680 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2681 emit_int8(0x6F);
2682 emit_int8((unsigned char)(0xC0 | encode));
2683 }
2684
2685 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2686 assert(VM_Version::supports_evex(), "");
2687 InstructionMark im(this);
2688 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2689 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2690 attributes.set_is_evex_instruction();
2691 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2692 emit_int8(0x6F);
2693 emit_operand(dst, src);
2694 }
2695
2696 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2697 assert(VM_Version::supports_evex(), "");
2698 assert(src != xnoreg, "sanity");
2699 InstructionMark im(this);
2700 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2701 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2702 attributes.reset_is_clear_context();
2703 attributes.set_is_evex_instruction();
2704 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2705 emit_int8(0x7F);
2706 emit_operand(src, dst);
2707 }
2708
2709 // Uses zero extension on 64bit
2710
2711 void Assembler::movl(Register dst, int32_t imm32) {
2712 int encode = prefix_and_encode(dst->encoding());
2713 emit_int8((unsigned char)(0xB8 | encode));
2714 emit_int32(imm32);
2715 }
2716
2717 void Assembler::movl(Register dst, Register src) {
2718 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2719 emit_int8((unsigned char)0x8B);
2720 emit_int8((unsigned char)(0xC0 | encode));
2721 }
2722
2723 void Assembler::movl(Register dst, Address src) {
2724 InstructionMark im(this);
2725 prefix(src, dst);
2726 emit_int8((unsigned char)0x8B);
2727 emit_operand(dst, src);
2728 }
2729
2730 void Assembler::movl(Address dst, int32_t imm32) {
2731 InstructionMark im(this);
2732 prefix(dst);
2733 emit_int8((unsigned char)0xC7);
2734 emit_operand(rax, dst, 4);
2735 emit_int32(imm32);
2736 }
2737
2738 void Assembler::movl(Address dst, Register src) {
2739 InstructionMark im(this);
2740 prefix(dst, src);
2741 emit_int8((unsigned char)0x89);
2742 emit_operand(src, dst);
2743 }
2744
2745 // New cpus require to use movsd and movss to avoid partial register stall
2746 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2747 // The selection is done in MacroAssembler::movdbl() and movflt().
2748 void Assembler::movlpd(XMMRegister dst, Address src) {
2749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2750 InstructionMark im(this);
2751 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2752 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2753 attributes.set_rex_vex_w_reverted();
2754 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2755 emit_int8(0x12);
2756 emit_operand(dst, src);
2757 }
2758
2759 void Assembler::movq( MMXRegister dst, Address src ) {
2760 assert( VM_Version::supports_mmx(), "" );
2761 emit_int8(0x0F);
2762 emit_int8(0x6F);
2763 emit_operand(dst, src);
2764 }
2765
2766 void Assembler::movq( Address dst, MMXRegister src ) {
2767 assert( VM_Version::supports_mmx(), "" );
2768 emit_int8(0x0F);
2769 emit_int8(0x7F);
2770 // workaround gcc (3.2.1-7a) bug
2771 // In that version of gcc with only an emit_operand(MMX, Address)
2772 // gcc will tail jump and try and reverse the parameters completely
2773 // obliterating dst in the process. By having a version available
2774 // that doesn't need to swap the args at the tail jump the bug is
2775 // avoided.
2776 emit_operand(dst, src);
2777 }
2778
2779 void Assembler::movq(XMMRegister dst, Address src) {
2780 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2781 InstructionMark im(this);
2782 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2783 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2784 attributes.set_rex_vex_w_reverted();
2785 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2786 emit_int8(0x7E);
2787 emit_operand(dst, src);
2788 }
2789
2790 void Assembler::movq(Address dst, XMMRegister src) {
2791 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2792 InstructionMark im(this);
2793 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2794 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2795 attributes.set_rex_vex_w_reverted();
2796 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2797 emit_int8((unsigned char)0xD6);
2798 emit_operand(src, dst);
2799 }
2800
2801 void Assembler::movsbl(Register dst, Address src) { // movsxb
2802 InstructionMark im(this);
2803 prefix(src, dst);
2804 emit_int8(0x0F);
2805 emit_int8((unsigned char)0xBE);
2806 emit_operand(dst, src);
2807 }
2808
2809 void Assembler::movsbl(Register dst, Register src) { // movsxb
2810 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2811 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2812 emit_int8(0x0F);
2813 emit_int8((unsigned char)0xBE);
2814 emit_int8((unsigned char)(0xC0 | encode));
2815 }
2816
2817 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2819 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2820 attributes.set_rex_vex_w_reverted();
2821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2822 emit_int8(0x10);
2823 emit_int8((unsigned char)(0xC0 | encode));
2824 }
2825
2826 void Assembler::movsd(XMMRegister dst, Address src) {
2827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2828 InstructionMark im(this);
2829 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2831 attributes.set_rex_vex_w_reverted();
2832 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2833 emit_int8(0x10);
2834 emit_operand(dst, src);
2835 }
2836
2837 void Assembler::movsd(Address dst, XMMRegister src) {
2838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2839 InstructionMark im(this);
2840 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2841 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2842 attributes.reset_is_clear_context();
2843 attributes.set_rex_vex_w_reverted();
2844 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2845 emit_int8(0x11);
2846 emit_operand(src, dst);
2847 }
2848
2849 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2852 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2853 emit_int8(0x10);
2854 emit_int8((unsigned char)(0xC0 | encode));
2855 }
2856
2857 void Assembler::movss(XMMRegister dst, Address src) {
2858 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2859 InstructionMark im(this);
2860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2861 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2862 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2863 emit_int8(0x10);
2864 emit_operand(dst, src);
2865 }
2866
2867 void Assembler::movss(Address dst, XMMRegister src) {
2868 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2869 InstructionMark im(this);
2870 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2871 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2872 attributes.reset_is_clear_context();
2873 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2874 emit_int8(0x11);
2875 emit_operand(src, dst);
2876 }
2877
2878 void Assembler::movswl(Register dst, Address src) { // movsxw
2879 InstructionMark im(this);
2880 prefix(src, dst);
2881 emit_int8(0x0F);
2882 emit_int8((unsigned char)0xBF);
2883 emit_operand(dst, src);
2884 }
2885
2886 void Assembler::movswl(Register dst, Register src) { // movsxw
2887 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2888 emit_int8(0x0F);
2889 emit_int8((unsigned char)0xBF);
2890 emit_int8((unsigned char)(0xC0 | encode));
2891 }
2892
2893 void Assembler::movw(Address dst, int imm16) {
2894 InstructionMark im(this);
2895
2896 emit_int8(0x66); // switch to 16-bit mode
2897 prefix(dst);
2898 emit_int8((unsigned char)0xC7);
2899 emit_operand(rax, dst, 2);
2900 emit_int16(imm16);
2901 }
2902
2903 void Assembler::movw(Register dst, Address src) {
2904 InstructionMark im(this);
2905 emit_int8(0x66);
2906 prefix(src, dst);
2907 emit_int8((unsigned char)0x8B);
2908 emit_operand(dst, src);
2909 }
2910
2911 void Assembler::movw(Address dst, Register src) {
2912 InstructionMark im(this);
2913 emit_int8(0x66);
2914 prefix(dst, src);
2915 emit_int8((unsigned char)0x89);
2916 emit_operand(src, dst);
2917 }
2918
2919 void Assembler::movzbl(Register dst, Address src) { // movzxb
2920 InstructionMark im(this);
2921 prefix(src, dst);
2922 emit_int8(0x0F);
2923 emit_int8((unsigned char)0xB6);
2924 emit_operand(dst, src);
2925 }
2926
2927 void Assembler::movzbl(Register dst, Register src) { // movzxb
2928 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2929 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2930 emit_int8(0x0F);
2931 emit_int8((unsigned char)0xB6);
2932 emit_int8(0xC0 | encode);
2933 }
2934
2935 void Assembler::movzwl(Register dst, Address src) { // movzxw
2936 InstructionMark im(this);
2937 prefix(src, dst);
2938 emit_int8(0x0F);
2939 emit_int8((unsigned char)0xB7);
2940 emit_operand(dst, src);
2941 }
2942
2943 void Assembler::movzwl(Register dst, Register src) { // movzxw
2944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2945 emit_int8(0x0F);
2946 emit_int8((unsigned char)0xB7);
2947 emit_int8(0xC0 | encode);
2948 }
2949
2950 void Assembler::mull(Address src) {
2951 InstructionMark im(this);
2952 prefix(src);
2953 emit_int8((unsigned char)0xF7);
2954 emit_operand(rsp, src);
2955 }
2956
2957 void Assembler::mull(Register src) {
2958 int encode = prefix_and_encode(src->encoding());
2959 emit_int8((unsigned char)0xF7);
2960 emit_int8((unsigned char)(0xE0 | encode));
2961 }
2962
2963 void Assembler::mulsd(XMMRegister dst, Address src) {
2964 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2965 InstructionMark im(this);
2966 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2967 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2968 attributes.set_rex_vex_w_reverted();
2969 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2970 emit_int8(0x59);
2971 emit_operand(dst, src);
2972 }
2973
2974 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2976 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2977 attributes.set_rex_vex_w_reverted();
2978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2979 emit_int8(0x59);
2980 emit_int8((unsigned char)(0xC0 | encode));
2981 }
2982
2983 void Assembler::mulss(XMMRegister dst, Address src) {
2984 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2985 InstructionMark im(this);
2986 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2987 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2988 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2989 emit_int8(0x59);
2990 emit_operand(dst, src);
2991 }
2992
2993 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2994 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2996 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2997 emit_int8(0x59);
2998 emit_int8((unsigned char)(0xC0 | encode));
2999 }
3000
3001 void Assembler::negl(Register dst) {
3002 int encode = prefix_and_encode(dst->encoding());
3003 emit_int8((unsigned char)0xF7);
3004 emit_int8((unsigned char)(0xD8 | encode));
3005 }
3006
3007 void Assembler::nop(int i) {
3008 #ifdef ASSERT
3009 assert(i > 0, " ");
3010 // The fancy nops aren't currently recognized by debuggers making it a
3011 // pain to disassemble code while debugging. If asserts are on clearly
3012 // speed is not an issue so simply use the single byte traditional nop
3013 // to do alignment.
3014
3015 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3016 return;
3017
3018 #endif // ASSERT
3019
3020 if (UseAddressNop && VM_Version::is_intel()) {
3021 //
3022 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3023 // 1: 0x90
3024 // 2: 0x66 0x90
3025 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3026 // 4: 0x0F 0x1F 0x40 0x00
3027 // 5: 0x0F 0x1F 0x44 0x00 0x00
3028 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3029 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3030 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3031 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3032 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3033 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3034
3035 // The rest coding is Intel specific - don't use consecutive address nops
3036
3037 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3038 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3039 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3040 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3041
3042 while(i >= 15) {
3043 // For Intel don't generate consecutive addess nops (mix with regular nops)
3044 i -= 15;
3045 emit_int8(0x66); // size prefix
3046 emit_int8(0x66); // size prefix
3047 emit_int8(0x66); // size prefix
3048 addr_nop_8();
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66); // size prefix
3051 emit_int8(0x66); // size prefix
3052 emit_int8((unsigned char)0x90);
3053 // nop
3054 }
3055 switch (i) {
3056 case 14:
3057 emit_int8(0x66); // size prefix
3058 case 13:
3059 emit_int8(0x66); // size prefix
3060 case 12:
3061 addr_nop_8();
3062 emit_int8(0x66); // size prefix
3063 emit_int8(0x66); // size prefix
3064 emit_int8(0x66); // size prefix
3065 emit_int8((unsigned char)0x90);
3066 // nop
3067 break;
3068 case 11:
3069 emit_int8(0x66); // size prefix
3070 case 10:
3071 emit_int8(0x66); // size prefix
3072 case 9:
3073 emit_int8(0x66); // size prefix
3074 case 8:
3075 addr_nop_8();
3076 break;
3077 case 7:
3078 addr_nop_7();
3079 break;
3080 case 6:
3081 emit_int8(0x66); // size prefix
3082 case 5:
3083 addr_nop_5();
3084 break;
3085 case 4:
3086 addr_nop_4();
3087 break;
3088 case 3:
3089 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3090 emit_int8(0x66); // size prefix
3091 case 2:
3092 emit_int8(0x66); // size prefix
3093 case 1:
3094 emit_int8((unsigned char)0x90);
3095 // nop
3096 break;
3097 default:
3098 assert(i == 0, " ");
3099 }
3100 return;
3101 }
3102 if (UseAddressNop && VM_Version::is_amd()) {
3103 //
3104 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3105 // 1: 0x90
3106 // 2: 0x66 0x90
3107 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3108 // 4: 0x0F 0x1F 0x40 0x00
3109 // 5: 0x0F 0x1F 0x44 0x00 0x00
3110 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3111 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3112 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3113 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3114 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3115 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3116
3117 // The rest coding is AMD specific - use consecutive address nops
3118
3119 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3120 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3121 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3122 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3123 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3124 // Size prefixes (0x66) are added for larger sizes
3125
3126 while(i >= 22) {
3127 i -= 11;
3128 emit_int8(0x66); // size prefix
3129 emit_int8(0x66); // size prefix
3130 emit_int8(0x66); // size prefix
3131 addr_nop_8();
3132 }
3133 // Generate first nop for size between 21-12
3134 switch (i) {
3135 case 21:
3136 i -= 1;
3137 emit_int8(0x66); // size prefix
3138 case 20:
3139 case 19:
3140 i -= 1;
3141 emit_int8(0x66); // size prefix
3142 case 18:
3143 case 17:
3144 i -= 1;
3145 emit_int8(0x66); // size prefix
3146 case 16:
3147 case 15:
3148 i -= 8;
3149 addr_nop_8();
3150 break;
3151 case 14:
3152 case 13:
3153 i -= 7;
3154 addr_nop_7();
3155 break;
3156 case 12:
3157 i -= 6;
3158 emit_int8(0x66); // size prefix
3159 addr_nop_5();
3160 break;
3161 default:
3162 assert(i < 12, " ");
3163 }
3164
3165 // Generate second nop for size between 11-1
3166 switch (i) {
3167 case 11:
3168 emit_int8(0x66); // size prefix
3169 case 10:
3170 emit_int8(0x66); // size prefix
3171 case 9:
3172 emit_int8(0x66); // size prefix
3173 case 8:
3174 addr_nop_8();
3175 break;
3176 case 7:
3177 addr_nop_7();
3178 break;
3179 case 6:
3180 emit_int8(0x66); // size prefix
3181 case 5:
3182 addr_nop_5();
3183 break;
3184 case 4:
3185 addr_nop_4();
3186 break;
3187 case 3:
3188 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3189 emit_int8(0x66); // size prefix
3190 case 2:
3191 emit_int8(0x66); // size prefix
3192 case 1:
3193 emit_int8((unsigned char)0x90);
3194 // nop
3195 break;
3196 default:
3197 assert(i == 0, " ");
3198 }
3199 return;
3200 }
3201
3202 if (UseAddressNop && VM_Version::is_zx()) {
3203 //
3204 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3205 // 1: 0x90
3206 // 2: 0x66 0x90
3207 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3208 // 4: 0x0F 0x1F 0x40 0x00
3209 // 5: 0x0F 0x1F 0x44 0x00 0x00
3210 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3211 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3212 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3213 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3214 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3215 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3216
3217 // The rest coding is ZX specific - don't use consecutive address nops
3218
3219 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3220 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3221 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3222 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3223
3224 while (i >= 15) {
3225 // For ZX don't generate consecutive addess nops (mix with regular nops)
3226 i -= 15;
3227 emit_int8(0x66); // size prefix
3228 emit_int8(0x66); // size prefix
3229 emit_int8(0x66); // size prefix
3230 addr_nop_8();
3231 emit_int8(0x66); // size prefix
3232 emit_int8(0x66); // size prefix
3233 emit_int8(0x66); // size prefix
3234 emit_int8((unsigned char)0x90);
3235 // nop
3236 }
3237 switch (i) {
3238 case 14:
3239 emit_int8(0x66); // size prefix
3240 case 13:
3241 emit_int8(0x66); // size prefix
3242 case 12:
3243 addr_nop_8();
3244 emit_int8(0x66); // size prefix
3245 emit_int8(0x66); // size prefix
3246 emit_int8(0x66); // size prefix
3247 emit_int8((unsigned char)0x90);
3248 // nop
3249 break;
3250 case 11:
3251 emit_int8(0x66); // size prefix
3252 case 10:
3253 emit_int8(0x66); // size prefix
3254 case 9:
3255 emit_int8(0x66); // size prefix
3256 case 8:
3257 addr_nop_8();
3258 break;
3259 case 7:
3260 addr_nop_7();
3261 break;
3262 case 6:
3263 emit_int8(0x66); // size prefix
3264 case 5:
3265 addr_nop_5();
3266 break;
3267 case 4:
3268 addr_nop_4();
3269 break;
3270 case 3:
3271 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3272 emit_int8(0x66); // size prefix
3273 case 2:
3274 emit_int8(0x66); // size prefix
3275 case 1:
3276 emit_int8((unsigned char)0x90);
3277 // nop
3278 break;
3279 default:
3280 assert(i == 0, " ");
3281 }
3282 return;
3283 }
3284
3285 // Using nops with size prefixes "0x66 0x90".
3286 // From AMD Optimization Guide:
3287 // 1: 0x90
3288 // 2: 0x66 0x90
3289 // 3: 0x66 0x66 0x90
3290 // 4: 0x66 0x66 0x66 0x90
3291 // 5: 0x66 0x66 0x90 0x66 0x90
3292 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3293 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3294 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3295 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3296 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3297 //
3298 while(i > 12) {
3299 i -= 4;
3300 emit_int8(0x66); // size prefix
3301 emit_int8(0x66);
3302 emit_int8(0x66);
3303 emit_int8((unsigned char)0x90);
3304 // nop
3305 }
3306 // 1 - 12 nops
3307 if(i > 8) {
3308 if(i > 9) {
3309 i -= 1;
3310 emit_int8(0x66);
3311 }
3312 i -= 3;
3313 emit_int8(0x66);
3314 emit_int8(0x66);
3315 emit_int8((unsigned char)0x90);
3316 }
3317 // 1 - 8 nops
3318 if(i > 4) {
3319 if(i > 6) {
3320 i -= 1;
3321 emit_int8(0x66);
3322 }
3323 i -= 3;
3324 emit_int8(0x66);
3325 emit_int8(0x66);
3326 emit_int8((unsigned char)0x90);
3327 }
3328 switch (i) {
3329 case 4:
3330 emit_int8(0x66);
3331 case 3:
3332 emit_int8(0x66);
3333 case 2:
3334 emit_int8(0x66);
3335 case 1:
3336 emit_int8((unsigned char)0x90);
3337 break;
3338 default:
3339 assert(i == 0, " ");
3340 }
3341 }
3342
3343 void Assembler::notl(Register dst) {
3344 int encode = prefix_and_encode(dst->encoding());
3345 emit_int8((unsigned char)0xF7);
3346 emit_int8((unsigned char)(0xD0 | encode));
3347 }
3348
3349 void Assembler::orl(Address dst, int32_t imm32) {
3350 InstructionMark im(this);
3351 prefix(dst);
3352 emit_arith_operand(0x81, rcx, dst, imm32);
3353 }
3354
3355 void Assembler::orl(Register dst, int32_t imm32) {
3356 prefix(dst);
3357 emit_arith(0x81, 0xC8, dst, imm32);
3358 }
3359
3360 void Assembler::orl(Register dst, Address src) {
3361 InstructionMark im(this);
3362 prefix(src, dst);
3363 emit_int8(0x0B);
3364 emit_operand(dst, src);
3365 }
3366
3367 void Assembler::orl(Register dst, Register src) {
3368 (void) prefix_and_encode(dst->encoding(), src->encoding());
3369 emit_arith(0x0B, 0xC0, dst, src);
3370 }
3371
3372 void Assembler::orl(Address dst, Register src) {
3373 InstructionMark im(this);
3374 prefix(dst, src);
3375 emit_int8(0x09);
3376 emit_operand(src, dst);
3377 }
3378
3379 void Assembler::orb(Address dst, int imm8) {
3380 InstructionMark im(this);
3381 prefix(dst);
3382 emit_int8((unsigned char)0x80);
3383 emit_operand(rcx, dst, 1);
3384 emit_int8(imm8);
3385 }
3386
3387 void Assembler::packuswb(XMMRegister dst, Address src) {
3388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3389 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3390 InstructionMark im(this);
3391 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3392 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3393 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3394 emit_int8(0x67);
3395 emit_operand(dst, src);
3396 }
3397
3398 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3401 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3402 emit_int8(0x67);
3403 emit_int8((unsigned char)(0xC0 | encode));
3404 }
3405
3406 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3407 assert(UseAVX > 0, "some form of AVX must be enabled");
3408 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3409 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3410 emit_int8(0x67);
3411 emit_int8((unsigned char)(0xC0 | encode));
3412 }
3413
3414 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3415 assert(VM_Version::supports_avx2(), "");
3416 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3417 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3418 emit_int8(0x00);
3419 emit_int8(0xC0 | encode);
3420 emit_int8(imm8);
3421 }
3422
3423 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3424 assert(VM_Version::supports_avx2(), "");
3425 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3426 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3427 emit_int8(0x46);
3428 emit_int8(0xC0 | encode);
3429 emit_int8(imm8);
3430 }
3431
3432 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3433 assert(VM_Version::supports_avx(), "");
3434 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3435 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3436 emit_int8(0x06);
3437 emit_int8(0xC0 | encode);
3438 emit_int8(imm8);
3439 }
3440
3441 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3442 assert(VM_Version::supports_evex(), "");
3443 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3444 attributes.set_is_evex_instruction();
3445 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3446 emit_int8(0x76);
3447 emit_int8((unsigned char)(0xC0 | encode));
3448 }
3449
3450
3451 void Assembler::pause() {
3452 emit_int8((unsigned char)0xF3);
3453 emit_int8((unsigned char)0x90);
3454 }
3455
3456 void Assembler::ud2() {
3457 emit_int8(0x0F);
3458 emit_int8(0x0B);
3459 }
3460
3461 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3462 assert(VM_Version::supports_sse4_2(), "");
3463 InstructionMark im(this);
3464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3465 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3466 emit_int8(0x61);
3467 emit_operand(dst, src);
3468 emit_int8(imm8);
3469 }
3470
3471 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3472 assert(VM_Version::supports_sse4_2(), "");
3473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3474 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3475 emit_int8(0x61);
3476 emit_int8((unsigned char)(0xC0 | encode));
3477 emit_int8(imm8);
3478 }
3479
3480 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3481 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3482 assert(VM_Version::supports_sse2(), "");
3483 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3484 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3485 emit_int8(0x74);
3486 emit_int8((unsigned char)(0xC0 | encode));
3487 }
3488
3489 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3490 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3491 assert(VM_Version::supports_avx(), "");
3492 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3493 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3494 emit_int8(0x74);
3495 emit_int8((unsigned char)(0xC0 | encode));
3496 }
3497
3498 // In this context, kdst is written the mask used to process the equal components
3499 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3500 assert(VM_Version::supports_avx512bw(), "");
3501 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3502 attributes.set_is_evex_instruction();
3503 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3504 emit_int8(0x74);
3505 emit_int8((unsigned char)(0xC0 | encode));
3506 }
3507
3508 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3509 assert(VM_Version::supports_avx512vlbw(), "");
3510 InstructionMark im(this);
3511 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3512 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3513 attributes.set_is_evex_instruction();
3514 int dst_enc = kdst->encoding();
3515 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3516 emit_int8(0x64);
3517 emit_operand(as_Register(dst_enc), src);
3518 }
3519
3520 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3521 assert(VM_Version::supports_avx512vlbw(), "");
3522 InstructionMark im(this);
3523 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3524 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3525 attributes.reset_is_clear_context();
3526 attributes.set_embedded_opmask_register_specifier(mask);
3527 attributes.set_is_evex_instruction();
3528 int dst_enc = kdst->encoding();
3529 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3530 emit_int8(0x64);
3531 emit_operand(as_Register(dst_enc), src);
3532 }
3533
3534 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3535 assert(VM_Version::supports_avx512vlbw(), "");
3536 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3537 attributes.set_is_evex_instruction();
3538 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3539 emit_int8(0x3E);
3540 emit_int8((unsigned char)(0xC0 | encode));
3541 emit_int8(vcc);
3542 }
3543
3544 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3545 assert(VM_Version::supports_avx512vlbw(), "");
3546 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3547 attributes.reset_is_clear_context();
3548 attributes.set_embedded_opmask_register_specifier(mask);
3549 attributes.set_is_evex_instruction();
3550 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3551 emit_int8(0x3E);
3552 emit_int8((unsigned char)(0xC0 | encode));
3553 emit_int8(vcc);
3554 }
3555
3556 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3557 assert(VM_Version::supports_avx512vlbw(), "");
3558 InstructionMark im(this);
3559 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3560 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3561 attributes.set_is_evex_instruction();
3562 int dst_enc = kdst->encoding();
3563 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3564 emit_int8(0x3E);
3565 emit_operand(as_Register(dst_enc), src);
3566 emit_int8(vcc);
3567 }
3568
3569 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3570 assert(VM_Version::supports_avx512bw(), "");
3571 InstructionMark im(this);
3572 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3573 attributes.set_is_evex_instruction();
3574 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3575 int dst_enc = kdst->encoding();
3576 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3577 emit_int8(0x74);
3578 emit_operand(as_Register(dst_enc), src);
3579 }
3580
3581 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3582 assert(VM_Version::supports_avx512vlbw(), "");
3583 InstructionMark im(this);
3584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true);
3585 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3586 attributes.reset_is_clear_context();
3587 attributes.set_embedded_opmask_register_specifier(mask);
3588 attributes.set_is_evex_instruction();
3589 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3590 emit_int8(0x74);
3591 emit_operand(as_Register(kdst->encoding()), src);
3592 }
3593
3594 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3595 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3596 assert(VM_Version::supports_sse2(), "");
3597 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3598 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3599 emit_int8(0x75);
3600 emit_int8((unsigned char)(0xC0 | encode));
3601 }
3602
3603 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3604 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3605 assert(VM_Version::supports_avx(), "");
3606 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3607 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3608 emit_int8(0x75);
3609 emit_int8((unsigned char)(0xC0 | encode));
3610 }
3611
3612 // In this context, kdst is written the mask used to process the equal components
3613 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3614 assert(VM_Version::supports_avx512bw(), "");
3615 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3616 attributes.set_is_evex_instruction();
3617 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3618 emit_int8(0x75);
3619 emit_int8((unsigned char)(0xC0 | encode));
3620 }
3621
3622 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3623 assert(VM_Version::supports_avx512bw(), "");
3624 InstructionMark im(this);
3625 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3626 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3627 attributes.set_is_evex_instruction();
3628 int dst_enc = kdst->encoding();
3629 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3630 emit_int8(0x75);
3631 emit_operand(as_Register(dst_enc), src);
3632 }
3633
3634 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3635 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3636 assert(VM_Version::supports_sse2(), "");
3637 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3638 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3639 emit_int8(0x76);
3640 emit_int8((unsigned char)(0xC0 | encode));
3641 }
3642
3643 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3644 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3645 assert(VM_Version::supports_avx(), "");
3646 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3647 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3648 emit_int8(0x76);
3649 emit_int8((unsigned char)(0xC0 | encode));
3650 }
3651
3652 // In this context, kdst is written the mask used to process the equal components
3653 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3654 assert(VM_Version::supports_evex(), "");
3655 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3656 attributes.set_is_evex_instruction();
3657 attributes.reset_is_clear_context();
3658 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3659 emit_int8(0x76);
3660 emit_int8((unsigned char)(0xC0 | encode));
3661 }
3662
3663 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3664 assert(VM_Version::supports_evex(), "");
3665 InstructionMark im(this);
3666 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3667 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3668 attributes.reset_is_clear_context();
3669 attributes.set_is_evex_instruction();
3670 int dst_enc = kdst->encoding();
3671 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3672 emit_int8(0x76);
3673 emit_operand(as_Register(dst_enc), src);
3674 }
3675
3676 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3677 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3678 assert(VM_Version::supports_sse4_1(), "");
3679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3681 emit_int8(0x29);
3682 emit_int8((unsigned char)(0xC0 | encode));
3683 }
3684
3685 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3686 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3687 assert(VM_Version::supports_avx(), "");
3688 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3689 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3690 emit_int8(0x29);
3691 emit_int8((unsigned char)(0xC0 | encode));
3692 }
3693
3694 // In this context, kdst is written the mask used to process the equal components
3695 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3696 assert(VM_Version::supports_evex(), "");
3697 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3698 attributes.reset_is_clear_context();
3699 attributes.set_is_evex_instruction();
3700 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3701 emit_int8(0x29);
3702 emit_int8((unsigned char)(0xC0 | encode));
3703 }
3704
3705 // In this context, kdst is written the mask used to process the equal components
3706 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3707 assert(VM_Version::supports_evex(), "");
3708 InstructionMark im(this);
3709 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3710 attributes.reset_is_clear_context();
3711 attributes.set_is_evex_instruction();
3712 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3713 int dst_enc = kdst->encoding();
3714 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3715 emit_int8(0x29);
3716 emit_operand(as_Register(dst_enc), src);
3717 }
3718
3719 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3720 assert(VM_Version::supports_sse2(), "");
3721 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3722 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3723 emit_int8((unsigned char)0xD7);
3724 emit_int8((unsigned char)(0xC0 | encode));
3725 }
3726
3727 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3728 assert(VM_Version::supports_avx2(), "");
3729 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3730 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3731 emit_int8((unsigned char)0xD7);
3732 emit_int8((unsigned char)(0xC0 | encode));
3733 }
3734
3735 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3736 assert(VM_Version::supports_sse4_1(), "");
3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3738 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3739 emit_int8(0x16);
3740 emit_int8((unsigned char)(0xC0 | encode));
3741 emit_int8(imm8);
3742 }
3743
3744 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3745 assert(VM_Version::supports_sse4_1(), "");
3746 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3747 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3748 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3749 emit_int8(0x16);
3750 emit_operand(src, dst);
3751 emit_int8(imm8);
3752 }
3753
3754 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3755 assert(VM_Version::supports_sse4_1(), "");
3756 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3757 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3758 emit_int8(0x16);
3759 emit_int8((unsigned char)(0xC0 | encode));
3760 emit_int8(imm8);
3761 }
3762
3763 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3764 assert(VM_Version::supports_sse4_1(), "");
3765 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3766 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3767 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3768 emit_int8(0x16);
3769 emit_operand(src, dst);
3770 emit_int8(imm8);
3771 }
3772
3773 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3774 assert(VM_Version::supports_sse2(), "");
3775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3776 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3777 emit_int8((unsigned char)0xC5);
3778 emit_int8((unsigned char)(0xC0 | encode));
3779 emit_int8(imm8);
3780 }
3781
3782 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3783 assert(VM_Version::supports_sse4_1(), "");
3784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3786 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3787 emit_int8((unsigned char)0x15);
3788 emit_operand(src, dst);
3789 emit_int8(imm8);
3790 }
3791
3792 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3793 assert(VM_Version::supports_sse4_1(), "");
3794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3795 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3796 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3797 emit_int8(0x14);
3798 emit_operand(src, dst);
3799 emit_int8(imm8);
3800 }
3801
3802 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3803 assert(VM_Version::supports_sse4_1(), "");
3804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3805 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3806 emit_int8(0x22);
3807 emit_int8((unsigned char)(0xC0 | encode));
3808 emit_int8(imm8);
3809 }
3810
3811 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3812 assert(VM_Version::supports_sse4_1(), "");
3813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3814 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3815 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3816 emit_int8(0x22);
3817 emit_operand(dst,src);
3818 emit_int8(imm8);
3819 }
3820
3821 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3822 assert(VM_Version::supports_sse4_1(), "");
3823 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3824 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3825 emit_int8(0x22);
3826 emit_int8((unsigned char)(0xC0 | encode));
3827 emit_int8(imm8);
3828 }
3829
3830 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3831 assert(VM_Version::supports_sse4_1(), "");
3832 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3833 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3834 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3835 emit_int8(0x22);
3836 emit_operand(dst, src);
3837 emit_int8(imm8);
3838 }
3839
3840 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3841 assert(VM_Version::supports_sse2(), "");
3842 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3843 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3844 emit_int8((unsigned char)0xC4);
3845 emit_int8((unsigned char)(0xC0 | encode));
3846 emit_int8(imm8);
3847 }
3848
3849 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3850 assert(VM_Version::supports_sse2(), "");
3851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3852 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3853 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3854 emit_int8((unsigned char)0xC4);
3855 emit_operand(dst, src);
3856 emit_int8(imm8);
3857 }
3858
3859 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3860 assert(VM_Version::supports_sse4_1(), "");
3861 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3862 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3863 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3864 emit_int8(0x20);
3865 emit_operand(dst, src);
3866 emit_int8(imm8);
3867 }
3868
3869 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3870 assert(VM_Version::supports_sse4_1(), "");
3871 InstructionMark im(this);
3872 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3873 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3874 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3875 emit_int8(0x30);
3876 emit_operand(dst, src);
3877 }
3878
3879 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3880 assert(VM_Version::supports_sse4_1(), "");
3881 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3882 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3883 emit_int8(0x30);
3884 emit_int8((unsigned char)(0xC0 | encode));
3885 }
3886
3887 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3888 assert(VM_Version::supports_avx(), "");
3889 InstructionMark im(this);
3890 assert(dst != xnoreg, "sanity");
3891 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3892 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3893 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3894 emit_int8(0x30);
3895 emit_operand(dst, src);
3896 }
3897
3898 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3899 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3900 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3901 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3902 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3903 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3904 emit_int8(0x30);
3905 emit_int8((unsigned char) (0xC0 | encode));
3906 }
3907
3908
3909 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3910 assert(VM_Version::supports_avx512vlbw(), "");
3911 assert(dst != xnoreg, "sanity");
3912 InstructionMark im(this);
3913 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3914 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3915 attributes.set_embedded_opmask_register_specifier(mask);
3916 attributes.set_is_evex_instruction();
3917 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3918 emit_int8(0x30);
3919 emit_operand(dst, src);
3920 }
3921 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3922 assert(VM_Version::supports_avx512vlbw(), "");
3923 assert(src != xnoreg, "sanity");
3924 InstructionMark im(this);
3925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3926 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3927 attributes.set_is_evex_instruction();
3928 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3929 emit_int8(0x30);
3930 emit_operand(src, dst);
3931 }
3932
3933 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3934 assert(VM_Version::supports_avx512vlbw(), "");
3935 assert(src != xnoreg, "sanity");
3936 InstructionMark im(this);
3937 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3938 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3939 attributes.reset_is_clear_context();
3940 attributes.set_embedded_opmask_register_specifier(mask);
3941 attributes.set_is_evex_instruction();
3942 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3943 emit_int8(0x30);
3944 emit_operand(src, dst);
3945 }
3946
3947 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
3948 assert(VM_Version::supports_evex(), "");
3949 assert(src != xnoreg, "sanity");
3950 InstructionMark im(this);
3951 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3952 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
3953 attributes.set_is_evex_instruction();
3954 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3955 emit_int8(0x31);
3956 emit_operand(src, dst);
3957 }
3958
3959 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
3960 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3961 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3962 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
3963 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3964 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3965 emit_int8(0x33);
3966 emit_int8((unsigned char)(0xC0 | encode));
3967 }
3968
3969 // generic
3970 void Assembler::pop(Register dst) {
3971 int encode = prefix_and_encode(dst->encoding());
3972 emit_int8(0x58 | encode);
3973 }
3974
3975 void Assembler::popcntl(Register dst, Address src) {
3976 assert(VM_Version::supports_popcnt(), "must support");
3977 InstructionMark im(this);
3978 emit_int8((unsigned char)0xF3);
3979 prefix(src, dst);
3980 emit_int8(0x0F);
3981 emit_int8((unsigned char)0xB8);
3982 emit_operand(dst, src);
3983 }
3984
3985 void Assembler::popcntl(Register dst, Register src) {
3986 assert(VM_Version::supports_popcnt(), "must support");
3987 emit_int8((unsigned char)0xF3);
3988 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3989 emit_int8(0x0F);
3990 emit_int8((unsigned char)0xB8);
3991 emit_int8((unsigned char)(0xC0 | encode));
3992 }
3993
3994 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
3995 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
3996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3997 attributes.set_is_evex_instruction();
3998 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3999 emit_int8(0x55);
4000 emit_int8((unsigned char)(0xC0 | encode));
4001 }
4002
4003 void Assembler::popf() {
4004 emit_int8((unsigned char)0x9D);
4005 }
4006
4007 #ifndef _LP64 // no 32bit push/pop on amd64
4008 void Assembler::popl(Address dst) {
4009 // NOTE: this will adjust stack by 8byte on 64bits
4010 InstructionMark im(this);
4011 prefix(dst);
4012 emit_int8((unsigned char)0x8F);
4013 emit_operand(rax, dst);
4014 }
4015 #endif
4016
4017 void Assembler::prefetch_prefix(Address src) {
4018 prefix(src);
4019 emit_int8(0x0F);
4020 }
4021
4022 void Assembler::prefetchnta(Address src) {
4023 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4024 InstructionMark im(this);
4025 prefetch_prefix(src);
4026 emit_int8(0x18);
4027 emit_operand(rax, src); // 0, src
4028 }
4029
4030 void Assembler::prefetchr(Address src) {
4031 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4032 InstructionMark im(this);
4033 prefetch_prefix(src);
4034 emit_int8(0x0D);
4035 emit_operand(rax, src); // 0, src
4036 }
4037
4038 void Assembler::prefetcht0(Address src) {
4039 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4040 InstructionMark im(this);
4041 prefetch_prefix(src);
4042 emit_int8(0x18);
4043 emit_operand(rcx, src); // 1, src
4044 }
4045
4046 void Assembler::prefetcht1(Address src) {
4047 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4048 InstructionMark im(this);
4049 prefetch_prefix(src);
4050 emit_int8(0x18);
4051 emit_operand(rdx, src); // 2, src
4052 }
4053
4054 void Assembler::prefetcht2(Address src) {
4055 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4056 InstructionMark im(this);
4057 prefetch_prefix(src);
4058 emit_int8(0x18);
4059 emit_operand(rbx, src); // 3, src
4060 }
4061
4062 void Assembler::prefetchw(Address src) {
4063 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4064 InstructionMark im(this);
4065 prefetch_prefix(src);
4066 emit_int8(0x0D);
4067 emit_operand(rcx, src); // 1, src
4068 }
4069
4070 void Assembler::prefix(Prefix p) {
4071 emit_int8(p);
4072 }
4073
4074 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4075 assert(VM_Version::supports_ssse3(), "");
4076 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4077 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4078 emit_int8(0x00);
4079 emit_int8((unsigned char)(0xC0 | encode));
4080 }
4081
4082 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4083 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4084 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4085 0, "");
4086 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4087 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4088 emit_int8(0x00);
4089 emit_int8((unsigned char)(0xC0 | encode));
4090 }
4091
4092 void Assembler::pshufb(XMMRegister dst, Address src) {
4093 assert(VM_Version::supports_ssse3(), "");
4094 InstructionMark im(this);
4095 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4096 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4097 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4098 emit_int8(0x00);
4099 emit_operand(dst, src);
4100 }
4101
4102 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4103 assert(isByte(mode), "invalid value");
4104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4105 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4106 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4107 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4108 emit_int8(0x70);
4109 emit_int8((unsigned char)(0xC0 | encode));
4110 emit_int8(mode & 0xFF);
4111 }
4112
4113 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4114 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4115 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4116 0, "");
4117 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4118 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4119 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4120 emit_int8(0x70);
4121 emit_int8((unsigned char)(0xC0 | encode));
4122 emit_int8(mode & 0xFF);
4123 }
4124
4125 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4126 assert(isByte(mode), "invalid value");
4127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4128 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4129 InstructionMark im(this);
4130 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4131 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4132 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4133 emit_int8(0x70);
4134 emit_operand(dst, src);
4135 emit_int8(mode & 0xFF);
4136 }
4137
4138 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4139 assert(isByte(mode), "invalid value");
4140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4142 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4143 emit_int8(0x70);
4144 emit_int8((unsigned char)(0xC0 | encode));
4145 emit_int8(mode & 0xFF);
4146 }
4147
4148 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4149 assert(isByte(mode), "invalid value");
4150 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4151 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4152 InstructionMark im(this);
4153 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4154 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4155 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4156 emit_int8(0x70);
4157 emit_operand(dst, src);
4158 emit_int8(mode & 0xFF);
4159 }
4160 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4161 assert(VM_Version::supports_evex(), "requires EVEX support");
4162 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4163 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4164 attributes.set_is_evex_instruction();
4165 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4166 emit_int8(0x43);
4167 emit_int8((unsigned char)(0xC0 | encode));
4168 emit_int8(imm8 & 0xFF);
4169 }
4170
4171 void Assembler::psrldq(XMMRegister dst, int shift) {
4172 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4173 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4175 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4176 emit_int8(0x73);
4177 emit_int8((unsigned char)(0xC0 | encode));
4178 emit_int8(shift);
4179 }
4180
4181 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4182 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4183 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4184 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4185 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4186 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4187 emit_int8(0x73);
4188 emit_int8((unsigned char)(0xC0 | encode));
4189 emit_int8(shift & 0xFF);
4190 }
4191
4192 void Assembler::pslldq(XMMRegister dst, int shift) {
4193 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4194 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4195 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4196 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4197 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4198 emit_int8(0x73);
4199 emit_int8((unsigned char)(0xC0 | encode));
4200 emit_int8(shift);
4201 }
4202
4203 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4204 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4205 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4206 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4207 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4208 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4209 emit_int8(0x73);
4210 emit_int8((unsigned char)(0xC0 | encode));
4211 emit_int8(shift & 0xFF);
4212 }
4213
4214 void Assembler::ptest(XMMRegister dst, Address src) {
4215 assert(VM_Version::supports_sse4_1(), "");
4216 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4217 InstructionMark im(this);
4218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4219 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4220 emit_int8(0x17);
4221 emit_operand(dst, src);
4222 }
4223
4224 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4225 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
4226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4227 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4228 emit_int8(0x17);
4229 emit_int8((unsigned char)(0xC0 | encode));
4230 }
4231
4232 void Assembler::vptest(XMMRegister dst, Address src) {
4233 assert(VM_Version::supports_avx(), "");
4234 InstructionMark im(this);
4235 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4236 assert(dst != xnoreg, "sanity");
4237 // swap src<->dst for encoding
4238 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4239 emit_int8(0x17);
4240 emit_operand(dst, src);
4241 }
4242
4243 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4244 assert(VM_Version::supports_avx(), "");
4245 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4246 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4247 emit_int8(0x17);
4248 emit_int8((unsigned char)(0xC0 | encode));
4249 }
4250
4251 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4252 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4253 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4254 InstructionMark im(this);
4255 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4256 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4257 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4258 emit_int8(0x60);
4259 emit_operand(dst, src);
4260 }
4261
4262 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4263 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4266 emit_int8(0x60);
4267 emit_int8((unsigned char)(0xC0 | encode));
4268 }
4269
4270 void Assembler::punpckldq(XMMRegister dst, Address src) {
4271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4272 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4273 InstructionMark im(this);
4274 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4275 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4276 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4277 emit_int8(0x62);
4278 emit_operand(dst, src);
4279 }
4280
4281 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4282 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4283 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4284 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4285 emit_int8(0x62);
4286 emit_int8((unsigned char)(0xC0 | encode));
4287 }
4288
4289 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4291 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4292 attributes.set_rex_vex_w_reverted();
4293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4294 emit_int8(0x6C);
4295 emit_int8((unsigned char)(0xC0 | encode));
4296 }
4297
4298 void Assembler::push(int32_t imm32) {
4299 // in 64bits we push 64bits onto the stack but only
4300 // take a 32bit immediate
4301 emit_int8(0x68);
4302 emit_int32(imm32);
4303 }
4304
4305 void Assembler::push(Register src) {
4306 int encode = prefix_and_encode(src->encoding());
4307
4308 emit_int8(0x50 | encode);
4309 }
4310
4311 void Assembler::pushf() {
4312 emit_int8((unsigned char)0x9C);
4313 }
4314
4315 #ifndef _LP64 // no 32bit push/pop on amd64
4316 void Assembler::pushl(Address src) {
4317 // Note this will push 64bit on 64bit
4318 InstructionMark im(this);
4319 prefix(src);
4320 emit_int8((unsigned char)0xFF);
4321 emit_operand(rsi, src);
4322 }
4323 #endif
4324
4325 void Assembler::rcll(Register dst, int imm8) {
4326 assert(isShiftCount(imm8), "illegal shift count");
4327 int encode = prefix_and_encode(dst->encoding());
4328 if (imm8 == 1) {
4329 emit_int8((unsigned char)0xD1);
4330 emit_int8((unsigned char)(0xD0 | encode));
4331 } else {
4332 emit_int8((unsigned char)0xC1);
4333 emit_int8((unsigned char)0xD0 | encode);
4334 emit_int8(imm8);
4335 }
4336 }
4337
4338 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4339 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4341 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4342 emit_int8(0x53);
4343 emit_int8((unsigned char)(0xC0 | encode));
4344 }
4345
4346 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4347 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4348 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4350 emit_int8(0x53);
4351 emit_int8((unsigned char)(0xC0 | encode));
4352 }
4353
4354 void Assembler::rdtsc() {
4355 emit_int8((unsigned char)0x0F);
4356 emit_int8((unsigned char)0x31);
4357 }
4358
4359 // copies data from [esi] to [edi] using rcx pointer sized words
4360 // generic
4361 void Assembler::rep_mov() {
4362 emit_int8((unsigned char)0xF3);
4363 // MOVSQ
4364 LP64_ONLY(prefix(REX_W));
4365 emit_int8((unsigned char)0xA5);
4366 }
4367
4368 // sets rcx bytes with rax, value at [edi]
4369 void Assembler::rep_stosb() {
4370 emit_int8((unsigned char)0xF3); // REP
4371 LP64_ONLY(prefix(REX_W));
4372 emit_int8((unsigned char)0xAA); // STOSB
4373 }
4374
4375 // sets rcx pointer sized words with rax, value at [edi]
4376 // generic
4377 void Assembler::rep_stos() {
4378 emit_int8((unsigned char)0xF3); // REP
4379 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4380 emit_int8((unsigned char)0xAB);
4381 }
4382
4383 // scans rcx pointer sized words at [edi] for occurance of rax,
4384 // generic
4385 void Assembler::repne_scan() { // repne_scan
4386 emit_int8((unsigned char)0xF2);
4387 // SCASQ
4388 LP64_ONLY(prefix(REX_W));
4389 emit_int8((unsigned char)0xAF);
4390 }
4391
4392 #ifdef _LP64
4393 // scans rcx 4 byte words at [edi] for occurance of rax,
4394 // generic
4395 void Assembler::repne_scanl() { // repne_scan
4396 emit_int8((unsigned char)0xF2);
4397 // SCASL
4398 emit_int8((unsigned char)0xAF);
4399 }
4400 #endif
4401
4402 void Assembler::ret(int imm16) {
4403 if (imm16 == 0) {
4404 emit_int8((unsigned char)0xC3);
4405 } else {
4406 emit_int8((unsigned char)0xC2);
4407 emit_int16(imm16);
4408 }
4409 }
4410
4411 void Assembler::sahf() {
4412 #ifdef _LP64
4413 // Not supported in 64bit mode
4414 ShouldNotReachHere();
4415 #endif
4416 emit_int8((unsigned char)0x9E);
4417 }
4418
4419 void Assembler::sarl(Register dst, int imm8) {
4420 int encode = prefix_and_encode(dst->encoding());
4421 assert(isShiftCount(imm8), "illegal shift count");
4422 if (imm8 == 1) {
4423 emit_int8((unsigned char)0xD1);
4424 emit_int8((unsigned char)(0xF8 | encode));
4425 } else {
4426 emit_int8((unsigned char)0xC1);
4427 emit_int8((unsigned char)(0xF8 | encode));
4428 emit_int8(imm8);
4429 }
4430 }
4431
4432 void Assembler::sarl(Register dst) {
4433 int encode = prefix_and_encode(dst->encoding());
4434 emit_int8((unsigned char)0xD3);
4435 emit_int8((unsigned char)(0xF8 | encode));
4436 }
4437
4438 void Assembler::sbbl(Address dst, int32_t imm32) {
4439 InstructionMark im(this);
4440 prefix(dst);
4441 emit_arith_operand(0x81, rbx, dst, imm32);
4442 }
4443
4444 void Assembler::sbbl(Register dst, int32_t imm32) {
4445 prefix(dst);
4446 emit_arith(0x81, 0xD8, dst, imm32);
4447 }
4448
4449
4450 void Assembler::sbbl(Register dst, Address src) {
4451 InstructionMark im(this);
4452 prefix(src, dst);
4453 emit_int8(0x1B);
4454 emit_operand(dst, src);
4455 }
4456
4457 void Assembler::sbbl(Register dst, Register src) {
4458 (void) prefix_and_encode(dst->encoding(), src->encoding());
4459 emit_arith(0x1B, 0xC0, dst, src);
4460 }
4461
4462 void Assembler::setb(Condition cc, Register dst) {
4463 assert(0 <= cc && cc < 16, "illegal cc");
4464 int encode = prefix_and_encode(dst->encoding(), true);
4465 emit_int8(0x0F);
4466 emit_int8((unsigned char)0x90 | cc);
4467 emit_int8((unsigned char)(0xC0 | encode));
4468 }
4469
4470 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4471 assert(VM_Version::supports_ssse3(), "");
4472 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4473 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4474 emit_int8((unsigned char)0x0F);
4475 emit_int8((unsigned char)(0xC0 | encode));
4476 emit_int8(imm8);
4477 }
4478
4479 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4480 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4481 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4482 0, "");
4483 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4484 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4485 emit_int8((unsigned char)0x0F);
4486 emit_int8((unsigned char)(0xC0 | encode));
4487 emit_int8(imm8);
4488 }
4489
4490 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4491 assert(VM_Version::supports_evex(), "");
4492 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4493 attributes.set_is_evex_instruction();
4494 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4495 emit_int8(0x3);
4496 emit_int8((unsigned char)(0xC0 | encode));
4497 emit_int8(imm8);
4498 }
4499
4500 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4501 assert(VM_Version::supports_sse4_1(), "");
4502 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4503 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4504 emit_int8((unsigned char)0x0E);
4505 emit_int8((unsigned char)(0xC0 | encode));
4506 emit_int8(imm8);
4507 }
4508
4509 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4510 assert(VM_Version::supports_sha(), "");
4511 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4512 emit_int8((unsigned char)0xCC);
4513 emit_int8((unsigned char)(0xC0 | encode));
4514 emit_int8((unsigned char)imm8);
4515 }
4516
4517 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4518 assert(VM_Version::supports_sha(), "");
4519 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4520 emit_int8((unsigned char)0xC8);
4521 emit_int8((unsigned char)(0xC0 | encode));
4522 }
4523
4524 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4525 assert(VM_Version::supports_sha(), "");
4526 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4527 emit_int8((unsigned char)0xC9);
4528 emit_int8((unsigned char)(0xC0 | encode));
4529 }
4530
4531 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4532 assert(VM_Version::supports_sha(), "");
4533 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4534 emit_int8((unsigned char)0xCA);
4535 emit_int8((unsigned char)(0xC0 | encode));
4536 }
4537
4538 // xmm0 is implicit additional source to this instruction.
4539 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4540 assert(VM_Version::supports_sha(), "");
4541 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4542 emit_int8((unsigned char)0xCB);
4543 emit_int8((unsigned char)(0xC0 | encode));
4544 }
4545
4546 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4547 assert(VM_Version::supports_sha(), "");
4548 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4549 emit_int8((unsigned char)0xCC);
4550 emit_int8((unsigned char)(0xC0 | encode));
4551 }
4552
4553 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4554 assert(VM_Version::supports_sha(), "");
4555 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4556 emit_int8((unsigned char)0xCD);
4557 emit_int8((unsigned char)(0xC0 | encode));
4558 }
4559
4560
4561 void Assembler::shll(Register dst, int imm8) {
4562 assert(isShiftCount(imm8), "illegal shift count");
4563 int encode = prefix_and_encode(dst->encoding());
4564 if (imm8 == 1 ) {
4565 emit_int8((unsigned char)0xD1);
4566 emit_int8((unsigned char)(0xE0 | encode));
4567 } else {
4568 emit_int8((unsigned char)0xC1);
4569 emit_int8((unsigned char)(0xE0 | encode));
4570 emit_int8(imm8);
4571 }
4572 }
4573
4574 void Assembler::shll(Register dst) {
4575 int encode = prefix_and_encode(dst->encoding());
4576 emit_int8((unsigned char)0xD3);
4577 emit_int8((unsigned char)(0xE0 | encode));
4578 }
4579
4580 void Assembler::shrl(Register dst, int imm8) {
4581 assert(isShiftCount(imm8), "illegal shift count");
4582 int encode = prefix_and_encode(dst->encoding());
4583 emit_int8((unsigned char)0xC1);
4584 emit_int8((unsigned char)(0xE8 | encode));
4585 emit_int8(imm8);
4586 }
4587
4588 void Assembler::shrl(Register dst) {
4589 int encode = prefix_and_encode(dst->encoding());
4590 emit_int8((unsigned char)0xD3);
4591 emit_int8((unsigned char)(0xE8 | encode));
4592 }
4593
4594 // copies a single word from [esi] to [edi]
4595 void Assembler::smovl() {
4596 emit_int8((unsigned char)0xA5);
4597 }
4598
4599 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4601 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4602 attributes.set_rex_vex_w_reverted();
4603 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4604 emit_int8(0x51);
4605 emit_int8((unsigned char)(0xC0 | encode));
4606 }
4607
4608 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4610 InstructionMark im(this);
4611 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4612 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4613 attributes.set_rex_vex_w_reverted();
4614 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4615 emit_int8(0x51);
4616 emit_operand(dst, src);
4617 }
4618
4619 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4620 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4621 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4622 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4623 emit_int8(0x51);
4624 emit_int8((unsigned char)(0xC0 | encode));
4625 }
4626
4627 void Assembler::std() {
4628 emit_int8((unsigned char)0xFD);
4629 }
4630
4631 void Assembler::sqrtss(XMMRegister dst, Address src) {
4632 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4633 InstructionMark im(this);
4634 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4635 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4636 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4637 emit_int8(0x51);
4638 emit_operand(dst, src);
4639 }
4640
4641 void Assembler::stmxcsr( Address dst) {
4642 if (UseAVX > 0 ) {
4643 assert(VM_Version::supports_avx(), "");
4644 InstructionMark im(this);
4645 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4646 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4647 emit_int8((unsigned char)0xAE);
4648 emit_operand(as_Register(3), dst);
4649 } else {
4650 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4651 InstructionMark im(this);
4652 prefix(dst);
4653 emit_int8(0x0F);
4654 emit_int8((unsigned char)0xAE);
4655 emit_operand(as_Register(3), dst);
4656 }
4657 }
4658
4659 void Assembler::subl(Address dst, int32_t imm32) {
4660 InstructionMark im(this);
4661 prefix(dst);
4662 emit_arith_operand(0x81, rbp, dst, imm32);
4663 }
4664
4665 void Assembler::subl(Address dst, Register src) {
4666 InstructionMark im(this);
4667 prefix(dst, src);
4668 emit_int8(0x29);
4669 emit_operand(src, dst);
4670 }
4671
4672 void Assembler::subl(Register dst, int32_t imm32) {
4673 prefix(dst);
4674 emit_arith(0x81, 0xE8, dst, imm32);
4675 }
4676
4677 // Force generation of a 4 byte immediate value even if it fits into 8bit
4678 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4679 prefix(dst);
4680 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4681 }
4682
4683 void Assembler::subl(Register dst, Address src) {
4684 InstructionMark im(this);
4685 prefix(src, dst);
4686 emit_int8(0x2B);
4687 emit_operand(dst, src);
4688 }
4689
4690 void Assembler::subl(Register dst, Register src) {
4691 (void) prefix_and_encode(dst->encoding(), src->encoding());
4692 emit_arith(0x2B, 0xC0, dst, src);
4693 }
4694
4695 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4696 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4697 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4698 attributes.set_rex_vex_w_reverted();
4699 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4700 emit_int8(0x5C);
4701 emit_int8((unsigned char)(0xC0 | encode));
4702 }
4703
4704 void Assembler::subsd(XMMRegister dst, Address src) {
4705 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4706 InstructionMark im(this);
4707 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4708 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4709 attributes.set_rex_vex_w_reverted();
4710 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4711 emit_int8(0x5C);
4712 emit_operand(dst, src);
4713 }
4714
4715 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4716 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4718 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4719 emit_int8(0x5C);
4720 emit_int8((unsigned char)(0xC0 | encode));
4721 }
4722
4723 void Assembler::subss(XMMRegister dst, Address src) {
4724 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4725 InstructionMark im(this);
4726 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4727 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4728 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4729 emit_int8(0x5C);
4730 emit_operand(dst, src);
4731 }
4732
4733 void Assembler::testb(Register dst, int imm8) {
4734 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4735 (void) prefix_and_encode(dst->encoding(), true);
4736 emit_arith_b(0xF6, 0xC0, dst, imm8);
4737 }
4738
4739 void Assembler::testb(Address dst, int imm8) {
4740 InstructionMark im(this);
4741 prefix(dst);
4742 emit_int8((unsigned char)0xF6);
4743 emit_operand(rax, dst, 1);
4744 emit_int8(imm8);
4745 }
4746
4747 void Assembler::testl(Register dst, int32_t imm32) {
4748 // not using emit_arith because test
4749 // doesn't support sign-extension of
4750 // 8bit operands
4751 int encode = dst->encoding();
4752 if (encode == 0) {
4753 emit_int8((unsigned char)0xA9);
4754 } else {
4755 encode = prefix_and_encode(encode);
4756 emit_int8((unsigned char)0xF7);
4757 emit_int8((unsigned char)(0xC0 | encode));
4758 }
4759 emit_int32(imm32);
4760 }
4761
4762 void Assembler::testl(Register dst, Register src) {
4763 (void) prefix_and_encode(dst->encoding(), src->encoding());
4764 emit_arith(0x85, 0xC0, dst, src);
4765 }
4766
4767 void Assembler::testl(Register dst, Address src) {
4768 InstructionMark im(this);
4769 prefix(src, dst);
4770 emit_int8((unsigned char)0x85);
4771 emit_operand(dst, src);
4772 }
4773
4774 void Assembler::tzcntl(Register dst, Register src) {
4775 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4776 emit_int8((unsigned char)0xF3);
4777 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4778 emit_int8(0x0F);
4779 emit_int8((unsigned char)0xBC);
4780 emit_int8((unsigned char)0xC0 | encode);
4781 }
4782
4783 void Assembler::tzcntq(Register dst, Register src) {
4784 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4785 emit_int8((unsigned char)0xF3);
4786 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4787 emit_int8(0x0F);
4788 emit_int8((unsigned char)0xBC);
4789 emit_int8((unsigned char)(0xC0 | encode));
4790 }
4791
4792 void Assembler::ucomisd(XMMRegister dst, Address src) {
4793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4794 InstructionMark im(this);
4795 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4796 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4797 attributes.set_rex_vex_w_reverted();
4798 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4799 emit_int8(0x2E);
4800 emit_operand(dst, src);
4801 }
4802
4803 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4805 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4806 attributes.set_rex_vex_w_reverted();
4807 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4808 emit_int8(0x2E);
4809 emit_int8((unsigned char)(0xC0 | encode));
4810 }
4811
4812 void Assembler::ucomiss(XMMRegister dst, Address src) {
4813 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4814 InstructionMark im(this);
4815 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4816 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4817 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4818 emit_int8(0x2E);
4819 emit_operand(dst, src);
4820 }
4821
4822 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4825 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4826 emit_int8(0x2E);
4827 emit_int8((unsigned char)(0xC0 | encode));
4828 }
4829
4830 void Assembler::xabort(int8_t imm8) {
4831 emit_int8((unsigned char)0xC6);
4832 emit_int8((unsigned char)0xF8);
4833 emit_int8((unsigned char)(imm8 & 0xFF));
4834 }
4835
4836 void Assembler::xaddb(Address dst, Register src) {
4837 InstructionMark im(this);
4838 prefix(dst, src, true);
4839 emit_int8(0x0F);
4840 emit_int8((unsigned char)0xC0);
4841 emit_operand(src, dst);
4842 }
4843
4844 void Assembler::xaddw(Address dst, Register src) {
4845 InstructionMark im(this);
4846 emit_int8(0x66);
4847 prefix(dst, src);
4848 emit_int8(0x0F);
4849 emit_int8((unsigned char)0xC1);
4850 emit_operand(src, dst);
4851 }
4852
4853 void Assembler::xaddl(Address dst, Register src) {
4854 InstructionMark im(this);
4855 prefix(dst, src);
4856 emit_int8(0x0F);
4857 emit_int8((unsigned char)0xC1);
4858 emit_operand(src, dst);
4859 }
4860
4861 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4862 InstructionMark im(this);
4863 relocate(rtype);
4864 if (abort.is_bound()) {
4865 address entry = target(abort);
4866 assert(entry != NULL, "abort entry NULL");
4867 intptr_t offset = entry - pc();
4868 emit_int8((unsigned char)0xC7);
4869 emit_int8((unsigned char)0xF8);
4870 emit_int32(offset - 6); // 2 opcode + 4 address
4871 } else {
4872 abort.add_patch_at(code(), locator());
4873 emit_int8((unsigned char)0xC7);
4874 emit_int8((unsigned char)0xF8);
4875 emit_int32(0);
4876 }
4877 }
4878
4879 void Assembler::xchgb(Register dst, Address src) { // xchg
4880 InstructionMark im(this);
4881 prefix(src, dst, true);
4882 emit_int8((unsigned char)0x86);
4883 emit_operand(dst, src);
4884 }
4885
4886 void Assembler::xchgw(Register dst, Address src) { // xchg
4887 InstructionMark im(this);
4888 emit_int8(0x66);
4889 prefix(src, dst);
4890 emit_int8((unsigned char)0x87);
4891 emit_operand(dst, src);
4892 }
4893
4894 void Assembler::xchgl(Register dst, Address src) { // xchg
4895 InstructionMark im(this);
4896 prefix(src, dst);
4897 emit_int8((unsigned char)0x87);
4898 emit_operand(dst, src);
4899 }
4900
4901 void Assembler::xchgl(Register dst, Register src) {
4902 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4903 emit_int8((unsigned char)0x87);
4904 emit_int8((unsigned char)(0xC0 | encode));
4905 }
4906
4907 void Assembler::xend() {
4908 emit_int8((unsigned char)0x0F);
4909 emit_int8((unsigned char)0x01);
4910 emit_int8((unsigned char)0xD5);
4911 }
4912
4913 void Assembler::xgetbv() {
4914 emit_int8(0x0F);
4915 emit_int8(0x01);
4916 emit_int8((unsigned char)0xD0);
4917 }
4918
4919 void Assembler::xorl(Register dst, int32_t imm32) {
4920 prefix(dst);
4921 emit_arith(0x81, 0xF0, dst, imm32);
4922 }
4923
4924 void Assembler::xorl(Register dst, Address src) {
4925 InstructionMark im(this);
4926 prefix(src, dst);
4927 emit_int8(0x33);
4928 emit_operand(dst, src);
4929 }
4930
4931 void Assembler::xorl(Register dst, Register src) {
4932 (void) prefix_and_encode(dst->encoding(), src->encoding());
4933 emit_arith(0x33, 0xC0, dst, src);
4934 }
4935
4936 void Assembler::xorb(Register dst, Address src) {
4937 InstructionMark im(this);
4938 prefix(src, dst);
4939 emit_int8(0x32);
4940 emit_operand(dst, src);
4941 }
4942
4943 // AVX 3-operands scalar float-point arithmetic instructions
4944
4945 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4946 assert(VM_Version::supports_avx(), "");
4947 InstructionMark im(this);
4948 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4949 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4950 attributes.set_rex_vex_w_reverted();
4951 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4952 emit_int8(0x58);
4953 emit_operand(dst, src);
4954 }
4955
4956 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4957 assert(VM_Version::supports_avx(), "");
4958 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4959 attributes.set_rex_vex_w_reverted();
4960 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4961 emit_int8(0x58);
4962 emit_int8((unsigned char)(0xC0 | encode));
4963 }
4964
4965 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4966 assert(VM_Version::supports_avx(), "");
4967 InstructionMark im(this);
4968 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4969 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4970 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4971 emit_int8(0x58);
4972 emit_operand(dst, src);
4973 }
4974
4975 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4976 assert(VM_Version::supports_avx(), "");
4977 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4978 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4979 emit_int8(0x58);
4980 emit_int8((unsigned char)(0xC0 | encode));
4981 }
4982
4983 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4984 assert(VM_Version::supports_avx(), "");
4985 InstructionMark im(this);
4986 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4987 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4988 attributes.set_rex_vex_w_reverted();
4989 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4990 emit_int8(0x5E);
4991 emit_operand(dst, src);
4992 }
4993
4994 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4995 assert(VM_Version::supports_avx(), "");
4996 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4997 attributes.set_rex_vex_w_reverted();
4998 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4999 emit_int8(0x5E);
5000 emit_int8((unsigned char)(0xC0 | encode));
5001 }
5002
5003 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5004 assert(VM_Version::supports_avx(), "");
5005 InstructionMark im(this);
5006 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5007 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5008 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5009 emit_int8(0x5E);
5010 emit_operand(dst, src);
5011 }
5012
5013 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5014 assert(VM_Version::supports_avx(), "");
5015 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5016 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5017 emit_int8(0x5E);
5018 emit_int8((unsigned char)(0xC0 | encode));
5019 }
5020
5021 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5022 assert(VM_Version::supports_fma(), "");
5023 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5024 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5025 emit_int8((unsigned char)0xB9);
5026 emit_int8((unsigned char)(0xC0 | encode));
5027 }
5028
5029 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5030 assert(VM_Version::supports_fma(), "");
5031 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5032 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5033 emit_int8((unsigned char)0xB9);
5034 emit_int8((unsigned char)(0xC0 | encode));
5035 }
5036
5037 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5038 assert(VM_Version::supports_avx(), "");
5039 InstructionMark im(this);
5040 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5041 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5042 attributes.set_rex_vex_w_reverted();
5043 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5044 emit_int8(0x59);
5045 emit_operand(dst, src);
5046 }
5047
5048 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5049 assert(VM_Version::supports_avx(), "");
5050 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5051 attributes.set_rex_vex_w_reverted();
5052 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5053 emit_int8(0x59);
5054 emit_int8((unsigned char)(0xC0 | encode));
5055 }
5056
5057 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5058 assert(VM_Version::supports_avx(), "");
5059 InstructionMark im(this);
5060 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5061 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5062 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5063 emit_int8(0x59);
5064 emit_operand(dst, src);
5065 }
5066
5067 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5068 assert(VM_Version::supports_avx(), "");
5069 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5070 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5071 emit_int8(0x59);
5072 emit_int8((unsigned char)(0xC0 | encode));
5073 }
5074
5075 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5076 assert(VM_Version::supports_avx(), "");
5077 InstructionMark im(this);
5078 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5079 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5080 attributes.set_rex_vex_w_reverted();
5081 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5082 emit_int8(0x5C);
5083 emit_operand(dst, src);
5084 }
5085
5086 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5087 assert(VM_Version::supports_avx(), "");
5088 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5089 attributes.set_rex_vex_w_reverted();
5090 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5091 emit_int8(0x5C);
5092 emit_int8((unsigned char)(0xC0 | encode));
5093 }
5094
5095 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5096 assert(VM_Version::supports_avx(), "");
5097 InstructionMark im(this);
5098 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5099 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5100 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5101 emit_int8(0x5C);
5102 emit_operand(dst, src);
5103 }
5104
5105 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5106 assert(VM_Version::supports_avx(), "");
5107 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5108 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5109 emit_int8(0x5C);
5110 emit_int8((unsigned char)(0xC0 | encode));
5111 }
5112
5113 //====================VECTOR ARITHMETIC=====================================
5114
5115 // Float-point vector arithmetic
5116
5117 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5119 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5120 attributes.set_rex_vex_w_reverted();
5121 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5122 emit_int8(0x58);
5123 emit_int8((unsigned char)(0xC0 | encode));
5124 }
5125
5126 void Assembler::addpd(XMMRegister dst, Address src) {
5127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5128 InstructionMark im(this);
5129 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5130 attributes.set_rex_vex_w_reverted();
5131 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5132 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5133 emit_int8(0x58);
5134 emit_operand(dst, src);
5135 }
5136
5137
5138 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5139 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5140 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5141 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5142 emit_int8(0x58);
5143 emit_int8((unsigned char)(0xC0 | encode));
5144 }
5145
5146 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5147 assert(VM_Version::supports_avx(), "");
5148 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5149 attributes.set_rex_vex_w_reverted();
5150 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5151 emit_int8(0x58);
5152 emit_int8((unsigned char)(0xC0 | encode));
5153 }
5154
5155 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5156 assert(VM_Version::supports_avx(), "");
5157 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5158 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5159 emit_int8(0x58);
5160 emit_int8((unsigned char)(0xC0 | encode));
5161 }
5162
5163 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5164 assert(VM_Version::supports_avx(), "");
5165 InstructionMark im(this);
5166 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5167 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5168 attributes.set_rex_vex_w_reverted();
5169 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5170 emit_int8(0x58);
5171 emit_operand(dst, src);
5172 }
5173
5174 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5175 assert(VM_Version::supports_avx(), "");
5176 InstructionMark im(this);
5177 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5178 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5179 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5180 emit_int8(0x58);
5181 emit_operand(dst, src);
5182 }
5183
5184 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5185 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5186 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5187 attributes.set_rex_vex_w_reverted();
5188 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5189 emit_int8(0x5C);
5190 emit_int8((unsigned char)(0xC0 | encode));
5191 }
5192
5193 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5194 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5195 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5196 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5197 emit_int8(0x5C);
5198 emit_int8((unsigned char)(0xC0 | encode));
5199 }
5200
5201 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5202 assert(VM_Version::supports_avx(), "");
5203 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5204 attributes.set_rex_vex_w_reverted();
5205 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5206 emit_int8(0x5C);
5207 emit_int8((unsigned char)(0xC0 | encode));
5208 }
5209
5210 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5211 assert(VM_Version::supports_avx(), "");
5212 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5213 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5214 emit_int8(0x5C);
5215 emit_int8((unsigned char)(0xC0 | encode));
5216 }
5217
5218 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5219 assert(VM_Version::supports_avx(), "");
5220 InstructionMark im(this);
5221 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5222 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5223 attributes.set_rex_vex_w_reverted();
5224 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5225 emit_int8(0x5C);
5226 emit_operand(dst, src);
5227 }
5228
5229 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5230 assert(VM_Version::supports_avx(), "");
5231 InstructionMark im(this);
5232 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5233 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5234 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5235 emit_int8(0x5C);
5236 emit_operand(dst, src);
5237 }
5238
5239 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5240 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5241 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5242 attributes.set_rex_vex_w_reverted();
5243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5244 emit_int8(0x59);
5245 emit_int8((unsigned char)(0xC0 | encode));
5246 }
5247
5248 void Assembler::mulpd(XMMRegister dst, Address src) {
5249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5250 InstructionMark im(this);
5251 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5252 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5253 attributes.set_rex_vex_w_reverted();
5254 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5255 emit_int8(0x59);
5256 emit_operand(dst, src);
5257 }
5258
5259 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5262 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5263 emit_int8(0x59);
5264 emit_int8((unsigned char)(0xC0 | encode));
5265 }
5266
5267 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5268 assert(VM_Version::supports_avx(), "");
5269 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5270 attributes.set_rex_vex_w_reverted();
5271 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5272 emit_int8(0x59);
5273 emit_int8((unsigned char)(0xC0 | encode));
5274 }
5275
5276 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5277 assert(VM_Version::supports_avx(), "");
5278 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5279 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5280 emit_int8(0x59);
5281 emit_int8((unsigned char)(0xC0 | encode));
5282 }
5283
5284 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5285 assert(VM_Version::supports_avx(), "");
5286 InstructionMark im(this);
5287 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5288 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5289 attributes.set_rex_vex_w_reverted();
5290 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5291 emit_int8(0x59);
5292 emit_operand(dst, src);
5293 }
5294
5295 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5296 assert(VM_Version::supports_avx(), "");
5297 InstructionMark im(this);
5298 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5299 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5300 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5301 emit_int8(0x59);
5302 emit_operand(dst, src);
5303 }
5304
5305 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5306 assert(VM_Version::supports_fma(), "");
5307 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5308 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5309 emit_int8((unsigned char)0xB8);
5310 emit_int8((unsigned char)(0xC0 | encode));
5311 }
5312
5313 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5314 assert(VM_Version::supports_fma(), "");
5315 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5316 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5317 emit_int8((unsigned char)0xB8);
5318 emit_int8((unsigned char)(0xC0 | encode));
5319 }
5320
5321 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5322 assert(VM_Version::supports_fma(), "");
5323 InstructionMark im(this);
5324 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5325 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5326 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5327 emit_int8((unsigned char)0xB8);
5328 emit_operand(dst, src2);
5329 }
5330
5331 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5332 assert(VM_Version::supports_fma(), "");
5333 InstructionMark im(this);
5334 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5335 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5336 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5337 emit_int8((unsigned char)0xB8);
5338 emit_operand(dst, src2);
5339 }
5340
5341 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5342 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5343 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5344 attributes.set_rex_vex_w_reverted();
5345 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5346 emit_int8(0x5E);
5347 emit_int8((unsigned char)(0xC0 | encode));
5348 }
5349
5350 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5351 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5352 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5353 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5354 emit_int8(0x5E);
5355 emit_int8((unsigned char)(0xC0 | encode));
5356 }
5357
5358 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5359 assert(VM_Version::supports_avx(), "");
5360 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5361 attributes.set_rex_vex_w_reverted();
5362 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5363 emit_int8(0x5E);
5364 emit_int8((unsigned char)(0xC0 | encode));
5365 }
5366
5367 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5368 assert(VM_Version::supports_avx(), "");
5369 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5370 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5371 emit_int8(0x5E);
5372 emit_int8((unsigned char)(0xC0 | encode));
5373 }
5374
5375 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5376 assert(VM_Version::supports_avx(), "");
5377 InstructionMark im(this);
5378 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5379 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5380 attributes.set_rex_vex_w_reverted();
5381 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382 emit_int8(0x5E);
5383 emit_operand(dst, src);
5384 }
5385
5386 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5387 assert(VM_Version::supports_avx(), "");
5388 InstructionMark im(this);
5389 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5390 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5391 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5392 emit_int8(0x5E);
5393 emit_operand(dst, src);
5394 }
5395
5396 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5397 assert(VM_Version::supports_avx(), "");
5398 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5399 attributes.set_rex_vex_w_reverted();
5400 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5401 emit_int8(0x51);
5402 emit_int8((unsigned char)(0xC0 | encode));
5403 }
5404
5405 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5406 assert(VM_Version::supports_avx(), "");
5407 InstructionMark im(this);
5408 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5409 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5410 attributes.set_rex_vex_w_reverted();
5411 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5412 emit_int8(0x51);
5413 emit_operand(dst, src);
5414 }
5415
5416 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5417 assert(VM_Version::supports_avx(), "");
5418 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5419 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5420 emit_int8(0x51);
5421 emit_int8((unsigned char)(0xC0 | encode));
5422 }
5423
5424 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5425 assert(VM_Version::supports_avx(), "");
5426 InstructionMark im(this);
5427 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5428 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5429 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5430 emit_int8(0x51);
5431 emit_operand(dst, src);
5432 }
5433
5434 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5436 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5437 attributes.set_rex_vex_w_reverted();
5438 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5439 emit_int8(0x54);
5440 emit_int8((unsigned char)(0xC0 | encode));
5441 }
5442
5443 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5444 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5446 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5447 emit_int8(0x54);
5448 emit_int8((unsigned char)(0xC0 | encode));
5449 }
5450
5451 void Assembler::andps(XMMRegister dst, Address src) {
5452 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5453 InstructionMark im(this);
5454 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5455 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5456 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5457 emit_int8(0x54);
5458 emit_operand(dst, src);
5459 }
5460
5461 void Assembler::andpd(XMMRegister dst, Address src) {
5462 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5463 InstructionMark im(this);
5464 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5465 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5466 attributes.set_rex_vex_w_reverted();
5467 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5468 emit_int8(0x54);
5469 emit_operand(dst, src);
5470 }
5471
5472 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5473 assert(VM_Version::supports_avx(), "");
5474 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5475 attributes.set_rex_vex_w_reverted();
5476 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5477 emit_int8(0x54);
5478 emit_int8((unsigned char)(0xC0 | encode));
5479 }
5480
5481 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5482 assert(VM_Version::supports_avx(), "");
5483 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5484 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5485 emit_int8(0x54);
5486 emit_int8((unsigned char)(0xC0 | encode));
5487 }
5488
5489 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5490 assert(VM_Version::supports_avx(), "");
5491 InstructionMark im(this);
5492 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5493 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5494 attributes.set_rex_vex_w_reverted();
5495 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5496 emit_int8(0x54);
5497 emit_operand(dst, src);
5498 }
5499
5500 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5501 assert(VM_Version::supports_avx(), "");
5502 InstructionMark im(this);
5503 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5504 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5505 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5506 emit_int8(0x54);
5507 emit_operand(dst, src);
5508 }
5509
5510 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5511 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5512 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5513 attributes.set_rex_vex_w_reverted();
5514 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5515 emit_int8(0x15);
5516 emit_int8((unsigned char)(0xC0 | encode));
5517 }
5518
5519 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5521 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5522 attributes.set_rex_vex_w_reverted();
5523 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5524 emit_int8(0x14);
5525 emit_int8((unsigned char)(0xC0 | encode));
5526 }
5527
5528 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5529 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5530 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5531 attributes.set_rex_vex_w_reverted();
5532 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5533 emit_int8(0x57);
5534 emit_int8((unsigned char)(0xC0 | encode));
5535 }
5536
5537 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5538 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5540 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5541 emit_int8(0x57);
5542 emit_int8((unsigned char)(0xC0 | encode));
5543 }
5544
5545 void Assembler::xorpd(XMMRegister dst, Address src) {
5546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5547 InstructionMark im(this);
5548 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5549 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5550 attributes.set_rex_vex_w_reverted();
5551 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5552 emit_int8(0x57);
5553 emit_operand(dst, src);
5554 }
5555
5556 void Assembler::xorps(XMMRegister dst, Address src) {
5557 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5558 InstructionMark im(this);
5559 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5560 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5561 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5562 emit_int8(0x57);
5563 emit_operand(dst, src);
5564 }
5565
5566 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5567 assert(VM_Version::supports_avx(), "");
5568 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5569 attributes.set_rex_vex_w_reverted();
5570 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5571 emit_int8(0x57);
5572 emit_int8((unsigned char)(0xC0 | encode));
5573 }
5574
5575 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5576 assert(VM_Version::supports_avx(), "");
5577 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5578 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5579 emit_int8(0x57);
5580 emit_int8((unsigned char)(0xC0 | encode));
5581 }
5582
5583 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5584 assert(VM_Version::supports_avx(), "");
5585 InstructionMark im(this);
5586 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5587 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5588 attributes.set_rex_vex_w_reverted();
5589 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5590 emit_int8(0x57);
5591 emit_operand(dst, src);
5592 }
5593
5594 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5595 assert(VM_Version::supports_avx(), "");
5596 InstructionMark im(this);
5597 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5598 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5599 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5600 emit_int8(0x57);
5601 emit_operand(dst, src);
5602 }
5603
5604 // Integer vector arithmetic
5605 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5606 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5607 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5608 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5609 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5610 emit_int8(0x01);
5611 emit_int8((unsigned char)(0xC0 | encode));
5612 }
5613
5614 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5615 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5616 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5617 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5618 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5619 emit_int8(0x02);
5620 emit_int8((unsigned char)(0xC0 | encode));
5621 }
5622
5623 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5624 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5625 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5626 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5627 emit_int8((unsigned char)0xFC);
5628 emit_int8((unsigned char)(0xC0 | encode));
5629 }
5630
5631 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5632 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5633 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5634 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5635 emit_int8((unsigned char)0xFD);
5636 emit_int8((unsigned char)(0xC0 | encode));
5637 }
5638
5639 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5641 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5642 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5643 emit_int8((unsigned char)0xFE);
5644 emit_int8((unsigned char)(0xC0 | encode));
5645 }
5646
5647 void Assembler::paddd(XMMRegister dst, Address src) {
5648 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5649 InstructionMark im(this);
5650 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5651 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5652 emit_int8((unsigned char)0xFE);
5653 emit_operand(dst, src);
5654 }
5655
5656 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5658 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5659 attributes.set_rex_vex_w_reverted();
5660 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5661 emit_int8((unsigned char)0xD4);
5662 emit_int8((unsigned char)(0xC0 | encode));
5663 }
5664
5665 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5666 assert(VM_Version::supports_sse3(), "");
5667 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5668 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5669 emit_int8(0x01);
5670 emit_int8((unsigned char)(0xC0 | encode));
5671 }
5672
5673 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5674 assert(VM_Version::supports_sse3(), "");
5675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5676 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5677 emit_int8(0x02);
5678 emit_int8((unsigned char)(0xC0 | encode));
5679 }
5680
5681 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5682 assert(UseAVX > 0, "requires some form of AVX");
5683 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5684 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5685 emit_int8((unsigned char)0xFC);
5686 emit_int8((unsigned char)(0xC0 | encode));
5687 }
5688
5689 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5690 assert(UseAVX > 0, "requires some form of AVX");
5691 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5692 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5693 emit_int8((unsigned char)0xFD);
5694 emit_int8((unsigned char)(0xC0 | encode));
5695 }
5696
5697 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5698 assert(UseAVX > 0, "requires some form of AVX");
5699 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5700 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5701 emit_int8((unsigned char)0xFE);
5702 emit_int8((unsigned char)(0xC0 | encode));
5703 }
5704
5705 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5706 assert(UseAVX > 0, "requires some form of AVX");
5707 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5708 attributes.set_rex_vex_w_reverted();
5709 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5710 emit_int8((unsigned char)0xD4);
5711 emit_int8((unsigned char)(0xC0 | encode));
5712 }
5713
5714 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5715 assert(UseAVX > 0, "requires some form of AVX");
5716 InstructionMark im(this);
5717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5718 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5719 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5720 emit_int8((unsigned char)0xFC);
5721 emit_operand(dst, src);
5722 }
5723
5724 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5725 assert(UseAVX > 0, "requires some form of AVX");
5726 InstructionMark im(this);
5727 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5728 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5729 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5730 emit_int8((unsigned char)0xFD);
5731 emit_operand(dst, src);
5732 }
5733
5734 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5735 assert(UseAVX > 0, "requires some form of AVX");
5736 InstructionMark im(this);
5737 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5738 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5739 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5740 emit_int8((unsigned char)0xFE);
5741 emit_operand(dst, src);
5742 }
5743
5744 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5745 assert(UseAVX > 0, "requires some form of AVX");
5746 InstructionMark im(this);
5747 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5748 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5749 attributes.set_rex_vex_w_reverted();
5750 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5751 emit_int8((unsigned char)0xD4);
5752 emit_operand(dst, src);
5753 }
5754
5755 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5757 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5759 emit_int8((unsigned char)0xF8);
5760 emit_int8((unsigned char)(0xC0 | encode));
5761 }
5762
5763 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5764 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5765 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5766 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5767 emit_int8((unsigned char)0xF9);
5768 emit_int8((unsigned char)(0xC0 | encode));
5769 }
5770
5771 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5772 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5773 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5774 emit_int8((unsigned char)0xFA);
5775 emit_int8((unsigned char)(0xC0 | encode));
5776 }
5777
5778 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5780 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5781 attributes.set_rex_vex_w_reverted();
5782 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5783 emit_int8((unsigned char)0xFB);
5784 emit_int8((unsigned char)(0xC0 | encode));
5785 }
5786
5787 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5788 assert(UseAVX > 0, "requires some form of AVX");
5789 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5790 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5791 emit_int8((unsigned char)0xF8);
5792 emit_int8((unsigned char)(0xC0 | encode));
5793 }
5794
5795 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5796 assert(UseAVX > 0, "requires some form of AVX");
5797 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5798 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5799 emit_int8((unsigned char)0xF9);
5800 emit_int8((unsigned char)(0xC0 | encode));
5801 }
5802
5803 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5804 assert(UseAVX > 0, "requires some form of AVX");
5805 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5806 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5807 emit_int8((unsigned char)0xFA);
5808 emit_int8((unsigned char)(0xC0 | encode));
5809 }
5810
5811 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5812 assert(UseAVX > 0, "requires some form of AVX");
5813 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5814 attributes.set_rex_vex_w_reverted();
5815 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5816 emit_int8((unsigned char)0xFB);
5817 emit_int8((unsigned char)(0xC0 | encode));
5818 }
5819
5820 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5821 assert(UseAVX > 0, "requires some form of AVX");
5822 InstructionMark im(this);
5823 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5824 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5825 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5826 emit_int8((unsigned char)0xF8);
5827 emit_operand(dst, src);
5828 }
5829
5830 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5831 assert(UseAVX > 0, "requires some form of AVX");
5832 InstructionMark im(this);
5833 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5834 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5835 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5836 emit_int8((unsigned char)0xF9);
5837 emit_operand(dst, src);
5838 }
5839
5840 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5841 assert(UseAVX > 0, "requires some form of AVX");
5842 InstructionMark im(this);
5843 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5844 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5845 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5846 emit_int8((unsigned char)0xFA);
5847 emit_operand(dst, src);
5848 }
5849
5850 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5851 assert(UseAVX > 0, "requires some form of AVX");
5852 InstructionMark im(this);
5853 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5854 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5855 attributes.set_rex_vex_w_reverted();
5856 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5857 emit_int8((unsigned char)0xFB);
5858 emit_operand(dst, src);
5859 }
5860
5861 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5863 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5865 emit_int8((unsigned char)0xD5);
5866 emit_int8((unsigned char)(0xC0 | encode));
5867 }
5868
5869 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5870 assert(VM_Version::supports_sse4_1(), "");
5871 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5872 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5873 emit_int8(0x40);
5874 emit_int8((unsigned char)(0xC0 | encode));
5875 }
5876
5877 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5878 assert(UseAVX > 0, "requires some form of AVX");
5879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5880 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5881 emit_int8((unsigned char)0xD5);
5882 emit_int8((unsigned char)(0xC0 | encode));
5883 }
5884
5885 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5886 assert(UseAVX > 0, "requires some form of AVX");
5887 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5888 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5889 emit_int8(0x40);
5890 emit_int8((unsigned char)(0xC0 | encode));
5891 }
5892
5893 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5894 assert(UseAVX > 2, "requires some form of EVEX");
5895 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5896 attributes.set_is_evex_instruction();
5897 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5898 emit_int8(0x40);
5899 emit_int8((unsigned char)(0xC0 | encode));
5900 }
5901
5902 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5903 assert(UseAVX > 0, "requires some form of AVX");
5904 InstructionMark im(this);
5905 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5906 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5907 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5908 emit_int8((unsigned char)0xD5);
5909 emit_operand(dst, src);
5910 }
5911
5912 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5913 assert(UseAVX > 0, "requires some form of AVX");
5914 InstructionMark im(this);
5915 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5916 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5917 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5918 emit_int8(0x40);
5919 emit_operand(dst, src);
5920 }
5921
5922 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5923 assert(UseAVX > 2, "requires some form of EVEX");
5924 InstructionMark im(this);
5925 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5926 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5927 attributes.set_is_evex_instruction();
5928 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5929 emit_int8(0x40);
5930 emit_operand(dst, src);
5931 }
5932
5933 // Shift packed integers left by specified number of bits.
5934 void Assembler::psllw(XMMRegister dst, int shift) {
5935 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5936 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5937 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5938 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5939 emit_int8(0x71);
5940 emit_int8((unsigned char)(0xC0 | encode));
5941 emit_int8(shift & 0xFF);
5942 }
5943
5944 void Assembler::pslld(XMMRegister dst, int shift) {
5945 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5946 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5947 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5948 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5949 emit_int8(0x72);
5950 emit_int8((unsigned char)(0xC0 | encode));
5951 emit_int8(shift & 0xFF);
5952 }
5953
5954 void Assembler::psllq(XMMRegister dst, int shift) {
5955 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5956 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5957 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5958 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5959 emit_int8(0x73);
5960 emit_int8((unsigned char)(0xC0 | encode));
5961 emit_int8(shift & 0xFF);
5962 }
5963
5964 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5965 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5966 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5967 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5968 emit_int8((unsigned char)0xF1);
5969 emit_int8((unsigned char)(0xC0 | encode));
5970 }
5971
5972 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5973 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5974 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5975 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5976 emit_int8((unsigned char)0xF2);
5977 emit_int8((unsigned char)(0xC0 | encode));
5978 }
5979
5980 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5981 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5982 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5983 attributes.set_rex_vex_w_reverted();
5984 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5985 emit_int8((unsigned char)0xF3);
5986 emit_int8((unsigned char)(0xC0 | encode));
5987 }
5988
5989 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5990 assert(UseAVX > 0, "requires some form of AVX");
5991 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5992 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5993 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5994 emit_int8(0x71);
5995 emit_int8((unsigned char)(0xC0 | encode));
5996 emit_int8(shift & 0xFF);
5997 }
5998
5999 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6000 assert(UseAVX > 0, "requires some form of AVX");
6001 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6002 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6003 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6004 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6005 emit_int8(0x72);
6006 emit_int8((unsigned char)(0xC0 | encode));
6007 emit_int8(shift & 0xFF);
6008 }
6009
6010 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6011 assert(UseAVX > 0, "requires some form of AVX");
6012 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6013 attributes.set_rex_vex_w_reverted();
6014 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6015 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6016 emit_int8(0x73);
6017 emit_int8((unsigned char)(0xC0 | encode));
6018 emit_int8(shift & 0xFF);
6019 }
6020
6021 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6022 assert(UseAVX > 0, "requires some form of AVX");
6023 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6024 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6025 emit_int8((unsigned char)0xF1);
6026 emit_int8((unsigned char)(0xC0 | encode));
6027 }
6028
6029 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6030 assert(UseAVX > 0, "requires some form of AVX");
6031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6032 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6033 emit_int8((unsigned char)0xF2);
6034 emit_int8((unsigned char)(0xC0 | encode));
6035 }
6036
6037 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6038 assert(UseAVX > 0, "requires some form of AVX");
6039 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6040 attributes.set_rex_vex_w_reverted();
6041 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6042 emit_int8((unsigned char)0xF3);
6043 emit_int8((unsigned char)(0xC0 | encode));
6044 }
6045
6046 // Shift packed integers logically right by specified number of bits.
6047 void Assembler::psrlw(XMMRegister dst, int shift) {
6048 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6049 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6050 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6051 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6052 emit_int8(0x71);
6053 emit_int8((unsigned char)(0xC0 | encode));
6054 emit_int8(shift & 0xFF);
6055 }
6056
6057 void Assembler::psrld(XMMRegister dst, int shift) {
6058 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6059 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6060 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6061 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6062 emit_int8(0x72);
6063 emit_int8((unsigned char)(0xC0 | encode));
6064 emit_int8(shift & 0xFF);
6065 }
6066
6067 void Assembler::psrlq(XMMRegister dst, int shift) {
6068 // Do not confuse it with psrldq SSE2 instruction which
6069 // shifts 128 bit value in xmm register by number of bytes.
6070 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6071 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6072 attributes.set_rex_vex_w_reverted();
6073 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6074 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6075 emit_int8(0x73);
6076 emit_int8((unsigned char)(0xC0 | encode));
6077 emit_int8(shift & 0xFF);
6078 }
6079
6080 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6081 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6082 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6083 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6084 emit_int8((unsigned char)0xD1);
6085 emit_int8((unsigned char)(0xC0 | encode));
6086 }
6087
6088 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6089 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6090 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6091 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6092 emit_int8((unsigned char)0xD2);
6093 emit_int8((unsigned char)(0xC0 | encode));
6094 }
6095
6096 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6098 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6099 attributes.set_rex_vex_w_reverted();
6100 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6101 emit_int8((unsigned char)0xD3);
6102 emit_int8((unsigned char)(0xC0 | encode));
6103 }
6104
6105 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6106 assert(UseAVX > 0, "requires some form of AVX");
6107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6108 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6109 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6110 emit_int8(0x71);
6111 emit_int8((unsigned char)(0xC0 | encode));
6112 emit_int8(shift & 0xFF);
6113 }
6114
6115 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6116 assert(UseAVX > 0, "requires some form of AVX");
6117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6118 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6119 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6120 emit_int8(0x72);
6121 emit_int8((unsigned char)(0xC0 | encode));
6122 emit_int8(shift & 0xFF);
6123 }
6124
6125 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6126 assert(UseAVX > 0, "requires some form of AVX");
6127 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6128 attributes.set_rex_vex_w_reverted();
6129 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6130 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6131 emit_int8(0x73);
6132 emit_int8((unsigned char)(0xC0 | encode));
6133 emit_int8(shift & 0xFF);
6134 }
6135
6136 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6137 assert(UseAVX > 0, "requires some form of AVX");
6138 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6139 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6140 emit_int8((unsigned char)0xD1);
6141 emit_int8((unsigned char)(0xC0 | encode));
6142 }
6143
6144 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6145 assert(UseAVX > 0, "requires some form of AVX");
6146 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6147 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6148 emit_int8((unsigned char)0xD2);
6149 emit_int8((unsigned char)(0xC0 | encode));
6150 }
6151
6152 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6153 assert(UseAVX > 0, "requires some form of AVX");
6154 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6155 attributes.set_rex_vex_w_reverted();
6156 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6157 emit_int8((unsigned char)0xD3);
6158 emit_int8((unsigned char)(0xC0 | encode));
6159 }
6160
6161 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6162 assert(VM_Version::supports_avx512bw(), "");
6163 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6164 attributes.set_is_evex_instruction();
6165 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6166 emit_int8(0x10);
6167 emit_int8((unsigned char)(0xC0 | encode));
6168 }
6169
6170 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6171 assert(VM_Version::supports_avx512bw(), "");
6172 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6173 attributes.set_is_evex_instruction();
6174 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6175 emit_int8(0x12);
6176 emit_int8((unsigned char)(0xC0 | encode));
6177 }
6178
6179 // Shift packed integers arithmetically right by specified number of bits.
6180 void Assembler::psraw(XMMRegister dst, int shift) {
6181 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6183 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6184 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6185 emit_int8(0x71);
6186 emit_int8((unsigned char)(0xC0 | encode));
6187 emit_int8(shift & 0xFF);
6188 }
6189
6190 void Assembler::psrad(XMMRegister dst, int shift) {
6191 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6192 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6193 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6194 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6195 emit_int8(0x72);
6196 emit_int8((unsigned char)(0xC0 | encode));
6197 emit_int8(shift & 0xFF);
6198 }
6199
6200 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6202 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6203 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6204 emit_int8((unsigned char)0xE1);
6205 emit_int8((unsigned char)(0xC0 | encode));
6206 }
6207
6208 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6209 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6211 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6212 emit_int8((unsigned char)0xE2);
6213 emit_int8((unsigned char)(0xC0 | encode));
6214 }
6215
6216 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6217 assert(UseAVX > 0, "requires some form of AVX");
6218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6219 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6220 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6221 emit_int8(0x71);
6222 emit_int8((unsigned char)(0xC0 | encode));
6223 emit_int8(shift & 0xFF);
6224 }
6225
6226 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6227 assert(UseAVX > 0, "requires some form of AVX");
6228 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6229 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6230 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6231 emit_int8(0x72);
6232 emit_int8((unsigned char)(0xC0 | encode));
6233 emit_int8(shift & 0xFF);
6234 }
6235
6236 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6237 assert(UseAVX > 0, "requires some form of AVX");
6238 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6239 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6240 emit_int8((unsigned char)0xE1);
6241 emit_int8((unsigned char)(0xC0 | encode));
6242 }
6243
6244 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6245 assert(UseAVX > 0, "requires some form of AVX");
6246 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6247 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6248 emit_int8((unsigned char)0xE2);
6249 emit_int8((unsigned char)(0xC0 | encode));
6250 }
6251
6252
6253 // logical operations packed integers
6254 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6255 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6256 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6257 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6258 emit_int8((unsigned char)0xDB);
6259 emit_int8((unsigned char)(0xC0 | encode));
6260 }
6261
6262 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6263 assert(UseAVX > 0, "requires some form of AVX");
6264 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6265 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6266 emit_int8((unsigned char)0xDB);
6267 emit_int8((unsigned char)(0xC0 | encode));
6268 }
6269
6270 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6271 assert(UseAVX > 0, "requires some form of AVX");
6272 InstructionMark im(this);
6273 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6274 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6275 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6276 emit_int8((unsigned char)0xDB);
6277 emit_operand(dst, src);
6278 }
6279
6280 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6281 assert(VM_Version::supports_evex(), "");
6282 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6283 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6284 emit_int8((unsigned char)0xDB);
6285 emit_int8((unsigned char)(0xC0 | encode));
6286 }
6287
6288
6289 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6291 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6292 attributes.set_rex_vex_w_reverted();
6293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6294 emit_int8((unsigned char)0xDF);
6295 emit_int8((unsigned char)(0xC0 | encode));
6296 }
6297
6298 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6299 assert(UseAVX > 0, "requires some form of AVX");
6300 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6301 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6302 emit_int8((unsigned char)0xDF);
6303 emit_int8((unsigned char)(0xC0 | encode));
6304 }
6305
6306
6307 void Assembler::por(XMMRegister dst, XMMRegister src) {
6308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6309 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6310 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6311 emit_int8((unsigned char)0xEB);
6312 emit_int8((unsigned char)(0xC0 | encode));
6313 }
6314
6315 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6316 assert(UseAVX > 0, "requires some form of AVX");
6317 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6318 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6319 emit_int8((unsigned char)0xEB);
6320 emit_int8((unsigned char)(0xC0 | encode));
6321 }
6322
6323 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6324 assert(UseAVX > 0, "requires some form of AVX");
6325 InstructionMark im(this);
6326 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6327 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6328 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6329 emit_int8((unsigned char)0xEB);
6330 emit_operand(dst, src);
6331 }
6332
6333 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6334 assert(VM_Version::supports_evex(), "");
6335 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6336 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6337 emit_int8((unsigned char)0xEB);
6338 emit_int8((unsigned char)(0xC0 | encode));
6339 }
6340
6341
6342 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6345 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6346 emit_int8((unsigned char)0xEF);
6347 emit_int8((unsigned char)(0xC0 | encode));
6348 }
6349
6350 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6351 assert(UseAVX > 0, "requires some form of AVX");
6352 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6353 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6354 emit_int8((unsigned char)0xEF);
6355 emit_int8((unsigned char)(0xC0 | encode));
6356 }
6357
6358 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6359 assert(UseAVX > 0, "requires some form of AVX");
6360 InstructionMark im(this);
6361 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6362 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6363 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6364 emit_int8((unsigned char)0xEF);
6365 emit_operand(dst, src);
6366 }
6367
6368 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6369 assert(VM_Version::supports_evex(), "requires EVEX support");
6370 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6371 attributes.set_is_evex_instruction();
6372 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6373 emit_int8((unsigned char)0xEF);
6374 emit_int8((unsigned char)(0xC0 | encode));
6375 }
6376
6377 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6378 assert(VM_Version::supports_evex(), "requires EVEX support");
6379 assert(dst != xnoreg, "sanity");
6380 InstructionMark im(this);
6381 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6382 attributes.set_is_evex_instruction();
6383 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6384 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6385 emit_int8((unsigned char)0xEF);
6386 emit_operand(dst, src);
6387 }
6388
6389
6390 // vinserti forms
6391
6392 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6393 assert(VM_Version::supports_avx2(), "");
6394 assert(imm8 <= 0x01, "imm8: %u", imm8);
6395 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6396 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6397 emit_int8(0x38);
6398 emit_int8((unsigned char)(0xC0 | encode));
6399 // 0x00 - insert into lower 128 bits
6400 // 0x01 - insert into upper 128 bits
6401 emit_int8(imm8 & 0x01);
6402 }
6403
6404 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6405 assert(VM_Version::supports_avx2(), "");
6406 assert(dst != xnoreg, "sanity");
6407 assert(imm8 <= 0x01, "imm8: %u", imm8);
6408 InstructionMark im(this);
6409 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6410 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6411 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6412 emit_int8(0x38);
6413 emit_operand(dst, src);
6414 // 0x00 - insert into lower 128 bits
6415 // 0x01 - insert into upper 128 bits
6416 emit_int8(imm8 & 0x01);
6417 }
6418
6419 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6420 assert(VM_Version::supports_evex(), "");
6421 assert(imm8 <= 0x03, "imm8: %u", imm8);
6422 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6423 attributes.set_is_evex_instruction();
6424 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6425 emit_int8(0x38);
6426 emit_int8((unsigned char)(0xC0 | encode));
6427 // 0x00 - insert into q0 128 bits (0..127)
6428 // 0x01 - insert into q1 128 bits (128..255)
6429 // 0x02 - insert into q2 128 bits (256..383)
6430 // 0x03 - insert into q3 128 bits (384..511)
6431 emit_int8(imm8 & 0x03);
6432 }
6433
6434 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6435 assert(VM_Version::supports_avx(), "");
6436 assert(dst != xnoreg, "sanity");
6437 assert(imm8 <= 0x03, "imm8: %u", imm8);
6438 InstructionMark im(this);
6439 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6440 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6441 attributes.set_is_evex_instruction();
6442 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6443 emit_int8(0x18);
6444 emit_operand(dst, src);
6445 // 0x00 - insert into q0 128 bits (0..127)
6446 // 0x01 - insert into q1 128 bits (128..255)
6447 // 0x02 - insert into q2 128 bits (256..383)
6448 // 0x03 - insert into q3 128 bits (384..511)
6449 emit_int8(imm8 & 0x03);
6450 }
6451
6452 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6453 assert(VM_Version::supports_evex(), "");
6454 assert(imm8 <= 0x01, "imm8: %u", imm8);
6455 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6456 attributes.set_is_evex_instruction();
6457 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6458 emit_int8(0x3A);
6459 emit_int8((unsigned char)(0xC0 | encode));
6460 // 0x00 - insert into lower 256 bits
6461 // 0x01 - insert into upper 256 bits
6462 emit_int8(imm8 & 0x01);
6463 }
6464
6465
6466 // vinsertf forms
6467
6468 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6469 assert(VM_Version::supports_avx(), "");
6470 assert(imm8 <= 0x01, "imm8: %u", imm8);
6471 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6473 emit_int8(0x18);
6474 emit_int8((unsigned char)(0xC0 | encode));
6475 // 0x00 - insert into lower 128 bits
6476 // 0x01 - insert into upper 128 bits
6477 emit_int8(imm8 & 0x01);
6478 }
6479
6480 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6481 assert(VM_Version::supports_avx(), "");
6482 assert(dst != xnoreg, "sanity");
6483 assert(imm8 <= 0x01, "imm8: %u", imm8);
6484 InstructionMark im(this);
6485 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6486 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6487 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6488 emit_int8(0x18);
6489 emit_operand(dst, src);
6490 // 0x00 - insert into lower 128 bits
6491 // 0x01 - insert into upper 128 bits
6492 emit_int8(imm8 & 0x01);
6493 }
6494
6495 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6496 assert(VM_Version::supports_avx2(), "");
6497 assert(imm8 <= 0x03, "imm8: %u", imm8);
6498 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6499 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6500 emit_int8(0x18);
6501 emit_int8((unsigned char)(0xC0 | encode));
6502 // 0x00 - insert into q0 128 bits (0..127)
6503 // 0x01 - insert into q1 128 bits (128..255)
6504 // 0x02 - insert into q0 128 bits (256..383)
6505 // 0x03 - insert into q1 128 bits (384..512)
6506 emit_int8(imm8 & 0x03);
6507 }
6508
6509 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6510 assert(VM_Version::supports_avx(), "");
6511 assert(dst != xnoreg, "sanity");
6512 assert(imm8 <= 0x03, "imm8: %u", imm8);
6513 InstructionMark im(this);
6514 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6515 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6516 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6517 emit_int8(0x18);
6518 emit_operand(dst, src);
6519 // 0x00 - insert into q0 128 bits (0..127)
6520 // 0x01 - insert into q1 128 bits (128..255)
6521 // 0x02 - insert into q0 128 bits (256..383)
6522 // 0x03 - insert into q1 128 bits (384..512)
6523 emit_int8(imm8 & 0x03);
6524 }
6525
6526 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6527 assert(VM_Version::supports_evex(), "");
6528 assert(imm8 <= 0x01, "imm8: %u", imm8);
6529 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6530 attributes.set_is_evex_instruction();
6531 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6532 emit_int8(0x1A);
6533 emit_int8((unsigned char)(0xC0 | encode));
6534 // 0x00 - insert into lower 256 bits
6535 // 0x01 - insert into upper 256 bits
6536 emit_int8(imm8 & 0x01);
6537 }
6538
6539 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6540 assert(VM_Version::supports_evex(), "");
6541 assert(dst != xnoreg, "sanity");
6542 assert(imm8 <= 0x01, "imm8: %u", imm8);
6543 InstructionMark im(this);
6544 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6545 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6546 attributes.set_is_evex_instruction();
6547 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6548 emit_int8(0x1A);
6549 emit_operand(dst, src);
6550 // 0x00 - insert into lower 256 bits
6551 // 0x01 - insert into upper 256 bits
6552 emit_int8(imm8 & 0x01);
6553 }
6554
6555
6556 // vextracti forms
6557
6558 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6559 assert(VM_Version::supports_avx2(), "");
6560 assert(imm8 <= 0x01, "imm8: %u", imm8);
6561 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6562 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6563 emit_int8(0x39);
6564 emit_int8((unsigned char)(0xC0 | encode));
6565 // 0x00 - extract from lower 128 bits
6566 // 0x01 - extract from upper 128 bits
6567 emit_int8(imm8 & 0x01);
6568 }
6569
6570 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6571 assert(VM_Version::supports_avx2(), "");
6572 assert(src != xnoreg, "sanity");
6573 assert(imm8 <= 0x01, "imm8: %u", imm8);
6574 InstructionMark im(this);
6575 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6576 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6577 attributes.reset_is_clear_context();
6578 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6579 emit_int8(0x39);
6580 emit_operand(src, dst);
6581 // 0x00 - extract from lower 128 bits
6582 // 0x01 - extract from upper 128 bits
6583 emit_int8(imm8 & 0x01);
6584 }
6585
6586 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6587 assert(VM_Version::supports_evex(), "");
6588 assert(imm8 <= 0x03, "imm8: %u", imm8);
6589 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6590 attributes.set_is_evex_instruction();
6591 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6592 emit_int8(0x39);
6593 emit_int8((unsigned char)(0xC0 | encode));
6594 // 0x00 - extract from bits 127:0
6595 // 0x01 - extract from bits 255:128
6596 // 0x02 - extract from bits 383:256
6597 // 0x03 - extract from bits 511:384
6598 emit_int8(imm8 & 0x03);
6599 }
6600
6601 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6602 assert(VM_Version::supports_evex(), "");
6603 assert(src != xnoreg, "sanity");
6604 assert(imm8 <= 0x03, "imm8: %u", imm8);
6605 InstructionMark im(this);
6606 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6607 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6608 attributes.reset_is_clear_context();
6609 attributes.set_is_evex_instruction();
6610 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6611 emit_int8(0x39);
6612 emit_operand(src, dst);
6613 // 0x00 - extract from bits 127:0
6614 // 0x01 - extract from bits 255:128
6615 // 0x02 - extract from bits 383:256
6616 // 0x03 - extract from bits 511:384
6617 emit_int8(imm8 & 0x03);
6618 }
6619
6620 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6621 assert(VM_Version::supports_avx512dq(), "");
6622 assert(imm8 <= 0x03, "imm8: %u", imm8);
6623 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6624 attributes.set_is_evex_instruction();
6625 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6626 emit_int8(0x39);
6627 emit_int8((unsigned char)(0xC0 | encode));
6628 // 0x00 - extract from bits 127:0
6629 // 0x01 - extract from bits 255:128
6630 // 0x02 - extract from bits 383:256
6631 // 0x03 - extract from bits 511:384
6632 emit_int8(imm8 & 0x03);
6633 }
6634
6635 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6636 assert(VM_Version::supports_evex(), "");
6637 assert(imm8 <= 0x01, "imm8: %u", imm8);
6638 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6639 attributes.set_is_evex_instruction();
6640 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6641 emit_int8(0x3B);
6642 emit_int8((unsigned char)(0xC0 | encode));
6643 // 0x00 - extract from lower 256 bits
6644 // 0x01 - extract from upper 256 bits
6645 emit_int8(imm8 & 0x01);
6646 }
6647
6648 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
6649 assert(VM_Version::supports_evex(), "");
6650 assert(src != xnoreg, "sanity");
6651 assert(imm8 <= 0x01, "imm8: %u", imm8);
6652 InstructionMark im(this);
6653 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6654 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6655 attributes.reset_is_clear_context();
6656 attributes.set_is_evex_instruction();
6657 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6658 emit_int8(0x38);
6659 emit_operand(src, dst);
6660 // 0x00 - extract from lower 256 bits
6661 // 0x01 - extract from upper 256 bits
6662 emit_int8(imm8 & 0x01);
6663 }
6664 // vextractf forms
6665
6666 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6667 assert(VM_Version::supports_avx(), "");
6668 assert(imm8 <= 0x01, "imm8: %u", imm8);
6669 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6670 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6671 emit_int8(0x19);
6672 emit_int8((unsigned char)(0xC0 | encode));
6673 // 0x00 - extract from lower 128 bits
6674 // 0x01 - extract from upper 128 bits
6675 emit_int8(imm8 & 0x01);
6676 }
6677
6678 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6679 assert(VM_Version::supports_avx(), "");
6680 assert(src != xnoreg, "sanity");
6681 assert(imm8 <= 0x01, "imm8: %u", imm8);
6682 InstructionMark im(this);
6683 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6684 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6685 attributes.reset_is_clear_context();
6686 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6687 emit_int8(0x19);
6688 emit_operand(src, dst);
6689 // 0x00 - extract from lower 128 bits
6690 // 0x01 - extract from upper 128 bits
6691 emit_int8(imm8 & 0x01);
6692 }
6693
6694 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6695 assert(VM_Version::supports_evex(), "");
6696 assert(imm8 <= 0x03, "imm8: %u", imm8);
6697 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6698 attributes.set_is_evex_instruction();
6699 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6700 emit_int8(0x19);
6701 emit_int8((unsigned char)(0xC0 | encode));
6702 // 0x00 - extract from bits 127:0
6703 // 0x01 - extract from bits 255:128
6704 // 0x02 - extract from bits 383:256
6705 // 0x03 - extract from bits 511:384
6706 emit_int8(imm8 & 0x03);
6707 }
6708
6709 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6710 assert(VM_Version::supports_evex(), "");
6711 assert(src != xnoreg, "sanity");
6712 assert(imm8 <= 0x03, "imm8: %u", imm8);
6713 InstructionMark im(this);
6714 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6715 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6716 attributes.reset_is_clear_context();
6717 attributes.set_is_evex_instruction();
6718 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6719 emit_int8(0x19);
6720 emit_operand(src, dst);
6721 // 0x00 - extract from bits 127:0
6722 // 0x01 - extract from bits 255:128
6723 // 0x02 - extract from bits 383:256
6724 // 0x03 - extract from bits 511:384
6725 emit_int8(imm8 & 0x03);
6726 }
6727
6728 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6729 assert(VM_Version::supports_avx512dq(), "");
6730 assert(imm8 <= 0x03, "imm8: %u", imm8);
6731 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6732 attributes.set_is_evex_instruction();
6733 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6734 emit_int8(0x19);
6735 emit_int8((unsigned char)(0xC0 | encode));
6736 // 0x00 - extract from bits 127:0
6737 // 0x01 - extract from bits 255:128
6738 // 0x02 - extract from bits 383:256
6739 // 0x03 - extract from bits 511:384
6740 emit_int8(imm8 & 0x03);
6741 }
6742
6743 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6744 assert(VM_Version::supports_evex(), "");
6745 assert(imm8 <= 0x01, "imm8: %u", imm8);
6746 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6747 attributes.set_is_evex_instruction();
6748 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6749 emit_int8(0x1B);
6750 emit_int8((unsigned char)(0xC0 | encode));
6751 // 0x00 - extract from lower 256 bits
6752 // 0x01 - extract from upper 256 bits
6753 emit_int8(imm8 & 0x01);
6754 }
6755
6756 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6757 assert(VM_Version::supports_evex(), "");
6758 assert(src != xnoreg, "sanity");
6759 assert(imm8 <= 0x01, "imm8: %u", imm8);
6760 InstructionMark im(this);
6761 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6762 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6763 attributes.reset_is_clear_context();
6764 attributes.set_is_evex_instruction();
6765 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6766 emit_int8(0x1B);
6767 emit_operand(src, dst);
6768 // 0x00 - extract from lower 256 bits
6769 // 0x01 - extract from upper 256 bits
6770 emit_int8(imm8 & 0x01);
6771 }
6772
6773 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6774 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6775 assert(VM_Version::supports_avx2(), "");
6776 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6777 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6778 emit_int8(0x78);
6779 emit_int8((unsigned char)(0xC0 | encode));
6780 }
6781
6782 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6783 assert(VM_Version::supports_avx2(), "");
6784 assert(dst != xnoreg, "sanity");
6785 InstructionMark im(this);
6786 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6788 // swap src<->dst for encoding
6789 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6790 emit_int8(0x78);
6791 emit_operand(dst, src);
6792 }
6793
6794 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6795 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6796 assert(VM_Version::supports_avx2(), "");
6797 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6798 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6799 emit_int8(0x79);
6800 emit_int8((unsigned char)(0xC0 | encode));
6801 }
6802
6803 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6804 assert(VM_Version::supports_avx2(), "");
6805 assert(dst != xnoreg, "sanity");
6806 InstructionMark im(this);
6807 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6808 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6809 // swap src<->dst for encoding
6810 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6811 emit_int8(0x79);
6812 emit_operand(dst, src);
6813 }
6814
6815 // xmm/mem sourced byte/word/dword/qword replicate
6816
6817 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6818 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6819 assert(UseAVX >= 2, "");
6820 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6821 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6822 emit_int8(0x58);
6823 emit_int8((unsigned char)(0xC0 | encode));
6824 }
6825
6826 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6827 assert(VM_Version::supports_avx2(), "");
6828 assert(dst != xnoreg, "sanity");
6829 InstructionMark im(this);
6830 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6831 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6832 // swap src<->dst for encoding
6833 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6834 emit_int8(0x58);
6835 emit_operand(dst, src);
6836 }
6837
6838 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6839 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6840 assert(VM_Version::supports_avx2(), "");
6841 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6842 attributes.set_rex_vex_w_reverted();
6843 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6844 emit_int8(0x59);
6845 emit_int8((unsigned char)(0xC0 | encode));
6846 }
6847
6848 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6849 assert(VM_Version::supports_avx2(), "");
6850 assert(dst != xnoreg, "sanity");
6851 InstructionMark im(this);
6852 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6853 attributes.set_rex_vex_w_reverted();
6854 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6855 // swap src<->dst for encoding
6856 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6857 emit_int8(0x59);
6858 emit_operand(dst, src);
6859 }
6860 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6861 assert(vector_len != Assembler::AVX_128bit, "");
6862 assert(VM_Version::supports_avx512dq(), "");
6863 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6864 attributes.set_rex_vex_w_reverted();
6865 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6866 emit_int8(0x5A);
6867 emit_int8((unsigned char)(0xC0 | encode));
6868 }
6869
6870 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
6871 assert(vector_len != Assembler::AVX_128bit, "");
6872 assert(VM_Version::supports_avx512dq(), "");
6873 assert(dst != xnoreg, "sanity");
6874 InstructionMark im(this);
6875 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6876 attributes.set_rex_vex_w_reverted();
6877 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
6878 // swap src<->dst for encoding
6879 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6880 emit_int8(0x5A);
6881 emit_operand(dst, src);
6882 }
6883
6884 // scalar single/double precision replicate
6885
6886 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6887 void Assembler::vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6888 assert(VM_Version::supports_avx(), "");
6889 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6890 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6891 emit_int8(0x18);
6892 emit_int8((unsigned char)(0xC0 | encode));
6893 }
6894
6895 void Assembler::vpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6896 assert(VM_Version::supports_avx(), "");
6897 assert(dst != xnoreg, "sanity");
6898 InstructionMark im(this);
6899 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6900 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6901 // swap src<->dst for encoding
6902 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6903 emit_int8(0x18);
6904 emit_operand(dst, src);
6905 }
6906
6907 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6908 void Assembler::vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6909 assert(VM_Version::supports_avx(), "");
6910 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6911 attributes.set_rex_vex_w_reverted();
6912 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6913 emit_int8(0x19);
6914 emit_int8((unsigned char)(0xC0 | encode));
6915 }
6916
6917 void Assembler::vpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6918 assert(VM_Version::supports_avx(), "");
6919 assert(dst != xnoreg, "sanity");
6920 InstructionMark im(this);
6921 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6922 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6923 attributes.set_rex_vex_w_reverted();
6924 // swap src<->dst for encoding
6925 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6926 emit_int8(0x19);
6927 emit_operand(dst, src);
6928 }
6929
6930
6931 // gpr source broadcast forms
6932
6933 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6934 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6935 assert(VM_Version::supports_avx512bw(), "");
6936 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6937 attributes.set_is_evex_instruction();
6938 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6939 emit_int8(0x7A);
6940 emit_int8((unsigned char)(0xC0 | encode));
6941 }
6942
6943 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6944 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6945 assert(VM_Version::supports_avx512bw(), "");
6946 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6947 attributes.set_is_evex_instruction();
6948 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6949 emit_int8(0x7B);
6950 emit_int8((unsigned char)(0xC0 | encode));
6951 }
6952
6953 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6954 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6955 assert(VM_Version::supports_evex(), "");
6956 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6957 attributes.set_is_evex_instruction();
6958 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6959 emit_int8(0x7C);
6960 emit_int8((unsigned char)(0xC0 | encode));
6961 }
6962
6963 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6964 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6965 assert(VM_Version::supports_evex(), "");
6966 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6967 attributes.set_is_evex_instruction();
6968 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6969 emit_int8(0x7C);
6970 emit_int8((unsigned char)(0xC0 | encode));
6971 }
6972
6973 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
6974 assert(VM_Version::supports_evex(), "");
6975 assert(dst != xnoreg, "sanity");
6976 InstructionMark im(this);
6977 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6978 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6979 attributes.reset_is_clear_context();
6980 attributes.set_embedded_opmask_register_specifier(mask);
6981 attributes.set_is_evex_instruction();
6982 // swap src<->dst for encoding
6983 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6984 emit_int8((unsigned char)0x90);
6985 emit_operand(dst, src);
6986 }
6987
6988 // Carry-Less Multiplication Quadword
6989 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6990 assert(VM_Version::supports_clmul(), "");
6991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
6992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6993 emit_int8(0x44);
6994 emit_int8((unsigned char)(0xC0 | encode));
6995 emit_int8((unsigned char)mask);
6996 }
6997
6998 // Carry-Less Multiplication Quadword
6999 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
7000 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
7001 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7002 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7003 emit_int8(0x44);
7004 emit_int8((unsigned char)(0xC0 | encode));
7005 emit_int8((unsigned char)mask);
7006 }
7007
7008 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
7009 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
7010 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7011 attributes.set_is_evex_instruction();
7012 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7013 emit_int8(0x44);
7014 emit_int8((unsigned char)(0xC0 | encode));
7015 emit_int8((unsigned char)mask);
7016 }
7017
7018 void Assembler::vzeroupper() {
7019 if (VM_Version::supports_vzeroupper()) {
7020 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7021 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7022 emit_int8(0x77);
7023 }
7024 }
7025
7026 #ifndef _LP64
7027 // 32bit only pieces of the assembler
7028
7029 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7030 // NO PREFIX AS NEVER 64BIT
7031 InstructionMark im(this);
7032 emit_int8((unsigned char)0x81);
7033 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7034 emit_data(imm32, rspec, 0);
7035 }
7036
7037 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7038 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7039 InstructionMark im(this);
7040 emit_int8((unsigned char)0x81);
7041 emit_operand(rdi, src1);
7042 emit_data(imm32, rspec, 0);
7043 }
7044
7045 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7046 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7047 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7048 void Assembler::cmpxchg8(Address adr) {
7049 InstructionMark im(this);
7050 emit_int8(0x0F);
7051 emit_int8((unsigned char)0xC7);
7052 emit_operand(rcx, adr);
7053 }
7054
7055 void Assembler::decl(Register dst) {
7056 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7057 emit_int8(0x48 | dst->encoding());
7058 }
7059
7060 #endif // _LP64
7061
7062 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7063
7064 void Assembler::fabs() {
7065 emit_int8((unsigned char)0xD9);
7066 emit_int8((unsigned char)0xE1);
7067 }
7068
7069 void Assembler::fadd(int i) {
7070 emit_farith(0xD8, 0xC0, i);
7071 }
7072
7073 void Assembler::fadd_d(Address src) {
7074 InstructionMark im(this);
7075 emit_int8((unsigned char)0xDC);
7076 emit_operand32(rax, src);
7077 }
7078
7079 void Assembler::fadd_s(Address src) {
7080 InstructionMark im(this);
7081 emit_int8((unsigned char)0xD8);
7082 emit_operand32(rax, src);
7083 }
7084
7085 void Assembler::fadda(int i) {
7086 emit_farith(0xDC, 0xC0, i);
7087 }
7088
7089 void Assembler::faddp(int i) {
7090 emit_farith(0xDE, 0xC0, i);
7091 }
7092
7093 void Assembler::fchs() {
7094 emit_int8((unsigned char)0xD9);
7095 emit_int8((unsigned char)0xE0);
7096 }
7097
7098 void Assembler::fcom(int i) {
7099 emit_farith(0xD8, 0xD0, i);
7100 }
7101
7102 void Assembler::fcomp(int i) {
7103 emit_farith(0xD8, 0xD8, i);
7104 }
7105
7106 void Assembler::fcomp_d(Address src) {
7107 InstructionMark im(this);
7108 emit_int8((unsigned char)0xDC);
7109 emit_operand32(rbx, src);
7110 }
7111
7112 void Assembler::fcomp_s(Address src) {
7113 InstructionMark im(this);
7114 emit_int8((unsigned char)0xD8);
7115 emit_operand32(rbx, src);
7116 }
7117
7118 void Assembler::fcompp() {
7119 emit_int8((unsigned char)0xDE);
7120 emit_int8((unsigned char)0xD9);
7121 }
7122
7123 void Assembler::fcos() {
7124 emit_int8((unsigned char)0xD9);
7125 emit_int8((unsigned char)0xFF);
7126 }
7127
7128 void Assembler::fdecstp() {
7129 emit_int8((unsigned char)0xD9);
7130 emit_int8((unsigned char)0xF6);
7131 }
7132
7133 void Assembler::fdiv(int i) {
7134 emit_farith(0xD8, 0xF0, i);
7135 }
7136
7137 void Assembler::fdiv_d(Address src) {
7138 InstructionMark im(this);
7139 emit_int8((unsigned char)0xDC);
7140 emit_operand32(rsi, src);
7141 }
7142
7143 void Assembler::fdiv_s(Address src) {
7144 InstructionMark im(this);
7145 emit_int8((unsigned char)0xD8);
7146 emit_operand32(rsi, src);
7147 }
7148
7149 void Assembler::fdiva(int i) {
7150 emit_farith(0xDC, 0xF8, i);
7151 }
7152
7153 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7154 // is erroneous for some of the floating-point instructions below.
7155
7156 void Assembler::fdivp(int i) {
7157 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7158 }
7159
7160 void Assembler::fdivr(int i) {
7161 emit_farith(0xD8, 0xF8, i);
7162 }
7163
7164 void Assembler::fdivr_d(Address src) {
7165 InstructionMark im(this);
7166 emit_int8((unsigned char)0xDC);
7167 emit_operand32(rdi, src);
7168 }
7169
7170 void Assembler::fdivr_s(Address src) {
7171 InstructionMark im(this);
7172 emit_int8((unsigned char)0xD8);
7173 emit_operand32(rdi, src);
7174 }
7175
7176 void Assembler::fdivra(int i) {
7177 emit_farith(0xDC, 0xF0, i);
7178 }
7179
7180 void Assembler::fdivrp(int i) {
7181 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7182 }
7183
7184 void Assembler::ffree(int i) {
7185 emit_farith(0xDD, 0xC0, i);
7186 }
7187
7188 void Assembler::fild_d(Address adr) {
7189 InstructionMark im(this);
7190 emit_int8((unsigned char)0xDF);
7191 emit_operand32(rbp, adr);
7192 }
7193
7194 void Assembler::fild_s(Address adr) {
7195 InstructionMark im(this);
7196 emit_int8((unsigned char)0xDB);
7197 emit_operand32(rax, adr);
7198 }
7199
7200 void Assembler::fincstp() {
7201 emit_int8((unsigned char)0xD9);
7202 emit_int8((unsigned char)0xF7);
7203 }
7204
7205 void Assembler::finit() {
7206 emit_int8((unsigned char)0x9B);
7207 emit_int8((unsigned char)0xDB);
7208 emit_int8((unsigned char)0xE3);
7209 }
7210
7211 void Assembler::fist_s(Address adr) {
7212 InstructionMark im(this);
7213 emit_int8((unsigned char)0xDB);
7214 emit_operand32(rdx, adr);
7215 }
7216
7217 void Assembler::fistp_d(Address adr) {
7218 InstructionMark im(this);
7219 emit_int8((unsigned char)0xDF);
7220 emit_operand32(rdi, adr);
7221 }
7222
7223 void Assembler::fistp_s(Address adr) {
7224 InstructionMark im(this);
7225 emit_int8((unsigned char)0xDB);
7226 emit_operand32(rbx, adr);
7227 }
7228
7229 void Assembler::fld1() {
7230 emit_int8((unsigned char)0xD9);
7231 emit_int8((unsigned char)0xE8);
7232 }
7233
7234 void Assembler::fld_d(Address adr) {
7235 InstructionMark im(this);
7236 emit_int8((unsigned char)0xDD);
7237 emit_operand32(rax, adr);
7238 }
7239
7240 void Assembler::fld_s(Address adr) {
7241 InstructionMark im(this);
7242 emit_int8((unsigned char)0xD9);
7243 emit_operand32(rax, adr);
7244 }
7245
7246
7247 void Assembler::fld_s(int index) {
7248 emit_farith(0xD9, 0xC0, index);
7249 }
7250
7251 void Assembler::fld_x(Address adr) {
7252 InstructionMark im(this);
7253 emit_int8((unsigned char)0xDB);
7254 emit_operand32(rbp, adr);
7255 }
7256
7257 void Assembler::fldcw(Address src) {
7258 InstructionMark im(this);
7259 emit_int8((unsigned char)0xD9);
7260 emit_operand32(rbp, src);
7261 }
7262
7263 void Assembler::fldenv(Address src) {
7264 InstructionMark im(this);
7265 emit_int8((unsigned char)0xD9);
7266 emit_operand32(rsp, src);
7267 }
7268
7269 void Assembler::fldlg2() {
7270 emit_int8((unsigned char)0xD9);
7271 emit_int8((unsigned char)0xEC);
7272 }
7273
7274 void Assembler::fldln2() {
7275 emit_int8((unsigned char)0xD9);
7276 emit_int8((unsigned char)0xED);
7277 }
7278
7279 void Assembler::fldz() {
7280 emit_int8((unsigned char)0xD9);
7281 emit_int8((unsigned char)0xEE);
7282 }
7283
7284 void Assembler::flog() {
7285 fldln2();
7286 fxch();
7287 fyl2x();
7288 }
7289
7290 void Assembler::flog10() {
7291 fldlg2();
7292 fxch();
7293 fyl2x();
7294 }
7295
7296 void Assembler::fmul(int i) {
7297 emit_farith(0xD8, 0xC8, i);
7298 }
7299
7300 void Assembler::fmul_d(Address src) {
7301 InstructionMark im(this);
7302 emit_int8((unsigned char)0xDC);
7303 emit_operand32(rcx, src);
7304 }
7305
7306 void Assembler::fmul_s(Address src) {
7307 InstructionMark im(this);
7308 emit_int8((unsigned char)0xD8);
7309 emit_operand32(rcx, src);
7310 }
7311
7312 void Assembler::fmula(int i) {
7313 emit_farith(0xDC, 0xC8, i);
7314 }
7315
7316 void Assembler::fmulp(int i) {
7317 emit_farith(0xDE, 0xC8, i);
7318 }
7319
7320 void Assembler::fnsave(Address dst) {
7321 InstructionMark im(this);
7322 emit_int8((unsigned char)0xDD);
7323 emit_operand32(rsi, dst);
7324 }
7325
7326 void Assembler::fnstcw(Address src) {
7327 InstructionMark im(this);
7328 emit_int8((unsigned char)0x9B);
7329 emit_int8((unsigned char)0xD9);
7330 emit_operand32(rdi, src);
7331 }
7332
7333 void Assembler::fnstsw_ax() {
7334 emit_int8((unsigned char)0xDF);
7335 emit_int8((unsigned char)0xE0);
7336 }
7337
7338 void Assembler::fprem() {
7339 emit_int8((unsigned char)0xD9);
7340 emit_int8((unsigned char)0xF8);
7341 }
7342
7343 void Assembler::fprem1() {
7344 emit_int8((unsigned char)0xD9);
7345 emit_int8((unsigned char)0xF5);
7346 }
7347
7348 void Assembler::frstor(Address src) {
7349 InstructionMark im(this);
7350 emit_int8((unsigned char)0xDD);
7351 emit_operand32(rsp, src);
7352 }
7353
7354 void Assembler::fsin() {
7355 emit_int8((unsigned char)0xD9);
7356 emit_int8((unsigned char)0xFE);
7357 }
7358
7359 void Assembler::fsqrt() {
7360 emit_int8((unsigned char)0xD9);
7361 emit_int8((unsigned char)0xFA);
7362 }
7363
7364 void Assembler::fst_d(Address adr) {
7365 InstructionMark im(this);
7366 emit_int8((unsigned char)0xDD);
7367 emit_operand32(rdx, adr);
7368 }
7369
7370 void Assembler::fst_s(Address adr) {
7371 InstructionMark im(this);
7372 emit_int8((unsigned char)0xD9);
7373 emit_operand32(rdx, adr);
7374 }
7375
7376 void Assembler::fstp_d(Address adr) {
7377 InstructionMark im(this);
7378 emit_int8((unsigned char)0xDD);
7379 emit_operand32(rbx, adr);
7380 }
7381
7382 void Assembler::fstp_d(int index) {
7383 emit_farith(0xDD, 0xD8, index);
7384 }
7385
7386 void Assembler::fstp_s(Address adr) {
7387 InstructionMark im(this);
7388 emit_int8((unsigned char)0xD9);
7389 emit_operand32(rbx, adr);
7390 }
7391
7392 void Assembler::fstp_x(Address adr) {
7393 InstructionMark im(this);
7394 emit_int8((unsigned char)0xDB);
7395 emit_operand32(rdi, adr);
7396 }
7397
7398 void Assembler::fsub(int i) {
7399 emit_farith(0xD8, 0xE0, i);
7400 }
7401
7402 void Assembler::fsub_d(Address src) {
7403 InstructionMark im(this);
7404 emit_int8((unsigned char)0xDC);
7405 emit_operand32(rsp, src);
7406 }
7407
7408 void Assembler::fsub_s(Address src) {
7409 InstructionMark im(this);
7410 emit_int8((unsigned char)0xD8);
7411 emit_operand32(rsp, src);
7412 }
7413
7414 void Assembler::fsuba(int i) {
7415 emit_farith(0xDC, 0xE8, i);
7416 }
7417
7418 void Assembler::fsubp(int i) {
7419 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7420 }
7421
7422 void Assembler::fsubr(int i) {
7423 emit_farith(0xD8, 0xE8, i);
7424 }
7425
7426 void Assembler::fsubr_d(Address src) {
7427 InstructionMark im(this);
7428 emit_int8((unsigned char)0xDC);
7429 emit_operand32(rbp, src);
7430 }
7431
7432 void Assembler::fsubr_s(Address src) {
7433 InstructionMark im(this);
7434 emit_int8((unsigned char)0xD8);
7435 emit_operand32(rbp, src);
7436 }
7437
7438 void Assembler::fsubra(int i) {
7439 emit_farith(0xDC, 0xE0, i);
7440 }
7441
7442 void Assembler::fsubrp(int i) {
7443 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7444 }
7445
7446 void Assembler::ftan() {
7447 emit_int8((unsigned char)0xD9);
7448 emit_int8((unsigned char)0xF2);
7449 emit_int8((unsigned char)0xDD);
7450 emit_int8((unsigned char)0xD8);
7451 }
7452
7453 void Assembler::ftst() {
7454 emit_int8((unsigned char)0xD9);
7455 emit_int8((unsigned char)0xE4);
7456 }
7457
7458 void Assembler::fucomi(int i) {
7459 // make sure the instruction is supported (introduced for P6, together with cmov)
7460 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7461 emit_farith(0xDB, 0xE8, i);
7462 }
7463
7464 void Assembler::fucomip(int i) {
7465 // make sure the instruction is supported (introduced for P6, together with cmov)
7466 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7467 emit_farith(0xDF, 0xE8, i);
7468 }
7469
7470 void Assembler::fwait() {
7471 emit_int8((unsigned char)0x9B);
7472 }
7473
7474 void Assembler::fxch(int i) {
7475 emit_farith(0xD9, 0xC8, i);
7476 }
7477
7478 void Assembler::fyl2x() {
7479 emit_int8((unsigned char)0xD9);
7480 emit_int8((unsigned char)0xF1);
7481 }
7482
7483 void Assembler::frndint() {
7484 emit_int8((unsigned char)0xD9);
7485 emit_int8((unsigned char)0xFC);
7486 }
7487
7488 void Assembler::f2xm1() {
7489 emit_int8((unsigned char)0xD9);
7490 emit_int8((unsigned char)0xF0);
7491 }
7492
7493 void Assembler::fldl2e() {
7494 emit_int8((unsigned char)0xD9);
7495 emit_int8((unsigned char)0xEA);
7496 }
7497
7498 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7499 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7500 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7501 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7502
7503 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7504 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7505 if (pre > 0) {
7506 emit_int8(simd_pre[pre]);
7507 }
7508 if (rex_w) {
7509 prefixq(adr, xreg);
7510 } else {
7511 prefix(adr, xreg);
7512 }
7513 if (opc > 0) {
7514 emit_int8(0x0F);
7515 int opc2 = simd_opc[opc];
7516 if (opc2 > 0) {
7517 emit_int8(opc2);
7518 }
7519 }
7520 }
7521
7522 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7523 if (pre > 0) {
7524 emit_int8(simd_pre[pre]);
7525 }
7526 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7527 if (opc > 0) {
7528 emit_int8(0x0F);
7529 int opc2 = simd_opc[opc];
7530 if (opc2 > 0) {
7531 emit_int8(opc2);
7532 }
7533 }
7534 return encode;
7535 }
7536
7537
7538 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7539 int vector_len = _attributes->get_vector_len();
7540 bool vex_w = _attributes->is_rex_vex_w();
7541 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7542 prefix(VEX_3bytes);
7543
7544 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7545 byte1 = (~byte1) & 0xE0;
7546 byte1 |= opc;
7547 emit_int8(byte1);
7548
7549 int byte2 = ((~nds_enc) & 0xf) << 3;
7550 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7551 emit_int8(byte2);
7552 } else {
7553 prefix(VEX_2bytes);
7554
7555 int byte1 = vex_r ? VEX_R : 0;
7556 byte1 = (~byte1) & 0x80;
7557 byte1 |= ((~nds_enc) & 0xf) << 3;
7558 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7559 emit_int8(byte1);
7560 }
7561 }
7562
7563 // This is a 4 byte encoding
7564 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7565 // EVEX 0x62 prefix
7566 prefix(EVEX_4bytes);
7567 bool vex_w = _attributes->is_rex_vex_w();
7568 int evex_encoding = (vex_w ? VEX_W : 0);
7569 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7570 _attributes->set_evex_encoding(evex_encoding);
7571
7572 // P0: byte 2, initialized to RXBR`00mm
7573 // instead of not'd
7574 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7575 byte2 = (~byte2) & 0xF0;
7576 // confine opc opcode extensions in mm bits to lower two bits
7577 // of form {0F, 0F_38, 0F_3A}
7578 byte2 |= opc;
7579 emit_int8(byte2);
7580
7581 // P1: byte 3 as Wvvvv1pp
7582 int byte3 = ((~nds_enc) & 0xf) << 3;
7583 // p[10] is always 1
7584 byte3 |= EVEX_F;
7585 byte3 |= (vex_w & 1) << 7;
7586 // confine pre opcode extensions in pp bits to lower two bits
7587 // of form {66, F3, F2}
7588 byte3 |= pre;
7589 emit_int8(byte3);
7590
7591 // P2: byte 4 as zL'Lbv'aaa
7592 // kregs are implemented in the low 3 bits as aaa
7593 int byte4 = (_attributes->is_no_reg_mask()) ?
7594 0 :
7595 _attributes->get_embedded_opmask_register_specifier();
7596 // EVEX.v` for extending EVEX.vvvv or VIDX
7597 byte4 |= (evex_v ? 0: EVEX_V);
7598 // third EXEC.b for broadcast actions
7599 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7600 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7601 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7602 // last is EVEX.z for zero/merge actions
7603 if (_attributes->is_no_reg_mask() == false) {
7604 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7605 }
7606 emit_int8(byte4);
7607 }
7608
7609 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7610 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7611 bool vex_b = adr.base_needs_rex();
7612 bool vex_x;
7613 if (adr.isxmmindex()) {
7614 vex_x = adr.xmmindex_needs_rex();
7615 } else {
7616 vex_x = adr.index_needs_rex();
7617 }
7618 set_attributes(attributes);
7619 attributes->set_current_assembler(this);
7620
7621 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7622 // is allowed in legacy mode and has resources which will fit in it.
7623 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7624 if (!attributes->is_legacy_mode()) {
7625 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7626 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
7627 attributes->set_is_legacy_mode();
7628 }
7629 }
7630 }
7631
7632 if (UseAVX > 2) {
7633 assert(((!attributes->uses_vl()) ||
7634 (attributes->get_vector_len() == AVX_512bit) ||
7635 (!_legacy_mode_vl) ||
7636 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7637 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7638 }
7639
7640 _is_managed = false;
7641 if (UseAVX > 2 && !attributes->is_legacy_mode())
7642 {
7643 bool evex_r = (xreg_enc >= 16);
7644 bool evex_v;
7645 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7646 if (adr.isxmmindex()) {
7647 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7648 } else {
7649 evex_v = (nds_enc >= 16);
7650 }
7651 attributes->set_is_evex_instruction();
7652 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7653 } else {
7654 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7655 attributes->set_rex_vex_w(false);
7656 }
7657 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7658 }
7659 }
7660
7661 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7662 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7663 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7664 bool vex_x = false;
7665 set_attributes(attributes);
7666 attributes->set_current_assembler(this);
7667
7668 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7669 // is allowed in legacy mode and has resources which will fit in it.
7670 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7671 if (!attributes->is_legacy_mode()) {
7672 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7673 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
7674 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
7675 attributes->set_is_legacy_mode();
7676 }
7677 }
7678 }
7679
7680 if (UseAVX > 2) {
7681 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
7682 // Instruction with uses_vl true are vector instructions
7683 // All the vector instructions with AVX_512bit length can have legacy_mode as false
7684 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
7685 // Rest all should have legacy_mode set as true
7686 assert(((!attributes->uses_vl()) ||
7687 (attributes->get_vector_len() == AVX_512bit) ||
7688 (!_legacy_mode_vl) ||
7689 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7690 // Instruction with legacy_mode true should have dst, nds and src < 15
7691 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7692 }
7693
7694 _is_managed = false;
7695 if (UseAVX > 2 && !attributes->is_legacy_mode())
7696 {
7697 bool evex_r = (dst_enc >= 16);
7698 bool evex_v = (nds_enc >= 16);
7699 // can use vex_x as bank extender on rm encoding
7700 vex_x = (src_enc >= 16);
7701 attributes->set_is_evex_instruction();
7702 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7703 } else {
7704 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7705 attributes->set_rex_vex_w(false);
7706 }
7707 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7708 }
7709
7710 // return modrm byte components for operands
7711 return (((dst_enc & 7) << 3) | (src_enc & 7));
7712 }
7713
7714
7715 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7716 VexOpcode opc, InstructionAttr *attributes) {
7717 if (UseAVX > 0) {
7718 int xreg_enc = xreg->encoding();
7719 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7720 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7721 } else {
7722 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7723 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7724 }
7725 }
7726
7727 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7728 VexOpcode opc, InstructionAttr *attributes) {
7729 int dst_enc = dst->encoding();
7730 int src_enc = src->encoding();
7731 if (UseAVX > 0) {
7732 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7733 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7734 } else {
7735 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7736 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7737 }
7738 }
7739
7740 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7741 assert(VM_Version::supports_avx(), "");
7742 assert(!VM_Version::supports_evex(), "");
7743 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7744 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7745 emit_int8((unsigned char)0xC2);
7746 emit_int8((unsigned char)(0xC0 | encode));
7747 emit_int8((unsigned char)(0xF & cop));
7748 }
7749
7750 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7751 assert(VM_Version::supports_avx(), "");
7752 assert(!VM_Version::supports_evex(), "");
7753 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7754 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7755 emit_int8((unsigned char)0x4B);
7756 emit_int8((unsigned char)(0xC0 | encode));
7757 int src2_enc = src2->encoding();
7758 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7759 }
7760
7761 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7762 assert(VM_Version::supports_avx(), "");
7763 assert(!VM_Version::supports_evex(), "");
7764 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7765 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7766 emit_int8((unsigned char)0xC2);
7767 emit_int8((unsigned char)(0xC0 | encode));
7768 emit_int8((unsigned char)(0xF & cop));
7769 }
7770
7771 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7772 assert(VM_Version::supports_avx(), "");
7773 assert(!VM_Version::supports_evex(), "");
7774 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7775 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7776 emit_int8((unsigned char)0x4A);
7777 emit_int8((unsigned char)(0xC0 | encode));
7778 int src2_enc = src2->encoding();
7779 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7780 }
7781
7782 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7783 assert(VM_Version::supports_avx2(), "");
7784 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7785 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7786 emit_int8((unsigned char)0x02);
7787 emit_int8((unsigned char)(0xC0 | encode));
7788 emit_int8((unsigned char)imm8);
7789 }
7790
7791 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7792 assert(VM_Version::supports_bmi2(), "");
7793 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7794 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7795 emit_int8((unsigned char)0xF7);
7796 emit_int8((unsigned char)(0xC0 | encode));
7797 }
7798
7799 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7800 assert(VM_Version::supports_bmi2(), "");
7801 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7802 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7803 emit_int8((unsigned char)0xF7);
7804 emit_int8((unsigned char)(0xC0 | encode));
7805 }
7806
7807 #ifndef _LP64
7808
7809 void Assembler::incl(Register dst) {
7810 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7811 emit_int8(0x40 | dst->encoding());
7812 }
7813
7814 void Assembler::lea(Register dst, Address src) {
7815 leal(dst, src);
7816 }
7817
7818 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7819 InstructionMark im(this);
7820 emit_int8((unsigned char)0xC7);
7821 emit_operand(rax, dst);
7822 emit_data((int)imm32, rspec, 0);
7823 }
7824
7825 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7826 InstructionMark im(this);
7827 int encode = prefix_and_encode(dst->encoding());
7828 emit_int8((unsigned char)(0xB8 | encode));
7829 emit_data((int)imm32, rspec, 0);
7830 }
7831
7832 void Assembler::popa() { // 32bit
7833 emit_int8(0x61);
7834 }
7835
7836 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7837 InstructionMark im(this);
7838 emit_int8(0x68);
7839 emit_data(imm32, rspec, 0);
7840 }
7841
7842 void Assembler::pusha() { // 32bit
7843 emit_int8(0x60);
7844 }
7845
7846 void Assembler::set_byte_if_not_zero(Register dst) {
7847 emit_int8(0x0F);
7848 emit_int8((unsigned char)0x95);
7849 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7850 }
7851
7852 void Assembler::shldl(Register dst, Register src) {
7853 emit_int8(0x0F);
7854 emit_int8((unsigned char)0xA5);
7855 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7856 }
7857
7858 // 0F A4 / r ib
7859 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7860 emit_int8(0x0F);
7861 emit_int8((unsigned char)0xA4);
7862 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7863 emit_int8(imm8);
7864 }
7865
7866 void Assembler::shrdl(Register dst, Register src) {
7867 emit_int8(0x0F);
7868 emit_int8((unsigned char)0xAD);
7869 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7870 }
7871
7872 #else // LP64
7873
7874 void Assembler::set_byte_if_not_zero(Register dst) {
7875 int enc = prefix_and_encode(dst->encoding(), true);
7876 emit_int8(0x0F);
7877 emit_int8((unsigned char)0x95);
7878 emit_int8((unsigned char)(0xE0 | enc));
7879 }
7880
7881 // 64bit only pieces of the assembler
7882 // This should only be used by 64bit instructions that can use rip-relative
7883 // it cannot be used by instructions that want an immediate value.
7884
7885 bool Assembler::reachable(AddressLiteral adr) {
7886 int64_t disp;
7887 // None will force a 64bit literal to the code stream. Likely a placeholder
7888 // for something that will be patched later and we need to certain it will
7889 // always be reachable.
7890 if (adr.reloc() == relocInfo::none) {
7891 return false;
7892 }
7893 if (adr.reloc() == relocInfo::internal_word_type) {
7894 // This should be rip relative and easily reachable.
7895 return true;
7896 }
7897 if (adr.reloc() == relocInfo::virtual_call_type ||
7898 adr.reloc() == relocInfo::opt_virtual_call_type ||
7899 adr.reloc() == relocInfo::static_call_type ||
7900 adr.reloc() == relocInfo::static_stub_type ) {
7901 // This should be rip relative within the code cache and easily
7902 // reachable until we get huge code caches. (At which point
7903 // ic code is going to have issues).
7904 return true;
7905 }
7906 if (adr.reloc() != relocInfo::external_word_type &&
7907 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7908 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7909 adr.reloc() != relocInfo::runtime_call_type ) {
7910 return false;
7911 }
7912
7913 // Stress the correction code
7914 if (ForceUnreachable) {
7915 // Must be runtimecall reloc, see if it is in the codecache
7916 // Flipping stuff in the codecache to be unreachable causes issues
7917 // with things like inline caches where the additional instructions
7918 // are not handled.
7919 if (CodeCache::find_blob(adr._target) == NULL) {
7920 return false;
7921 }
7922 }
7923 // For external_word_type/runtime_call_type if it is reachable from where we
7924 // are now (possibly a temp buffer) and where we might end up
7925 // anywhere in the codeCache then we are always reachable.
7926 // This would have to change if we ever save/restore shared code
7927 // to be more pessimistic.
7928 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7929 if (!is_simm32(disp)) return false;
7930 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7931 if (!is_simm32(disp)) return false;
7932
7933 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7934
7935 // Because rip relative is a disp + address_of_next_instruction and we
7936 // don't know the value of address_of_next_instruction we apply a fudge factor
7937 // to make sure we will be ok no matter the size of the instruction we get placed into.
7938 // We don't have to fudge the checks above here because they are already worst case.
7939
7940 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7941 // + 4 because better safe than sorry.
7942 const int fudge = 12 + 4;
7943 if (disp < 0) {
7944 disp -= fudge;
7945 } else {
7946 disp += fudge;
7947 }
7948 return is_simm32(disp);
7949 }
7950
7951 // Check if the polling page is not reachable from the code cache using rip-relative
7952 // addressing.
7953 bool Assembler::is_polling_page_far() {
7954 intptr_t addr = (intptr_t)os::get_polling_page();
7955 return ForceUnreachable ||
7956 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7957 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7958 }
7959
7960 void Assembler::emit_data64(jlong data,
7961 relocInfo::relocType rtype,
7962 int format) {
7963 if (rtype == relocInfo::none) {
7964 emit_int64(data);
7965 } else {
7966 emit_data64(data, Relocation::spec_simple(rtype), format);
7967 }
7968 }
7969
7970 void Assembler::emit_data64(jlong data,
7971 RelocationHolder const& rspec,
7972 int format) {
7973 assert(imm_operand == 0, "default format must be immediate in this file");
7974 assert(imm_operand == format, "must be immediate");
7975 assert(inst_mark() != NULL, "must be inside InstructionMark");
7976 // Do not use AbstractAssembler::relocate, which is not intended for
7977 // embedded words. Instead, relocate to the enclosing instruction.
7978 code_section()->relocate(inst_mark(), rspec, format);
7979 #ifdef ASSERT
7980 check_relocation(rspec, format);
7981 #endif
7982 emit_int64(data);
7983 }
7984
7985 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7986 if (reg_enc >= 8) {
7987 prefix(REX_B);
7988 reg_enc -= 8;
7989 } else if (byteinst && reg_enc >= 4) {
7990 prefix(REX);
7991 }
7992 return reg_enc;
7993 }
7994
7995 int Assembler::prefixq_and_encode(int reg_enc) {
7996 if (reg_enc < 8) {
7997 prefix(REX_W);
7998 } else {
7999 prefix(REX_WB);
8000 reg_enc -= 8;
8001 }
8002 return reg_enc;
8003 }
8004
8005 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
8006 if (dst_enc < 8) {
8007 if (src_enc >= 8) {
8008 prefix(REX_B);
8009 src_enc -= 8;
8010 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8011 prefix(REX);
8012 }
8013 } else {
8014 if (src_enc < 8) {
8015 prefix(REX_R);
8016 } else {
8017 prefix(REX_RB);
8018 src_enc -= 8;
8019 }
8020 dst_enc -= 8;
8021 }
8022 return dst_enc << 3 | src_enc;
8023 }
8024
8025 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8026 if (dst_enc < 8) {
8027 if (src_enc < 8) {
8028 prefix(REX_W);
8029 } else {
8030 prefix(REX_WB);
8031 src_enc -= 8;
8032 }
8033 } else {
8034 if (src_enc < 8) {
8035 prefix(REX_WR);
8036 } else {
8037 prefix(REX_WRB);
8038 src_enc -= 8;
8039 }
8040 dst_enc -= 8;
8041 }
8042 return dst_enc << 3 | src_enc;
8043 }
8044
8045 void Assembler::prefix(Register reg) {
8046 if (reg->encoding() >= 8) {
8047 prefix(REX_B);
8048 }
8049 }
8050
8051 void Assembler::prefix(Register dst, Register src, Prefix p) {
8052 if (src->encoding() >= 8) {
8053 p = (Prefix)(p | REX_B);
8054 }
8055 if (dst->encoding() >= 8) {
8056 p = (Prefix)( p | REX_R);
8057 }
8058 if (p != Prefix_EMPTY) {
8059 // do not generate an empty prefix
8060 prefix(p);
8061 }
8062 }
8063
8064 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8065 if (adr.base_needs_rex()) {
8066 if (adr.index_needs_rex()) {
8067 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8068 } else {
8069 prefix(REX_B);
8070 }
8071 } else {
8072 if (adr.index_needs_rex()) {
8073 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8074 }
8075 }
8076 if (dst->encoding() >= 8) {
8077 p = (Prefix)(p | REX_R);
8078 }
8079 if (p != Prefix_EMPTY) {
8080 // do not generate an empty prefix
8081 prefix(p);
8082 }
8083 }
8084
8085 void Assembler::prefix(Address adr) {
8086 if (adr.base_needs_rex()) {
8087 if (adr.index_needs_rex()) {
8088 prefix(REX_XB);
8089 } else {
8090 prefix(REX_B);
8091 }
8092 } else {
8093 if (adr.index_needs_rex()) {
8094 prefix(REX_X);
8095 }
8096 }
8097 }
8098
8099 void Assembler::prefixq(Address adr) {
8100 if (adr.base_needs_rex()) {
8101 if (adr.index_needs_rex()) {
8102 prefix(REX_WXB);
8103 } else {
8104 prefix(REX_WB);
8105 }
8106 } else {
8107 if (adr.index_needs_rex()) {
8108 prefix(REX_WX);
8109 } else {
8110 prefix(REX_W);
8111 }
8112 }
8113 }
8114
8115
8116 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8117 if (reg->encoding() < 8) {
8118 if (adr.base_needs_rex()) {
8119 if (adr.index_needs_rex()) {
8120 prefix(REX_XB);
8121 } else {
8122 prefix(REX_B);
8123 }
8124 } else {
8125 if (adr.index_needs_rex()) {
8126 prefix(REX_X);
8127 } else if (byteinst && reg->encoding() >= 4 ) {
8128 prefix(REX);
8129 }
8130 }
8131 } else {
8132 if (adr.base_needs_rex()) {
8133 if (adr.index_needs_rex()) {
8134 prefix(REX_RXB);
8135 } else {
8136 prefix(REX_RB);
8137 }
8138 } else {
8139 if (adr.index_needs_rex()) {
8140 prefix(REX_RX);
8141 } else {
8142 prefix(REX_R);
8143 }
8144 }
8145 }
8146 }
8147
8148 void Assembler::prefixq(Address adr, Register src) {
8149 if (src->encoding() < 8) {
8150 if (adr.base_needs_rex()) {
8151 if (adr.index_needs_rex()) {
8152 prefix(REX_WXB);
8153 } else {
8154 prefix(REX_WB);
8155 }
8156 } else {
8157 if (adr.index_needs_rex()) {
8158 prefix(REX_WX);
8159 } else {
8160 prefix(REX_W);
8161 }
8162 }
8163 } else {
8164 if (adr.base_needs_rex()) {
8165 if (adr.index_needs_rex()) {
8166 prefix(REX_WRXB);
8167 } else {
8168 prefix(REX_WRB);
8169 }
8170 } else {
8171 if (adr.index_needs_rex()) {
8172 prefix(REX_WRX);
8173 } else {
8174 prefix(REX_WR);
8175 }
8176 }
8177 }
8178 }
8179
8180 void Assembler::prefix(Address adr, XMMRegister reg) {
8181 if (reg->encoding() < 8) {
8182 if (adr.base_needs_rex()) {
8183 if (adr.index_needs_rex()) {
8184 prefix(REX_XB);
8185 } else {
8186 prefix(REX_B);
8187 }
8188 } else {
8189 if (adr.index_needs_rex()) {
8190 prefix(REX_X);
8191 }
8192 }
8193 } else {
8194 if (adr.base_needs_rex()) {
8195 if (adr.index_needs_rex()) {
8196 prefix(REX_RXB);
8197 } else {
8198 prefix(REX_RB);
8199 }
8200 } else {
8201 if (adr.index_needs_rex()) {
8202 prefix(REX_RX);
8203 } else {
8204 prefix(REX_R);
8205 }
8206 }
8207 }
8208 }
8209
8210 void Assembler::prefixq(Address adr, XMMRegister src) {
8211 if (src->encoding() < 8) {
8212 if (adr.base_needs_rex()) {
8213 if (adr.index_needs_rex()) {
8214 prefix(REX_WXB);
8215 } else {
8216 prefix(REX_WB);
8217 }
8218 } else {
8219 if (adr.index_needs_rex()) {
8220 prefix(REX_WX);
8221 } else {
8222 prefix(REX_W);
8223 }
8224 }
8225 } else {
8226 if (adr.base_needs_rex()) {
8227 if (adr.index_needs_rex()) {
8228 prefix(REX_WRXB);
8229 } else {
8230 prefix(REX_WRB);
8231 }
8232 } else {
8233 if (adr.index_needs_rex()) {
8234 prefix(REX_WRX);
8235 } else {
8236 prefix(REX_WR);
8237 }
8238 }
8239 }
8240 }
8241
8242 void Assembler::adcq(Register dst, int32_t imm32) {
8243 (void) prefixq_and_encode(dst->encoding());
8244 emit_arith(0x81, 0xD0, dst, imm32);
8245 }
8246
8247 void Assembler::adcq(Register dst, Address src) {
8248 InstructionMark im(this);
8249 prefixq(src, dst);
8250 emit_int8(0x13);
8251 emit_operand(dst, src);
8252 }
8253
8254 void Assembler::adcq(Register dst, Register src) {
8255 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8256 emit_arith(0x13, 0xC0, dst, src);
8257 }
8258
8259 void Assembler::addq(Address dst, int32_t imm32) {
8260 InstructionMark im(this);
8261 prefixq(dst);
8262 emit_arith_operand(0x81, rax, dst,imm32);
8263 }
8264
8265 void Assembler::addq(Address dst, Register src) {
8266 InstructionMark im(this);
8267 prefixq(dst, src);
8268 emit_int8(0x01);
8269 emit_operand(src, dst);
8270 }
8271
8272 void Assembler::addq(Register dst, int32_t imm32) {
8273 (void) prefixq_and_encode(dst->encoding());
8274 emit_arith(0x81, 0xC0, dst, imm32);
8275 }
8276
8277 void Assembler::addq(Register dst, Address src) {
8278 InstructionMark im(this);
8279 prefixq(src, dst);
8280 emit_int8(0x03);
8281 emit_operand(dst, src);
8282 }
8283
8284 void Assembler::addq(Register dst, Register src) {
8285 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8286 emit_arith(0x03, 0xC0, dst, src);
8287 }
8288
8289 void Assembler::adcxq(Register dst, Register src) {
8290 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8291 emit_int8((unsigned char)0x66);
8292 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8293 emit_int8(0x0F);
8294 emit_int8(0x38);
8295 emit_int8((unsigned char)0xF6);
8296 emit_int8((unsigned char)(0xC0 | encode));
8297 }
8298
8299 void Assembler::adoxq(Register dst, Register src) {
8300 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8301 emit_int8((unsigned char)0xF3);
8302 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8303 emit_int8(0x0F);
8304 emit_int8(0x38);
8305 emit_int8((unsigned char)0xF6);
8306 emit_int8((unsigned char)(0xC0 | encode));
8307 }
8308
8309 void Assembler::andq(Address dst, int32_t imm32) {
8310 InstructionMark im(this);
8311 prefixq(dst);
8312 emit_int8((unsigned char)0x81);
8313 emit_operand(rsp, dst, 4);
8314 emit_int32(imm32);
8315 }
8316
8317 void Assembler::andq(Register dst, int32_t imm32) {
8318 (void) prefixq_and_encode(dst->encoding());
8319 emit_arith(0x81, 0xE0, dst, imm32);
8320 }
8321
8322 void Assembler::andq(Register dst, Address src) {
8323 InstructionMark im(this);
8324 prefixq(src, dst);
8325 emit_int8(0x23);
8326 emit_operand(dst, src);
8327 }
8328
8329 void Assembler::andq(Register dst, Register src) {
8330 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8331 emit_arith(0x23, 0xC0, dst, src);
8332 }
8333
8334 void Assembler::andnq(Register dst, Register src1, Register src2) {
8335 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8336 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8337 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8338 emit_int8((unsigned char)0xF2);
8339 emit_int8((unsigned char)(0xC0 | encode));
8340 }
8341
8342 void Assembler::andnq(Register dst, Register src1, Address src2) {
8343 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8344 InstructionMark im(this);
8345 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8346 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8347 emit_int8((unsigned char)0xF2);
8348 emit_operand(dst, src2);
8349 }
8350
8351 void Assembler::bsfq(Register dst, Register src) {
8352 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8353 emit_int8(0x0F);
8354 emit_int8((unsigned char)0xBC);
8355 emit_int8((unsigned char)(0xC0 | encode));
8356 }
8357
8358 void Assembler::bsrq(Register dst, Register src) {
8359 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8360 emit_int8(0x0F);
8361 emit_int8((unsigned char)0xBD);
8362 emit_int8((unsigned char)(0xC0 | encode));
8363 }
8364
8365 void Assembler::bswapq(Register reg) {
8366 int encode = prefixq_and_encode(reg->encoding());
8367 emit_int8(0x0F);
8368 emit_int8((unsigned char)(0xC8 | encode));
8369 }
8370
8371 void Assembler::blsiq(Register dst, Register src) {
8372 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8373 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8374 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8375 emit_int8((unsigned char)0xF3);
8376 emit_int8((unsigned char)(0xC0 | encode));
8377 }
8378
8379 void Assembler::blsiq(Register dst, Address src) {
8380 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8381 InstructionMark im(this);
8382 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8383 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8384 emit_int8((unsigned char)0xF3);
8385 emit_operand(rbx, src);
8386 }
8387
8388 void Assembler::blsmskq(Register dst, Register src) {
8389 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8390 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8391 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8392 emit_int8((unsigned char)0xF3);
8393 emit_int8((unsigned char)(0xC0 | encode));
8394 }
8395
8396 void Assembler::blsmskq(Register dst, Address src) {
8397 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8398 InstructionMark im(this);
8399 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8400 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8401 emit_int8((unsigned char)0xF3);
8402 emit_operand(rdx, src);
8403 }
8404
8405 void Assembler::blsrq(Register dst, Register src) {
8406 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8407 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8408 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8409 emit_int8((unsigned char)0xF3);
8410 emit_int8((unsigned char)(0xC0 | encode));
8411 }
8412
8413 void Assembler::blsrq(Register dst, Address src) {
8414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8415 InstructionMark im(this);
8416 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8417 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8418 emit_int8((unsigned char)0xF3);
8419 emit_operand(rcx, src);
8420 }
8421
8422 void Assembler::cdqq() {
8423 prefix(REX_W);
8424 emit_int8((unsigned char)0x99);
8425 }
8426
8427 void Assembler::clflush(Address adr) {
8428 prefix(adr);
8429 emit_int8(0x0F);
8430 emit_int8((unsigned char)0xAE);
8431 emit_operand(rdi, adr);
8432 }
8433
8434 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8435 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8436 emit_int8(0x0F);
8437 emit_int8(0x40 | cc);
8438 emit_int8((unsigned char)(0xC0 | encode));
8439 }
8440
8441 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8442 InstructionMark im(this);
8443 prefixq(src, dst);
8444 emit_int8(0x0F);
8445 emit_int8(0x40 | cc);
8446 emit_operand(dst, src);
8447 }
8448
8449 void Assembler::cmpq(Address dst, int32_t imm32) {
8450 InstructionMark im(this);
8451 prefixq(dst);
8452 emit_int8((unsigned char)0x81);
8453 emit_operand(rdi, dst, 4);
8454 emit_int32(imm32);
8455 }
8456
8457 void Assembler::cmpq(Register dst, int32_t imm32) {
8458 (void) prefixq_and_encode(dst->encoding());
8459 emit_arith(0x81, 0xF8, dst, imm32);
8460 }
8461
8462 void Assembler::cmpq(Address dst, Register src) {
8463 InstructionMark im(this);
8464 prefixq(dst, src);
8465 emit_int8(0x3B);
8466 emit_operand(src, dst);
8467 }
8468
8469 void Assembler::cmpq(Register dst, Register src) {
8470 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8471 emit_arith(0x3B, 0xC0, dst, src);
8472 }
8473
8474 void Assembler::cmpq(Register dst, Address src) {
8475 InstructionMark im(this);
8476 prefixq(src, dst);
8477 emit_int8(0x3B);
8478 emit_operand(dst, src);
8479 }
8480
8481 void Assembler::cmpxchgq(Register reg, Address adr) {
8482 InstructionMark im(this);
8483 prefixq(adr, reg);
8484 emit_int8(0x0F);
8485 emit_int8((unsigned char)0xB1);
8486 emit_operand(reg, adr);
8487 }
8488
8489 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8490 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8491 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8492 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8493 emit_int8(0x2A);
8494 emit_int8((unsigned char)(0xC0 | encode));
8495 }
8496
8497 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8499 InstructionMark im(this);
8500 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8501 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8502 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8503 emit_int8(0x2A);
8504 emit_operand(dst, src);
8505 }
8506
8507 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8508 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8509 InstructionMark im(this);
8510 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8511 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8512 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8513 emit_int8(0x2A);
8514 emit_operand(dst, src);
8515 }
8516
8517 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8518 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8519 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8520 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8521 emit_int8(0x2C);
8522 emit_int8((unsigned char)(0xC0 | encode));
8523 }
8524
8525 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8526 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8527 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8528 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8529 emit_int8(0x2C);
8530 emit_int8((unsigned char)(0xC0 | encode));
8531 }
8532
8533 void Assembler::decl(Register dst) {
8534 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8535 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8536 int encode = prefix_and_encode(dst->encoding());
8537 emit_int8((unsigned char)0xFF);
8538 emit_int8((unsigned char)(0xC8 | encode));
8539 }
8540
8541 void Assembler::decq(Register dst) {
8542 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8543 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8544 int encode = prefixq_and_encode(dst->encoding());
8545 emit_int8((unsigned char)0xFF);
8546 emit_int8(0xC8 | encode);
8547 }
8548
8549 void Assembler::decq(Address dst) {
8550 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8551 InstructionMark im(this);
8552 prefixq(dst);
8553 emit_int8((unsigned char)0xFF);
8554 emit_operand(rcx, dst);
8555 }
8556
8557 void Assembler::fxrstor(Address src) {
8558 prefixq(src);
8559 emit_int8(0x0F);
8560 emit_int8((unsigned char)0xAE);
8561 emit_operand(as_Register(1), src);
8562 }
8563
8564 void Assembler::xrstor(Address src) {
8565 prefixq(src);
8566 emit_int8(0x0F);
8567 emit_int8((unsigned char)0xAE);
8568 emit_operand(as_Register(5), src);
8569 }
8570
8571 void Assembler::fxsave(Address dst) {
8572 prefixq(dst);
8573 emit_int8(0x0F);
8574 emit_int8((unsigned char)0xAE);
8575 emit_operand(as_Register(0), dst);
8576 }
8577
8578 void Assembler::xsave(Address dst) {
8579 prefixq(dst);
8580 emit_int8(0x0F);
8581 emit_int8((unsigned char)0xAE);
8582 emit_operand(as_Register(4), dst);
8583 }
8584
8585 void Assembler::idivq(Register src) {
8586 int encode = prefixq_and_encode(src->encoding());
8587 emit_int8((unsigned char)0xF7);
8588 emit_int8((unsigned char)(0xF8 | encode));
8589 }
8590
8591 void Assembler::imulq(Register dst, Register src) {
8592 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8593 emit_int8(0x0F);
8594 emit_int8((unsigned char)0xAF);
8595 emit_int8((unsigned char)(0xC0 | encode));
8596 }
8597
8598 void Assembler::imulq(Register dst, Register src, int value) {
8599 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8600 if (is8bit(value)) {
8601 emit_int8(0x6B);
8602 emit_int8((unsigned char)(0xC0 | encode));
8603 emit_int8(value & 0xFF);
8604 } else {
8605 emit_int8(0x69);
8606 emit_int8((unsigned char)(0xC0 | encode));
8607 emit_int32(value);
8608 }
8609 }
8610
8611 void Assembler::imulq(Register dst, Address src) {
8612 InstructionMark im(this);
8613 prefixq(src, dst);
8614 emit_int8(0x0F);
8615 emit_int8((unsigned char) 0xAF);
8616 emit_operand(dst, src);
8617 }
8618
8619 void Assembler::incl(Register dst) {
8620 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8621 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8622 int encode = prefix_and_encode(dst->encoding());
8623 emit_int8((unsigned char)0xFF);
8624 emit_int8((unsigned char)(0xC0 | encode));
8625 }
8626
8627 void Assembler::incq(Register dst) {
8628 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8629 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8630 int encode = prefixq_and_encode(dst->encoding());
8631 emit_int8((unsigned char)0xFF);
8632 emit_int8((unsigned char)(0xC0 | encode));
8633 }
8634
8635 void Assembler::incq(Address dst) {
8636 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8637 InstructionMark im(this);
8638 prefixq(dst);
8639 emit_int8((unsigned char)0xFF);
8640 emit_operand(rax, dst);
8641 }
8642
8643 void Assembler::lea(Register dst, Address src) {
8644 leaq(dst, src);
8645 }
8646
8647 void Assembler::leaq(Register dst, Address src) {
8648 InstructionMark im(this);
8649 prefixq(src, dst);
8650 emit_int8((unsigned char)0x8D);
8651 emit_operand(dst, src);
8652 }
8653
8654 void Assembler::mov64(Register dst, int64_t imm64) {
8655 InstructionMark im(this);
8656 int encode = prefixq_and_encode(dst->encoding());
8657 emit_int8((unsigned char)(0xB8 | encode));
8658 emit_int64(imm64);
8659 }
8660
8661 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8662 InstructionMark im(this);
8663 int encode = prefixq_and_encode(dst->encoding());
8664 emit_int8(0xB8 | encode);
8665 emit_data64(imm64, rspec);
8666 }
8667
8668 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8669 InstructionMark im(this);
8670 int encode = prefix_and_encode(dst->encoding());
8671 emit_int8((unsigned char)(0xB8 | encode));
8672 emit_data((int)imm32, rspec, narrow_oop_operand);
8673 }
8674
8675 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8676 InstructionMark im(this);
8677 prefix(dst);
8678 emit_int8((unsigned char)0xC7);
8679 emit_operand(rax, dst, 4);
8680 emit_data((int)imm32, rspec, narrow_oop_operand);
8681 }
8682
8683 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8684 InstructionMark im(this);
8685 int encode = prefix_and_encode(src1->encoding());
8686 emit_int8((unsigned char)0x81);
8687 emit_int8((unsigned char)(0xF8 | encode));
8688 emit_data((int)imm32, rspec, narrow_oop_operand);
8689 }
8690
8691 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8692 InstructionMark im(this);
8693 prefix(src1);
8694 emit_int8((unsigned char)0x81);
8695 emit_operand(rax, src1, 4);
8696 emit_data((int)imm32, rspec, narrow_oop_operand);
8697 }
8698
8699 void Assembler::lzcntq(Register dst, Register src) {
8700 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8701 emit_int8((unsigned char)0xF3);
8702 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8703 emit_int8(0x0F);
8704 emit_int8((unsigned char)0xBD);
8705 emit_int8((unsigned char)(0xC0 | encode));
8706 }
8707
8708 void Assembler::movdq(XMMRegister dst, Register src) {
8709 // table D-1 says MMX/SSE2
8710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8711 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8712 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8713 emit_int8(0x6E);
8714 emit_int8((unsigned char)(0xC0 | encode));
8715 }
8716
8717 void Assembler::movdq(Register dst, XMMRegister src) {
8718 // table D-1 says MMX/SSE2
8719 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8720 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8721 // swap src/dst to get correct prefix
8722 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8723 emit_int8(0x7E);
8724 emit_int8((unsigned char)(0xC0 | encode));
8725 }
8726
8727 void Assembler::movq(Register dst, Register src) {
8728 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8729 emit_int8((unsigned char)0x8B);
8730 emit_int8((unsigned char)(0xC0 | encode));
8731 }
8732
8733 void Assembler::movq(Register dst, Address src) {
8734 InstructionMark im(this);
8735 prefixq(src, dst);
8736 emit_int8((unsigned char)0x8B);
8737 emit_operand(dst, src);
8738 }
8739
8740 void Assembler::movq(Address dst, Register src) {
8741 InstructionMark im(this);
8742 prefixq(dst, src);
8743 emit_int8((unsigned char)0x89);
8744 emit_operand(src, dst);
8745 }
8746
8747 void Assembler::movsbq(Register dst, Address src) {
8748 InstructionMark im(this);
8749 prefixq(src, dst);
8750 emit_int8(0x0F);
8751 emit_int8((unsigned char)0xBE);
8752 emit_operand(dst, src);
8753 }
8754
8755 void Assembler::movsbq(Register dst, Register src) {
8756 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8757 emit_int8(0x0F);
8758 emit_int8((unsigned char)0xBE);
8759 emit_int8((unsigned char)(0xC0 | encode));
8760 }
8761
8762 void Assembler::movslq(Register dst, int32_t imm32) {
8763 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8764 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8765 // as a result we shouldn't use until tested at runtime...
8766 ShouldNotReachHere();
8767 InstructionMark im(this);
8768 int encode = prefixq_and_encode(dst->encoding());
8769 emit_int8((unsigned char)(0xC7 | encode));
8770 emit_int32(imm32);
8771 }
8772
8773 void Assembler::movslq(Address dst, int32_t imm32) {
8774 assert(is_simm32(imm32), "lost bits");
8775 InstructionMark im(this);
8776 prefixq(dst);
8777 emit_int8((unsigned char)0xC7);
8778 emit_operand(rax, dst, 4);
8779 emit_int32(imm32);
8780 }
8781
8782 void Assembler::movslq(Register dst, Address src) {
8783 InstructionMark im(this);
8784 prefixq(src, dst);
8785 emit_int8(0x63);
8786 emit_operand(dst, src);
8787 }
8788
8789 void Assembler::movslq(Register dst, Register src) {
8790 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8791 emit_int8(0x63);
8792 emit_int8((unsigned char)(0xC0 | encode));
8793 }
8794
8795 void Assembler::movswq(Register dst, Address src) {
8796 InstructionMark im(this);
8797 prefixq(src, dst);
8798 emit_int8(0x0F);
8799 emit_int8((unsigned char)0xBF);
8800 emit_operand(dst, src);
8801 }
8802
8803 void Assembler::movswq(Register dst, Register src) {
8804 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8805 emit_int8((unsigned char)0x0F);
8806 emit_int8((unsigned char)0xBF);
8807 emit_int8((unsigned char)(0xC0 | encode));
8808 }
8809
8810 void Assembler::movzbq(Register dst, Address src) {
8811 InstructionMark im(this);
8812 prefixq(src, dst);
8813 emit_int8((unsigned char)0x0F);
8814 emit_int8((unsigned char)0xB6);
8815 emit_operand(dst, src);
8816 }
8817
8818 void Assembler::movzbq(Register dst, Register src) {
8819 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8820 emit_int8(0x0F);
8821 emit_int8((unsigned char)0xB6);
8822 emit_int8(0xC0 | encode);
8823 }
8824
8825 void Assembler::movzwq(Register dst, Address src) {
8826 InstructionMark im(this);
8827 prefixq(src, dst);
8828 emit_int8((unsigned char)0x0F);
8829 emit_int8((unsigned char)0xB7);
8830 emit_operand(dst, src);
8831 }
8832
8833 void Assembler::movzwq(Register dst, Register src) {
8834 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8835 emit_int8((unsigned char)0x0F);
8836 emit_int8((unsigned char)0xB7);
8837 emit_int8((unsigned char)(0xC0 | encode));
8838 }
8839
8840 void Assembler::mulq(Address src) {
8841 InstructionMark im(this);
8842 prefixq(src);
8843 emit_int8((unsigned char)0xF7);
8844 emit_operand(rsp, src);
8845 }
8846
8847 void Assembler::mulq(Register src) {
8848 int encode = prefixq_and_encode(src->encoding());
8849 emit_int8((unsigned char)0xF7);
8850 emit_int8((unsigned char)(0xE0 | encode));
8851 }
8852
8853 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8854 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8855 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8856 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8857 emit_int8((unsigned char)0xF6);
8858 emit_int8((unsigned char)(0xC0 | encode));
8859 }
8860
8861 void Assembler::negq(Register dst) {
8862 int encode = prefixq_and_encode(dst->encoding());
8863 emit_int8((unsigned char)0xF7);
8864 emit_int8((unsigned char)(0xD8 | encode));
8865 }
8866
8867 void Assembler::notq(Register dst) {
8868 int encode = prefixq_and_encode(dst->encoding());
8869 emit_int8((unsigned char)0xF7);
8870 emit_int8((unsigned char)(0xD0 | encode));
8871 }
8872
8873 void Assembler::orq(Address dst, int32_t imm32) {
8874 InstructionMark im(this);
8875 prefixq(dst);
8876 emit_int8((unsigned char)0x81);
8877 emit_operand(rcx, dst, 4);
8878 emit_int32(imm32);
8879 }
8880
8881 void Assembler::orq(Register dst, int32_t imm32) {
8882 (void) prefixq_and_encode(dst->encoding());
8883 emit_arith(0x81, 0xC8, dst, imm32);
8884 }
8885
8886 void Assembler::orq(Register dst, Address src) {
8887 InstructionMark im(this);
8888 prefixq(src, dst);
8889 emit_int8(0x0B);
8890 emit_operand(dst, src);
8891 }
8892
8893 void Assembler::orq(Register dst, Register src) {
8894 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8895 emit_arith(0x0B, 0xC0, dst, src);
8896 }
8897
8898 void Assembler::popa() { // 64bit
8899 movq(r15, Address(rsp, 0));
8900 movq(r14, Address(rsp, wordSize));
8901 movq(r13, Address(rsp, 2 * wordSize));
8902 movq(r12, Address(rsp, 3 * wordSize));
8903 movq(r11, Address(rsp, 4 * wordSize));
8904 movq(r10, Address(rsp, 5 * wordSize));
8905 movq(r9, Address(rsp, 6 * wordSize));
8906 movq(r8, Address(rsp, 7 * wordSize));
8907 movq(rdi, Address(rsp, 8 * wordSize));
8908 movq(rsi, Address(rsp, 9 * wordSize));
8909 movq(rbp, Address(rsp, 10 * wordSize));
8910 // skip rsp
8911 movq(rbx, Address(rsp, 12 * wordSize));
8912 movq(rdx, Address(rsp, 13 * wordSize));
8913 movq(rcx, Address(rsp, 14 * wordSize));
8914 movq(rax, Address(rsp, 15 * wordSize));
8915
8916 addq(rsp, 16 * wordSize);
8917 }
8918
8919 void Assembler::popcntq(Register dst, Address src) {
8920 assert(VM_Version::supports_popcnt(), "must support");
8921 InstructionMark im(this);
8922 emit_int8((unsigned char)0xF3);
8923 prefixq(src, dst);
8924 emit_int8((unsigned char)0x0F);
8925 emit_int8((unsigned char)0xB8);
8926 emit_operand(dst, src);
8927 }
8928
8929 void Assembler::popcntq(Register dst, Register src) {
8930 assert(VM_Version::supports_popcnt(), "must support");
8931 emit_int8((unsigned char)0xF3);
8932 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8933 emit_int8((unsigned char)0x0F);
8934 emit_int8((unsigned char)0xB8);
8935 emit_int8((unsigned char)(0xC0 | encode));
8936 }
8937
8938 void Assembler::popq(Address dst) {
8939 InstructionMark im(this);
8940 prefixq(dst);
8941 emit_int8((unsigned char)0x8F);
8942 emit_operand(rax, dst);
8943 }
8944
8945 void Assembler::pusha() { // 64bit
8946 // we have to store original rsp. ABI says that 128 bytes
8947 // below rsp are local scratch.
8948 movq(Address(rsp, -5 * wordSize), rsp);
8949
8950 subq(rsp, 16 * wordSize);
8951
8952 movq(Address(rsp, 15 * wordSize), rax);
8953 movq(Address(rsp, 14 * wordSize), rcx);
8954 movq(Address(rsp, 13 * wordSize), rdx);
8955 movq(Address(rsp, 12 * wordSize), rbx);
8956 // skip rsp
8957 movq(Address(rsp, 10 * wordSize), rbp);
8958 movq(Address(rsp, 9 * wordSize), rsi);
8959 movq(Address(rsp, 8 * wordSize), rdi);
8960 movq(Address(rsp, 7 * wordSize), r8);
8961 movq(Address(rsp, 6 * wordSize), r9);
8962 movq(Address(rsp, 5 * wordSize), r10);
8963 movq(Address(rsp, 4 * wordSize), r11);
8964 movq(Address(rsp, 3 * wordSize), r12);
8965 movq(Address(rsp, 2 * wordSize), r13);
8966 movq(Address(rsp, wordSize), r14);
8967 movq(Address(rsp, 0), r15);
8968 }
8969
8970 void Assembler::pushq(Address src) {
8971 InstructionMark im(this);
8972 prefixq(src);
8973 emit_int8((unsigned char)0xFF);
8974 emit_operand(rsi, src);
8975 }
8976
8977 void Assembler::rclq(Register dst, int imm8) {
8978 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8979 int encode = prefixq_and_encode(dst->encoding());
8980 if (imm8 == 1) {
8981 emit_int8((unsigned char)0xD1);
8982 emit_int8((unsigned char)(0xD0 | encode));
8983 } else {
8984 emit_int8((unsigned char)0xC1);
8985 emit_int8((unsigned char)(0xD0 | encode));
8986 emit_int8(imm8);
8987 }
8988 }
8989
8990 void Assembler::rcrq(Register dst, int imm8) {
8991 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8992 int encode = prefixq_and_encode(dst->encoding());
8993 if (imm8 == 1) {
8994 emit_int8((unsigned char)0xD1);
8995 emit_int8((unsigned char)(0xD8 | encode));
8996 } else {
8997 emit_int8((unsigned char)0xC1);
8998 emit_int8((unsigned char)(0xD8 | encode));
8999 emit_int8(imm8);
9000 }
9001 }
9002
9003 void Assembler::rorq(Register dst, int imm8) {
9004 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9005 int encode = prefixq_and_encode(dst->encoding());
9006 if (imm8 == 1) {
9007 emit_int8((unsigned char)0xD1);
9008 emit_int8((unsigned char)(0xC8 | encode));
9009 } else {
9010 emit_int8((unsigned char)0xC1);
9011 emit_int8((unsigned char)(0xc8 | encode));
9012 emit_int8(imm8);
9013 }
9014 }
9015
9016 void Assembler::rorxq(Register dst, Register src, int imm8) {
9017 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9018 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9019 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9020 emit_int8((unsigned char)0xF0);
9021 emit_int8((unsigned char)(0xC0 | encode));
9022 emit_int8(imm8);
9023 }
9024
9025 void Assembler::rorxd(Register dst, Register src, int imm8) {
9026 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9027 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9028 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9029 emit_int8((unsigned char)0xF0);
9030 emit_int8((unsigned char)(0xC0 | encode));
9031 emit_int8(imm8);
9032 }
9033
9034 void Assembler::sarq(Register dst, int imm8) {
9035 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9036 int encode = prefixq_and_encode(dst->encoding());
9037 if (imm8 == 1) {
9038 emit_int8((unsigned char)0xD1);
9039 emit_int8((unsigned char)(0xF8 | encode));
9040 } else {
9041 emit_int8((unsigned char)0xC1);
9042 emit_int8((unsigned char)(0xF8 | encode));
9043 emit_int8(imm8);
9044 }
9045 }
9046
9047 void Assembler::sarq(Register dst) {
9048 int encode = prefixq_and_encode(dst->encoding());
9049 emit_int8((unsigned char)0xD3);
9050 emit_int8((unsigned char)(0xF8 | encode));
9051 }
9052
9053 void Assembler::sbbq(Address dst, int32_t imm32) {
9054 InstructionMark im(this);
9055 prefixq(dst);
9056 emit_arith_operand(0x81, rbx, dst, imm32);
9057 }
9058
9059 void Assembler::sbbq(Register dst, int32_t imm32) {
9060 (void) prefixq_and_encode(dst->encoding());
9061 emit_arith(0x81, 0xD8, dst, imm32);
9062 }
9063
9064 void Assembler::sbbq(Register dst, Address src) {
9065 InstructionMark im(this);
9066 prefixq(src, dst);
9067 emit_int8(0x1B);
9068 emit_operand(dst, src);
9069 }
9070
9071 void Assembler::sbbq(Register dst, Register src) {
9072 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9073 emit_arith(0x1B, 0xC0, dst, src);
9074 }
9075
9076 void Assembler::shlq(Register dst, int imm8) {
9077 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9078 int encode = prefixq_and_encode(dst->encoding());
9079 if (imm8 == 1) {
9080 emit_int8((unsigned char)0xD1);
9081 emit_int8((unsigned char)(0xE0 | encode));
9082 } else {
9083 emit_int8((unsigned char)0xC1);
9084 emit_int8((unsigned char)(0xE0 | encode));
9085 emit_int8(imm8);
9086 }
9087 }
9088
9089 void Assembler::shlq(Register dst) {
9090 int encode = prefixq_and_encode(dst->encoding());
9091 emit_int8((unsigned char)0xD3);
9092 emit_int8((unsigned char)(0xE0 | encode));
9093 }
9094
9095 void Assembler::shrq(Register dst, int imm8) {
9096 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9097 int encode = prefixq_and_encode(dst->encoding());
9098 emit_int8((unsigned char)0xC1);
9099 emit_int8((unsigned char)(0xE8 | encode));
9100 emit_int8(imm8);
9101 }
9102
9103 void Assembler::shrq(Register dst) {
9104 int encode = prefixq_and_encode(dst->encoding());
9105 emit_int8((unsigned char)0xD3);
9106 emit_int8(0xE8 | encode);
9107 }
9108
9109 void Assembler::subq(Address dst, int32_t imm32) {
9110 InstructionMark im(this);
9111 prefixq(dst);
9112 emit_arith_operand(0x81, rbp, dst, imm32);
9113 }
9114
9115 void Assembler::subq(Address dst, Register src) {
9116 InstructionMark im(this);
9117 prefixq(dst, src);
9118 emit_int8(0x29);
9119 emit_operand(src, dst);
9120 }
9121
9122 void Assembler::subq(Register dst, int32_t imm32) {
9123 (void) prefixq_and_encode(dst->encoding());
9124 emit_arith(0x81, 0xE8, dst, imm32);
9125 }
9126
9127 // Force generation of a 4 byte immediate value even if it fits into 8bit
9128 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9129 (void) prefixq_and_encode(dst->encoding());
9130 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9131 }
9132
9133 void Assembler::subq(Register dst, Address src) {
9134 InstructionMark im(this);
9135 prefixq(src, dst);
9136 emit_int8(0x2B);
9137 emit_operand(dst, src);
9138 }
9139
9140 void Assembler::subq(Register dst, Register src) {
9141 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9142 emit_arith(0x2B, 0xC0, dst, src);
9143 }
9144
9145 void Assembler::testq(Register dst, int32_t imm32) {
9146 // not using emit_arith because test
9147 // doesn't support sign-extension of
9148 // 8bit operands
9149 int encode = dst->encoding();
9150 if (encode == 0) {
9151 prefix(REX_W);
9152 emit_int8((unsigned char)0xA9);
9153 } else {
9154 encode = prefixq_and_encode(encode);
9155 emit_int8((unsigned char)0xF7);
9156 emit_int8((unsigned char)(0xC0 | encode));
9157 }
9158 emit_int32(imm32);
9159 }
9160
9161 void Assembler::testq(Register dst, Register src) {
9162 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9163 emit_arith(0x85, 0xC0, dst, src);
9164 }
9165
9166 void Assembler::testq(Register dst, Address src) {
9167 InstructionMark im(this);
9168 prefixq(src, dst);
9169 emit_int8((unsigned char)0x85);
9170 emit_operand(dst, src);
9171 }
9172
9173 void Assembler::xaddq(Address dst, Register src) {
9174 InstructionMark im(this);
9175 prefixq(dst, src);
9176 emit_int8(0x0F);
9177 emit_int8((unsigned char)0xC1);
9178 emit_operand(src, dst);
9179 }
9180
9181 void Assembler::xchgq(Register dst, Address src) {
9182 InstructionMark im(this);
9183 prefixq(src, dst);
9184 emit_int8((unsigned char)0x87);
9185 emit_operand(dst, src);
9186 }
9187
9188 void Assembler::xchgq(Register dst, Register src) {
9189 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9190 emit_int8((unsigned char)0x87);
9191 emit_int8((unsigned char)(0xc0 | encode));
9192 }
9193
9194 void Assembler::xorq(Register dst, Register src) {
9195 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9196 emit_arith(0x33, 0xC0, dst, src);
9197 }
9198
9199 void Assembler::xorq(Register dst, Address src) {
9200 InstructionMark im(this);
9201 prefixq(src, dst);
9202 emit_int8(0x33);
9203 emit_operand(dst, src);
9204 }
9205
9206 #endif // !LP64