1 // 2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved. 3 // Copyright 2012, 2015 SAP AG. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 // 25 26 // 27 // PPC64 Architecture Description File 28 // 29 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ 31 // This information is used by the matcher and the register allocator to 32 // describe individual registers and classes of registers within the target 33 // architecture. 34 register %{ 35 //----------Architecture Description Register Definitions---------------------- 36 // General Registers 37 // "reg_def" name (register save type, C convention save type, 38 // ideal register type, encoding); 39 // 40 // Register Save Types: 41 // 42 // NS = No-Save: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, & 44 // that they do not need to be saved at call sites. 45 // 46 // SOC = Save-On-Call: The register allocator assumes that these registers 47 // can be used without saving upon entry to the method, 48 // but that they must be saved at call sites. 49 // These are called "volatiles" on ppc. 50 // 51 // SOE = Save-On-Entry: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, but they do not need to be saved at call 54 // sites. 55 // These are called "nonvolatiles" on ppc. 56 // 57 // AS = Always-Save: The register allocator assumes that these registers 58 // must be saved before using them upon entry to the 59 // method, & that they must be saved at call sites. 60 // 61 // Ideal Register Type is used to determine how to save & restore a 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64 // 65 // The encoding number is the actual bit-pattern placed into the opcodes. 66 // 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68 // Supplement Version 1.7 as of 2003-10-29. 69 // 70 // For each 64-bit register we must define two registers: the register 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72 // e.g. R3_H, which is needed by the allocator, but is not used 73 // for stores, loads, etc. 74 75 // ---------------------------- 76 // Integer/Long Registers 77 // ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148 // ---------------------------- 149 // Float/Double Registers 150 // ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229 // ---------------------------- 230 // Special Registers 231 // ---------------------------- 232 233 // Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258 // ---------------------------- 259 // Specify priority of register selection within phases of register 260 // allocation. Highest priority is first. A useful heuristic is to 261 // give registers a low priority when they are required by machine 262 // instructions, like EAX and EDX on I486, and choose no-save registers 263 // before save-on-call, & save-on-call before save-on-entry. Registers 264 // which participate in fixed calling sequences should come last. 265 // Registers which are used as pairs must fall on an even boundary. 266 267 // It's worth about 1% on SPEC geomean to get this right. 268 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g. 271 // R3_num. Therefore, R3_num may not be (and in reality is not) 272 // the same as R3->encoding()! Furthermore, we cannot make any 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. 274 // Additionally, the function 275 // static enum RC rc_class(OptoReg::Name reg ) 276 // maps a given <register>_num value to its chunk type (except for flags) 277 // and its current implementation relies on chunk0 and chunk1 having a 278 // size of 64 each. 279 280 // If you change this allocation class, please have a look at the 281 // default values for the parameters RoundRobinIntegerRegIntervalStart 282 // and RoundRobinFloatRegIntervalStart 283 284 alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326 ); 327 328 // If you change this allocation class, please have a look at the 329 // default values for the parameters RoundRobinIntegerRegIntervalStart 330 // and RoundRobinFloatRegIntervalStart 331 332 alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372 ); 373 374 alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385 ); 386 387 alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396 ); 397 398 //-------Architecture Description Register Classes----------------------- 399 400 // Several register classes are automatically defined based upon 401 // information in this architecture description. 402 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407 // 408 409 // ---------------------------- 410 // 32 Bit Register Classes 411 // ---------------------------- 412 413 // We specify registers twice, once as read/write, and once read-only. 414 // We use the read-only registers for source operands. With this, we 415 // can include preset read only registers in this class, as a hard-coded 416 // '0'-register. (We used to simulate this on ppc.) 417 418 // 32 bit registers that can be read and written i.e. these registers 419 // can be dest (or src) of normal instructions. 420 reg_class bits32_reg_rw( 421 /*R0*/ // R0 422 /*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434 /*R13*/ // system thread id 435 R14, 436 R15, 437 /*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450 /*R29,*/ // global TOC 451 R30, 452 R31 453 ); 454 455 // 32 bit registers that can only be read i.e. these registers can 456 // only be src of all instructions. 457 reg_class bits32_reg_ro( 458 /*R0*/ // R0 459 /*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471 /*R13*/ // system thread id 472 R14, 473 R15, 474 /*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487 /*R29,*/ 488 R30, 489 R31 490 ); 491 492 reg_class rscratch1_bits32_reg(R11); 493 reg_class rscratch2_bits32_reg(R12); 494 reg_class rarg1_bits32_reg(R3); 495 reg_class rarg2_bits32_reg(R4); 496 reg_class rarg3_bits32_reg(R5); 497 reg_class rarg4_bits32_reg(R6); 498 499 // ---------------------------- 500 // 64 Bit Register Classes 501 // ---------------------------- 502 // 64-bit build means 64-bit pointers means hi/lo pairs 503 504 reg_class rscratch1_bits64_reg(R11_H, R11); 505 reg_class rscratch2_bits64_reg(R12_H, R12); 506 reg_class rarg1_bits64_reg(R3_H, R3); 507 reg_class rarg2_bits64_reg(R4_H, R4); 508 reg_class rarg3_bits64_reg(R5_H, R5); 509 reg_class rarg4_bits64_reg(R6_H, R6); 510 // Thread register, 'written' by tlsLoadP, see there. 511 reg_class thread_bits64_reg(R16_H, R16); 512 513 reg_class r19_bits64_reg(R19_H, R19); 514 515 // 64 bit registers that can be read and written i.e. these registers 516 // can be dest (or src) of normal instructions. 517 reg_class bits64_reg_rw( 518 /*R0_H, R0*/ // R0 519 /*R1_H, R1*/ // SP 520 R2_H, R2, // TOC 521 R3_H, R3, 522 R4_H, R4, 523 R5_H, R5, 524 R6_H, R6, 525 R7_H, R7, 526 R8_H, R8, 527 R9_H, R9, 528 R10_H, R10, 529 R11_H, R11, 530 R12_H, R12, 531 /*R13_H, R13*/ // system thread id 532 R14_H, R14, 533 R15_H, R15, 534 /*R16_H, R16*/ // R16_thread 535 R17_H, R17, 536 R18_H, R18, 537 R19_H, R19, 538 R20_H, R20, 539 R21_H, R21, 540 R22_H, R22, 541 R23_H, R23, 542 R24_H, R24, 543 R25_H, R25, 544 R26_H, R26, 545 R27_H, R27, 546 R28_H, R28, 547 /*R29_H, R29,*/ 548 R30_H, R30, 549 R31_H, R31 550 ); 551 552 // 64 bit registers used excluding r2, r11 and r12 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses 554 // r2, r11 and r12 internally. 555 reg_class bits64_reg_leaf_call( 556 /*R0_H, R0*/ // R0 557 /*R1_H, R1*/ // SP 558 /*R2_H, R2*/ // TOC 559 R3_H, R3, 560 R4_H, R4, 561 R5_H, R5, 562 R6_H, R6, 563 R7_H, R7, 564 R8_H, R8, 565 R9_H, R9, 566 R10_H, R10, 567 /*R11_H, R11*/ 568 /*R12_H, R12*/ 569 /*R13_H, R13*/ // system thread id 570 R14_H, R14, 571 R15_H, R15, 572 /*R16_H, R16*/ // R16_thread 573 R17_H, R17, 574 R18_H, R18, 575 R19_H, R19, 576 R20_H, R20, 577 R21_H, R21, 578 R22_H, R22, 579 R23_H, R23, 580 R24_H, R24, 581 R25_H, R25, 582 R26_H, R26, 583 R27_H, R27, 584 R28_H, R28, 585 /*R29_H, R29,*/ 586 R30_H, R30, 587 R31_H, R31 588 ); 589 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall 591 // which uses r19 as inline cache internally and expanded LeafCall which uses 592 // r2, r11 and r12 internally. 593 reg_class bits64_constant_table_base( 594 /*R0_H, R0*/ // R0 595 /*R1_H, R1*/ // SP 596 /*R2_H, R2*/ // TOC 597 R3_H, R3, 598 R4_H, R4, 599 R5_H, R5, 600 R6_H, R6, 601 R7_H, R7, 602 R8_H, R8, 603 R9_H, R9, 604 R10_H, R10, 605 /*R11_H, R11*/ 606 /*R12_H, R12*/ 607 /*R13_H, R13*/ // system thread id 608 R14_H, R14, 609 R15_H, R15, 610 /*R16_H, R16*/ // R16_thread 611 R17_H, R17, 612 R18_H, R18, 613 /*R19_H, R19*/ 614 R20_H, R20, 615 R21_H, R21, 616 R22_H, R22, 617 R23_H, R23, 618 R24_H, R24, 619 R25_H, R25, 620 R26_H, R26, 621 R27_H, R27, 622 R28_H, R28, 623 /*R29_H, R29,*/ 624 R30_H, R30, 625 R31_H, R31 626 ); 627 628 // 64 bit registers that can only be read i.e. these registers can 629 // only be src of all instructions. 630 reg_class bits64_reg_ro( 631 /*R0_H, R0*/ // R0 632 R1_H, R1, 633 R2_H, R2, // TOC 634 R3_H, R3, 635 R4_H, R4, 636 R5_H, R5, 637 R6_H, R6, 638 R7_H, R7, 639 R8_H, R8, 640 R9_H, R9, 641 R10_H, R10, 642 R11_H, R11, 643 R12_H, R12, 644 /*R13_H, R13*/ // system thread id 645 R14_H, R14, 646 R15_H, R15, 647 R16_H, R16, // R16_thread 648 R17_H, R17, 649 R18_H, R18, 650 R19_H, R19, 651 R20_H, R20, 652 R21_H, R21, 653 R22_H, R22, 654 R23_H, R23, 655 R24_H, R24, 656 R25_H, R25, 657 R26_H, R26, 658 R27_H, R27, 659 R28_H, R28, 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!! 661 R30_H, R30, 662 R31_H, R31 663 ); 664 665 666 // ---------------------------- 667 // Special Class for Condition Code Flags Register 668 669 reg_class int_flags( 670 /*CCR0*/ // scratch 671 /*CCR1*/ // scratch 672 /*CCR2*/ // nv! 673 /*CCR3*/ // nv! 674 /*CCR4*/ // nv! 675 CCR5, 676 CCR6, 677 CCR7 678 ); 679 680 reg_class int_flags_ro( 681 CCR0, 682 CCR1, 683 CCR2, 684 CCR3, 685 CCR4, 686 CCR5, 687 CCR6, 688 CCR7 689 ); 690 691 reg_class int_flags_CR0(CCR0); 692 reg_class int_flags_CR1(CCR1); 693 reg_class int_flags_CR6(CCR6); 694 reg_class ctr_reg(SR_CTR); 695 696 // ---------------------------- 697 // Float Register Classes 698 // ---------------------------- 699 700 reg_class flt_reg( 701 /*F0*/ // scratch 702 F1, 703 F2, 704 F3, 705 F4, 706 F5, 707 F6, 708 F7, 709 F8, 710 F9, 711 F10, 712 F11, 713 F12, 714 F13, 715 F14, // nv! 716 F15, // nv! 717 F16, // nv! 718 F17, // nv! 719 F18, // nv! 720 F19, // nv! 721 F20, // nv! 722 F21, // nv! 723 F22, // nv! 724 F23, // nv! 725 F24, // nv! 726 F25, // nv! 727 F26, // nv! 728 F27, // nv! 729 F28, // nv! 730 F29, // nv! 731 F30, // nv! 732 F31 // nv! 733 ); 734 735 // Double precision float registers have virtual `high halves' that 736 // are needed by the allocator. 737 reg_class dbl_reg( 738 /*F0, F0_H*/ // scratch 739 F1, F1_H, 740 F2, F2_H, 741 F3, F3_H, 742 F4, F4_H, 743 F5, F5_H, 744 F6, F6_H, 745 F7, F7_H, 746 F8, F8_H, 747 F9, F9_H, 748 F10, F10_H, 749 F11, F11_H, 750 F12, F12_H, 751 F13, F13_H, 752 F14, F14_H, // nv! 753 F15, F15_H, // nv! 754 F16, F16_H, // nv! 755 F17, F17_H, // nv! 756 F18, F18_H, // nv! 757 F19, F19_H, // nv! 758 F20, F20_H, // nv! 759 F21, F21_H, // nv! 760 F22, F22_H, // nv! 761 F23, F23_H, // nv! 762 F24, F24_H, // nv! 763 F25, F25_H, // nv! 764 F26, F26_H, // nv! 765 F27, F27_H, // nv! 766 F28, F28_H, // nv! 767 F29, F29_H, // nv! 768 F30, F30_H, // nv! 769 F31, F31_H // nv! 770 ); 771 772 %} 773 774 //----------DEFINITION BLOCK--------------------------------------------------- 775 // Define name --> value mappings to inform the ADLC of an integer valued name 776 // Current support includes integer values in the range [0, 0x7FFFFFFF] 777 // Format: 778 // int_def <name> ( <int_value>, <expression>); 779 // Generated Code in ad_<arch>.hpp 780 // #define <name> (<expression>) 781 // // value == <int_value> 782 // Generated code in ad_<arch>.cpp adlc_verification() 783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 784 // 785 definitions %{ 786 // The default cost (of an ALU instruction). 787 int_def DEFAULT_COST_LOW ( 30, 30); 788 int_def DEFAULT_COST ( 100, 100); 789 int_def HUGE_COST (1000000, 1000000); 790 791 // Memory refs 792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 794 795 // Branches are even more expensive. 796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 797 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 798 %} 799 800 801 //----------SOURCE BLOCK------------------------------------------------------- 802 // This is a block of C++ code which provides values, functions, and 803 // definitions necessary in the rest of the architecture description. 804 source_hpp %{ 805 // Header information of the source block. 806 // Method declarations/definitions which are used outside 807 // the ad-scope can conveniently be defined here. 808 // 809 // To keep related declarations/definitions/uses close together, 810 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 811 812 // Returns true if Node n is followed by a MemBar node that 813 // will do an acquire. If so, this node must not do the acquire 814 // operation. 815 bool followed_by_acquire(const Node *n); 816 %} 817 818 source %{ 819 820 // Optimize load-acquire. 821 // 822 // Check if acquire is unnecessary due to following operation that does 823 // acquire anyways. 824 // Walk the pattern: 825 // 826 // n: Load.acq 827 // | 828 // MemBarAcquire 829 // | | 830 // Proj(ctrl) Proj(mem) 831 // | | 832 // MemBarRelease/Volatile 833 // 834 bool followed_by_acquire(const Node *load) { 835 assert(load->is_Load(), "So far implemented only for loads."); 836 837 // Find MemBarAcquire. 838 const Node *mba = NULL; 839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 840 const Node *out = load->fast_out(i); 841 if (out->Opcode() == Op_MemBarAcquire) { 842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 843 mba = out; 844 break; 845 } 846 } 847 if (!mba) return false; 848 849 // Find following MemBar node. 850 // 851 // The following node must be reachable by control AND memory 852 // edge to assure no other operations are in between the two nodes. 853 // 854 // So first get the Proj node, mem_proj, to use it to iterate forward. 855 Node *mem_proj = NULL; 856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 858 assert(mem_proj->is_Proj(), "only projections here"); 859 ProjNode *proj = mem_proj->as_Proj(); 860 if (proj->_con == TypeFunc::Memory && 861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 862 break; 863 } 864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 865 866 // Search MemBar behind Proj. If there are other memory operations 867 // behind the Proj we lost. 868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 869 Node *x = mem_proj->fast_out(j); 870 // Proj might have an edge to a store or load node which precedes the membar. 871 if (x->is_Mem()) return false; 872 873 // On PPC64 release and volatile are implemented by an instruction 874 // that also has acquire semantics. I.e. there is no need for an 875 // acquire before these. 876 int xop = x->Opcode(); 877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 878 // Make sure we're not missing Call/Phi/MergeMem by checking 879 // control edges. The control edge must directly lead back 880 // to the MemBarAcquire 881 Node *ctrl_proj = x->in(0); 882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 883 return true; 884 } 885 } 886 } 887 888 return false; 889 } 890 891 #define __ _masm. 892 893 // Tertiary op of a LoadP or StoreP encoding. 894 #define REGP_OP true 895 896 // **************************************************************************** 897 898 // REQUIRED FUNCTIONALITY 899 900 // !!!!! Special hack to get all type of calls to specify the byte offset 901 // from the start of the call to the point where the return address 902 // will point. 903 904 // PPC port: Removed use of lazy constant construct. 905 906 int MachCallStaticJavaNode::ret_addr_offset() { 907 // It's only a single branch-and-link instruction. 908 return 4; 909 } 910 911 int MachCallDynamicJavaNode::ret_addr_offset() { 912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 913 // postalloc expanded calls if we use inline caches and do not update method data. 914 if (UseInlineCaches) 915 return 4; 916 917 int vtable_index = this->_vtable_index; 918 if (vtable_index < 0) { 919 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 921 return 12; 922 } else { 923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 924 return 24; 925 } 926 } 927 928 int MachCallRuntimeNode::ret_addr_offset() { 929 #if defined(ABI_ELFv2) 930 return 28; 931 #else 932 return 40; 933 #endif 934 } 935 936 //============================================================================= 937 938 // condition code conversions 939 940 static int cc_to_boint(int cc) { 941 return Assembler::bcondCRbiIs0 | (cc & 8); 942 } 943 944 static int cc_to_inverse_boint(int cc) { 945 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 946 } 947 948 static int cc_to_biint(int cc, int flags_reg) { 949 return (flags_reg << 2) | (cc & 3); 950 } 951 952 //============================================================================= 953 954 // Compute padding required for nodes which need alignment. The padding 955 // is the number of bytes (not instructions) which will be inserted before 956 // the instruction. The padding must match the size of a NOP instruction. 957 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 959 return (3*4-current_offset)&31; 960 } 961 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const { 963 return (2*4-current_offset)&31; 964 } 965 966 int string_indexOf_immNode::compute_padding(int current_offset) const { 967 return (3*4-current_offset)&31; 968 } 969 970 int string_indexOfNode::compute_padding(int current_offset) const { 971 return (1*4-current_offset)&31; 972 } 973 974 int string_compareNode::compute_padding(int current_offset) const { 975 return (4*4-current_offset)&31; 976 } 977 978 int string_equals_immNode::compute_padding(int current_offset) const { 979 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). 980 return (2*4-current_offset)&31; 981 } 982 983 int string_equalsNode::compute_padding(int current_offset) const { 984 return (7*4-current_offset)&31; 985 } 986 987 int inlineCallClearArrayNode::compute_padding(int current_offset) const { 988 return (2*4-current_offset)&31; 989 } 990 991 //============================================================================= 992 993 // Indicate if the safepoint node needs the polling page as an input. 994 bool SafePointNode::needs_polling_address_input() { 995 // The address is loaded from thread by a seperate node. 996 return true; 997 } 998 999 //============================================================================= 1000 1001 // Emit an interrupt that is caught by the debugger (for debugging compiler). 1002 void emit_break(CodeBuffer &cbuf) { 1003 MacroAssembler _masm(&cbuf); 1004 __ illtrap(); 1005 } 1006 1007 #ifndef PRODUCT 1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1009 st->print("BREAKPOINT"); 1010 } 1011 #endif 1012 1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1014 emit_break(cbuf); 1015 } 1016 1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1018 return MachNode::size(ra_); 1019 } 1020 1021 //============================================================================= 1022 1023 void emit_nop(CodeBuffer &cbuf) { 1024 MacroAssembler _masm(&cbuf); 1025 __ nop(); 1026 } 1027 1028 static inline void emit_long(CodeBuffer &cbuf, int value) { 1029 *((int*)(cbuf.insts_end())) = value; 1030 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1031 } 1032 1033 //============================================================================= 1034 1035 %} // interrupt source 1036 1037 source_hpp %{ // Header information of the source block. 1038 1039 //-------------------------------------------------------------- 1040 //---< Used for optimization in Compile::Shorten_branches >--- 1041 //-------------------------------------------------------------- 1042 1043 const uint trampoline_stub_size = 6 * BytesPerInstWord; 1044 1045 class CallStubImpl { 1046 1047 public: 1048 1049 // Emit call stub, compiled java to interpreter. 1050 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1051 1052 // Size of call trampoline stub. 1053 // This doesn't need to be accurate to the byte, but it 1054 // must be larger than or equal to the real size of the stub. 1055 static uint size_call_trampoline() { 1056 return trampoline_stub_size; 1057 } 1058 1059 // number of relocations needed by a call trampoline stub 1060 static uint reloc_call_trampoline() { 1061 return 5; 1062 } 1063 1064 }; 1065 1066 %} // end source_hpp 1067 1068 source %{ 1069 1070 // Emit a trampoline stub for a call to a target which is too far away. 1071 // 1072 // code sequences: 1073 // 1074 // call-site: 1075 // branch-and-link to <destination> or <trampoline stub> 1076 // 1077 // Related trampoline stub for this call-site in the stub section: 1078 // load the call target from the constant pool 1079 // branch via CTR (LR/link still points to the call-site above) 1080 1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1082 // Start the stub. 1083 address stub = __ start_a_stub(Compile::MAX_stubs_size/2); 1084 if (stub == NULL) { 1085 ciEnv::current()->record_failure("CodeCache is full"); 1086 return; 1087 } 1088 1089 // For java_to_interp stubs we use R11_scratch1 as scratch register 1090 // and in call trampoline stubs we use R12_scratch2. This way we 1091 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1092 Register reg_scratch = R12_scratch2; 1093 1094 // Create a trampoline stub relocation which relates this trampoline stub 1095 // with the call instruction at insts_call_instruction_offset in the 1096 // instructions code-section. 1097 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); 1098 const int stub_start_offset = __ offset(); 1099 1100 // Now, create the trampoline stub's code: 1101 // - load the TOC 1102 // - load the call target from the constant pool 1103 // - call 1104 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1105 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); 1106 __ mtctr(reg_scratch); 1107 __ bctr(); 1108 1109 const address stub_start_addr = __ addr_at(stub_start_offset); 1110 1111 // FIXME: Assert that the trampoline stub can be identified and patched. 1112 1113 // Assert that the encoded destination_toc_offset can be identified and that it is correct. 1114 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), 1115 "encoded offset into the constant pool must match"); 1116 // Trampoline_stub_size should be good. 1117 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); 1118 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 1119 1120 // End the stub. 1121 __ end_a_stub(); 1122 } 1123 1124 //============================================================================= 1125 1126 // Emit an inline branch-and-link call and a related trampoline stub. 1127 // 1128 // code sequences: 1129 // 1130 // call-site: 1131 // branch-and-link to <destination> or <trampoline stub> 1132 // 1133 // Related trampoline stub for this call-site in the stub section: 1134 // load the call target from the constant pool 1135 // branch via CTR (LR/link still points to the call-site above) 1136 // 1137 1138 typedef struct { 1139 int insts_call_instruction_offset; 1140 int ret_addr_offset; 1141 } EmitCallOffsets; 1142 1143 // Emit a branch-and-link instruction that branches to a trampoline. 1144 // - Remember the offset of the branch-and-link instruction. 1145 // - Add a relocation at the branch-and-link instruction. 1146 // - Emit a branch-and-link. 1147 // - Remember the return pc offset. 1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1149 EmitCallOffsets offsets = { -1, -1 }; 1150 const int start_offset = __ offset(); 1151 offsets.insts_call_instruction_offset = __ offset(); 1152 1153 // No entry point given, use the current pc. 1154 if (entry_point == NULL) entry_point = __ pc(); 1155 1156 if (!Compile::current()->in_scratch_emit_size()) { 1157 // Put the entry point as a constant into the constant pool. 1158 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1159 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1160 1161 // Emit the trampoline stub which will be related to the branch-and-link below. 1162 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1163 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full. 1164 __ relocate(rtype); 1165 } 1166 1167 // Note: At this point we do not have the address of the trampoline 1168 // stub, and the entry point might be too far away for bl, so __ pc() 1169 // serves as dummy and the bl will be patched later. 1170 __ bl((address) __ pc()); 1171 1172 offsets.ret_addr_offset = __ offset() - start_offset; 1173 1174 return offsets; 1175 } 1176 1177 //============================================================================= 1178 1179 // Factory for creating loadConL* nodes for large/small constant pool. 1180 1181 static inline jlong replicate_immF(float con) { 1182 // Replicate float con 2 times and pack into vector. 1183 int val = *((int*)&con); 1184 jlong lval = val; 1185 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1186 return lval; 1187 } 1188 1189 //============================================================================= 1190 1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1192 int Compile::ConstantTable::calculate_table_base_offset() const { 1193 return 0; // absolute addressing, no offset 1194 } 1195 1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1198 iRegPdstOper *op_dst = new iRegPdstOper(); 1199 MachNode *m1 = new loadToc_hiNode(); 1200 MachNode *m2 = new loadToc_loNode(); 1201 1202 m1->add_req(NULL); 1203 m2->add_req(NULL, m1); 1204 m1->_opnds[0] = op_dst; 1205 m2->_opnds[0] = op_dst; 1206 m2->_opnds[1] = op_dst; 1207 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1208 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1209 nodes->push(m1); 1210 nodes->push(m2); 1211 } 1212 1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1214 // Is postalloc expanded. 1215 ShouldNotReachHere(); 1216 } 1217 1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1219 return 0; 1220 } 1221 1222 #ifndef PRODUCT 1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1224 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1225 } 1226 #endif 1227 1228 //============================================================================= 1229 1230 #ifndef PRODUCT 1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1232 Compile* C = ra_->C; 1233 const long framesize = C->frame_slots() << LogBytesPerInt; 1234 1235 st->print("PROLOG\n\t"); 1236 if (C->need_stack_bang(framesize)) { 1237 st->print("stack_overflow_check\n\t"); 1238 } 1239 1240 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1241 st->print("save return pc\n\t"); 1242 st->print("push frame %ld\n\t", -framesize); 1243 } 1244 } 1245 #endif 1246 1247 // Macro used instead of the common __ to emulate the pipes of PPC. 1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though 1250 // still no scheduling of this code is possible, the micro scheduler is aware of the 1251 // code and can update its internal data. The following mechanism is used to achieve this: 1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a 1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1254 #if 0 // TODO: PPC port 1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1256 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1257 _masm. 1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1259 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1261 C->hb_scheduling()->_pdScheduling->advance_offset 1262 #else 1263 #define ___(op) if (UsePower6SchedulerPPC64) \ 1264 Unimplemented(); \ 1265 _masm. 1266 #define ___stop if (UsePower6SchedulerPPC64) \ 1267 Unimplemented() 1268 #define ___advance if (UsePower6SchedulerPPC64) \ 1269 Unimplemented() 1270 #endif 1271 1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1273 Compile* C = ra_->C; 1274 MacroAssembler _masm(&cbuf); 1275 1276 const long framesize = C->frame_size_in_bytes(); 1277 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1278 1279 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1280 1281 const Register return_pc = R20; // Must match return_addr() in frame section. 1282 const Register callers_sp = R21; 1283 const Register push_frame_temp = R22; 1284 const Register toc_temp = R23; 1285 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1286 1287 if (method_is_frameless) { 1288 // Add nop at beginning of all frameless methods to prevent any 1289 // oop instructions from getting overwritten by make_not_entrant 1290 // (patching attempt would fail). 1291 ___(nop) nop(); 1292 } else { 1293 // Get return pc. 1294 ___(mflr) mflr(return_pc); 1295 } 1296 1297 // Calls to C2R adapters often do not accept exceptional returns. 1298 // We require that their callers must bang for them. But be 1299 // careful, because some VM calls (such as call site linkage) can 1300 // use several kilobytes of stack. But the stack safety zone should 1301 // account for that. See bugs 4446381, 4468289, 4497237. 1302 1303 int bangsize = C->bang_size_in_bytes(); 1304 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1305 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1306 // Unfortunately we cannot use the function provided in 1307 // assembler.cpp as we have to emulate the pipes. So I had to 1308 // insert the code of generate_stack_overflow_check(), see 1309 // assembler.cpp for some illuminative comments. 1310 const int page_size = os::vm_page_size(); 1311 int bang_end = StackShadowPages * page_size; 1312 1313 // This is how far the previous frame's stack banging extended. 1314 const int bang_end_safe = bang_end; 1315 1316 if (bangsize > page_size) { 1317 bang_end += bangsize; 1318 } 1319 1320 int bang_offset = bang_end_safe; 1321 1322 while (bang_offset <= bang_end) { 1323 // Need at least one stack bang at end of shadow zone. 1324 1325 // Again I had to copy code, this time from assembler_ppc.cpp, 1326 // bang_stack_with_offset - see there for comments. 1327 1328 // Stack grows down, caller passes positive offset. 1329 assert(bang_offset > 0, "must bang with positive offset"); 1330 1331 long stdoffset = -bang_offset; 1332 1333 if (Assembler::is_simm(stdoffset, 16)) { 1334 // Signed 16 bit offset, a simple std is ok. 1335 if (UseLoadInstructionsForStackBangingPPC64) { 1336 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1337 } else { 1338 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1339 } 1340 } else if (Assembler::is_simm(stdoffset, 31)) { 1341 // Use largeoffset calculations for addis & ld/std. 1342 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1343 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1344 1345 Register tmp = R11; 1346 ___(addis) addis(tmp, R1_SP, hi); 1347 if (UseLoadInstructionsForStackBangingPPC64) { 1348 ___(ld) ld(R0, lo, tmp); 1349 } else { 1350 ___(std) std(R0, lo, tmp); 1351 } 1352 } else { 1353 ShouldNotReachHere(); 1354 } 1355 1356 bang_offset += page_size; 1357 } 1358 // R11 trashed 1359 } // C->need_stack_bang(framesize) && UseStackBanging 1360 1361 unsigned int bytes = (unsigned int)framesize; 1362 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1363 ciMethod *currMethod = C->method(); 1364 1365 // Optimized version for most common case. 1366 if (UsePower6SchedulerPPC64 && 1367 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1368 !(false /* ConstantsALot TODO: PPC port*/)) { 1369 ___(or) mr(callers_sp, R1_SP); 1370 ___(std) std(return_pc, _abi(lr), R1_SP); 1371 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1372 return; 1373 } 1374 1375 if (!method_is_frameless) { 1376 // Get callers sp. 1377 ___(or) mr(callers_sp, R1_SP); 1378 1379 // Push method's frame, modifies SP. 1380 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1381 // The ABI is already accounted for in 'framesize' via the 1382 // 'out_preserve' area. 1383 Register tmp = push_frame_temp; 1384 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1385 if (Assembler::is_simm(-offset, 16)) { 1386 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1387 } else { 1388 long x = -offset; 1389 // Had to insert load_const(tmp, -offset). 1390 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1391 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1392 ___(rldicr) sldi(tmp, tmp, 32); 1393 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1394 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1395 1396 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1397 } 1398 } 1399 #if 0 // TODO: PPC port 1400 // For testing large constant pools, emit a lot of constants to constant pool. 1401 // "Randomize" const_size. 1402 if (ConstantsALot) { 1403 const int num_consts = const_size(); 1404 for (int i = 0; i < num_consts; i++) { 1405 __ long_constant(0xB0B5B00BBABE); 1406 } 1407 } 1408 #endif 1409 if (!method_is_frameless) { 1410 // Save return pc. 1411 ___(std) std(return_pc, _abi(lr), callers_sp); 1412 } 1413 } 1414 #undef ___ 1415 #undef ___stop 1416 #undef ___advance 1417 1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1419 // Variable size. determine dynamically. 1420 return MachNode::size(ra_); 1421 } 1422 1423 int MachPrologNode::reloc() const { 1424 // Return number of relocatable values contained in this instruction. 1425 return 1; // 1 reloc entry for load_const(toc). 1426 } 1427 1428 //============================================================================= 1429 1430 #ifndef PRODUCT 1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1432 Compile* C = ra_->C; 1433 1434 st->print("EPILOG\n\t"); 1435 st->print("restore return pc\n\t"); 1436 st->print("pop frame\n\t"); 1437 1438 if (do_polling() && C->is_method_compilation()) { 1439 st->print("touch polling page\n\t"); 1440 } 1441 } 1442 #endif 1443 1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1445 Compile* C = ra_->C; 1446 MacroAssembler _masm(&cbuf); 1447 1448 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1449 assert(framesize >= 0, "negative frame-size?"); 1450 1451 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1452 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1453 const Register return_pc = R11; 1454 const Register polling_page = R12; 1455 1456 if (!method_is_frameless) { 1457 // Restore return pc relative to callers' sp. 1458 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1459 } 1460 1461 if (method_needs_polling) { 1462 if (LoadPollAddressFromThread) { 1463 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1464 Unimplemented(); 1465 } else { 1466 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1467 } 1468 } 1469 1470 if (!method_is_frameless) { 1471 // Move return pc to LR. 1472 __ mtlr(return_pc); 1473 // Pop frame (fixed frame-size). 1474 __ addi(R1_SP, R1_SP, (int)framesize); 1475 } 1476 1477 if (method_needs_polling) { 1478 // We need to mark the code position where the load from the safepoint 1479 // polling page was emitted as relocInfo::poll_return_type here. 1480 __ relocate(relocInfo::poll_return_type); 1481 __ load_from_polling_page(polling_page); 1482 } 1483 } 1484 1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1486 // Variable size. Determine dynamically. 1487 return MachNode::size(ra_); 1488 } 1489 1490 int MachEpilogNode::reloc() const { 1491 // Return number of relocatable values contained in this instruction. 1492 return 1; // 1 for load_from_polling_page. 1493 } 1494 1495 const Pipeline * MachEpilogNode::pipeline() const { 1496 return MachNode::pipeline_class(); 1497 } 1498 1499 // This method seems to be obsolete. It is declared in machnode.hpp 1500 // and defined in all *.ad files, but it is never called. Should we 1501 // get rid of it? 1502 int MachEpilogNode::safepoint_offset() const { 1503 assert(do_polling(), "no return for this epilog node"); 1504 return 0; 1505 } 1506 1507 #if 0 // TODO: PPC port 1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1509 MacroAssembler _masm(&cbuf); 1510 if (LoadPollAddressFromThread) { 1511 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1512 } else { 1513 _masm.nop(); 1514 } 1515 } 1516 1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1518 if (LoadPollAddressFromThread) { 1519 return 4; 1520 } else { 1521 return 4; 1522 } 1523 } 1524 1525 #ifndef PRODUCT 1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1527 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1528 } 1529 #endif 1530 1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1532 return RSCRATCH1_BITS64_REG_mask(); 1533 } 1534 #endif // PPC port 1535 1536 // ============================================================================= 1537 1538 // Figure out which register class each belongs in: rc_int, rc_float or 1539 // rc_stack. 1540 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1541 1542 static enum RC rc_class(OptoReg::Name reg) { 1543 // Return the register class for the given register. The given register 1544 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1545 // enumeration in adGlobals_ppc.hpp. 1546 1547 if (reg == OptoReg::Bad) return rc_bad; 1548 1549 // We have 64 integer register halves, starting at index 0. 1550 if (reg < 64) return rc_int; 1551 1552 // We have 64 floating-point register halves, starting at index 64. 1553 if (reg < 64+64) return rc_float; 1554 1555 // Between float regs & stack are the flags regs. 1556 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1557 1558 return rc_stack; 1559 } 1560 1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1562 bool do_print, Compile* C, outputStream *st) { 1563 1564 assert(opcode == Assembler::LD_OPCODE || 1565 opcode == Assembler::STD_OPCODE || 1566 opcode == Assembler::LWZ_OPCODE || 1567 opcode == Assembler::STW_OPCODE || 1568 opcode == Assembler::LFD_OPCODE || 1569 opcode == Assembler::STFD_OPCODE || 1570 opcode == Assembler::LFS_OPCODE || 1571 opcode == Assembler::STFS_OPCODE, 1572 "opcode not supported"); 1573 1574 if (cbuf) { 1575 int d = 1576 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1577 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1578 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1579 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1580 } 1581 #ifndef PRODUCT 1582 else if (do_print) { 1583 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1584 op_str, 1585 Matcher::regName[reg], 1586 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1587 } 1588 #endif 1589 return 4; // size 1590 } 1591 1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1593 Compile* C = ra_->C; 1594 1595 // Get registers to move. 1596 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1597 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1598 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1599 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1600 1601 enum RC src_hi_rc = rc_class(src_hi); 1602 enum RC src_lo_rc = rc_class(src_lo); 1603 enum RC dst_hi_rc = rc_class(dst_hi); 1604 enum RC dst_lo_rc = rc_class(dst_lo); 1605 1606 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1607 if (src_hi != OptoReg::Bad) 1608 assert((src_lo&1)==0 && src_lo+1==src_hi && 1609 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1610 "expected aligned-adjacent pairs"); 1611 // Generate spill code! 1612 int size = 0; 1613 1614 if (src_lo == dst_lo && src_hi == dst_hi) 1615 return size; // Self copy, no move. 1616 1617 // -------------------------------------- 1618 // Memory->Memory Spill. Use R0 to hold the value. 1619 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1620 int src_offset = ra_->reg2offset(src_lo); 1621 int dst_offset = ra_->reg2offset(dst_lo); 1622 if (src_hi != OptoReg::Bad) { 1623 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1624 "expected same type of move for high parts"); 1625 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1626 if (!cbuf && !do_size) st->print("\n\t"); 1627 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1628 } else { 1629 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1630 if (!cbuf && !do_size) st->print("\n\t"); 1631 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1632 } 1633 return size; 1634 } 1635 1636 // -------------------------------------- 1637 // Check for float->int copy; requires a trip through memory. 1638 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1639 Unimplemented(); 1640 } 1641 1642 // -------------------------------------- 1643 // Check for integer reg-reg copy. 1644 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1645 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1646 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1647 size = (Rsrc != Rdst) ? 4 : 0; 1648 1649 if (cbuf) { 1650 MacroAssembler _masm(cbuf); 1651 if (size) { 1652 __ mr(Rdst, Rsrc); 1653 } 1654 } 1655 #ifndef PRODUCT 1656 else if (!do_size) { 1657 if (size) { 1658 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1659 } else { 1660 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1661 } 1662 } 1663 #endif 1664 return size; 1665 } 1666 1667 // Check for integer store. 1668 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1669 int dst_offset = ra_->reg2offset(dst_lo); 1670 if (src_hi != OptoReg::Bad) { 1671 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1672 "expected same type of move for high parts"); 1673 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1674 } else { 1675 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1676 } 1677 return size; 1678 } 1679 1680 // Check for integer load. 1681 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1682 int src_offset = ra_->reg2offset(src_lo); 1683 if (src_hi != OptoReg::Bad) { 1684 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1685 "expected same type of move for high parts"); 1686 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1687 } else { 1688 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1689 } 1690 return size; 1691 } 1692 1693 // Check for float reg-reg copy. 1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1695 if (cbuf) { 1696 MacroAssembler _masm(cbuf); 1697 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1698 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1699 __ fmr(Rdst, Rsrc); 1700 } 1701 #ifndef PRODUCT 1702 else if (!do_size) { 1703 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1704 } 1705 #endif 1706 return 4; 1707 } 1708 1709 // Check for float store. 1710 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1711 int dst_offset = ra_->reg2offset(dst_lo); 1712 if (src_hi != OptoReg::Bad) { 1713 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1714 "expected same type of move for high parts"); 1715 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1716 } else { 1717 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1718 } 1719 return size; 1720 } 1721 1722 // Check for float load. 1723 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1724 int src_offset = ra_->reg2offset(src_lo); 1725 if (src_hi != OptoReg::Bad) { 1726 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1727 "expected same type of move for high parts"); 1728 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1729 } else { 1730 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1731 } 1732 return size; 1733 } 1734 1735 // -------------------------------------------------------------------- 1736 // Check for hi bits still needing moving. Only happens for misaligned 1737 // arguments to native calls. 1738 if (src_hi == dst_hi) 1739 return size; // Self copy; no move. 1740 1741 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1742 ShouldNotReachHere(); // Unimplemented 1743 return 0; 1744 } 1745 1746 #ifndef PRODUCT 1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1748 if (!ra_) 1749 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1750 else 1751 implementation(NULL, ra_, false, st); 1752 } 1753 #endif 1754 1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1756 implementation(&cbuf, ra_, false, NULL); 1757 } 1758 1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1760 return implementation(NULL, ra_, true, NULL); 1761 } 1762 1763 #if 0 // TODO: PPC port 1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1765 #ifndef PRODUCT 1766 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1767 #endif 1768 assert(ra_->node_regs_max_index() != 0, ""); 1769 1770 // Get registers to move. 1771 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1772 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1773 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1774 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1775 1776 enum RC src_lo_rc = rc_class(src_lo); 1777 enum RC dst_lo_rc = rc_class(dst_lo); 1778 1779 if (src_lo == dst_lo && src_hi == dst_hi) 1780 return ppc64Opcode_none; // Self copy, no move. 1781 1782 // -------------------------------------- 1783 // Memory->Memory Spill. Use R0 to hold the value. 1784 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1785 return ppc64Opcode_compound; 1786 } 1787 1788 // -------------------------------------- 1789 // Check for float->int copy; requires a trip through memory. 1790 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1791 Unimplemented(); 1792 } 1793 1794 // -------------------------------------- 1795 // Check for integer reg-reg copy. 1796 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1797 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1798 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1799 if (Rsrc == Rdst) { 1800 return ppc64Opcode_none; 1801 } else { 1802 return ppc64Opcode_or; 1803 } 1804 } 1805 1806 // Check for integer store. 1807 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1808 if (src_hi != OptoReg::Bad) { 1809 return ppc64Opcode_std; 1810 } else { 1811 return ppc64Opcode_stw; 1812 } 1813 } 1814 1815 // Check for integer load. 1816 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1817 if (src_hi != OptoReg::Bad) { 1818 return ppc64Opcode_ld; 1819 } else { 1820 return ppc64Opcode_lwz; 1821 } 1822 } 1823 1824 // Check for float reg-reg copy. 1825 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1826 return ppc64Opcode_fmr; 1827 } 1828 1829 // Check for float store. 1830 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1831 if (src_hi != OptoReg::Bad) { 1832 return ppc64Opcode_stfd; 1833 } else { 1834 return ppc64Opcode_stfs; 1835 } 1836 } 1837 1838 // Check for float load. 1839 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1840 if (src_hi != OptoReg::Bad) { 1841 return ppc64Opcode_lfd; 1842 } else { 1843 return ppc64Opcode_lfs; 1844 } 1845 } 1846 1847 // -------------------------------------------------------------------- 1848 // Check for hi bits still needing moving. Only happens for misaligned 1849 // arguments to native calls. 1850 if (src_hi == dst_hi) { 1851 return ppc64Opcode_none; // Self copy; no move. 1852 } 1853 1854 ShouldNotReachHere(); 1855 return ppc64Opcode_undefined; 1856 } 1857 #endif // PPC port 1858 1859 #ifndef PRODUCT 1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1861 st->print("NOP \t// %d nops to pad for loops.", _count); 1862 } 1863 #endif 1864 1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1866 MacroAssembler _masm(&cbuf); 1867 // _count contains the number of nops needed for padding. 1868 for (int i = 0; i < _count; i++) { 1869 __ nop(); 1870 } 1871 } 1872 1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1874 return _count * 4; 1875 } 1876 1877 #ifndef PRODUCT 1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1879 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1880 char reg_str[128]; 1881 ra_->dump_register(this, reg_str); 1882 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset); 1883 } 1884 #endif 1885 1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1887 MacroAssembler _masm(&cbuf); 1888 1889 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1890 int reg = ra_->get_encode(this); 1891 1892 if (Assembler::is_simm(offset, 16)) { 1893 __ addi(as_Register(reg), R1, offset); 1894 } else { 1895 ShouldNotReachHere(); 1896 } 1897 } 1898 1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1900 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1901 return 4; 1902 } 1903 1904 #ifndef PRODUCT 1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1906 st->print_cr("---- MachUEPNode ----"); 1907 st->print_cr("..."); 1908 } 1909 #endif 1910 1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1912 // This is the unverified entry point. 1913 MacroAssembler _masm(&cbuf); 1914 1915 // Inline_cache contains a klass. 1916 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1917 Register receiver_klass = R12_scratch2; // tmp 1918 1919 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 1920 assert(R11_scratch1 == R11, "need prologue scratch register"); 1921 1922 // Check for NULL argument if we don't have implicit null checks. 1923 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 1924 if (TrapBasedNullChecks) { 1925 __ trap_null_check(R3_ARG1); 1926 } else { 1927 Label valid; 1928 __ cmpdi(CCR0, R3_ARG1, 0); 1929 __ bne_predict_taken(CCR0, valid); 1930 // We have a null argument, branch to ic_miss_stub. 1931 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1932 relocInfo::runtime_call_type); 1933 __ bind(valid); 1934 } 1935 } 1936 // Assume argument is not NULL, load klass from receiver. 1937 __ load_klass(receiver_klass, R3_ARG1); 1938 1939 if (TrapBasedICMissChecks) { 1940 __ trap_ic_miss_check(receiver_klass, ic_klass); 1941 } else { 1942 Label valid; 1943 __ cmpd(CCR0, receiver_klass, ic_klass); 1944 __ beq_predict_taken(CCR0, valid); 1945 // We have an unexpected klass, branch to ic_miss_stub. 1946 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1947 relocInfo::runtime_call_type); 1948 __ bind(valid); 1949 } 1950 1951 // Argument is valid and klass is as expected, continue. 1952 } 1953 1954 #if 0 // TODO: PPC port 1955 // Optimize UEP code on z (save a load_const() call in main path). 1956 int MachUEPNode::ep_offset() { 1957 return 0; 1958 } 1959 #endif 1960 1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1962 // Variable size. Determine dynamically. 1963 return MachNode::size(ra_); 1964 } 1965 1966 //============================================================================= 1967 1968 %} // interrupt source 1969 1970 source_hpp %{ // Header information of the source block. 1971 1972 class HandlerImpl { 1973 1974 public: 1975 1976 static int emit_exception_handler(CodeBuffer &cbuf); 1977 static int emit_deopt_handler(CodeBuffer& cbuf); 1978 1979 static uint size_exception_handler() { 1980 // The exception_handler is a b64_patchable. 1981 return MacroAssembler::b64_patchable_size; 1982 } 1983 1984 static uint size_deopt_handler() { 1985 // The deopt_handler is a bl64_patchable. 1986 return MacroAssembler::bl64_patchable_size; 1987 } 1988 1989 }; 1990 1991 %} // end source_hpp 1992 1993 source %{ 1994 1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1996 MacroAssembler _masm(&cbuf); 1997 1998 address base = __ start_a_stub(size_exception_handler()); 1999 if (base == NULL) return 0; // CodeBuffer::expand failed 2000 2001 int offset = __ offset(); 2002 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 2003 relocInfo::runtime_call_type); 2004 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 2005 __ end_a_stub(); 2006 2007 return offset; 2008 } 2009 2010 // The deopt_handler is like the exception handler, but it calls to 2011 // the deoptimization blob instead of jumping to the exception blob. 2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 2013 MacroAssembler _masm(&cbuf); 2014 2015 address base = __ start_a_stub(size_deopt_handler()); 2016 if (base == NULL) return 0; // CodeBuffer::expand failed 2017 2018 int offset = __ offset(); 2019 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 2020 relocInfo::runtime_call_type); 2021 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 2022 __ end_a_stub(); 2023 2024 return offset; 2025 } 2026 2027 //============================================================================= 2028 2029 // Use a frame slots bias for frameless methods if accessing the stack. 2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 2031 if (as_Register(reg_enc) == R1_SP) { 2032 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 2033 } 2034 return 0; 2035 } 2036 2037 const bool Matcher::match_rule_supported(int opcode) { 2038 if (!has_match_rule(opcode)) 2039 return false; 2040 2041 switch (opcode) { 2042 case Op_SqrtD: 2043 return VM_Version::has_fsqrt(); 2044 case Op_CountLeadingZerosI: 2045 case Op_CountLeadingZerosL: 2046 case Op_CountTrailingZerosI: 2047 case Op_CountTrailingZerosL: 2048 if (!UseCountLeadingZerosInstructionsPPC64) 2049 return false; 2050 break; 2051 2052 case Op_PopCountI: 2053 case Op_PopCountL: 2054 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2055 2056 case Op_StrComp: 2057 return SpecialStringCompareTo; 2058 case Op_StrEquals: 2059 return SpecialStringEquals; 2060 case Op_StrIndexOf: 2061 return SpecialStringIndexOf; 2062 } 2063 2064 return true; // Per default match rules are supported. 2065 } 2066 2067 const int Matcher::float_pressure(int default_pressure_threshold) { 2068 return default_pressure_threshold; 2069 } 2070 2071 int Matcher::regnum_to_fpu_offset(int regnum) { 2072 // No user for this method? 2073 Unimplemented(); 2074 return 999; 2075 } 2076 2077 const bool Matcher::convL2FSupported(void) { 2078 // fcfids can do the conversion (>= Power7). 2079 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2080 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2081 } 2082 2083 // Vector width in bytes. 2084 const int Matcher::vector_width_in_bytes(BasicType bt) { 2085 assert(MaxVectorSize == 8, ""); 2086 return 8; 2087 } 2088 2089 // Vector ideal reg. 2090 const int Matcher::vector_ideal_reg(int size) { 2091 assert(MaxVectorSize == 8 && size == 8, ""); 2092 return Op_RegL; 2093 } 2094 2095 const int Matcher::vector_shift_count_ideal_reg(int size) { 2096 fatal("vector shift is not supported"); 2097 return Node::NotAMachineReg; 2098 } 2099 2100 // Limits on vector size (number of elements) loaded into vector. 2101 const int Matcher::max_vector_size(const BasicType bt) { 2102 assert(is_java_primitive(bt), "only primitive type vectors"); 2103 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2104 } 2105 2106 const int Matcher::min_vector_size(const BasicType bt) { 2107 return max_vector_size(bt); // Same as max. 2108 } 2109 2110 // PPC doesn't support misaligned vectors store/load. 2111 const bool Matcher::misaligned_vectors_ok() { 2112 return false; 2113 } 2114 2115 // PPC AES support not yet implemented 2116 const bool Matcher::pass_original_key_for_aes() { 2117 return false; 2118 } 2119 2120 // RETURNS: whether this branch offset is short enough that a short 2121 // branch can be used. 2122 // 2123 // If the platform does not provide any short branch variants, then 2124 // this method should return `false' for offset 0. 2125 // 2126 // `Compile::Fill_buffer' will decide on basis of this information 2127 // whether to do the pass `Compile::Shorten_branches' at all. 2128 // 2129 // And `Compile::Shorten_branches' will decide on basis of this 2130 // information whether to replace particular branch sites by short 2131 // ones. 2132 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2133 // Is the offset within the range of a ppc64 pc relative branch? 2134 bool b; 2135 2136 const int safety_zone = 3 * BytesPerInstWord; 2137 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2138 29 - 16 + 1 + 2); 2139 return b; 2140 } 2141 2142 const bool Matcher::isSimpleConstant64(jlong value) { 2143 // Probably always true, even if a temp register is required. 2144 return true; 2145 } 2146 /* TODO: PPC port 2147 // Make a new machine dependent decode node (with its operands). 2148 MachTypeNode *Matcher::make_decode_node() { 2149 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2150 "This method is only implemented for unscaled cOops mode so far"); 2151 MachTypeNode *decode = new decodeN_unscaledNode(); 2152 decode->set_opnd_array(0, new iRegPdstOper()); 2153 decode->set_opnd_array(1, new iRegNsrcOper()); 2154 return decode; 2155 } 2156 */ 2157 // Threshold size for cleararray. 2158 const int Matcher::init_array_short_size = 8 * BytesPerLong; 2159 2160 // false => size gets scaled to BytesPerLong, ok. 2161 const bool Matcher::init_array_count_is_in_bytes = false; 2162 2163 // Use conditional move (CMOVL) on Power7. 2164 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2165 2166 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2167 // fsel doesn't accept a condition register as input, so this would be slightly different. 2168 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2169 2170 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2171 const bool Matcher::require_postalloc_expand = true; 2172 2173 // Should the Matcher clone shifts on addressing modes, expecting them to 2174 // be subsumed into complex addressing expressions or compute them into 2175 // registers? True for Intel but false for most RISCs. 2176 const bool Matcher::clone_shift_expressions = false; 2177 2178 // Do we need to mask the count passed to shift instructions or does 2179 // the cpu only look at the lower 5/6 bits anyway? 2180 // PowerPC requires masked shift counts. 2181 const bool Matcher::need_masked_shift_count = true; 2182 2183 // This affects two different things: 2184 // - how Decode nodes are matched 2185 // - how ImplicitNullCheck opportunities are recognized 2186 // If true, the matcher will try to remove all Decodes and match them 2187 // (as operands) into nodes. NullChecks are not prepared to deal with 2188 // Decodes by final_graph_reshaping(). 2189 // If false, final_graph_reshaping() forces the decode behind the Cmp 2190 // for a NullCheck. The matcher matches the Decode node into a register. 2191 // Implicit_null_check optimization moves the Decode along with the 2192 // memory operation back up before the NullCheck. 2193 bool Matcher::narrow_oop_use_complex_address() { 2194 // TODO: PPC port if (MatchDecodeNodes) return true; 2195 return false; 2196 } 2197 2198 bool Matcher::narrow_klass_use_complex_address() { 2199 NOT_LP64(ShouldNotCallThis()); 2200 assert(UseCompressedClassPointers, "only for compressed klass code"); 2201 // TODO: PPC port if (MatchDecodeNodes) return true; 2202 return false; 2203 } 2204 2205 // Is it better to copy float constants, or load them directly from memory? 2206 // Intel can load a float constant from a direct address, requiring no 2207 // extra registers. Most RISCs will have to materialize an address into a 2208 // register first, so they would do better to copy the constant from stack. 2209 const bool Matcher::rematerialize_float_constants = false; 2210 2211 // If CPU can load and store mis-aligned doubles directly then no fixup is 2212 // needed. Else we split the double into 2 integer pieces and move it 2213 // piece-by-piece. Only happens when passing doubles into C code as the 2214 // Java calling convention forces doubles to be aligned. 2215 const bool Matcher::misaligned_doubles_ok = true; 2216 2217 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2218 Unimplemented(); 2219 } 2220 2221 // Advertise here if the CPU requires explicit rounding operations 2222 // to implement the UseStrictFP mode. 2223 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2224 2225 // Do floats take an entire double register or just half? 2226 // 2227 // A float occupies a ppc64 double register. For the allocator, a 2228 // ppc64 double register appears as a pair of float registers. 2229 bool Matcher::float_in_double() { return true; } 2230 2231 // Do ints take an entire long register or just half? 2232 // The relevant question is how the int is callee-saved: 2233 // the whole long is written but de-opt'ing will have to extract 2234 // the relevant 32 bits. 2235 const bool Matcher::int_in_long = true; 2236 2237 // Constants for c2c and c calling conventions. 2238 2239 const MachRegisterNumbers iarg_reg[8] = { 2240 R3_num, R4_num, R5_num, R6_num, 2241 R7_num, R8_num, R9_num, R10_num 2242 }; 2243 2244 const MachRegisterNumbers farg_reg[13] = { 2245 F1_num, F2_num, F3_num, F4_num, 2246 F5_num, F6_num, F7_num, F8_num, 2247 F9_num, F10_num, F11_num, F12_num, 2248 F13_num 2249 }; 2250 2251 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2252 2253 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2254 2255 // Return whether or not this register is ever used as an argument. This 2256 // function is used on startup to build the trampoline stubs in generateOptoStub. 2257 // Registers not mentioned will be killed by the VM call in the trampoline, and 2258 // arguments in those registers not be available to the callee. 2259 bool Matcher::can_be_java_arg(int reg) { 2260 // We return true for all registers contained in iarg_reg[] and 2261 // farg_reg[] and their virtual halves. 2262 // We must include the virtual halves in order to get STDs and LDs 2263 // instead of STWs and LWs in the trampoline stubs. 2264 2265 if ( reg == R3_num || reg == R3_H_num 2266 || reg == R4_num || reg == R4_H_num 2267 || reg == R5_num || reg == R5_H_num 2268 || reg == R6_num || reg == R6_H_num 2269 || reg == R7_num || reg == R7_H_num 2270 || reg == R8_num || reg == R8_H_num 2271 || reg == R9_num || reg == R9_H_num 2272 || reg == R10_num || reg == R10_H_num) 2273 return true; 2274 2275 if ( reg == F1_num || reg == F1_H_num 2276 || reg == F2_num || reg == F2_H_num 2277 || reg == F3_num || reg == F3_H_num 2278 || reg == F4_num || reg == F4_H_num 2279 || reg == F5_num || reg == F5_H_num 2280 || reg == F6_num || reg == F6_H_num 2281 || reg == F7_num || reg == F7_H_num 2282 || reg == F8_num || reg == F8_H_num 2283 || reg == F9_num || reg == F9_H_num 2284 || reg == F10_num || reg == F10_H_num 2285 || reg == F11_num || reg == F11_H_num 2286 || reg == F12_num || reg == F12_H_num 2287 || reg == F13_num || reg == F13_H_num) 2288 return true; 2289 2290 return false; 2291 } 2292 2293 bool Matcher::is_spillable_arg(int reg) { 2294 return can_be_java_arg(reg); 2295 } 2296 2297 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2298 return false; 2299 } 2300 2301 // Register for DIVI projection of divmodI. 2302 RegMask Matcher::divI_proj_mask() { 2303 ShouldNotReachHere(); 2304 return RegMask(); 2305 } 2306 2307 // Register for MODI projection of divmodI. 2308 RegMask Matcher::modI_proj_mask() { 2309 ShouldNotReachHere(); 2310 return RegMask(); 2311 } 2312 2313 // Register for DIVL projection of divmodL. 2314 RegMask Matcher::divL_proj_mask() { 2315 ShouldNotReachHere(); 2316 return RegMask(); 2317 } 2318 2319 // Register for MODL projection of divmodL. 2320 RegMask Matcher::modL_proj_mask() { 2321 ShouldNotReachHere(); 2322 return RegMask(); 2323 } 2324 2325 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2326 return RegMask(); 2327 } 2328 2329 %} 2330 2331 //----------ENCODING BLOCK----------------------------------------------------- 2332 // This block specifies the encoding classes used by the compiler to output 2333 // byte streams. Encoding classes are parameterized macros used by 2334 // Machine Instruction Nodes in order to generate the bit encoding of the 2335 // instruction. Operands specify their base encoding interface with the 2336 // interface keyword. There are currently supported four interfaces, 2337 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2338 // operand to generate a function which returns its register number when 2339 // queried. CONST_INTER causes an operand to generate a function which 2340 // returns the value of the constant when queried. MEMORY_INTER causes an 2341 // operand to generate four functions which return the Base Register, the 2342 // Index Register, the Scale Value, and the Offset Value of the operand when 2343 // queried. COND_INTER causes an operand to generate six functions which 2344 // return the encoding code (ie - encoding bits for the instruction) 2345 // associated with each basic boolean condition for a conditional instruction. 2346 // 2347 // Instructions specify two basic values for encoding. Again, a function 2348 // is available to check if the constant displacement is an oop. They use the 2349 // ins_encode keyword to specify their encoding classes (which must be 2350 // a sequence of enc_class names, and their parameters, specified in 2351 // the encoding block), and they use the 2352 // opcode keyword to specify, in order, their primary, secondary, and 2353 // tertiary opcode. Only the opcode sections which a particular instruction 2354 // needs for encoding need to be specified. 2355 encode %{ 2356 enc_class enc_unimplemented %{ 2357 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2358 MacroAssembler _masm(&cbuf); 2359 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2360 %} 2361 2362 enc_class enc_untested %{ 2363 #ifdef ASSERT 2364 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2365 MacroAssembler _masm(&cbuf); 2366 __ untested("Untested mach node encoding in AD file."); 2367 #else 2368 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2369 #endif 2370 %} 2371 2372 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2373 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2374 MacroAssembler _masm(&cbuf); 2375 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2376 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2377 %} 2378 2379 // Load acquire. 2380 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2381 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2382 MacroAssembler _masm(&cbuf); 2383 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2384 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2385 __ twi_0($dst$$Register); 2386 __ isync(); 2387 %} 2388 2389 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2390 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2391 2392 MacroAssembler _masm(&cbuf); 2393 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2394 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2395 %} 2396 2397 // Load acquire. 2398 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2399 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2400 2401 MacroAssembler _masm(&cbuf); 2402 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2403 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2404 __ twi_0($dst$$Register); 2405 __ isync(); 2406 %} 2407 2408 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2409 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2410 2411 MacroAssembler _masm(&cbuf); 2412 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2413 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2414 %} 2415 2416 // Load acquire. 2417 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2418 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2419 2420 MacroAssembler _masm(&cbuf); 2421 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2422 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2423 __ twi_0($dst$$Register); 2424 __ isync(); 2425 %} 2426 2427 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2428 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2429 MacroAssembler _masm(&cbuf); 2430 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2431 // Operand 'ds' requires 4-alignment. 2432 assert((Idisp & 0x3) == 0, "unaligned offset"); 2433 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2434 %} 2435 2436 // Load acquire. 2437 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2438 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2439 MacroAssembler _masm(&cbuf); 2440 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2441 // Operand 'ds' requires 4-alignment. 2442 assert((Idisp & 0x3) == 0, "unaligned offset"); 2443 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2444 __ twi_0($dst$$Register); 2445 __ isync(); 2446 %} 2447 2448 enc_class enc_lfd(RegF dst, memory mem) %{ 2449 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2450 MacroAssembler _masm(&cbuf); 2451 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2452 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2453 %} 2454 2455 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2456 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2457 2458 MacroAssembler _masm(&cbuf); 2459 int toc_offset = 0; 2460 2461 if (!ra_->C->in_scratch_emit_size()) { 2462 address const_toc_addr; 2463 // Create a non-oop constant, no relocation needed. 2464 // If it is an IC, it has a virtual_call_Relocation. 2465 const_toc_addr = __ long_constant((jlong)$src$$constant); 2466 2467 // Get the constant's TOC offset. 2468 toc_offset = __ offset_to_method_toc(const_toc_addr); 2469 2470 // Keep the current instruction offset in mind. 2471 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2472 } 2473 2474 __ ld($dst$$Register, toc_offset, $toc$$Register); 2475 %} 2476 2477 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2478 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2479 2480 MacroAssembler _masm(&cbuf); 2481 2482 if (!ra_->C->in_scratch_emit_size()) { 2483 address const_toc_addr; 2484 // Create a non-oop constant, no relocation needed. 2485 // If it is an IC, it has a virtual_call_Relocation. 2486 const_toc_addr = __ long_constant((jlong)$src$$constant); 2487 2488 // Get the constant's TOC offset. 2489 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2490 // Store the toc offset of the constant. 2491 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2492 2493 // Also keep the current instruction offset in mind. 2494 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2495 } 2496 2497 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2498 %} 2499 2500 %} // encode 2501 2502 source %{ 2503 2504 typedef struct { 2505 loadConL_hiNode *_large_hi; 2506 loadConL_loNode *_large_lo; 2507 loadConLNode *_small; 2508 MachNode *_last; 2509 } loadConLNodesTuple; 2510 2511 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2512 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2513 loadConLNodesTuple nodes; 2514 2515 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2516 if (large_constant_pool) { 2517 // Create new nodes. 2518 loadConL_hiNode *m1 = new loadConL_hiNode(); 2519 loadConL_loNode *m2 = new loadConL_loNode(); 2520 2521 // inputs for new nodes 2522 m1->add_req(NULL, toc); 2523 m2->add_req(NULL, m1); 2524 2525 // operands for new nodes 2526 m1->_opnds[0] = new iRegLdstOper(); // dst 2527 m1->_opnds[1] = immSrc; // src 2528 m1->_opnds[2] = new iRegPdstOper(); // toc 2529 m2->_opnds[0] = new iRegLdstOper(); // dst 2530 m2->_opnds[1] = immSrc; // src 2531 m2->_opnds[2] = new iRegLdstOper(); // base 2532 2533 // Initialize ins_attrib TOC fields. 2534 m1->_const_toc_offset = -1; 2535 m2->_const_toc_offset_hi_node = m1; 2536 2537 // Initialize ins_attrib instruction offset. 2538 m1->_cbuf_insts_offset = -1; 2539 2540 // register allocation for new nodes 2541 ra_->set_pair(m1->_idx, reg_second, reg_first); 2542 ra_->set_pair(m2->_idx, reg_second, reg_first); 2543 2544 // Create result. 2545 nodes._large_hi = m1; 2546 nodes._large_lo = m2; 2547 nodes._small = NULL; 2548 nodes._last = nodes._large_lo; 2549 assert(m2->bottom_type()->isa_long(), "must be long"); 2550 } else { 2551 loadConLNode *m2 = new loadConLNode(); 2552 2553 // inputs for new nodes 2554 m2->add_req(NULL, toc); 2555 2556 // operands for new nodes 2557 m2->_opnds[0] = new iRegLdstOper(); // dst 2558 m2->_opnds[1] = immSrc; // src 2559 m2->_opnds[2] = new iRegPdstOper(); // toc 2560 2561 // Initialize ins_attrib instruction offset. 2562 m2->_cbuf_insts_offset = -1; 2563 2564 // register allocation for new nodes 2565 ra_->set_pair(m2->_idx, reg_second, reg_first); 2566 2567 // Create result. 2568 nodes._large_hi = NULL; 2569 nodes._large_lo = NULL; 2570 nodes._small = m2; 2571 nodes._last = nodes._small; 2572 assert(m2->bottom_type()->isa_long(), "must be long"); 2573 } 2574 2575 return nodes; 2576 } 2577 2578 %} // source 2579 2580 encode %{ 2581 // Postalloc expand emitter for loading a long constant from the method's TOC. 2582 // Enc_class needed as consttanttablebase is not supported by postalloc 2583 // expand. 2584 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2585 // Create new nodes. 2586 loadConLNodesTuple loadConLNodes = 2587 loadConLNodesTuple_create(ra_, n_toc, op_src, 2588 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2589 2590 // Push new nodes. 2591 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2592 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2593 2594 // some asserts 2595 assert(nodes->length() >= 1, "must have created at least 1 node"); 2596 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2597 %} 2598 2599 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2600 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2601 2602 MacroAssembler _masm(&cbuf); 2603 int toc_offset = 0; 2604 2605 if (!ra_->C->in_scratch_emit_size()) { 2606 intptr_t val = $src$$constant; 2607 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2608 address const_toc_addr; 2609 if (constant_reloc == relocInfo::oop_type) { 2610 // Create an oop constant and a corresponding relocation. 2611 AddressLiteral a = __ allocate_oop_address((jobject)val); 2612 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2613 __ relocate(a.rspec()); 2614 } else if (constant_reloc == relocInfo::metadata_type) { 2615 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2616 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2617 __ relocate(a.rspec()); 2618 } else { 2619 // Create a non-oop constant, no relocation needed. 2620 const_toc_addr = __ long_constant((jlong)$src$$constant); 2621 } 2622 2623 // Get the constant's TOC offset. 2624 toc_offset = __ offset_to_method_toc(const_toc_addr); 2625 } 2626 2627 __ ld($dst$$Register, toc_offset, $toc$$Register); 2628 %} 2629 2630 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2631 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2632 2633 MacroAssembler _masm(&cbuf); 2634 if (!ra_->C->in_scratch_emit_size()) { 2635 intptr_t val = $src$$constant; 2636 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2637 address const_toc_addr; 2638 if (constant_reloc == relocInfo::oop_type) { 2639 // Create an oop constant and a corresponding relocation. 2640 AddressLiteral a = __ allocate_oop_address((jobject)val); 2641 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2642 __ relocate(a.rspec()); 2643 } else if (constant_reloc == relocInfo::metadata_type) { 2644 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2645 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2646 __ relocate(a.rspec()); 2647 } else { // non-oop pointers, e.g. card mark base, heap top 2648 // Create a non-oop constant, no relocation needed. 2649 const_toc_addr = __ long_constant((jlong)$src$$constant); 2650 } 2651 2652 // Get the constant's TOC offset. 2653 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2654 // Store the toc offset of the constant. 2655 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2656 } 2657 2658 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2659 %} 2660 2661 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2662 // Enc_class needed as consttanttablebase is not supported by postalloc 2663 // expand. 2664 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2665 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2666 if (large_constant_pool) { 2667 // Create new nodes. 2668 loadConP_hiNode *m1 = new loadConP_hiNode(); 2669 loadConP_loNode *m2 = new loadConP_loNode(); 2670 2671 // inputs for new nodes 2672 m1->add_req(NULL, n_toc); 2673 m2->add_req(NULL, m1); 2674 2675 // operands for new nodes 2676 m1->_opnds[0] = new iRegPdstOper(); // dst 2677 m1->_opnds[1] = op_src; // src 2678 m1->_opnds[2] = new iRegPdstOper(); // toc 2679 m2->_opnds[0] = new iRegPdstOper(); // dst 2680 m2->_opnds[1] = op_src; // src 2681 m2->_opnds[2] = new iRegLdstOper(); // base 2682 2683 // Initialize ins_attrib TOC fields. 2684 m1->_const_toc_offset = -1; 2685 m2->_const_toc_offset_hi_node = m1; 2686 2687 // Register allocation for new nodes. 2688 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2689 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2690 2691 nodes->push(m1); 2692 nodes->push(m2); 2693 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2694 } else { 2695 loadConPNode *m2 = new loadConPNode(); 2696 2697 // inputs for new nodes 2698 m2->add_req(NULL, n_toc); 2699 2700 // operands for new nodes 2701 m2->_opnds[0] = new iRegPdstOper(); // dst 2702 m2->_opnds[1] = op_src; // src 2703 m2->_opnds[2] = new iRegPdstOper(); // toc 2704 2705 // Register allocation for new nodes. 2706 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2707 2708 nodes->push(m2); 2709 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2710 } 2711 %} 2712 2713 // Enc_class needed as consttanttablebase is not supported by postalloc 2714 // expand. 2715 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2716 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2717 2718 MachNode *m2; 2719 if (large_constant_pool) { 2720 m2 = new loadConFCompNode(); 2721 } else { 2722 m2 = new loadConFNode(); 2723 } 2724 // inputs for new nodes 2725 m2->add_req(NULL, n_toc); 2726 2727 // operands for new nodes 2728 m2->_opnds[0] = op_dst; 2729 m2->_opnds[1] = op_src; 2730 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2731 2732 // register allocation for new nodes 2733 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2734 nodes->push(m2); 2735 %} 2736 2737 // Enc_class needed as consttanttablebase is not supported by postalloc 2738 // expand. 2739 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2740 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2741 2742 MachNode *m2; 2743 if (large_constant_pool) { 2744 m2 = new loadConDCompNode(); 2745 } else { 2746 m2 = new loadConDNode(); 2747 } 2748 // inputs for new nodes 2749 m2->add_req(NULL, n_toc); 2750 2751 // operands for new nodes 2752 m2->_opnds[0] = op_dst; 2753 m2->_opnds[1] = op_src; 2754 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2755 2756 // register allocation for new nodes 2757 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2758 nodes->push(m2); 2759 %} 2760 2761 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2762 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2763 MacroAssembler _masm(&cbuf); 2764 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2765 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2766 %} 2767 2768 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2769 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2770 MacroAssembler _masm(&cbuf); 2771 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2772 // Operand 'ds' requires 4-alignment. 2773 assert((Idisp & 0x3) == 0, "unaligned offset"); 2774 __ std($src$$Register, Idisp, $mem$$base$$Register); 2775 %} 2776 2777 enc_class enc_stfs(RegF src, memory mem) %{ 2778 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2779 MacroAssembler _masm(&cbuf); 2780 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2781 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2782 %} 2783 2784 enc_class enc_stfd(RegF src, memory mem) %{ 2785 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2786 MacroAssembler _masm(&cbuf); 2787 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2788 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2789 %} 2790 2791 // Use release_store for card-marking to ensure that previous 2792 // oop-stores are visible before the card-mark change. 2793 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 2794 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2795 // FIXME: Implement this as a cmove and use a fixed condition code 2796 // register which is written on every transition to compiled code, 2797 // e.g. in call-stub and when returning from runtime stubs. 2798 // 2799 // Proposed code sequence for the cmove implementation: 2800 // 2801 // Label skip_release; 2802 // __ beq(CCRfixed, skip_release); 2803 // __ release(); 2804 // __ bind(skip_release); 2805 // __ stb(card mark); 2806 2807 MacroAssembler _masm(&cbuf); 2808 Label skip_storestore; 2809 2810 #if 0 // TODO: PPC port 2811 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2812 // StoreStore barrier conditionally. 2813 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2814 __ cmpwi($crx$$CondRegister, R0, 0); 2815 __ beq_predict_taken($crx$$CondRegister, skip_storestore); 2816 #endif 2817 __ li(R0, 0); 2818 __ membar(Assembler::StoreStore); 2819 #if 0 // TODO: PPC port 2820 __ bind(skip_storestore); 2821 #endif 2822 2823 // Do the store. 2824 if ($mem$$index == 0) { 2825 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2826 } else { 2827 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2828 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2829 } 2830 %} 2831 2832 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2833 2834 if (VM_Version::has_isel()) { 2835 // use isel instruction with Power 7 2836 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2837 encodeP_subNode *n_sub_base = new encodeP_subNode(); 2838 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2839 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode(); 2840 2841 n_compare->add_req(n_region, n_src); 2842 n_compare->_opnds[0] = op_crx; 2843 n_compare->_opnds[1] = op_src; 2844 n_compare->_opnds[2] = new immL16Oper(0); 2845 2846 n_sub_base->add_req(n_region, n_src); 2847 n_sub_base->_opnds[0] = op_dst; 2848 n_sub_base->_opnds[1] = op_src; 2849 n_sub_base->_bottom_type = _bottom_type; 2850 2851 n_shift->add_req(n_region, n_sub_base); 2852 n_shift->_opnds[0] = op_dst; 2853 n_shift->_opnds[1] = op_dst; 2854 n_shift->_bottom_type = _bottom_type; 2855 2856 n_cond_set->add_req(n_region, n_compare, n_shift); 2857 n_cond_set->_opnds[0] = op_dst; 2858 n_cond_set->_opnds[1] = op_crx; 2859 n_cond_set->_opnds[2] = op_dst; 2860 n_cond_set->_bottom_type = _bottom_type; 2861 2862 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2863 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2864 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2865 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2866 2867 nodes->push(n_compare); 2868 nodes->push(n_sub_base); 2869 nodes->push(n_shift); 2870 nodes->push(n_cond_set); 2871 2872 } else { 2873 // before Power 7 2874 moveRegNode *n_move = new moveRegNode(); 2875 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2876 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2877 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode(); 2878 2879 n_move->add_req(n_region, n_src); 2880 n_move->_opnds[0] = op_dst; 2881 n_move->_opnds[1] = op_src; 2882 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2883 2884 n_compare->add_req(n_region, n_src); 2885 n_compare->add_prec(n_move); 2886 2887 n_compare->_opnds[0] = op_crx; 2888 n_compare->_opnds[1] = op_src; 2889 n_compare->_opnds[2] = new immL16Oper(0); 2890 2891 n_sub_base->add_req(n_region, n_compare, n_src); 2892 n_sub_base->_opnds[0] = op_dst; 2893 n_sub_base->_opnds[1] = op_crx; 2894 n_sub_base->_opnds[2] = op_src; 2895 n_sub_base->_bottom_type = _bottom_type; 2896 2897 n_shift->add_req(n_region, n_sub_base); 2898 n_shift->_opnds[0] = op_dst; 2899 n_shift->_opnds[1] = op_dst; 2900 n_shift->_bottom_type = _bottom_type; 2901 2902 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2903 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2904 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2905 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2906 2907 nodes->push(n_move); 2908 nodes->push(n_compare); 2909 nodes->push(n_sub_base); 2910 nodes->push(n_shift); 2911 } 2912 2913 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2914 %} 2915 2916 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 2917 2918 encodeP_subNode *n1 = new encodeP_subNode(); 2919 n1->add_req(n_region, n_src); 2920 n1->_opnds[0] = op_dst; 2921 n1->_opnds[1] = op_src; 2922 n1->_bottom_type = _bottom_type; 2923 2924 encodeP_shiftNode *n2 = new encodeP_shiftNode(); 2925 n2->add_req(n_region, n1); 2926 n2->_opnds[0] = op_dst; 2927 n2->_opnds[1] = op_dst; 2928 n2->_bottom_type = _bottom_type; 2929 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2930 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2931 2932 nodes->push(n1); 2933 nodes->push(n2); 2934 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2935 %} 2936 2937 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 2938 decodeN_shiftNode *n_shift = new decodeN_shiftNode(); 2939 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 2940 2941 n_compare->add_req(n_region, n_src); 2942 n_compare->_opnds[0] = op_crx; 2943 n_compare->_opnds[1] = op_src; 2944 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 2945 2946 n_shift->add_req(n_region, n_src); 2947 n_shift->_opnds[0] = op_dst; 2948 n_shift->_opnds[1] = op_src; 2949 n_shift->_bottom_type = _bottom_type; 2950 2951 if (VM_Version::has_isel()) { 2952 // use isel instruction with Power 7 2953 2954 decodeN_addNode *n_add_base = new decodeN_addNode(); 2955 n_add_base->add_req(n_region, n_shift); 2956 n_add_base->_opnds[0] = op_dst; 2957 n_add_base->_opnds[1] = op_dst; 2958 n_add_base->_bottom_type = _bottom_type; 2959 2960 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 2961 n_cond_set->add_req(n_region, n_compare, n_add_base); 2962 n_cond_set->_opnds[0] = op_dst; 2963 n_cond_set->_opnds[1] = op_crx; 2964 n_cond_set->_opnds[2] = op_dst; 2965 n_cond_set->_bottom_type = _bottom_type; 2966 2967 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2968 ra_->set_oop(n_cond_set, true); 2969 2970 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2971 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2972 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2973 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2974 2975 nodes->push(n_compare); 2976 nodes->push(n_shift); 2977 nodes->push(n_add_base); 2978 nodes->push(n_cond_set); 2979 2980 } else { 2981 // before Power 7 2982 cond_add_baseNode *n_add_base = new cond_add_baseNode(); 2983 2984 n_add_base->add_req(n_region, n_compare, n_shift); 2985 n_add_base->_opnds[0] = op_dst; 2986 n_add_base->_opnds[1] = op_crx; 2987 n_add_base->_opnds[2] = op_dst; 2988 n_add_base->_bottom_type = _bottom_type; 2989 2990 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2991 ra_->set_oop(n_add_base, true); 2992 2993 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2994 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2995 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2996 2997 nodes->push(n_compare); 2998 nodes->push(n_shift); 2999 nodes->push(n_add_base); 3000 } 3001 %} 3002 3003 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 3004 decodeN_shiftNode *n1 = new decodeN_shiftNode(); 3005 n1->add_req(n_region, n_src); 3006 n1->_opnds[0] = op_dst; 3007 n1->_opnds[1] = op_src; 3008 n1->_bottom_type = _bottom_type; 3009 3010 decodeN_addNode *n2 = new decodeN_addNode(); 3011 n2->add_req(n_region, n1); 3012 n2->_opnds[0] = op_dst; 3013 n2->_opnds[1] = op_dst; 3014 n2->_bottom_type = _bottom_type; 3015 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3016 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3017 3018 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3019 ra_->set_oop(n2, true); 3020 3021 nodes->push(n1); 3022 nodes->push(n2); 3023 %} 3024 3025 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{ 3026 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3027 3028 MacroAssembler _masm(&cbuf); 3029 int cc = $cmp$$cmpcode; 3030 int flags_reg = $crx$$reg; 3031 Label done; 3032 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3033 // Branch if not (cmp crx). 3034 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3035 __ mr($dst$$Register, $src$$Register); 3036 // TODO PPC port __ endgroup_if_needed(_size == 12); 3037 __ bind(done); 3038 %} 3039 3040 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{ 3041 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3042 3043 MacroAssembler _masm(&cbuf); 3044 Label done; 3045 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3046 // Branch if not (cmp crx). 3047 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3048 __ li($dst$$Register, $src$$constant); 3049 // TODO PPC port __ endgroup_if_needed(_size == 12); 3050 __ bind(done); 3051 %} 3052 3053 // New atomics. 3054 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3055 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3056 3057 MacroAssembler _masm(&cbuf); 3058 Register Rtmp = R0; 3059 Register Rres = $res$$Register; 3060 Register Rsrc = $src$$Register; 3061 Register Rptr = $mem_ptr$$Register; 3062 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3063 Register Rold = RegCollision ? Rtmp : Rres; 3064 3065 Label Lretry; 3066 __ bind(Lretry); 3067 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3068 __ add(Rtmp, Rsrc, Rold); 3069 __ stwcx_(Rtmp, Rptr); 3070 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3071 __ bne_predict_not_taken(CCR0, Lretry); 3072 } else { 3073 __ bne( CCR0, Lretry); 3074 } 3075 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3076 __ fence(); 3077 %} 3078 3079 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3080 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3081 3082 MacroAssembler _masm(&cbuf); 3083 Register Rtmp = R0; 3084 Register Rres = $res$$Register; 3085 Register Rsrc = $src$$Register; 3086 Register Rptr = $mem_ptr$$Register; 3087 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3088 Register Rold = RegCollision ? Rtmp : Rres; 3089 3090 Label Lretry; 3091 __ bind(Lretry); 3092 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3093 __ add(Rtmp, Rsrc, Rold); 3094 __ stdcx_(Rtmp, Rptr); 3095 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3096 __ bne_predict_not_taken(CCR0, Lretry); 3097 } else { 3098 __ bne( CCR0, Lretry); 3099 } 3100 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3101 __ fence(); 3102 %} 3103 3104 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3105 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3106 3107 MacroAssembler _masm(&cbuf); 3108 Register Rtmp = R0; 3109 Register Rres = $res$$Register; 3110 Register Rsrc = $src$$Register; 3111 Register Rptr = $mem_ptr$$Register; 3112 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3113 Register Rold = RegCollision ? Rtmp : Rres; 3114 3115 Label Lretry; 3116 __ bind(Lretry); 3117 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3118 __ stwcx_(Rsrc, Rptr); 3119 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3120 __ bne_predict_not_taken(CCR0, Lretry); 3121 } else { 3122 __ bne( CCR0, Lretry); 3123 } 3124 if (RegCollision) __ mr(Rres, Rtmp); 3125 __ fence(); 3126 %} 3127 3128 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3129 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3130 3131 MacroAssembler _masm(&cbuf); 3132 Register Rtmp = R0; 3133 Register Rres = $res$$Register; 3134 Register Rsrc = $src$$Register; 3135 Register Rptr = $mem_ptr$$Register; 3136 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3137 Register Rold = RegCollision ? Rtmp : Rres; 3138 3139 Label Lretry; 3140 __ bind(Lretry); 3141 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3142 __ stdcx_(Rsrc, Rptr); 3143 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3144 __ bne_predict_not_taken(CCR0, Lretry); 3145 } else { 3146 __ bne( CCR0, Lretry); 3147 } 3148 if (RegCollision) __ mr(Rres, Rtmp); 3149 __ fence(); 3150 %} 3151 3152 // This enc_class is needed so that scheduler gets proper 3153 // input mapping for latency computation. 3154 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3155 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3156 MacroAssembler _masm(&cbuf); 3157 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3158 %} 3159 3160 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3161 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3162 3163 MacroAssembler _masm(&cbuf); 3164 3165 Label done; 3166 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3167 __ li($dst$$Register, $zero$$constant); 3168 __ beq($crx$$CondRegister, done); 3169 __ li($dst$$Register, $notzero$$constant); 3170 __ bind(done); 3171 %} 3172 3173 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3174 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3175 3176 MacroAssembler _masm(&cbuf); 3177 3178 Label done; 3179 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3180 __ li($dst$$Register, $zero$$constant); 3181 __ beq($crx$$CondRegister, done); 3182 __ li($dst$$Register, $notzero$$constant); 3183 __ bind(done); 3184 %} 3185 3186 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{ 3187 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3188 3189 MacroAssembler _masm(&cbuf); 3190 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3191 Label done; 3192 __ bso($crx$$CondRegister, done); 3193 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3194 // TODO PPC port __ endgroup_if_needed(_size == 12); 3195 __ bind(done); 3196 %} 3197 3198 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3199 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3200 3201 MacroAssembler _masm(&cbuf); 3202 Label d; // dummy 3203 __ bind(d); 3204 Label* p = ($lbl$$label); 3205 // `p' is `NULL' when this encoding class is used only to 3206 // determine the size of the encoded instruction. 3207 Label& l = (NULL == p)? d : *(p); 3208 int cc = $cmp$$cmpcode; 3209 int flags_reg = $crx$$reg; 3210 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3211 int bhint = Assembler::bhintNoHint; 3212 3213 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3214 if (_prob <= PROB_NEVER) { 3215 bhint = Assembler::bhintIsNotTaken; 3216 } else if (_prob >= PROB_ALWAYS) { 3217 bhint = Assembler::bhintIsTaken; 3218 } 3219 } 3220 3221 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3222 cc_to_biint(cc, flags_reg), 3223 l); 3224 %} 3225 3226 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3227 // The scheduler doesn't know about branch shortening, so we set the opcode 3228 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3229 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3230 3231 MacroAssembler _masm(&cbuf); 3232 Label d; // dummy 3233 __ bind(d); 3234 Label* p = ($lbl$$label); 3235 // `p' is `NULL' when this encoding class is used only to 3236 // determine the size of the encoded instruction. 3237 Label& l = (NULL == p)? d : *(p); 3238 int cc = $cmp$$cmpcode; 3239 int flags_reg = $crx$$reg; 3240 int bhint = Assembler::bhintNoHint; 3241 3242 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3243 if (_prob <= PROB_NEVER) { 3244 bhint = Assembler::bhintIsNotTaken; 3245 } else if (_prob >= PROB_ALWAYS) { 3246 bhint = Assembler::bhintIsTaken; 3247 } 3248 } 3249 3250 // Tell the conditional far branch to optimize itself when being relocated. 3251 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3252 cc_to_biint(cc, flags_reg), 3253 l, 3254 MacroAssembler::bc_far_optimize_on_relocate); 3255 %} 3256 3257 // Branch used with Power6 scheduling (can be shortened without changing the node). 3258 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3259 // The scheduler doesn't know about branch shortening, so we set the opcode 3260 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3261 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3262 3263 MacroAssembler _masm(&cbuf); 3264 Label d; // dummy 3265 __ bind(d); 3266 Label* p = ($lbl$$label); 3267 // `p' is `NULL' when this encoding class is used only to 3268 // determine the size of the encoded instruction. 3269 Label& l = (NULL == p)? d : *(p); 3270 int cc = $cmp$$cmpcode; 3271 int flags_reg = $crx$$reg; 3272 int bhint = Assembler::bhintNoHint; 3273 3274 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3275 if (_prob <= PROB_NEVER) { 3276 bhint = Assembler::bhintIsNotTaken; 3277 } else if (_prob >= PROB_ALWAYS) { 3278 bhint = Assembler::bhintIsTaken; 3279 } 3280 } 3281 3282 #if 0 // TODO: PPC port 3283 if (_size == 8) { 3284 // Tell the conditional far branch to optimize itself when being relocated. 3285 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3286 cc_to_biint(cc, flags_reg), 3287 l, 3288 MacroAssembler::bc_far_optimize_on_relocate); 3289 } else { 3290 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3291 cc_to_biint(cc, flags_reg), 3292 l); 3293 } 3294 #endif 3295 Unimplemented(); 3296 %} 3297 3298 // Postalloc expand emitter for loading a replicatef float constant from 3299 // the method's TOC. 3300 // Enc_class needed as consttanttablebase is not supported by postalloc 3301 // expand. 3302 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3303 // Create new nodes. 3304 3305 // Make an operand with the bit pattern to load as float. 3306 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF())); 3307 3308 loadConLNodesTuple loadConLNodes = 3309 loadConLNodesTuple_create(ra_, n_toc, op_repl, 3310 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3311 3312 // Push new nodes. 3313 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3314 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3315 3316 assert(nodes->length() >= 1, "must have created at least 1 node"); 3317 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3318 %} 3319 3320 // This enc_class is needed so that scheduler gets proper 3321 // input mapping for latency computation. 3322 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3323 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3324 // Fake operand dst needed for PPC scheduler. 3325 assert($dst$$constant == 0x0, "dst must be 0x0"); 3326 3327 MacroAssembler _masm(&cbuf); 3328 // Mark the code position where the load from the safepoint 3329 // polling page was emitted as relocInfo::poll_type. 3330 __ relocate(relocInfo::poll_type); 3331 __ load_from_polling_page($poll$$Register); 3332 %} 3333 3334 // A Java static call or a runtime call. 3335 // 3336 // Branch-and-link relative to a trampoline. 3337 // The trampoline loads the target address and does a long branch to there. 3338 // In case we call java, the trampoline branches to a interpreter_stub 3339 // which loads the inline cache and the real call target from the constant pool. 3340 // 3341 // This basically looks like this: 3342 // 3343 // >>>> consts -+ -+ 3344 // | |- offset1 3345 // [call target1] | <-+ 3346 // [IC cache] |- offset2 3347 // [call target2] <--+ 3348 // 3349 // <<<< consts 3350 // >>>> insts 3351 // 3352 // bl offset16 -+ -+ ??? // How many bits available? 3353 // | | 3354 // <<<< insts | | 3355 // >>>> stubs | | 3356 // | |- trampoline_stub_Reloc 3357 // trampoline stub: | <-+ 3358 // r2 = toc | 3359 // r2 = [r2 + offset1] | // Load call target1 from const section 3360 // mtctr r2 | 3361 // bctr |- static_stub_Reloc 3362 // comp_to_interp_stub: <---+ 3363 // r1 = toc 3364 // ICreg = [r1 + IC_offset] // Load IC from const section 3365 // r1 = [r1 + offset2] // Load call target2 from const section 3366 // mtctr r1 3367 // bctr 3368 // 3369 // <<<< stubs 3370 // 3371 // The call instruction in the code either 3372 // - Branches directly to a compiled method if the offset is encodable in instruction. 3373 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3374 // - Branches to the compiled_to_interp stub if the target is interpreted. 3375 // 3376 // Further there are three relocations from the loads to the constants in 3377 // the constant section. 3378 // 3379 // Usage of r1 and r2 in the stubs allows to distinguish them. 3380 enc_class enc_java_static_call(method meth) %{ 3381 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3382 3383 MacroAssembler _masm(&cbuf); 3384 address entry_point = (address)$meth$$method; 3385 3386 if (!_method) { 3387 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3388 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3389 } else { 3390 // Remember the offset not the address. 3391 const int start_offset = __ offset(); 3392 // The trampoline stub. 3393 if (!Compile::current()->in_scratch_emit_size()) { 3394 // No entry point given, use the current pc. 3395 // Make sure branch fits into 3396 if (entry_point == 0) entry_point = __ pc(); 3397 3398 // Put the entry point as a constant into the constant pool. 3399 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3400 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3401 3402 // Emit the trampoline stub which will be related to the branch-and-link below. 3403 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3404 if (ciEnv::current()->failing()) { return; } // Code cache may be full. 3405 __ relocate(_optimized_virtual ? 3406 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); 3407 } 3408 3409 // The real call. 3410 // Note: At this point we do not have the address of the trampoline 3411 // stub, and the entry point might be too far away for bl, so __ pc() 3412 // serves as dummy and the bl will be patched later. 3413 cbuf.set_insts_mark(); 3414 __ bl(__ pc()); // Emits a relocation. 3415 3416 // The stub for call to interpreter. 3417 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 3418 if (stub == NULL) { 3419 ciEnv::current()->record_failure("CodeCache is full"); 3420 return; 3421 } 3422 } 3423 %} 3424 3425 // Emit a method handle call. 3426 // 3427 // Method handle calls from compiled to compiled are going thru a 3428 // c2i -> i2c adapter, extending the frame for their arguments. The 3429 // caller however, returns directly to the compiled callee, that has 3430 // to cope with the extended frame. We restore the original frame by 3431 // loading the callers sp and adding the calculated framesize. 3432 enc_class enc_java_handle_call(method meth) %{ 3433 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3434 3435 MacroAssembler _masm(&cbuf); 3436 address entry_point = (address)$meth$$method; 3437 3438 // Remember the offset not the address. 3439 const int start_offset = __ offset(); 3440 // The trampoline stub. 3441 if (!ra_->C->in_scratch_emit_size()) { 3442 // No entry point given, use the current pc. 3443 // Make sure branch fits into 3444 if (entry_point == 0) entry_point = __ pc(); 3445 3446 // Put the entry point as a constant into the constant pool. 3447 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3448 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3449 3450 // Emit the trampoline stub which will be related to the branch-and-link below. 3451 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3452 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3453 assert(_optimized_virtual, "methodHandle call should be a virtual call"); 3454 __ relocate(relocInfo::opt_virtual_call_type); 3455 } 3456 3457 // The real call. 3458 // Note: At this point we do not have the address of the trampoline 3459 // stub, and the entry point might be too far away for bl, so __ pc() 3460 // serves as dummy and the bl will be patched later. 3461 cbuf.set_insts_mark(); 3462 __ bl(__ pc()); // Emits a relocation. 3463 3464 assert(_method, "execute next statement conditionally"); 3465 // The stub for call to interpreter. 3466 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 3467 if (stub == NULL) { 3468 ciEnv::current()->record_failure("CodeCache is full"); 3469 return; 3470 } 3471 3472 // Restore original sp. 3473 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp. 3474 const long framesize = ra_->C->frame_slots() << LogBytesPerInt; 3475 unsigned int bytes = (unsigned int)framesize; 3476 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 3477 if (Assembler::is_simm(-offset, 16)) { 3478 __ addi(R1_SP, R11_scratch1, -offset); 3479 } else { 3480 __ load_const_optimized(R12_scratch2, -offset); 3481 __ add(R1_SP, R11_scratch1, R12_scratch2); 3482 } 3483 #ifdef ASSERT 3484 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. 3485 __ cmpd(CCR0, R11_scratch1, R12_scratch2); 3486 __ asm_assert_eq("backlink changed", 0x8000); 3487 #endif 3488 // If fails should store backlink before unextending. 3489 3490 if (ra_->C->env()->failing()) { 3491 return; 3492 } 3493 %} 3494 3495 // Second node of expanded dynamic call - the call. 3496 enc_class enc_java_dynamic_call_sched(method meth) %{ 3497 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3498 3499 MacroAssembler _masm(&cbuf); 3500 3501 if (!ra_->C->in_scratch_emit_size()) { 3502 // Create a call trampoline stub for the given method. 3503 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3504 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3505 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3506 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3507 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3508 3509 // Build relocation at call site with ic position as data. 3510 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3511 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3512 "must have one, but can't have both"); 3513 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3514 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3515 "must contain instruction offset"); 3516 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3517 ? _load_ic_hi_node->_cbuf_insts_offset 3518 : _load_ic_node->_cbuf_insts_offset; 3519 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3520 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3521 "should be load from TOC"); 3522 3523 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 3524 } 3525 3526 // At this point I do not have the address of the trampoline stub, 3527 // and the entry point might be too far away for bl. Pc() serves 3528 // as dummy and bl will be patched later. 3529 __ bl((address) __ pc()); 3530 %} 3531 3532 // postalloc expand emitter for virtual calls. 3533 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3534 3535 // Create the nodes for loading the IC from the TOC. 3536 loadConLNodesTuple loadConLNodes_IC = 3537 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()), 3538 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3539 3540 // Create the call node. 3541 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode(); 3542 call->_method_handle_invoke = _method_handle_invoke; 3543 call->_vtable_index = _vtable_index; 3544 call->_method = _method; 3545 call->_bci = _bci; 3546 call->_optimized_virtual = _optimized_virtual; 3547 call->_tf = _tf; 3548 call->_entry_point = _entry_point; 3549 call->_cnt = _cnt; 3550 call->_argsize = _argsize; 3551 call->_oop_map = _oop_map; 3552 call->_jvms = _jvms; 3553 call->_jvmadj = _jvmadj; 3554 call->_in_rms = _in_rms; 3555 call->_nesting = _nesting; 3556 3557 // New call needs all inputs of old call. 3558 // Req... 3559 for (uint i = 0; i < req(); ++i) { 3560 // The expanded node does not need toc any more. 3561 // Add the inline cache constant here instead. This expresses the 3562 // register of the inline cache must be live at the call. 3563 // Else we would have to adapt JVMState by -1. 3564 if (i == mach_constant_base_node_input()) { 3565 call->add_req(loadConLNodes_IC._last); 3566 } else { 3567 call->add_req(in(i)); 3568 } 3569 } 3570 // ...as well as prec 3571 for (uint i = req(); i < len(); ++i) { 3572 call->add_prec(in(i)); 3573 } 3574 3575 // Remember nodes loading the inline cache into r19. 3576 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3577 call->_load_ic_node = loadConLNodes_IC._small; 3578 3579 // Operands for new nodes. 3580 call->_opnds[0] = _opnds[0]; 3581 call->_opnds[1] = _opnds[1]; 3582 3583 // Only the inline cache is associated with a register. 3584 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3585 3586 // Push new nodes. 3587 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3588 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3589 nodes->push(call); 3590 %} 3591 3592 // Compound version of call dynamic 3593 // Toc is only passed so that it can be used in ins_encode statement. 3594 // In the code we have to use $constanttablebase. 3595 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3596 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3597 MacroAssembler _masm(&cbuf); 3598 int start_offset = __ offset(); 3599 3600 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3601 #if 0 3602 int vtable_index = this->_vtable_index; 3603 if (_vtable_index < 0) { 3604 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3605 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3606 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3607 3608 // Virtual call relocation will point to ic load. 3609 address virtual_call_meta_addr = __ pc(); 3610 // Load a clear inline cache. 3611 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3612 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc); 3613 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3614 // to determine who we intended to call. 3615 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3616 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3617 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3618 "Fix constant in ret_addr_offset()"); 3619 } else { 3620 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3621 // Go thru the vtable. Get receiver klass. Receiver already 3622 // checked for non-null. If we'll go thru a C2I adapter, the 3623 // interpreter expects method in R19_method. 3624 3625 __ load_klass(R11_scratch1, R3); 3626 3627 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); 3628 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); 3629 __ li(R19_method, v_off); 3630 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3631 // NOTE: for vtable dispatches, the vtable entry will never be 3632 // null. However it may very well end up in handle_wrong_method 3633 // if the method is abstract for the particular class. 3634 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3635 // Call target. Either compiled code or C2I adapter. 3636 __ mtctr(R11_scratch1); 3637 __ bctrl(); 3638 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3639 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3640 } 3641 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3642 "Fix constant in ret_addr_offset()"); 3643 } 3644 #endif 3645 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3646 %} 3647 3648 // a runtime call 3649 enc_class enc_java_to_runtime_call (method meth) %{ 3650 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3651 3652 MacroAssembler _masm(&cbuf); 3653 const address start_pc = __ pc(); 3654 3655 #if defined(ABI_ELFv2) 3656 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3657 __ call_c(entry, relocInfo::runtime_call_type); 3658 #else 3659 // The function we're going to call. 3660 FunctionDescriptor fdtemp; 3661 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3662 3663 Register Rtoc = R12_scratch2; 3664 // Calculate the method's TOC. 3665 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3666 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3667 // pool entries; call_c_using_toc will optimize the call. 3668 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3669 #endif 3670 3671 // Check the ret_addr_offset. 3672 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3673 "Fix constant in ret_addr_offset()"); 3674 %} 3675 3676 // Move to ctr for leaf call. 3677 // This enc_class is needed so that scheduler gets proper 3678 // input mapping for latency computation. 3679 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3680 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3681 MacroAssembler _masm(&cbuf); 3682 __ mtctr($src$$Register); 3683 %} 3684 3685 // Postalloc expand emitter for runtime leaf calls. 3686 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3687 loadConLNodesTuple loadConLNodes_Entry; 3688 #if defined(ABI_ELFv2) 3689 jlong entry_address = (jlong) this->entry_point(); 3690 assert(entry_address, "need address here"); 3691 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3692 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3693 #else 3694 // Get the struct that describes the function we are about to call. 3695 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3696 assert(fd, "need fd here"); 3697 jlong entry_address = (jlong) fd->entry(); 3698 // new nodes 3699 loadConLNodesTuple loadConLNodes_Env; 3700 loadConLNodesTuple loadConLNodes_Toc; 3701 3702 // Create nodes and operands for loading the entry point. 3703 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3704 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3705 3706 3707 // Create nodes and operands for loading the env pointer. 3708 if (fd->env() != NULL) { 3709 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()), 3710 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3711 } else { 3712 loadConLNodes_Env._large_hi = NULL; 3713 loadConLNodes_Env._large_lo = NULL; 3714 loadConLNodes_Env._small = NULL; 3715 loadConLNodes_Env._last = new loadConL16Node(); 3716 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper(); 3717 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0); 3718 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3719 } 3720 3721 // Create nodes and operands for loading the Toc point. 3722 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()), 3723 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3724 #endif // ABI_ELFv2 3725 // mtctr node 3726 MachNode *mtctr = new CallLeafDirect_mtctrNode(); 3727 3728 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3729 mtctr->add_req(0, loadConLNodes_Entry._last); 3730 3731 mtctr->_opnds[0] = new iRegLdstOper(); 3732 mtctr->_opnds[1] = new iRegLdstOper(); 3733 3734 // call node 3735 MachCallLeafNode *call = new CallLeafDirectNode(); 3736 3737 call->_opnds[0] = _opnds[0]; 3738 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later. 3739 3740 // Make the new call node look like the old one. 3741 call->_name = _name; 3742 call->_tf = _tf; 3743 call->_entry_point = _entry_point; 3744 call->_cnt = _cnt; 3745 call->_argsize = _argsize; 3746 call->_oop_map = _oop_map; 3747 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3748 call->_jvms = NULL; 3749 call->_jvmadj = _jvmadj; 3750 call->_in_rms = _in_rms; 3751 call->_nesting = _nesting; 3752 3753 3754 // New call needs all inputs of old call. 3755 // Req... 3756 for (uint i = 0; i < req(); ++i) { 3757 if (i != mach_constant_base_node_input()) { 3758 call->add_req(in(i)); 3759 } 3760 } 3761 3762 // These must be reqired edges, as the registers are live up to 3763 // the call. Else the constants are handled as kills. 3764 call->add_req(mtctr); 3765 #if !defined(ABI_ELFv2) 3766 call->add_req(loadConLNodes_Env._last); 3767 call->add_req(loadConLNodes_Toc._last); 3768 #endif 3769 3770 // ...as well as prec 3771 for (uint i = req(); i < len(); ++i) { 3772 call->add_prec(in(i)); 3773 } 3774 3775 // registers 3776 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3777 3778 // Insert the new nodes. 3779 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3780 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3781 #if !defined(ABI_ELFv2) 3782 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3783 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3784 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3785 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3786 #endif 3787 nodes->push(mtctr); 3788 nodes->push(call); 3789 %} 3790 %} 3791 3792 //----------FRAME-------------------------------------------------------------- 3793 // Definition of frame structure and management information. 3794 3795 frame %{ 3796 // What direction does stack grow in (assumed to be same for native & Java). 3797 stack_direction(TOWARDS_LOW); 3798 3799 // These two registers define part of the calling convention between 3800 // compiled code and the interpreter. 3801 3802 // Inline Cache Register or method for I2C. 3803 inline_cache_reg(R19); // R19_method 3804 3805 // Method Oop Register when calling interpreter. 3806 interpreter_method_oop_reg(R19); // R19_method 3807 3808 // Optional: name the operand used by cisc-spilling to access 3809 // [stack_pointer + offset]. 3810 cisc_spilling_operand_name(indOffset); 3811 3812 // Number of stack slots consumed by a Monitor enter. 3813 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3814 3815 // Compiled code's Frame Pointer. 3816 frame_pointer(R1); // R1_SP 3817 3818 // Interpreter stores its frame pointer in a register which is 3819 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3820 // interpreted java to compiled java. 3821 // 3822 // R14_state holds pointer to caller's cInterpreter. 3823 interpreter_frame_pointer(R14); // R14_state 3824 3825 stack_alignment(frame::alignment_in_bytes); 3826 3827 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3828 3829 // Number of outgoing stack slots killed above the 3830 // out_preserve_stack_slots for calls to C. Supports the var-args 3831 // backing area for register parms. 3832 // 3833 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3834 3835 // The after-PROLOG location of the return address. Location of 3836 // return address specifies a type (REG or STACK) and a number 3837 // representing the register number (i.e. - use a register name) or 3838 // stack slot. 3839 // 3840 // A: Link register is stored in stack slot ... 3841 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3842 // J: Therefore, we make sure that the link register is also in R11_scratch1 3843 // at the end of the prolog. 3844 // B: We use R20, now. 3845 //return_addr(REG R20); 3846 3847 // G: After reading the comments made by all the luminaries on their 3848 // failure to tell the compiler where the return address really is, 3849 // I hardly dare to try myself. However, I'm convinced it's in slot 3850 // 4 what apparently works and saves us some spills. 3851 return_addr(STACK 4); 3852 3853 // This is the body of the function 3854 // 3855 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3856 // uint length, // length of array 3857 // bool is_outgoing) 3858 // 3859 // The `sig' array is to be updated. sig[j] represents the location 3860 // of the j-th argument, either a register or a stack slot. 3861 3862 // Comment taken from i486.ad: 3863 // Body of function which returns an integer array locating 3864 // arguments either in registers or in stack slots. Passed an array 3865 // of ideal registers called "sig" and a "length" count. Stack-slot 3866 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3867 // arguments for a CALLEE. Incoming stack arguments are 3868 // automatically biased by the preserve_stack_slots field above. 3869 calling_convention %{ 3870 // No difference between ingoing/outgoing. Just pass false. 3871 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3872 %} 3873 3874 // Comment taken from i486.ad: 3875 // Body of function which returns an integer array locating 3876 // arguments either in registers or in stack slots. Passed an array 3877 // of ideal registers called "sig" and a "length" count. Stack-slot 3878 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3879 // arguments for a CALLEE. Incoming stack arguments are 3880 // automatically biased by the preserve_stack_slots field above. 3881 c_calling_convention %{ 3882 // This is obviously always outgoing. 3883 // C argument in register AND stack slot. 3884 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3885 %} 3886 3887 // Location of native (C/C++) and interpreter return values. This 3888 // is specified to be the same as Java. In the 32-bit VM, long 3889 // values are actually returned from native calls in O0:O1 and 3890 // returned to the interpreter in I0:I1. The copying to and from 3891 // the register pairs is done by the appropriate call and epilog 3892 // opcodes. This simplifies the register allocator. 3893 c_return_value %{ 3894 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3895 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3896 "only return normal values"); 3897 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3898 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3899 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3900 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3901 %} 3902 3903 // Location of compiled Java return values. Same as C 3904 return_value %{ 3905 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3906 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3907 "only return normal values"); 3908 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3909 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3910 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3911 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3912 %} 3913 %} 3914 3915 3916 //----------ATTRIBUTES--------------------------------------------------------- 3917 3918 //----------Operand Attributes------------------------------------------------- 3919 op_attrib op_cost(1); // Required cost attribute. 3920 3921 //----------Instruction Attributes--------------------------------------------- 3922 3923 // Cost attribute. required. 3924 ins_attrib ins_cost(DEFAULT_COST); 3925 3926 // Is this instruction a non-matching short branch variant of some 3927 // long branch? Not required. 3928 ins_attrib ins_short_branch(0); 3929 3930 ins_attrib ins_is_TrapBasedCheckNode(true); 3931 3932 // Number of constants. 3933 // This instruction uses the given number of constants 3934 // (optional attribute). 3935 // This is needed to determine in time whether the constant pool will 3936 // exceed 4000 entries. Before postalloc_expand the overall number of constants 3937 // is determined. It's also used to compute the constant pool size 3938 // in Output(). 3939 ins_attrib ins_num_consts(0); 3940 3941 // Required alignment attribute (must be a power of 2) specifies the 3942 // alignment that some part of the instruction (not necessarily the 3943 // start) requires. If > 1, a compute_padding() function must be 3944 // provided for the instruction. 3945 ins_attrib ins_alignment(1); 3946 3947 // Enforce/prohibit rematerializations. 3948 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 3949 // then rematerialization of that instruction is prohibited and the 3950 // instruction's value will be spilled if necessary. 3951 // Causes that MachNode::rematerialize() returns false. 3952 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 3953 // then rematerialization should be enforced and a copy of the instruction 3954 // should be inserted if possible; rematerialization is not guaranteed. 3955 // Note: this may result in rematerializations in front of every use. 3956 // Causes that MachNode::rematerialize() can return true. 3957 // (optional attribute) 3958 ins_attrib ins_cannot_rematerialize(false); 3959 ins_attrib ins_should_rematerialize(false); 3960 3961 // Instruction has variable size depending on alignment. 3962 ins_attrib ins_variable_size_depending_on_alignment(false); 3963 3964 // Instruction is a nop. 3965 ins_attrib ins_is_nop(false); 3966 3967 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 3968 ins_attrib ins_use_mach_if_fast_lock_node(false); 3969 3970 // Field for the toc offset of a constant. 3971 // 3972 // This is needed if the toc offset is not encodable as an immediate in 3973 // the PPC load instruction. If so, the upper (hi) bits of the offset are 3974 // added to the toc, and from this a load with immediate is performed. 3975 // With postalloc expand, we get two nodes that require the same offset 3976 // but which don't know about each other. The offset is only known 3977 // when the constant is added to the constant pool during emitting. 3978 // It is generated in the 'hi'-node adding the upper bits, and saved 3979 // in this node. The 'lo'-node has a link to the 'hi'-node and reads 3980 // the offset from there when it gets encoded. 3981 ins_attrib ins_field_const_toc_offset(0); 3982 ins_attrib ins_field_const_toc_offset_hi_node(0); 3983 3984 // A field that can hold the instructions offset in the code buffer. 3985 // Set in the nodes emitter. 3986 ins_attrib ins_field_cbuf_insts_offset(-1); 3987 3988 // Fields for referencing a call's load-IC-node. 3989 // If the toc offset can not be encoded as an immediate in a load, we 3990 // use two nodes. 3991 ins_attrib ins_field_load_ic_hi_node(0); 3992 ins_attrib ins_field_load_ic_node(0); 3993 3994 //----------OPERANDS----------------------------------------------------------- 3995 // Operand definitions must precede instruction definitions for correct 3996 // parsing in the ADLC because operands constitute user defined types 3997 // which are used in instruction definitions. 3998 // 3999 // Formats are generated automatically for constants and base registers. 4000 4001 //----------Simple Operands---------------------------------------------------- 4002 // Immediate Operands 4003 4004 // Integer Immediate: 32-bit 4005 operand immI() %{ 4006 match(ConI); 4007 op_cost(40); 4008 format %{ %} 4009 interface(CONST_INTER); 4010 %} 4011 4012 operand immI8() %{ 4013 predicate(Assembler::is_simm(n->get_int(), 8)); 4014 op_cost(0); 4015 match(ConI); 4016 format %{ %} 4017 interface(CONST_INTER); 4018 %} 4019 4020 // Integer Immediate: 16-bit 4021 operand immI16() %{ 4022 predicate(Assembler::is_simm(n->get_int(), 16)); 4023 op_cost(0); 4024 match(ConI); 4025 format %{ %} 4026 interface(CONST_INTER); 4027 %} 4028 4029 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 4030 operand immIhi16() %{ 4031 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 4032 match(ConI); 4033 op_cost(0); 4034 format %{ %} 4035 interface(CONST_INTER); 4036 %} 4037 4038 operand immInegpow2() %{ 4039 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 4040 match(ConI); 4041 op_cost(0); 4042 format %{ %} 4043 interface(CONST_INTER); 4044 %} 4045 4046 operand immIpow2minus1() %{ 4047 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 4048 match(ConI); 4049 op_cost(0); 4050 format %{ %} 4051 interface(CONST_INTER); 4052 %} 4053 4054 operand immIpowerOf2() %{ 4055 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 4056 match(ConI); 4057 op_cost(0); 4058 format %{ %} 4059 interface(CONST_INTER); 4060 %} 4061 4062 // Unsigned Integer Immediate: the values 0-31 4063 operand uimmI5() %{ 4064 predicate(Assembler::is_uimm(n->get_int(), 5)); 4065 match(ConI); 4066 op_cost(0); 4067 format %{ %} 4068 interface(CONST_INTER); 4069 %} 4070 4071 // Unsigned Integer Immediate: 6-bit 4072 operand uimmI6() %{ 4073 predicate(Assembler::is_uimm(n->get_int(), 6)); 4074 match(ConI); 4075 op_cost(0); 4076 format %{ %} 4077 interface(CONST_INTER); 4078 %} 4079 4080 // Unsigned Integer Immediate: 6-bit int, greater than 32 4081 operand uimmI6_ge32() %{ 4082 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4083 match(ConI); 4084 op_cost(0); 4085 format %{ %} 4086 interface(CONST_INTER); 4087 %} 4088 4089 // Unsigned Integer Immediate: 15-bit 4090 operand uimmI15() %{ 4091 predicate(Assembler::is_uimm(n->get_int(), 15)); 4092 match(ConI); 4093 op_cost(0); 4094 format %{ %} 4095 interface(CONST_INTER); 4096 %} 4097 4098 // Unsigned Integer Immediate: 16-bit 4099 operand uimmI16() %{ 4100 predicate(Assembler::is_uimm(n->get_int(), 16)); 4101 match(ConI); 4102 op_cost(0); 4103 format %{ %} 4104 interface(CONST_INTER); 4105 %} 4106 4107 // constant 'int 0'. 4108 operand immI_0() %{ 4109 predicate(n->get_int() == 0); 4110 match(ConI); 4111 op_cost(0); 4112 format %{ %} 4113 interface(CONST_INTER); 4114 %} 4115 4116 // constant 'int 1'. 4117 operand immI_1() %{ 4118 predicate(n->get_int() == 1); 4119 match(ConI); 4120 op_cost(0); 4121 format %{ %} 4122 interface(CONST_INTER); 4123 %} 4124 4125 // constant 'int -1'. 4126 operand immI_minus1() %{ 4127 predicate(n->get_int() == -1); 4128 match(ConI); 4129 op_cost(0); 4130 format %{ %} 4131 interface(CONST_INTER); 4132 %} 4133 4134 // int value 16. 4135 operand immI_16() %{ 4136 predicate(n->get_int() == 16); 4137 match(ConI); 4138 op_cost(0); 4139 format %{ %} 4140 interface(CONST_INTER); 4141 %} 4142 4143 // int value 24. 4144 operand immI_24() %{ 4145 predicate(n->get_int() == 24); 4146 match(ConI); 4147 op_cost(0); 4148 format %{ %} 4149 interface(CONST_INTER); 4150 %} 4151 4152 // Compressed oops constants 4153 // Pointer Immediate 4154 operand immN() %{ 4155 match(ConN); 4156 4157 op_cost(10); 4158 format %{ %} 4159 interface(CONST_INTER); 4160 %} 4161 4162 // NULL Pointer Immediate 4163 operand immN_0() %{ 4164 predicate(n->get_narrowcon() == 0); 4165 match(ConN); 4166 4167 op_cost(0); 4168 format %{ %} 4169 interface(CONST_INTER); 4170 %} 4171 4172 // Compressed klass constants 4173 operand immNKlass() %{ 4174 match(ConNKlass); 4175 4176 op_cost(0); 4177 format %{ %} 4178 interface(CONST_INTER); 4179 %} 4180 4181 // This operand can be used to avoid matching of an instruct 4182 // with chain rule. 4183 operand immNKlass_NM() %{ 4184 match(ConNKlass); 4185 predicate(false); 4186 op_cost(0); 4187 format %{ %} 4188 interface(CONST_INTER); 4189 %} 4190 4191 // Pointer Immediate: 64-bit 4192 operand immP() %{ 4193 match(ConP); 4194 op_cost(0); 4195 format %{ %} 4196 interface(CONST_INTER); 4197 %} 4198 4199 // Operand to avoid match of loadConP. 4200 // This operand can be used to avoid matching of an instruct 4201 // with chain rule. 4202 operand immP_NM() %{ 4203 match(ConP); 4204 predicate(false); 4205 op_cost(0); 4206 format %{ %} 4207 interface(CONST_INTER); 4208 %} 4209 4210 // costant 'pointer 0'. 4211 operand immP_0() %{ 4212 predicate(n->get_ptr() == 0); 4213 match(ConP); 4214 op_cost(0); 4215 format %{ %} 4216 interface(CONST_INTER); 4217 %} 4218 4219 // pointer 0x0 or 0x1 4220 operand immP_0or1() %{ 4221 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4222 match(ConP); 4223 op_cost(0); 4224 format %{ %} 4225 interface(CONST_INTER); 4226 %} 4227 4228 operand immL() %{ 4229 match(ConL); 4230 op_cost(40); 4231 format %{ %} 4232 interface(CONST_INTER); 4233 %} 4234 4235 // Long Immediate: 16-bit 4236 operand immL16() %{ 4237 predicate(Assembler::is_simm(n->get_long(), 16)); 4238 match(ConL); 4239 op_cost(0); 4240 format %{ %} 4241 interface(CONST_INTER); 4242 %} 4243 4244 // Long Immediate: 16-bit, 4-aligned 4245 operand immL16Alg4() %{ 4246 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4247 match(ConL); 4248 op_cost(0); 4249 format %{ %} 4250 interface(CONST_INTER); 4251 %} 4252 4253 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4254 operand immL32hi16() %{ 4255 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4256 match(ConL); 4257 op_cost(0); 4258 format %{ %} 4259 interface(CONST_INTER); 4260 %} 4261 4262 // Long Immediate: 32-bit 4263 operand immL32() %{ 4264 predicate(Assembler::is_simm(n->get_long(), 32)); 4265 match(ConL); 4266 op_cost(0); 4267 format %{ %} 4268 interface(CONST_INTER); 4269 %} 4270 4271 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4272 operand immLhighest16() %{ 4273 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4274 match(ConL); 4275 op_cost(0); 4276 format %{ %} 4277 interface(CONST_INTER); 4278 %} 4279 4280 operand immLnegpow2() %{ 4281 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4282 match(ConL); 4283 op_cost(0); 4284 format %{ %} 4285 interface(CONST_INTER); 4286 %} 4287 4288 operand immLpow2minus1() %{ 4289 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4290 (n->get_long() != (jlong)0xffffffffffffffffL)); 4291 match(ConL); 4292 op_cost(0); 4293 format %{ %} 4294 interface(CONST_INTER); 4295 %} 4296 4297 // constant 'long 0'. 4298 operand immL_0() %{ 4299 predicate(n->get_long() == 0L); 4300 match(ConL); 4301 op_cost(0); 4302 format %{ %} 4303 interface(CONST_INTER); 4304 %} 4305 4306 // constat ' long -1'. 4307 operand immL_minus1() %{ 4308 predicate(n->get_long() == -1L); 4309 match(ConL); 4310 op_cost(0); 4311 format %{ %} 4312 interface(CONST_INTER); 4313 %} 4314 4315 // Long Immediate: low 32-bit mask 4316 operand immL_32bits() %{ 4317 predicate(n->get_long() == 0xFFFFFFFFL); 4318 match(ConL); 4319 op_cost(0); 4320 format %{ %} 4321 interface(CONST_INTER); 4322 %} 4323 4324 // Unsigned Long Immediate: 16-bit 4325 operand uimmL16() %{ 4326 predicate(Assembler::is_uimm(n->get_long(), 16)); 4327 match(ConL); 4328 op_cost(0); 4329 format %{ %} 4330 interface(CONST_INTER); 4331 %} 4332 4333 // Float Immediate 4334 operand immF() %{ 4335 match(ConF); 4336 op_cost(40); 4337 format %{ %} 4338 interface(CONST_INTER); 4339 %} 4340 4341 // Float Immediate: +0.0f. 4342 operand immF_0() %{ 4343 predicate(jint_cast(n->getf()) == 0); 4344 match(ConF); 4345 4346 op_cost(0); 4347 format %{ %} 4348 interface(CONST_INTER); 4349 %} 4350 4351 // Double Immediate 4352 operand immD() %{ 4353 match(ConD); 4354 op_cost(40); 4355 format %{ %} 4356 interface(CONST_INTER); 4357 %} 4358 4359 // Integer Register Operands 4360 // Integer Destination Register 4361 // See definition of reg_class bits32_reg_rw. 4362 operand iRegIdst() %{ 4363 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4364 match(RegI); 4365 match(rscratch1RegI); 4366 match(rscratch2RegI); 4367 match(rarg1RegI); 4368 match(rarg2RegI); 4369 match(rarg3RegI); 4370 match(rarg4RegI); 4371 format %{ %} 4372 interface(REG_INTER); 4373 %} 4374 4375 // Integer Source Register 4376 // See definition of reg_class bits32_reg_ro. 4377 operand iRegIsrc() %{ 4378 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4379 match(RegI); 4380 match(rscratch1RegI); 4381 match(rscratch2RegI); 4382 match(rarg1RegI); 4383 match(rarg2RegI); 4384 match(rarg3RegI); 4385 match(rarg4RegI); 4386 format %{ %} 4387 interface(REG_INTER); 4388 %} 4389 4390 operand rscratch1RegI() %{ 4391 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4392 match(iRegIdst); 4393 format %{ %} 4394 interface(REG_INTER); 4395 %} 4396 4397 operand rscratch2RegI() %{ 4398 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4399 match(iRegIdst); 4400 format %{ %} 4401 interface(REG_INTER); 4402 %} 4403 4404 operand rarg1RegI() %{ 4405 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4406 match(iRegIdst); 4407 format %{ %} 4408 interface(REG_INTER); 4409 %} 4410 4411 operand rarg2RegI() %{ 4412 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4413 match(iRegIdst); 4414 format %{ %} 4415 interface(REG_INTER); 4416 %} 4417 4418 operand rarg3RegI() %{ 4419 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4420 match(iRegIdst); 4421 format %{ %} 4422 interface(REG_INTER); 4423 %} 4424 4425 operand rarg4RegI() %{ 4426 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4427 match(iRegIdst); 4428 format %{ %} 4429 interface(REG_INTER); 4430 %} 4431 4432 operand rarg1RegL() %{ 4433 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4434 match(iRegLdst); 4435 format %{ %} 4436 interface(REG_INTER); 4437 %} 4438 4439 operand rarg2RegL() %{ 4440 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4441 match(iRegLdst); 4442 format %{ %} 4443 interface(REG_INTER); 4444 %} 4445 4446 operand rarg3RegL() %{ 4447 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4448 match(iRegLdst); 4449 format %{ %} 4450 interface(REG_INTER); 4451 %} 4452 4453 operand rarg4RegL() %{ 4454 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4455 match(iRegLdst); 4456 format %{ %} 4457 interface(REG_INTER); 4458 %} 4459 4460 // Pointer Destination Register 4461 // See definition of reg_class bits64_reg_rw. 4462 operand iRegPdst() %{ 4463 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4464 match(RegP); 4465 match(rscratch1RegP); 4466 match(rscratch2RegP); 4467 match(rarg1RegP); 4468 match(rarg2RegP); 4469 match(rarg3RegP); 4470 match(rarg4RegP); 4471 format %{ %} 4472 interface(REG_INTER); 4473 %} 4474 4475 // Pointer Destination Register 4476 // Operand not using r11 and r12 (killed in epilog). 4477 operand iRegPdstNoScratch() %{ 4478 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4479 match(RegP); 4480 match(rarg1RegP); 4481 match(rarg2RegP); 4482 match(rarg3RegP); 4483 match(rarg4RegP); 4484 format %{ %} 4485 interface(REG_INTER); 4486 %} 4487 4488 // Pointer Source Register 4489 // See definition of reg_class bits64_reg_ro. 4490 operand iRegPsrc() %{ 4491 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4492 match(RegP); 4493 match(iRegPdst); 4494 match(rscratch1RegP); 4495 match(rscratch2RegP); 4496 match(rarg1RegP); 4497 match(rarg2RegP); 4498 match(rarg3RegP); 4499 match(rarg4RegP); 4500 match(threadRegP); 4501 format %{ %} 4502 interface(REG_INTER); 4503 %} 4504 4505 // Thread operand. 4506 operand threadRegP() %{ 4507 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4508 match(iRegPdst); 4509 format %{ "R16" %} 4510 interface(REG_INTER); 4511 %} 4512 4513 operand rscratch1RegP() %{ 4514 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4515 match(iRegPdst); 4516 format %{ "R11" %} 4517 interface(REG_INTER); 4518 %} 4519 4520 operand rscratch2RegP() %{ 4521 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4522 match(iRegPdst); 4523 format %{ %} 4524 interface(REG_INTER); 4525 %} 4526 4527 operand rarg1RegP() %{ 4528 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4529 match(iRegPdst); 4530 format %{ %} 4531 interface(REG_INTER); 4532 %} 4533 4534 operand rarg2RegP() %{ 4535 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4536 match(iRegPdst); 4537 format %{ %} 4538 interface(REG_INTER); 4539 %} 4540 4541 operand rarg3RegP() %{ 4542 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4543 match(iRegPdst); 4544 format %{ %} 4545 interface(REG_INTER); 4546 %} 4547 4548 operand rarg4RegP() %{ 4549 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4550 match(iRegPdst); 4551 format %{ %} 4552 interface(REG_INTER); 4553 %} 4554 4555 operand iRegNsrc() %{ 4556 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4557 match(RegN); 4558 match(iRegNdst); 4559 4560 format %{ %} 4561 interface(REG_INTER); 4562 %} 4563 4564 operand iRegNdst() %{ 4565 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4566 match(RegN); 4567 4568 format %{ %} 4569 interface(REG_INTER); 4570 %} 4571 4572 // Long Destination Register 4573 // See definition of reg_class bits64_reg_rw. 4574 operand iRegLdst() %{ 4575 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4576 match(RegL); 4577 match(rscratch1RegL); 4578 match(rscratch2RegL); 4579 format %{ %} 4580 interface(REG_INTER); 4581 %} 4582 4583 // Long Source Register 4584 // See definition of reg_class bits64_reg_ro. 4585 operand iRegLsrc() %{ 4586 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4587 match(RegL); 4588 match(iRegLdst); 4589 match(rscratch1RegL); 4590 match(rscratch2RegL); 4591 format %{ %} 4592 interface(REG_INTER); 4593 %} 4594 4595 // Special operand for ConvL2I. 4596 operand iRegL2Isrc(iRegLsrc reg) %{ 4597 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4598 match(ConvL2I reg); 4599 format %{ "ConvL2I($reg)" %} 4600 interface(REG_INTER) 4601 %} 4602 4603 operand rscratch1RegL() %{ 4604 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4605 match(RegL); 4606 format %{ %} 4607 interface(REG_INTER); 4608 %} 4609 4610 operand rscratch2RegL() %{ 4611 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4612 match(RegL); 4613 format %{ %} 4614 interface(REG_INTER); 4615 %} 4616 4617 // Condition Code Flag Registers 4618 operand flagsReg() %{ 4619 constraint(ALLOC_IN_RC(int_flags)); 4620 match(RegFlags); 4621 format %{ %} 4622 interface(REG_INTER); 4623 %} 4624 4625 operand flagsRegSrc() %{ 4626 constraint(ALLOC_IN_RC(int_flags_ro)); 4627 match(RegFlags); 4628 match(flagsReg); 4629 match(flagsRegCR0); 4630 format %{ %} 4631 interface(REG_INTER); 4632 %} 4633 4634 // Condition Code Flag Register CR0 4635 operand flagsRegCR0() %{ 4636 constraint(ALLOC_IN_RC(int_flags_CR0)); 4637 match(RegFlags); 4638 format %{ "CR0" %} 4639 interface(REG_INTER); 4640 %} 4641 4642 operand flagsRegCR1() %{ 4643 constraint(ALLOC_IN_RC(int_flags_CR1)); 4644 match(RegFlags); 4645 format %{ "CR1" %} 4646 interface(REG_INTER); 4647 %} 4648 4649 operand flagsRegCR6() %{ 4650 constraint(ALLOC_IN_RC(int_flags_CR6)); 4651 match(RegFlags); 4652 format %{ "CR6" %} 4653 interface(REG_INTER); 4654 %} 4655 4656 operand regCTR() %{ 4657 constraint(ALLOC_IN_RC(ctr_reg)); 4658 // RegFlags should work. Introducing a RegSpecial type would cause a 4659 // lot of changes. 4660 match(RegFlags); 4661 format %{"SR_CTR" %} 4662 interface(REG_INTER); 4663 %} 4664 4665 operand regD() %{ 4666 constraint(ALLOC_IN_RC(dbl_reg)); 4667 match(RegD); 4668 format %{ %} 4669 interface(REG_INTER); 4670 %} 4671 4672 operand regF() %{ 4673 constraint(ALLOC_IN_RC(flt_reg)); 4674 match(RegF); 4675 format %{ %} 4676 interface(REG_INTER); 4677 %} 4678 4679 // Special Registers 4680 4681 // Method Register 4682 operand inline_cache_regP(iRegPdst reg) %{ 4683 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4684 match(reg); 4685 format %{ %} 4686 interface(REG_INTER); 4687 %} 4688 4689 operand compiler_method_oop_regP(iRegPdst reg) %{ 4690 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4691 match(reg); 4692 format %{ %} 4693 interface(REG_INTER); 4694 %} 4695 4696 operand interpreter_method_oop_regP(iRegPdst reg) %{ 4697 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4698 match(reg); 4699 format %{ %} 4700 interface(REG_INTER); 4701 %} 4702 4703 // Operands to remove register moves in unscaled mode. 4704 // Match read/write registers with an EncodeP node if neither shift nor add are required. 4705 operand iRegP2N(iRegPsrc reg) %{ 4706 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4707 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4708 match(EncodeP reg); 4709 format %{ "$reg" %} 4710 interface(REG_INTER) 4711 %} 4712 4713 operand iRegN2P(iRegNsrc reg) %{ 4714 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4715 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4716 match(DecodeN reg); 4717 format %{ "$reg" %} 4718 interface(REG_INTER) 4719 %} 4720 4721 operand iRegN2P_klass(iRegNsrc reg) %{ 4722 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4723 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4724 match(DecodeNKlass reg); 4725 format %{ "$reg" %} 4726 interface(REG_INTER) 4727 %} 4728 4729 //----------Complex Operands--------------------------------------------------- 4730 // Indirect Memory Reference 4731 operand indirect(iRegPsrc reg) %{ 4732 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4733 match(reg); 4734 op_cost(100); 4735 format %{ "[$reg]" %} 4736 interface(MEMORY_INTER) %{ 4737 base($reg); 4738 index(0x0); 4739 scale(0x0); 4740 disp(0x0); 4741 %} 4742 %} 4743 4744 // Indirect with Offset 4745 operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4746 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4747 match(AddP reg offset); 4748 op_cost(100); 4749 format %{ "[$reg + $offset]" %} 4750 interface(MEMORY_INTER) %{ 4751 base($reg); 4752 index(0x0); 4753 scale(0x0); 4754 disp($offset); 4755 %} 4756 %} 4757 4758 // Indirect with 4-aligned Offset 4759 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4760 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4761 match(AddP reg offset); 4762 op_cost(100); 4763 format %{ "[$reg + $offset]" %} 4764 interface(MEMORY_INTER) %{ 4765 base($reg); 4766 index(0x0); 4767 scale(0x0); 4768 disp($offset); 4769 %} 4770 %} 4771 4772 //----------Complex Operands for Compressed OOPs------------------------------- 4773 // Compressed OOPs with narrow_oop_shift == 0. 4774 4775 // Indirect Memory Reference, compressed OOP 4776 operand indirectNarrow(iRegNsrc reg) %{ 4777 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4778 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4779 match(DecodeN reg); 4780 op_cost(100); 4781 format %{ "[$reg]" %} 4782 interface(MEMORY_INTER) %{ 4783 base($reg); 4784 index(0x0); 4785 scale(0x0); 4786 disp(0x0); 4787 %} 4788 %} 4789 4790 operand indirectNarrow_klass(iRegNsrc reg) %{ 4791 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4792 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4793 match(DecodeNKlass reg); 4794 op_cost(100); 4795 format %{ "[$reg]" %} 4796 interface(MEMORY_INTER) %{ 4797 base($reg); 4798 index(0x0); 4799 scale(0x0); 4800 disp(0x0); 4801 %} 4802 %} 4803 4804 // Indirect with Offset, compressed OOP 4805 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4806 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4807 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4808 match(AddP (DecodeN reg) offset); 4809 op_cost(100); 4810 format %{ "[$reg + $offset]" %} 4811 interface(MEMORY_INTER) %{ 4812 base($reg); 4813 index(0x0); 4814 scale(0x0); 4815 disp($offset); 4816 %} 4817 %} 4818 4819 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{ 4820 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4821 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4822 match(AddP (DecodeNKlass reg) offset); 4823 op_cost(100); 4824 format %{ "[$reg + $offset]" %} 4825 interface(MEMORY_INTER) %{ 4826 base($reg); 4827 index(0x0); 4828 scale(0x0); 4829 disp($offset); 4830 %} 4831 %} 4832 4833 // Indirect with 4-aligned Offset, compressed OOP 4834 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4835 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4836 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4837 match(AddP (DecodeN reg) offset); 4838 op_cost(100); 4839 format %{ "[$reg + $offset]" %} 4840 interface(MEMORY_INTER) %{ 4841 base($reg); 4842 index(0x0); 4843 scale(0x0); 4844 disp($offset); 4845 %} 4846 %} 4847 4848 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{ 4849 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4850 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4851 match(AddP (DecodeNKlass reg) offset); 4852 op_cost(100); 4853 format %{ "[$reg + $offset]" %} 4854 interface(MEMORY_INTER) %{ 4855 base($reg); 4856 index(0x0); 4857 scale(0x0); 4858 disp($offset); 4859 %} 4860 %} 4861 4862 //----------Special Memory Operands-------------------------------------------- 4863 // Stack Slot Operand 4864 // 4865 // This operand is used for loading and storing temporary values on 4866 // the stack where a match requires a value to flow through memory. 4867 operand stackSlotI(sRegI reg) %{ 4868 constraint(ALLOC_IN_RC(stack_slots)); 4869 op_cost(100); 4870 //match(RegI); 4871 format %{ "[sp+$reg]" %} 4872 interface(MEMORY_INTER) %{ 4873 base(0x1); // R1_SP 4874 index(0x0); 4875 scale(0x0); 4876 disp($reg); // Stack Offset 4877 %} 4878 %} 4879 4880 operand stackSlotL(sRegL reg) %{ 4881 constraint(ALLOC_IN_RC(stack_slots)); 4882 op_cost(100); 4883 //match(RegL); 4884 format %{ "[sp+$reg]" %} 4885 interface(MEMORY_INTER) %{ 4886 base(0x1); // R1_SP 4887 index(0x0); 4888 scale(0x0); 4889 disp($reg); // Stack Offset 4890 %} 4891 %} 4892 4893 operand stackSlotP(sRegP reg) %{ 4894 constraint(ALLOC_IN_RC(stack_slots)); 4895 op_cost(100); 4896 //match(RegP); 4897 format %{ "[sp+$reg]" %} 4898 interface(MEMORY_INTER) %{ 4899 base(0x1); // R1_SP 4900 index(0x0); 4901 scale(0x0); 4902 disp($reg); // Stack Offset 4903 %} 4904 %} 4905 4906 operand stackSlotF(sRegF reg) %{ 4907 constraint(ALLOC_IN_RC(stack_slots)); 4908 op_cost(100); 4909 //match(RegF); 4910 format %{ "[sp+$reg]" %} 4911 interface(MEMORY_INTER) %{ 4912 base(0x1); // R1_SP 4913 index(0x0); 4914 scale(0x0); 4915 disp($reg); // Stack Offset 4916 %} 4917 %} 4918 4919 operand stackSlotD(sRegD reg) %{ 4920 constraint(ALLOC_IN_RC(stack_slots)); 4921 op_cost(100); 4922 //match(RegD); 4923 format %{ "[sp+$reg]" %} 4924 interface(MEMORY_INTER) %{ 4925 base(0x1); // R1_SP 4926 index(0x0); 4927 scale(0x0); 4928 disp($reg); // Stack Offset 4929 %} 4930 %} 4931 4932 // Operands for expressing Control Flow 4933 // NOTE: Label is a predefined operand which should not be redefined in 4934 // the AD file. It is generically handled within the ADLC. 4935 4936 //----------Conditional Branch Operands---------------------------------------- 4937 // Comparison Op 4938 // 4939 // This is the operation of the comparison, and is limited to the 4940 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4941 // (!=). 4942 // 4943 // Other attributes of the comparison, such as unsignedness, are specified 4944 // by the comparison instruction that sets a condition code flags register. 4945 // That result is represented by a flags operand whose subtype is appropriate 4946 // to the unsignedness (etc.) of the comparison. 4947 // 4948 // Later, the instruction which matches both the Comparison Op (a Bool) and 4949 // the flags (produced by the Cmp) specifies the coding of the comparison op 4950 // by matching a specific subtype of Bool operand below. 4951 4952 // When used for floating point comparisons: unordered same as less. 4953 operand cmpOp() %{ 4954 match(Bool); 4955 format %{ "" %} 4956 interface(COND_INTER) %{ 4957 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4958 // BO & BI 4959 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4960 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4961 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4962 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4963 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4964 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4965 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4966 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4967 %} 4968 %} 4969 4970 //----------OPERAND CLASSES---------------------------------------------------- 4971 // Operand Classes are groups of operands that are used to simplify 4972 // instruction definitions by not requiring the AD writer to specify 4973 // seperate instructions for every form of operand when the 4974 // instruction accepts multiple operand types with the same basic 4975 // encoding and format. The classic case of this is memory operands. 4976 // Indirect is not included since its use is limited to Compare & Swap. 4977 4978 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass); 4979 // Memory operand where offsets are 4-aligned. Required for ld, std. 4980 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass); 4981 opclass indirectMemory(indirect, indirectNarrow); 4982 4983 // Special opclass for I and ConvL2I. 4984 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 4985 4986 // Operand classes to match encode and decode. iRegN_P2N is only used 4987 // for storeN. I have never seen an encode node elsewhere. 4988 opclass iRegN_P2N(iRegNsrc, iRegP2N); 4989 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass); 4990 4991 //----------PIPELINE----------------------------------------------------------- 4992 4993 pipeline %{ 4994 4995 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM 4996 // J. Res. & Dev., No. 1, Jan. 2002. 4997 4998 //----------ATTRIBUTES--------------------------------------------------------- 4999 attributes %{ 5000 5001 // Power4 instructions are of fixed length. 5002 fixed_size_instructions; 5003 5004 // TODO: if `bundle' means number of instructions fetched 5005 // per cycle, this is 8. If `bundle' means Power4 `group', that is 5006 // max instructions issued per cycle, this is 5. 5007 max_instructions_per_bundle = 8; 5008 5009 // A Power4 instruction is 4 bytes long. 5010 instruction_unit_size = 4; 5011 5012 // The Power4 processor fetches 64 bytes... 5013 instruction_fetch_unit_size = 64; 5014 5015 // ...in one line 5016 instruction_fetch_units = 1 5017 5018 // Unused, list one so that array generated by adlc is not empty. 5019 // Aix compiler chokes if _nop_count = 0. 5020 nops(fxNop); 5021 %} 5022 5023 //----------RESOURCES---------------------------------------------------------- 5024 // Resources are the functional units available to the machine 5025 resources( 5026 PPC_BR, // branch unit 5027 PPC_CR, // condition unit 5028 PPC_FX1, // integer arithmetic unit 1 5029 PPC_FX2, // integer arithmetic unit 2 5030 PPC_LDST1, // load/store unit 1 5031 PPC_LDST2, // load/store unit 2 5032 PPC_FP1, // float arithmetic unit 1 5033 PPC_FP2, // float arithmetic unit 2 5034 PPC_LDST = PPC_LDST1 | PPC_LDST2, 5035 PPC_FX = PPC_FX1 | PPC_FX2, 5036 PPC_FP = PPC_FP1 | PPC_FP2 5037 ); 5038 5039 //----------PIPELINE DESCRIPTION----------------------------------------------- 5040 // Pipeline Description specifies the stages in the machine's pipeline 5041 pipe_desc( 5042 // Power4 longest pipeline path 5043 PPC_IF, // instruction fetch 5044 PPC_IC, 5045 //PPC_BP, // branch prediction 5046 PPC_D0, // decode 5047 PPC_D1, // decode 5048 PPC_D2, // decode 5049 PPC_D3, // decode 5050 PPC_Xfer1, 5051 PPC_GD, // group definition 5052 PPC_MP, // map 5053 PPC_ISS, // issue 5054 PPC_RF, // resource fetch 5055 PPC_EX1, // execute (all units) 5056 PPC_EX2, // execute (FP, LDST) 5057 PPC_EX3, // execute (FP, LDST) 5058 PPC_EX4, // execute (FP) 5059 PPC_EX5, // execute (FP) 5060 PPC_EX6, // execute (FP) 5061 PPC_WB, // write back 5062 PPC_Xfer2, 5063 PPC_CP 5064 ); 5065 5066 //----------PIPELINE CLASSES--------------------------------------------------- 5067 // Pipeline Classes describe the stages in which input and output are 5068 // referenced by the hardware pipeline. 5069 5070 // Simple pipeline classes. 5071 5072 // Default pipeline class. 5073 pipe_class pipe_class_default() %{ 5074 single_instruction; 5075 fixed_latency(2); 5076 %} 5077 5078 // Pipeline class for empty instructions. 5079 pipe_class pipe_class_empty() %{ 5080 single_instruction; 5081 fixed_latency(0); 5082 %} 5083 5084 // Pipeline class for compares. 5085 pipe_class pipe_class_compare() %{ 5086 single_instruction; 5087 fixed_latency(16); 5088 %} 5089 5090 // Pipeline class for traps. 5091 pipe_class pipe_class_trap() %{ 5092 single_instruction; 5093 fixed_latency(100); 5094 %} 5095 5096 // Pipeline class for memory operations. 5097 pipe_class pipe_class_memory() %{ 5098 single_instruction; 5099 fixed_latency(16); 5100 %} 5101 5102 // Pipeline class for call. 5103 pipe_class pipe_class_call() %{ 5104 single_instruction; 5105 fixed_latency(100); 5106 %} 5107 5108 // Define the class for the Nop node. 5109 define %{ 5110 MachNop = pipe_class_default; 5111 %} 5112 5113 %} 5114 5115 //----------INSTRUCTIONS------------------------------------------------------- 5116 5117 // Naming of instructions: 5118 // opA_operB / opA_operB_operC: 5119 // Operation 'op' with one or two source operands 'oper'. Result 5120 // type is A, source operand types are B and C. 5121 // Iff A == B == C, B and C are left out. 5122 // 5123 // The instructions are ordered according to the following scheme: 5124 // - loads 5125 // - load constants 5126 // - prefetch 5127 // - store 5128 // - encode/decode 5129 // - membar 5130 // - conditional moves 5131 // - compare & swap 5132 // - arithmetic and logic operations 5133 // * int: Add, Sub, Mul, Div, Mod 5134 // * int: lShift, arShift, urShift, rot 5135 // * float: Add, Sub, Mul, Div 5136 // * and, or, xor ... 5137 // - register moves: float <-> int, reg <-> stack, repl 5138 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5139 // - conv (low level type cast requiring bit changes (sign extend etc) 5140 // - compares, range & zero checks. 5141 // - branches 5142 // - complex operations, intrinsics, min, max, replicate 5143 // - lock 5144 // - Calls 5145 // 5146 // If there are similar instructions with different types they are sorted: 5147 // int before float 5148 // small before big 5149 // signed before unsigned 5150 // e.g., loadS before loadUS before loadI before loadF. 5151 5152 5153 //----------Load/Store Instructions-------------------------------------------- 5154 5155 //----------Load Instructions-------------------------------------------------- 5156 5157 // Converts byte to int. 5158 // As convB2I_reg, but without match rule. The match rule of convB2I_reg 5159 // reuses the 'amount' operand, but adlc expects that operand specification 5160 // and operands in match rule are equivalent. 5161 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5162 effect(DEF dst, USE src); 5163 format %{ "EXTSB $dst, $src \t// byte->int" %} 5164 size(4); 5165 ins_encode %{ 5166 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5167 __ extsb($dst$$Register, $src$$Register); 5168 %} 5169 ins_pipe(pipe_class_default); 5170 %} 5171 5172 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5173 // match-rule, false predicate 5174 match(Set dst (LoadB mem)); 5175 predicate(false); 5176 5177 format %{ "LBZ $dst, $mem" %} 5178 size(4); 5179 ins_encode( enc_lbz(dst, mem) ); 5180 ins_pipe(pipe_class_memory); 5181 %} 5182 5183 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5184 // match-rule, false predicate 5185 match(Set dst (LoadB mem)); 5186 predicate(false); 5187 5188 format %{ "LBZ $dst, $mem\n\t" 5189 "TWI $dst\n\t" 5190 "ISYNC" %} 5191 size(12); 5192 ins_encode( enc_lbz_ac(dst, mem) ); 5193 ins_pipe(pipe_class_memory); 5194 %} 5195 5196 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5197 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5198 match(Set dst (LoadB mem)); 5199 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5200 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5201 expand %{ 5202 iRegIdst tmp; 5203 loadUB_indirect(tmp, mem); 5204 convB2I_reg_2(dst, tmp); 5205 %} 5206 %} 5207 5208 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5209 match(Set dst (LoadB mem)); 5210 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5211 expand %{ 5212 iRegIdst tmp; 5213 loadUB_indirect_ac(tmp, mem); 5214 convB2I_reg_2(dst, tmp); 5215 %} 5216 %} 5217 5218 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5219 // match-rule, false predicate 5220 match(Set dst (LoadB mem)); 5221 predicate(false); 5222 5223 format %{ "LBZ $dst, $mem" %} 5224 size(4); 5225 ins_encode( enc_lbz(dst, mem) ); 5226 ins_pipe(pipe_class_memory); 5227 %} 5228 5229 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5230 // match-rule, false predicate 5231 match(Set dst (LoadB mem)); 5232 predicate(false); 5233 5234 format %{ "LBZ $dst, $mem\n\t" 5235 "TWI $dst\n\t" 5236 "ISYNC" %} 5237 size(12); 5238 ins_encode( enc_lbz_ac(dst, mem) ); 5239 ins_pipe(pipe_class_memory); 5240 %} 5241 5242 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5243 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5244 match(Set dst (LoadB mem)); 5245 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5246 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5247 5248 expand %{ 5249 iRegIdst tmp; 5250 loadUB_indOffset16(tmp, mem); 5251 convB2I_reg_2(dst, tmp); 5252 %} 5253 %} 5254 5255 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5256 match(Set dst (LoadB mem)); 5257 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5258 5259 expand %{ 5260 iRegIdst tmp; 5261 loadUB_indOffset16_ac(tmp, mem); 5262 convB2I_reg_2(dst, tmp); 5263 %} 5264 %} 5265 5266 // Load Unsigned Byte (8bit UNsigned) into an int reg. 5267 instruct loadUB(iRegIdst dst, memory mem) %{ 5268 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5269 match(Set dst (LoadUB mem)); 5270 ins_cost(MEMORY_REF_COST); 5271 5272 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5273 size(4); 5274 ins_encode( enc_lbz(dst, mem) ); 5275 ins_pipe(pipe_class_memory); 5276 %} 5277 5278 // Load Unsigned Byte (8bit UNsigned) acquire. 5279 instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5280 match(Set dst (LoadUB mem)); 5281 ins_cost(3*MEMORY_REF_COST); 5282 5283 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5284 "TWI $dst\n\t" 5285 "ISYNC" %} 5286 size(12); 5287 ins_encode( enc_lbz_ac(dst, mem) ); 5288 ins_pipe(pipe_class_memory); 5289 %} 5290 5291 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 5292 instruct loadUB2L(iRegLdst dst, memory mem) %{ 5293 match(Set dst (ConvI2L (LoadUB mem))); 5294 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5295 ins_cost(MEMORY_REF_COST); 5296 5297 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5298 size(4); 5299 ins_encode( enc_lbz(dst, mem) ); 5300 ins_pipe(pipe_class_memory); 5301 %} 5302 5303 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5304 match(Set dst (ConvI2L (LoadUB mem))); 5305 ins_cost(3*MEMORY_REF_COST); 5306 5307 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5308 "TWI $dst\n\t" 5309 "ISYNC" %} 5310 size(12); 5311 ins_encode( enc_lbz_ac(dst, mem) ); 5312 ins_pipe(pipe_class_memory); 5313 %} 5314 5315 // Load Short (16bit signed) 5316 instruct loadS(iRegIdst dst, memory mem) %{ 5317 match(Set dst (LoadS mem)); 5318 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5319 ins_cost(MEMORY_REF_COST); 5320 5321 format %{ "LHA $dst, $mem" %} 5322 size(4); 5323 ins_encode %{ 5324 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5325 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5326 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5327 %} 5328 ins_pipe(pipe_class_memory); 5329 %} 5330 5331 // Load Short (16bit signed) acquire. 5332 instruct loadS_ac(iRegIdst dst, memory mem) %{ 5333 match(Set dst (LoadS mem)); 5334 ins_cost(3*MEMORY_REF_COST); 5335 5336 format %{ "LHA $dst, $mem\t acquire\n\t" 5337 "TWI $dst\n\t" 5338 "ISYNC" %} 5339 size(12); 5340 ins_encode %{ 5341 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5342 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5343 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5344 __ twi_0($dst$$Register); 5345 __ isync(); 5346 %} 5347 ins_pipe(pipe_class_memory); 5348 %} 5349 5350 // Load Char (16bit unsigned) 5351 instruct loadUS(iRegIdst dst, memory mem) %{ 5352 match(Set dst (LoadUS mem)); 5353 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5354 ins_cost(MEMORY_REF_COST); 5355 5356 format %{ "LHZ $dst, $mem" %} 5357 size(4); 5358 ins_encode( enc_lhz(dst, mem) ); 5359 ins_pipe(pipe_class_memory); 5360 %} 5361 5362 // Load Char (16bit unsigned) acquire. 5363 instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5364 match(Set dst (LoadUS mem)); 5365 ins_cost(3*MEMORY_REF_COST); 5366 5367 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5368 "TWI $dst\n\t" 5369 "ISYNC" %} 5370 size(12); 5371 ins_encode( enc_lhz_ac(dst, mem) ); 5372 ins_pipe(pipe_class_memory); 5373 %} 5374 5375 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5376 instruct loadUS2L(iRegLdst dst, memory mem) %{ 5377 match(Set dst (ConvI2L (LoadUS mem))); 5378 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5379 ins_cost(MEMORY_REF_COST); 5380 5381 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5382 size(4); 5383 ins_encode( enc_lhz(dst, mem) ); 5384 ins_pipe(pipe_class_memory); 5385 %} 5386 5387 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5388 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5389 match(Set dst (ConvI2L (LoadUS mem))); 5390 ins_cost(3*MEMORY_REF_COST); 5391 5392 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5393 "TWI $dst\n\t" 5394 "ISYNC" %} 5395 size(12); 5396 ins_encode( enc_lhz_ac(dst, mem) ); 5397 ins_pipe(pipe_class_memory); 5398 %} 5399 5400 // Load Integer. 5401 instruct loadI(iRegIdst dst, memory mem) %{ 5402 match(Set dst (LoadI mem)); 5403 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5404 ins_cost(MEMORY_REF_COST); 5405 5406 format %{ "LWZ $dst, $mem" %} 5407 size(4); 5408 ins_encode( enc_lwz(dst, mem) ); 5409 ins_pipe(pipe_class_memory); 5410 %} 5411 5412 // Load Integer acquire. 5413 instruct loadI_ac(iRegIdst dst, memory mem) %{ 5414 match(Set dst (LoadI mem)); 5415 ins_cost(3*MEMORY_REF_COST); 5416 5417 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5418 "TWI $dst\n\t" 5419 "ISYNC" %} 5420 size(12); 5421 ins_encode( enc_lwz_ac(dst, mem) ); 5422 ins_pipe(pipe_class_memory); 5423 %} 5424 5425 // Match loading integer and casting it to unsigned int in 5426 // long register. 5427 // LoadI + ConvI2L + AndL 0xffffffff. 5428 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5429 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5430 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5431 ins_cost(MEMORY_REF_COST); 5432 5433 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5434 size(4); 5435 ins_encode( enc_lwz(dst, mem) ); 5436 ins_pipe(pipe_class_memory); 5437 %} 5438 5439 // Match loading integer and casting it to long. 5440 instruct loadI2L(iRegLdst dst, memory mem) %{ 5441 match(Set dst (ConvI2L (LoadI mem))); 5442 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5443 ins_cost(MEMORY_REF_COST); 5444 5445 format %{ "LWA $dst, $mem \t// loadI2L" %} 5446 size(4); 5447 ins_encode %{ 5448 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5449 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5450 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5451 %} 5452 ins_pipe(pipe_class_memory); 5453 %} 5454 5455 // Match loading integer and casting it to long - acquire. 5456 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5457 match(Set dst (ConvI2L (LoadI mem))); 5458 ins_cost(3*MEMORY_REF_COST); 5459 5460 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5461 "TWI $dst\n\t" 5462 "ISYNC" %} 5463 size(12); 5464 ins_encode %{ 5465 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5466 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5467 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5468 __ twi_0($dst$$Register); 5469 __ isync(); 5470 %} 5471 ins_pipe(pipe_class_memory); 5472 %} 5473 5474 // Load Long - aligned 5475 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5476 match(Set dst (LoadL mem)); 5477 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5478 ins_cost(MEMORY_REF_COST); 5479 5480 format %{ "LD $dst, $mem \t// long" %} 5481 size(4); 5482 ins_encode( enc_ld(dst, mem) ); 5483 ins_pipe(pipe_class_memory); 5484 %} 5485 5486 // Load Long - aligned acquire. 5487 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5488 match(Set dst (LoadL mem)); 5489 ins_cost(3*MEMORY_REF_COST); 5490 5491 format %{ "LD $dst, $mem \t// long acquire\n\t" 5492 "TWI $dst\n\t" 5493 "ISYNC" %} 5494 size(12); 5495 ins_encode( enc_ld_ac(dst, mem) ); 5496 ins_pipe(pipe_class_memory); 5497 %} 5498 5499 // Load Long - UNaligned 5500 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5501 match(Set dst (LoadL_unaligned mem)); 5502 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5503 ins_cost(MEMORY_REF_COST); 5504 5505 format %{ "LD $dst, $mem \t// unaligned long" %} 5506 size(4); 5507 ins_encode( enc_ld(dst, mem) ); 5508 ins_pipe(pipe_class_memory); 5509 %} 5510 5511 // Load nodes for superwords 5512 5513 // Load Aligned Packed Byte 5514 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5515 predicate(n->as_LoadVector()->memory_size() == 8); 5516 match(Set dst (LoadVector mem)); 5517 ins_cost(MEMORY_REF_COST); 5518 5519 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5520 size(4); 5521 ins_encode( enc_ld(dst, mem) ); 5522 ins_pipe(pipe_class_memory); 5523 %} 5524 5525 // Load Range, range = array length (=jint) 5526 instruct loadRange(iRegIdst dst, memory mem) %{ 5527 match(Set dst (LoadRange mem)); 5528 ins_cost(MEMORY_REF_COST); 5529 5530 format %{ "LWZ $dst, $mem \t// range" %} 5531 size(4); 5532 ins_encode( enc_lwz(dst, mem) ); 5533 ins_pipe(pipe_class_memory); 5534 %} 5535 5536 // Load Compressed Pointer 5537 instruct loadN(iRegNdst dst, memory mem) %{ 5538 match(Set dst (LoadN mem)); 5539 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5540 ins_cost(MEMORY_REF_COST); 5541 5542 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5543 size(4); 5544 ins_encode( enc_lwz(dst, mem) ); 5545 ins_pipe(pipe_class_memory); 5546 %} 5547 5548 // Load Compressed Pointer acquire. 5549 instruct loadN_ac(iRegNdst dst, memory mem) %{ 5550 match(Set dst (LoadN mem)); 5551 ins_cost(3*MEMORY_REF_COST); 5552 5553 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5554 "TWI $dst\n\t" 5555 "ISYNC" %} 5556 size(12); 5557 ins_encode( enc_lwz_ac(dst, mem) ); 5558 ins_pipe(pipe_class_memory); 5559 %} 5560 5561 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5562 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5563 match(Set dst (DecodeN (LoadN mem))); 5564 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5565 ins_cost(MEMORY_REF_COST); 5566 5567 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5568 size(4); 5569 ins_encode( enc_lwz(dst, mem) ); 5570 ins_pipe(pipe_class_memory); 5571 %} 5572 5573 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{ 5574 match(Set dst (DecodeNKlass (LoadNKlass mem))); 5575 // SAPJVM GL 2014-05-21 Differs. 5576 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 && 5577 _kids[0]->_leaf->as_Load()->is_unordered()); 5578 ins_cost(MEMORY_REF_COST); 5579 5580 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5581 size(4); 5582 ins_encode( enc_lwz(dst, mem) ); 5583 ins_pipe(pipe_class_memory); 5584 %} 5585 5586 // Load Pointer 5587 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5588 match(Set dst (LoadP mem)); 5589 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5590 ins_cost(MEMORY_REF_COST); 5591 5592 format %{ "LD $dst, $mem \t// ptr" %} 5593 size(4); 5594 ins_encode( enc_ld(dst, mem) ); 5595 ins_pipe(pipe_class_memory); 5596 %} 5597 5598 // Load Pointer acquire. 5599 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5600 match(Set dst (LoadP mem)); 5601 ins_cost(3*MEMORY_REF_COST); 5602 5603 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5604 "TWI $dst\n\t" 5605 "ISYNC" %} 5606 size(12); 5607 ins_encode( enc_ld_ac(dst, mem) ); 5608 ins_pipe(pipe_class_memory); 5609 %} 5610 5611 // LoadP + CastP2L 5612 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5613 match(Set dst (CastP2X (LoadP mem))); 5614 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5615 ins_cost(MEMORY_REF_COST); 5616 5617 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5618 size(4); 5619 ins_encode( enc_ld(dst, mem) ); 5620 ins_pipe(pipe_class_memory); 5621 %} 5622 5623 // Load compressed klass pointer. 5624 instruct loadNKlass(iRegNdst dst, memory mem) %{ 5625 match(Set dst (LoadNKlass mem)); 5626 ins_cost(MEMORY_REF_COST); 5627 5628 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5629 size(4); 5630 ins_encode( enc_lwz(dst, mem) ); 5631 ins_pipe(pipe_class_memory); 5632 %} 5633 5634 // Load Klass Pointer 5635 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5636 match(Set dst (LoadKlass mem)); 5637 ins_cost(MEMORY_REF_COST); 5638 5639 format %{ "LD $dst, $mem \t// klass ptr" %} 5640 size(4); 5641 ins_encode( enc_ld(dst, mem) ); 5642 ins_pipe(pipe_class_memory); 5643 %} 5644 5645 // Load Float 5646 instruct loadF(regF dst, memory mem) %{ 5647 match(Set dst (LoadF mem)); 5648 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5649 ins_cost(MEMORY_REF_COST); 5650 5651 format %{ "LFS $dst, $mem" %} 5652 size(4); 5653 ins_encode %{ 5654 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5655 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5656 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5657 %} 5658 ins_pipe(pipe_class_memory); 5659 %} 5660 5661 // Load Float acquire. 5662 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{ 5663 match(Set dst (LoadF mem)); 5664 effect(TEMP cr0); 5665 ins_cost(3*MEMORY_REF_COST); 5666 5667 format %{ "LFS $dst, $mem \t// acquire\n\t" 5668 "FCMPU cr0, $dst, $dst\n\t" 5669 "BNE cr0, next\n" 5670 "next:\n\t" 5671 "ISYNC" %} 5672 size(16); 5673 ins_encode %{ 5674 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5675 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5676 Label next; 5677 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5678 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5679 __ bne(CCR0, next); 5680 __ bind(next); 5681 __ isync(); 5682 %} 5683 ins_pipe(pipe_class_memory); 5684 %} 5685 5686 // Load Double - aligned 5687 instruct loadD(regD dst, memory mem) %{ 5688 match(Set dst (LoadD mem)); 5689 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5690 ins_cost(MEMORY_REF_COST); 5691 5692 format %{ "LFD $dst, $mem" %} 5693 size(4); 5694 ins_encode( enc_lfd(dst, mem) ); 5695 ins_pipe(pipe_class_memory); 5696 %} 5697 5698 // Load Double - aligned acquire. 5699 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{ 5700 match(Set dst (LoadD mem)); 5701 effect(TEMP cr0); 5702 ins_cost(3*MEMORY_REF_COST); 5703 5704 format %{ "LFD $dst, $mem \t// acquire\n\t" 5705 "FCMPU cr0, $dst, $dst\n\t" 5706 "BNE cr0, next\n" 5707 "next:\n\t" 5708 "ISYNC" %} 5709 size(16); 5710 ins_encode %{ 5711 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5712 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5713 Label next; 5714 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5715 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5716 __ bne(CCR0, next); 5717 __ bind(next); 5718 __ isync(); 5719 %} 5720 ins_pipe(pipe_class_memory); 5721 %} 5722 5723 // Load Double - UNaligned 5724 instruct loadD_unaligned(regD dst, memory mem) %{ 5725 match(Set dst (LoadD_unaligned mem)); 5726 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5727 ins_cost(MEMORY_REF_COST); 5728 5729 format %{ "LFD $dst, $mem" %} 5730 size(4); 5731 ins_encode( enc_lfd(dst, mem) ); 5732 ins_pipe(pipe_class_memory); 5733 %} 5734 5735 //----------Constants-------------------------------------------------------- 5736 5737 // Load MachConstantTableBase: add hi offset to global toc. 5738 // TODO: Handle hidden register r29 in bundler! 5739 instruct loadToc_hi(iRegLdst dst) %{ 5740 effect(DEF dst); 5741 ins_cost(DEFAULT_COST); 5742 5743 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5744 size(4); 5745 ins_encode %{ 5746 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5747 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5748 %} 5749 ins_pipe(pipe_class_default); 5750 %} 5751 5752 // Load MachConstantTableBase: add lo offset to global toc. 5753 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5754 effect(DEF dst, USE src); 5755 ins_cost(DEFAULT_COST); 5756 5757 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5758 size(4); 5759 ins_encode %{ 5760 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5761 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5762 %} 5763 ins_pipe(pipe_class_default); 5764 %} 5765 5766 // Load 16-bit integer constant 0xssss???? 5767 instruct loadConI16(iRegIdst dst, immI16 src) %{ 5768 match(Set dst src); 5769 5770 format %{ "LI $dst, $src" %} 5771 size(4); 5772 ins_encode %{ 5773 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5774 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5775 %} 5776 ins_pipe(pipe_class_default); 5777 %} 5778 5779 // Load integer constant 0x????0000 5780 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5781 match(Set dst src); 5782 ins_cost(DEFAULT_COST); 5783 5784 format %{ "LIS $dst, $src.hi" %} 5785 size(4); 5786 ins_encode %{ 5787 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5788 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5789 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5790 %} 5791 ins_pipe(pipe_class_default); 5792 %} 5793 5794 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5795 // and sign extended), this adds the low 16 bits. 5796 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5797 // no match-rule, false predicate 5798 effect(DEF dst, USE src1, USE src2); 5799 predicate(false); 5800 5801 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5802 size(4); 5803 ins_encode %{ 5804 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5805 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5806 %} 5807 ins_pipe(pipe_class_default); 5808 %} 5809 5810 instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5811 match(Set dst src); 5812 ins_cost(DEFAULT_COST*2); 5813 5814 expand %{ 5815 // Would like to use $src$$constant. 5816 immI16 srcLo %{ _opnds[1]->constant() %} 5817 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5818 immIhi16 srcHi %{ _opnds[1]->constant() %} 5819 iRegIdst tmpI; 5820 loadConIhi16(tmpI, srcHi); 5821 loadConI32_lo16(dst, tmpI, srcLo); 5822 %} 5823 %} 5824 5825 // No constant pool entries required. 5826 instruct loadConL16(iRegLdst dst, immL16 src) %{ 5827 match(Set dst src); 5828 5829 format %{ "LI $dst, $src \t// long" %} 5830 size(4); 5831 ins_encode %{ 5832 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5833 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5834 %} 5835 ins_pipe(pipe_class_default); 5836 %} 5837 5838 // Load long constant 0xssssssss????0000 5839 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5840 match(Set dst src); 5841 ins_cost(DEFAULT_COST); 5842 5843 format %{ "LIS $dst, $src.hi \t// long" %} 5844 size(4); 5845 ins_encode %{ 5846 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5847 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5848 %} 5849 ins_pipe(pipe_class_default); 5850 %} 5851 5852 // To load a 32 bit constant: merge lower 16 bits into already loaded 5853 // high 16 bits. 5854 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5855 // no match-rule, false predicate 5856 effect(DEF dst, USE src1, USE src2); 5857 predicate(false); 5858 5859 format %{ "ORI $dst, $src1, $src2.lo" %} 5860 size(4); 5861 ins_encode %{ 5862 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5863 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5864 %} 5865 ins_pipe(pipe_class_default); 5866 %} 5867 5868 // Load 32-bit long constant 5869 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5870 match(Set dst src); 5871 ins_cost(DEFAULT_COST*2); 5872 5873 expand %{ 5874 // Would like to use $src$$constant. 5875 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5876 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5877 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5878 iRegLdst tmpL; 5879 loadConL32hi16(tmpL, srcHi); 5880 loadConL32_lo16(dst, tmpL, srcLo); 5881 %} 5882 %} 5883 5884 // Load long constant 0x????000000000000. 5885 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5886 match(Set dst src); 5887 ins_cost(DEFAULT_COST); 5888 5889 expand %{ 5890 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5891 immI shift32 %{ 32 %} 5892 iRegLdst tmpL; 5893 loadConL32hi16(tmpL, srcHi); 5894 lshiftL_regL_immI(dst, tmpL, shift32); 5895 %} 5896 %} 5897 5898 // Expand node for constant pool load: small offset. 5899 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5900 effect(DEF dst, USE src, USE toc); 5901 ins_cost(MEMORY_REF_COST); 5902 5903 ins_num_consts(1); 5904 // Needed so that CallDynamicJavaDirect can compute the address of this 5905 // instruction for relocation. 5906 ins_field_cbuf_insts_offset(int); 5907 5908 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5909 size(4); 5910 ins_encode( enc_load_long_constL(dst, src, toc) ); 5911 ins_pipe(pipe_class_memory); 5912 %} 5913 5914 // Expand node for constant pool load: large offset. 5915 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5916 effect(DEF dst, USE src, USE toc); 5917 predicate(false); 5918 5919 ins_num_consts(1); 5920 ins_field_const_toc_offset(int); 5921 // Needed so that CallDynamicJavaDirect can compute the address of this 5922 // instruction for relocation. 5923 ins_field_cbuf_insts_offset(int); 5924 5925 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5926 size(4); 5927 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5928 ins_pipe(pipe_class_default); 5929 %} 5930 5931 // Expand node for constant pool load: large offset. 5932 // No constant pool entries required. 5933 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5934 effect(DEF dst, USE src, USE base); 5935 predicate(false); 5936 5937 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5938 5939 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5940 size(4); 5941 ins_encode %{ 5942 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5943 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5944 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5945 %} 5946 ins_pipe(pipe_class_memory); 5947 %} 5948 5949 // Load long constant from constant table. Expand in case of 5950 // offset > 16 bit is needed. 5951 // Adlc adds toc node MachConstantTableBase. 5952 instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5953 match(Set dst src); 5954 ins_cost(MEMORY_REF_COST); 5955 5956 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5957 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5958 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5959 %} 5960 5961 // Load NULL as compressed oop. 5962 instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5963 match(Set dst src); 5964 ins_cost(DEFAULT_COST); 5965 5966 format %{ "LI $dst, $src \t// compressed ptr" %} 5967 size(4); 5968 ins_encode %{ 5969 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5970 __ li($dst$$Register, 0); 5971 %} 5972 ins_pipe(pipe_class_default); 5973 %} 5974 5975 // Load hi part of compressed oop constant. 5976 instruct loadConN_hi(iRegNdst dst, immN src) %{ 5977 effect(DEF dst, USE src); 5978 ins_cost(DEFAULT_COST); 5979 5980 format %{ "LIS $dst, $src \t// narrow oop hi" %} 5981 size(4); 5982 ins_encode %{ 5983 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5984 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 5985 %} 5986 ins_pipe(pipe_class_default); 5987 %} 5988 5989 // Add lo part of compressed oop constant to already loaded hi part. 5990 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 5991 effect(DEF dst, USE src1, USE src2); 5992 ins_cost(DEFAULT_COST); 5993 5994 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 5995 size(4); 5996 ins_encode %{ 5997 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5998 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5999 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 6000 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6001 __ relocate(rspec, 1); 6002 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 6003 %} 6004 ins_pipe(pipe_class_default); 6005 %} 6006 6007 // Needed to postalloc expand loadConN: ConN is loaded as ConI 6008 // leaving the upper 32 bits with sign-extension bits. 6009 // This clears these bits: dst = src & 0xFFFFFFFF. 6010 // TODO: Eventually call this maskN_regN_FFFFFFFF. 6011 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 6012 effect(DEF dst, USE src); 6013 predicate(false); 6014 6015 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 6016 size(4); 6017 ins_encode %{ 6018 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6019 __ clrldi($dst$$Register, $src$$Register, 0x20); 6020 %} 6021 ins_pipe(pipe_class_default); 6022 %} 6023 6024 // Optimize DecodeN for disjoint base. 6025 // Load base of compressed oops into a register 6026 instruct loadBase(iRegLdst dst) %{ 6027 effect(DEF dst); 6028 6029 format %{ "LoadConst $dst, heapbase" %} 6030 ins_encode %{ 6031 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6032 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0); 6033 %} 6034 ins_pipe(pipe_class_default); 6035 %} 6036 6037 // Loading ConN must be postalloc expanded so that edges between 6038 // the nodes are safe. They may not interfere with a safepoint. 6039 // GL TODO: This needs three instructions: better put this into the constant pool. 6040 instruct loadConN_Ex(iRegNdst dst, immN src) %{ 6041 match(Set dst src); 6042 ins_cost(DEFAULT_COST*2); 6043 6044 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6045 postalloc_expand %{ 6046 MachNode *m1 = new loadConN_hiNode(); 6047 MachNode *m2 = new loadConN_loNode(); 6048 MachNode *m3 = new clearMs32bNode(); 6049 m1->add_req(NULL); 6050 m2->add_req(NULL, m1); 6051 m3->add_req(NULL, m2); 6052 m1->_opnds[0] = op_dst; 6053 m1->_opnds[1] = op_src; 6054 m2->_opnds[0] = op_dst; 6055 m2->_opnds[1] = op_dst; 6056 m2->_opnds[2] = op_src; 6057 m3->_opnds[0] = op_dst; 6058 m3->_opnds[1] = op_dst; 6059 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6060 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6061 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6062 nodes->push(m1); 6063 nodes->push(m2); 6064 nodes->push(m3); 6065 %} 6066 %} 6067 6068 // We have seen a safepoint between the hi and lo parts, and this node was handled 6069 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is 6070 // not a narrow oop. 6071 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 6072 match(Set dst src); 6073 effect(DEF dst, USE src); 6074 ins_cost(DEFAULT_COST); 6075 6076 format %{ "LIS $dst, $src \t// narrow klass hi" %} 6077 size(4); 6078 ins_encode %{ 6079 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6080 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6081 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6082 %} 6083 ins_pipe(pipe_class_default); 6084 %} 6085 6086 // As loadConNKlass_hi this must be recognized as narrow klass, not oop! 6087 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6088 match(Set dst src1); 6089 effect(TEMP src2); 6090 ins_cost(DEFAULT_COST); 6091 6092 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 6093 size(4); 6094 ins_encode %{ 6095 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6096 __ clrldi($dst$$Register, $src2$$Register, 0x20); 6097 %} 6098 ins_pipe(pipe_class_default); 6099 %} 6100 6101 // This needs a match rule so that build_oop_map knows this is 6102 // not a narrow oop. 6103 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6104 match(Set dst src1); 6105 effect(TEMP src2); 6106 ins_cost(DEFAULT_COST); 6107 6108 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 6109 size(4); 6110 ins_encode %{ 6111 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 6112 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6113 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6114 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6115 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6116 6117 __ relocate(rspec, 1); 6118 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6119 %} 6120 ins_pipe(pipe_class_default); 6121 %} 6122 6123 // Loading ConNKlass must be postalloc expanded so that edges between 6124 // the nodes are safe. They may not interfere with a safepoint. 6125 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6126 match(Set dst src); 6127 ins_cost(DEFAULT_COST*2); 6128 6129 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6130 postalloc_expand %{ 6131 // Load high bits into register. Sign extended. 6132 MachNode *m1 = new loadConNKlass_hiNode(); 6133 m1->add_req(NULL); 6134 m1->_opnds[0] = op_dst; 6135 m1->_opnds[1] = op_src; 6136 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6137 nodes->push(m1); 6138 6139 MachNode *m2 = m1; 6140 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6141 // Value might be 1-extended. Mask out these bits. 6142 m2 = new loadConNKlass_maskNode(); 6143 m2->add_req(NULL, m1); 6144 m2->_opnds[0] = op_dst; 6145 m2->_opnds[1] = op_src; 6146 m2->_opnds[2] = op_dst; 6147 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6148 nodes->push(m2); 6149 } 6150 6151 MachNode *m3 = new loadConNKlass_loNode(); 6152 m3->add_req(NULL, m2); 6153 m3->_opnds[0] = op_dst; 6154 m3->_opnds[1] = op_src; 6155 m3->_opnds[2] = op_dst; 6156 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6157 nodes->push(m3); 6158 %} 6159 %} 6160 6161 // 0x1 is used in object initialization (initial object header). 6162 // No constant pool entries required. 6163 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6164 match(Set dst src); 6165 6166 format %{ "LI $dst, $src \t// ptr" %} 6167 size(4); 6168 ins_encode %{ 6169 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6170 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6171 %} 6172 ins_pipe(pipe_class_default); 6173 %} 6174 6175 // Expand node for constant pool load: small offset. 6176 // The match rule is needed to generate the correct bottom_type(), 6177 // however this node should never match. The use of predicate is not 6178 // possible since ADLC forbids predicates for chain rules. The higher 6179 // costs do not prevent matching in this case. For that reason the 6180 // operand immP_NM with predicate(false) is used. 6181 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6182 match(Set dst src); 6183 effect(TEMP toc); 6184 6185 ins_num_consts(1); 6186 6187 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6188 size(4); 6189 ins_encode( enc_load_long_constP(dst, src, toc) ); 6190 ins_pipe(pipe_class_memory); 6191 %} 6192 6193 // Expand node for constant pool load: large offset. 6194 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6195 effect(DEF dst, USE src, USE toc); 6196 predicate(false); 6197 6198 ins_num_consts(1); 6199 ins_field_const_toc_offset(int); 6200 6201 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6202 size(4); 6203 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6204 ins_pipe(pipe_class_default); 6205 %} 6206 6207 // Expand node for constant pool load: large offset. 6208 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6209 match(Set dst src); 6210 effect(TEMP base); 6211 6212 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6213 6214 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6215 size(4); 6216 ins_encode %{ 6217 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6218 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6219 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6220 %} 6221 ins_pipe(pipe_class_memory); 6222 %} 6223 6224 // Load pointer constant from constant table. Expand in case an 6225 // offset > 16 bit is needed. 6226 // Adlc adds toc node MachConstantTableBase. 6227 instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6228 match(Set dst src); 6229 ins_cost(MEMORY_REF_COST); 6230 6231 // This rule does not use "expand" because then 6232 // the result type is not known to be an Oop. An ADLC 6233 // enhancement will be needed to make that work - not worth it! 6234 6235 // If this instruction rematerializes, it prolongs the live range 6236 // of the toc node, causing illegal graphs. 6237 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6238 ins_cannot_rematerialize(true); 6239 6240 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6241 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6242 %} 6243 6244 // Expand node for constant pool load: small offset. 6245 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6246 effect(DEF dst, USE src, USE toc); 6247 ins_cost(MEMORY_REF_COST); 6248 6249 ins_num_consts(1); 6250 6251 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6252 size(4); 6253 ins_encode %{ 6254 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6255 address float_address = __ float_constant($src$$constant); 6256 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6257 %} 6258 ins_pipe(pipe_class_memory); 6259 %} 6260 6261 // Expand node for constant pool load: large offset. 6262 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6263 effect(DEF dst, USE src, USE toc); 6264 ins_cost(MEMORY_REF_COST); 6265 6266 ins_num_consts(1); 6267 6268 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6269 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6270 "ADDIS $toc, $toc, -offset_hi"%} 6271 size(12); 6272 ins_encode %{ 6273 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6274 FloatRegister Rdst = $dst$$FloatRegister; 6275 Register Rtoc = $toc$$Register; 6276 address float_address = __ float_constant($src$$constant); 6277 int offset = __ offset_to_method_toc(float_address); 6278 int hi = (offset + (1<<15))>>16; 6279 int lo = offset - hi * (1<<16); 6280 6281 __ addis(Rtoc, Rtoc, hi); 6282 __ lfs(Rdst, lo, Rtoc); 6283 __ addis(Rtoc, Rtoc, -hi); 6284 %} 6285 ins_pipe(pipe_class_memory); 6286 %} 6287 6288 // Adlc adds toc node MachConstantTableBase. 6289 instruct loadConF_Ex(regF dst, immF src) %{ 6290 match(Set dst src); 6291 ins_cost(MEMORY_REF_COST); 6292 6293 // See loadConP. 6294 ins_cannot_rematerialize(true); 6295 6296 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6297 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6298 %} 6299 6300 // Expand node for constant pool load: small offset. 6301 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6302 effect(DEF dst, USE src, USE toc); 6303 ins_cost(MEMORY_REF_COST); 6304 6305 ins_num_consts(1); 6306 6307 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6308 size(4); 6309 ins_encode %{ 6310 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6311 int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); 6312 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6313 %} 6314 ins_pipe(pipe_class_memory); 6315 %} 6316 6317 // Expand node for constant pool load: large offset. 6318 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6319 effect(DEF dst, USE src, USE toc); 6320 ins_cost(MEMORY_REF_COST); 6321 6322 ins_num_consts(1); 6323 6324 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6325 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6326 "ADDIS $toc, $toc, -offset_hi" %} 6327 size(12); 6328 ins_encode %{ 6329 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6330 FloatRegister Rdst = $dst$$FloatRegister; 6331 Register Rtoc = $toc$$Register; 6332 address float_address = __ double_constant($src$$constant); 6333 int offset = __ offset_to_method_toc(float_address); 6334 int hi = (offset + (1<<15))>>16; 6335 int lo = offset - hi * (1<<16); 6336 6337 __ addis(Rtoc, Rtoc, hi); 6338 __ lfd(Rdst, lo, Rtoc); 6339 __ addis(Rtoc, Rtoc, -hi); 6340 %} 6341 ins_pipe(pipe_class_memory); 6342 %} 6343 6344 // Adlc adds toc node MachConstantTableBase. 6345 instruct loadConD_Ex(regD dst, immD src) %{ 6346 match(Set dst src); 6347 ins_cost(MEMORY_REF_COST); 6348 6349 // See loadConP. 6350 ins_cannot_rematerialize(true); 6351 6352 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6353 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6354 %} 6355 6356 // Prefetch instructions. 6357 // Must be safe to execute with invalid address (cannot fault). 6358 6359 // Special prefetch versions which use the dcbz instruction. 6360 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6361 match(PrefetchAllocation (AddP mem src)); 6362 predicate(AllocatePrefetchStyle == 3); 6363 ins_cost(MEMORY_REF_COST); 6364 6365 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6366 size(4); 6367 ins_encode %{ 6368 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6369 __ dcbz($src$$Register, $mem$$base$$Register); 6370 %} 6371 ins_pipe(pipe_class_memory); 6372 %} 6373 6374 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6375 match(PrefetchAllocation mem); 6376 predicate(AllocatePrefetchStyle == 3); 6377 ins_cost(MEMORY_REF_COST); 6378 6379 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6380 size(4); 6381 ins_encode %{ 6382 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6383 __ dcbz($mem$$base$$Register); 6384 %} 6385 ins_pipe(pipe_class_memory); 6386 %} 6387 6388 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6389 match(PrefetchAllocation (AddP mem src)); 6390 predicate(AllocatePrefetchStyle != 3); 6391 ins_cost(MEMORY_REF_COST); 6392 6393 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6394 size(4); 6395 ins_encode %{ 6396 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6397 __ dcbtst($src$$Register, $mem$$base$$Register); 6398 %} 6399 ins_pipe(pipe_class_memory); 6400 %} 6401 6402 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6403 match(PrefetchAllocation mem); 6404 predicate(AllocatePrefetchStyle != 3); 6405 ins_cost(MEMORY_REF_COST); 6406 6407 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6408 size(4); 6409 ins_encode %{ 6410 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6411 __ dcbtst($mem$$base$$Register); 6412 %} 6413 ins_pipe(pipe_class_memory); 6414 %} 6415 6416 //----------Store Instructions------------------------------------------------- 6417 6418 // Store Byte 6419 instruct storeB(memory mem, iRegIsrc src) %{ 6420 match(Set mem (StoreB mem src)); 6421 ins_cost(MEMORY_REF_COST); 6422 6423 format %{ "STB $src, $mem \t// byte" %} 6424 size(4); 6425 ins_encode %{ 6426 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6427 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6428 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6429 %} 6430 ins_pipe(pipe_class_memory); 6431 %} 6432 6433 // Store Char/Short 6434 instruct storeC(memory mem, iRegIsrc src) %{ 6435 match(Set mem (StoreC mem src)); 6436 ins_cost(MEMORY_REF_COST); 6437 6438 format %{ "STH $src, $mem \t// short" %} 6439 size(4); 6440 ins_encode %{ 6441 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6442 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6443 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6444 %} 6445 ins_pipe(pipe_class_memory); 6446 %} 6447 6448 // Store Integer 6449 instruct storeI(memory mem, iRegIsrc src) %{ 6450 match(Set mem (StoreI mem src)); 6451 ins_cost(MEMORY_REF_COST); 6452 6453 format %{ "STW $src, $mem" %} 6454 size(4); 6455 ins_encode( enc_stw(src, mem) ); 6456 ins_pipe(pipe_class_memory); 6457 %} 6458 6459 // ConvL2I + StoreI. 6460 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6461 match(Set mem (StoreI mem (ConvL2I src))); 6462 ins_cost(MEMORY_REF_COST); 6463 6464 format %{ "STW l2i($src), $mem" %} 6465 size(4); 6466 ins_encode( enc_stw(src, mem) ); 6467 ins_pipe(pipe_class_memory); 6468 %} 6469 6470 // Store Long 6471 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6472 match(Set mem (StoreL mem src)); 6473 ins_cost(MEMORY_REF_COST); 6474 6475 format %{ "STD $src, $mem \t// long" %} 6476 size(4); 6477 ins_encode( enc_std(src, mem) ); 6478 ins_pipe(pipe_class_memory); 6479 %} 6480 6481 // Store super word nodes. 6482 6483 // Store Aligned Packed Byte long register to memory 6484 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6485 predicate(n->as_StoreVector()->memory_size() == 8); 6486 match(Set mem (StoreVector mem src)); 6487 ins_cost(MEMORY_REF_COST); 6488 6489 format %{ "STD $mem, $src \t// packed8B" %} 6490 size(4); 6491 ins_encode( enc_std(src, mem) ); 6492 ins_pipe(pipe_class_memory); 6493 %} 6494 6495 // Store Compressed Oop 6496 instruct storeN(memory dst, iRegN_P2N src) %{ 6497 match(Set dst (StoreN dst src)); 6498 ins_cost(MEMORY_REF_COST); 6499 6500 format %{ "STW $src, $dst \t// compressed oop" %} 6501 size(4); 6502 ins_encode( enc_stw(src, dst) ); 6503 ins_pipe(pipe_class_memory); 6504 %} 6505 6506 // Store Compressed KLass 6507 instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6508 match(Set dst (StoreNKlass dst src)); 6509 ins_cost(MEMORY_REF_COST); 6510 6511 format %{ "STW $src, $dst \t// compressed klass" %} 6512 size(4); 6513 ins_encode( enc_stw(src, dst) ); 6514 ins_pipe(pipe_class_memory); 6515 %} 6516 6517 // Store Pointer 6518 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6519 match(Set dst (StoreP dst src)); 6520 ins_cost(MEMORY_REF_COST); 6521 6522 format %{ "STD $src, $dst \t// ptr" %} 6523 size(4); 6524 ins_encode( enc_std(src, dst) ); 6525 ins_pipe(pipe_class_memory); 6526 %} 6527 6528 // Store Float 6529 instruct storeF(memory mem, regF src) %{ 6530 match(Set mem (StoreF mem src)); 6531 ins_cost(MEMORY_REF_COST); 6532 6533 format %{ "STFS $src, $mem" %} 6534 size(4); 6535 ins_encode( enc_stfs(src, mem) ); 6536 ins_pipe(pipe_class_memory); 6537 %} 6538 6539 // Store Double 6540 instruct storeD(memory mem, regD src) %{ 6541 match(Set mem (StoreD mem src)); 6542 ins_cost(MEMORY_REF_COST); 6543 6544 format %{ "STFD $src, $mem" %} 6545 size(4); 6546 ins_encode( enc_stfd(src, mem) ); 6547 ins_pipe(pipe_class_memory); 6548 %} 6549 6550 //----------Store Instructions With Zeros-------------------------------------- 6551 6552 // Card-mark for CMS garbage collection. 6553 // This cardmark does an optimization so that it must not always 6554 // do a releasing store. For this, it gets the address of 6555 // CMSCollectorCardTableModRefBSExt::_requires_release as input. 6556 // (Using releaseFieldAddr in the match rule is a hack.) 6557 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 6558 match(Set mem (StoreCM mem releaseFieldAddr)); 6559 effect(TEMP crx); 6560 predicate(false); 6561 ins_cost(MEMORY_REF_COST); 6562 6563 // See loadConP. 6564 ins_cannot_rematerialize(true); 6565 6566 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6567 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) ); 6568 ins_pipe(pipe_class_memory); 6569 %} 6570 6571 // Card-mark for CMS garbage collection. 6572 // This cardmark does an optimization so that it must not always 6573 // do a releasing store. For this, it needs the constant address of 6574 // CMSCollectorCardTableModRefBSExt::_requires_release. 6575 // This constant address is split off here by expand so we can use 6576 // adlc / matcher functionality to load it from the constant section. 6577 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6578 match(Set mem (StoreCM mem zero)); 6579 predicate(UseConcMarkSweepGC); 6580 6581 expand %{ 6582 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6583 iRegLdst releaseFieldAddress; 6584 flagsReg crx; 6585 loadConL_Ex(releaseFieldAddress, baseImm); 6586 storeCM_CMS(mem, releaseFieldAddress, crx); 6587 %} 6588 %} 6589 6590 instruct storeCM_G1(memory mem, immI_0 zero) %{ 6591 match(Set mem (StoreCM mem zero)); 6592 predicate(UseG1GC); 6593 ins_cost(MEMORY_REF_COST); 6594 6595 ins_cannot_rematerialize(true); 6596 6597 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6598 size(8); 6599 ins_encode %{ 6600 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6601 __ li(R0, 0); 6602 //__ release(); // G1: oops are allowed to get visible after dirty marking 6603 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6604 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6605 %} 6606 ins_pipe(pipe_class_memory); 6607 %} 6608 6609 // Convert oop pointer into compressed form. 6610 6611 // Nodes for postalloc expand. 6612 6613 // Shift node for expand. 6614 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6615 // The match rule is needed to make it a 'MachTypeNode'! 6616 match(Set dst (EncodeP src)); 6617 predicate(false); 6618 6619 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6620 size(4); 6621 ins_encode %{ 6622 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6623 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6624 %} 6625 ins_pipe(pipe_class_default); 6626 %} 6627 6628 // Add node for expand. 6629 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6630 // The match rule is needed to make it a 'MachTypeNode'! 6631 match(Set dst (EncodeP src)); 6632 predicate(false); 6633 6634 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6635 ins_encode %{ 6636 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6637 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6638 %} 6639 ins_pipe(pipe_class_default); 6640 %} 6641 6642 // Conditional sub base. 6643 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6644 // The match rule is needed to make it a 'MachTypeNode'! 6645 match(Set dst (EncodeP (Binary crx src1))); 6646 predicate(false); 6647 6648 format %{ "BEQ $crx, done\n\t" 6649 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n" 6650 "done:" %} 6651 ins_encode %{ 6652 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6653 Label done; 6654 __ beq($crx$$CondRegister, done); 6655 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0); 6656 __ bind(done); 6657 %} 6658 ins_pipe(pipe_class_default); 6659 %} 6660 6661 // Power 7 can use isel instruction 6662 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6663 // The match rule is needed to make it a 'MachTypeNode'! 6664 match(Set dst (EncodeP (Binary crx src1))); 6665 predicate(false); 6666 6667 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6668 size(4); 6669 ins_encode %{ 6670 // This is a Power7 instruction for which no machine description exists. 6671 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6672 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6673 %} 6674 ins_pipe(pipe_class_default); 6675 %} 6676 6677 // Disjoint narrow oop base. 6678 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6679 match(Set dst (EncodeP src)); 6680 predicate(Universe::narrow_oop_base_disjoint()); 6681 6682 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6683 size(4); 6684 ins_encode %{ 6685 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6686 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6687 %} 6688 ins_pipe(pipe_class_default); 6689 %} 6690 6691 // shift != 0, base != 0 6692 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6693 match(Set dst (EncodeP src)); 6694 effect(TEMP crx); 6695 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6696 Universe::narrow_oop_shift() != 0 && 6697 Universe::narrow_oop_base_overlaps()); 6698 6699 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6700 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6701 %} 6702 6703 // shift != 0, base != 0 6704 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6705 match(Set dst (EncodeP src)); 6706 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6707 Universe::narrow_oop_shift() != 0 && 6708 Universe::narrow_oop_base_overlaps()); 6709 6710 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6711 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6712 %} 6713 6714 // shift != 0, base == 0 6715 // TODO: This is the same as encodeP_shift. Merge! 6716 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6717 match(Set dst (EncodeP src)); 6718 predicate(Universe::narrow_oop_shift() != 0 && 6719 Universe::narrow_oop_base() ==0); 6720 6721 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6722 size(4); 6723 ins_encode %{ 6724 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6725 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6726 %} 6727 ins_pipe(pipe_class_default); 6728 %} 6729 6730 // Compressed OOPs with narrow_oop_shift == 0. 6731 // shift == 0, base == 0 6732 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6733 match(Set dst (EncodeP src)); 6734 predicate(Universe::narrow_oop_shift() == 0); 6735 6736 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6737 // variable size, 0 or 4. 6738 ins_encode %{ 6739 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6740 __ mr_if_needed($dst$$Register, $src$$Register); 6741 %} 6742 ins_pipe(pipe_class_default); 6743 %} 6744 6745 // Decode nodes. 6746 6747 // Shift node for expand. 6748 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6749 // The match rule is needed to make it a 'MachTypeNode'! 6750 match(Set dst (DecodeN src)); 6751 predicate(false); 6752 6753 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6754 size(4); 6755 ins_encode %{ 6756 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6757 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6758 %} 6759 ins_pipe(pipe_class_default); 6760 %} 6761 6762 // Add node for expand. 6763 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6764 // The match rule is needed to make it a 'MachTypeNode'! 6765 match(Set dst (DecodeN src)); 6766 predicate(false); 6767 6768 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %} 6769 ins_encode %{ 6770 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6771 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6772 %} 6773 ins_pipe(pipe_class_default); 6774 %} 6775 6776 // conditianal add base for expand 6777 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{ 6778 // The match rule is needed to make it a 'MachTypeNode'! 6779 // NOTICE that the rule is nonsense - we just have to make sure that: 6780 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6781 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6782 match(Set dst (DecodeN (Binary crx src))); 6783 predicate(false); 6784 6785 format %{ "BEQ $crx, done\n\t" 6786 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n" 6787 "done:" %} 6788 ins_encode %{ 6789 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6790 Label done; 6791 __ beq($crx$$CondRegister, done); 6792 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6793 __ bind(done); 6794 %} 6795 ins_pipe(pipe_class_default); 6796 %} 6797 6798 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6799 // The match rule is needed to make it a 'MachTypeNode'! 6800 // NOTICE that the rule is nonsense - we just have to make sure that: 6801 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6802 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6803 match(Set dst (DecodeN (Binary crx src1))); 6804 predicate(false); 6805 6806 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6807 size(4); 6808 ins_encode %{ 6809 // This is a Power7 instruction for which no machine description exists. 6810 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6811 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6812 %} 6813 ins_pipe(pipe_class_default); 6814 %} 6815 6816 // shift != 0, base != 0 6817 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6818 match(Set dst (DecodeN src)); 6819 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6820 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6821 Universe::narrow_oop_shift() != 0 && 6822 Universe::narrow_oop_base() != 0); 6823 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex. 6824 effect(TEMP crx); 6825 6826 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6827 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6828 %} 6829 6830 // shift != 0, base == 0 6831 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6832 match(Set dst (DecodeN src)); 6833 predicate(Universe::narrow_oop_shift() != 0 && 6834 Universe::narrow_oop_base() == 0); 6835 6836 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6837 size(4); 6838 ins_encode %{ 6839 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6840 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6841 %} 6842 ins_pipe(pipe_class_default); 6843 %} 6844 6845 // Optimize DecodeN for disjoint base. 6846 // Shift narrow oop and or it into register that already contains the heap base. 6847 // Base == dst must hold, and is assured by construction in postaloc_expand. 6848 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{ 6849 match(Set dst (DecodeN src)); 6850 effect(TEMP base); 6851 predicate(false); 6852 6853 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %} 6854 size(4); 6855 ins_encode %{ 6856 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 6857 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift()); 6858 %} 6859 ins_pipe(pipe_class_default); 6860 %} 6861 6862 // Optimize DecodeN for disjoint base. 6863 // This node requires only one cycle on the critical path. 6864 // We must postalloc_expand as we can not express use_def effects where 6865 // the used register is L and the def'ed register P. 6866 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{ 6867 match(Set dst (DecodeN src)); 6868 effect(TEMP_DEF dst); 6869 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6870 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6871 Universe::narrow_oop_base_disjoint()); 6872 ins_cost(DEFAULT_COST); 6873 6874 format %{ "MOV $dst, heapbase \t\n" 6875 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %} 6876 postalloc_expand %{ 6877 loadBaseNode *n1 = new loadBaseNode(); 6878 n1->add_req(NULL); 6879 n1->_opnds[0] = op_dst; 6880 6881 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6882 n2->add_req(n_region, n_src, n1); 6883 n2->_opnds[0] = op_dst; 6884 n2->_opnds[1] = op_src; 6885 n2->_opnds[2] = op_dst; 6886 n2->_bottom_type = _bottom_type; 6887 6888 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6889 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6890 6891 nodes->push(n1); 6892 nodes->push(n2); 6893 %} 6894 %} 6895 6896 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6897 match(Set dst (DecodeN src)); 6898 effect(TEMP_DEF dst, TEMP crx); 6899 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6900 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6901 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel()); 6902 ins_cost(3 * DEFAULT_COST); 6903 6904 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %} 6905 postalloc_expand %{ 6906 loadBaseNode *n1 = new loadBaseNode(); 6907 n1->add_req(NULL); 6908 n1->_opnds[0] = op_dst; 6909 6910 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 6911 n_compare->add_req(n_region, n_src); 6912 n_compare->_opnds[0] = op_crx; 6913 n_compare->_opnds[1] = op_src; 6914 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 6915 6916 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6917 n2->add_req(n_region, n_src, n1); 6918 n2->_opnds[0] = op_dst; 6919 n2->_opnds[1] = op_src; 6920 n2->_opnds[2] = op_dst; 6921 n2->_bottom_type = _bottom_type; 6922 6923 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 6924 n_cond_set->add_req(n_region, n_compare, n2); 6925 n_cond_set->_opnds[0] = op_dst; 6926 n_cond_set->_opnds[1] = op_crx; 6927 n_cond_set->_opnds[2] = op_dst; 6928 n_cond_set->_bottom_type = _bottom_type; 6929 6930 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 6931 ra_->set_oop(n_cond_set, true); 6932 6933 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6934 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 6935 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6936 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6937 6938 nodes->push(n1); 6939 nodes->push(n_compare); 6940 nodes->push(n2); 6941 nodes->push(n_cond_set); 6942 %} 6943 %} 6944 6945 // src != 0, shift != 0, base != 0 6946 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 6947 match(Set dst (DecodeN src)); 6948 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6949 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6950 Universe::narrow_oop_shift() != 0 && 6951 Universe::narrow_oop_base() != 0); 6952 ins_cost(2 * DEFAULT_COST); 6953 6954 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 6955 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 6956 %} 6957 6958 // Compressed OOPs with narrow_oop_shift == 0. 6959 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 6960 match(Set dst (DecodeN src)); 6961 predicate(Universe::narrow_oop_shift() == 0); 6962 ins_cost(DEFAULT_COST); 6963 6964 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 6965 // variable size, 0 or 4. 6966 ins_encode %{ 6967 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6968 __ mr_if_needed($dst$$Register, $src$$Register); 6969 %} 6970 ins_pipe(pipe_class_default); 6971 %} 6972 6973 // Convert compressed oop into int for vectors alignment masking. 6974 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 6975 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6976 predicate(Universe::narrow_oop_shift() == 0); 6977 ins_cost(DEFAULT_COST); 6978 6979 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 6980 // variable size, 0 or 4. 6981 ins_encode %{ 6982 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6983 __ mr_if_needed($dst$$Register, $src$$Register); 6984 %} 6985 ins_pipe(pipe_class_default); 6986 %} 6987 6988 // Convert klass pointer into compressed form. 6989 6990 // Nodes for postalloc expand. 6991 6992 // Shift node for expand. 6993 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 6994 // The match rule is needed to make it a 'MachTypeNode'! 6995 match(Set dst (EncodePKlass src)); 6996 predicate(false); 6997 6998 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6999 size(4); 7000 ins_encode %{ 7001 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 7002 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7003 %} 7004 ins_pipe(pipe_class_default); 7005 %} 7006 7007 // Add node for expand. 7008 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7009 // The match rule is needed to make it a 'MachTypeNode'! 7010 match(Set dst (EncodePKlass (Binary base src))); 7011 predicate(false); 7012 7013 format %{ "SUB $dst, $base, $src \t// encode" %} 7014 size(4); 7015 ins_encode %{ 7016 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7017 __ subf($dst$$Register, $base$$Register, $src$$Register); 7018 %} 7019 ins_pipe(pipe_class_default); 7020 %} 7021 7022 // Disjoint narrow oop base. 7023 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{ 7024 match(Set dst (EncodePKlass src)); 7025 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 7026 7027 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 7028 size(4); 7029 ins_encode %{ 7030 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 7031 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 7032 %} 7033 ins_pipe(pipe_class_default); 7034 %} 7035 7036 // shift != 0, base != 0 7037 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 7038 match(Set dst (EncodePKlass (Binary base src))); 7039 predicate(false); 7040 7041 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7042 postalloc_expand %{ 7043 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode(); 7044 n1->add_req(n_region, n_base, n_src); 7045 n1->_opnds[0] = op_dst; 7046 n1->_opnds[1] = op_base; 7047 n1->_opnds[2] = op_src; 7048 n1->_bottom_type = _bottom_type; 7049 7050 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode(); 7051 n2->add_req(n_region, n1); 7052 n2->_opnds[0] = op_dst; 7053 n2->_opnds[1] = op_dst; 7054 n2->_bottom_type = _bottom_type; 7055 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7056 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7057 7058 nodes->push(n1); 7059 nodes->push(n2); 7060 %} 7061 %} 7062 7063 // shift != 0, base != 0 7064 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7065 match(Set dst (EncodePKlass src)); 7066 //predicate(Universe::narrow_klass_shift() != 0 && 7067 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7068 7069 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7070 ins_cost(DEFAULT_COST*2); // Don't count constant. 7071 expand %{ 7072 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7073 iRegLdst base; 7074 loadConL_Ex(base, baseImm); 7075 encodePKlass_not_null_Ex(dst, base, src); 7076 %} 7077 %} 7078 7079 // Decode nodes. 7080 7081 // Shift node for expand. 7082 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7083 // The match rule is needed to make it a 'MachTypeNode'! 7084 match(Set dst (DecodeNKlass src)); 7085 predicate(false); 7086 7087 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7088 size(4); 7089 ins_encode %{ 7090 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7091 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7092 %} 7093 ins_pipe(pipe_class_default); 7094 %} 7095 7096 // Add node for expand. 7097 7098 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7099 // The match rule is needed to make it a 'MachTypeNode'! 7100 match(Set dst (DecodeNKlass (Binary base src))); 7101 predicate(false); 7102 7103 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7104 size(4); 7105 ins_encode %{ 7106 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7107 __ add($dst$$Register, $base$$Register, $src$$Register); 7108 %} 7109 ins_pipe(pipe_class_default); 7110 %} 7111 7112 // src != 0, shift != 0, base != 0 7113 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7114 match(Set dst (DecodeNKlass (Binary base src))); 7115 //effect(kill src); // We need a register for the immediate result after shifting. 7116 predicate(false); 7117 7118 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7119 postalloc_expand %{ 7120 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode(); 7121 n1->add_req(n_region, n_base, n_src); 7122 n1->_opnds[0] = op_dst; 7123 n1->_opnds[1] = op_base; 7124 n1->_opnds[2] = op_src; 7125 n1->_bottom_type = _bottom_type; 7126 7127 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode(); 7128 n2->add_req(n_region, n1); 7129 n2->_opnds[0] = op_dst; 7130 n2->_opnds[1] = op_dst; 7131 n2->_bottom_type = _bottom_type; 7132 7133 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7134 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7135 7136 nodes->push(n1); 7137 nodes->push(n2); 7138 %} 7139 %} 7140 7141 // src != 0, shift != 0, base != 0 7142 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7143 match(Set dst (DecodeNKlass src)); 7144 // predicate(Universe::narrow_klass_shift() != 0 && 7145 // Universe::narrow_klass_base() != 0); 7146 7147 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7148 7149 ins_cost(DEFAULT_COST*2); // Don't count constant. 7150 expand %{ 7151 // We add first, then we shift. Like this, we can get along with one register less. 7152 // But we have to load the base pre-shifted. 7153 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7154 iRegLdst base; 7155 loadConL_Ex(base, baseImm); 7156 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7157 %} 7158 %} 7159 7160 //----------MemBar Instructions----------------------------------------------- 7161 // Memory barrier flavors 7162 7163 instruct membar_acquire() %{ 7164 match(LoadFence); 7165 ins_cost(4*MEMORY_REF_COST); 7166 7167 format %{ "MEMBAR-acquire" %} 7168 size(4); 7169 ins_encode %{ 7170 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7171 __ acquire(); 7172 %} 7173 ins_pipe(pipe_class_default); 7174 %} 7175 7176 instruct unnecessary_membar_acquire() %{ 7177 match(MemBarAcquire); 7178 ins_cost(0); 7179 7180 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7181 size(0); 7182 ins_encode( /*empty*/ ); 7183 ins_pipe(pipe_class_default); 7184 %} 7185 7186 instruct membar_acquire_lock() %{ 7187 match(MemBarAcquireLock); 7188 ins_cost(0); 7189 7190 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7191 size(0); 7192 ins_encode( /*empty*/ ); 7193 ins_pipe(pipe_class_default); 7194 %} 7195 7196 instruct membar_release() %{ 7197 match(MemBarRelease); 7198 match(StoreFence); 7199 ins_cost(4*MEMORY_REF_COST); 7200 7201 format %{ "MEMBAR-release" %} 7202 size(4); 7203 ins_encode %{ 7204 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7205 __ release(); 7206 %} 7207 ins_pipe(pipe_class_default); 7208 %} 7209 7210 instruct membar_storestore() %{ 7211 match(MemBarStoreStore); 7212 ins_cost(4*MEMORY_REF_COST); 7213 7214 format %{ "MEMBAR-store-store" %} 7215 size(4); 7216 ins_encode %{ 7217 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7218 __ membar(Assembler::StoreStore); 7219 %} 7220 ins_pipe(pipe_class_default); 7221 %} 7222 7223 instruct membar_release_lock() %{ 7224 match(MemBarReleaseLock); 7225 ins_cost(0); 7226 7227 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7228 size(0); 7229 ins_encode( /*empty*/ ); 7230 ins_pipe(pipe_class_default); 7231 %} 7232 7233 instruct membar_volatile() %{ 7234 match(MemBarVolatile); 7235 ins_cost(4*MEMORY_REF_COST); 7236 7237 format %{ "MEMBAR-volatile" %} 7238 size(4); 7239 ins_encode %{ 7240 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7241 __ fence(); 7242 %} 7243 ins_pipe(pipe_class_default); 7244 %} 7245 7246 // This optimization is wrong on PPC. The following pattern is not supported: 7247 // MemBarVolatile 7248 // ^ ^ 7249 // | | 7250 // CtrlProj MemProj 7251 // ^ ^ 7252 // | | 7253 // | Load 7254 // | 7255 // MemBarVolatile 7256 // 7257 // The first MemBarVolatile could get optimized out! According to 7258 // Vladimir, this pattern can not occur on Oracle platforms. 7259 // However, it does occur on PPC64 (because of membars in 7260 // inline_unsafe_load_store). 7261 // 7262 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7263 // Don't forget to look at the implementation of post_store_load_barrier again, 7264 // we did other fixes in that method. 7265 //instruct unnecessary_membar_volatile() %{ 7266 // match(MemBarVolatile); 7267 // predicate(Matcher::post_store_load_barrier(n)); 7268 // ins_cost(0); 7269 // 7270 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7271 // size(0); 7272 // ins_encode( /*empty*/ ); 7273 // ins_pipe(pipe_class_default); 7274 //%} 7275 7276 instruct membar_CPUOrder() %{ 7277 match(MemBarCPUOrder); 7278 ins_cost(0); 7279 7280 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7281 size(0); 7282 ins_encode( /*empty*/ ); 7283 ins_pipe(pipe_class_default); 7284 %} 7285 7286 //----------Conditional Move--------------------------------------------------- 7287 7288 // Cmove using isel. 7289 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7290 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7291 predicate(VM_Version::has_isel()); 7292 ins_cost(DEFAULT_COST); 7293 7294 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7295 size(4); 7296 ins_encode %{ 7297 // This is a Power7 instruction for which no machine description 7298 // exists. Anyways, the scheduler should be off on Power7. 7299 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7300 int cc = $cmp$$cmpcode; 7301 __ isel($dst$$Register, $crx$$CondRegister, 7302 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7303 %} 7304 ins_pipe(pipe_class_default); 7305 %} 7306 7307 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7308 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7309 predicate(!VM_Version::has_isel()); 7310 ins_cost(DEFAULT_COST+BRANCH_COST); 7311 7312 ins_variable_size_depending_on_alignment(true); 7313 7314 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7315 // Worst case is branch + move + stop, no stop without scheduler 7316 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7317 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7318 ins_pipe(pipe_class_default); 7319 %} 7320 7321 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{ 7322 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7323 ins_cost(DEFAULT_COST+BRANCH_COST); 7324 7325 ins_variable_size_depending_on_alignment(true); 7326 7327 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7328 // Worst case is branch + move + stop, no stop without scheduler 7329 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7330 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7331 ins_pipe(pipe_class_default); 7332 %} 7333 7334 // Cmove using isel. 7335 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7336 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7337 predicate(VM_Version::has_isel()); 7338 ins_cost(DEFAULT_COST); 7339 7340 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7341 size(4); 7342 ins_encode %{ 7343 // This is a Power7 instruction for which no machine description 7344 // exists. Anyways, the scheduler should be off on Power7. 7345 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7346 int cc = $cmp$$cmpcode; 7347 __ isel($dst$$Register, $crx$$CondRegister, 7348 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7349 %} 7350 ins_pipe(pipe_class_default); 7351 %} 7352 7353 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7354 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7355 predicate(!VM_Version::has_isel()); 7356 ins_cost(DEFAULT_COST+BRANCH_COST); 7357 7358 ins_variable_size_depending_on_alignment(true); 7359 7360 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7361 // Worst case is branch + move + stop, no stop without scheduler. 7362 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7363 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7364 ins_pipe(pipe_class_default); 7365 %} 7366 7367 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{ 7368 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7369 ins_cost(DEFAULT_COST+BRANCH_COST); 7370 7371 ins_variable_size_depending_on_alignment(true); 7372 7373 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7374 // Worst case is branch + move + stop, no stop without scheduler. 7375 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7376 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7377 ins_pipe(pipe_class_default); 7378 %} 7379 7380 // Cmove using isel. 7381 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7382 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7383 predicate(VM_Version::has_isel()); 7384 ins_cost(DEFAULT_COST); 7385 7386 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7387 size(4); 7388 ins_encode %{ 7389 // This is a Power7 instruction for which no machine description 7390 // exists. Anyways, the scheduler should be off on Power7. 7391 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7392 int cc = $cmp$$cmpcode; 7393 __ isel($dst$$Register, $crx$$CondRegister, 7394 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7395 %} 7396 ins_pipe(pipe_class_default); 7397 %} 7398 7399 // Conditional move for RegN. Only cmov(reg, reg). 7400 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7401 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7402 predicate(!VM_Version::has_isel()); 7403 ins_cost(DEFAULT_COST+BRANCH_COST); 7404 7405 ins_variable_size_depending_on_alignment(true); 7406 7407 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7408 // Worst case is branch + move + stop, no stop without scheduler. 7409 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7410 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7411 ins_pipe(pipe_class_default); 7412 %} 7413 7414 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{ 7415 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7416 ins_cost(DEFAULT_COST+BRANCH_COST); 7417 7418 ins_variable_size_depending_on_alignment(true); 7419 7420 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7421 // Worst case is branch + move + stop, no stop without scheduler. 7422 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7423 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7424 ins_pipe(pipe_class_default); 7425 %} 7426 7427 // Cmove using isel. 7428 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{ 7429 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7430 predicate(VM_Version::has_isel()); 7431 ins_cost(DEFAULT_COST); 7432 7433 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7434 size(4); 7435 ins_encode %{ 7436 // This is a Power7 instruction for which no machine description 7437 // exists. Anyways, the scheduler should be off on Power7. 7438 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7439 int cc = $cmp$$cmpcode; 7440 __ isel($dst$$Register, $crx$$CondRegister, 7441 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7442 %} 7443 ins_pipe(pipe_class_default); 7444 %} 7445 7446 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{ 7447 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7448 predicate(!VM_Version::has_isel()); 7449 ins_cost(DEFAULT_COST+BRANCH_COST); 7450 7451 ins_variable_size_depending_on_alignment(true); 7452 7453 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7454 // Worst case is branch + move + stop, no stop without scheduler. 7455 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7456 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7457 ins_pipe(pipe_class_default); 7458 %} 7459 7460 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{ 7461 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7462 ins_cost(DEFAULT_COST+BRANCH_COST); 7463 7464 ins_variable_size_depending_on_alignment(true); 7465 7466 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7467 // Worst case is branch + move + stop, no stop without scheduler. 7468 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7469 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7470 ins_pipe(pipe_class_default); 7471 %} 7472 7473 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{ 7474 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7475 ins_cost(DEFAULT_COST+BRANCH_COST); 7476 7477 ins_variable_size_depending_on_alignment(true); 7478 7479 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7480 // Worst case is branch + move + stop, no stop without scheduler. 7481 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7482 ins_encode %{ 7483 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7484 Label done; 7485 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7486 // Branch if not (cmp crx). 7487 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7488 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7489 // TODO PPC port __ endgroup_if_needed(_size == 12); 7490 __ bind(done); 7491 %} 7492 ins_pipe(pipe_class_default); 7493 %} 7494 7495 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{ 7496 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7497 ins_cost(DEFAULT_COST+BRANCH_COST); 7498 7499 ins_variable_size_depending_on_alignment(true); 7500 7501 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7502 // Worst case is branch + move + stop, no stop without scheduler. 7503 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7504 ins_encode %{ 7505 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7506 Label done; 7507 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7508 // Branch if not (cmp crx). 7509 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7510 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7511 // TODO PPC port __ endgroup_if_needed(_size == 12); 7512 __ bind(done); 7513 %} 7514 ins_pipe(pipe_class_default); 7515 %} 7516 7517 //----------Conditional_store-------------------------------------------------- 7518 // Conditional-store of the updated heap-top. 7519 // Used during allocation of the shared heap. 7520 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7521 7522 // As compareAndSwapL, but return flag register instead of boolean value in 7523 // int register. 7524 // Used by sun/misc/AtomicLongCSImpl.java. 7525 // Mem_ptr must be a memory operand, else this node does not get 7526 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7527 // can be rematerialized which leads to errors. 7528 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{ 7529 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7530 effect(TEMP cr0); 7531 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7532 ins_encode %{ 7533 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7534 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7535 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(), 7536 noreg, NULL, true); 7537 %} 7538 ins_pipe(pipe_class_default); 7539 %} 7540 7541 // As compareAndSwapP, but return flag register instead of boolean value in 7542 // int register. 7543 // This instruction is matched if UseTLAB is off. 7544 // Mem_ptr must be a memory operand, else this node does not get 7545 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7546 // can be rematerialized which leads to errors. 7547 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7548 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal))); 7549 ins_cost(2*MEMORY_REF_COST); 7550 7551 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7552 ins_encode %{ 7553 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_); 7554 __ stdcx_($newVal$$Register, $mem_ptr$$Register); 7555 %} 7556 ins_pipe(pipe_class_memory); 7557 %} 7558 7559 // Implement LoadPLocked. Must be ordered against changes of the memory location 7560 // by storePConditional. 7561 // Don't know whether this is ever used. 7562 instruct loadPLocked(iRegPdst dst, memory mem) %{ 7563 match(Set dst (LoadPLocked mem)); 7564 ins_cost(2*MEMORY_REF_COST); 7565 7566 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %} 7567 size(4); 7568 ins_encode %{ 7569 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx); 7570 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update()); 7571 %} 7572 ins_pipe(pipe_class_memory); 7573 %} 7574 7575 //----------Compare-And-Swap--------------------------------------------------- 7576 7577 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7578 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7579 // matched. 7580 7581 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{ 7582 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7583 effect(TEMP cr0); 7584 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7585 // Variable size: instruction count smaller if regs are disjoint. 7586 ins_encode %{ 7587 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7588 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7589 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7590 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7591 $res$$Register, true); 7592 %} 7593 ins_pipe(pipe_class_default); 7594 %} 7595 7596 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{ 7597 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7598 effect(TEMP cr0); 7599 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7600 // Variable size: instruction count smaller if regs are disjoint. 7601 ins_encode %{ 7602 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7603 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7604 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7605 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7606 $res$$Register, true); 7607 %} 7608 ins_pipe(pipe_class_default); 7609 %} 7610 7611 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 7612 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7613 effect(TEMP cr0); 7614 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7615 // Variable size: instruction count smaller if regs are disjoint. 7616 ins_encode %{ 7617 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7618 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7619 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7620 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7621 $res$$Register, NULL, true); 7622 %} 7623 ins_pipe(pipe_class_default); 7624 %} 7625 7626 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{ 7627 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7628 effect(TEMP cr0); 7629 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7630 // Variable size: instruction count smaller if regs are disjoint. 7631 ins_encode %{ 7632 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7633 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7634 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7635 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7636 $res$$Register, NULL, true); 7637 %} 7638 ins_pipe(pipe_class_default); 7639 %} 7640 7641 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7642 match(Set res (GetAndAddI mem_ptr src)); 7643 effect(TEMP cr0); 7644 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7645 // Variable size: instruction count smaller if regs are disjoint. 7646 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7647 ins_pipe(pipe_class_default); 7648 %} 7649 7650 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7651 match(Set res (GetAndAddL mem_ptr src)); 7652 effect(TEMP cr0); 7653 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7654 // Variable size: instruction count smaller if regs are disjoint. 7655 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7656 ins_pipe(pipe_class_default); 7657 %} 7658 7659 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7660 match(Set res (GetAndSetI mem_ptr src)); 7661 effect(TEMP cr0); 7662 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7663 // Variable size: instruction count smaller if regs are disjoint. 7664 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7665 ins_pipe(pipe_class_default); 7666 %} 7667 7668 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7669 match(Set res (GetAndSetL mem_ptr src)); 7670 effect(TEMP cr0); 7671 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7672 // Variable size: instruction count smaller if regs are disjoint. 7673 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7674 ins_pipe(pipe_class_default); 7675 %} 7676 7677 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{ 7678 match(Set res (GetAndSetP mem_ptr src)); 7679 effect(TEMP cr0); 7680 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7681 // Variable size: instruction count smaller if regs are disjoint. 7682 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7683 ins_pipe(pipe_class_default); 7684 %} 7685 7686 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{ 7687 match(Set res (GetAndSetN mem_ptr src)); 7688 effect(TEMP cr0); 7689 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7690 // Variable size: instruction count smaller if regs are disjoint. 7691 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7692 ins_pipe(pipe_class_default); 7693 %} 7694 7695 //----------Arithmetic Instructions-------------------------------------------- 7696 // Addition Instructions 7697 7698 // Register Addition 7699 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7700 match(Set dst (AddI src1 src2)); 7701 format %{ "ADD $dst, $src1, $src2" %} 7702 size(4); 7703 ins_encode %{ 7704 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7705 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7706 %} 7707 ins_pipe(pipe_class_default); 7708 %} 7709 7710 // Expand does not work with above instruct. (??) 7711 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7712 // no match-rule 7713 effect(DEF dst, USE src1, USE src2); 7714 format %{ "ADD $dst, $src1, $src2" %} 7715 size(4); 7716 ins_encode %{ 7717 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7718 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7719 %} 7720 ins_pipe(pipe_class_default); 7721 %} 7722 7723 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7724 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7725 ins_cost(DEFAULT_COST*3); 7726 7727 expand %{ 7728 // FIXME: we should do this in the ideal world. 7729 iRegIdst tmp1; 7730 iRegIdst tmp2; 7731 addI_reg_reg(tmp1, src1, src2); 7732 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7733 addI_reg_reg(dst, tmp1, tmp2); 7734 %} 7735 %} 7736 7737 // Immediate Addition 7738 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7739 match(Set dst (AddI src1 src2)); 7740 format %{ "ADDI $dst, $src1, $src2" %} 7741 size(4); 7742 ins_encode %{ 7743 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7744 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7745 %} 7746 ins_pipe(pipe_class_default); 7747 %} 7748 7749 // Immediate Addition with 16-bit shifted operand 7750 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7751 match(Set dst (AddI src1 src2)); 7752 format %{ "ADDIS $dst, $src1, $src2" %} 7753 size(4); 7754 ins_encode %{ 7755 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7756 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7757 %} 7758 ins_pipe(pipe_class_default); 7759 %} 7760 7761 // Long Addition 7762 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7763 match(Set dst (AddL src1 src2)); 7764 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7765 size(4); 7766 ins_encode %{ 7767 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7768 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7769 %} 7770 ins_pipe(pipe_class_default); 7771 %} 7772 7773 // Expand does not work with above instruct. (??) 7774 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7775 // no match-rule 7776 effect(DEF dst, USE src1, USE src2); 7777 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7778 size(4); 7779 ins_encode %{ 7780 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7781 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7782 %} 7783 ins_pipe(pipe_class_default); 7784 %} 7785 7786 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7787 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7788 ins_cost(DEFAULT_COST*3); 7789 7790 expand %{ 7791 // FIXME: we should do this in the ideal world. 7792 iRegLdst tmp1; 7793 iRegLdst tmp2; 7794 addL_reg_reg(tmp1, src1, src2); 7795 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7796 addL_reg_reg(dst, tmp1, tmp2); 7797 %} 7798 %} 7799 7800 // AddL + ConvL2I. 7801 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7802 match(Set dst (ConvL2I (AddL src1 src2))); 7803 7804 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7805 size(4); 7806 ins_encode %{ 7807 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7808 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7809 %} 7810 ins_pipe(pipe_class_default); 7811 %} 7812 7813 // No constant pool entries required. 7814 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7815 match(Set dst (AddL src1 src2)); 7816 7817 format %{ "ADDI $dst, $src1, $src2" %} 7818 size(4); 7819 ins_encode %{ 7820 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7821 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7822 %} 7823 ins_pipe(pipe_class_default); 7824 %} 7825 7826 // Long Immediate Addition with 16-bit shifted operand. 7827 // No constant pool entries required. 7828 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7829 match(Set dst (AddL src1 src2)); 7830 7831 format %{ "ADDIS $dst, $src1, $src2" %} 7832 size(4); 7833 ins_encode %{ 7834 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7835 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7836 %} 7837 ins_pipe(pipe_class_default); 7838 %} 7839 7840 // Pointer Register Addition 7841 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7842 match(Set dst (AddP src1 src2)); 7843 format %{ "ADD $dst, $src1, $src2" %} 7844 size(4); 7845 ins_encode %{ 7846 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7847 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7848 %} 7849 ins_pipe(pipe_class_default); 7850 %} 7851 7852 // Pointer Immediate Addition 7853 // No constant pool entries required. 7854 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7855 match(Set dst (AddP src1 src2)); 7856 7857 format %{ "ADDI $dst, $src1, $src2" %} 7858 size(4); 7859 ins_encode %{ 7860 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7861 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7862 %} 7863 ins_pipe(pipe_class_default); 7864 %} 7865 7866 // Pointer Immediate Addition with 16-bit shifted operand. 7867 // No constant pool entries required. 7868 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7869 match(Set dst (AddP src1 src2)); 7870 7871 format %{ "ADDIS $dst, $src1, $src2" %} 7872 size(4); 7873 ins_encode %{ 7874 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7875 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7876 %} 7877 ins_pipe(pipe_class_default); 7878 %} 7879 7880 //--------------------- 7881 // Subtraction Instructions 7882 7883 // Register Subtraction 7884 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7885 match(Set dst (SubI src1 src2)); 7886 format %{ "SUBF $dst, $src2, $src1" %} 7887 size(4); 7888 ins_encode %{ 7889 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7890 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7891 %} 7892 ins_pipe(pipe_class_default); 7893 %} 7894 7895 // Immediate Subtraction 7896 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 7897 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16. 7898 7899 // SubI from constant (using subfic). 7900 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7901 match(Set dst (SubI src1 src2)); 7902 format %{ "SUBI $dst, $src1, $src2" %} 7903 7904 size(4); 7905 ins_encode %{ 7906 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7907 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7908 %} 7909 ins_pipe(pipe_class_default); 7910 %} 7911 7912 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7913 // positive integers and 0xF...F for negative ones. 7914 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7915 // no match-rule, false predicate 7916 effect(DEF dst, USE src); 7917 predicate(false); 7918 7919 format %{ "SRAWI $dst, $src, #31" %} 7920 size(4); 7921 ins_encode %{ 7922 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7923 __ srawi($dst$$Register, $src$$Register, 0x1f); 7924 %} 7925 ins_pipe(pipe_class_default); 7926 %} 7927 7928 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7929 match(Set dst (AbsI src)); 7930 ins_cost(DEFAULT_COST*3); 7931 7932 expand %{ 7933 iRegIdst tmp1; 7934 iRegIdst tmp2; 7935 signmask32I_regI(tmp1, src); 7936 xorI_reg_reg(tmp2, tmp1, src); 7937 subI_reg_reg(dst, tmp2, tmp1); 7938 %} 7939 %} 7940 7941 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 7942 match(Set dst (SubI zero src2)); 7943 format %{ "NEG $dst, $src2" %} 7944 size(4); 7945 ins_encode %{ 7946 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7947 __ neg($dst$$Register, $src2$$Register); 7948 %} 7949 ins_pipe(pipe_class_default); 7950 %} 7951 7952 // Long subtraction 7953 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7954 match(Set dst (SubL src1 src2)); 7955 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 7956 size(4); 7957 ins_encode %{ 7958 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7959 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7960 %} 7961 ins_pipe(pipe_class_default); 7962 %} 7963 7964 // SubL + convL2I. 7965 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7966 match(Set dst (ConvL2I (SubL src1 src2))); 7967 7968 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 7969 size(4); 7970 ins_encode %{ 7971 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7972 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7973 %} 7974 ins_pipe(pipe_class_default); 7975 %} 7976 7977 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7978 // positive longs and 0xF...F for negative ones. 7979 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7980 // no match-rule, false predicate 7981 effect(DEF dst, USE src); 7982 predicate(false); 7983 7984 format %{ "SRADI $dst, $src, #63" %} 7985 size(4); 7986 ins_encode %{ 7987 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7988 __ sradi($dst$$Register, $src$$Register, 0x3f); 7989 %} 7990 ins_pipe(pipe_class_default); 7991 %} 7992 7993 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7994 // positive longs and 0xF...F for negative ones. 7995 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7996 // no match-rule, false predicate 7997 effect(DEF dst, USE src); 7998 predicate(false); 7999 8000 format %{ "SRADI $dst, $src, #63" %} 8001 size(4); 8002 ins_encode %{ 8003 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8004 __ sradi($dst$$Register, $src$$Register, 0x3f); 8005 %} 8006 ins_pipe(pipe_class_default); 8007 %} 8008 8009 // Long negation 8010 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 8011 match(Set dst (SubL zero src2)); 8012 format %{ "NEG $dst, $src2 \t// long" %} 8013 size(4); 8014 ins_encode %{ 8015 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8016 __ neg($dst$$Register, $src2$$Register); 8017 %} 8018 ins_pipe(pipe_class_default); 8019 %} 8020 8021 // NegL + ConvL2I. 8022 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 8023 match(Set dst (ConvL2I (SubL zero src2))); 8024 8025 format %{ "NEG $dst, $src2 \t// long + l2i" %} 8026 size(4); 8027 ins_encode %{ 8028 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8029 __ neg($dst$$Register, $src2$$Register); 8030 %} 8031 ins_pipe(pipe_class_default); 8032 %} 8033 8034 // Multiplication Instructions 8035 // Integer Multiplication 8036 8037 // Register Multiplication 8038 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8039 match(Set dst (MulI src1 src2)); 8040 ins_cost(DEFAULT_COST); 8041 8042 format %{ "MULLW $dst, $src1, $src2" %} 8043 size(4); 8044 ins_encode %{ 8045 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8046 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8047 %} 8048 ins_pipe(pipe_class_default); 8049 %} 8050 8051 // Immediate Multiplication 8052 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8053 match(Set dst (MulI src1 src2)); 8054 ins_cost(DEFAULT_COST); 8055 8056 format %{ "MULLI $dst, $src1, $src2" %} 8057 size(4); 8058 ins_encode %{ 8059 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8060 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8061 %} 8062 ins_pipe(pipe_class_default); 8063 %} 8064 8065 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8066 match(Set dst (MulL src1 src2)); 8067 ins_cost(DEFAULT_COST); 8068 8069 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8070 size(4); 8071 ins_encode %{ 8072 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8073 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8074 %} 8075 ins_pipe(pipe_class_default); 8076 %} 8077 8078 // Multiply high for optimized long division by constant. 8079 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8080 match(Set dst (MulHiL src1 src2)); 8081 ins_cost(DEFAULT_COST); 8082 8083 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8084 size(4); 8085 ins_encode %{ 8086 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8087 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8088 %} 8089 ins_pipe(pipe_class_default); 8090 %} 8091 8092 // Immediate Multiplication 8093 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8094 match(Set dst (MulL src1 src2)); 8095 ins_cost(DEFAULT_COST); 8096 8097 format %{ "MULLI $dst, $src1, $src2" %} 8098 size(4); 8099 ins_encode %{ 8100 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8101 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8102 %} 8103 ins_pipe(pipe_class_default); 8104 %} 8105 8106 // Integer Division with Immediate -1: Negate. 8107 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8108 match(Set dst (DivI src1 src2)); 8109 ins_cost(DEFAULT_COST); 8110 8111 format %{ "NEG $dst, $src1 \t// /-1" %} 8112 size(4); 8113 ins_encode %{ 8114 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8115 __ neg($dst$$Register, $src1$$Register); 8116 %} 8117 ins_pipe(pipe_class_default); 8118 %} 8119 8120 // Integer Division with constant, but not -1. 8121 // We should be able to improve this by checking the type of src2. 8122 // It might well be that src2 is known to be positive. 8123 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8124 match(Set dst (DivI src1 src2)); 8125 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8126 ins_cost(2*DEFAULT_COST); 8127 8128 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8129 size(4); 8130 ins_encode %{ 8131 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8132 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8133 %} 8134 ins_pipe(pipe_class_default); 8135 %} 8136 8137 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{ 8138 effect(USE_DEF dst, USE src1, USE crx); 8139 predicate(false); 8140 8141 ins_variable_size_depending_on_alignment(true); 8142 8143 format %{ "CMOVE $dst, neg($src1), $crx" %} 8144 // Worst case is branch + move + stop, no stop without scheduler. 8145 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8146 ins_encode %{ 8147 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8148 Label done; 8149 __ bne($crx$$CondRegister, done); 8150 __ neg($dst$$Register, $src1$$Register); 8151 // TODO PPC port __ endgroup_if_needed(_size == 12); 8152 __ bind(done); 8153 %} 8154 ins_pipe(pipe_class_default); 8155 %} 8156 8157 // Integer Division with Registers not containing constants. 8158 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8159 match(Set dst (DivI src1 src2)); 8160 ins_cost(10*DEFAULT_COST); 8161 8162 expand %{ 8163 immI16 imm %{ (int)-1 %} 8164 flagsReg tmp1; 8165 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8166 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8167 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8168 %} 8169 %} 8170 8171 // Long Division with Immediate -1: Negate. 8172 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8173 match(Set dst (DivL src1 src2)); 8174 ins_cost(DEFAULT_COST); 8175 8176 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8177 size(4); 8178 ins_encode %{ 8179 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8180 __ neg($dst$$Register, $src1$$Register); 8181 %} 8182 ins_pipe(pipe_class_default); 8183 %} 8184 8185 // Long Division with constant, but not -1. 8186 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8187 match(Set dst (DivL src1 src2)); 8188 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8189 ins_cost(2*DEFAULT_COST); 8190 8191 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8192 size(4); 8193 ins_encode %{ 8194 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8195 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8196 %} 8197 ins_pipe(pipe_class_default); 8198 %} 8199 8200 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{ 8201 effect(USE_DEF dst, USE src1, USE crx); 8202 predicate(false); 8203 8204 ins_variable_size_depending_on_alignment(true); 8205 8206 format %{ "CMOVE $dst, neg($src1), $crx" %} 8207 // Worst case is branch + move + stop, no stop without scheduler. 8208 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8209 ins_encode %{ 8210 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8211 Label done; 8212 __ bne($crx$$CondRegister, done); 8213 __ neg($dst$$Register, $src1$$Register); 8214 // TODO PPC port __ endgroup_if_needed(_size == 12); 8215 __ bind(done); 8216 %} 8217 ins_pipe(pipe_class_default); 8218 %} 8219 8220 // Long Division with Registers not containing constants. 8221 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8222 match(Set dst (DivL src1 src2)); 8223 ins_cost(10*DEFAULT_COST); 8224 8225 expand %{ 8226 immL16 imm %{ (int)-1 %} 8227 flagsReg tmp1; 8228 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8229 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8230 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8231 %} 8232 %} 8233 8234 // Integer Remainder with registers. 8235 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8236 match(Set dst (ModI src1 src2)); 8237 ins_cost(10*DEFAULT_COST); 8238 8239 expand %{ 8240 immI16 imm %{ (int)-1 %} 8241 flagsReg tmp1; 8242 iRegIdst tmp2; 8243 iRegIdst tmp3; 8244 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8245 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8246 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8247 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8248 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8249 %} 8250 %} 8251 8252 // Long Remainder with registers 8253 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8254 match(Set dst (ModL src1 src2)); 8255 ins_cost(10*DEFAULT_COST); 8256 8257 expand %{ 8258 immL16 imm %{ (int)-1 %} 8259 flagsReg tmp1; 8260 iRegLdst tmp2; 8261 iRegLdst tmp3; 8262 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8263 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8264 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8265 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8266 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8267 %} 8268 %} 8269 8270 // Integer Shift Instructions 8271 8272 // Register Shift Left 8273 8274 // Clear all but the lowest #mask bits. 8275 // Used to normalize shift amounts in registers. 8276 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8277 // no match-rule, false predicate 8278 effect(DEF dst, USE src, USE mask); 8279 predicate(false); 8280 8281 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8282 size(4); 8283 ins_encode %{ 8284 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8285 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8286 %} 8287 ins_pipe(pipe_class_default); 8288 %} 8289 8290 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8291 // no match-rule, false predicate 8292 effect(DEF dst, USE src1, USE src2); 8293 predicate(false); 8294 8295 format %{ "SLW $dst, $src1, $src2" %} 8296 size(4); 8297 ins_encode %{ 8298 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8299 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8300 %} 8301 ins_pipe(pipe_class_default); 8302 %} 8303 8304 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8305 match(Set dst (LShiftI src1 src2)); 8306 ins_cost(DEFAULT_COST*2); 8307 expand %{ 8308 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8309 iRegIdst tmpI; 8310 maskI_reg_imm(tmpI, src2, mask); 8311 lShiftI_reg_reg(dst, src1, tmpI); 8312 %} 8313 %} 8314 8315 // Register Shift Left Immediate 8316 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8317 match(Set dst (LShiftI src1 src2)); 8318 8319 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8320 size(4); 8321 ins_encode %{ 8322 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8323 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8324 %} 8325 ins_pipe(pipe_class_default); 8326 %} 8327 8328 // AndI with negpow2-constant + LShiftI 8329 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8330 match(Set dst (LShiftI (AndI src1 src2) src3)); 8331 predicate(UseRotateAndMaskInstructionsPPC64); 8332 8333 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8334 size(4); 8335 ins_encode %{ 8336 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8337 long src2 = $src2$$constant; 8338 long src3 = $src3$$constant; 8339 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8340 if (maskbits >= 32) { 8341 __ li($dst$$Register, 0); // addi 8342 } else { 8343 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8344 } 8345 %} 8346 ins_pipe(pipe_class_default); 8347 %} 8348 8349 // RShiftI + AndI with negpow2-constant + LShiftI 8350 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8351 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8352 predicate(UseRotateAndMaskInstructionsPPC64); 8353 8354 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8355 size(4); 8356 ins_encode %{ 8357 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8358 long src2 = $src2$$constant; 8359 long src3 = $src3$$constant; 8360 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8361 if (maskbits >= 32) { 8362 __ li($dst$$Register, 0); // addi 8363 } else { 8364 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8365 } 8366 %} 8367 ins_pipe(pipe_class_default); 8368 %} 8369 8370 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8371 // no match-rule, false predicate 8372 effect(DEF dst, USE src1, USE src2); 8373 predicate(false); 8374 8375 format %{ "SLD $dst, $src1, $src2" %} 8376 size(4); 8377 ins_encode %{ 8378 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8379 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8380 %} 8381 ins_pipe(pipe_class_default); 8382 %} 8383 8384 // Register Shift Left 8385 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8386 match(Set dst (LShiftL src1 src2)); 8387 ins_cost(DEFAULT_COST*2); 8388 expand %{ 8389 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8390 iRegIdst tmpI; 8391 maskI_reg_imm(tmpI, src2, mask); 8392 lShiftL_regL_regI(dst, src1, tmpI); 8393 %} 8394 %} 8395 8396 // Register Shift Left Immediate 8397 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8398 match(Set dst (LShiftL src1 src2)); 8399 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8400 size(4); 8401 ins_encode %{ 8402 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8403 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8404 %} 8405 ins_pipe(pipe_class_default); 8406 %} 8407 8408 // If we shift more than 32 bits, we need not convert I2L. 8409 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8410 match(Set dst (LShiftL (ConvI2L src1) src2)); 8411 ins_cost(DEFAULT_COST); 8412 8413 size(4); 8414 format %{ "SLDI $dst, i2l($src1), $src2" %} 8415 ins_encode %{ 8416 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8417 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8418 %} 8419 ins_pipe(pipe_class_default); 8420 %} 8421 8422 // Shift a postivie int to the left. 8423 // Clrlsldi clears the upper 32 bits and shifts. 8424 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8425 match(Set dst (LShiftL (ConvI2L src1) src2)); 8426 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8427 8428 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8429 size(4); 8430 ins_encode %{ 8431 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8432 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8433 %} 8434 ins_pipe(pipe_class_default); 8435 %} 8436 8437 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8438 // no match-rule, false predicate 8439 effect(DEF dst, USE src1, USE src2); 8440 predicate(false); 8441 8442 format %{ "SRAW $dst, $src1, $src2" %} 8443 size(4); 8444 ins_encode %{ 8445 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8446 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8447 %} 8448 ins_pipe(pipe_class_default); 8449 %} 8450 8451 // Register Arithmetic Shift Right 8452 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8453 match(Set dst (RShiftI src1 src2)); 8454 ins_cost(DEFAULT_COST*2); 8455 expand %{ 8456 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8457 iRegIdst tmpI; 8458 maskI_reg_imm(tmpI, src2, mask); 8459 arShiftI_reg_reg(dst, src1, tmpI); 8460 %} 8461 %} 8462 8463 // Register Arithmetic Shift Right Immediate 8464 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8465 match(Set dst (RShiftI src1 src2)); 8466 8467 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8468 size(4); 8469 ins_encode %{ 8470 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8471 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8472 %} 8473 ins_pipe(pipe_class_default); 8474 %} 8475 8476 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8477 // no match-rule, false predicate 8478 effect(DEF dst, USE src1, USE src2); 8479 predicate(false); 8480 8481 format %{ "SRAD $dst, $src1, $src2" %} 8482 size(4); 8483 ins_encode %{ 8484 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8485 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8486 %} 8487 ins_pipe(pipe_class_default); 8488 %} 8489 8490 // Register Shift Right Arithmetic Long 8491 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8492 match(Set dst (RShiftL src1 src2)); 8493 ins_cost(DEFAULT_COST*2); 8494 8495 expand %{ 8496 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8497 iRegIdst tmpI; 8498 maskI_reg_imm(tmpI, src2, mask); 8499 arShiftL_regL_regI(dst, src1, tmpI); 8500 %} 8501 %} 8502 8503 // Register Shift Right Immediate 8504 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8505 match(Set dst (RShiftL src1 src2)); 8506 8507 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8508 size(4); 8509 ins_encode %{ 8510 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8511 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8512 %} 8513 ins_pipe(pipe_class_default); 8514 %} 8515 8516 // RShiftL + ConvL2I 8517 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8518 match(Set dst (ConvL2I (RShiftL src1 src2))); 8519 8520 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8521 size(4); 8522 ins_encode %{ 8523 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8524 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8525 %} 8526 ins_pipe(pipe_class_default); 8527 %} 8528 8529 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8530 // no match-rule, false predicate 8531 effect(DEF dst, USE src1, USE src2); 8532 predicate(false); 8533 8534 format %{ "SRW $dst, $src1, $src2" %} 8535 size(4); 8536 ins_encode %{ 8537 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8538 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8539 %} 8540 ins_pipe(pipe_class_default); 8541 %} 8542 8543 // Register Shift Right 8544 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8545 match(Set dst (URShiftI src1 src2)); 8546 ins_cost(DEFAULT_COST*2); 8547 8548 expand %{ 8549 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8550 iRegIdst tmpI; 8551 maskI_reg_imm(tmpI, src2, mask); 8552 urShiftI_reg_reg(dst, src1, tmpI); 8553 %} 8554 %} 8555 8556 // Register Shift Right Immediate 8557 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8558 match(Set dst (URShiftI src1 src2)); 8559 8560 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8561 size(4); 8562 ins_encode %{ 8563 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8564 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8565 %} 8566 ins_pipe(pipe_class_default); 8567 %} 8568 8569 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8570 // no match-rule, false predicate 8571 effect(DEF dst, USE src1, USE src2); 8572 predicate(false); 8573 8574 format %{ "SRD $dst, $src1, $src2" %} 8575 size(4); 8576 ins_encode %{ 8577 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8578 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8579 %} 8580 ins_pipe(pipe_class_default); 8581 %} 8582 8583 // Register Shift Right 8584 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8585 match(Set dst (URShiftL src1 src2)); 8586 ins_cost(DEFAULT_COST*2); 8587 8588 expand %{ 8589 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8590 iRegIdst tmpI; 8591 maskI_reg_imm(tmpI, src2, mask); 8592 urShiftL_regL_regI(dst, src1, tmpI); 8593 %} 8594 %} 8595 8596 // Register Shift Right Immediate 8597 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8598 match(Set dst (URShiftL src1 src2)); 8599 8600 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8601 size(4); 8602 ins_encode %{ 8603 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8604 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8605 %} 8606 ins_pipe(pipe_class_default); 8607 %} 8608 8609 // URShiftL + ConvL2I. 8610 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8611 match(Set dst (ConvL2I (URShiftL src1 src2))); 8612 8613 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8614 size(4); 8615 ins_encode %{ 8616 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8617 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8618 %} 8619 ins_pipe(pipe_class_default); 8620 %} 8621 8622 // Register Shift Right Immediate with a CastP2X 8623 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8624 match(Set dst (URShiftL (CastP2X src1) src2)); 8625 8626 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8627 size(4); 8628 ins_encode %{ 8629 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8630 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8631 %} 8632 ins_pipe(pipe_class_default); 8633 %} 8634 8635 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8636 match(Set dst (ConvL2I (ConvI2L src))); 8637 8638 format %{ "EXTSW $dst, $src \t// int->int" %} 8639 size(4); 8640 ins_encode %{ 8641 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8642 __ extsw($dst$$Register, $src$$Register); 8643 %} 8644 ins_pipe(pipe_class_default); 8645 %} 8646 8647 //----------Rotate Instructions------------------------------------------------ 8648 8649 // Rotate Left by 8-bit immediate 8650 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8651 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8652 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8653 8654 format %{ "ROTLWI $dst, $src, $lshift" %} 8655 size(4); 8656 ins_encode %{ 8657 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8658 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8659 %} 8660 ins_pipe(pipe_class_default); 8661 %} 8662 8663 // Rotate Right by 8-bit immediate 8664 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8665 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8666 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8667 8668 format %{ "ROTRWI $dst, $rshift" %} 8669 size(4); 8670 ins_encode %{ 8671 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8672 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8673 %} 8674 ins_pipe(pipe_class_default); 8675 %} 8676 8677 //----------Floating Point Arithmetic Instructions----------------------------- 8678 8679 // Add float single precision 8680 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8681 match(Set dst (AddF src1 src2)); 8682 8683 format %{ "FADDS $dst, $src1, $src2" %} 8684 size(4); 8685 ins_encode %{ 8686 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8687 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8688 %} 8689 ins_pipe(pipe_class_default); 8690 %} 8691 8692 // Add float double precision 8693 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8694 match(Set dst (AddD src1 src2)); 8695 8696 format %{ "FADD $dst, $src1, $src2" %} 8697 size(4); 8698 ins_encode %{ 8699 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8700 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8701 %} 8702 ins_pipe(pipe_class_default); 8703 %} 8704 8705 // Sub float single precision 8706 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8707 match(Set dst (SubF src1 src2)); 8708 8709 format %{ "FSUBS $dst, $src1, $src2" %} 8710 size(4); 8711 ins_encode %{ 8712 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8713 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8714 %} 8715 ins_pipe(pipe_class_default); 8716 %} 8717 8718 // Sub float double precision 8719 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8720 match(Set dst (SubD src1 src2)); 8721 format %{ "FSUB $dst, $src1, $src2" %} 8722 size(4); 8723 ins_encode %{ 8724 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8725 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8726 %} 8727 ins_pipe(pipe_class_default); 8728 %} 8729 8730 // Mul float single precision 8731 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8732 match(Set dst (MulF src1 src2)); 8733 format %{ "FMULS $dst, $src1, $src2" %} 8734 size(4); 8735 ins_encode %{ 8736 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8737 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8738 %} 8739 ins_pipe(pipe_class_default); 8740 %} 8741 8742 // Mul float double precision 8743 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8744 match(Set dst (MulD src1 src2)); 8745 format %{ "FMUL $dst, $src1, $src2" %} 8746 size(4); 8747 ins_encode %{ 8748 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8749 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8750 %} 8751 ins_pipe(pipe_class_default); 8752 %} 8753 8754 // Div float single precision 8755 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8756 match(Set dst (DivF src1 src2)); 8757 format %{ "FDIVS $dst, $src1, $src2" %} 8758 size(4); 8759 ins_encode %{ 8760 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8761 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8762 %} 8763 ins_pipe(pipe_class_default); 8764 %} 8765 8766 // Div float double precision 8767 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8768 match(Set dst (DivD src1 src2)); 8769 format %{ "FDIV $dst, $src1, $src2" %} 8770 size(4); 8771 ins_encode %{ 8772 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8773 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8774 %} 8775 ins_pipe(pipe_class_default); 8776 %} 8777 8778 // Absolute float single precision 8779 instruct absF_reg(regF dst, regF src) %{ 8780 match(Set dst (AbsF src)); 8781 format %{ "FABS $dst, $src \t// float" %} 8782 size(4); 8783 ins_encode %{ 8784 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8785 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8786 %} 8787 ins_pipe(pipe_class_default); 8788 %} 8789 8790 // Absolute float double precision 8791 instruct absD_reg(regD dst, regD src) %{ 8792 match(Set dst (AbsD src)); 8793 format %{ "FABS $dst, $src \t// double" %} 8794 size(4); 8795 ins_encode %{ 8796 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8797 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8798 %} 8799 ins_pipe(pipe_class_default); 8800 %} 8801 8802 instruct negF_reg(regF dst, regF src) %{ 8803 match(Set dst (NegF src)); 8804 format %{ "FNEG $dst, $src \t// float" %} 8805 size(4); 8806 ins_encode %{ 8807 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8808 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8809 %} 8810 ins_pipe(pipe_class_default); 8811 %} 8812 8813 instruct negD_reg(regD dst, regD src) %{ 8814 match(Set dst (NegD src)); 8815 format %{ "FNEG $dst, $src \t// double" %} 8816 size(4); 8817 ins_encode %{ 8818 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8819 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8820 %} 8821 ins_pipe(pipe_class_default); 8822 %} 8823 8824 // AbsF + NegF. 8825 instruct negF_absF_reg(regF dst, regF src) %{ 8826 match(Set dst (NegF (AbsF src))); 8827 format %{ "FNABS $dst, $src \t// float" %} 8828 size(4); 8829 ins_encode %{ 8830 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8831 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8832 %} 8833 ins_pipe(pipe_class_default); 8834 %} 8835 8836 // AbsD + NegD. 8837 instruct negD_absD_reg(regD dst, regD src) %{ 8838 match(Set dst (NegD (AbsD src))); 8839 format %{ "FNABS $dst, $src \t// double" %} 8840 size(4); 8841 ins_encode %{ 8842 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8843 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8844 %} 8845 ins_pipe(pipe_class_default); 8846 %} 8847 8848 // VM_Version::has_fsqrt() decides if this node will be used. 8849 // Sqrt float double precision 8850 instruct sqrtD_reg(regD dst, regD src) %{ 8851 match(Set dst (SqrtD src)); 8852 format %{ "FSQRT $dst, $src" %} 8853 size(4); 8854 ins_encode %{ 8855 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8856 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8857 %} 8858 ins_pipe(pipe_class_default); 8859 %} 8860 8861 // Single-precision sqrt. 8862 instruct sqrtF_reg(regF dst, regF src) %{ 8863 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8864 predicate(VM_Version::has_fsqrts()); 8865 ins_cost(DEFAULT_COST); 8866 8867 format %{ "FSQRTS $dst, $src" %} 8868 size(4); 8869 ins_encode %{ 8870 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8871 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8872 %} 8873 ins_pipe(pipe_class_default); 8874 %} 8875 8876 instruct roundDouble_nop(regD dst) %{ 8877 match(Set dst (RoundDouble dst)); 8878 ins_cost(0); 8879 8880 format %{ " -- \t// RoundDouble not needed - empty" %} 8881 size(0); 8882 // PPC results are already "rounded" (i.e., normal-format IEEE). 8883 ins_encode( /*empty*/ ); 8884 ins_pipe(pipe_class_default); 8885 %} 8886 8887 instruct roundFloat_nop(regF dst) %{ 8888 match(Set dst (RoundFloat dst)); 8889 ins_cost(0); 8890 8891 format %{ " -- \t// RoundFloat not needed - empty" %} 8892 size(0); 8893 // PPC results are already "rounded" (i.e., normal-format IEEE). 8894 ins_encode( /*empty*/ ); 8895 ins_pipe(pipe_class_default); 8896 %} 8897 8898 //----------Logical Instructions----------------------------------------------- 8899 8900 // And Instructions 8901 8902 // Register And 8903 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8904 match(Set dst (AndI src1 src2)); 8905 format %{ "AND $dst, $src1, $src2" %} 8906 size(4); 8907 ins_encode %{ 8908 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8909 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8910 %} 8911 ins_pipe(pipe_class_default); 8912 %} 8913 8914 // Immediate And 8915 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8916 match(Set dst (AndI src1 src2)); 8917 effect(KILL cr0); 8918 8919 format %{ "ANDI $dst, $src1, $src2" %} 8920 size(4); 8921 ins_encode %{ 8922 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8923 // FIXME: avoid andi_ ? 8924 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8925 %} 8926 ins_pipe(pipe_class_default); 8927 %} 8928 8929 // Immediate And where the immediate is a negative power of 2. 8930 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 8931 match(Set dst (AndI src1 src2)); 8932 format %{ "ANDWI $dst, $src1, $src2" %} 8933 size(4); 8934 ins_encode %{ 8935 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8936 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 8937 %} 8938 ins_pipe(pipe_class_default); 8939 %} 8940 8941 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 8942 match(Set dst (AndI src1 src2)); 8943 format %{ "ANDWI $dst, $src1, $src2" %} 8944 size(4); 8945 ins_encode %{ 8946 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8947 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8948 %} 8949 ins_pipe(pipe_class_default); 8950 %} 8951 8952 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 8953 match(Set dst (AndI src1 src2)); 8954 predicate(UseRotateAndMaskInstructionsPPC64); 8955 format %{ "ANDWI $dst, $src1, $src2" %} 8956 size(4); 8957 ins_encode %{ 8958 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8959 __ rlwinm($dst$$Register, $src1$$Register, 0, 8960 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 8961 %} 8962 ins_pipe(pipe_class_default); 8963 %} 8964 8965 // Register And Long 8966 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8967 match(Set dst (AndL src1 src2)); 8968 ins_cost(DEFAULT_COST); 8969 8970 format %{ "AND $dst, $src1, $src2 \t// long" %} 8971 size(4); 8972 ins_encode %{ 8973 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8974 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8975 %} 8976 ins_pipe(pipe_class_default); 8977 %} 8978 8979 // Immediate And long 8980 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 8981 match(Set dst (AndL src1 src2)); 8982 effect(KILL cr0); 8983 8984 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 8985 size(4); 8986 ins_encode %{ 8987 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8988 // FIXME: avoid andi_ ? 8989 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8990 %} 8991 ins_pipe(pipe_class_default); 8992 %} 8993 8994 // Immediate And Long where the immediate is a negative power of 2. 8995 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 8996 match(Set dst (AndL src1 src2)); 8997 format %{ "ANDDI $dst, $src1, $src2" %} 8998 size(4); 8999 ins_encode %{ 9000 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 9001 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 9002 %} 9003 ins_pipe(pipe_class_default); 9004 %} 9005 9006 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 9007 match(Set dst (AndL src1 src2)); 9008 format %{ "ANDDI $dst, $src1, $src2" %} 9009 size(4); 9010 ins_encode %{ 9011 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9012 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 9013 %} 9014 ins_pipe(pipe_class_default); 9015 %} 9016 9017 // AndL + ConvL2I. 9018 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 9019 match(Set dst (ConvL2I (AndL src1 src2))); 9020 ins_cost(DEFAULT_COST); 9021 9022 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 9023 size(4); 9024 ins_encode %{ 9025 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9026 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 9027 %} 9028 ins_pipe(pipe_class_default); 9029 %} 9030 9031 // Or Instructions 9032 9033 // Register Or 9034 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9035 match(Set dst (OrI src1 src2)); 9036 format %{ "OR $dst, $src1, $src2" %} 9037 size(4); 9038 ins_encode %{ 9039 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9040 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9041 %} 9042 ins_pipe(pipe_class_default); 9043 %} 9044 9045 // Expand does not work with above instruct. (??) 9046 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9047 // no match-rule 9048 effect(DEF dst, USE src1, USE src2); 9049 format %{ "OR $dst, $src1, $src2" %} 9050 size(4); 9051 ins_encode %{ 9052 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9053 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9054 %} 9055 ins_pipe(pipe_class_default); 9056 %} 9057 9058 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9059 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9060 ins_cost(DEFAULT_COST*3); 9061 9062 expand %{ 9063 // FIXME: we should do this in the ideal world. 9064 iRegIdst tmp1; 9065 iRegIdst tmp2; 9066 orI_reg_reg(tmp1, src1, src2); 9067 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9068 orI_reg_reg(dst, tmp1, tmp2); 9069 %} 9070 %} 9071 9072 // Immediate Or 9073 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9074 match(Set dst (OrI src1 src2)); 9075 format %{ "ORI $dst, $src1, $src2" %} 9076 size(4); 9077 ins_encode %{ 9078 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9079 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9080 %} 9081 ins_pipe(pipe_class_default); 9082 %} 9083 9084 // Register Or Long 9085 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9086 match(Set dst (OrL src1 src2)); 9087 ins_cost(DEFAULT_COST); 9088 9089 size(4); 9090 format %{ "OR $dst, $src1, $src2 \t// long" %} 9091 ins_encode %{ 9092 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9093 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9094 %} 9095 ins_pipe(pipe_class_default); 9096 %} 9097 9098 // OrL + ConvL2I. 9099 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9100 match(Set dst (ConvL2I (OrL src1 src2))); 9101 ins_cost(DEFAULT_COST); 9102 9103 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9104 size(4); 9105 ins_encode %{ 9106 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9107 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9108 %} 9109 ins_pipe(pipe_class_default); 9110 %} 9111 9112 // Immediate Or long 9113 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9114 match(Set dst (OrL src1 con)); 9115 ins_cost(DEFAULT_COST); 9116 9117 format %{ "ORI $dst, $src1, $con \t// long" %} 9118 size(4); 9119 ins_encode %{ 9120 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9121 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9122 %} 9123 ins_pipe(pipe_class_default); 9124 %} 9125 9126 // Xor Instructions 9127 9128 // Register Xor 9129 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9130 match(Set dst (XorI src1 src2)); 9131 format %{ "XOR $dst, $src1, $src2" %} 9132 size(4); 9133 ins_encode %{ 9134 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9135 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9136 %} 9137 ins_pipe(pipe_class_default); 9138 %} 9139 9140 // Expand does not work with above instruct. (??) 9141 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9142 // no match-rule 9143 effect(DEF dst, USE src1, USE src2); 9144 format %{ "XOR $dst, $src1, $src2" %} 9145 size(4); 9146 ins_encode %{ 9147 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9148 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9149 %} 9150 ins_pipe(pipe_class_default); 9151 %} 9152 9153 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9154 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9155 ins_cost(DEFAULT_COST*3); 9156 9157 expand %{ 9158 // FIXME: we should do this in the ideal world. 9159 iRegIdst tmp1; 9160 iRegIdst tmp2; 9161 xorI_reg_reg(tmp1, src1, src2); 9162 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9163 xorI_reg_reg(dst, tmp1, tmp2); 9164 %} 9165 %} 9166 9167 // Immediate Xor 9168 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9169 match(Set dst (XorI src1 src2)); 9170 format %{ "XORI $dst, $src1, $src2" %} 9171 size(4); 9172 ins_encode %{ 9173 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9174 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9175 %} 9176 ins_pipe(pipe_class_default); 9177 %} 9178 9179 // Register Xor Long 9180 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9181 match(Set dst (XorL src1 src2)); 9182 ins_cost(DEFAULT_COST); 9183 9184 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9185 size(4); 9186 ins_encode %{ 9187 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9188 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9189 %} 9190 ins_pipe(pipe_class_default); 9191 %} 9192 9193 // XorL + ConvL2I. 9194 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9195 match(Set dst (ConvL2I (XorL src1 src2))); 9196 ins_cost(DEFAULT_COST); 9197 9198 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9199 size(4); 9200 ins_encode %{ 9201 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9202 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9203 %} 9204 ins_pipe(pipe_class_default); 9205 %} 9206 9207 // Immediate Xor Long 9208 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9209 match(Set dst (XorL src1 src2)); 9210 ins_cost(DEFAULT_COST); 9211 9212 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9213 size(4); 9214 ins_encode %{ 9215 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9216 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9217 %} 9218 ins_pipe(pipe_class_default); 9219 %} 9220 9221 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9222 match(Set dst (XorI src1 src2)); 9223 ins_cost(DEFAULT_COST); 9224 9225 format %{ "NOT $dst, $src1 ($src2)" %} 9226 size(4); 9227 ins_encode %{ 9228 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9229 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9230 %} 9231 ins_pipe(pipe_class_default); 9232 %} 9233 9234 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9235 match(Set dst (XorL src1 src2)); 9236 ins_cost(DEFAULT_COST); 9237 9238 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9239 size(4); 9240 ins_encode %{ 9241 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9242 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9243 %} 9244 ins_pipe(pipe_class_default); 9245 %} 9246 9247 // And-complement 9248 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9249 match(Set dst (AndI (XorI src1 src2) src3)); 9250 ins_cost(DEFAULT_COST); 9251 9252 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9253 size(4); 9254 ins_encode( enc_andc(dst, src3, src1) ); 9255 ins_pipe(pipe_class_default); 9256 %} 9257 9258 // And-complement 9259 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9260 // no match-rule, false predicate 9261 effect(DEF dst, USE src1, USE src2); 9262 predicate(false); 9263 9264 format %{ "ANDC $dst, $src1, $src2" %} 9265 size(4); 9266 ins_encode %{ 9267 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9268 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9269 %} 9270 ins_pipe(pipe_class_default); 9271 %} 9272 9273 //----------Moves between int/long and float/double---------------------------- 9274 // 9275 // The following rules move values from int/long registers/stack-locations 9276 // to float/double registers/stack-locations and vice versa, without doing any 9277 // conversions. These rules are used to implement the bit-conversion methods 9278 // of java.lang.Float etc., e.g. 9279 // int floatToIntBits(float value) 9280 // float intBitsToFloat(int bits) 9281 // 9282 // Notes on the implementation on ppc64: 9283 // We only provide rules which move between a register and a stack-location, 9284 // because we always have to go through memory when moving between a float 9285 // register and an integer register. 9286 9287 //---------- Chain stack slots between similar types -------- 9288 9289 // These are needed so that the rules below can match. 9290 9291 // Load integer from stack slot 9292 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9293 match(Set dst src); 9294 ins_cost(MEMORY_REF_COST); 9295 9296 format %{ "LWZ $dst, $src" %} 9297 size(4); 9298 ins_encode( enc_lwz(dst, src) ); 9299 ins_pipe(pipe_class_memory); 9300 %} 9301 9302 // Store integer to stack slot 9303 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9304 match(Set dst src); 9305 ins_cost(MEMORY_REF_COST); 9306 9307 format %{ "STW $src, $dst \t// stk" %} 9308 size(4); 9309 ins_encode( enc_stw(src, dst) ); // rs=rt 9310 ins_pipe(pipe_class_memory); 9311 %} 9312 9313 // Load long from stack slot 9314 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9315 match(Set dst src); 9316 ins_cost(MEMORY_REF_COST); 9317 9318 format %{ "LD $dst, $src \t// long" %} 9319 size(4); 9320 ins_encode( enc_ld(dst, src) ); 9321 ins_pipe(pipe_class_memory); 9322 %} 9323 9324 // Store long to stack slot 9325 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9326 match(Set dst src); 9327 ins_cost(MEMORY_REF_COST); 9328 9329 format %{ "STD $src, $dst \t// long" %} 9330 size(4); 9331 ins_encode( enc_std(src, dst) ); // rs=rt 9332 ins_pipe(pipe_class_memory); 9333 %} 9334 9335 //----------Moves between int and float 9336 9337 // Move float value from float stack-location to integer register. 9338 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9339 match(Set dst (MoveF2I src)); 9340 ins_cost(MEMORY_REF_COST); 9341 9342 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9343 size(4); 9344 ins_encode( enc_lwz(dst, src) ); 9345 ins_pipe(pipe_class_memory); 9346 %} 9347 9348 // Move float value from float register to integer stack-location. 9349 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9350 match(Set dst (MoveF2I src)); 9351 ins_cost(MEMORY_REF_COST); 9352 9353 format %{ "STFS $src, $dst \t// MoveF2I" %} 9354 size(4); 9355 ins_encode( enc_stfs(src, dst) ); 9356 ins_pipe(pipe_class_memory); 9357 %} 9358 9359 // Move integer value from integer stack-location to float register. 9360 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9361 match(Set dst (MoveI2F src)); 9362 ins_cost(MEMORY_REF_COST); 9363 9364 format %{ "LFS $dst, $src \t// MoveI2F" %} 9365 size(4); 9366 ins_encode %{ 9367 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9368 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9369 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9370 %} 9371 ins_pipe(pipe_class_memory); 9372 %} 9373 9374 // Move integer value from integer register to float stack-location. 9375 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9376 match(Set dst (MoveI2F src)); 9377 ins_cost(MEMORY_REF_COST); 9378 9379 format %{ "STW $src, $dst \t// MoveI2F" %} 9380 size(4); 9381 ins_encode( enc_stw(src, dst) ); 9382 ins_pipe(pipe_class_memory); 9383 %} 9384 9385 //----------Moves between long and float 9386 9387 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9388 // no match-rule, false predicate 9389 effect(DEF dst, USE src); 9390 predicate(false); 9391 9392 format %{ "storeD $src, $dst \t// STACK" %} 9393 size(4); 9394 ins_encode( enc_stfd(src, dst) ); 9395 ins_pipe(pipe_class_default); 9396 %} 9397 9398 //----------Moves between long and double 9399 9400 // Move double value from double stack-location to long register. 9401 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9402 match(Set dst (MoveD2L src)); 9403 ins_cost(MEMORY_REF_COST); 9404 size(4); 9405 format %{ "LD $dst, $src \t// MoveD2L" %} 9406 ins_encode( enc_ld(dst, src) ); 9407 ins_pipe(pipe_class_memory); 9408 %} 9409 9410 // Move double value from double register to long stack-location. 9411 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9412 match(Set dst (MoveD2L src)); 9413 effect(DEF dst, USE src); 9414 ins_cost(MEMORY_REF_COST); 9415 9416 format %{ "STFD $src, $dst \t// MoveD2L" %} 9417 size(4); 9418 ins_encode( enc_stfd(src, dst) ); 9419 ins_pipe(pipe_class_memory); 9420 %} 9421 9422 // Move long value from long stack-location to double register. 9423 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9424 match(Set dst (MoveL2D src)); 9425 ins_cost(MEMORY_REF_COST); 9426 9427 format %{ "LFD $dst, $src \t// MoveL2D" %} 9428 size(4); 9429 ins_encode( enc_lfd(dst, src) ); 9430 ins_pipe(pipe_class_memory); 9431 %} 9432 9433 // Move long value from long register to double stack-location. 9434 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9435 match(Set dst (MoveL2D src)); 9436 ins_cost(MEMORY_REF_COST); 9437 9438 format %{ "STD $src, $dst \t// MoveL2D" %} 9439 size(4); 9440 ins_encode( enc_std(src, dst) ); 9441 ins_pipe(pipe_class_memory); 9442 %} 9443 9444 //----------Register Move Instructions----------------------------------------- 9445 9446 // Replicate for Superword 9447 9448 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9449 predicate(false); 9450 effect(DEF dst, USE src); 9451 9452 format %{ "MR $dst, $src \t// replicate " %} 9453 // variable size, 0 or 4. 9454 ins_encode %{ 9455 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9456 __ mr_if_needed($dst$$Register, $src$$Register); 9457 %} 9458 ins_pipe(pipe_class_default); 9459 %} 9460 9461 //----------Cast instructions (Java-level type cast)--------------------------- 9462 9463 // Cast Long to Pointer for unsafe natives. 9464 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9465 match(Set dst (CastX2P src)); 9466 9467 format %{ "MR $dst, $src \t// Long->Ptr" %} 9468 // variable size, 0 or 4. 9469 ins_encode %{ 9470 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9471 __ mr_if_needed($dst$$Register, $src$$Register); 9472 %} 9473 ins_pipe(pipe_class_default); 9474 %} 9475 9476 // Cast Pointer to Long for unsafe natives. 9477 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9478 match(Set dst (CastP2X src)); 9479 9480 format %{ "MR $dst, $src \t// Ptr->Long" %} 9481 // variable size, 0 or 4. 9482 ins_encode %{ 9483 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9484 __ mr_if_needed($dst$$Register, $src$$Register); 9485 %} 9486 ins_pipe(pipe_class_default); 9487 %} 9488 9489 instruct castPP(iRegPdst dst) %{ 9490 match(Set dst (CastPP dst)); 9491 format %{ " -- \t// castPP of $dst" %} 9492 size(0); 9493 ins_encode( /*empty*/ ); 9494 ins_pipe(pipe_class_default); 9495 %} 9496 9497 instruct castII(iRegIdst dst) %{ 9498 match(Set dst (CastII dst)); 9499 format %{ " -- \t// castII of $dst" %} 9500 size(0); 9501 ins_encode( /*empty*/ ); 9502 ins_pipe(pipe_class_default); 9503 %} 9504 9505 instruct checkCastPP(iRegPdst dst) %{ 9506 match(Set dst (CheckCastPP dst)); 9507 format %{ " -- \t// checkcastPP of $dst" %} 9508 size(0); 9509 ins_encode( /*empty*/ ); 9510 ins_pipe(pipe_class_default); 9511 %} 9512 9513 //----------Convert instructions----------------------------------------------- 9514 9515 // Convert to boolean. 9516 9517 // int_to_bool(src) : { 1 if src != 0 9518 // { 0 else 9519 // 9520 // strategy: 9521 // 1) Count leading zeros of 32 bit-value src, 9522 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9523 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9524 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9525 9526 // convI2Bool 9527 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9528 match(Set dst (Conv2B src)); 9529 predicate(UseCountLeadingZerosInstructionsPPC64); 9530 ins_cost(DEFAULT_COST); 9531 9532 expand %{ 9533 immI shiftAmount %{ 0x5 %} 9534 uimmI16 mask %{ 0x1 %} 9535 iRegIdst tmp1; 9536 iRegIdst tmp2; 9537 countLeadingZerosI(tmp1, src); 9538 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9539 xorI_reg_uimm16(dst, tmp2, mask); 9540 %} 9541 %} 9542 9543 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9544 match(Set dst (Conv2B src)); 9545 effect(TEMP crx); 9546 predicate(!UseCountLeadingZerosInstructionsPPC64); 9547 ins_cost(DEFAULT_COST); 9548 9549 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9550 "LI $dst, #0\n\t" 9551 "BEQ $crx, done\n\t" 9552 "LI $dst, #1\n" 9553 "done:" %} 9554 size(16); 9555 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9556 ins_pipe(pipe_class_compare); 9557 %} 9558 9559 // ConvI2B + XorI 9560 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9561 match(Set dst (XorI (Conv2B src) mask)); 9562 predicate(UseCountLeadingZerosInstructionsPPC64); 9563 ins_cost(DEFAULT_COST); 9564 9565 expand %{ 9566 immI shiftAmount %{ 0x5 %} 9567 iRegIdst tmp1; 9568 countLeadingZerosI(tmp1, src); 9569 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9570 %} 9571 %} 9572 9573 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9574 match(Set dst (XorI (Conv2B src) mask)); 9575 effect(TEMP crx); 9576 predicate(!UseCountLeadingZerosInstructionsPPC64); 9577 ins_cost(DEFAULT_COST); 9578 9579 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9580 "LI $dst, #1\n\t" 9581 "BEQ $crx, done\n\t" 9582 "LI $dst, #0\n" 9583 "done:" %} 9584 size(16); 9585 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9586 ins_pipe(pipe_class_compare); 9587 %} 9588 9589 // AndI 0b0..010..0 + ConvI2B 9590 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9591 match(Set dst (Conv2B (AndI src mask))); 9592 predicate(UseRotateAndMaskInstructionsPPC64); 9593 ins_cost(DEFAULT_COST); 9594 9595 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9596 size(4); 9597 ins_encode %{ 9598 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9599 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9600 %} 9601 ins_pipe(pipe_class_default); 9602 %} 9603 9604 // Convert pointer to boolean. 9605 // 9606 // ptr_to_bool(src) : { 1 if src != 0 9607 // { 0 else 9608 // 9609 // strategy: 9610 // 1) Count leading zeros of 64 bit-value src, 9611 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9612 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9613 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9614 9615 // ConvP2B 9616 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9617 match(Set dst (Conv2B src)); 9618 predicate(UseCountLeadingZerosInstructionsPPC64); 9619 ins_cost(DEFAULT_COST); 9620 9621 expand %{ 9622 immI shiftAmount %{ 0x6 %} 9623 uimmI16 mask %{ 0x1 %} 9624 iRegIdst tmp1; 9625 iRegIdst tmp2; 9626 countLeadingZerosP(tmp1, src); 9627 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9628 xorI_reg_uimm16(dst, tmp2, mask); 9629 %} 9630 %} 9631 9632 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9633 match(Set dst (Conv2B src)); 9634 effect(TEMP crx); 9635 predicate(!UseCountLeadingZerosInstructionsPPC64); 9636 ins_cost(DEFAULT_COST); 9637 9638 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9639 "LI $dst, #0\n\t" 9640 "BEQ $crx, done\n\t" 9641 "LI $dst, #1\n" 9642 "done:" %} 9643 size(16); 9644 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9645 ins_pipe(pipe_class_compare); 9646 %} 9647 9648 // ConvP2B + XorI 9649 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9650 match(Set dst (XorI (Conv2B src) mask)); 9651 predicate(UseCountLeadingZerosInstructionsPPC64); 9652 ins_cost(DEFAULT_COST); 9653 9654 expand %{ 9655 immI shiftAmount %{ 0x6 %} 9656 iRegIdst tmp1; 9657 countLeadingZerosP(tmp1, src); 9658 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9659 %} 9660 %} 9661 9662 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9663 match(Set dst (XorI (Conv2B src) mask)); 9664 effect(TEMP crx); 9665 predicate(!UseCountLeadingZerosInstructionsPPC64); 9666 ins_cost(DEFAULT_COST); 9667 9668 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9669 "LI $dst, #1\n\t" 9670 "BEQ $crx, done\n\t" 9671 "LI $dst, #0\n" 9672 "done:" %} 9673 size(16); 9674 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9675 ins_pipe(pipe_class_compare); 9676 %} 9677 9678 // if src1 < src2, return -1 else return 0 9679 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9680 match(Set dst (CmpLTMask src1 src2)); 9681 ins_cost(DEFAULT_COST*4); 9682 9683 expand %{ 9684 iRegLdst src1s; 9685 iRegLdst src2s; 9686 iRegLdst diff; 9687 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9688 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9689 subL_reg_reg(diff, src1s, src2s); 9690 // Need to consider >=33 bit result, therefore we need signmaskL. 9691 signmask64I_regL(dst, diff); 9692 %} 9693 %} 9694 9695 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9696 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9697 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9698 size(4); 9699 ins_encode %{ 9700 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9701 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9702 %} 9703 ins_pipe(pipe_class_default); 9704 %} 9705 9706 //----------Arithmetic Conversion Instructions--------------------------------- 9707 9708 // Convert to Byte -- nop 9709 // Convert to Short -- nop 9710 9711 // Convert to Int 9712 9713 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9714 match(Set dst (RShiftI (LShiftI src amount) amount)); 9715 format %{ "EXTSB $dst, $src \t// byte->int" %} 9716 size(4); 9717 ins_encode %{ 9718 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9719 __ extsb($dst$$Register, $src$$Register); 9720 %} 9721 ins_pipe(pipe_class_default); 9722 %} 9723 9724 // LShiftI 16 + RShiftI 16 converts short to int. 9725 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9726 match(Set dst (RShiftI (LShiftI src amount) amount)); 9727 format %{ "EXTSH $dst, $src \t// short->int" %} 9728 size(4); 9729 ins_encode %{ 9730 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9731 __ extsh($dst$$Register, $src$$Register); 9732 %} 9733 ins_pipe(pipe_class_default); 9734 %} 9735 9736 // ConvL2I + ConvI2L: Sign extend int in long register. 9737 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9738 match(Set dst (ConvI2L (ConvL2I src))); 9739 9740 format %{ "EXTSW $dst, $src \t// long->long" %} 9741 size(4); 9742 ins_encode %{ 9743 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9744 __ extsw($dst$$Register, $src$$Register); 9745 %} 9746 ins_pipe(pipe_class_default); 9747 %} 9748 9749 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9750 match(Set dst (ConvL2I src)); 9751 format %{ "MR $dst, $src \t// long->int" %} 9752 // variable size, 0 or 4 9753 ins_encode %{ 9754 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9755 __ mr_if_needed($dst$$Register, $src$$Register); 9756 %} 9757 ins_pipe(pipe_class_default); 9758 %} 9759 9760 instruct convD2IRaw_regD(regD dst, regD src) %{ 9761 // no match-rule, false predicate 9762 effect(DEF dst, USE src); 9763 predicate(false); 9764 9765 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9766 size(4); 9767 ins_encode %{ 9768 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9769 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9770 %} 9771 ins_pipe(pipe_class_default); 9772 %} 9773 9774 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{ 9775 // no match-rule, false predicate 9776 effect(DEF dst, USE crx, USE src); 9777 predicate(false); 9778 9779 ins_variable_size_depending_on_alignment(true); 9780 9781 format %{ "cmovI $crx, $dst, $src" %} 9782 // Worst case is branch + move + stop, no stop without scheduler. 9783 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9784 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9785 ins_pipe(pipe_class_default); 9786 %} 9787 9788 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9789 // no match-rule, false predicate 9790 effect(DEF dst, USE crx, USE mem); 9791 predicate(false); 9792 9793 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9794 postalloc_expand %{ 9795 // 9796 // replaces 9797 // 9798 // region dst crx mem 9799 // \ | | / 9800 // dst=cmovI_bso_stackSlotL_conLvalue0 9801 // 9802 // with 9803 // 9804 // region dst 9805 // \ / 9806 // dst=loadConI16(0) 9807 // | 9808 // ^ region dst crx mem 9809 // | \ | | / 9810 // dst=cmovI_bso_stackSlotL 9811 // 9812 9813 // Create new nodes. 9814 MachNode *m1 = new loadConI16Node(); 9815 MachNode *m2 = new cmovI_bso_stackSlotLNode(); 9816 9817 // inputs for new nodes 9818 m1->add_req(n_region); 9819 m2->add_req(n_region, n_crx, n_mem); 9820 9821 // precedences for new nodes 9822 m2->add_prec(m1); 9823 9824 // operands for new nodes 9825 m1->_opnds[0] = op_dst; 9826 m1->_opnds[1] = new immI16Oper(0); 9827 9828 m2->_opnds[0] = op_dst; 9829 m2->_opnds[1] = op_crx; 9830 m2->_opnds[2] = op_mem; 9831 9832 // registers for new nodes 9833 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9834 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9835 9836 // Insert new nodes. 9837 nodes->push(m1); 9838 nodes->push(m2); 9839 %} 9840 %} 9841 9842 // Double to Int conversion, NaN is mapped to 0. 9843 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9844 match(Set dst (ConvD2I src)); 9845 ins_cost(DEFAULT_COST); 9846 9847 expand %{ 9848 regD tmpD; 9849 stackSlotL tmpS; 9850 flagsReg crx; 9851 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9852 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9853 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9854 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9855 %} 9856 %} 9857 9858 instruct convF2IRaw_regF(regF dst, regF src) %{ 9859 // no match-rule, false predicate 9860 effect(DEF dst, USE src); 9861 predicate(false); 9862 9863 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9864 size(4); 9865 ins_encode %{ 9866 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9867 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9868 %} 9869 ins_pipe(pipe_class_default); 9870 %} 9871 9872 // Float to Int conversion, NaN is mapped to 0. 9873 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9874 match(Set dst (ConvF2I src)); 9875 ins_cost(DEFAULT_COST); 9876 9877 expand %{ 9878 regF tmpF; 9879 stackSlotL tmpS; 9880 flagsReg crx; 9881 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9882 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9883 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9884 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9885 %} 9886 %} 9887 9888 // Convert to Long 9889 9890 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9891 match(Set dst (ConvI2L src)); 9892 format %{ "EXTSW $dst, $src \t// int->long" %} 9893 size(4); 9894 ins_encode %{ 9895 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9896 __ extsw($dst$$Register, $src$$Register); 9897 %} 9898 ins_pipe(pipe_class_default); 9899 %} 9900 9901 // Zero-extend: convert unsigned int to long (convUI2L). 9902 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9903 match(Set dst (AndL (ConvI2L src) mask)); 9904 ins_cost(DEFAULT_COST); 9905 9906 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9907 size(4); 9908 ins_encode %{ 9909 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9910 __ clrldi($dst$$Register, $src$$Register, 32); 9911 %} 9912 ins_pipe(pipe_class_default); 9913 %} 9914 9915 // Zero-extend: convert unsigned int to long in long register. 9916 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 9917 match(Set dst (AndL src mask)); 9918 ins_cost(DEFAULT_COST); 9919 9920 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9921 size(4); 9922 ins_encode %{ 9923 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9924 __ clrldi($dst$$Register, $src$$Register, 32); 9925 %} 9926 ins_pipe(pipe_class_default); 9927 %} 9928 9929 instruct convF2LRaw_regF(regF dst, regF src) %{ 9930 // no match-rule, false predicate 9931 effect(DEF dst, USE src); 9932 predicate(false); 9933 9934 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 9935 size(4); 9936 ins_encode %{ 9937 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9938 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9939 %} 9940 ins_pipe(pipe_class_default); 9941 %} 9942 9943 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{ 9944 // no match-rule, false predicate 9945 effect(DEF dst, USE crx, USE src); 9946 predicate(false); 9947 9948 ins_variable_size_depending_on_alignment(true); 9949 9950 format %{ "cmovL $crx, $dst, $src" %} 9951 // Worst case is branch + move + stop, no stop without scheduler. 9952 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 9953 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9954 ins_pipe(pipe_class_default); 9955 %} 9956 9957 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9958 // no match-rule, false predicate 9959 effect(DEF dst, USE crx, USE mem); 9960 predicate(false); 9961 9962 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 9963 postalloc_expand %{ 9964 // 9965 // replaces 9966 // 9967 // region dst crx mem 9968 // \ | | / 9969 // dst=cmovL_bso_stackSlotL_conLvalue0 9970 // 9971 // with 9972 // 9973 // region dst 9974 // \ / 9975 // dst=loadConL16(0) 9976 // | 9977 // ^ region dst crx mem 9978 // | \ | | / 9979 // dst=cmovL_bso_stackSlotL 9980 // 9981 9982 // Create new nodes. 9983 MachNode *m1 = new loadConL16Node(); 9984 MachNode *m2 = new cmovL_bso_stackSlotLNode(); 9985 9986 // inputs for new nodes 9987 m1->add_req(n_region); 9988 m2->add_req(n_region, n_crx, n_mem); 9989 m2->add_prec(m1); 9990 9991 // operands for new nodes 9992 m1->_opnds[0] = op_dst; 9993 m1->_opnds[1] = new immL16Oper(0); 9994 m2->_opnds[0] = op_dst; 9995 m2->_opnds[1] = op_crx; 9996 m2->_opnds[2] = op_mem; 9997 9998 // registers for new nodes 9999 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10000 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10001 10002 // Insert new nodes. 10003 nodes->push(m1); 10004 nodes->push(m2); 10005 %} 10006 %} 10007 10008 // Float to Long conversion, NaN is mapped to 0. 10009 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 10010 match(Set dst (ConvF2L src)); 10011 ins_cost(DEFAULT_COST); 10012 10013 expand %{ 10014 regF tmpF; 10015 stackSlotL tmpS; 10016 flagsReg crx; 10017 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10018 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 10019 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 10020 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10021 %} 10022 %} 10023 10024 instruct convD2LRaw_regD(regD dst, regD src) %{ 10025 // no match-rule, false predicate 10026 effect(DEF dst, USE src); 10027 predicate(false); 10028 10029 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 10030 size(4); 10031 ins_encode %{ 10032 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 10033 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 10034 %} 10035 ins_pipe(pipe_class_default); 10036 %} 10037 10038 // Double to Long conversion, NaN is mapped to 0. 10039 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 10040 match(Set dst (ConvD2L src)); 10041 ins_cost(DEFAULT_COST); 10042 10043 expand %{ 10044 regD tmpD; 10045 stackSlotL tmpS; 10046 flagsReg crx; 10047 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10048 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10049 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10050 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10051 %} 10052 %} 10053 10054 // Convert to Float 10055 10056 // Placed here as needed in expand. 10057 instruct convL2DRaw_regD(regD dst, regD src) %{ 10058 // no match-rule, false predicate 10059 effect(DEF dst, USE src); 10060 predicate(false); 10061 10062 format %{ "FCFID $dst, $src \t// convL2D" %} 10063 size(4); 10064 ins_encode %{ 10065 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10066 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10067 %} 10068 ins_pipe(pipe_class_default); 10069 %} 10070 10071 // Placed here as needed in expand. 10072 instruct convD2F_reg(regF dst, regD src) %{ 10073 match(Set dst (ConvD2F src)); 10074 format %{ "FRSP $dst, $src \t// convD2F" %} 10075 size(4); 10076 ins_encode %{ 10077 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10078 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10079 %} 10080 ins_pipe(pipe_class_default); 10081 %} 10082 10083 // Integer to Float conversion. 10084 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10085 match(Set dst (ConvI2F src)); 10086 predicate(!VM_Version::has_fcfids()); 10087 ins_cost(DEFAULT_COST); 10088 10089 expand %{ 10090 iRegLdst tmpL; 10091 stackSlotL tmpS; 10092 regD tmpD; 10093 regD tmpD2; 10094 convI2L_reg(tmpL, src); // Sign-extension int to long. 10095 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10096 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10097 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10098 convD2F_reg(dst, tmpD2); // Convert double to float. 10099 %} 10100 %} 10101 10102 instruct convL2FRaw_regF(regF dst, regD src) %{ 10103 // no match-rule, false predicate 10104 effect(DEF dst, USE src); 10105 predicate(false); 10106 10107 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10108 size(4); 10109 ins_encode %{ 10110 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10111 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10112 %} 10113 ins_pipe(pipe_class_default); 10114 %} 10115 10116 // Integer to Float conversion. Special version for Power7. 10117 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10118 match(Set dst (ConvI2F src)); 10119 predicate(VM_Version::has_fcfids()); 10120 ins_cost(DEFAULT_COST); 10121 10122 expand %{ 10123 iRegLdst tmpL; 10124 stackSlotL tmpS; 10125 regD tmpD; 10126 convI2L_reg(tmpL, src); // Sign-extension int to long. 10127 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10128 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10129 convL2FRaw_regF(dst, tmpD); // Convert to float. 10130 %} 10131 %} 10132 10133 // L2F to avoid runtime call. 10134 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10135 match(Set dst (ConvL2F src)); 10136 predicate(VM_Version::has_fcfids()); 10137 ins_cost(DEFAULT_COST); 10138 10139 expand %{ 10140 stackSlotL tmpS; 10141 regD tmpD; 10142 regL_to_stkL(tmpS, src); // Store long to stack. 10143 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10144 convL2FRaw_regF(dst, tmpD); // Convert to float. 10145 %} 10146 %} 10147 10148 // Moved up as used in expand. 10149 //instruct convD2F_reg(regF dst, regD src) %{%} 10150 10151 // Convert to Double 10152 10153 // Integer to Double conversion. 10154 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10155 match(Set dst (ConvI2D src)); 10156 ins_cost(DEFAULT_COST); 10157 10158 expand %{ 10159 iRegLdst tmpL; 10160 stackSlotL tmpS; 10161 regD tmpD; 10162 convI2L_reg(tmpL, src); // Sign-extension int to long. 10163 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10164 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10165 convL2DRaw_regD(dst, tmpD); // Convert to double. 10166 %} 10167 %} 10168 10169 // Long to Double conversion 10170 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10171 match(Set dst (ConvL2D src)); 10172 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10173 10174 expand %{ 10175 regD tmpD; 10176 moveL2D_stack_reg(tmpD, src); 10177 convL2DRaw_regD(dst, tmpD); 10178 %} 10179 %} 10180 10181 instruct convF2D_reg(regD dst, regF src) %{ 10182 match(Set dst (ConvF2D src)); 10183 format %{ "FMR $dst, $src \t// float->double" %} 10184 // variable size, 0 or 4 10185 ins_encode %{ 10186 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10187 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10188 %} 10189 ins_pipe(pipe_class_default); 10190 %} 10191 10192 //----------Control Flow Instructions------------------------------------------ 10193 // Compare Instructions 10194 10195 // Compare Integers 10196 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10197 match(Set crx (CmpI src1 src2)); 10198 size(4); 10199 format %{ "CMPW $crx, $src1, $src2" %} 10200 ins_encode %{ 10201 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10202 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10203 %} 10204 ins_pipe(pipe_class_compare); 10205 %} 10206 10207 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10208 match(Set crx (CmpI src1 src2)); 10209 format %{ "CMPWI $crx, $src1, $src2" %} 10210 size(4); 10211 ins_encode %{ 10212 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10213 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10214 %} 10215 ins_pipe(pipe_class_compare); 10216 %} 10217 10218 // (src1 & src2) == 0? 10219 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10220 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10221 // r0 is killed 10222 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10223 size(4); 10224 ins_encode %{ 10225 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10226 __ andi_(R0, $src1$$Register, $src2$$constant); 10227 %} 10228 ins_pipe(pipe_class_compare); 10229 %} 10230 10231 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10232 match(Set crx (CmpL src1 src2)); 10233 format %{ "CMPD $crx, $src1, $src2" %} 10234 size(4); 10235 ins_encode %{ 10236 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10237 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10238 %} 10239 ins_pipe(pipe_class_compare); 10240 %} 10241 10242 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10243 match(Set crx (CmpL src1 src2)); 10244 format %{ "CMPDI $crx, $src1, $src2" %} 10245 size(4); 10246 ins_encode %{ 10247 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10248 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10249 %} 10250 ins_pipe(pipe_class_compare); 10251 %} 10252 10253 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10254 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10255 // r0 is killed 10256 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10257 size(4); 10258 ins_encode %{ 10259 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10260 __ and_(R0, $src1$$Register, $src2$$Register); 10261 %} 10262 ins_pipe(pipe_class_compare); 10263 %} 10264 10265 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10266 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10267 // r0 is killed 10268 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10269 size(4); 10270 ins_encode %{ 10271 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10272 __ andi_(R0, $src1$$Register, $src2$$constant); 10273 %} 10274 ins_pipe(pipe_class_compare); 10275 %} 10276 10277 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{ 10278 // no match-rule, false predicate 10279 effect(DEF dst, USE crx); 10280 predicate(false); 10281 10282 ins_variable_size_depending_on_alignment(true); 10283 10284 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10285 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10286 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10287 ins_encode %{ 10288 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10289 Label done; 10290 // li(Rdst, 0); // equal -> 0 10291 __ beq($crx$$CondRegister, done); 10292 __ li($dst$$Register, 1); // greater -> +1 10293 __ bgt($crx$$CondRegister, done); 10294 __ li($dst$$Register, -1); // unordered or less -> -1 10295 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10296 __ bind(done); 10297 %} 10298 ins_pipe(pipe_class_compare); 10299 %} 10300 10301 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{ 10302 // no match-rule, false predicate 10303 effect(DEF dst, USE crx); 10304 predicate(false); 10305 10306 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10307 postalloc_expand %{ 10308 // 10309 // replaces 10310 // 10311 // region crx 10312 // \ | 10313 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10314 // 10315 // with 10316 // 10317 // region 10318 // \ 10319 // dst=loadConI16(0) 10320 // | 10321 // ^ region crx 10322 // | \ | 10323 // dst=cmovI_conIvalueMinus1_conIvalue1 10324 // 10325 10326 // Create new nodes. 10327 MachNode *m1 = new loadConI16Node(); 10328 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node(); 10329 10330 // inputs for new nodes 10331 m1->add_req(n_region); 10332 m2->add_req(n_region, n_crx); 10333 m2->add_prec(m1); 10334 10335 // operands for new nodes 10336 m1->_opnds[0] = op_dst; 10337 m1->_opnds[1] = new immI16Oper(0); 10338 m2->_opnds[0] = op_dst; 10339 m2->_opnds[1] = op_crx; 10340 10341 // registers for new nodes 10342 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10343 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10344 10345 // Insert new nodes. 10346 nodes->push(m1); 10347 nodes->push(m2); 10348 %} 10349 %} 10350 10351 // Manifest a CmpL3 result in an integer register. Very painful. 10352 // This is the test to avoid. 10353 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10354 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10355 match(Set dst (CmpL3 src1 src2)); 10356 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10357 10358 expand %{ 10359 flagsReg tmp1; 10360 cmpL_reg_reg(tmp1, src1, src2); 10361 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10362 %} 10363 %} 10364 10365 // Implicit range checks. 10366 // A range check in the ideal world has one of the following shapes: 10367 // - (If le (CmpU length index)), (IfTrue throw exception) 10368 // - (If lt (CmpU index length)), (IfFalse throw exception) 10369 // 10370 // Match range check 'If le (CmpU length index)'. 10371 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10372 match(If cmp (CmpU src_length index)); 10373 effect(USE labl); 10374 predicate(TrapBasedRangeChecks && 10375 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10376 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10377 (Matcher::branches_to_uncommon_trap(_leaf))); 10378 10379 ins_is_TrapBasedCheckNode(true); 10380 10381 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10382 size(4); 10383 ins_encode %{ 10384 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10385 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10386 __ trap_range_check_le($src_length$$Register, $index$$constant); 10387 } else { 10388 // Both successors are uncommon traps, probability is 0. 10389 // Node got flipped during fixup flow. 10390 assert($cmp$$cmpcode == 0x9, "must be greater"); 10391 __ trap_range_check_g($src_length$$Register, $index$$constant); 10392 } 10393 %} 10394 ins_pipe(pipe_class_trap); 10395 %} 10396 10397 // Match range check 'If lt (CmpU index length)'. 10398 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10399 match(If cmp (CmpU src_index src_length)); 10400 effect(USE labl); 10401 predicate(TrapBasedRangeChecks && 10402 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10403 _leaf->as_If()->_prob >= PROB_ALWAYS && 10404 (Matcher::branches_to_uncommon_trap(_leaf))); 10405 10406 ins_is_TrapBasedCheckNode(true); 10407 10408 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10409 size(4); 10410 ins_encode %{ 10411 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10412 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10413 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10414 } else { 10415 // Both successors are uncommon traps, probability is 0. 10416 // Node got flipped during fixup flow. 10417 assert($cmp$$cmpcode == 0x8, "must be less"); 10418 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10419 } 10420 %} 10421 ins_pipe(pipe_class_trap); 10422 %} 10423 10424 // Match range check 'If lt (CmpU index length)'. 10425 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10426 match(If cmp (CmpU src_index length)); 10427 effect(USE labl); 10428 predicate(TrapBasedRangeChecks && 10429 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10430 _leaf->as_If()->_prob >= PROB_ALWAYS && 10431 (Matcher::branches_to_uncommon_trap(_leaf))); 10432 10433 ins_is_TrapBasedCheckNode(true); 10434 10435 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10436 size(4); 10437 ins_encode %{ 10438 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10439 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10440 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10441 } else { 10442 // Both successors are uncommon traps, probability is 0. 10443 // Node got flipped during fixup flow. 10444 assert($cmp$$cmpcode == 0x8, "must be less"); 10445 __ trap_range_check_l($src_index$$Register, $length$$constant); 10446 } 10447 %} 10448 ins_pipe(pipe_class_trap); 10449 %} 10450 10451 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10452 match(Set crx (CmpU src1 src2)); 10453 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10454 size(4); 10455 ins_encode %{ 10456 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10457 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10458 %} 10459 ins_pipe(pipe_class_compare); 10460 %} 10461 10462 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10463 match(Set crx (CmpU src1 src2)); 10464 size(4); 10465 format %{ "CMPLWI $crx, $src1, $src2" %} 10466 ins_encode %{ 10467 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10468 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10469 %} 10470 ins_pipe(pipe_class_compare); 10471 %} 10472 10473 // Implicit zero checks (more implicit null checks). 10474 // No constant pool entries required. 10475 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10476 match(If cmp (CmpN value zero)); 10477 effect(USE labl); 10478 predicate(TrapBasedNullChecks && 10479 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10480 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10481 Matcher::branches_to_uncommon_trap(_leaf)); 10482 ins_cost(1); 10483 10484 ins_is_TrapBasedCheckNode(true); 10485 10486 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10487 size(4); 10488 ins_encode %{ 10489 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10490 if ($cmp$$cmpcode == 0xA) { 10491 __ trap_null_check($value$$Register); 10492 } else { 10493 // Both successors are uncommon traps, probability is 0. 10494 // Node got flipped during fixup flow. 10495 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10496 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10497 } 10498 %} 10499 ins_pipe(pipe_class_trap); 10500 %} 10501 10502 // Compare narrow oops. 10503 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10504 match(Set crx (CmpN src1 src2)); 10505 10506 size(4); 10507 ins_cost(2); 10508 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10509 ins_encode %{ 10510 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10511 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10512 %} 10513 ins_pipe(pipe_class_compare); 10514 %} 10515 10516 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10517 match(Set crx (CmpN src1 src2)); 10518 // Make this more expensive than zeroCheckN_iReg_imm0. 10519 ins_cost(2); 10520 10521 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10522 size(4); 10523 ins_encode %{ 10524 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10525 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10526 %} 10527 ins_pipe(pipe_class_compare); 10528 %} 10529 10530 // Implicit zero checks (more implicit null checks). 10531 // No constant pool entries required. 10532 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10533 match(If cmp (CmpP value zero)); 10534 effect(USE labl); 10535 predicate(TrapBasedNullChecks && 10536 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10537 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10538 Matcher::branches_to_uncommon_trap(_leaf)); 10539 ins_cost(1); // Should not be cheaper than zeroCheckN. 10540 10541 ins_is_TrapBasedCheckNode(true); 10542 10543 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10544 size(4); 10545 ins_encode %{ 10546 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10547 if ($cmp$$cmpcode == 0xA) { 10548 __ trap_null_check($value$$Register); 10549 } else { 10550 // Both successors are uncommon traps, probability is 0. 10551 // Node got flipped during fixup flow. 10552 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10553 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10554 } 10555 %} 10556 ins_pipe(pipe_class_trap); 10557 %} 10558 10559 // Compare Pointers 10560 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10561 match(Set crx (CmpP src1 src2)); 10562 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10563 size(4); 10564 ins_encode %{ 10565 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10566 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10567 %} 10568 ins_pipe(pipe_class_compare); 10569 %} 10570 10571 // Used in postalloc expand. 10572 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10573 // This match rule prevents reordering of node before a safepoint. 10574 // This only makes sense if this instructions is used exclusively 10575 // for the expansion of EncodeP! 10576 match(Set crx (CmpP src1 src2)); 10577 predicate(false); 10578 10579 format %{ "CMPDI $crx, $src1, $src2" %} 10580 size(4); 10581 ins_encode %{ 10582 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10583 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10584 %} 10585 ins_pipe(pipe_class_compare); 10586 %} 10587 10588 //----------Float Compares---------------------------------------------------- 10589 10590 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10591 // Needs matchrule, see cmpDUnordered. 10592 match(Set crx (CmpF src1 src2)); 10593 // no match-rule, false predicate 10594 predicate(false); 10595 10596 format %{ "cmpFUrd $crx, $src1, $src2" %} 10597 size(4); 10598 ins_encode %{ 10599 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10600 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10601 %} 10602 ins_pipe(pipe_class_default); 10603 %} 10604 10605 instruct cmov_bns_less(flagsReg crx) %{ 10606 // no match-rule, false predicate 10607 effect(DEF crx); 10608 predicate(false); 10609 10610 ins_variable_size_depending_on_alignment(true); 10611 10612 format %{ "cmov $crx" %} 10613 // Worst case is branch + move + stop, no stop without scheduler. 10614 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10615 ins_encode %{ 10616 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10617 Label done; 10618 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10619 __ li(R0, 0); 10620 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10621 // TODO PPC port __ endgroup_if_needed(_size == 16); 10622 __ bind(done); 10623 %} 10624 ins_pipe(pipe_class_default); 10625 %} 10626 10627 // Compare floating, generate condition code. 10628 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10629 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10630 // 10631 // The following code sequence occurs a lot in mpegaudio: 10632 // 10633 // block BXX: 10634 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10635 // cmpFUrd CCR6, F11, F9 10636 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10637 // cmov CCR6 10638 // 8: instruct branchConSched: 10639 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10640 match(Set crx (CmpF src1 src2)); 10641 ins_cost(DEFAULT_COST+BRANCH_COST); 10642 10643 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10644 postalloc_expand %{ 10645 // 10646 // replaces 10647 // 10648 // region src1 src2 10649 // \ | | 10650 // crx=cmpF_reg_reg 10651 // 10652 // with 10653 // 10654 // region src1 src2 10655 // \ | | 10656 // crx=cmpFUnordered_reg_reg 10657 // | 10658 // ^ region 10659 // | \ 10660 // crx=cmov_bns_less 10661 // 10662 10663 // Create new nodes. 10664 MachNode *m1 = new cmpFUnordered_reg_regNode(); 10665 MachNode *m2 = new cmov_bns_lessNode(); 10666 10667 // inputs for new nodes 10668 m1->add_req(n_region, n_src1, n_src2); 10669 m2->add_req(n_region); 10670 m2->add_prec(m1); 10671 10672 // operands for new nodes 10673 m1->_opnds[0] = op_crx; 10674 m1->_opnds[1] = op_src1; 10675 m1->_opnds[2] = op_src2; 10676 m2->_opnds[0] = op_crx; 10677 10678 // registers for new nodes 10679 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10680 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10681 10682 // Insert new nodes. 10683 nodes->push(m1); 10684 nodes->push(m2); 10685 %} 10686 %} 10687 10688 // Compare float, generate -1,0,1 10689 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10690 match(Set dst (CmpF3 src1 src2)); 10691 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10692 10693 expand %{ 10694 flagsReg tmp1; 10695 cmpFUnordered_reg_reg(tmp1, src1, src2); 10696 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10697 %} 10698 %} 10699 10700 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10701 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the 10702 // node right before the conditional move using it. 10703 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7, 10704 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle 10705 // crashed in register allocation where the flags Reg between cmpDUnoredered and a 10706 // conditional move was supposed to be spilled. 10707 match(Set crx (CmpD src1 src2)); 10708 // False predicate, shall not be matched. 10709 predicate(false); 10710 10711 format %{ "cmpFUrd $crx, $src1, $src2" %} 10712 size(4); 10713 ins_encode %{ 10714 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10715 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10716 %} 10717 ins_pipe(pipe_class_default); 10718 %} 10719 10720 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10721 match(Set crx (CmpD src1 src2)); 10722 ins_cost(DEFAULT_COST+BRANCH_COST); 10723 10724 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10725 postalloc_expand %{ 10726 // 10727 // replaces 10728 // 10729 // region src1 src2 10730 // \ | | 10731 // crx=cmpD_reg_reg 10732 // 10733 // with 10734 // 10735 // region src1 src2 10736 // \ | | 10737 // crx=cmpDUnordered_reg_reg 10738 // | 10739 // ^ region 10740 // | \ 10741 // crx=cmov_bns_less 10742 // 10743 10744 // create new nodes 10745 MachNode *m1 = new cmpDUnordered_reg_regNode(); 10746 MachNode *m2 = new cmov_bns_lessNode(); 10747 10748 // inputs for new nodes 10749 m1->add_req(n_region, n_src1, n_src2); 10750 m2->add_req(n_region); 10751 m2->add_prec(m1); 10752 10753 // operands for new nodes 10754 m1->_opnds[0] = op_crx; 10755 m1->_opnds[1] = op_src1; 10756 m1->_opnds[2] = op_src2; 10757 m2->_opnds[0] = op_crx; 10758 10759 // registers for new nodes 10760 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10761 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10762 10763 // Insert new nodes. 10764 nodes->push(m1); 10765 nodes->push(m2); 10766 %} 10767 %} 10768 10769 // Compare double, generate -1,0,1 10770 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10771 match(Set dst (CmpD3 src1 src2)); 10772 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10773 10774 expand %{ 10775 flagsReg tmp1; 10776 cmpDUnordered_reg_reg(tmp1, src1, src2); 10777 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10778 %} 10779 %} 10780 10781 //----------Branches--------------------------------------------------------- 10782 // Jump 10783 10784 // Direct Branch. 10785 instruct branch(label labl) %{ 10786 match(Goto); 10787 effect(USE labl); 10788 ins_cost(BRANCH_COST); 10789 10790 format %{ "B $labl" %} 10791 size(4); 10792 ins_encode %{ 10793 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10794 Label d; // dummy 10795 __ bind(d); 10796 Label* p = $labl$$label; 10797 // `p' is `NULL' when this encoding class is used only to 10798 // determine the size of the encoded instruction. 10799 Label& l = (NULL == p)? d : *(p); 10800 __ b(l); 10801 %} 10802 ins_pipe(pipe_class_default); 10803 %} 10804 10805 // Conditional Near Branch 10806 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10807 // Same match rule as `branchConFar'. 10808 match(If cmp crx); 10809 effect(USE lbl); 10810 ins_cost(BRANCH_COST); 10811 10812 // If set to 1 this indicates that the current instruction is a 10813 // short variant of a long branch. This avoids using this 10814 // instruction in first-pass matching. It will then only be used in 10815 // the `Shorten_branches' pass. 10816 ins_short_branch(1); 10817 10818 format %{ "B$cmp $crx, $lbl" %} 10819 size(4); 10820 ins_encode( enc_bc(crx, cmp, lbl) ); 10821 ins_pipe(pipe_class_default); 10822 %} 10823 10824 // This is for cases when the ppc64 `bc' instruction does not 10825 // reach far enough. So we emit a far branch here, which is more 10826 // expensive. 10827 // 10828 // Conditional Far Branch 10829 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10830 // Same match rule as `branchCon'. 10831 match(If cmp crx); 10832 effect(USE crx, USE lbl); 10833 predicate(!false /* TODO: PPC port HB_Schedule*/); 10834 // Higher cost than `branchCon'. 10835 ins_cost(5*BRANCH_COST); 10836 10837 // This is not a short variant of a branch, but the long variant. 10838 ins_short_branch(0); 10839 10840 format %{ "B_FAR$cmp $crx, $lbl" %} 10841 size(8); 10842 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10843 ins_pipe(pipe_class_default); 10844 %} 10845 10846 // Conditional Branch used with Power6 scheduler (can be far or short). 10847 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10848 // Same match rule as `branchCon'. 10849 match(If cmp crx); 10850 effect(USE crx, USE lbl); 10851 predicate(false /* TODO: PPC port HB_Schedule*/); 10852 // Higher cost than `branchCon'. 10853 ins_cost(5*BRANCH_COST); 10854 10855 // Actually size doesn't depend on alignment but on shortening. 10856 ins_variable_size_depending_on_alignment(true); 10857 // long variant. 10858 ins_short_branch(0); 10859 10860 format %{ "B_FAR$cmp $crx, $lbl" %} 10861 size(8); // worst case 10862 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10863 ins_pipe(pipe_class_default); 10864 %} 10865 10866 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10867 match(CountedLoopEnd cmp crx); 10868 effect(USE labl); 10869 ins_cost(BRANCH_COST); 10870 10871 // short variant. 10872 ins_short_branch(1); 10873 10874 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10875 size(4); 10876 ins_encode( enc_bc(crx, cmp, labl) ); 10877 ins_pipe(pipe_class_default); 10878 %} 10879 10880 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10881 match(CountedLoopEnd cmp crx); 10882 effect(USE labl); 10883 predicate(!false /* TODO: PPC port HB_Schedule */); 10884 ins_cost(BRANCH_COST); 10885 10886 // Long variant. 10887 ins_short_branch(0); 10888 10889 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10890 size(8); 10891 ins_encode( enc_bc_far(crx, cmp, labl) ); 10892 ins_pipe(pipe_class_default); 10893 %} 10894 10895 // Conditional Branch used with Power6 scheduler (can be far or short). 10896 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10897 match(CountedLoopEnd cmp crx); 10898 effect(USE labl); 10899 predicate(false /* TODO: PPC port HB_Schedule */); 10900 // Higher cost than `branchCon'. 10901 ins_cost(5*BRANCH_COST); 10902 10903 // Actually size doesn't depend on alignment but on shortening. 10904 ins_variable_size_depending_on_alignment(true); 10905 // Long variant. 10906 ins_short_branch(0); 10907 10908 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10909 size(8); // worst case 10910 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10911 ins_pipe(pipe_class_default); 10912 %} 10913 10914 // ============================================================================ 10915 // Java runtime operations, intrinsics and other complex operations. 10916 10917 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10918 // array for an instance of the superklass. Set a hidden internal cache on a 10919 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10920 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10921 // 10922 // GL TODO: Improve this. 10923 // - result should not be a TEMP 10924 // - Add match rule as on sparc avoiding additional Cmp. 10925 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 10926 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 10927 match(Set result (PartialSubtypeCheck subklass superklass)); 10928 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr); 10929 ins_cost(DEFAULT_COST*10); 10930 10931 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 10932 ins_encode %{ 10933 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10934 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 10935 $tmp_klass$$Register, NULL, $result$$Register); 10936 %} 10937 ins_pipe(pipe_class_default); 10938 %} 10939 10940 // inlined locking and unlocking 10941 10942 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10943 match(Set crx (FastLock oop box)); 10944 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10945 predicate(!Compile::current()->use_rtm()); 10946 10947 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %} 10948 ins_encode %{ 10949 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10950 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10951 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register, 10952 UseBiasedLocking && !UseOptoBiasInlining); // SAPJVM MD 2014-11-06 UseOptoBiasInlining 10953 // If locking was successfull, crx should indicate 'EQ'. 10954 // The compiler generates a branch to the runtime call to 10955 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10956 %} 10957 ins_pipe(pipe_class_compare); 10958 %} 10959 10960 // Separate version for TM. Use bound register for box to enable USE_KILL. 10961 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10962 match(Set crx (FastLock oop box)); 10963 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box); 10964 predicate(Compile::current()->use_rtm()); 10965 10966 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %} 10967 ins_encode %{ 10968 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10969 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10970 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register, 10971 /*Biased Locking*/ false, 10972 _rtm_counters, _stack_rtm_counters, 10973 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), 10974 /*TM*/ true, ra_->C->profile_rtm()); 10975 // If locking was successfull, crx should indicate 'EQ'. 10976 // The compiler generates a branch to the runtime call to 10977 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10978 %} 10979 ins_pipe(pipe_class_compare); 10980 %} 10981 10982 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10983 match(Set crx (FastUnlock oop box)); 10984 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10985 predicate(!Compile::current()->use_rtm()); 10986 10987 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 10988 ins_encode %{ 10989 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10990 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10991 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register, 10992 UseBiasedLocking && !UseOptoBiasInlining, 10993 false); 10994 // If unlocking was successfull, crx should indicate 'EQ'. 10995 // The compiler generates a branch to the runtime call to 10996 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10997 %} 10998 ins_pipe(pipe_class_compare); 10999 %} 11000 11001 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 11002 match(Set crx (FastUnlock oop box)); 11003 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 11004 predicate(Compile::current()->use_rtm()); 11005 11006 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %} 11007 ins_encode %{ 11008 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11009 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 11010 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register, 11011 /*Biased Locking*/ false, /*TM*/ true); 11012 // If unlocking was successfull, crx should indicate 'EQ'. 11013 // The compiler generates a branch to the runtime call to 11014 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 11015 %} 11016 ins_pipe(pipe_class_compare); 11017 %} 11018 11019 // Align address. 11020 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 11021 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 11022 11023 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 11024 size(4); 11025 ins_encode %{ 11026 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 11027 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 11028 %} 11029 ins_pipe(pipe_class_default); 11030 %} 11031 11032 // Array size computation. 11033 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 11034 match(Set dst (SubL (CastP2X end) (CastP2X start))); 11035 11036 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 11037 size(4); 11038 ins_encode %{ 11039 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 11040 __ subf($dst$$Register, $start$$Register, $end$$Register); 11041 %} 11042 ins_pipe(pipe_class_default); 11043 %} 11044 11045 // Clear-array with dynamic array-size. 11046 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 11047 match(Set dummy (ClearArray cnt base)); 11048 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 11049 ins_cost(MEMORY_REF_COST); 11050 11051 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11052 11053 format %{ "ClearArray $cnt, $base" %} 11054 ins_encode %{ 11055 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11056 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 11057 %} 11058 ins_pipe(pipe_class_default); 11059 %} 11060 11061 // String_IndexOf for needle of length 1. 11062 // 11063 // Match needle into immediate operands: no loadConP node needed. Saves one 11064 // register and two instructions over string_indexOf_imm1Node. 11065 // 11066 // Assumes register result differs from all input registers. 11067 // 11068 // Preserves registers haystack, haycnt 11069 // Kills registers tmp1, tmp2 11070 // Defines registers result 11071 // 11072 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11073 // 11074 // Unfortunately this does not match too often. In many situations the AddP is used 11075 // by several nodes, even several StrIndexOf nodes, breaking the match tree. 11076 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11077 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11078 iRegIdst tmp1, iRegIdst tmp2, 11079 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11080 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported 11081 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11082 11083 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); 11084 11085 ins_cost(150); 11086 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11087 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11088 11089 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11090 ins_encode %{ 11091 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11092 immPOper *needleOper = (immPOper *)$needleImm; 11093 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11094 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11095 11096 __ string_indexof_1($result$$Register, 11097 $haystack$$Register, $haycnt$$Register, 11098 R0, needle_values->char_at(0), 11099 $tmp1$$Register, $tmp2$$Register); 11100 %} 11101 ins_pipe(pipe_class_compare); 11102 %} 11103 11104 // String_IndexOf for needle of length 1. 11105 // 11106 // Special case requires less registers and emits less instructions. 11107 // 11108 // Assumes register result differs from all input registers. 11109 // 11110 // Preserves registers haystack, haycnt 11111 // Kills registers tmp1, tmp2, needle 11112 // Defines registers result 11113 // 11114 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11115 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11116 rscratch2RegP needle, immI_1 needlecntImm, 11117 iRegIdst tmp1, iRegIdst tmp2, 11118 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11119 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11120 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result, 11121 TEMP tmp1, TEMP tmp2); 11122 // Required for EA: check if it is still a type_array. 11123 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11124 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11125 ins_cost(180); 11126 11127 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11128 11129 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11130 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11131 ins_encode %{ 11132 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11133 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11134 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11135 guarantee(needle_values, "sanity"); 11136 if (needle_values != NULL) { 11137 __ string_indexof_1($result$$Register, 11138 $haystack$$Register, $haycnt$$Register, 11139 R0, needle_values->char_at(0), 11140 $tmp1$$Register, $tmp2$$Register); 11141 } else { 11142 __ string_indexof_1($result$$Register, 11143 $haystack$$Register, $haycnt$$Register, 11144 $needle$$Register, 0, 11145 $tmp1$$Register, $tmp2$$Register); 11146 } 11147 %} 11148 ins_pipe(pipe_class_compare); 11149 %} 11150 11151 // String_IndexOf. 11152 // 11153 // Length of needle as immediate. This saves instruction loading constant needle 11154 // length. 11155 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11156 // completely or do it in vector instruction. This should save registers for 11157 // needlecnt and needle. 11158 // 11159 // Assumes register result differs from all input registers. 11160 // Overwrites haycnt, needlecnt. 11161 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11162 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11163 iRegPsrc needle, uimmI15 needlecntImm, 11164 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11165 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11166 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11167 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11168 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); 11169 // Required for EA: check if it is still a type_array. 11170 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11171 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11172 ins_cost(250); 11173 11174 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11175 11176 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11177 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11178 ins_encode %{ 11179 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11180 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11181 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11182 11183 __ string_indexof($result$$Register, 11184 $haystack$$Register, $haycnt$$Register, 11185 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11186 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11187 %} 11188 ins_pipe(pipe_class_compare); 11189 %} 11190 11191 // StrIndexOf node. 11192 // 11193 // Assumes register result differs from all input registers. 11194 // Overwrites haycnt, needlecnt. 11195 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11196 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11197 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11198 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11199 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11200 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11201 TEMP_DEF result, 11202 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); 11203 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. 11204 ins_cost(300); 11205 11206 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11207 11208 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11209 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11210 ins_encode %{ 11211 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11212 __ string_indexof($result$$Register, 11213 $haystack$$Register, $haycnt$$Register, 11214 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11215 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11216 %} 11217 ins_pipe(pipe_class_compare); 11218 %} 11219 11220 // String equals with immediate. 11221 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11222 iRegPdst tmp1, iRegPdst tmp2, 11223 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11224 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11225 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, 11226 KILL cr0, KILL cr6, KILL ctr); 11227 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11228 ins_cost(250); 11229 11230 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11231 11232 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11233 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11234 ins_encode %{ 11235 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11236 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11237 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11238 %} 11239 ins_pipe(pipe_class_compare); 11240 %} 11241 11242 // String equals. 11243 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11244 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11245 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11246 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11247 match(Set result (StrEquals (Binary str1 str2) cnt)); 11248 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11249 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11250 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11251 ins_cost(300); 11252 11253 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11254 11255 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11256 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11257 ins_encode %{ 11258 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11259 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11260 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11261 %} 11262 ins_pipe(pipe_class_compare); 11263 %} 11264 11265 // String compare. 11266 // Char[] pointers are passed in. 11267 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11268 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11269 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11270 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11271 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr); 11272 ins_cost(300); 11273 11274 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11275 11276 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11277 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11278 ins_encode %{ 11279 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11280 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11281 $result$$Register, $tmp$$Register); 11282 %} 11283 ins_pipe(pipe_class_compare); 11284 %} 11285 11286 //---------- Min/Max Instructions --------------------------------------------- 11287 11288 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11289 match(Set dst (MinI src1 src2)); 11290 ins_cost(DEFAULT_COST*6); 11291 11292 expand %{ 11293 iRegLdst src1s; 11294 iRegLdst src2s; 11295 iRegLdst diff; 11296 iRegLdst sm; 11297 iRegLdst doz; // difference or zero 11298 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11299 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11300 subL_reg_reg(diff, src2s, src1s); 11301 // Need to consider >=33 bit result, therefore we need signmaskL. 11302 signmask64L_regL(sm, diff); 11303 andL_reg_reg(doz, diff, sm); // <=0 11304 addI_regL_regL(dst, doz, src1s); 11305 %} 11306 %} 11307 11308 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11309 match(Set dst (MaxI src1 src2)); 11310 ins_cost(DEFAULT_COST*6); 11311 11312 expand %{ 11313 iRegLdst src1s; 11314 iRegLdst src2s; 11315 iRegLdst diff; 11316 iRegLdst sm; 11317 iRegLdst doz; // difference or zero 11318 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11319 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11320 subL_reg_reg(diff, src2s, src1s); 11321 // Need to consider >=33 bit result, therefore we need signmaskL. 11322 signmask64L_regL(sm, diff); 11323 andcL_reg_reg(doz, diff, sm); // >=0 11324 addI_regL_regL(dst, doz, src1s); 11325 %} 11326 %} 11327 11328 //---------- Population Count Instructions ------------------------------------ 11329 11330 // Popcnt for Power7. 11331 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11332 match(Set dst (PopCountI src)); 11333 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11334 ins_cost(DEFAULT_COST); 11335 11336 format %{ "POPCNTW $dst, $src" %} 11337 size(4); 11338 ins_encode %{ 11339 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11340 __ popcntw($dst$$Register, $src$$Register); 11341 %} 11342 ins_pipe(pipe_class_default); 11343 %} 11344 11345 // Popcnt for Power7. 11346 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11347 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11348 match(Set dst (PopCountL src)); 11349 ins_cost(DEFAULT_COST); 11350 11351 format %{ "POPCNTD $dst, $src" %} 11352 size(4); 11353 ins_encode %{ 11354 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11355 __ popcntd($dst$$Register, $src$$Register); 11356 %} 11357 ins_pipe(pipe_class_default); 11358 %} 11359 11360 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11361 match(Set dst (CountLeadingZerosI src)); 11362 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11363 ins_cost(DEFAULT_COST); 11364 11365 format %{ "CNTLZW $dst, $src" %} 11366 size(4); 11367 ins_encode %{ 11368 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11369 __ cntlzw($dst$$Register, $src$$Register); 11370 %} 11371 ins_pipe(pipe_class_default); 11372 %} 11373 11374 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11375 match(Set dst (CountLeadingZerosL src)); 11376 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11377 ins_cost(DEFAULT_COST); 11378 11379 format %{ "CNTLZD $dst, $src" %} 11380 size(4); 11381 ins_encode %{ 11382 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11383 __ cntlzd($dst$$Register, $src$$Register); 11384 %} 11385 ins_pipe(pipe_class_default); 11386 %} 11387 11388 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 11389 // no match-rule, false predicate 11390 effect(DEF dst, USE src); 11391 predicate(false); 11392 11393 format %{ "CNTLZD $dst, $src" %} 11394 size(4); 11395 ins_encode %{ 11396 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11397 __ cntlzd($dst$$Register, $src$$Register); 11398 %} 11399 ins_pipe(pipe_class_default); 11400 %} 11401 11402 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 11403 match(Set dst (CountTrailingZerosI src)); 11404 predicate(UseCountLeadingZerosInstructionsPPC64); 11405 ins_cost(DEFAULT_COST); 11406 11407 expand %{ 11408 immI16 imm1 %{ (int)-1 %} 11409 immI16 imm2 %{ (int)32 %} 11410 immI_minus1 m1 %{ -1 %} 11411 iRegIdst tmpI1; 11412 iRegIdst tmpI2; 11413 iRegIdst tmpI3; 11414 addI_reg_imm16(tmpI1, src, imm1); 11415 andcI_reg_reg(tmpI2, src, m1, tmpI1); 11416 countLeadingZerosI(tmpI3, tmpI2); 11417 subI_imm16_reg(dst, imm2, tmpI3); 11418 %} 11419 %} 11420 11421 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 11422 match(Set dst (CountTrailingZerosL src)); 11423 predicate(UseCountLeadingZerosInstructionsPPC64); 11424 ins_cost(DEFAULT_COST); 11425 11426 expand %{ 11427 immL16 imm1 %{ (long)-1 %} 11428 immI16 imm2 %{ (int)64 %} 11429 iRegLdst tmpL1; 11430 iRegLdst tmpL2; 11431 iRegIdst tmpL3; 11432 addL_reg_imm16(tmpL1, src, imm1); 11433 andcL_reg_reg(tmpL2, tmpL1, src); 11434 countLeadingZerosL(tmpL3, tmpL2); 11435 subI_imm16_reg(dst, imm2, tmpL3); 11436 %} 11437 %} 11438 11439 // Expand nodes for byte_reverse_int. 11440 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11441 effect(DEF dst, USE src, USE pos, USE shift); 11442 predicate(false); 11443 11444 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11445 size(4); 11446 ins_encode %{ 11447 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11448 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11449 %} 11450 ins_pipe(pipe_class_default); 11451 %} 11452 11453 // As insrwi_a, but with USE_DEF. 11454 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11455 effect(USE_DEF dst, USE src, USE pos, USE shift); 11456 predicate(false); 11457 11458 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11459 size(4); 11460 ins_encode %{ 11461 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11462 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11463 %} 11464 ins_pipe(pipe_class_default); 11465 %} 11466 11467 // Just slightly faster than java implementation. 11468 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 11469 match(Set dst (ReverseBytesI src)); 11470 predicate(UseCountLeadingZerosInstructionsPPC64); 11471 ins_cost(DEFAULT_COST); 11472 11473 expand %{ 11474 immI16 imm24 %{ (int) 24 %} 11475 immI16 imm16 %{ (int) 16 %} 11476 immI16 imm8 %{ (int) 8 %} 11477 immI16 imm4 %{ (int) 4 %} 11478 immI16 imm0 %{ (int) 0 %} 11479 iRegLdst tmpI1; 11480 iRegLdst tmpI2; 11481 iRegLdst tmpI3; 11482 11483 urShiftI_reg_imm(tmpI1, src, imm24); 11484 insrwi_a(dst, tmpI1, imm24, imm8); 11485 urShiftI_reg_imm(tmpI2, src, imm16); 11486 insrwi(dst, tmpI2, imm8, imm16); 11487 urShiftI_reg_imm(tmpI3, src, imm8); 11488 insrwi(dst, tmpI3, imm8, imm8); 11489 insrwi(dst, src, imm0, imm8); 11490 %} 11491 %} 11492 11493 //---------- Replicate Vector Instructions ------------------------------------ 11494 11495 // Insrdi does replicate if src == dst. 11496 instruct repl32(iRegLdst dst) %{ 11497 predicate(false); 11498 effect(USE_DEF dst); 11499 11500 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 11501 size(4); 11502 ins_encode %{ 11503 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11504 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 11505 %} 11506 ins_pipe(pipe_class_default); 11507 %} 11508 11509 // Insrdi does replicate if src == dst. 11510 instruct repl48(iRegLdst dst) %{ 11511 predicate(false); 11512 effect(USE_DEF dst); 11513 11514 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 11515 size(4); 11516 ins_encode %{ 11517 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11518 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 11519 %} 11520 ins_pipe(pipe_class_default); 11521 %} 11522 11523 // Insrdi does replicate if src == dst. 11524 instruct repl56(iRegLdst dst) %{ 11525 predicate(false); 11526 effect(USE_DEF dst); 11527 11528 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 11529 size(4); 11530 ins_encode %{ 11531 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11532 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 11533 %} 11534 ins_pipe(pipe_class_default); 11535 %} 11536 11537 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11538 match(Set dst (ReplicateB src)); 11539 predicate(n->as_Vector()->length() == 8); 11540 expand %{ 11541 moveReg(dst, src); 11542 repl56(dst); 11543 repl48(dst); 11544 repl32(dst); 11545 %} 11546 %} 11547 11548 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 11549 match(Set dst (ReplicateB zero)); 11550 predicate(n->as_Vector()->length() == 8); 11551 format %{ "LI $dst, #0 \t// replicate8B" %} 11552 size(4); 11553 ins_encode %{ 11554 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11555 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11556 %} 11557 ins_pipe(pipe_class_default); 11558 %} 11559 11560 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11561 match(Set dst (ReplicateB src)); 11562 predicate(n->as_Vector()->length() == 8); 11563 format %{ "LI $dst, #-1 \t// replicate8B" %} 11564 size(4); 11565 ins_encode %{ 11566 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11567 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11568 %} 11569 ins_pipe(pipe_class_default); 11570 %} 11571 11572 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11573 match(Set dst (ReplicateS src)); 11574 predicate(n->as_Vector()->length() == 4); 11575 expand %{ 11576 moveReg(dst, src); 11577 repl48(dst); 11578 repl32(dst); 11579 %} 11580 %} 11581 11582 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 11583 match(Set dst (ReplicateS zero)); 11584 predicate(n->as_Vector()->length() == 4); 11585 format %{ "LI $dst, #0 \t// replicate4C" %} 11586 size(4); 11587 ins_encode %{ 11588 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11589 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11590 %} 11591 ins_pipe(pipe_class_default); 11592 %} 11593 11594 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11595 match(Set dst (ReplicateS src)); 11596 predicate(n->as_Vector()->length() == 4); 11597 format %{ "LI $dst, -1 \t// replicate4C" %} 11598 size(4); 11599 ins_encode %{ 11600 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11601 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11602 %} 11603 ins_pipe(pipe_class_default); 11604 %} 11605 11606 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11607 match(Set dst (ReplicateI src)); 11608 predicate(n->as_Vector()->length() == 2); 11609 ins_cost(2 * DEFAULT_COST); 11610 expand %{ 11611 moveReg(dst, src); 11612 repl32(dst); 11613 %} 11614 %} 11615 11616 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 11617 match(Set dst (ReplicateI zero)); 11618 predicate(n->as_Vector()->length() == 2); 11619 format %{ "LI $dst, #0 \t// replicate4C" %} 11620 size(4); 11621 ins_encode %{ 11622 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11623 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11624 %} 11625 ins_pipe(pipe_class_default); 11626 %} 11627 11628 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11629 match(Set dst (ReplicateI src)); 11630 predicate(n->as_Vector()->length() == 2); 11631 format %{ "LI $dst, -1 \t// replicate4C" %} 11632 size(4); 11633 ins_encode %{ 11634 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11635 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11636 %} 11637 ins_pipe(pipe_class_default); 11638 %} 11639 11640 // Move float to int register via stack, replicate. 11641 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 11642 match(Set dst (ReplicateF src)); 11643 predicate(n->as_Vector()->length() == 2); 11644 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 11645 expand %{ 11646 stackSlotL tmpS; 11647 iRegIdst tmpI; 11648 moveF2I_reg_stack(tmpS, src); // Move float to stack. 11649 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 11650 moveReg(dst, tmpI); // Move int to long reg. 11651 repl32(dst); // Replicate bitpattern. 11652 %} 11653 %} 11654 11655 // Replicate scalar constant to packed float values in Double register 11656 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 11657 match(Set dst (ReplicateF src)); 11658 predicate(n->as_Vector()->length() == 2); 11659 ins_cost(5 * DEFAULT_COST); 11660 11661 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 11662 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 11663 %} 11664 11665 // Replicate scalar zero constant to packed float values in Double register 11666 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 11667 match(Set dst (ReplicateF zero)); 11668 predicate(n->as_Vector()->length() == 2); 11669 11670 format %{ "LI $dst, #0 \t// replicate2F" %} 11671 ins_encode %{ 11672 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11673 __ li($dst$$Register, 0x0); 11674 %} 11675 ins_pipe(pipe_class_default); 11676 %} 11677 11678 11679 //----------Overflow Math Instructions----------------------------------------- 11680 11681 // Note that we have to make sure that XER.SO is reset before using overflow instructions. 11682 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc). 11683 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.) 11684 11685 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11686 match(Set cr0 (OverflowAddL op1 op2)); 11687 11688 format %{ "add_ $op1, $op2\t# overflow check long" %} 11689 ins_encode %{ 11690 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11691 __ li(R0, 0); 11692 __ mtxer(R0); // clear XER.SO 11693 __ addo_(R0, $op1$$Register, $op2$$Register); 11694 %} 11695 ins_pipe(pipe_class_default); 11696 %} 11697 11698 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11699 match(Set cr0 (OverflowSubL op1 op2)); 11700 11701 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %} 11702 ins_encode %{ 11703 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11704 __ li(R0, 0); 11705 __ mtxer(R0); // clear XER.SO 11706 __ subfo_(R0, $op2$$Register, $op1$$Register); 11707 %} 11708 ins_pipe(pipe_class_default); 11709 %} 11710 11711 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{ 11712 match(Set cr0 (OverflowSubL zero op2)); 11713 11714 format %{ "nego_ R0, $op2\t# overflow check long" %} 11715 ins_encode %{ 11716 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11717 __ li(R0, 0); 11718 __ mtxer(R0); // clear XER.SO 11719 __ nego_(R0, $op2$$Register); 11720 %} 11721 ins_pipe(pipe_class_default); 11722 %} 11723 11724 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11725 match(Set cr0 (OverflowMulL op1 op2)); 11726 11727 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %} 11728 ins_encode %{ 11729 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11730 __ li(R0, 0); 11731 __ mtxer(R0); // clear XER.SO 11732 __ mulldo_(R0, $op1$$Register, $op2$$Register); 11733 %} 11734 ins_pipe(pipe_class_default); 11735 %} 11736 11737 11738 // ============================================================================ 11739 // Safepoint Instruction 11740 11741 instruct safePoint_poll(iRegPdst poll) %{ 11742 match(SafePoint poll); 11743 predicate(LoadPollAddressFromThread); 11744 11745 // It caused problems to add the effect that r0 is killed, but this 11746 // effect no longer needs to be mentioned, since r0 is not contained 11747 // in a reg_class. 11748 11749 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 11750 size(4); 11751 ins_encode( enc_poll(0x0, poll) ); 11752 ins_pipe(pipe_class_default); 11753 %} 11754 11755 // Safepoint without per-thread support. Load address of page to poll 11756 // as constant. 11757 // Rscratch2RegP is R12. 11758 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be 11759 // a seperate node so that the oop map is at the right location. 11760 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 11761 match(SafePoint poll); 11762 predicate(!LoadPollAddressFromThread); 11763 11764 // It caused problems to add the effect that r0 is killed, but this 11765 // effect no longer needs to be mentioned, since r0 is not contained 11766 // in a reg_class. 11767 11768 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 11769 ins_encode( enc_poll(0x0, poll) ); 11770 ins_pipe(pipe_class_default); 11771 %} 11772 11773 // ============================================================================ 11774 // Call Instructions 11775 11776 // Call Java Static Instruction 11777 11778 // Schedulable version of call static node. 11779 instruct CallStaticJavaDirect(method meth) %{ 11780 match(CallStaticJava); 11781 effect(USE meth); 11782 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11783 ins_cost(CALL_COST); 11784 11785 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11786 11787 format %{ "CALL,static $meth \t// ==> " %} 11788 size(4); 11789 ins_encode( enc_java_static_call(meth) ); 11790 ins_pipe(pipe_class_call); 11791 %} 11792 11793 // Schedulable version of call static node. 11794 instruct CallStaticJavaDirectHandle(method meth) %{ 11795 match(CallStaticJava); 11796 effect(USE meth); 11797 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11798 ins_cost(CALL_COST); 11799 11800 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11801 11802 format %{ "CALL,static $meth \t// ==> " %} 11803 ins_encode( enc_java_handle_call(meth) ); 11804 ins_pipe(pipe_class_call); 11805 %} 11806 11807 // Call Java Dynamic Instruction 11808 11809 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 11810 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable 11811 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 11812 // The call destination must still be placed in the constant pool. 11813 instruct CallDynamicJavaDirectSched(method meth) %{ 11814 match(CallDynamicJava); // To get all the data fields we need ... 11815 effect(USE meth); 11816 predicate(false); // ... but never match. 11817 11818 ins_field_load_ic_hi_node(loadConL_hiNode*); 11819 ins_field_load_ic_node(loadConLNode*); 11820 ins_num_consts(1 /* 1 patchable constant: call destination */); 11821 11822 format %{ "BL \t// dynamic $meth ==> " %} 11823 size(4); 11824 ins_encode( enc_java_dynamic_call_sched(meth) ); 11825 ins_pipe(pipe_class_call); 11826 %} 11827 11828 // Schedulable (i.e. postalloc expanded) version of call dynamic java. 11829 // We use postalloc expanded calls if we use inline caches 11830 // and do not update method data. 11831 // 11832 // This instruction has two constants: inline cache (IC) and call destination. 11833 // Loading the inline cache will be postalloc expanded, thus leaving a call with 11834 // one constant. 11835 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 11836 match(CallDynamicJava); 11837 effect(USE meth); 11838 predicate(UseInlineCaches); 11839 ins_cost(CALL_COST); 11840 11841 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 11842 11843 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 11844 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 11845 %} 11846 11847 // Compound version of call dynamic java 11848 // We use postalloc expanded calls if we use inline caches 11849 // and do not update method data. 11850 instruct CallDynamicJavaDirect(method meth) %{ 11851 match(CallDynamicJava); 11852 effect(USE meth); 11853 predicate(!UseInlineCaches); 11854 ins_cost(CALL_COST); 11855 11856 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 11857 ins_num_consts(4); 11858 11859 format %{ "CALL,dynamic $meth \t// ==> " %} 11860 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 11861 ins_pipe(pipe_class_call); 11862 %} 11863 11864 // Call Runtime Instruction 11865 11866 instruct CallRuntimeDirect(method meth) %{ 11867 match(CallRuntime); 11868 effect(USE meth); 11869 ins_cost(CALL_COST); 11870 11871 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11872 // env for callee, C-toc. 11873 ins_num_consts(3); 11874 11875 format %{ "CALL,runtime" %} 11876 ins_encode( enc_java_to_runtime_call(meth) ); 11877 ins_pipe(pipe_class_call); 11878 %} 11879 11880 // Call Leaf 11881 11882 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). 11883 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 11884 effect(DEF dst, USE src); 11885 11886 ins_num_consts(1); 11887 11888 format %{ "MTCTR $src" %} 11889 size(4); 11890 ins_encode( enc_leaf_call_mtctr(src) ); 11891 ins_pipe(pipe_class_default); 11892 %} 11893 11894 // Used by postalloc expand of CallLeafDirect_Ex (actual call). 11895 instruct CallLeafDirect(method meth) %{ 11896 match(CallLeaf); // To get the data all the data fields we need ... 11897 effect(USE meth); 11898 predicate(false); // but never match. 11899 11900 format %{ "BCTRL \t// leaf call $meth ==> " %} 11901 size(4); 11902 ins_encode %{ 11903 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 11904 __ bctrl(); 11905 %} 11906 ins_pipe(pipe_class_call); 11907 %} 11908 11909 // postalloc expand of CallLeafDirect. 11910 // Load adress to call from TOC, then bl to it. 11911 instruct CallLeafDirect_Ex(method meth) %{ 11912 match(CallLeaf); 11913 effect(USE meth); 11914 ins_cost(CALL_COST); 11915 11916 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 11917 // env for callee, C-toc. 11918 ins_num_consts(3); 11919 11920 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 11921 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11922 %} 11923 11924 // Call runtime without safepoint - same as CallLeaf. 11925 // postalloc expand of CallLeafNoFPDirect. 11926 // Load adress to call from TOC, then bl to it. 11927 instruct CallLeafNoFPDirect_Ex(method meth) %{ 11928 match(CallLeafNoFP); 11929 effect(USE meth); 11930 ins_cost(CALL_COST); 11931 11932 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11933 // env for callee, C-toc. 11934 ins_num_consts(3); 11935 11936 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 11937 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11938 %} 11939 11940 // Tail Call; Jump from runtime stub to Java code. 11941 // Also known as an 'interprocedural jump'. 11942 // Target of jump will eventually return to caller. 11943 // TailJump below removes the return address. 11944 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 11945 match(TailCall jump_target method_oop); 11946 ins_cost(CALL_COST); 11947 11948 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 11949 "BCTR \t// tail call" %} 11950 size(8); 11951 ins_encode %{ 11952 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11953 __ mtctr($jump_target$$Register); 11954 __ bctr(); 11955 %} 11956 ins_pipe(pipe_class_call); 11957 %} 11958 11959 // Return Instruction 11960 instruct Ret() %{ 11961 match(Return); 11962 format %{ "BLR \t// branch to link register" %} 11963 size(4); 11964 ins_encode %{ 11965 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 11966 // LR is restored in MachEpilogNode. Just do the RET here. 11967 __ blr(); 11968 %} 11969 ins_pipe(pipe_class_default); 11970 %} 11971 11972 // Tail Jump; remove the return address; jump to target. 11973 // TailCall above leaves the return address around. 11974 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 11975 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 11976 // "restore" before this instruction (in Epilogue), we need to materialize it 11977 // in %i0. 11978 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 11979 match(TailJump jump_target ex_oop); 11980 ins_cost(CALL_COST); 11981 11982 format %{ "LD R4_ARG2 = LR\n\t" 11983 "MTCTR $jump_target\n\t" 11984 "BCTR \t// TailJump, exception oop: $ex_oop" %} 11985 size(12); 11986 ins_encode %{ 11987 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11988 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 11989 __ mtctr($jump_target$$Register); 11990 __ bctr(); 11991 %} 11992 ins_pipe(pipe_class_call); 11993 %} 11994 11995 // Create exception oop: created by stack-crawling runtime code. 11996 // Created exception is now available to this handler, and is setup 11997 // just prior to jumping to this handler. No code emitted. 11998 instruct CreateException(rarg1RegP ex_oop) %{ 11999 match(Set ex_oop (CreateEx)); 12000 ins_cost(0); 12001 12002 format %{ " -- \t// exception oop; no code emitted" %} 12003 size(0); 12004 ins_encode( /*empty*/ ); 12005 ins_pipe(pipe_class_default); 12006 %} 12007 12008 // Rethrow exception: The exception oop will come in the first 12009 // argument position. Then JUMP (not call) to the rethrow stub code. 12010 instruct RethrowException() %{ 12011 match(Rethrow); 12012 ins_cost(CALL_COST); 12013 12014 format %{ "Jmp rethrow_stub" %} 12015 ins_encode %{ 12016 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12017 cbuf.set_insts_mark(); 12018 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 12019 %} 12020 ins_pipe(pipe_class_call); 12021 %} 12022 12023 // Die now. 12024 instruct ShouldNotReachHere() %{ 12025 match(Halt); 12026 ins_cost(CALL_COST); 12027 12028 format %{ "ShouldNotReachHere" %} 12029 size(4); 12030 ins_encode %{ 12031 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 12032 __ trap_should_not_reach_here(); 12033 %} 12034 ins_pipe(pipe_class_default); 12035 %} 12036 12037 // This name is KNOWN by the ADLC and cannot be changed. The ADLC 12038 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. 12039 // Get a DEF on threadRegP, no costs, no encoding, use 12040 // 'ins_should_rematerialize(true)' to avoid spilling. 12041 instruct tlsLoadP(threadRegP dst) %{ 12042 match(Set dst (ThreadLocal)); 12043 ins_cost(0); 12044 12045 ins_should_rematerialize(true); 12046 12047 format %{ " -- \t// $dst=Thread::current(), empty" %} 12048 size(0); 12049 ins_encode( /*empty*/ ); 12050 ins_pipe(pipe_class_empty); 12051 %} 12052 12053 //---Some PPC specific nodes--------------------------------------------------- 12054 12055 // Stop a group. 12056 instruct endGroup() %{ 12057 ins_cost(0); 12058 12059 ins_is_nop(true); 12060 12061 format %{ "End Bundle (ori r1, r1, 0)" %} 12062 size(4); 12063 ins_encode %{ 12064 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 12065 __ endgroup(); 12066 %} 12067 ins_pipe(pipe_class_default); 12068 %} 12069 12070 // Nop instructions 12071 12072 instruct fxNop() %{ 12073 ins_cost(0); 12074 12075 ins_is_nop(true); 12076 12077 format %{ "fxNop" %} 12078 size(4); 12079 ins_encode %{ 12080 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12081 __ nop(); 12082 %} 12083 ins_pipe(pipe_class_default); 12084 %} 12085 12086 instruct fpNop0() %{ 12087 ins_cost(0); 12088 12089 ins_is_nop(true); 12090 12091 format %{ "fpNop0" %} 12092 size(4); 12093 ins_encode %{ 12094 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12095 __ fpnop0(); 12096 %} 12097 ins_pipe(pipe_class_default); 12098 %} 12099 12100 instruct fpNop1() %{ 12101 ins_cost(0); 12102 12103 ins_is_nop(true); 12104 12105 format %{ "fpNop1" %} 12106 size(4); 12107 ins_encode %{ 12108 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12109 __ fpnop1(); 12110 %} 12111 ins_pipe(pipe_class_default); 12112 %} 12113 12114 instruct brNop0() %{ 12115 ins_cost(0); 12116 size(4); 12117 format %{ "brNop0" %} 12118 ins_encode %{ 12119 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12120 __ brnop0(); 12121 %} 12122 ins_is_nop(true); 12123 ins_pipe(pipe_class_default); 12124 %} 12125 12126 instruct brNop1() %{ 12127 ins_cost(0); 12128 12129 ins_is_nop(true); 12130 12131 format %{ "brNop1" %} 12132 size(4); 12133 ins_encode %{ 12134 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12135 __ brnop1(); 12136 %} 12137 ins_pipe(pipe_class_default); 12138 %} 12139 12140 instruct brNop2() %{ 12141 ins_cost(0); 12142 12143 ins_is_nop(true); 12144 12145 format %{ "brNop2" %} 12146 size(4); 12147 ins_encode %{ 12148 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12149 __ brnop2(); 12150 %} 12151 ins_pipe(pipe_class_default); 12152 %} 12153 12154 //----------PEEPHOLE RULES----------------------------------------------------- 12155 // These must follow all instruction definitions as they use the names 12156 // defined in the instructions definitions. 12157 // 12158 // peepmatch ( root_instr_name [preceeding_instruction]* ); 12159 // 12160 // peepconstraint %{ 12161 // (instruction_number.operand_name relational_op instruction_number.operand_name 12162 // [, ...] ); 12163 // // instruction numbers are zero-based using left to right order in peepmatch 12164 // 12165 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12166 // // provide an instruction_number.operand_name for each operand that appears 12167 // // in the replacement instruction's match rule 12168 // 12169 // ---------VM FLAGS--------------------------------------------------------- 12170 // 12171 // All peephole optimizations can be turned off using -XX:-OptoPeephole 12172 // 12173 // Each peephole rule is given an identifying number starting with zero and 12174 // increasing by one in the order seen by the parser. An individual peephole 12175 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12176 // on the command-line. 12177 // 12178 // ---------CURRENT LIMITATIONS---------------------------------------------- 12179 // 12180 // Only match adjacent instructions in same basic block 12181 // Only equality constraints 12182 // Only constraints between operands, not (0.dest_reg == EAX_enc) 12183 // Only one replacement instruction 12184 // 12185 // ---------EXAMPLE---------------------------------------------------------- 12186 // 12187 // // pertinent parts of existing instructions in architecture description 12188 // instruct movI(eRegI dst, eRegI src) %{ 12189 // match(Set dst (CopyI src)); 12190 // %} 12191 // 12192 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12193 // match(Set dst (AddI dst src)); 12194 // effect(KILL cr); 12195 // %} 12196 // 12197 // // Change (inc mov) to lea 12198 // peephole %{ 12199 // // increment preceeded by register-register move 12200 // peepmatch ( incI_eReg movI ); 12201 // // require that the destination register of the increment 12202 // // match the destination register of the move 12203 // peepconstraint ( 0.dst == 1.dst ); 12204 // // construct a replacement instruction that sets 12205 // // the destination to ( move's source register + one ) 12206 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12207 // %} 12208 // 12209 // Implementation no longer uses movX instructions since 12210 // machine-independent system no longer uses CopyX nodes. 12211 // 12212 // peephole %{ 12213 // peepmatch ( incI_eReg movI ); 12214 // peepconstraint ( 0.dst == 1.dst ); 12215 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12216 // %} 12217 // 12218 // peephole %{ 12219 // peepmatch ( decI_eReg movI ); 12220 // peepconstraint ( 0.dst == 1.dst ); 12221 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12222 // %} 12223 // 12224 // peephole %{ 12225 // peepmatch ( addI_eReg_imm movI ); 12226 // peepconstraint ( 0.dst == 1.dst ); 12227 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12228 // %} 12229 // 12230 // peephole %{ 12231 // peepmatch ( addP_eReg_imm movP ); 12232 // peepconstraint ( 0.dst == 1.dst ); 12233 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12234 // %} 12235 12236 // // Change load of spilled value to only a spill 12237 // instruct storeI(memory mem, eRegI src) %{ 12238 // match(Set mem (StoreI mem src)); 12239 // %} 12240 // 12241 // instruct loadI(eRegI dst, memory mem) %{ 12242 // match(Set dst (LoadI mem)); 12243 // %} 12244 // 12245 peephole %{ 12246 peepmatch ( loadI storeI ); 12247 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12248 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12249 %} 12250 12251 peephole %{ 12252 peepmatch ( loadL storeL ); 12253 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12254 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12255 %} 12256 12257 peephole %{ 12258 peepmatch ( loadP storeP ); 12259 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12260 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12261 %} 12262 12263 //----------SMARTSPILL RULES--------------------------------------------------- 12264 // These must follow all instruction definitions as they use the names 12265 // defined in the instructions definitions.