src/cpu/sparc/vm/assembler_sparc.hpp

*** 122,131 ****
--- 122,133 ----
      fpop1_op3    = 0x34,
      fpop2_op3    = 0x35,
      impdep1_op3  = 0x36,
      aes3_op3     = 0x36,
      sha_op3      = 0x36,
+     bmask_op3    = 0x36,
+     bshuffle_op3   = 0x36,
      alignaddr_op3  = 0x36,
      faligndata_op3 = 0x36,
      flog3_op3    = 0x36,
      edge_op3     = 0x36,
      fzero_op3    = 0x36,
*** 192,211 ****
--- 194,215 ----
  
      fnegs_opf          = 0x05,
      fnegd_opf          = 0x06,
  
      alignaddr_opf      = 0x18,
+     bmask_opf          = 0x19,
  
      fadds_opf          = 0x41,
      faddd_opf          = 0x42,
      fsubs_opf          = 0x45,
      fsubd_opf          = 0x46,
  
      faligndata_opf     = 0x48,
  
      fmuls_opf          = 0x49,
      fmuld_opf          = 0x4a,
+     bshuffle_opf       = 0x4c,
      fdivs_opf          = 0x4d,
      fdivd_opf          = 0x4e,
  
      fcmps_opf          = 0x51,
      fcmpd_opf          = 0x52,
*** 1224,1233 ****
--- 1228,1240 ----
  
    //  VIS2 instructions
  
    void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
  
+   void bmask( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); }
+   void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis2_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); }
+ 
    // VIS3 instructions
  
    void movstosw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
    void movstouw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
    void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }