1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableModRefBS.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 #define __ _masm->
41
42
43 //------------------------------------------------------------
44
45
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
47 if (opr->is_constant()) {
48 LIR_Const* constant = opr->as_constant_ptr();
49 switch (constant->type()) {
50 case T_INT: {
51 jint value = constant->as_jint();
52 return Assembler::is_simm13(value);
53 }
54
55 default:
56 return false;
57 }
58 }
59 return false;
60 }
61
62
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
64 switch (op->code()) {
65 case lir_null_check:
66 return true;
67
68
69 case lir_add:
70 case lir_ushr:
71 case lir_shr:
72 case lir_shl:
73 // integer shifts and adds are always one instruction
74 return op->result_opr()->is_single_cpu();
75
76
77 case lir_move: {
78 LIR_Op1* op1 = op->as_Op1();
79 LIR_Opr src = op1->in_opr();
80 LIR_Opr dst = op1->result_opr();
81
82 if (src == dst) {
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (UseCompressedOops) {
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
106 }
107
108 if (UseCompressedClassPointers) {
109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
111 }
112
113 if (dst->is_register()) {
114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
115 return !PatchALot;
116 } else if (src->is_single_stack()) {
117 return true;
118 }
119 }
120
121 if (src->is_register()) {
122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
123 return !PatchALot;
124 } else if (dst->is_single_stack()) {
125 return true;
126 }
127 }
128
129 if (dst->is_register() &&
130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
132 return true;
133 }
134
135 return false;
136 }
137
138 default:
139 return false;
140 }
141 ShouldNotReachHere();
142 }
143
144
145 LIR_Opr LIR_Assembler::receiverOpr() {
146 return FrameMap::O0_oop_opr;
147 }
148
149
150 LIR_Opr LIR_Assembler::osrBufferPointer() {
151 return FrameMap::I0_opr;
152 }
153
154
155 int LIR_Assembler::initial_frame_size_in_bytes() const {
156 return in_bytes(frame_map()->framesize_in_bytes());
157 }
158
159
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
161 // we fetch the class of the receiver (O0) and compare it with the cached class.
162 // If they do not match we jump to slow case.
163 int LIR_Assembler::check_icache() {
164 int offset = __ offset();
165 __ inline_cache_check(O0, G5_inline_cache_reg);
166 return offset;
167 }
168
169
170 void LIR_Assembler::osr_entry() {
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
172 //
173 // 1. Create a new compiled activation.
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
175 // at the osr_bci; it is not initialized.
176 // 3. Jump to the continuation address in compiled code to resume execution.
177
178 // OSR entry point
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
181 ValueStack* entry_state = osr_entry->end()->state();
182 int number_of_locks = entry_state->locks_size();
183
184 // Create a frame for the compiled activation.
185 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
186
187 // OSR buffer is
188 //
189 // locals[nlocals-1..0]
190 // monitors[number_of_locks-1..0]
191 //
192 // locals is a direct copy of the interpreter frame so in the osr buffer
193 // so first slot in the local array is the last local from the interpreter
194 // and last slot is local[0] (receiver) from the interpreter
195 //
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
198 // in the interpreter frame (the method lock if a sync method)
199
200 // Initialize monitors in the compiled activation.
201 // I0: pointer to osr buffer
202 //
203 // All other registers are dead at this point and the locals will be
204 // copied into place by code emitted in the IR.
205
206 Register OSR_buf = osrBufferPointer()->as_register();
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
208 int monitor_offset = BytesPerWord * method()->max_locals() +
209 (2 * BytesPerWord) * (number_of_locks - 1);
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
211 // the OSR buffer using 2 word entries: first the lock and then
212 // the oop.
213 for (int i = 0; i < number_of_locks; i++) {
214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
215 #ifdef ASSERT
216 // verify the interpreter's monitor has a non-null object
217 {
218 Label L;
219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
221 __ stop("locked object is NULL");
222 __ bind(L);
223 }
224 #endif // ASSERT
225 // Copy the lock field into the compiled activation.
226 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
230 }
231 }
232 }
233
234
235 // --------------------------------------------------------------------------------------------
236
237 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
238 if (!GenerateSynchronizationCode) return;
239
240 Register obj_reg = obj_opr->as_register();
241 Register lock_reg = lock_opr->as_register();
242
243 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
244 Register reg = mon_addr.base();
245 int offset = mon_addr.disp();
246 // compute pointer to BasicLock
247 if (mon_addr.is_simm13()) {
248 __ add(reg, offset, lock_reg);
249 }
250 else {
251 __ set(offset, lock_reg);
252 __ add(reg, lock_reg, lock_reg);
253 }
254 // unlock object
255 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
256 // _slow_case_stubs->append(slow_case);
257 // temporary fix: must be created after exceptionhandler, therefore as call stub
258 _slow_case_stubs->append(slow_case);
259 if (UseFastLocking) {
260 // try inlined fast unlocking first, revert to slow locking if it fails
261 // note: lock_reg points to the displaced header since the displaced header offset is 0!
262 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
263 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
264 } else {
265 // always do slow unlocking
266 // note: the slow unlocking code could be inlined here, however if we use
267 // slow unlocking, speed doesn't matter anyway and this solution is
268 // simpler and requires less duplicated code - additionally, the
269 // slow unlocking code is the same in either case which simplifies
270 // debugging
271 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
272 __ delayed()->nop();
273 }
274 // done
275 __ bind(*slow_case->continuation());
276 }
277
278
279 int LIR_Assembler::emit_exception_handler() {
280 // if the last instruction is a call (typically to do a throw which
281 // is coming at the end after block reordering) the return address
282 // must still point into the code area in order to avoid assertion
283 // failures when searching for the corresponding bci => add a nop
284 // (was bug 5/14/1999 - gri)
285 __ nop();
286
287 // generate code for exception handler
288 ciMethod* method = compilation()->method();
289
290 address handler_base = __ start_a_stub(exception_handler_size);
291
292 if (handler_base == NULL) {
293 // not enough space left for the handler
294 bailout("exception handler overflow");
295 return -1;
296 }
297
298 int offset = code_offset();
299
300 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
301 __ delayed()->nop();
302 __ should_not_reach_here();
303 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
304 __ end_a_stub();
305
306 return offset;
307 }
308
309
310 // Emit the code to remove the frame from the stack in the exception
311 // unwind path.
312 int LIR_Assembler::emit_unwind_handler() {
313 #ifndef PRODUCT
314 if (CommentedAssembly) {
315 _masm->block_comment("Unwind handler");
316 }
317 #endif
318
319 int offset = code_offset();
320
321 // Fetch the exception from TLS and clear out exception related thread state
322 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
323 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
324 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
325
326 __ bind(_unwind_handler_entry);
327 __ verify_not_null_oop(O0);
328 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
329 __ mov(O0, I0); // Preserve the exception
330 }
331
332 // Preform needed unlocking
333 MonitorExitStub* stub = NULL;
334 if (method()->is_synchronized()) {
335 monitor_address(0, FrameMap::I1_opr);
336 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
337 __ unlock_object(I3, I2, I1, *stub->entry());
338 __ bind(*stub->continuation());
339 }
340
341 if (compilation()->env()->dtrace_method_probes()) {
342 __ mov(G2_thread, O0);
343 __ save_thread(I1); // need to preserve thread in G2 across
344 // runtime call
345 metadata2reg(method()->constant_encoding(), O1);
346 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
347 __ delayed()->nop();
348 __ restore_thread(I1);
349 }
350
351 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
352 __ mov(I0, O0); // Restore the exception
353 }
354
355 // dispatch to the unwind logic
356 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
357 __ delayed()->nop();
358
359 // Emit the slow path assembly
360 if (stub != NULL) {
361 stub->emit_code(this);
362 }
363
364 return offset;
365 }
366
367
368 int LIR_Assembler::emit_deopt_handler() {
369 // if the last instruction is a call (typically to do a throw which
370 // is coming at the end after block reordering) the return address
371 // must still point into the code area in order to avoid assertion
372 // failures when searching for the corresponding bci => add a nop
373 // (was bug 5/14/1999 - gri)
374 __ nop();
375
376 // generate code for deopt handler
377 ciMethod* method = compilation()->method();
378 address handler_base = __ start_a_stub(deopt_handler_size);
379 if (handler_base == NULL) {
380 // not enough space left for the handler
381 bailout("deopt handler overflow");
382 return -1;
383 }
384
385 int offset = code_offset();
386 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
387 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
388 __ delayed()->nop();
389 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
390 __ end_a_stub();
391
392 return offset;
393 }
394
395
396 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
397 if (o == NULL) {
398 __ set(NULL_WORD, reg);
399 } else {
400 int oop_index = __ oop_recorder()->find_index(o);
401 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
402 RelocationHolder rspec = oop_Relocation::spec(oop_index);
403 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
404 }
405 }
406
407
408 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
409 // Allocate a new index in table to hold the object once it's been patched
410 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
411 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
412
413 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
414 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
415 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
416 // NULL will be dynamically patched later and the patched value may be large. We must
417 // therefore generate the sethi/add as a placeholders
418 __ patchable_set(addrlit, reg);
419
420 patching_epilog(patch, lir_patch_normal, reg, info);
421 }
422
423
424 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
425 __ set_metadata_constant(o, reg);
426 }
427
428 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
429 // Allocate a new index in table to hold the klass once it's been patched
430 int index = __ oop_recorder()->allocate_metadata_index(NULL);
431 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
432 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
433 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
434 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
435 // NULL will be dynamically patched later and the patched value may be large. We must
436 // therefore generate the sethi/add as a placeholders
437 __ patchable_set(addrlit, reg);
438
439 patching_epilog(patch, lir_patch_normal, reg, info);
440 }
441
442 void LIR_Assembler::emit_op3(LIR_Op3* op) {
443 Register Rdividend = op->in_opr1()->as_register();
444 Register Rdivisor = noreg;
445 Register Rscratch = op->in_opr3()->as_register();
446 Register Rresult = op->result_opr()->as_register();
447 int divisor = -1;
448
449 if (op->in_opr2()->is_register()) {
450 Rdivisor = op->in_opr2()->as_register();
451 } else {
452 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
453 assert(Assembler::is_simm13(divisor), "can only handle simm13");
454 }
455
456 assert(Rdividend != Rscratch, "");
457 assert(Rdivisor != Rscratch, "");
458 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
459
460 if (Rdivisor == noreg && is_power_of_2(divisor)) {
461 // convert division by a power of two into some shifts and logical operations
462 if (op->code() == lir_idiv) {
463 if (divisor == 2) {
464 __ srl(Rdividend, 31, Rscratch);
465 } else {
466 __ sra(Rdividend, 31, Rscratch);
467 __ and3(Rscratch, divisor - 1, Rscratch);
468 }
469 __ add(Rdividend, Rscratch, Rscratch);
470 __ sra(Rscratch, log2_intptr(divisor), Rresult);
471 return;
472 } else {
473 if (divisor == 2) {
474 __ srl(Rdividend, 31, Rscratch);
475 } else {
476 __ sra(Rdividend, 31, Rscratch);
477 __ and3(Rscratch, divisor - 1,Rscratch);
478 }
479 __ add(Rdividend, Rscratch, Rscratch);
480 __ andn(Rscratch, divisor - 1,Rscratch);
481 __ sub(Rdividend, Rscratch, Rresult);
482 return;
483 }
484 }
485
486 __ sra(Rdividend, 31, Rscratch);
487 __ wry(Rscratch);
488
489 add_debug_info_for_div0_here(op->info());
490
491 if (Rdivisor != noreg) {
492 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
493 } else {
494 assert(Assembler::is_simm13(divisor), "can only handle simm13");
495 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
496 }
497
498 Label skip;
499 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
500 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
501 __ bind(skip);
502
503 if (op->code() == lir_irem) {
504 if (Rdivisor != noreg) {
505 __ smul(Rscratch, Rdivisor, Rscratch);
506 } else {
507 __ smul(Rscratch, divisor, Rscratch);
508 }
509 __ sub(Rdividend, Rscratch, Rresult);
510 }
511 }
512
513
514 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
515 #ifdef ASSERT
516 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
517 if (op->block() != NULL) _branch_target_blocks.append(op->block());
518 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
519 #endif
520 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
521
522 if (op->cond() == lir_cond_always) {
523 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
524 } else if (op->code() == lir_cond_float_branch) {
525 assert(op->ublock() != NULL, "must have unordered successor");
526 bool is_unordered = (op->ublock() == op->block());
527 Assembler::Condition acond;
528 switch (op->cond()) {
529 case lir_cond_equal: acond = Assembler::f_equal; break;
530 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
531 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
532 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
533 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
534 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
535 default : ShouldNotReachHere();
536 }
537 __ fb( acond, false, Assembler::pn, *(op->label()));
538 } else {
539 assert (op->code() == lir_branch, "just checking");
540
541 Assembler::Condition acond;
542 switch (op->cond()) {
543 case lir_cond_equal: acond = Assembler::equal; break;
544 case lir_cond_notEqual: acond = Assembler::notEqual; break;
545 case lir_cond_less: acond = Assembler::less; break;
546 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
547 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
548 case lir_cond_greater: acond = Assembler::greater; break;
549 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
550 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
551 default: ShouldNotReachHere();
552 };
553
554 // sparc has different condition codes for testing 32-bit
555 // vs. 64-bit values. We could always test xcc is we could
556 // guarantee that 32-bit loads always sign extended but that isn't
557 // true and since sign extension isn't free, it would impose a
558 // slight cost.
559 #ifdef _LP64
560 if (op->type() == T_INT) {
561 __ br(acond, false, Assembler::pn, *(op->label()));
562 } else
563 #endif
564 __ brx(acond, false, Assembler::pn, *(op->label()));
565 }
566 // The peephole pass fills the delay slot
567 }
568
569
570 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
571 Bytecodes::Code code = op->bytecode();
572 LIR_Opr dst = op->result_opr();
573
574 switch(code) {
575 case Bytecodes::_i2l: {
576 Register rlo = dst->as_register_lo();
577 Register rhi = dst->as_register_hi();
578 Register rval = op->in_opr()->as_register();
579 #ifdef _LP64
580 __ sra(rval, 0, rlo);
581 #else
582 __ mov(rval, rlo);
583 __ sra(rval, BitsPerInt-1, rhi);
584 #endif
585 break;
586 }
587 case Bytecodes::_i2d:
588 case Bytecodes::_i2f: {
589 bool is_double = (code == Bytecodes::_i2d);
590 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
591 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
592 FloatRegister rsrc = op->in_opr()->as_float_reg();
593 if (rsrc != rdst) {
594 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
595 }
596 __ fitof(w, rdst, rdst);
597 break;
598 }
599 case Bytecodes::_f2i:{
600 FloatRegister rsrc = op->in_opr()->as_float_reg();
601 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
602 Label L;
603 // result must be 0 if value is NaN; test by comparing value to itself
604 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
605 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
606 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
607 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
608 // move integer result from float register to int register
609 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
610 __ bind (L);
611 break;
612 }
613 case Bytecodes::_l2i: {
614 Register rlo = op->in_opr()->as_register_lo();
615 Register rhi = op->in_opr()->as_register_hi();
616 Register rdst = dst->as_register();
617 #ifdef _LP64
618 __ sra(rlo, 0, rdst);
619 #else
620 __ mov(rlo, rdst);
621 #endif
622 break;
623 }
624 case Bytecodes::_d2f:
625 case Bytecodes::_f2d: {
626 bool is_double = (code == Bytecodes::_f2d);
627 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
628 LIR_Opr val = op->in_opr();
629 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
630 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
631 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
632 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
633 __ ftof(vw, dw, rval, rdst);
634 break;
635 }
636 case Bytecodes::_i2s:
637 case Bytecodes::_i2b: {
638 Register rval = op->in_opr()->as_register();
639 Register rdst = dst->as_register();
640 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
641 __ sll (rval, shift, rdst);
642 __ sra (rdst, shift, rdst);
643 break;
644 }
645 case Bytecodes::_i2c: {
646 Register rval = op->in_opr()->as_register();
647 Register rdst = dst->as_register();
648 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
649 __ sll (rval, shift, rdst);
650 __ srl (rdst, shift, rdst);
651 break;
652 }
653
654 default: ShouldNotReachHere();
655 }
656 }
657
658
659 void LIR_Assembler::align_call(LIR_Code) {
660 // do nothing since all instructions are word aligned on sparc
661 }
662
663
664 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
665 __ call(op->addr(), rtype);
666 // The peephole pass fills the delay slot, add_call_info is done in
667 // LIR_Assembler::emit_delay.
668 }
669
670
671 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
672 __ ic_call(op->addr(), false);
673 // The peephole pass fills the delay slot, add_call_info is done in
674 // LIR_Assembler::emit_delay.
675 }
676
677
678 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
679 add_debug_info_for_null_check_here(op->info());
680 __ load_klass(O0, G3_scratch);
681 if (Assembler::is_simm13(op->vtable_offset())) {
682 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
683 } else {
684 // This will generate 2 instructions
685 __ set(op->vtable_offset(), G5_method);
686 // ld_ptr, set_hi, set
687 __ ld_ptr(G3_scratch, G5_method, G5_method);
688 }
689 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
690 __ callr(G3_scratch, G0);
691 // the peephole pass fills the delay slot
692 }
693
694 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
695 int store_offset;
696 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
697 assert(!unaligned, "can't handle this");
698 // for offsets larger than a simm13 we setup the offset in O7
699 __ set(offset, O7);
700 store_offset = store(from_reg, base, O7, type, wide);
701 } else {
702 if (type == T_ARRAY || type == T_OBJECT) {
703 __ verify_oop(from_reg->as_register());
704 }
705 store_offset = code_offset();
706 switch (type) {
707 case T_BOOLEAN: // fall through
708 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
709 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
710 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
711 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
712 case T_LONG :
713 #ifdef _LP64
714 if (unaligned || PatchALot) {
715 __ srax(from_reg->as_register_lo(), 32, O7);
716 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
717 __ stw(O7, base, offset + hi_word_offset_in_bytes);
718 } else {
719 __ stx(from_reg->as_register_lo(), base, offset);
720 }
721 #else
722 assert(Assembler::is_simm13(offset + 4), "must be");
723 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
724 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
725 #endif
726 break;
727 case T_ADDRESS:
728 case T_METADATA:
729 __ st_ptr(from_reg->as_register(), base, offset);
730 break;
731 case T_ARRAY : // fall through
732 case T_OBJECT:
733 {
734 if (UseCompressedOops && !wide) {
735 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
736 store_offset = code_offset();
737 __ stw(G3_scratch, base, offset);
738 } else {
739 __ st_ptr(from_reg->as_register(), base, offset);
740 }
741 break;
742 }
743
744 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
745 case T_DOUBLE:
746 {
747 FloatRegister reg = from_reg->as_double_reg();
748 // split unaligned stores
749 if (unaligned || PatchALot) {
750 assert(Assembler::is_simm13(offset + 4), "must be");
751 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
752 __ stf(FloatRegisterImpl::S, reg, base, offset);
753 } else {
754 __ stf(FloatRegisterImpl::D, reg, base, offset);
755 }
756 break;
757 }
758 default : ShouldNotReachHere();
759 }
760 }
761 return store_offset;
762 }
763
764
765 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
766 if (type == T_ARRAY || type == T_OBJECT) {
767 __ verify_oop(from_reg->as_register());
768 }
769 int store_offset = code_offset();
770 switch (type) {
771 case T_BOOLEAN: // fall through
772 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
773 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
774 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
775 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
776 case T_LONG :
777 #ifdef _LP64
778 __ stx(from_reg->as_register_lo(), base, disp);
779 #else
780 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
781 __ std(from_reg->as_register_hi(), base, disp);
782 #endif
783 break;
784 case T_ADDRESS:
785 __ st_ptr(from_reg->as_register(), base, disp);
786 break;
787 case T_ARRAY : // fall through
788 case T_OBJECT:
789 {
790 if (UseCompressedOops && !wide) {
791 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
792 store_offset = code_offset();
793 __ stw(G3_scratch, base, disp);
794 } else {
795 __ st_ptr(from_reg->as_register(), base, disp);
796 }
797 break;
798 }
799 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
800 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
801 default : ShouldNotReachHere();
802 }
803 return store_offset;
804 }
805
806
807 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
808 int load_offset;
809 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
810 assert(base != O7, "destroying register");
811 assert(!unaligned, "can't handle this");
812 // for offsets larger than a simm13 we setup the offset in O7
813 __ set(offset, O7);
814 load_offset = load(base, O7, to_reg, type, wide);
815 } else {
816 load_offset = code_offset();
817 switch(type) {
818 case T_BOOLEAN: // fall through
819 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
820 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
821 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
822 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
823 case T_LONG :
824 if (!unaligned) {
825 #ifdef _LP64
826 __ ldx(base, offset, to_reg->as_register_lo());
827 #else
828 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
829 "must be sequential");
830 __ ldd(base, offset, to_reg->as_register_hi());
831 #endif
832 } else {
833 #ifdef _LP64
834 assert(base != to_reg->as_register_lo(), "can't handle this");
835 assert(O7 != to_reg->as_register_lo(), "can't handle this");
836 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
837 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
838 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
839 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
840 #else
841 if (base == to_reg->as_register_lo()) {
842 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
843 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
844 } else {
845 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
846 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
847 }
848 #endif
849 }
850 break;
851 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
852 case T_ADDRESS:
853 #ifdef _LP64
854 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
855 __ lduw(base, offset, to_reg->as_register());
856 __ decode_klass_not_null(to_reg->as_register());
857 } else
858 #endif
859 {
860 __ ld_ptr(base, offset, to_reg->as_register());
861 }
862 break;
863 case T_ARRAY : // fall through
864 case T_OBJECT:
865 {
866 if (UseCompressedOops && !wide) {
867 __ lduw(base, offset, to_reg->as_register());
868 __ decode_heap_oop(to_reg->as_register());
869 } else {
870 __ ld_ptr(base, offset, to_reg->as_register());
871 }
872 break;
873 }
874 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
875 case T_DOUBLE:
876 {
877 FloatRegister reg = to_reg->as_double_reg();
878 // split unaligned loads
879 if (unaligned || PatchALot) {
880 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
881 __ ldf(FloatRegisterImpl::S, base, offset, reg);
882 } else {
883 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
884 }
885 break;
886 }
887 default : ShouldNotReachHere();
888 }
889 if (type == T_ARRAY || type == T_OBJECT) {
890 __ verify_oop(to_reg->as_register());
891 }
892 }
893 return load_offset;
894 }
895
896
897 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
898 int load_offset = code_offset();
899 switch(type) {
900 case T_BOOLEAN: // fall through
901 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
902 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
903 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
904 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
905 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
906 case T_ARRAY : // fall through
907 case T_OBJECT:
908 {
909 if (UseCompressedOops && !wide) {
910 __ lduw(base, disp, to_reg->as_register());
911 __ decode_heap_oop(to_reg->as_register());
912 } else {
913 __ ld_ptr(base, disp, to_reg->as_register());
914 }
915 break;
916 }
917 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
918 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
919 case T_LONG :
920 #ifdef _LP64
921 __ ldx(base, disp, to_reg->as_register_lo());
922 #else
923 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
924 "must be sequential");
925 __ ldd(base, disp, to_reg->as_register_hi());
926 #endif
927 break;
928 default : ShouldNotReachHere();
929 }
930 if (type == T_ARRAY || type == T_OBJECT) {
931 __ verify_oop(to_reg->as_register());
932 }
933 return load_offset;
934 }
935
936 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
937 LIR_Const* c = src->as_constant_ptr();
938 switch (c->type()) {
939 case T_INT:
940 case T_FLOAT: {
941 Register src_reg = O7;
942 int value = c->as_jint_bits();
943 if (value == 0) {
944 src_reg = G0;
945 } else {
946 __ set(value, O7);
947 }
948 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
949 __ stw(src_reg, addr.base(), addr.disp());
950 break;
951 }
952 case T_ADDRESS: {
953 Register src_reg = O7;
954 int value = c->as_jint_bits();
955 if (value == 0) {
956 src_reg = G0;
957 } else {
958 __ set(value, O7);
959 }
960 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
961 __ st_ptr(src_reg, addr.base(), addr.disp());
962 break;
963 }
964 case T_OBJECT: {
965 Register src_reg = O7;
966 jobject2reg(c->as_jobject(), src_reg);
967 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
968 __ st_ptr(src_reg, addr.base(), addr.disp());
969 break;
970 }
971 case T_LONG:
972 case T_DOUBLE: {
973 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
974
975 Register tmp = O7;
976 int value_lo = c->as_jint_lo_bits();
977 if (value_lo == 0) {
978 tmp = G0;
979 } else {
980 __ set(value_lo, O7);
981 }
982 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
983 int value_hi = c->as_jint_hi_bits();
984 if (value_hi == 0) {
985 tmp = G0;
986 } else {
987 __ set(value_hi, O7);
988 }
989 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
990 break;
991 }
992 default:
993 Unimplemented();
994 }
995 }
996
997
998 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
999 LIR_Const* c = src->as_constant_ptr();
1000 LIR_Address* addr = dest->as_address_ptr();
1001 Register base = addr->base()->as_pointer_register();
1002 int offset = -1;
1003
1004 switch (c->type()) {
1005 case T_INT:
1006 case T_FLOAT:
1007 case T_ADDRESS: {
1008 LIR_Opr tmp = FrameMap::O7_opr;
1009 int value = c->as_jint_bits();
1010 if (value == 0) {
1011 tmp = FrameMap::G0_opr;
1012 } else if (Assembler::is_simm13(value)) {
1013 __ set(value, O7);
1014 }
1015 if (addr->index()->is_valid()) {
1016 assert(addr->disp() == 0, "must be zero");
1017 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1018 } else {
1019 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1020 offset = store(tmp, base, addr->disp(), type, wide, false);
1021 }
1022 break;
1023 }
1024 case T_LONG:
1025 case T_DOUBLE: {
1026 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1027 assert(Assembler::is_simm13(addr->disp()) &&
1028 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1029
1030 LIR_Opr tmp = FrameMap::O7_opr;
1031 int value_lo = c->as_jint_lo_bits();
1032 if (value_lo == 0) {
1033 tmp = FrameMap::G0_opr;
1034 } else {
1035 __ set(value_lo, O7);
1036 }
1037 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1038 int value_hi = c->as_jint_hi_bits();
1039 if (value_hi == 0) {
1040 tmp = FrameMap::G0_opr;
1041 } else {
1042 __ set(value_hi, O7);
1043 }
1044 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1045 break;
1046 }
1047 case T_OBJECT: {
1048 jobject obj = c->as_jobject();
1049 LIR_Opr tmp;
1050 if (obj == NULL) {
1051 tmp = FrameMap::G0_opr;
1052 } else {
1053 tmp = FrameMap::O7_opr;
1054 jobject2reg(c->as_jobject(), O7);
1055 }
1056 // handle either reg+reg or reg+disp address
1057 if (addr->index()->is_valid()) {
1058 assert(addr->disp() == 0, "must be zero");
1059 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1060 } else {
1061 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1062 offset = store(tmp, base, addr->disp(), type, wide, false);
1063 }
1064
1065 break;
1066 }
1067 default:
1068 Unimplemented();
1069 }
1070 if (info != NULL) {
1071 assert(offset != -1, "offset should've been set");
1072 add_debug_info_for_null_check(offset, info);
1073 }
1074 }
1075
1076
1077 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1078 LIR_Const* c = src->as_constant_ptr();
1079 LIR_Opr to_reg = dest;
1080
1081 switch (c->type()) {
1082 case T_INT:
1083 case T_ADDRESS:
1084 {
1085 jint con = c->as_jint();
1086 if (to_reg->is_single_cpu()) {
1087 assert(patch_code == lir_patch_none, "no patching handled here");
1088 __ set(con, to_reg->as_register());
1089 } else {
1090 ShouldNotReachHere();
1091 assert(to_reg->is_single_fpu(), "wrong register kind");
1092
1093 __ set(con, O7);
1094 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1095 __ st(O7, temp_slot);
1096 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1097 }
1098 }
1099 break;
1100
1101 case T_LONG:
1102 {
1103 jlong con = c->as_jlong();
1104
1105 if (to_reg->is_double_cpu()) {
1106 #ifdef _LP64
1107 __ set(con, to_reg->as_register_lo());
1108 #else
1109 __ set(low(con), to_reg->as_register_lo());
1110 __ set(high(con), to_reg->as_register_hi());
1111 #endif
1112 #ifdef _LP64
1113 } else if (to_reg->is_single_cpu()) {
1114 __ set(con, to_reg->as_register());
1115 #endif
1116 } else {
1117 ShouldNotReachHere();
1118 assert(to_reg->is_double_fpu(), "wrong register kind");
1119 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1120 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1121 __ set(low(con), O7);
1122 __ st(O7, temp_slot_lo);
1123 __ set(high(con), O7);
1124 __ st(O7, temp_slot_hi);
1125 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1126 }
1127 }
1128 break;
1129
1130 case T_OBJECT:
1131 {
1132 if (patch_code == lir_patch_none) {
1133 jobject2reg(c->as_jobject(), to_reg->as_register());
1134 } else {
1135 jobject2reg_with_patching(to_reg->as_register(), info);
1136 }
1137 }
1138 break;
1139
1140 case T_METADATA:
1141 {
1142 if (patch_code == lir_patch_none) {
1143 metadata2reg(c->as_metadata(), to_reg->as_register());
1144 } else {
1145 klass2reg_with_patching(to_reg->as_register(), info);
1146 }
1147 }
1148 break;
1149
1150 case T_FLOAT:
1151 {
1152 address const_addr = __ float_constant(c->as_jfloat());
1153 if (const_addr == NULL) {
1154 bailout("const section overflow");
1155 break;
1156 }
1157 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1158 AddressLiteral const_addrlit(const_addr, rspec);
1159 if (to_reg->is_single_fpu()) {
1160 __ patchable_sethi(const_addrlit, O7);
1161 __ relocate(rspec);
1162 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1163
1164 } else {
1165 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1166
1167 __ set(const_addrlit, O7);
1168 __ ld(O7, 0, to_reg->as_register());
1169 }
1170 }
1171 break;
1172
1173 case T_DOUBLE:
1174 {
1175 address const_addr = __ double_constant(c->as_jdouble());
1176 if (const_addr == NULL) {
1177 bailout("const section overflow");
1178 break;
1179 }
1180 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1181
1182 if (to_reg->is_double_fpu()) {
1183 AddressLiteral const_addrlit(const_addr, rspec);
1184 __ patchable_sethi(const_addrlit, O7);
1185 __ relocate(rspec);
1186 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1187 } else {
1188 assert(to_reg->is_double_cpu(), "Must be a long register.");
1189 #ifdef _LP64
1190 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1191 #else
1192 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1193 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1194 #endif
1195 }
1196
1197 }
1198 break;
1199
1200 default:
1201 ShouldNotReachHere();
1202 }
1203 }
1204
1205 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1206 Register reg = addr->base()->as_pointer_register();
1207 LIR_Opr index = addr->index();
1208 if (index->is_illegal()) {
1209 return Address(reg, addr->disp());
1210 } else {
1211 assert (addr->disp() == 0, "unsupported address mode");
1212 return Address(reg, index->as_pointer_register());
1213 }
1214 }
1215
1216
1217 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1218 switch (type) {
1219 case T_INT:
1220 case T_FLOAT: {
1221 Register tmp = O7;
1222 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1223 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1224 __ lduw(from.base(), from.disp(), tmp);
1225 __ stw(tmp, to.base(), to.disp());
1226 break;
1227 }
1228 case T_OBJECT: {
1229 Register tmp = O7;
1230 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1231 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1232 __ ld_ptr(from.base(), from.disp(), tmp);
1233 __ st_ptr(tmp, to.base(), to.disp());
1234 break;
1235 }
1236 case T_LONG:
1237 case T_DOUBLE: {
1238 Register tmp = O7;
1239 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1240 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1241 __ lduw(from.base(), from.disp(), tmp);
1242 __ stw(tmp, to.base(), to.disp());
1243 __ lduw(from.base(), from.disp() + 4, tmp);
1244 __ stw(tmp, to.base(), to.disp() + 4);
1245 break;
1246 }
1247
1248 default:
1249 ShouldNotReachHere();
1250 }
1251 }
1252
1253
1254 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1255 Address base = as_Address(addr);
1256 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1257 }
1258
1259
1260 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1261 Address base = as_Address(addr);
1262 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1263 }
1264
1265
1266 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1267 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1268
1269 assert(type != T_METADATA, "load of metadata ptr not supported");
1270 LIR_Address* addr = src_opr->as_address_ptr();
1271 LIR_Opr to_reg = dest;
1272
1273 Register src = addr->base()->as_pointer_register();
1274 Register disp_reg = noreg;
1275 int disp_value = addr->disp();
1276 bool needs_patching = (patch_code != lir_patch_none);
1277
1278 if (addr->base()->type() == T_OBJECT) {
1279 __ verify_oop(src);
1280 }
1281
1282 PatchingStub* patch = NULL;
1283 if (needs_patching) {
1284 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1285 assert(!to_reg->is_double_cpu() ||
1286 patch_code == lir_patch_none ||
1287 patch_code == lir_patch_normal, "patching doesn't match register");
1288 }
1289
1290 if (addr->index()->is_illegal()) {
1291 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1292 if (needs_patching) {
1293 __ patchable_set(0, O7);
1294 } else {
1295 __ set(disp_value, O7);
1296 }
1297 disp_reg = O7;
1298 }
1299 } else if (unaligned || PatchALot) {
1300 __ add(src, addr->index()->as_register(), O7);
1301 src = O7;
1302 } else {
1303 disp_reg = addr->index()->as_pointer_register();
1304 assert(disp_value == 0, "can't handle 3 operand addresses");
1305 }
1306
1307 // remember the offset of the load. The patching_epilog must be done
1308 // before the call to add_debug_info, otherwise the PcDescs don't get
1309 // entered in increasing order.
1310 int offset = code_offset();
1311
1312 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1313 if (disp_reg == noreg) {
1314 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1315 } else {
1316 assert(!unaligned, "can't handle this");
1317 offset = load(src, disp_reg, to_reg, type, wide);
1318 }
1319
1320 if (patch != NULL) {
1321 patching_epilog(patch, patch_code, src, info);
1322 }
1323 if (info != NULL) add_debug_info_for_null_check(offset, info);
1324 }
1325
1326
1327 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1328 Address addr;
1329 if (src->is_single_word()) {
1330 addr = frame_map()->address_for_slot(src->single_stack_ix());
1331 } else if (src->is_double_word()) {
1332 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1333 }
1334
1335 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1336 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1337 }
1338
1339
1340 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1341 Address addr;
1342 if (dest->is_single_word()) {
1343 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1344 } else if (dest->is_double_word()) {
1345 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1346 }
1347 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1348 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1349 }
1350
1351
1352 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1353 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1354 if (from_reg->is_double_fpu()) {
1355 // double to double moves
1356 assert(to_reg->is_double_fpu(), "should match");
1357 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1358 } else {
1359 // float to float moves
1360 assert(to_reg->is_single_fpu(), "should match");
1361 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1362 }
1363 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1364 if (from_reg->is_double_cpu()) {
1365 #ifdef _LP64
1366 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1367 #else
1368 assert(to_reg->is_double_cpu() &&
1369 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1370 from_reg->as_register_lo() != to_reg->as_register_hi(),
1371 "should both be long and not overlap");
1372 // long to long moves
1373 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1374 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1375 #endif
1376 #ifdef _LP64
1377 } else if (to_reg->is_double_cpu()) {
1378 // int to int moves
1379 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1380 #endif
1381 } else {
1382 // int to int moves
1383 __ mov(from_reg->as_register(), to_reg->as_register());
1384 }
1385 } else {
1386 ShouldNotReachHere();
1387 }
1388 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1389 __ verify_oop(to_reg->as_register());
1390 }
1391 }
1392
1393
1394 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1395 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1396 bool wide, bool unaligned) {
1397 assert(type != T_METADATA, "store of metadata ptr not supported");
1398 LIR_Address* addr = dest->as_address_ptr();
1399
1400 Register src = addr->base()->as_pointer_register();
1401 Register disp_reg = noreg;
1402 int disp_value = addr->disp();
1403 bool needs_patching = (patch_code != lir_patch_none);
1404
1405 if (addr->base()->is_oop_register()) {
1406 __ verify_oop(src);
1407 }
1408
1409 PatchingStub* patch = NULL;
1410 if (needs_patching) {
1411 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1412 assert(!from_reg->is_double_cpu() ||
1413 patch_code == lir_patch_none ||
1414 patch_code == lir_patch_normal, "patching doesn't match register");
1415 }
1416
1417 if (addr->index()->is_illegal()) {
1418 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1419 if (needs_patching) {
1420 __ patchable_set(0, O7);
1421 } else {
1422 __ set(disp_value, O7);
1423 }
1424 disp_reg = O7;
1425 }
1426 } else if (unaligned || PatchALot) {
1427 __ add(src, addr->index()->as_register(), O7);
1428 src = O7;
1429 } else {
1430 disp_reg = addr->index()->as_pointer_register();
1431 assert(disp_value == 0, "can't handle 3 operand addresses");
1432 }
1433
1434 // remember the offset of the store. The patching_epilog must be done
1435 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1436 // entered in increasing order.
1437 int offset;
1438
1439 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1440 if (disp_reg == noreg) {
1441 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1442 } else {
1443 assert(!unaligned, "can't handle this");
1444 offset = store(from_reg, src, disp_reg, type, wide);
1445 }
1446
1447 if (patch != NULL) {
1448 patching_epilog(patch, patch_code, src, info);
1449 }
1450
1451 if (info != NULL) add_debug_info_for_null_check(offset, info);
1452 }
1453
1454
1455 void LIR_Assembler::return_op(LIR_Opr result) {
1456 // the poll may need a register so just pick one that isn't the return register
1457 #if defined(TIERED) && !defined(_LP64)
1458 if (result->type_field() == LIR_OprDesc::long_type) {
1459 // Must move the result to G1
1460 // Must leave proper result in O0,O1 and G1 (TIERED only)
1461 __ sllx(I0, 32, G1); // Shift bits into high G1
1462 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1463 __ or3 (I1, G1, G1); // OR 64 bits into G1
1464 #ifdef ASSERT
1465 // mangle it so any problems will show up
1466 __ set(0xdeadbeef, I0);
1467 __ set(0xdeadbeef, I1);
1468 #endif
1469 }
1470 #endif // TIERED
1471 __ set((intptr_t)os::get_polling_page(), L0);
1472 __ relocate(relocInfo::poll_return_type);
1473 __ ld_ptr(L0, 0, G0);
1474 __ ret();
1475 __ delayed()->restore();
1476 }
1477
1478
1479 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1480 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1481 if (info != NULL) {
1482 add_debug_info_for_branch(info);
1483 }
1484 int offset = __ offset();
1485 __ relocate(relocInfo::poll_type);
1486 __ ld_ptr(tmp->as_register(), 0, G0);
1487 return offset;
1488 }
1489
1490
1491 void LIR_Assembler::emit_static_call_stub() {
1492 address call_pc = __ pc();
1493 address stub = __ start_a_stub(call_stub_size);
1494 if (stub == NULL) {
1495 bailout("static call stub overflow");
1496 return;
1497 }
1498
1499 int start = __ offset();
1500 __ relocate(static_stub_Relocation::spec(call_pc));
1501
1502 __ set_metadata(NULL, G5);
1503 // must be set to -1 at code generation time
1504 AddressLiteral addrlit(-1);
1505 __ jump_to(addrlit, G3);
1506 __ delayed()->nop();
1507
1508 assert(__ offset() - start <= call_stub_size, "stub too big");
1509 __ end_a_stub();
1510 }
1511
1512
1513 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1514 if (opr1->is_single_fpu()) {
1515 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1516 } else if (opr1->is_double_fpu()) {
1517 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1518 } else if (opr1->is_single_cpu()) {
1519 if (opr2->is_constant()) {
1520 switch (opr2->as_constant_ptr()->type()) {
1521 case T_INT:
1522 { jint con = opr2->as_constant_ptr()->as_jint();
1523 if (Assembler::is_simm13(con)) {
1524 __ cmp(opr1->as_register(), con);
1525 } else {
1526 __ set(con, O7);
1527 __ cmp(opr1->as_register(), O7);
1528 }
1529 }
1530 break;
1531
1532 case T_OBJECT:
1533 // there are only equal/notequal comparisions on objects
1534 { jobject con = opr2->as_constant_ptr()->as_jobject();
1535 if (con == NULL) {
1536 __ cmp(opr1->as_register(), 0);
1537 } else {
1538 jobject2reg(con, O7);
1539 __ cmp(opr1->as_register(), O7);
1540 }
1541 }
1542 break;
1543
1544 default:
1545 ShouldNotReachHere();
1546 break;
1547 }
1548 } else {
1549 if (opr2->is_address()) {
1550 LIR_Address * addr = opr2->as_address_ptr();
1551 BasicType type = addr->type();
1552 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1553 else __ ld(as_Address(addr), O7);
1554 __ cmp(opr1->as_register(), O7);
1555 } else {
1556 __ cmp(opr1->as_register(), opr2->as_register());
1557 }
1558 }
1559 } else if (opr1->is_double_cpu()) {
1560 Register xlo = opr1->as_register_lo();
1561 Register xhi = opr1->as_register_hi();
1562 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1563 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1564 #ifdef _LP64
1565 __ orcc(xhi, G0, G0);
1566 #else
1567 __ orcc(xhi, xlo, G0);
1568 #endif
1569 } else if (opr2->is_register()) {
1570 Register ylo = opr2->as_register_lo();
1571 Register yhi = opr2->as_register_hi();
1572 #ifdef _LP64
1573 __ cmp(xlo, ylo);
1574 #else
1575 __ subcc(xlo, ylo, xlo);
1576 __ subccc(xhi, yhi, xhi);
1577 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1578 __ orcc(xhi, xlo, G0);
1579 }
1580 #endif
1581 } else {
1582 ShouldNotReachHere();
1583 }
1584 } else if (opr1->is_address()) {
1585 LIR_Address * addr = opr1->as_address_ptr();
1586 BasicType type = addr->type();
1587 assert (opr2->is_constant(), "Checking");
1588 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1589 else __ ld(as_Address(addr), O7);
1590 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1591 } else {
1592 ShouldNotReachHere();
1593 }
1594 }
1595
1596
1597 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1598 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1599 bool is_unordered_less = (code == lir_ucmp_fd2i);
1600 if (left->is_single_fpu()) {
1601 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1602 } else if (left->is_double_fpu()) {
1603 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1604 } else {
1605 ShouldNotReachHere();
1606 }
1607 } else if (code == lir_cmp_l2i) {
1608 #ifdef _LP64
1609 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1610 #else
1611 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1612 right->as_register_hi(), right->as_register_lo(),
1613 dst->as_register());
1614 #endif
1615 } else {
1616 ShouldNotReachHere();
1617 }
1618 }
1619
1620
1621 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1622 Assembler::Condition acond;
1623 switch (condition) {
1624 case lir_cond_equal: acond = Assembler::equal; break;
1625 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1626 case lir_cond_less: acond = Assembler::less; break;
1627 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1628 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1629 case lir_cond_greater: acond = Assembler::greater; break;
1630 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1631 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1632 default: ShouldNotReachHere();
1633 };
1634
1635 if (opr1->is_constant() && opr1->type() == T_INT) {
1636 Register dest = result->as_register();
1637 // load up first part of constant before branch
1638 // and do the rest in the delay slot.
1639 if (!Assembler::is_simm13(opr1->as_jint())) {
1640 __ sethi(opr1->as_jint(), dest);
1641 }
1642 } else if (opr1->is_constant()) {
1643 const2reg(opr1, result, lir_patch_none, NULL);
1644 } else if (opr1->is_register()) {
1645 reg2reg(opr1, result);
1646 } else if (opr1->is_stack()) {
1647 stack2reg(opr1, result, result->type());
1648 } else {
1649 ShouldNotReachHere();
1650 }
1651 Label skip;
1652 #ifdef _LP64
1653 if (type == T_INT) {
1654 __ br(acond, false, Assembler::pt, skip);
1655 } else
1656 #endif
1657 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1658 if (opr1->is_constant() && opr1->type() == T_INT) {
1659 Register dest = result->as_register();
1660 if (Assembler::is_simm13(opr1->as_jint())) {
1661 __ delayed()->or3(G0, opr1->as_jint(), dest);
1662 } else {
1663 // the sethi has been done above, so just put in the low 10 bits
1664 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1665 }
1666 } else {
1667 // can't do anything useful in the delay slot
1668 __ delayed()->nop();
1669 }
1670 if (opr2->is_constant()) {
1671 const2reg(opr2, result, lir_patch_none, NULL);
1672 } else if (opr2->is_register()) {
1673 reg2reg(opr2, result);
1674 } else if (opr2->is_stack()) {
1675 stack2reg(opr2, result, result->type());
1676 } else {
1677 ShouldNotReachHere();
1678 }
1679 __ bind(skip);
1680 }
1681
1682
1683 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1684 assert(info == NULL, "unused on this code path");
1685 assert(left->is_register(), "wrong items state");
1686 assert(dest->is_register(), "wrong items state");
1687
1688 if (right->is_register()) {
1689 if (dest->is_float_kind()) {
1690
1691 FloatRegister lreg, rreg, res;
1692 FloatRegisterImpl::Width w;
1693 if (right->is_single_fpu()) {
1694 w = FloatRegisterImpl::S;
1695 lreg = left->as_float_reg();
1696 rreg = right->as_float_reg();
1697 res = dest->as_float_reg();
1698 } else {
1699 w = FloatRegisterImpl::D;
1700 lreg = left->as_double_reg();
1701 rreg = right->as_double_reg();
1702 res = dest->as_double_reg();
1703 }
1704
1705 switch (code) {
1706 case lir_add: __ fadd(w, lreg, rreg, res); break;
1707 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1708 case lir_mul: // fall through
1709 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1710 case lir_div: // fall through
1711 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1712 default: ShouldNotReachHere();
1713 }
1714
1715 } else if (dest->is_double_cpu()) {
1716 #ifdef _LP64
1717 Register dst_lo = dest->as_register_lo();
1718 Register op1_lo = left->as_pointer_register();
1719 Register op2_lo = right->as_pointer_register();
1720
1721 switch (code) {
1722 case lir_add:
1723 __ add(op1_lo, op2_lo, dst_lo);
1724 break;
1725
1726 case lir_sub:
1727 __ sub(op1_lo, op2_lo, dst_lo);
1728 break;
1729
1730 default: ShouldNotReachHere();
1731 }
1732 #else
1733 Register op1_lo = left->as_register_lo();
1734 Register op1_hi = left->as_register_hi();
1735 Register op2_lo = right->as_register_lo();
1736 Register op2_hi = right->as_register_hi();
1737 Register dst_lo = dest->as_register_lo();
1738 Register dst_hi = dest->as_register_hi();
1739
1740 switch (code) {
1741 case lir_add:
1742 __ addcc(op1_lo, op2_lo, dst_lo);
1743 __ addc (op1_hi, op2_hi, dst_hi);
1744 break;
1745
1746 case lir_sub:
1747 __ subcc(op1_lo, op2_lo, dst_lo);
1748 __ subc (op1_hi, op2_hi, dst_hi);
1749 break;
1750
1751 default: ShouldNotReachHere();
1752 }
1753 #endif
1754 } else {
1755 assert (right->is_single_cpu(), "Just Checking");
1756
1757 Register lreg = left->as_register();
1758 Register res = dest->as_register();
1759 Register rreg = right->as_register();
1760 switch (code) {
1761 case lir_add: __ add (lreg, rreg, res); break;
1762 case lir_sub: __ sub (lreg, rreg, res); break;
1763 case lir_mul: __ mulx (lreg, rreg, res); break;
1764 default: ShouldNotReachHere();
1765 }
1766 }
1767 } else {
1768 assert (right->is_constant(), "must be constant");
1769
1770 if (dest->is_single_cpu()) {
1771 Register lreg = left->as_register();
1772 Register res = dest->as_register();
1773 int simm13 = right->as_constant_ptr()->as_jint();
1774
1775 switch (code) {
1776 case lir_add: __ add (lreg, simm13, res); break;
1777 case lir_sub: __ sub (lreg, simm13, res); break;
1778 case lir_mul: __ mulx (lreg, simm13, res); break;
1779 default: ShouldNotReachHere();
1780 }
1781 } else {
1782 Register lreg = left->as_pointer_register();
1783 Register res = dest->as_register_lo();
1784 long con = right->as_constant_ptr()->as_jlong();
1785 assert(Assembler::is_simm13(con), "must be simm13");
1786
1787 switch (code) {
1788 case lir_add: __ add (lreg, (int)con, res); break;
1789 case lir_sub: __ sub (lreg, (int)con, res); break;
1790 case lir_mul: __ mulx (lreg, (int)con, res); break;
1791 default: ShouldNotReachHere();
1792 }
1793 }
1794 }
1795 }
1796
1797
1798 void LIR_Assembler::fpop() {
1799 // do nothing
1800 }
1801
1802
1803 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1804 switch (code) {
1805 case lir_sin:
1806 case lir_tan:
1807 case lir_cos: {
1808 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1809 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1810 break;
1811 }
1812 case lir_sqrt: {
1813 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1814 FloatRegister src_reg = value->as_double_reg();
1815 FloatRegister dst_reg = dest->as_double_reg();
1816 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1817 break;
1818 }
1819 case lir_abs: {
1820 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1821 FloatRegister src_reg = value->as_double_reg();
1822 FloatRegister dst_reg = dest->as_double_reg();
1823 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1824 break;
1825 }
1826 default: {
1827 ShouldNotReachHere();
1828 break;
1829 }
1830 }
1831 }
1832
1833
1834 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1835 if (right->is_constant()) {
1836 if (dest->is_single_cpu()) {
1837 int simm13 = right->as_constant_ptr()->as_jint();
1838 switch (code) {
1839 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1840 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1841 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1842 default: ShouldNotReachHere();
1843 }
1844 } else {
1845 long c = right->as_constant_ptr()->as_jlong();
1846 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1847 int simm13 = (int)c;
1848 switch (code) {
1849 case lir_logic_and:
1850 #ifndef _LP64
1851 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1852 #endif
1853 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1854 break;
1855
1856 case lir_logic_or:
1857 #ifndef _LP64
1858 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1859 #endif
1860 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1861 break;
1862
1863 case lir_logic_xor:
1864 #ifndef _LP64
1865 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1866 #endif
1867 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1868 break;
1869
1870 default: ShouldNotReachHere();
1871 }
1872 }
1873 } else {
1874 assert(right->is_register(), "right should be in register");
1875
1876 if (dest->is_single_cpu()) {
1877 switch (code) {
1878 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1879 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1880 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1881 default: ShouldNotReachHere();
1882 }
1883 } else {
1884 #ifdef _LP64
1885 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1886 left->as_register_lo();
1887 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1888 right->as_register_lo();
1889
1890 switch (code) {
1891 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1892 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1893 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1894 default: ShouldNotReachHere();
1895 }
1896 #else
1897 switch (code) {
1898 case lir_logic_and:
1899 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1900 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1901 break;
1902
1903 case lir_logic_or:
1904 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1905 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1906 break;
1907
1908 case lir_logic_xor:
1909 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1910 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1911 break;
1912
1913 default: ShouldNotReachHere();
1914 }
1915 #endif
1916 }
1917 }
1918 }
1919
1920
1921 int LIR_Assembler::shift_amount(BasicType t) {
1922 int elem_size = type2aelembytes(t);
1923 switch (elem_size) {
1924 case 1 : return 0;
1925 case 2 : return 1;
1926 case 4 : return 2;
1927 case 8 : return 3;
1928 }
1929 ShouldNotReachHere();
1930 return -1;
1931 }
1932
1933
1934 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1935 assert(exceptionOop->as_register() == Oexception, "should match");
1936 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1937
1938 info->add_register_oop(exceptionOop);
1939
1940 // reuse the debug info from the safepoint poll for the throw op itself
1941 address pc_for_athrow = __ pc();
1942 int pc_for_athrow_offset = __ offset();
1943 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1944 __ set(pc_for_athrow, Oissuing_pc, rspec);
1945 add_call_info(pc_for_athrow_offset, info); // for exception handler
1946
1947 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1948 __ delayed()->nop();
1949 }
1950
1951
1952 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1953 assert(exceptionOop->as_register() == Oexception, "should match");
1954
1955 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1956 __ delayed()->nop();
1957 }
1958
1959 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1960 Register src = op->src()->as_register();
1961 Register dst = op->dst()->as_register();
1962 Register src_pos = op->src_pos()->as_register();
1963 Register dst_pos = op->dst_pos()->as_register();
1964 Register length = op->length()->as_register();
1965 Register tmp = op->tmp()->as_register();
1966 Register tmp2 = O7;
1967
1968 int flags = op->flags();
1969 ciArrayKlass* default_type = op->expected_type();
1970 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1971 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1972
1973 #ifdef _LP64
1974 // higher 32bits must be null
1975 __ sra(dst_pos, 0, dst_pos);
1976 __ sra(src_pos, 0, src_pos);
1977 __ sra(length, 0, length);
1978 #endif
1979
1980 // set up the arraycopy stub information
1981 ArrayCopyStub* stub = op->stub();
1982
1983 // always do stub if no type information is available. it's ok if
1984 // the known type isn't loaded since the code sanity checks
1985 // in debug mode and the type isn't required when we know the exact type
1986 // also check that the type is an array type.
1987 if (op->expected_type() == NULL) {
1988 __ mov(src, O0);
1989 __ mov(src_pos, O1);
1990 __ mov(dst, O2);
1991 __ mov(dst_pos, O3);
1992 __ mov(length, O4);
1993 address copyfunc_addr = StubRoutines::generic_arraycopy();
1994
1995 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1996 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1997 } else {
1998 #ifndef PRODUCT
1999 if (PrintC1Statistics) {
2000 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
2001 __ inc_counter(counter, G1, G3);
2002 }
2003 #endif
2004 __ call_VM_leaf(tmp, copyfunc_addr);
2005 }
2006
2007 if (copyfunc_addr != NULL) {
2008 __ xor3(O0, -1, tmp);
2009 __ sub(length, tmp, length);
2010 __ add(src_pos, tmp, src_pos);
2011 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2012 __ delayed()->add(dst_pos, tmp, dst_pos);
2013 } else {
2014 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2015 __ delayed()->nop();
2016 }
2017 __ bind(*stub->continuation());
2018 return;
2019 }
2020
2021 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2022
2023 // make sure src and dst are non-null and load array length
2024 if (flags & LIR_OpArrayCopy::src_null_check) {
2025 __ tst(src);
2026 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2027 __ delayed()->nop();
2028 }
2029
2030 if (flags & LIR_OpArrayCopy::dst_null_check) {
2031 __ tst(dst);
2032 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2033 __ delayed()->nop();
2034 }
2035
2036 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2037 // test src_pos register
2038 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
2039 __ delayed()->nop();
2040 }
2041
2042 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2043 // test dst_pos register
2044 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
2045 __ delayed()->nop();
2046 }
2047
2048 if (flags & LIR_OpArrayCopy::length_positive_check) {
2049 // make sure length isn't negative
2050 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
2051 __ delayed()->nop();
2052 }
2053
2054 if (flags & LIR_OpArrayCopy::src_range_check) {
2055 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2056 __ add(length, src_pos, tmp);
2057 __ cmp(tmp2, tmp);
2058 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2059 __ delayed()->nop();
2060 }
2061
2062 if (flags & LIR_OpArrayCopy::dst_range_check) {
2063 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2064 __ add(length, dst_pos, tmp);
2065 __ cmp(tmp2, tmp);
2066 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2067 __ delayed()->nop();
2068 }
2069
2070 int shift = shift_amount(basic_type);
2071
2072 if (flags & LIR_OpArrayCopy::type_check) {
2073 // We don't know the array types are compatible
2074 if (basic_type != T_OBJECT) {
2075 // Simple test for basic type arrays
2076 if (UseCompressedClassPointers) {
2077 // We don't need decode because we just need to compare
2078 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
2079 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2080 __ cmp(tmp, tmp2);
2081 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2082 } else {
2083 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2084 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2085 __ cmp(tmp, tmp2);
2086 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2087 }
2088 __ delayed()->nop();
2089 } else {
2090 // For object arrays, if src is a sub class of dst then we can
2091 // safely do the copy.
2092 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2093
2094 Label cont, slow;
2095 assert_different_registers(tmp, tmp2, G3, G1);
2096
2097 __ load_klass(src, G3);
2098 __ load_klass(dst, G1);
2099
2100 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2101
2102 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2103 __ delayed()->nop();
2104
2105 __ cmp(G3, 0);
2106 if (copyfunc_addr != NULL) { // use stub if available
2107 // src is not a sub class of dst so we have to do a
2108 // per-element check.
2109 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2110 __ delayed()->nop();
2111
2112 __ bind(slow);
2113
2114 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2115 if ((flags & mask) != mask) {
2116 // Check that at least both of them object arrays.
2117 assert(flags & mask, "one of the two should be known to be an object array");
2118
2119 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2120 __ load_klass(src, tmp);
2121 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2122 __ load_klass(dst, tmp);
2123 }
2124 int lh_offset = in_bytes(Klass::layout_helper_offset());
2125
2126 __ lduw(tmp, lh_offset, tmp2);
2127
2128 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2129 __ set(objArray_lh, tmp);
2130 __ cmp(tmp, tmp2);
2131 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2132 __ delayed()->nop();
2133 }
2134
2135 Register src_ptr = O0;
2136 Register dst_ptr = O1;
2137 Register len = O2;
2138 Register chk_off = O3;
2139 Register super_k = O4;
2140
2141 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2142 if (shift == 0) {
2143 __ add(src_ptr, src_pos, src_ptr);
2144 } else {
2145 __ sll(src_pos, shift, tmp);
2146 __ add(src_ptr, tmp, src_ptr);
2147 }
2148
2149 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2150 if (shift == 0) {
2151 __ add(dst_ptr, dst_pos, dst_ptr);
2152 } else {
2153 __ sll(dst_pos, shift, tmp);
2154 __ add(dst_ptr, tmp, dst_ptr);
2155 }
2156 __ mov(length, len);
2157 __ load_klass(dst, tmp);
2158
2159 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2160 __ ld_ptr(tmp, ek_offset, super_k);
2161
2162 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2163 __ lduw(super_k, sco_offset, chk_off);
2164
2165 __ call_VM_leaf(tmp, copyfunc_addr);
2166
2167 #ifndef PRODUCT
2168 if (PrintC1Statistics) {
2169 Label failed;
2170 __ br_notnull_short(O0, Assembler::pn, failed);
2171 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2172 __ bind(failed);
2173 }
2174 #endif
2175
2176 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2177 __ delayed()->xor3(O0, -1, tmp);
2178
2179 #ifndef PRODUCT
2180 if (PrintC1Statistics) {
2181 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2182 }
2183 #endif
2184
2185 __ sub(length, tmp, length);
2186 __ add(src_pos, tmp, src_pos);
2187 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2188 __ delayed()->add(dst_pos, tmp, dst_pos);
2189
2190 __ bind(cont);
2191 } else {
2192 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2193 __ delayed()->nop();
2194 __ bind(cont);
2195 }
2196 }
2197 }
2198
2199 #ifdef ASSERT
2200 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2201 // Sanity check the known type with the incoming class. For the
2202 // primitive case the types must match exactly with src.klass and
2203 // dst.klass each exactly matching the default type. For the
2204 // object array case, if no type check is needed then either the
2205 // dst type is exactly the expected type and the src type is a
2206 // subtype which we can't check or src is the same array as dst
2207 // but not necessarily exactly of type default_type.
2208 Label known_ok, halt;
2209 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2210 if (UseCompressedClassPointers) {
2211 // tmp holds the default type. It currently comes uncompressed after the
2212 // load of a constant, so encode it.
2213 __ encode_klass_not_null(tmp);
2214 // load the raw value of the dst klass, since we will be comparing
2215 // uncompressed values directly.
2216 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2217 if (basic_type != T_OBJECT) {
2218 __ cmp(tmp, tmp2);
2219 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2220 // load the raw value of the src klass.
2221 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2222 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2223 } else {
2224 __ cmp(tmp, tmp2);
2225 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2226 __ delayed()->cmp(src, dst);
2227 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2228 __ delayed()->nop();
2229 }
2230 } else {
2231 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2232 if (basic_type != T_OBJECT) {
2233 __ cmp(tmp, tmp2);
2234 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2235 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2236 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2237 } else {
2238 __ cmp(tmp, tmp2);
2239 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2240 __ delayed()->cmp(src, dst);
2241 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2242 __ delayed()->nop();
2243 }
2244 }
2245 __ bind(halt);
2246 __ stop("incorrect type information in arraycopy");
2247 __ bind(known_ok);
2248 }
2249 #endif
2250
2251 #ifndef PRODUCT
2252 if (PrintC1Statistics) {
2253 address counter = Runtime1::arraycopy_count_address(basic_type);
2254 __ inc_counter(counter, G1, G3);
2255 }
2256 #endif
2257
2258 Register src_ptr = O0;
2259 Register dst_ptr = O1;
2260 Register len = O2;
2261
2262 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2263 if (shift == 0) {
2264 __ add(src_ptr, src_pos, src_ptr);
2265 } else {
2266 __ sll(src_pos, shift, tmp);
2267 __ add(src_ptr, tmp, src_ptr);
2268 }
2269
2270 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2271 if (shift == 0) {
2272 __ add(dst_ptr, dst_pos, dst_ptr);
2273 } else {
2274 __ sll(dst_pos, shift, tmp);
2275 __ add(dst_ptr, tmp, dst_ptr);
2276 }
2277
2278 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2279 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2280 const char *name;
2281 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2282
2283 // arraycopy stubs takes a length in number of elements, so don't scale it.
2284 __ mov(length, len);
2285 __ call_VM_leaf(tmp, entry);
2286
2287 __ bind(*stub->continuation());
2288 }
2289
2290
2291 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2292 if (dest->is_single_cpu()) {
2293 #ifdef _LP64
2294 if (left->type() == T_OBJECT) {
2295 switch (code) {
2296 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2297 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2298 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2299 default: ShouldNotReachHere();
2300 }
2301 } else
2302 #endif
2303 switch (code) {
2304 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2305 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2306 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2307 default: ShouldNotReachHere();
2308 }
2309 } else {
2310 #ifdef _LP64
2311 switch (code) {
2312 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2313 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2314 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2315 default: ShouldNotReachHere();
2316 }
2317 #else
2318 switch (code) {
2319 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2320 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2321 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2322 default: ShouldNotReachHere();
2323 }
2324 #endif
2325 }
2326 }
2327
2328
2329 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2330 #ifdef _LP64
2331 if (left->type() == T_OBJECT) {
2332 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2333 Register l = left->as_register();
2334 Register d = dest->as_register_lo();
2335 switch (code) {
2336 case lir_shl: __ sllx (l, count, d); break;
2337 case lir_shr: __ srax (l, count, d); break;
2338 case lir_ushr: __ srlx (l, count, d); break;
2339 default: ShouldNotReachHere();
2340 }
2341 return;
2342 }
2343 #endif
2344
2345 if (dest->is_single_cpu()) {
2346 count = count & 0x1F; // Java spec
2347 switch (code) {
2348 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2349 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2350 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2351 default: ShouldNotReachHere();
2352 }
2353 } else if (dest->is_double_cpu()) {
2354 count = count & 63; // Java spec
2355 switch (code) {
2356 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2357 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2358 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2359 default: ShouldNotReachHere();
2360 }
2361 } else {
2362 ShouldNotReachHere();
2363 }
2364 }
2365
2366
2367 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2368 assert(op->tmp1()->as_register() == G1 &&
2369 op->tmp2()->as_register() == G3 &&
2370 op->tmp3()->as_register() == G4 &&
2371 op->obj()->as_register() == O0 &&
2372 op->klass()->as_register() == G5, "must be");
2373 if (op->init_check()) {
2374 __ ldub(op->klass()->as_register(),
2375 in_bytes(InstanceKlass::init_state_offset()),
2376 op->tmp1()->as_register());
2377 add_debug_info_for_null_check_here(op->stub()->info());
2378 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2379 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2380 __ delayed()->nop();
2381 }
2382 __ allocate_object(op->obj()->as_register(),
2383 op->tmp1()->as_register(),
2384 op->tmp2()->as_register(),
2385 op->tmp3()->as_register(),
2386 op->header_size(),
2387 op->object_size(),
2388 op->klass()->as_register(),
2389 *op->stub()->entry());
2390 __ bind(*op->stub()->continuation());
2391 __ verify_oop(op->obj()->as_register());
2392 }
2393
2394
2395 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2396 assert(op->tmp1()->as_register() == G1 &&
2397 op->tmp2()->as_register() == G3 &&
2398 op->tmp3()->as_register() == G4 &&
2399 op->tmp4()->as_register() == O1 &&
2400 op->klass()->as_register() == G5, "must be");
2401
2402 LP64_ONLY( __ signx(op->len()->as_register()); )
2403 if (UseSlowPath ||
2404 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2405 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2406 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2407 __ delayed()->nop();
2408 } else {
2409 __ allocate_array(op->obj()->as_register(),
2410 op->len()->as_register(),
2411 op->tmp1()->as_register(),
2412 op->tmp2()->as_register(),
2413 op->tmp3()->as_register(),
2414 arrayOopDesc::header_size(op->type()),
2415 type2aelembytes(op->type()),
2416 op->klass()->as_register(),
2417 *op->stub()->entry());
2418 }
2419 __ bind(*op->stub()->continuation());
2420 }
2421
2422
2423 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2424 ciMethodData *md, ciProfileData *data,
2425 Register recv, Register tmp1, Label* update_done) {
2426 uint i;
2427 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2428 Label next_test;
2429 // See if the receiver is receiver[n].
2430 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2431 mdo_offset_bias);
2432 __ ld_ptr(receiver_addr, tmp1);
2433 __ verify_klass_ptr(tmp1);
2434 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2435 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2436 mdo_offset_bias);
2437 __ ld_ptr(data_addr, tmp1);
2438 __ add(tmp1, DataLayout::counter_increment, tmp1);
2439 __ st_ptr(tmp1, data_addr);
2440 __ ba(*update_done);
2441 __ delayed()->nop();
2442 __ bind(next_test);
2443 }
2444
2445 // Didn't find receiver; find next empty slot and fill it in
2446 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2447 Label next_test;
2448 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2449 mdo_offset_bias);
2450 __ ld_ptr(recv_addr, tmp1);
2451 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2452 __ st_ptr(recv, recv_addr);
2453 __ set(DataLayout::counter_increment, tmp1);
2454 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2455 mdo_offset_bias);
2456 __ ba(*update_done);
2457 __ delayed()->nop();
2458 __ bind(next_test);
2459 }
2460 }
2461
2462
2463 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2464 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2465 md = method->method_data_or_null();
2466 assert(md != NULL, "Sanity");
2467 data = md->bci_to_data(bci);
2468 assert(data != NULL, "need data for checkcast");
2469 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2470 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2471 // The offset is large so bias the mdo by the base of the slot so
2472 // that the ld can use simm13s to reference the slots of the data
2473 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2474 }
2475 }
2476
2477 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2478 // we always need a stub for the failure case.
2479 CodeStub* stub = op->stub();
2480 Register obj = op->object()->as_register();
2481 Register k_RInfo = op->tmp1()->as_register();
2482 Register klass_RInfo = op->tmp2()->as_register();
2483 Register dst = op->result_opr()->as_register();
2484 Register Rtmp1 = op->tmp3()->as_register();
2485 ciKlass* k = op->klass();
2486
2487
2488 if (obj == k_RInfo) {
2489 k_RInfo = klass_RInfo;
2490 klass_RInfo = obj;
2491 }
2492
2493 ciMethodData* md;
2494 ciProfileData* data;
2495 int mdo_offset_bias = 0;
2496 if (op->should_profile()) {
2497 ciMethod* method = op->profiled_method();
2498 assert(method != NULL, "Should have method");
2499 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2500
2501 Label not_null;
2502 __ br_notnull_short(obj, Assembler::pn, not_null);
2503 Register mdo = k_RInfo;
2504 Register data_val = Rtmp1;
2505 metadata2reg(md->constant_encoding(), mdo);
2506 if (mdo_offset_bias > 0) {
2507 __ set(mdo_offset_bias, data_val);
2508 __ add(mdo, data_val, mdo);
2509 }
2510 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2511 __ ldub(flags_addr, data_val);
2512 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2513 __ stb(data_val, flags_addr);
2514 __ ba(*obj_is_null);
2515 __ delayed()->nop();
2516 __ bind(not_null);
2517 } else {
2518 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2519 __ delayed()->nop();
2520 }
2521
2522 Label profile_cast_failure, profile_cast_success;
2523 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2524 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2525
2526 // patching may screw with our temporaries on sparc,
2527 // so let's do it before loading the class
2528 if (k->is_loaded()) {
2529 metadata2reg(k->constant_encoding(), k_RInfo);
2530 } else {
2531 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2532 }
2533 assert(obj != k_RInfo, "must be different");
2534
2535 // get object class
2536 // not a safepoint as obj null check happens earlier
2537 __ load_klass(obj, klass_RInfo);
2538 if (op->fast_check()) {
2539 assert_different_registers(klass_RInfo, k_RInfo);
2540 __ cmp(k_RInfo, klass_RInfo);
2541 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2542 __ delayed()->nop();
2543 } else {
2544 bool need_slow_path = true;
2545 if (k->is_loaded()) {
2546 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2547 need_slow_path = false;
2548 // perform the fast part of the checking logic
2549 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2550 (need_slow_path ? success_target : NULL),
2551 failure_target, NULL,
2552 RegisterOrConstant(k->super_check_offset()));
2553 } else {
2554 // perform the fast part of the checking logic
2555 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2556 failure_target, NULL);
2557 }
2558 if (need_slow_path) {
2559 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2560 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2561 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2562 __ delayed()->nop();
2563 __ cmp(G3, 0);
2564 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2565 __ delayed()->nop();
2566 // Fall through to success case
2567 }
2568 }
2569
2570 if (op->should_profile()) {
2571 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2572 assert_different_registers(obj, mdo, recv, tmp1);
2573 __ bind(profile_cast_success);
2574 metadata2reg(md->constant_encoding(), mdo);
2575 if (mdo_offset_bias > 0) {
2576 __ set(mdo_offset_bias, tmp1);
2577 __ add(mdo, tmp1, mdo);
2578 }
2579 __ load_klass(obj, recv);
2580 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2581 // Jump over the failure case
2582 __ ba(*success);
2583 __ delayed()->nop();
2584 // Cast failure case
2585 __ bind(profile_cast_failure);
2586 metadata2reg(md->constant_encoding(), mdo);
2587 if (mdo_offset_bias > 0) {
2588 __ set(mdo_offset_bias, tmp1);
2589 __ add(mdo, tmp1, mdo);
2590 }
2591 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2592 __ ld_ptr(data_addr, tmp1);
2593 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2594 __ st_ptr(tmp1, data_addr);
2595 __ ba(*failure);
2596 __ delayed()->nop();
2597 }
2598 __ ba(*success);
2599 __ delayed()->nop();
2600 }
2601
2602 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2603 LIR_Code code = op->code();
2604 if (code == lir_store_check) {
2605 Register value = op->object()->as_register();
2606 Register array = op->array()->as_register();
2607 Register k_RInfo = op->tmp1()->as_register();
2608 Register klass_RInfo = op->tmp2()->as_register();
2609 Register Rtmp1 = op->tmp3()->as_register();
2610
2611 __ verify_oop(value);
2612 CodeStub* stub = op->stub();
2613 // check if it needs to be profiled
2614 ciMethodData* md;
2615 ciProfileData* data;
2616 int mdo_offset_bias = 0;
2617 if (op->should_profile()) {
2618 ciMethod* method = op->profiled_method();
2619 assert(method != NULL, "Should have method");
2620 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2621 }
2622 Label profile_cast_success, profile_cast_failure, done;
2623 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2624 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2625
2626 if (op->should_profile()) {
2627 Label not_null;
2628 __ br_notnull_short(value, Assembler::pn, not_null);
2629 Register mdo = k_RInfo;
2630 Register data_val = Rtmp1;
2631 metadata2reg(md->constant_encoding(), mdo);
2632 if (mdo_offset_bias > 0) {
2633 __ set(mdo_offset_bias, data_val);
2634 __ add(mdo, data_val, mdo);
2635 }
2636 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2637 __ ldub(flags_addr, data_val);
2638 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2639 __ stb(data_val, flags_addr);
2640 __ ba_short(done);
2641 __ bind(not_null);
2642 } else {
2643 __ br_null_short(value, Assembler::pn, done);
2644 }
2645 add_debug_info_for_null_check_here(op->info_for_exception());
2646 __ load_klass(array, k_RInfo);
2647 __ load_klass(value, klass_RInfo);
2648
2649 // get instance klass
2650 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2651 // perform the fast part of the checking logic
2652 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2653
2654 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2655 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2656 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2657 __ delayed()->nop();
2658 __ cmp(G3, 0);
2659 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2660 __ delayed()->nop();
2661 // fall through to the success case
2662
2663 if (op->should_profile()) {
2664 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2665 assert_different_registers(value, mdo, recv, tmp1);
2666 __ bind(profile_cast_success);
2667 metadata2reg(md->constant_encoding(), mdo);
2668 if (mdo_offset_bias > 0) {
2669 __ set(mdo_offset_bias, tmp1);
2670 __ add(mdo, tmp1, mdo);
2671 }
2672 __ load_klass(value, recv);
2673 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2674 __ ba_short(done);
2675 // Cast failure case
2676 __ bind(profile_cast_failure);
2677 metadata2reg(md->constant_encoding(), mdo);
2678 if (mdo_offset_bias > 0) {
2679 __ set(mdo_offset_bias, tmp1);
2680 __ add(mdo, tmp1, mdo);
2681 }
2682 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2683 __ ld_ptr(data_addr, tmp1);
2684 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2685 __ st_ptr(tmp1, data_addr);
2686 __ ba(*stub->entry());
2687 __ delayed()->nop();
2688 }
2689 __ bind(done);
2690 } else if (code == lir_checkcast) {
2691 Register obj = op->object()->as_register();
2692 Register dst = op->result_opr()->as_register();
2693 Label success;
2694 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2695 __ bind(success);
2696 __ mov(obj, dst);
2697 } else if (code == lir_instanceof) {
2698 Register obj = op->object()->as_register();
2699 Register dst = op->result_opr()->as_register();
2700 Label success, failure, done;
2701 emit_typecheck_helper(op, &success, &failure, &failure);
2702 __ bind(failure);
2703 __ set(0, dst);
2704 __ ba_short(done);
2705 __ bind(success);
2706 __ set(1, dst);
2707 __ bind(done);
2708 } else {
2709 ShouldNotReachHere();
2710 }
2711
2712 }
2713
2714
2715 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2716 if (op->code() == lir_cas_long) {
2717 assert(VM_Version::supports_cx8(), "wrong machine");
2718 Register addr = op->addr()->as_pointer_register();
2719 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2720 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2721 Register new_value_lo = op->new_value()->as_register_lo();
2722 Register new_value_hi = op->new_value()->as_register_hi();
2723 Register t1 = op->tmp1()->as_register();
2724 Register t2 = op->tmp2()->as_register();
2725 #ifdef _LP64
2726 __ mov(cmp_value_lo, t1);
2727 __ mov(new_value_lo, t2);
2728 // perform the compare and swap operation
2729 __ casx(addr, t1, t2);
2730 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2731 // overwritten with the original value in "addr" and will be equal to t1.
2732 __ cmp(t1, t2);
2733 #else
2734 // move high and low halves of long values into single registers
2735 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2736 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2737 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2738 __ sllx(new_value_hi, 32, t2);
2739 __ srl(new_value_lo, 0, new_value_lo);
2740 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2741 // perform the compare and swap operation
2742 __ casx(addr, t1, t2);
2743 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2744 // overwritten with the original value in "addr" and will be equal to t1.
2745 // Produce icc flag for 32bit.
2746 __ sub(t1, t2, t2);
2747 __ srlx(t2, 32, t1);
2748 __ orcc(t2, t1, G0);
2749 #endif
2750 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2751 Register addr = op->addr()->as_pointer_register();
2752 Register cmp_value = op->cmp_value()->as_register();
2753 Register new_value = op->new_value()->as_register();
2754 Register t1 = op->tmp1()->as_register();
2755 Register t2 = op->tmp2()->as_register();
2756 __ mov(cmp_value, t1);
2757 __ mov(new_value, t2);
2758 if (op->code() == lir_cas_obj) {
2759 if (UseCompressedOops) {
2760 __ encode_heap_oop(t1);
2761 __ encode_heap_oop(t2);
2762 __ cas(addr, t1, t2);
2763 } else {
2764 __ cas_ptr(addr, t1, t2);
2765 }
2766 } else {
2767 __ cas(addr, t1, t2);
2768 }
2769 __ cmp(t1, t2);
2770 } else {
2771 Unimplemented();
2772 }
2773 }
2774
2775 void LIR_Assembler::set_24bit_FPU() {
2776 Unimplemented();
2777 }
2778
2779
2780 void LIR_Assembler::reset_FPU() {
2781 Unimplemented();
2782 }
2783
2784
2785 void LIR_Assembler::breakpoint() {
2786 __ breakpoint_trap();
2787 }
2788
2789
2790 void LIR_Assembler::push(LIR_Opr opr) {
2791 Unimplemented();
2792 }
2793
2794
2795 void LIR_Assembler::pop(LIR_Opr opr) {
2796 Unimplemented();
2797 }
2798
2799
2800 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2801 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2802 Register dst = dst_opr->as_register();
2803 Register reg = mon_addr.base();
2804 int offset = mon_addr.disp();
2805 // compute pointer to BasicLock
2806 if (mon_addr.is_simm13()) {
2807 __ add(reg, offset, dst);
2808 } else {
2809 __ set(offset, dst);
2810 __ add(dst, reg, dst);
2811 }
2812 }
2813
2814 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2815 fatal("CRC32 intrinsic is not implemented on this platform");
2816 }
2817
2818 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2819 Register obj = op->obj_opr()->as_register();
2820 Register hdr = op->hdr_opr()->as_register();
2821 Register lock = op->lock_opr()->as_register();
2822
2823 // obj may not be an oop
2824 if (op->code() == lir_lock) {
2825 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2826 if (UseFastLocking) {
2827 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2828 // add debug info for NullPointerException only if one is possible
2829 if (op->info() != NULL) {
2830 add_debug_info_for_null_check_here(op->info());
2831 }
2832 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2833 } else {
2834 // always do slow locking
2835 // note: the slow locking code could be inlined here, however if we use
2836 // slow locking, speed doesn't matter anyway and this solution is
2837 // simpler and requires less duplicated code - additionally, the
2838 // slow locking code is the same in either case which simplifies
2839 // debugging
2840 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2841 __ delayed()->nop();
2842 }
2843 } else {
2844 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2845 if (UseFastLocking) {
2846 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2847 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2848 } else {
2849 // always do slow unlocking
2850 // note: the slow unlocking code could be inlined here, however if we use
2851 // slow unlocking, speed doesn't matter anyway and this solution is
2852 // simpler and requires less duplicated code - additionally, the
2853 // slow unlocking code is the same in either case which simplifies
2854 // debugging
2855 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2856 __ delayed()->nop();
2857 }
2858 }
2859 __ bind(*op->stub()->continuation());
2860 }
2861
2862
2863 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2864 ciMethod* method = op->profiled_method();
2865 int bci = op->profiled_bci();
2866 ciMethod* callee = op->profiled_callee();
2867
2868 // Update counter for all call types
2869 ciMethodData* md = method->method_data_or_null();
2870 assert(md != NULL, "Sanity");
2871 ciProfileData* data = md->bci_to_data(bci);
2872 assert(data->is_CounterData(), "need CounterData for calls");
2873 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2874 Register mdo = op->mdo()->as_register();
2875 #ifdef _LP64
2876 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2877 Register tmp1 = op->tmp1()->as_register_lo();
2878 #else
2879 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2880 Register tmp1 = op->tmp1()->as_register();
2881 #endif
2882 metadata2reg(md->constant_encoding(), mdo);
2883 int mdo_offset_bias = 0;
2884 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2885 data->size_in_bytes())) {
2886 // The offset is large so bias the mdo by the base of the slot so
2887 // that the ld can use simm13s to reference the slots of the data
2888 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2889 __ set(mdo_offset_bias, O7);
2890 __ add(mdo, O7, mdo);
2891 }
2892
2893 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2894 Bytecodes::Code bc = method->java_code_at_bci(bci);
2895 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2896 // Perform additional virtual call profiling for invokevirtual and
2897 // invokeinterface bytecodes
2898 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2899 !callee_is_static && // required for optimized MH invokes
2900 C1ProfileVirtualCalls) {
2901 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2902 Register recv = op->recv()->as_register();
2903 assert_different_registers(mdo, tmp1, recv);
2904 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2905 ciKlass* known_klass = op->known_holder();
2906 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2907 // We know the type that will be seen at this call site; we can
2908 // statically update the MethodData* rather than needing to do
2909 // dynamic tests on the receiver type
2910
2911 // NOTE: we should probably put a lock around this search to
2912 // avoid collisions by concurrent compilations
2913 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2914 uint i;
2915 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2916 ciKlass* receiver = vc_data->receiver(i);
2917 if (known_klass->equals(receiver)) {
2918 Address data_addr(mdo, md->byte_offset_of_slot(data,
2919 VirtualCallData::receiver_count_offset(i)) -
2920 mdo_offset_bias);
2921 __ ld_ptr(data_addr, tmp1);
2922 __ add(tmp1, DataLayout::counter_increment, tmp1);
2923 __ st_ptr(tmp1, data_addr);
2924 return;
2925 }
2926 }
2927
2928 // Receiver type not found in profile data; select an empty slot
2929
2930 // Note that this is less efficient than it should be because it
2931 // always does a write to the receiver part of the
2932 // VirtualCallData rather than just the first time
2933 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2934 ciKlass* receiver = vc_data->receiver(i);
2935 if (receiver == NULL) {
2936 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2937 mdo_offset_bias);
2938 metadata2reg(known_klass->constant_encoding(), tmp1);
2939 __ st_ptr(tmp1, recv_addr);
2940 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2941 mdo_offset_bias);
2942 __ ld_ptr(data_addr, tmp1);
2943 __ add(tmp1, DataLayout::counter_increment, tmp1);
2944 __ st_ptr(tmp1, data_addr);
2945 return;
2946 }
2947 }
2948 } else {
2949 __ load_klass(recv, recv);
2950 Label update_done;
2951 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2952 // Receiver did not match any saved receiver and there is no empty row for it.
2953 // Increment total counter to indicate polymorphic case.
2954 __ ld_ptr(counter_addr, tmp1);
2955 __ add(tmp1, DataLayout::counter_increment, tmp1);
2956 __ st_ptr(tmp1, counter_addr);
2957
2958 __ bind(update_done);
2959 }
2960 } else {
2961 // Static call
2962 __ ld_ptr(counter_addr, tmp1);
2963 __ add(tmp1, DataLayout::counter_increment, tmp1);
2964 __ st_ptr(tmp1, counter_addr);
2965 }
2966 }
2967
2968 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2969 Register obj = op->obj()->as_register();
2970 Register tmp1 = op->tmp()->as_pointer_register();
2971 Register tmp2 = G1;
2972 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2973 ciKlass* exact_klass = op->exact_klass();
2974 intptr_t current_klass = op->current_klass();
2975 bool not_null = op->not_null();
2976 bool no_conflict = op->no_conflict();
2977
2978 Label update, next, none;
2979
2980 bool do_null = !not_null;
2981 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2982 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2983
2984 assert(do_null || do_update, "why are we here?");
2985 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2986
2987 __ verify_oop(obj);
2988
2989 if (tmp1 != obj) {
2990 __ mov(obj, tmp1);
2991 }
2992 if (do_null) {
2993 __ br_notnull_short(tmp1, Assembler::pt, update);
2994 if (!TypeEntries::was_null_seen(current_klass)) {
2995 __ ld_ptr(mdo_addr, tmp1);
2996 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2997 __ st_ptr(tmp1, mdo_addr);
2998 }
2999 if (do_update) {
3000 __ ba(next);
3001 __ delayed()->nop();
3002 }
3003 #ifdef ASSERT
3004 } else {
3005 __ br_notnull_short(tmp1, Assembler::pt, update);
3006 __ stop("unexpect null obj");
3007 #endif
3008 }
3009
3010 __ bind(update);
3011
3012 if (do_update) {
3013 #ifdef ASSERT
3014 if (exact_klass != NULL) {
3015 Label ok;
3016 __ load_klass(tmp1, tmp1);
3017 metadata2reg(exact_klass->constant_encoding(), tmp2);
3018 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
3019 __ stop("exact klass and actual klass differ");
3020 __ bind(ok);
3021 }
3022 #endif
3023
3024 Label do_update;
3025 __ ld_ptr(mdo_addr, tmp2);
3026
3027 if (!no_conflict) {
3028 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3029 if (exact_klass != NULL) {
3030 metadata2reg(exact_klass->constant_encoding(), tmp1);
3031 } else {
3032 __ load_klass(tmp1, tmp1);
3033 }
3034
3035 __ xor3(tmp1, tmp2, tmp1);
3036 __ btst(TypeEntries::type_klass_mask, tmp1);
3037 // klass seen before, nothing to do. The unknown bit may have been
3038 // set already but no need to check.
3039 __ brx(Assembler::zero, false, Assembler::pt, next);
3040 __ delayed()->
3041
3042 btst(TypeEntries::type_unknown, tmp1);
3043 // already unknown. Nothing to do anymore.
3044 __ brx(Assembler::notZero, false, Assembler::pt, next);
3045
3046 if (TypeEntries::is_type_none(current_klass)) {
3047 __ delayed()->btst(TypeEntries::type_mask, tmp2);
3048 __ brx(Assembler::zero, true, Assembler::pt, do_update);
3049 // first time here. Set profile type.
3050 __ delayed()->or3(tmp2, tmp1, tmp2);
3051 } else {
3052 __ delayed()->nop();
3053 }
3054 } else {
3055 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3056 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3057
3058 __ btst(TypeEntries::type_unknown, tmp2);
3059 // already unknown. Nothing to do anymore.
3060 __ brx(Assembler::notZero, false, Assembler::pt, next);
3061 __ delayed()->nop();
3062 }
3063
3064 // different than before. Cannot keep accurate profile.
3065 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
3066 } else {
3067 // There's a single possible klass at this profile point
3068 assert(exact_klass != NULL, "should be");
3069 if (TypeEntries::is_type_none(current_klass)) {
3070 metadata2reg(exact_klass->constant_encoding(), tmp1);
3071 __ xor3(tmp1, tmp2, tmp1);
3072 __ btst(TypeEntries::type_klass_mask, tmp1);
3073 __ brx(Assembler::zero, false, Assembler::pt, next);
3074 #ifdef ASSERT
3075
3076 {
3077 Label ok;
3078 __ delayed()->btst(TypeEntries::type_mask, tmp2);
3079 __ brx(Assembler::zero, true, Assembler::pt, ok);
3080 __ delayed()->nop();
3081
3082 __ stop("unexpected profiling mismatch");
3083 __ bind(ok);
3084 }
3085 // first time here. Set profile type.
3086 __ or3(tmp2, tmp1, tmp2);
3087 #else
3088 // first time here. Set profile type.
3089 __ delayed()->or3(tmp2, tmp1, tmp2);
3090 #endif
3091
3092 } else {
3093 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3094 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3095
3096 // already unknown. Nothing to do anymore.
3097 __ btst(TypeEntries::type_unknown, tmp2);
3098 __ brx(Assembler::notZero, false, Assembler::pt, next);
3099 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
3100 }
3101 }
3102
3103 __ bind(do_update);
3104 __ st_ptr(tmp2, mdo_addr);
3105
3106 __ bind(next);
3107 }
3108 }
3109
3110 void LIR_Assembler::align_backward_branch_target() {
3111 __ align(OptoLoopAlignment);
3112 }
3113
3114
3115 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3116 // make sure we are expecting a delay
3117 // this has the side effect of clearing the delay state
3118 // so we can use _masm instead of _masm->delayed() to do the
3119 // code generation.
3120 __ delayed();
3121
3122 // make sure we only emit one instruction
3123 int offset = code_offset();
3124 op->delay_op()->emit_code(this);
3125 #ifdef ASSERT
3126 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3127 op->delay_op()->print();
3128 }
3129 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3130 "only one instruction can go in a delay slot");
3131 #endif
3132
3133 // we may also be emitting the call info for the instruction
3134 // which we are the delay slot of.
3135 CodeEmitInfo* call_info = op->call_info();
3136 if (call_info) {
3137 add_call_info(code_offset(), call_info);
3138 }
3139
3140 if (VerifyStackAtCalls) {
3141 _masm->sub(FP, SP, O7);
3142 _masm->cmp(O7, initial_frame_size_in_bytes());
3143 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3144 }
3145 }
3146
3147
3148 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3149 assert(left->is_register(), "can only handle registers");
3150
3151 if (left->is_single_cpu()) {
3152 __ neg(left->as_register(), dest->as_register());
3153 } else if (left->is_single_fpu()) {
3154 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3155 } else if (left->is_double_fpu()) {
3156 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3157 } else {
3158 assert (left->is_double_cpu(), "Must be a long");
3159 Register Rlow = left->as_register_lo();
3160 Register Rhi = left->as_register_hi();
3161 #ifdef _LP64
3162 __ sub(G0, Rlow, dest->as_register_lo());
3163 #else
3164 __ subcc(G0, Rlow, dest->as_register_lo());
3165 __ subc (G0, Rhi, dest->as_register_hi());
3166 #endif
3167 }
3168 }
3169
3170
3171 void LIR_Assembler::fxch(int i) {
3172 Unimplemented();
3173 }
3174
3175 void LIR_Assembler::fld(int i) {
3176 Unimplemented();
3177 }
3178
3179 void LIR_Assembler::ffree(int i) {
3180 Unimplemented();
3181 }
3182
3183 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3184 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3185
3186 // if tmp is invalid, then the function being called doesn't destroy the thread
3187 if (tmp->is_valid()) {
3188 __ save_thread(tmp->as_pointer_register());
3189 }
3190 __ call(dest, relocInfo::runtime_call_type);
3191 __ delayed()->nop();
3192 if (info != NULL) {
3193 add_call_info_here(info);
3194 }
3195 if (tmp->is_valid()) {
3196 __ restore_thread(tmp->as_pointer_register());
3197 }
3198
3199 #ifdef ASSERT
3200 __ verify_thread();
3201 #endif // ASSERT
3202 }
3203
3204
3205 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3206 #ifdef _LP64
3207 ShouldNotReachHere();
3208 #endif
3209
3210 NEEDS_CLEANUP;
3211 if (type == T_LONG) {
3212 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3213
3214 // (extended to allow indexed as well as constant displaced for JSR-166)
3215 Register idx = noreg; // contains either constant offset or index
3216
3217 int disp = mem_addr->disp();
3218 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3219 if (!Assembler::is_simm13(disp)) {
3220 idx = O7;
3221 __ set(disp, idx);
3222 }
3223 } else {
3224 assert(disp == 0, "not both indexed and disp");
3225 idx = mem_addr->index()->as_register();
3226 }
3227
3228 int null_check_offset = -1;
3229
3230 Register base = mem_addr->base()->as_register();
3231 if (src->is_register() && dest->is_address()) {
3232 // G4 is high half, G5 is low half
3233 // clear the top bits of G5, and scale up G4
3234 __ srl (src->as_register_lo(), 0, G5);
3235 __ sllx(src->as_register_hi(), 32, G4);
3236 // combine the two halves into the 64 bits of G4
3237 __ or3(G4, G5, G4);
3238 null_check_offset = __ offset();
3239 if (idx == noreg) {
3240 __ stx(G4, base, disp);
3241 } else {
3242 __ stx(G4, base, idx);
3243 }
3244 } else if (src->is_address() && dest->is_register()) {
3245 null_check_offset = __ offset();
3246 if (idx == noreg) {
3247 __ ldx(base, disp, G5);
3248 } else {
3249 __ ldx(base, idx, G5);
3250 }
3251 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3252 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3253 } else {
3254 Unimplemented();
3255 }
3256 if (info != NULL) {
3257 add_debug_info_for_null_check(null_check_offset, info);
3258 }
3259
3260 } else {
3261 // use normal move for all other volatiles since they don't need
3262 // special handling to remain atomic.
3263 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3264 }
3265 }
3266
3267 void LIR_Assembler::membar() {
3268 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3269 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3270 }
3271
3272 void LIR_Assembler::membar_acquire() {
3273 // no-op on TSO
3274 }
3275
3276 void LIR_Assembler::membar_release() {
3277 // no-op on TSO
3278 }
3279
3280 void LIR_Assembler::membar_loadload() {
3281 // no-op
3282 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3283 }
3284
3285 void LIR_Assembler::membar_storestore() {
3286 // no-op
3287 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3288 }
3289
3290 void LIR_Assembler::membar_loadstore() {
3291 // no-op
3292 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3293 }
3294
3295 void LIR_Assembler::membar_storeload() {
3296 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3297 }
3298
3299
3300 // Pack two sequential registers containing 32 bit values
3301 // into a single 64 bit register.
3302 // src and src->successor() are packed into dst
3303 // src and dst may be the same register.
3304 // Note: src is destroyed
3305 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3306 Register rs = src->as_register();
3307 Register rd = dst->as_register_lo();
3308 __ sllx(rs, 32, rs);
3309 __ srl(rs->successor(), 0, rs->successor());
3310 __ or3(rs, rs->successor(), rd);
3311 }
3312
3313 // Unpack a 64 bit value in a register into
3314 // two sequential registers.
3315 // src is unpacked into dst and dst->successor()
3316 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3317 Register rs = src->as_register_lo();
3318 Register rd = dst->as_register_hi();
3319 assert_different_registers(rs, rd, rd->successor());
3320 __ srlx(rs, 32, rd);
3321 __ srl (rs, 0, rd->successor());
3322 }
3323
3324
3325 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3326 LIR_Address* addr = addr_opr->as_address_ptr();
3327 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3328
3329 if (Assembler::is_simm13(addr->disp())) {
3330 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3331 } else {
3332 __ set(addr->disp(), G3_scratch);
3333 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3334 }
3335 }
3336
3337
3338 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3339 assert(result_reg->is_register(), "check");
3340 __ mov(G2_thread, result_reg->as_register());
3341 }
3342
3343 #ifdef ASSERT
3344 // emit run-time assertion
3345 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3346 assert(op->code() == lir_assert, "must be");
3347
3348 if (op->in_opr1()->is_valid()) {
3349 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3350 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3351 } else {
3352 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3353 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3354 }
3355
3356 Label ok;
3357 if (op->condition() != lir_cond_always) {
3358 Assembler::Condition acond;
3359 switch (op->condition()) {
3360 case lir_cond_equal: acond = Assembler::equal; break;
3361 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3362 case lir_cond_less: acond = Assembler::less; break;
3363 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3364 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3365 case lir_cond_greater: acond = Assembler::greater; break;
3366 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3367 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3368 default: ShouldNotReachHere();
3369 };
3370 __ br(acond, false, Assembler::pt, ok);
3371 __ delayed()->nop();
3372 }
3373 if (op->halt()) {
3374 const char* str = __ code_string(op->msg());
3375 __ stop(str);
3376 } else {
3377 breakpoint();
3378 }
3379 __ bind(ok);
3380 }
3381 #endif
3382
3383 void LIR_Assembler::peephole(LIR_List* lir) {
3384 LIR_OpList* inst = lir->instructions_list();
3385 for (int i = 0; i < inst->length(); i++) {
3386 LIR_Op* op = inst->at(i);
3387 switch (op->code()) {
3388 case lir_cond_float_branch:
3389 case lir_branch: {
3390 LIR_OpBranch* branch = op->as_OpBranch();
3391 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3392 LIR_Op* delay_op = NULL;
3393 // we'd like to be able to pull following instructions into
3394 // this slot but we don't know enough to do it safely yet so
3395 // only optimize block to block control flow.
3396 if (LIRFillDelaySlots && branch->block()) {
3397 LIR_Op* prev = inst->at(i - 1);
3398 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3399 // swap previous instruction into delay slot
3400 inst->at_put(i - 1, op);
3401 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3402 #ifndef PRODUCT
3403 if (LIRTracePeephole) {
3404 tty->print_cr("delayed");
3405 inst->at(i - 1)->print();
3406 inst->at(i)->print();
3407 tty->cr();
3408 }
3409 #endif
3410 continue;
3411 }
3412 }
3413
3414 if (!delay_op) {
3415 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3416 }
3417 inst->insert_before(i + 1, delay_op);
3418 break;
3419 }
3420 case lir_static_call:
3421 case lir_virtual_call:
3422 case lir_icvirtual_call:
3423 case lir_optvirtual_call:
3424 case lir_dynamic_call: {
3425 LIR_Op* prev = inst->at(i - 1);
3426 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3427 (op->code() != lir_virtual_call ||
3428 !prev->result_opr()->is_single_cpu() ||
3429 prev->result_opr()->as_register() != O0) &&
3430 LIR_Assembler::is_single_instruction(prev)) {
3431 // Only moves without info can be put into the delay slot.
3432 // Also don't allow the setup of the receiver in the delay
3433 // slot for vtable calls.
3434 inst->at_put(i - 1, op);
3435 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3436 #ifndef PRODUCT
3437 if (LIRTracePeephole) {
3438 tty->print_cr("delayed");
3439 inst->at(i - 1)->print();
3440 inst->at(i)->print();
3441 tty->cr();
3442 }
3443 #endif
3444 } else {
3445 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3446 inst->insert_before(i + 1, delay_op);
3447 i++;
3448 }
3449
3450 #if defined(TIERED) && !defined(_LP64)
3451 // fixup the return value from G1 to O0/O1 for long returns.
3452 // It's done here instead of in LIRGenerator because there's
3453 // such a mismatch between the single reg and double reg
3454 // calling convention.
3455 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3456 if (callop->result_opr() == FrameMap::out_long_opr) {
3457 LIR_OpJavaCall* call;
3458 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3459 for (int a = 0; a < arguments->length(); a++) {
3460 arguments[a] = callop->arguments()[a];
3461 }
3462 if (op->code() == lir_virtual_call) {
3463 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3464 callop->vtable_offset(), arguments, callop->info());
3465 } else {
3466 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3467 callop->addr(), arguments, callop->info());
3468 }
3469 inst->at_put(i - 1, call);
3470 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3471 T_LONG, lir_patch_none, NULL));
3472 }
3473 #endif
3474 break;
3475 }
3476 }
3477 }
3478 }
3479
3480 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3481 LIR_Address* addr = src->as_address_ptr();
3482
3483 assert(data == dest, "swap uses only 2 operands");
3484 assert (code == lir_xchg, "no xadd on sparc");
3485
3486 if (data->type() == T_INT) {
3487 __ swap(as_Address(addr), data->as_register());
3488 } else if (data->is_oop()) {
3489 Register obj = data->as_register();
3490 Register narrow = tmp->as_register();
3491 #ifdef _LP64
3492 assert(UseCompressedOops, "swap is 32bit only");
3493 __ encode_heap_oop(obj, narrow);
3494 __ swap(as_Address(addr), narrow);
3495 __ decode_heap_oop(narrow, obj);
3496 #else
3497 __ swap(as_Address(addr), obj);
3498 #endif
3499 } else {
3500 ShouldNotReachHere();
3501 }
3502 }
3503
3504 #undef __