1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/barrierSet.hpp"
39 #include "gc/shared/cardTableBarrierSet.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "vmreg_aarch64.inline.hpp"
46
47
48
49 #ifndef PRODUCT
50 #define COMMENT(x) do { __ block_comment(x); } while (0)
51 #else
52 #define COMMENT(x)
53 #endif
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rscratch2; // where the IC klass is cached
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == NULL) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == NULL) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == NULL) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 intptr_t addr_offset = intptr_t(addr->disp());
192 if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
193 return Address(base, addr_offset, Address::lsl(addr->scale()));
194 else {
195 __ mov(tmp, addr_offset);
196 return Address(base, tmp, Address::lsl(addr->scale()));
197 }
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216
217 void LIR_Assembler::osr_entry() {
218 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
219 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
220 ValueStack* entry_state = osr_entry->state();
221 int number_of_locks = entry_state->locks_size();
222
223 // we jump here if osr happens with the interpreter
224 // state set up to continue at the beginning of the
225 // loop that triggered osr - in particular, we have
226 // the following registers setup:
227 //
228 // r2: osr buffer
229 //
230
231 // build frame
232 ciMethod* m = compilation()->method();
233 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
234
235 // OSR buffer is
236 //
237 // locals[nlocals-1..0]
238 // monitors[0..number_of_locks]
239 //
240 // locals is a direct copy of the interpreter frame so in the osr buffer
241 // so first slot in the local array is the last local from the interpreter
242 // and last slot is local[0] (receiver) from the interpreter
243 //
244 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
245 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
246 // in the interpreter frame (the method lock if a sync method)
247
248 // Initialize monitors in the compiled activation.
249 // r2: pointer to osr buffer
250 //
251 // All other registers are dead at this point and the locals will be
252 // copied into place by code emitted in the IR.
253
254 Register OSR_buf = osrBufferPointer()->as_pointer_register();
255 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
256 int monitor_offset = BytesPerWord * method()->max_locals() +
257 (2 * BytesPerWord) * (number_of_locks - 1);
258 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
259 // the OSR buffer using 2 word entries: first the lock and then
260 // the oop.
261 for (int i = 0; i < number_of_locks; i++) {
262 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
263 #ifdef ASSERT
264 // verify the interpreter's monitor has a non-null object
265 {
266 Label L;
267 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
268 __ cbnz(rscratch1, L);
269 __ stop("locked object is NULL");
270 __ bind(L);
271 }
272 #endif
273 __ ldr(r19, Address(OSR_buf, slot_offset + 0));
274 __ str(r19, frame_map()->address_for_monitor_lock(i));
275 __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
276 __ str(r19, frame_map()->address_for_monitor_object(i));
277 }
278 }
279 }
280
281
282 // inline cache check; done before the frame is built.
283 int LIR_Assembler::check_icache() {
284 Register receiver = FrameMap::receiver_opr->as_register();
285 Register ic_klass = IC_Klass;
286 int start_offset = __ offset();
287 __ inline_cache_check(receiver, ic_klass);
288
289 // if icache check fails, then jump to runtime routine
290 // Note: RECEIVER must still contain the receiver!
291 Label dont;
292 __ br(Assembler::EQ, dont);
293 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
294
295 // We align the verified entry point unless the method body
296 // (including its inline cache check) will fit in a single 64-byte
297 // icache line.
298 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
299 // force alignment after the cache check.
300 __ align(CodeEntryAlignment);
301 }
302
303 __ bind(dont);
304 return start_offset;
305 }
306
307 void LIR_Assembler::clinit_barrier(ciMethod* method) {
308 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
309 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
310
311 Label L_skip_barrier;
312
313 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
314 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
315 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
316 __ bind(L_skip_barrier);
317 }
318
319 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
320 if (o == NULL) {
321 __ mov(reg, zr);
322 } else {
323 __ movoop(reg, o, /*immediate*/true);
324 }
325 }
326
327 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
328 address target = NULL;
329 relocInfo::relocType reloc_type = relocInfo::none;
330
331 switch (patching_id(info)) {
332 case PatchingStub::access_field_id:
333 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
334 reloc_type = relocInfo::section_word_type;
335 break;
336 case PatchingStub::load_klass_id:
337 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
338 reloc_type = relocInfo::metadata_type;
339 break;
340 case PatchingStub::load_mirror_id:
341 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
342 reloc_type = relocInfo::oop_type;
343 break;
344 case PatchingStub::load_appendix_id:
345 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
346 reloc_type = relocInfo::oop_type;
347 break;
348 default: ShouldNotReachHere();
349 }
350
351 __ far_call(RuntimeAddress(target));
352 add_call_info_here(info);
353 }
354
355 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
356 deoptimize_trap(info);
357 }
358
359
360 // This specifies the rsp decrement needed to build the frame
361 int LIR_Assembler::initial_frame_size_in_bytes() const {
362 // if rounding, must let FrameMap know!
363
364 // The frame_map records size in slots (32bit word)
365
366 // subtract two words to account for return address and link
367 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
368 }
369
370
371 int LIR_Assembler::emit_exception_handler() {
372 // if the last instruction is a call (typically to do a throw which
373 // is coming at the end after block reordering) the return address
374 // must still point into the code area in order to avoid assertion
375 // failures when searching for the corresponding bci => add a nop
376 // (was bug 5/14/1999 - gri)
377 __ nop();
378
379 // generate code for exception handler
380 address handler_base = __ start_a_stub(exception_handler_size());
381 if (handler_base == NULL) {
382 // not enough space left for the handler
383 bailout("exception handler overflow");
384 return -1;
385 }
386
387 int offset = code_offset();
388
389 // the exception oop and pc are in r0, and r3
390 // no other registers need to be preserved, so invalidate them
391 __ invalidate_registers(false, true, true, false, true, true);
392
393 // check that there is really an exception
394 __ verify_not_null_oop(r0);
395
396 // search an exception handler (r0: exception oop, r3: throwing pc)
397 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
398 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
399 __ end_a_stub();
400
401 return offset;
402 }
403
404
405 // Emit the code to remove the frame from the stack in the exception
406 // unwind path.
407 int LIR_Assembler::emit_unwind_handler() {
408 #ifndef PRODUCT
409 if (CommentedAssembly) {
410 _masm->block_comment("Unwind handler");
411 }
412 #endif
413
414 int offset = code_offset();
415
416 // Fetch the exception from TLS and clear out exception related thread state
417 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
418 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
419 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
420
421 __ bind(_unwind_handler_entry);
422 __ verify_not_null_oop(r0);
423 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
424 __ mov(r19, r0); // Preserve the exception
425 }
426
427 // Preform needed unlocking
428 MonitorExitStub* stub = NULL;
429 if (method()->is_synchronized()) {
430 monitor_address(0, FrameMap::r0_opr);
431 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
432 __ unlock_object(r5, r4, r0, *stub->entry());
433 __ bind(*stub->continuation());
434 }
435
436 if (compilation()->env()->dtrace_method_probes()) {
437 __ call_Unimplemented();
438 #if 0
439 __ movptr(Address(rsp, 0), rax);
440 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
441 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
442 #endif
443 }
444
445 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
446 __ mov(r0, r19); // Restore the exception
447 }
448
449 // remove the activation and dispatch to the unwind handler
450 __ block_comment("remove_frame and dispatch to the unwind handler");
451 __ remove_frame(initial_frame_size_in_bytes());
452 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
453
454 // Emit the slow path assembly
455 if (stub != NULL) {
456 stub->emit_code(this);
457 }
458
459 return offset;
460 }
461
462
463 int LIR_Assembler::emit_deopt_handler() {
464 // if the last instruction is a call (typically to do a throw which
465 // is coming at the end after block reordering) the return address
466 // must still point into the code area in order to avoid assertion
467 // failures when searching for the corresponding bci => add a nop
468 // (was bug 5/14/1999 - gri)
469 __ nop();
470
471 // generate code for exception handler
472 address handler_base = __ start_a_stub(deopt_handler_size());
473 if (handler_base == NULL) {
474 // not enough space left for the handler
475 bailout("deopt handler overflow");
476 return -1;
477 }
478
479 int offset = code_offset();
480
481 __ adr(lr, pc());
482 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
483 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
484 __ end_a_stub();
485
486 return offset;
487 }
488
489 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
490 _masm->code_section()->relocate(adr, relocInfo::poll_type);
491 int pc_offset = code_offset();
492 flush_debug_info(pc_offset);
493 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
494 if (info->exception_handlers() != NULL) {
495 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
496 }
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
501
502 // Pop the stack before the safepoint code
503 __ remove_frame(initial_frame_size_in_bytes());
504
505 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
506 __ reserved_stack_check();
507 }
508
509 address polling_page(os::get_polling_page());
510 __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
511 __ ret(lr);
512 }
513
514 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
515 address polling_page(os::get_polling_page());
516 guarantee(info != NULL, "Shouldn't be NULL");
517 assert(os::is_poll_address(polling_page), "should be");
518 __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
519 add_debug_info_for_branch(info); // This isn't just debug info:
520 // it's the oop map
521 __ read_polling_page(rscratch1, relocInfo::poll_type);
522 return __ offset();
523 }
524
525
526 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
527 if (from_reg == r31_sp)
528 from_reg = sp;
529 if (to_reg == r31_sp)
530 to_reg = sp;
531 __ mov(to_reg, from_reg);
532 }
533
534 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
535
536
537 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
538 assert(src->is_constant(), "should not call otherwise");
539 assert(dest->is_register(), "should not call otherwise");
540 LIR_Const* c = src->as_constant_ptr();
541
542 switch (c->type()) {
543 case T_INT: {
544 assert(patch_code == lir_patch_none, "no patching handled here");
545 __ movw(dest->as_register(), c->as_jint());
546 break;
547 }
548
549 case T_ADDRESS: {
550 assert(patch_code == lir_patch_none, "no patching handled here");
551 __ mov(dest->as_register(), c->as_jint());
552 break;
553 }
554
555 case T_LONG: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
558 break;
559 }
560
561 case T_OBJECT: {
562 if (patch_code == lir_patch_none) {
563 jobject2reg(c->as_jobject(), dest->as_register());
564 } else {
565 jobject2reg_with_patching(dest->as_register(), info);
566 }
567 break;
568 }
569
570 case T_METADATA: {
571 if (patch_code != lir_patch_none) {
572 klass2reg_with_patching(dest->as_register(), info);
573 } else {
574 __ mov_metadata(dest->as_register(), c->as_metadata());
575 }
576 break;
577 }
578
579 case T_FLOAT: {
580 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
581 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
582 } else {
583 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
584 __ ldrs(dest->as_float_reg(), Address(rscratch1));
585 }
586 break;
587 }
588
589 case T_DOUBLE: {
590 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
591 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
592 } else {
593 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
594 __ ldrd(dest->as_double_reg(), Address(rscratch1));
595 }
596 break;
597 }
598
599 default:
600 ShouldNotReachHere();
601 }
602 }
603
604 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
605 LIR_Const* c = src->as_constant_ptr();
606 switch (c->type()) {
607 case T_OBJECT:
608 {
609 if (! c->as_jobject())
610 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
611 else {
612 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
613 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
614 }
615 }
616 break;
617 case T_ADDRESS:
618 {
619 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
620 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
621 }
622 case T_INT:
623 case T_FLOAT:
624 {
625 Register reg = zr;
626 if (c->as_jint_bits() == 0)
627 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
628 else {
629 __ movw(rscratch1, c->as_jint_bits());
630 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
631 }
632 }
633 break;
634 case T_LONG:
635 case T_DOUBLE:
636 {
637 Register reg = zr;
638 if (c->as_jlong_bits() == 0)
639 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
640 lo_word_offset_in_bytes));
641 else {
642 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
643 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
644 lo_word_offset_in_bytes));
645 }
646 }
647 break;
648 default:
649 ShouldNotReachHere();
650 }
651 }
652
653 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
654 assert(src->is_constant(), "should not call otherwise");
655 LIR_Const* c = src->as_constant_ptr();
656 LIR_Address* to_addr = dest->as_address_ptr();
657
658 void (Assembler::* insn)(Register Rt, const Address &adr);
659
660 switch (type) {
661 case T_ADDRESS:
662 assert(c->as_jint() == 0, "should be");
663 insn = &Assembler::str;
664 break;
665 case T_LONG:
666 assert(c->as_jlong() == 0, "should be");
667 insn = &Assembler::str;
668 break;
669 case T_INT:
670 assert(c->as_jint() == 0, "should be");
671 insn = &Assembler::strw;
672 break;
673 case T_OBJECT:
674 case T_ARRAY:
675 assert(c->as_jobject() == 0, "should be");
676 if (UseCompressedOops && !wide) {
677 insn = &Assembler::strw;
678 } else {
679 insn = &Assembler::str;
680 }
681 break;
682 case T_CHAR:
683 case T_SHORT:
684 assert(c->as_jint() == 0, "should be");
685 insn = &Assembler::strh;
686 break;
687 case T_BOOLEAN:
688 case T_BYTE:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::strb;
691 break;
692 default:
693 ShouldNotReachHere();
694 insn = &Assembler::str; // unreachable
695 }
696
697 if (info) add_debug_info_for_null_check_here(info);
698 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
699 }
700
701 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
702 assert(src->is_register(), "should not call otherwise");
703 assert(dest->is_register(), "should not call otherwise");
704
705 // move between cpu-registers
706 if (dest->is_single_cpu()) {
707 if (src->type() == T_LONG) {
708 // Can do LONG -> OBJECT
709 move_regs(src->as_register_lo(), dest->as_register());
710 return;
711 }
712 assert(src->is_single_cpu(), "must match");
713 if (src->type() == T_OBJECT) {
714 __ verify_oop(src->as_register());
715 }
716 move_regs(src->as_register(), dest->as_register());
717
718 } else if (dest->is_double_cpu()) {
719 if (is_reference_type(src->type())) {
720 // Surprising to me but we can see move of a long to t_object
721 __ verify_oop(src->as_register());
722 move_regs(src->as_register(), dest->as_register_lo());
723 return;
724 }
725 assert(src->is_double_cpu(), "must match");
726 Register f_lo = src->as_register_lo();
727 Register f_hi = src->as_register_hi();
728 Register t_lo = dest->as_register_lo();
729 Register t_hi = dest->as_register_hi();
730 assert(f_hi == f_lo, "must be same");
731 assert(t_hi == t_lo, "must be same");
732 move_regs(f_lo, t_lo);
733
734 } else if (dest->is_single_fpu()) {
735 __ fmovs(dest->as_float_reg(), src->as_float_reg());
736
737 } else if (dest->is_double_fpu()) {
738 __ fmovd(dest->as_double_reg(), src->as_double_reg());
739
740 } else {
741 ShouldNotReachHere();
742 }
743 }
744
745 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
746 if (src->is_single_cpu()) {
747 if (is_reference_type(type)) {
748 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
749 __ verify_oop(src->as_register());
750 } else if (type == T_METADATA || type == T_DOUBLE) {
751 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
752 } else {
753 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
754 }
755
756 } else if (src->is_double_cpu()) {
757 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
758 __ str(src->as_register_lo(), dest_addr_LO);
759
760 } else if (src->is_single_fpu()) {
761 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
762 __ strs(src->as_float_reg(), dest_addr);
763
764 } else if (src->is_double_fpu()) {
765 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
766 __ strd(src->as_double_reg(), dest_addr);
767
768 } else {
769 ShouldNotReachHere();
770 }
771
772 }
773
774
775 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
776 LIR_Address* to_addr = dest->as_address_ptr();
777 PatchingStub* patch = NULL;
778 Register compressed_src = rscratch1;
779
780 if (patch_code != lir_patch_none) {
781 deoptimize_trap(info);
782 return;
783 }
784
785 if (is_reference_type(type)) {
786 __ verify_oop(src->as_register());
787
788 if (UseCompressedOops && !wide) {
789 __ encode_heap_oop(compressed_src, src->as_register());
790 } else {
791 compressed_src = src->as_register();
792 }
793 }
794
795 int null_check_here = code_offset();
796 switch (type) {
797 case T_FLOAT: {
798 __ strs(src->as_float_reg(), as_Address(to_addr));
799 break;
800 }
801
802 case T_DOUBLE: {
803 __ strd(src->as_double_reg(), as_Address(to_addr));
804 break;
805 }
806
807 case T_ARRAY: // fall through
808 case T_OBJECT: // fall through
809 if (UseCompressedOops && !wide) {
810 __ strw(compressed_src, as_Address(to_addr, rscratch2));
811 } else {
812 __ str(compressed_src, as_Address(to_addr));
813 }
814 break;
815 case T_METADATA:
816 // We get here to store a method pointer to the stack to pass to
817 // a dtrace runtime call. This can't work on 64 bit with
818 // compressed klass ptrs: T_METADATA can be a compressed klass
819 // ptr or a 64 bit method pointer.
820 ShouldNotReachHere();
821 __ str(src->as_register(), as_Address(to_addr));
822 break;
823 case T_ADDRESS:
824 __ str(src->as_register(), as_Address(to_addr));
825 break;
826 case T_INT:
827 __ strw(src->as_register(), as_Address(to_addr));
828 break;
829
830 case T_LONG: {
831 __ str(src->as_register_lo(), as_Address_lo(to_addr));
832 break;
833 }
834
835 case T_BYTE: // fall through
836 case T_BOOLEAN: {
837 __ strb(src->as_register(), as_Address(to_addr));
838 break;
839 }
840
841 case T_CHAR: // fall through
842 case T_SHORT:
843 __ strh(src->as_register(), as_Address(to_addr));
844 break;
845
846 default:
847 ShouldNotReachHere();
848 }
849 if (info != NULL) {
850 add_debug_info_for_null_check(null_check_here, info);
851 }
852 }
853
854
855 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
856 assert(src->is_stack(), "should not call otherwise");
857 assert(dest->is_register(), "should not call otherwise");
858
859 if (dest->is_single_cpu()) {
860 if (is_reference_type(type)) {
861 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
862 __ verify_oop(dest->as_register());
863 } else if (type == T_METADATA) {
864 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
865 } else {
866 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
867 }
868
869 } else if (dest->is_double_cpu()) {
870 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
871 __ ldr(dest->as_register_lo(), src_addr_LO);
872
873 } else if (dest->is_single_fpu()) {
874 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
875 __ ldrs(dest->as_float_reg(), src_addr);
876
877 } else if (dest->is_double_fpu()) {
878 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
879 __ ldrd(dest->as_double_reg(), src_addr);
880
881 } else {
882 ShouldNotReachHere();
883 }
884 }
885
886
887 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
888 address target = NULL;
889 relocInfo::relocType reloc_type = relocInfo::none;
890
891 switch (patching_id(info)) {
892 case PatchingStub::access_field_id:
893 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
894 reloc_type = relocInfo::section_word_type;
895 break;
896 case PatchingStub::load_klass_id:
897 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
898 reloc_type = relocInfo::metadata_type;
899 break;
900 case PatchingStub::load_mirror_id:
901 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
902 reloc_type = relocInfo::oop_type;
903 break;
904 case PatchingStub::load_appendix_id:
905 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
906 reloc_type = relocInfo::oop_type;
907 break;
908 default: ShouldNotReachHere();
909 }
910
911 __ far_call(RuntimeAddress(target));
912 add_call_info_here(info);
913 }
914
915 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
916
917 LIR_Opr temp;
918 if (type == T_LONG || type == T_DOUBLE)
919 temp = FrameMap::rscratch1_long_opr;
920 else
921 temp = FrameMap::rscratch1_opr;
922
923 stack2reg(src, temp, src->type());
924 reg2stack(temp, dest, dest->type(), false);
925 }
926
927
928 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
929 LIR_Address* addr = src->as_address_ptr();
930 LIR_Address* from_addr = src->as_address_ptr();
931
932 if (addr->base()->type() == T_OBJECT) {
933 __ verify_oop(addr->base()->as_pointer_register());
934 }
935
936 if (patch_code != lir_patch_none) {
937 deoptimize_trap(info);
938 return;
939 }
940
941 if (info != NULL) {
942 add_debug_info_for_null_check_here(info);
943 }
944 int null_check_here = code_offset();
945 switch (type) {
946 case T_FLOAT: {
947 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
948 break;
949 }
950
951 case T_DOUBLE: {
952 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
953 break;
954 }
955
956 case T_ARRAY: // fall through
957 case T_OBJECT: // fall through
958 if (UseCompressedOops && !wide) {
959 __ ldrw(dest->as_register(), as_Address(from_addr));
960 } else {
961 __ ldr(dest->as_register(), as_Address(from_addr));
962 }
963 break;
964 case T_METADATA:
965 // We get here to store a method pointer to the stack to pass to
966 // a dtrace runtime call. This can't work on 64 bit with
967 // compressed klass ptrs: T_METADATA can be a compressed klass
968 // ptr or a 64 bit method pointer.
969 ShouldNotReachHere();
970 __ ldr(dest->as_register(), as_Address(from_addr));
971 break;
972 case T_ADDRESS:
973 // FIXME: OMG this is a horrible kludge. Any offset from an
974 // address that matches klass_offset_in_bytes() will be loaded
975 // as a word, not a long.
976 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
977 __ ldrw(dest->as_register(), as_Address(from_addr));
978 } else {
979 __ ldr(dest->as_register(), as_Address(from_addr));
980 }
981 break;
982 case T_INT:
983 __ ldrw(dest->as_register(), as_Address(from_addr));
984 break;
985
986 case T_LONG: {
987 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
988 break;
989 }
990
991 case T_BYTE:
992 __ ldrsb(dest->as_register(), as_Address(from_addr));
993 break;
994 case T_BOOLEAN: {
995 __ ldrb(dest->as_register(), as_Address(from_addr));
996 break;
997 }
998
999 case T_CHAR:
1000 __ ldrh(dest->as_register(), as_Address(from_addr));
1001 break;
1002 case T_SHORT:
1003 __ ldrsh(dest->as_register(), as_Address(from_addr));
1004 break;
1005
1006 default:
1007 ShouldNotReachHere();
1008 }
1009
1010 if (is_reference_type(type)) {
1011 if (UseCompressedOops && !wide) {
1012 __ decode_heap_oop(dest->as_register());
1013 }
1014
1015 if (!UseZGC) {
1016 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1017 __ verify_oop(dest->as_register());
1018 }
1019 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1020 if (UseCompressedClassPointers) {
1021 __ decode_klass_not_null(dest->as_register());
1022 }
1023 }
1024 }
1025
1026
1027 int LIR_Assembler::array_element_size(BasicType type) const {
1028 int elem_size = type2aelembytes(type);
1029 return exact_log2(elem_size);
1030 }
1031
1032
1033 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1034 switch (op->code()) {
1035 case lir_idiv:
1036 case lir_irem:
1037 arithmetic_idiv(op->code(),
1038 op->in_opr1(),
1039 op->in_opr2(),
1040 op->in_opr3(),
1041 op->result_opr(),
1042 op->info());
1043 break;
1044 case lir_fmad:
1045 __ fmaddd(op->result_opr()->as_double_reg(),
1046 op->in_opr1()->as_double_reg(),
1047 op->in_opr2()->as_double_reg(),
1048 op->in_opr3()->as_double_reg());
1049 break;
1050 case lir_fmaf:
1051 __ fmadds(op->result_opr()->as_float_reg(),
1052 op->in_opr1()->as_float_reg(),
1053 op->in_opr2()->as_float_reg(),
1054 op->in_opr3()->as_float_reg());
1055 break;
1056 default: ShouldNotReachHere(); break;
1057 }
1058 }
1059
1060 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1061 #ifdef ASSERT
1062 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1063 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1064 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1065 #endif
1066
1067 if (op->cond() == lir_cond_always) {
1068 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1069 __ b(*(op->label()));
1070 } else {
1071 Assembler::Condition acond;
1072 if (op->code() == lir_cond_float_branch) {
1073 bool is_unordered = (op->ublock() == op->block());
1074 // Assembler::EQ does not permit unordered branches, so we add
1075 // another branch here. Likewise, Assembler::NE does not permit
1076 // ordered branches.
1077 if ((is_unordered && op->cond() == lir_cond_equal)
1078 || (!is_unordered && op->cond() == lir_cond_notEqual))
1079 __ br(Assembler::VS, *(op->ublock()->label()));
1080 switch(op->cond()) {
1081 case lir_cond_equal: acond = Assembler::EQ; break;
1082 case lir_cond_notEqual: acond = Assembler::NE; break;
1083 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1084 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1085 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1086 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1087 default: ShouldNotReachHere();
1088 acond = Assembler::EQ; // unreachable
1089 }
1090 } else {
1091 switch (op->cond()) {
1092 case lir_cond_equal: acond = Assembler::EQ; break;
1093 case lir_cond_notEqual: acond = Assembler::NE; break;
1094 case lir_cond_less: acond = Assembler::LT; break;
1095 case lir_cond_lessEqual: acond = Assembler::LE; break;
1096 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1097 case lir_cond_greater: acond = Assembler::GT; break;
1098 case lir_cond_belowEqual: acond = Assembler::LS; break;
1099 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1100 default: ShouldNotReachHere();
1101 acond = Assembler::EQ; // unreachable
1102 }
1103 }
1104 __ br(acond,*(op->label()));
1105 }
1106 }
1107
1108
1109
1110 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1111 LIR_Opr src = op->in_opr();
1112 LIR_Opr dest = op->result_opr();
1113
1114 switch (op->bytecode()) {
1115 case Bytecodes::_i2f:
1116 {
1117 __ scvtfws(dest->as_float_reg(), src->as_register());
1118 break;
1119 }
1120 case Bytecodes::_i2d:
1121 {
1122 __ scvtfwd(dest->as_double_reg(), src->as_register());
1123 break;
1124 }
1125 case Bytecodes::_l2d:
1126 {
1127 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1128 break;
1129 }
1130 case Bytecodes::_l2f:
1131 {
1132 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1133 break;
1134 }
1135 case Bytecodes::_f2d:
1136 {
1137 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1138 break;
1139 }
1140 case Bytecodes::_d2f:
1141 {
1142 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1143 break;
1144 }
1145 case Bytecodes::_i2c:
1146 {
1147 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1148 break;
1149 }
1150 case Bytecodes::_i2l:
1151 {
1152 __ sxtw(dest->as_register_lo(), src->as_register());
1153 break;
1154 }
1155 case Bytecodes::_i2s:
1156 {
1157 __ sxth(dest->as_register(), src->as_register());
1158 break;
1159 }
1160 case Bytecodes::_i2b:
1161 {
1162 __ sxtb(dest->as_register(), src->as_register());
1163 break;
1164 }
1165 case Bytecodes::_l2i:
1166 {
1167 _masm->block_comment("FIXME: This could be a no-op");
1168 __ uxtw(dest->as_register(), src->as_register_lo());
1169 break;
1170 }
1171 case Bytecodes::_d2l:
1172 {
1173 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1174 break;
1175 }
1176 case Bytecodes::_f2i:
1177 {
1178 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1179 break;
1180 }
1181 case Bytecodes::_f2l:
1182 {
1183 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1184 break;
1185 }
1186 case Bytecodes::_d2i:
1187 {
1188 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1189 break;
1190 }
1191 default: ShouldNotReachHere();
1192 }
1193 }
1194
1195 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1196 if (op->init_check()) {
1197 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1198 InstanceKlass::init_state_offset()));
1199 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1200 add_debug_info_for_null_check_here(op->stub()->info());
1201 __ br(Assembler::NE, *op->stub()->entry());
1202 }
1203 __ allocate_object(op->obj()->as_register(),
1204 op->tmp1()->as_register(),
1205 op->tmp2()->as_register(),
1206 op->header_size(),
1207 op->object_size(),
1208 op->klass()->as_register(),
1209 *op->stub()->entry());
1210 __ bind(*op->stub()->continuation());
1211 }
1212
1213 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1214 Register len = op->len()->as_register();
1215 __ uxtw(len, len);
1216
1217 if (UseSlowPath ||
1218 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1219 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1220 __ b(*op->stub()->entry());
1221 } else {
1222 Register tmp1 = op->tmp1()->as_register();
1223 Register tmp2 = op->tmp2()->as_register();
1224 Register tmp3 = op->tmp3()->as_register();
1225 if (len == tmp1) {
1226 tmp1 = tmp3;
1227 } else if (len == tmp2) {
1228 tmp2 = tmp3;
1229 } else if (len == tmp3) {
1230 // everything is ok
1231 } else {
1232 __ mov(tmp3, len);
1233 }
1234 __ allocate_array(op->obj()->as_register(),
1235 len,
1236 tmp1,
1237 tmp2,
1238 arrayOopDesc::header_size(op->type()),
1239 array_element_size(op->type()),
1240 op->klass()->as_register(),
1241 *op->stub()->entry());
1242 }
1243 __ bind(*op->stub()->continuation());
1244 }
1245
1246 void LIR_Assembler::type_profile_helper(Register mdo,
1247 ciMethodData *md, ciProfileData *data,
1248 Register recv, Label* update_done) {
1249 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1250 Label next_test;
1251 // See if the receiver is receiver[n].
1252 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1253 __ ldr(rscratch1, Address(rscratch2));
1254 __ cmp(recv, rscratch1);
1255 __ br(Assembler::NE, next_test);
1256 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1257 __ addptr(data_addr, DataLayout::counter_increment);
1258 __ b(*update_done);
1259 __ bind(next_test);
1260 }
1261
1262 // Didn't find receiver; find next empty slot and fill it in
1263 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1264 Label next_test;
1265 __ lea(rscratch2,
1266 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1267 Address recv_addr(rscratch2);
1268 __ ldr(rscratch1, recv_addr);
1269 __ cbnz(rscratch1, next_test);
1270 __ str(recv, recv_addr);
1271 __ mov(rscratch1, DataLayout::counter_increment);
1272 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1273 __ str(rscratch1, Address(rscratch2));
1274 __ b(*update_done);
1275 __ bind(next_test);
1276 }
1277 }
1278
1279 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1280 // we always need a stub for the failure case.
1281 CodeStub* stub = op->stub();
1282 Register obj = op->object()->as_register();
1283 Register k_RInfo = op->tmp1()->as_register();
1284 Register klass_RInfo = op->tmp2()->as_register();
1285 Register dst = op->result_opr()->as_register();
1286 ciKlass* k = op->klass();
1287 Register Rtmp1 = noreg;
1288
1289 // check if it needs to be profiled
1290 ciMethodData* md;
1291 ciProfileData* data;
1292
1293 const bool should_profile = op->should_profile();
1294
1295 if (should_profile) {
1296 ciMethod* method = op->profiled_method();
1297 assert(method != NULL, "Should have method");
1298 int bci = op->profiled_bci();
1299 md = method->method_data_or_null();
1300 assert(md != NULL, "Sanity");
1301 data = md->bci_to_data(bci);
1302 assert(data != NULL, "need data for type check");
1303 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1304 }
1305 Label profile_cast_success, profile_cast_failure;
1306 Label *success_target = should_profile ? &profile_cast_success : success;
1307 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1308
1309 if (obj == k_RInfo) {
1310 k_RInfo = dst;
1311 } else if (obj == klass_RInfo) {
1312 klass_RInfo = dst;
1313 }
1314 if (k->is_loaded() && !UseCompressedClassPointers) {
1315 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1316 } else {
1317 Rtmp1 = op->tmp3()->as_register();
1318 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1319 }
1320
1321 assert_different_registers(obj, k_RInfo, klass_RInfo);
1322
1323 if (should_profile) {
1324 Label not_null;
1325 __ cbnz(obj, not_null);
1326 // Object is null; update MDO and exit
1327 Register mdo = klass_RInfo;
1328 __ mov_metadata(mdo, md->constant_encoding());
1329 Address data_addr
1330 = __ form_address(rscratch2, mdo,
1331 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1332 0);
1333 __ ldrb(rscratch1, data_addr);
1334 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1335 __ strb(rscratch1, data_addr);
1336 __ b(*obj_is_null);
1337 __ bind(not_null);
1338 } else {
1339 __ cbz(obj, *obj_is_null);
1340 }
1341
1342 if (!k->is_loaded()) {
1343 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1344 } else {
1345 __ mov_metadata(k_RInfo, k->constant_encoding());
1346 }
1347 __ verify_oop(obj);
1348
1349 if (op->fast_check()) {
1350 // get object class
1351 // not a safepoint as obj null check happens earlier
1352 __ load_klass(rscratch1, obj);
1353 __ cmp( rscratch1, k_RInfo);
1354
1355 __ br(Assembler::NE, *failure_target);
1356 // successful cast, fall through to profile or jump
1357 } else {
1358 // get object class
1359 // not a safepoint as obj null check happens earlier
1360 __ load_klass(klass_RInfo, obj);
1361 if (k->is_loaded()) {
1362 // See if we get an immediate positive hit
1363 __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1364 __ cmp(k_RInfo, rscratch1);
1365 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1366 __ br(Assembler::NE, *failure_target);
1367 // successful cast, fall through to profile or jump
1368 } else {
1369 // See if we get an immediate positive hit
1370 __ br(Assembler::EQ, *success_target);
1371 // check for self
1372 __ cmp(klass_RInfo, k_RInfo);
1373 __ br(Assembler::EQ, *success_target);
1374
1375 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1376 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1377 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1378 // result is a boolean
1379 __ cbzw(klass_RInfo, *failure_target);
1380 // successful cast, fall through to profile or jump
1381 }
1382 } else {
1383 // perform the fast part of the checking logic
1384 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1385 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1386 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1387 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1388 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1389 // result is a boolean
1390 __ cbz(k_RInfo, *failure_target);
1391 // successful cast, fall through to profile or jump
1392 }
1393 }
1394 if (should_profile) {
1395 Register mdo = klass_RInfo, recv = k_RInfo;
1396 __ bind(profile_cast_success);
1397 __ mov_metadata(mdo, md->constant_encoding());
1398 __ load_klass(recv, obj);
1399 Label update_done;
1400 type_profile_helper(mdo, md, data, recv, success);
1401 __ b(*success);
1402
1403 __ bind(profile_cast_failure);
1404 __ mov_metadata(mdo, md->constant_encoding());
1405 Address counter_addr
1406 = __ form_address(rscratch2, mdo,
1407 md->byte_offset_of_slot(data, CounterData::count_offset()),
1408 0);
1409 __ ldr(rscratch1, counter_addr);
1410 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1411 __ str(rscratch1, counter_addr);
1412 __ b(*failure);
1413 }
1414 __ b(*success);
1415 }
1416
1417
1418 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1419 const bool should_profile = op->should_profile();
1420
1421 LIR_Code code = op->code();
1422 if (code == lir_store_check) {
1423 Register value = op->object()->as_register();
1424 Register array = op->array()->as_register();
1425 Register k_RInfo = op->tmp1()->as_register();
1426 Register klass_RInfo = op->tmp2()->as_register();
1427 Register Rtmp1 = op->tmp3()->as_register();
1428
1429 CodeStub* stub = op->stub();
1430
1431 // check if it needs to be profiled
1432 ciMethodData* md;
1433 ciProfileData* data;
1434
1435 if (should_profile) {
1436 ciMethod* method = op->profiled_method();
1437 assert(method != NULL, "Should have method");
1438 int bci = op->profiled_bci();
1439 md = method->method_data_or_null();
1440 assert(md != NULL, "Sanity");
1441 data = md->bci_to_data(bci);
1442 assert(data != NULL, "need data for type check");
1443 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1444 }
1445 Label profile_cast_success, profile_cast_failure, done;
1446 Label *success_target = should_profile ? &profile_cast_success : &done;
1447 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1448
1449 if (should_profile) {
1450 Label not_null;
1451 __ cbnz(value, not_null);
1452 // Object is null; update MDO and exit
1453 Register mdo = klass_RInfo;
1454 __ mov_metadata(mdo, md->constant_encoding());
1455 Address data_addr
1456 = __ form_address(rscratch2, mdo,
1457 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1458 0);
1459 __ ldrb(rscratch1, data_addr);
1460 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1461 __ strb(rscratch1, data_addr);
1462 __ b(done);
1463 __ bind(not_null);
1464 } else {
1465 __ cbz(value, done);
1466 }
1467
1468 add_debug_info_for_null_check_here(op->info_for_exception());
1469 __ load_klass(k_RInfo, array);
1470 __ load_klass(klass_RInfo, value);
1471
1472 // get instance klass (it's already uncompressed)
1473 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1474 // perform the fast part of the checking logic
1475 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1476 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1477 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1478 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1479 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1480 // result is a boolean
1481 __ cbzw(k_RInfo, *failure_target);
1482 // fall through to the success case
1483
1484 if (should_profile) {
1485 Register mdo = klass_RInfo, recv = k_RInfo;
1486 __ bind(profile_cast_success);
1487 __ mov_metadata(mdo, md->constant_encoding());
1488 __ load_klass(recv, value);
1489 Label update_done;
1490 type_profile_helper(mdo, md, data, recv, &done);
1491 __ b(done);
1492
1493 __ bind(profile_cast_failure);
1494 __ mov_metadata(mdo, md->constant_encoding());
1495 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1496 __ lea(rscratch2, counter_addr);
1497 __ ldr(rscratch1, Address(rscratch2));
1498 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1499 __ str(rscratch1, Address(rscratch2));
1500 __ b(*stub->entry());
1501 }
1502
1503 __ bind(done);
1504 } else if (code == lir_checkcast) {
1505 Register obj = op->object()->as_register();
1506 Register dst = op->result_opr()->as_register();
1507 Label success;
1508 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1509 __ bind(success);
1510 if (dst != obj) {
1511 __ mov(dst, obj);
1512 }
1513 } else if (code == lir_instanceof) {
1514 Register obj = op->object()->as_register();
1515 Register dst = op->result_opr()->as_register();
1516 Label success, failure, done;
1517 emit_typecheck_helper(op, &success, &failure, &failure);
1518 __ bind(failure);
1519 __ mov(dst, zr);
1520 __ b(done);
1521 __ bind(success);
1522 __ mov(dst, 1);
1523 __ bind(done);
1524 } else {
1525 ShouldNotReachHere();
1526 }
1527 }
1528
1529 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1530 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1531 __ cset(rscratch1, Assembler::NE);
1532 __ membar(__ AnyAny);
1533 }
1534
1535 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1536 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1537 __ cset(rscratch1, Assembler::NE);
1538 __ membar(__ AnyAny);
1539 }
1540
1541
1542 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1543 assert(VM_Version::supports_cx8(), "wrong machine");
1544 Register addr;
1545 if (op->addr()->is_register()) {
1546 addr = as_reg(op->addr());
1547 } else {
1548 assert(op->addr()->is_address(), "what else?");
1549 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1550 assert(addr_ptr->disp() == 0, "need 0 disp");
1551 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1552 addr = as_reg(addr_ptr->base());
1553 }
1554 Register newval = as_reg(op->new_value());
1555 Register cmpval = as_reg(op->cmp_value());
1556
1557 if (op->code() == lir_cas_obj) {
1558 if (UseCompressedOops) {
1559 Register t1 = op->tmp1()->as_register();
1560 assert(op->tmp1()->is_valid(), "must be");
1561 __ encode_heap_oop(t1, cmpval);
1562 cmpval = t1;
1563 __ encode_heap_oop(rscratch2, newval);
1564 newval = rscratch2;
1565 casw(addr, newval, cmpval);
1566 } else {
1567 casl(addr, newval, cmpval);
1568 }
1569 } else if (op->code() == lir_cas_int) {
1570 casw(addr, newval, cmpval);
1571 } else {
1572 casl(addr, newval, cmpval);
1573 }
1574 }
1575
1576
1577 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1578
1579 Assembler::Condition acond, ncond;
1580 switch (condition) {
1581 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1582 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1583 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1584 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1585 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1586 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1587 case lir_cond_belowEqual:
1588 case lir_cond_aboveEqual:
1589 default: ShouldNotReachHere();
1590 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1591 }
1592
1593 assert(result->is_single_cpu() || result->is_double_cpu(),
1594 "expect single register for result");
1595 if (opr1->is_constant() && opr2->is_constant()
1596 && opr1->type() == T_INT && opr2->type() == T_INT) {
1597 jint val1 = opr1->as_jint();
1598 jint val2 = opr2->as_jint();
1599 if (val1 == 0 && val2 == 1) {
1600 __ cset(result->as_register(), ncond);
1601 return;
1602 } else if (val1 == 1 && val2 == 0) {
1603 __ cset(result->as_register(), acond);
1604 return;
1605 }
1606 }
1607
1608 if (opr1->is_constant() && opr2->is_constant()
1609 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1610 jlong val1 = opr1->as_jlong();
1611 jlong val2 = opr2->as_jlong();
1612 if (val1 == 0 && val2 == 1) {
1613 __ cset(result->as_register_lo(), ncond);
1614 return;
1615 } else if (val1 == 1 && val2 == 0) {
1616 __ cset(result->as_register_lo(), acond);
1617 return;
1618 }
1619 }
1620
1621 if (opr1->is_stack()) {
1622 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1623 opr1 = FrameMap::rscratch1_opr;
1624 } else if (opr1->is_constant()) {
1625 LIR_Opr tmp
1626 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1627 const2reg(opr1, tmp, lir_patch_none, NULL);
1628 opr1 = tmp;
1629 }
1630
1631 if (opr2->is_stack()) {
1632 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1633 opr2 = FrameMap::rscratch2_opr;
1634 } else if (opr2->is_constant()) {
1635 LIR_Opr tmp
1636 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1637 const2reg(opr2, tmp, lir_patch_none, NULL);
1638 opr2 = tmp;
1639 }
1640
1641 if (result->type() == T_LONG)
1642 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1643 else
1644 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1645 }
1646
1647 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1648 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1649
1650 if (left->is_single_cpu()) {
1651 Register lreg = left->as_register();
1652 Register dreg = as_reg(dest);
1653
1654 if (right->is_single_cpu()) {
1655 // cpu register - cpu register
1656
1657 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1658 "should be");
1659 Register rreg = right->as_register();
1660 switch (code) {
1661 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1662 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1663 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1664 default: ShouldNotReachHere();
1665 }
1666
1667 } else if (right->is_double_cpu()) {
1668 Register rreg = right->as_register_lo();
1669 // single_cpu + double_cpu: can happen with obj+long
1670 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1671 switch (code) {
1672 case lir_add: __ add(dreg, lreg, rreg); break;
1673 case lir_sub: __ sub(dreg, lreg, rreg); break;
1674 default: ShouldNotReachHere();
1675 }
1676 } else if (right->is_constant()) {
1677 // cpu register - constant
1678 jlong c;
1679
1680 // FIXME. This is fugly: we really need to factor all this logic.
1681 switch(right->type()) {
1682 case T_LONG:
1683 c = right->as_constant_ptr()->as_jlong();
1684 break;
1685 case T_INT:
1686 case T_ADDRESS:
1687 c = right->as_constant_ptr()->as_jint();
1688 break;
1689 default:
1690 ShouldNotReachHere();
1691 c = 0; // unreachable
1692 break;
1693 }
1694
1695 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1696 if (c == 0 && dreg == lreg) {
1697 COMMENT("effective nop elided");
1698 return;
1699 }
1700 switch(left->type()) {
1701 case T_INT:
1702 switch (code) {
1703 case lir_add: __ addw(dreg, lreg, c); break;
1704 case lir_sub: __ subw(dreg, lreg, c); break;
1705 default: ShouldNotReachHere();
1706 }
1707 break;
1708 case T_OBJECT:
1709 case T_ADDRESS:
1710 switch (code) {
1711 case lir_add: __ add(dreg, lreg, c); break;
1712 case lir_sub: __ sub(dreg, lreg, c); break;
1713 default: ShouldNotReachHere();
1714 }
1715 break;
1716 default:
1717 ShouldNotReachHere();
1718 }
1719 } else {
1720 ShouldNotReachHere();
1721 }
1722
1723 } else if (left->is_double_cpu()) {
1724 Register lreg_lo = left->as_register_lo();
1725
1726 if (right->is_double_cpu()) {
1727 // cpu register - cpu register
1728 Register rreg_lo = right->as_register_lo();
1729 switch (code) {
1730 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1731 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1732 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1733 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1734 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1735 default:
1736 ShouldNotReachHere();
1737 }
1738
1739 } else if (right->is_constant()) {
1740 jlong c = right->as_constant_ptr()->as_jlong();
1741 Register dreg = as_reg(dest);
1742 switch (code) {
1743 case lir_add:
1744 case lir_sub:
1745 if (c == 0 && dreg == lreg_lo) {
1746 COMMENT("effective nop elided");
1747 return;
1748 }
1749 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1750 break;
1751 case lir_div:
1752 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1753 if (c == 1) {
1754 // move lreg_lo to dreg if divisor is 1
1755 __ mov(dreg, lreg_lo);
1756 } else {
1757 unsigned int shift = exact_log2_long(c);
1758 // use rscratch1 as intermediate result register
1759 __ asr(rscratch1, lreg_lo, 63);
1760 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1761 __ asr(dreg, rscratch1, shift);
1762 }
1763 break;
1764 case lir_rem:
1765 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1766 if (c == 1) {
1767 // move 0 to dreg if divisor is 1
1768 __ mov(dreg, zr);
1769 } else {
1770 // use rscratch1 as intermediate result register
1771 __ negs(rscratch1, lreg_lo);
1772 __ andr(dreg, lreg_lo, c - 1);
1773 __ andr(rscratch1, rscratch1, c - 1);
1774 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1775 }
1776 break;
1777 default:
1778 ShouldNotReachHere();
1779 }
1780 } else {
1781 ShouldNotReachHere();
1782 }
1783 } else if (left->is_single_fpu()) {
1784 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1785 switch (code) {
1786 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1787 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1788 case lir_mul_strictfp: // fall through
1789 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1790 case lir_div_strictfp: // fall through
1791 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1792 default:
1793 ShouldNotReachHere();
1794 }
1795 } else if (left->is_double_fpu()) {
1796 if (right->is_double_fpu()) {
1797 // fpu register - fpu register
1798 switch (code) {
1799 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1800 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1801 case lir_mul_strictfp: // fall through
1802 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1803 case lir_div_strictfp: // fall through
1804 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1805 default:
1806 ShouldNotReachHere();
1807 }
1808 } else {
1809 if (right->is_constant()) {
1810 ShouldNotReachHere();
1811 }
1812 ShouldNotReachHere();
1813 }
1814 } else if (left->is_single_stack() || left->is_address()) {
1815 assert(left == dest, "left and dest must be equal");
1816 ShouldNotReachHere();
1817 } else {
1818 ShouldNotReachHere();
1819 }
1820 }
1821
1822 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1823
1824
1825 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1826 switch(code) {
1827 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1828 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1829 default : ShouldNotReachHere();
1830 }
1831 }
1832
1833 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1834
1835 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1836 Register Rleft = left->is_single_cpu() ? left->as_register() :
1837 left->as_register_lo();
1838 if (dst->is_single_cpu()) {
1839 Register Rdst = dst->as_register();
1840 if (right->is_constant()) {
1841 switch (code) {
1842 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1843 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1844 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1845 default: ShouldNotReachHere(); break;
1846 }
1847 } else {
1848 Register Rright = right->is_single_cpu() ? right->as_register() :
1849 right->as_register_lo();
1850 switch (code) {
1851 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1852 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1853 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1854 default: ShouldNotReachHere(); break;
1855 }
1856 }
1857 } else {
1858 Register Rdst = dst->as_register_lo();
1859 if (right->is_constant()) {
1860 switch (code) {
1861 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1862 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1863 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1864 default: ShouldNotReachHere(); break;
1865 }
1866 } else {
1867 Register Rright = right->is_single_cpu() ? right->as_register() :
1868 right->as_register_lo();
1869 switch (code) {
1870 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1871 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1872 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1873 default: ShouldNotReachHere(); break;
1874 }
1875 }
1876 }
1877 }
1878
1879
1880
1881 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1882
1883 // opcode check
1884 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1885 bool is_irem = (code == lir_irem);
1886
1887 // operand check
1888 assert(left->is_single_cpu(), "left must be register");
1889 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1890 assert(result->is_single_cpu(), "result must be register");
1891 Register lreg = left->as_register();
1892 Register dreg = result->as_register();
1893
1894 // power-of-2 constant check and codegen
1895 if (right->is_constant()) {
1896 int c = right->as_constant_ptr()->as_jint();
1897 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1898 if (is_irem) {
1899 if (c == 1) {
1900 // move 0 to dreg if divisor is 1
1901 __ movw(dreg, zr);
1902 } else {
1903 // use rscratch1 as intermediate result register
1904 __ negsw(rscratch1, lreg);
1905 __ andw(dreg, lreg, c - 1);
1906 __ andw(rscratch1, rscratch1, c - 1);
1907 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1908 }
1909 } else {
1910 if (c == 1) {
1911 // move lreg to dreg if divisor is 1
1912 __ movw(dreg, lreg);
1913 } else {
1914 unsigned int shift = exact_log2(c);
1915 // use rscratch1 as intermediate result register
1916 __ asrw(rscratch1, lreg, 31);
1917 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1918 __ asrw(dreg, rscratch1, shift);
1919 }
1920 }
1921 } else {
1922 Register rreg = right->as_register();
1923 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1924 }
1925 }
1926
1927
1928 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1929 if (opr1->is_constant() && opr2->is_single_cpu()) {
1930 // tableswitch
1931 Register reg = as_reg(opr2);
1932 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1933 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1934 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1935 Register reg1 = as_reg(opr1);
1936 if (opr2->is_single_cpu()) {
1937 // cpu register - cpu register
1938 Register reg2 = opr2->as_register();
1939 if (is_reference_type(opr1->type())) {
1940 __ cmpoop(reg1, reg2);
1941 } else {
1942 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1943 __ cmpw(reg1, reg2);
1944 }
1945 return;
1946 }
1947 if (opr2->is_double_cpu()) {
1948 // cpu register - cpu register
1949 Register reg2 = opr2->as_register_lo();
1950 __ cmp(reg1, reg2);
1951 return;
1952 }
1953
1954 if (opr2->is_constant()) {
1955 bool is_32bit = false; // width of register operand
1956 jlong imm;
1957
1958 switch(opr2->type()) {
1959 case T_INT:
1960 imm = opr2->as_constant_ptr()->as_jint();
1961 is_32bit = true;
1962 break;
1963 case T_LONG:
1964 imm = opr2->as_constant_ptr()->as_jlong();
1965 break;
1966 case T_ADDRESS:
1967 imm = opr2->as_constant_ptr()->as_jint();
1968 break;
1969 case T_METADATA:
1970 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1971 break;
1972 case T_OBJECT:
1973 case T_ARRAY:
1974 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1975 __ cmpoop(reg1, rscratch1);
1976 return;
1977 default:
1978 ShouldNotReachHere();
1979 imm = 0; // unreachable
1980 break;
1981 }
1982
1983 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1984 if (is_32bit)
1985 __ cmpw(reg1, imm);
1986 else
1987 __ subs(zr, reg1, imm);
1988 return;
1989 } else {
1990 __ mov(rscratch1, imm);
1991 if (is_32bit)
1992 __ cmpw(reg1, rscratch1);
1993 else
1994 __ cmp(reg1, rscratch1);
1995 return;
1996 }
1997 } else
1998 ShouldNotReachHere();
1999 } else if (opr1->is_single_fpu()) {
2000 FloatRegister reg1 = opr1->as_float_reg();
2001 assert(opr2->is_single_fpu(), "expect single float register");
2002 FloatRegister reg2 = opr2->as_float_reg();
2003 __ fcmps(reg1, reg2);
2004 } else if (opr1->is_double_fpu()) {
2005 FloatRegister reg1 = opr1->as_double_reg();
2006 assert(opr2->is_double_fpu(), "expect double float register");
2007 FloatRegister reg2 = opr2->as_double_reg();
2008 __ fcmpd(reg1, reg2);
2009 } else {
2010 ShouldNotReachHere();
2011 }
2012 }
2013
2014 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2015 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2016 bool is_unordered_less = (code == lir_ucmp_fd2i);
2017 if (left->is_single_fpu()) {
2018 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2019 } else if (left->is_double_fpu()) {
2020 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2021 } else {
2022 ShouldNotReachHere();
2023 }
2024 } else if (code == lir_cmp_l2i) {
2025 Label done;
2026 __ cmp(left->as_register_lo(), right->as_register_lo());
2027 __ mov(dst->as_register(), (u_int64_t)-1L);
2028 __ br(Assembler::LT, done);
2029 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2030 __ bind(done);
2031 } else {
2032 ShouldNotReachHere();
2033 }
2034 }
2035
2036
2037 void LIR_Assembler::align_call(LIR_Code code) { }
2038
2039
2040 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2041 address call = __ trampoline_call(Address(op->addr(), rtype));
2042 if (call == NULL) {
2043 bailout("trampoline stub overflow");
2044 return;
2045 }
2046 add_call_info(code_offset(), op->info());
2047 }
2048
2049
2050 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2051 address call = __ ic_call(op->addr());
2052 if (call == NULL) {
2053 bailout("trampoline stub overflow");
2054 return;
2055 }
2056 add_call_info(code_offset(), op->info());
2057 }
2058
2059
2060 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2061 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2062 ShouldNotReachHere();
2063 }
2064
2065
2066 void LIR_Assembler::emit_static_call_stub() {
2067 address call_pc = __ pc();
2068 address stub = __ start_a_stub(call_stub_size());
2069 if (stub == NULL) {
2070 bailout("static call stub overflow");
2071 return;
2072 }
2073
2074 int start = __ offset();
2075
2076 __ relocate(static_stub_Relocation::spec(call_pc));
2077 __ emit_static_call_stub();
2078
2079 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2080 <= call_stub_size(), "stub too big");
2081 __ end_a_stub();
2082 }
2083
2084
2085 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2086 assert(exceptionOop->as_register() == r0, "must match");
2087 assert(exceptionPC->as_register() == r3, "must match");
2088
2089 // exception object is not added to oop map by LinearScan
2090 // (LinearScan assumes that no oops are in fixed registers)
2091 info->add_register_oop(exceptionOop);
2092 Runtime1::StubID unwind_id;
2093
2094 // get current pc information
2095 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2096 int pc_for_athrow_offset = __ offset();
2097 InternalAddress pc_for_athrow(__ pc());
2098 __ adr(exceptionPC->as_register(), pc_for_athrow);
2099 add_call_info(pc_for_athrow_offset, info); // for exception handler
2100
2101 __ verify_not_null_oop(r0);
2102 // search an exception handler (r0: exception oop, r3: throwing pc)
2103 if (compilation()->has_fpu_code()) {
2104 unwind_id = Runtime1::handle_exception_id;
2105 } else {
2106 unwind_id = Runtime1::handle_exception_nofpu_id;
2107 }
2108 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2109
2110 // FIXME: enough room for two byte trap ????
2111 __ nop();
2112 }
2113
2114
2115 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2116 assert(exceptionOop->as_register() == r0, "must match");
2117
2118 __ b(_unwind_handler_entry);
2119 }
2120
2121
2122 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2123 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2124 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2125
2126 switch (left->type()) {
2127 case T_INT: {
2128 switch (code) {
2129 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2130 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2131 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2132 default:
2133 ShouldNotReachHere();
2134 break;
2135 }
2136 break;
2137 case T_LONG:
2138 case T_ADDRESS:
2139 case T_OBJECT:
2140 switch (code) {
2141 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2142 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2143 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2144 default:
2145 ShouldNotReachHere();
2146 break;
2147 }
2148 break;
2149 default:
2150 ShouldNotReachHere();
2151 break;
2152 }
2153 }
2154 }
2155
2156
2157 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2158 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2159 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2160
2161 switch (left->type()) {
2162 case T_INT: {
2163 switch (code) {
2164 case lir_shl: __ lslw (dreg, lreg, count); break;
2165 case lir_shr: __ asrw (dreg, lreg, count); break;
2166 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2167 default:
2168 ShouldNotReachHere();
2169 break;
2170 }
2171 break;
2172 case T_LONG:
2173 case T_ADDRESS:
2174 case T_OBJECT:
2175 switch (code) {
2176 case lir_shl: __ lsl (dreg, lreg, count); break;
2177 case lir_shr: __ asr (dreg, lreg, count); break;
2178 case lir_ushr: __ lsr (dreg, lreg, count); break;
2179 default:
2180 ShouldNotReachHere();
2181 break;
2182 }
2183 break;
2184 default:
2185 ShouldNotReachHere();
2186 break;
2187 }
2188 }
2189 }
2190
2191
2192 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2193 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2194 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2195 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2196 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2197 }
2198
2199
2200 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2201 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2202 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2203 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2204 __ mov (rscratch1, c);
2205 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2206 }
2207
2208
2209 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2210 ShouldNotReachHere();
2211 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2212 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2213 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2214 __ lea(rscratch1, __ constant_oop_address(o));
2215 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2216 }
2217
2218
2219 // This code replaces a call to arraycopy; no exception may
2220 // be thrown in this code, they must be thrown in the System.arraycopy
2221 // activation frame; we could save some checks if this would not be the case
2222 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2223 ciArrayKlass* default_type = op->expected_type();
2224 Register src = op->src()->as_register();
2225 Register dst = op->dst()->as_register();
2226 Register src_pos = op->src_pos()->as_register();
2227 Register dst_pos = op->dst_pos()->as_register();
2228 Register length = op->length()->as_register();
2229 Register tmp = op->tmp()->as_register();
2230
2231 __ resolve(ACCESS_READ, src);
2232 __ resolve(ACCESS_WRITE, dst);
2233
2234 CodeStub* stub = op->stub();
2235 int flags = op->flags();
2236 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2237 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2238
2239 // if we don't know anything, just go through the generic arraycopy
2240 if (default_type == NULL // || basic_type == T_OBJECT
2241 ) {
2242 Label done;
2243 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2244
2245 // Save the arguments in case the generic arraycopy fails and we
2246 // have to fall back to the JNI stub
2247 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2248 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2249 __ str(src, Address(sp, 4*BytesPerWord));
2250
2251 address copyfunc_addr = StubRoutines::generic_arraycopy();
2252 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2253
2254 // The arguments are in java calling convention so we shift them
2255 // to C convention
2256 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2257 __ mov(c_rarg0, j_rarg0);
2258 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2259 __ mov(c_rarg1, j_rarg1);
2260 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2261 __ mov(c_rarg2, j_rarg2);
2262 assert_different_registers(c_rarg3, j_rarg4);
2263 __ mov(c_rarg3, j_rarg3);
2264 __ mov(c_rarg4, j_rarg4);
2265 #ifndef PRODUCT
2266 if (PrintC1Statistics) {
2267 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2268 }
2269 #endif
2270 __ far_call(RuntimeAddress(copyfunc_addr));
2271
2272 __ cbz(r0, *stub->continuation());
2273
2274 // Reload values from the stack so they are where the stub
2275 // expects them.
2276 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2277 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2278 __ ldr(src, Address(sp, 4*BytesPerWord));
2279
2280 // r0 is -1^K where K == partial copied count
2281 __ eonw(rscratch1, r0, zr);
2282 // adjust length down and src/end pos up by partial copied count
2283 __ subw(length, length, rscratch1);
2284 __ addw(src_pos, src_pos, rscratch1);
2285 __ addw(dst_pos, dst_pos, rscratch1);
2286 __ b(*stub->entry());
2287
2288 __ bind(*stub->continuation());
2289 return;
2290 }
2291
2292 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2293
2294 int elem_size = type2aelembytes(basic_type);
2295 int shift_amount;
2296 int scale = exact_log2(elem_size);
2297
2298 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2299 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2300 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2301 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2302
2303 // test for NULL
2304 if (flags & LIR_OpArrayCopy::src_null_check) {
2305 __ cbz(src, *stub->entry());
2306 }
2307 if (flags & LIR_OpArrayCopy::dst_null_check) {
2308 __ cbz(dst, *stub->entry());
2309 }
2310
2311 // If the compiler was not able to prove that exact type of the source or the destination
2312 // of the arraycopy is an array type, check at runtime if the source or the destination is
2313 // an instance type.
2314 if (flags & LIR_OpArrayCopy::type_check) {
2315 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2316 __ load_klass(tmp, dst);
2317 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2318 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2319 __ br(Assembler::GE, *stub->entry());
2320 }
2321
2322 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2323 __ load_klass(tmp, src);
2324 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2325 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2326 __ br(Assembler::GE, *stub->entry());
2327 }
2328 }
2329
2330 // check if negative
2331 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2332 __ cmpw(src_pos, 0);
2333 __ br(Assembler::LT, *stub->entry());
2334 }
2335 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2336 __ cmpw(dst_pos, 0);
2337 __ br(Assembler::LT, *stub->entry());
2338 }
2339
2340 if (flags & LIR_OpArrayCopy::length_positive_check) {
2341 __ cmpw(length, 0);
2342 __ br(Assembler::LT, *stub->entry());
2343 }
2344
2345 if (flags & LIR_OpArrayCopy::src_range_check) {
2346 __ addw(tmp, src_pos, length);
2347 __ ldrw(rscratch1, src_length_addr);
2348 __ cmpw(tmp, rscratch1);
2349 __ br(Assembler::HI, *stub->entry());
2350 }
2351 if (flags & LIR_OpArrayCopy::dst_range_check) {
2352 __ addw(tmp, dst_pos, length);
2353 __ ldrw(rscratch1, dst_length_addr);
2354 __ cmpw(tmp, rscratch1);
2355 __ br(Assembler::HI, *stub->entry());
2356 }
2357
2358 if (flags & LIR_OpArrayCopy::type_check) {
2359 // We don't know the array types are compatible
2360 if (basic_type != T_OBJECT) {
2361 // Simple test for basic type arrays
2362 if (UseCompressedClassPointers) {
2363 __ ldrw(tmp, src_klass_addr);
2364 __ ldrw(rscratch1, dst_klass_addr);
2365 __ cmpw(tmp, rscratch1);
2366 } else {
2367 __ ldr(tmp, src_klass_addr);
2368 __ ldr(rscratch1, dst_klass_addr);
2369 __ cmp(tmp, rscratch1);
2370 }
2371 __ br(Assembler::NE, *stub->entry());
2372 } else {
2373 // For object arrays, if src is a sub class of dst then we can
2374 // safely do the copy.
2375 Label cont, slow;
2376
2377 #define PUSH(r1, r2) \
2378 stp(r1, r2, __ pre(sp, -2 * wordSize));
2379
2380 #define POP(r1, r2) \
2381 ldp(r1, r2, __ post(sp, 2 * wordSize));
2382
2383 __ PUSH(src, dst);
2384
2385 __ load_klass(src, src);
2386 __ load_klass(dst, dst);
2387
2388 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2389
2390 __ PUSH(src, dst);
2391 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2392 __ POP(src, dst);
2393
2394 __ cbnz(src, cont);
2395
2396 __ bind(slow);
2397 __ POP(src, dst);
2398
2399 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2400 if (copyfunc_addr != NULL) { // use stub if available
2401 // src is not a sub class of dst so we have to do a
2402 // per-element check.
2403
2404 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2405 if ((flags & mask) != mask) {
2406 // Check that at least both of them object arrays.
2407 assert(flags & mask, "one of the two should be known to be an object array");
2408
2409 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2410 __ load_klass(tmp, src);
2411 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2412 __ load_klass(tmp, dst);
2413 }
2414 int lh_offset = in_bytes(Klass::layout_helper_offset());
2415 Address klass_lh_addr(tmp, lh_offset);
2416 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2417 __ ldrw(rscratch1, klass_lh_addr);
2418 __ mov(rscratch2, objArray_lh);
2419 __ eorw(rscratch1, rscratch1, rscratch2);
2420 __ cbnzw(rscratch1, *stub->entry());
2421 }
2422
2423 // Spill because stubs can use any register they like and it's
2424 // easier to restore just those that we care about.
2425 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2426 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2427 __ str(src, Address(sp, 4*BytesPerWord));
2428
2429 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2430 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2431 assert_different_registers(c_rarg0, dst, dst_pos, length);
2432 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2433 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2434 assert_different_registers(c_rarg1, dst, length);
2435 __ uxtw(c_rarg2, length);
2436 assert_different_registers(c_rarg2, dst);
2437
2438 __ load_klass(c_rarg4, dst);
2439 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2440 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2441 __ far_call(RuntimeAddress(copyfunc_addr));
2442
2443 #ifndef PRODUCT
2444 if (PrintC1Statistics) {
2445 Label failed;
2446 __ cbnz(r0, failed);
2447 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2448 __ bind(failed);
2449 }
2450 #endif
2451
2452 __ cbz(r0, *stub->continuation());
2453
2454 #ifndef PRODUCT
2455 if (PrintC1Statistics) {
2456 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2457 }
2458 #endif
2459 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2460
2461 // Restore previously spilled arguments
2462 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2463 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2464 __ ldr(src, Address(sp, 4*BytesPerWord));
2465
2466 // return value is -1^K where K is partial copied count
2467 __ eonw(rscratch1, r0, zr);
2468 // adjust length down and src/end pos up by partial copied count
2469 __ subw(length, length, rscratch1);
2470 __ addw(src_pos, src_pos, rscratch1);
2471 __ addw(dst_pos, dst_pos, rscratch1);
2472 }
2473
2474 __ b(*stub->entry());
2475
2476 __ bind(cont);
2477 __ POP(src, dst);
2478 }
2479 }
2480
2481 #ifdef ASSERT
2482 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2483 // Sanity check the known type with the incoming class. For the
2484 // primitive case the types must match exactly with src.klass and
2485 // dst.klass each exactly matching the default type. For the
2486 // object array case, if no type check is needed then either the
2487 // dst type is exactly the expected type and the src type is a
2488 // subtype which we can't check or src is the same array as dst
2489 // but not necessarily exactly of type default_type.
2490 Label known_ok, halt;
2491 __ mov_metadata(tmp, default_type->constant_encoding());
2492 if (UseCompressedClassPointers) {
2493 __ encode_klass_not_null(tmp);
2494 }
2495
2496 if (basic_type != T_OBJECT) {
2497
2498 if (UseCompressedClassPointers) {
2499 __ ldrw(rscratch1, dst_klass_addr);
2500 __ cmpw(tmp, rscratch1);
2501 } else {
2502 __ ldr(rscratch1, dst_klass_addr);
2503 __ cmp(tmp, rscratch1);
2504 }
2505 __ br(Assembler::NE, halt);
2506 if (UseCompressedClassPointers) {
2507 __ ldrw(rscratch1, src_klass_addr);
2508 __ cmpw(tmp, rscratch1);
2509 } else {
2510 __ ldr(rscratch1, src_klass_addr);
2511 __ cmp(tmp, rscratch1);
2512 }
2513 __ br(Assembler::EQ, known_ok);
2514 } else {
2515 if (UseCompressedClassPointers) {
2516 __ ldrw(rscratch1, dst_klass_addr);
2517 __ cmpw(tmp, rscratch1);
2518 } else {
2519 __ ldr(rscratch1, dst_klass_addr);
2520 __ cmp(tmp, rscratch1);
2521 }
2522 __ br(Assembler::EQ, known_ok);
2523 __ cmp(src, dst);
2524 __ br(Assembler::EQ, known_ok);
2525 }
2526 __ bind(halt);
2527 __ stop("incorrect type information in arraycopy");
2528 __ bind(known_ok);
2529 }
2530 #endif
2531
2532 #ifndef PRODUCT
2533 if (PrintC1Statistics) {
2534 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2535 }
2536 #endif
2537
2538 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2539 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2540 assert_different_registers(c_rarg0, dst, dst_pos, length);
2541 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2542 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2543 assert_different_registers(c_rarg1, dst, length);
2544 __ uxtw(c_rarg2, length);
2545 assert_different_registers(c_rarg2, dst);
2546
2547 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2548 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2549 const char *name;
2550 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2551
2552 CodeBlob *cb = CodeCache::find_blob(entry);
2553 if (cb) {
2554 __ far_call(RuntimeAddress(entry));
2555 } else {
2556 __ call_VM_leaf(entry, 3);
2557 }
2558
2559 __ bind(*stub->continuation());
2560 }
2561
2562
2563
2564
2565 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2566 Register obj = op->obj_opr()->as_register(); // may not be an oop
2567 Register hdr = op->hdr_opr()->as_register();
2568 Register lock = op->lock_opr()->as_register();
2569 if (!UseFastLocking) {
2570 __ b(*op->stub()->entry());
2571 } else if (op->code() == lir_lock) {
2572 Register scratch = noreg;
2573 if (UseBiasedLocking) {
2574 scratch = op->scratch_opr()->as_register();
2575 }
2576 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2577 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2578 // add debug info for NullPointerException only if one is possible
2579 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2580 if (op->info() != NULL) {
2581 add_debug_info_for_null_check(null_check_offset, op->info());
2582 }
2583 // done
2584 } else if (op->code() == lir_unlock) {
2585 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2586 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2587 } else {
2588 Unimplemented();
2589 }
2590 __ bind(*op->stub()->continuation());
2591 }
2592
2593
2594 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2595 ciMethod* method = op->profiled_method();
2596 int bci = op->profiled_bci();
2597 ciMethod* callee = op->profiled_callee();
2598
2599 // Update counter for all call types
2600 ciMethodData* md = method->method_data_or_null();
2601 assert(md != NULL, "Sanity");
2602 ciProfileData* data = md->bci_to_data(bci);
2603 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2604 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2605 Register mdo = op->mdo()->as_register();
2606 __ mov_metadata(mdo, md->constant_encoding());
2607 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2608 // Perform additional virtual call profiling for invokevirtual and
2609 // invokeinterface bytecodes
2610 if (op->should_profile_receiver_type()) {
2611 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2612 Register recv = op->recv()->as_register();
2613 assert_different_registers(mdo, recv);
2614 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2615 ciKlass* known_klass = op->known_holder();
2616 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2617 // We know the type that will be seen at this call site; we can
2618 // statically update the MethodData* rather than needing to do
2619 // dynamic tests on the receiver type
2620
2621 // NOTE: we should probably put a lock around this search to
2622 // avoid collisions by concurrent compilations
2623 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2624 uint i;
2625 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2626 ciKlass* receiver = vc_data->receiver(i);
2627 if (known_klass->equals(receiver)) {
2628 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2629 __ addptr(data_addr, DataLayout::counter_increment);
2630 return;
2631 }
2632 }
2633
2634 // Receiver type not found in profile data; select an empty slot
2635
2636 // Note that this is less efficient than it should be because it
2637 // always does a write to the receiver part of the
2638 // VirtualCallData rather than just the first time
2639 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2640 ciKlass* receiver = vc_data->receiver(i);
2641 if (receiver == NULL) {
2642 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2643 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2644 __ lea(rscratch2, recv_addr);
2645 __ str(rscratch1, Address(rscratch2));
2646 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2647 __ addptr(data_addr, DataLayout::counter_increment);
2648 return;
2649 }
2650 }
2651 } else {
2652 __ load_klass(recv, recv);
2653 Label update_done;
2654 type_profile_helper(mdo, md, data, recv, &update_done);
2655 // Receiver did not match any saved receiver and there is no empty row for it.
2656 // Increment total counter to indicate polymorphic case.
2657 __ addptr(counter_addr, DataLayout::counter_increment);
2658
2659 __ bind(update_done);
2660 }
2661 } else {
2662 // Static call
2663 __ addptr(counter_addr, DataLayout::counter_increment);
2664 }
2665 }
2666
2667
2668 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2669 Unimplemented();
2670 }
2671
2672
2673 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2674 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2675 }
2676
2677 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2678 assert(op->crc()->is_single_cpu(), "crc must be register");
2679 assert(op->val()->is_single_cpu(), "byte value must be register");
2680 assert(op->result_opr()->is_single_cpu(), "result must be register");
2681 Register crc = op->crc()->as_register();
2682 Register val = op->val()->as_register();
2683 Register res = op->result_opr()->as_register();
2684
2685 assert_different_registers(val, crc, res);
2686 unsigned long offset;
2687 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2688 if (offset) __ add(res, res, offset);
2689
2690 __ mvnw(crc, crc); // ~crc
2691 __ update_byte_crc32(crc, val, res);
2692 __ mvnw(res, crc); // ~crc
2693 }
2694
2695 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2696 COMMENT("emit_profile_type {");
2697 Register obj = op->obj()->as_register();
2698 Register tmp = op->tmp()->as_pointer_register();
2699 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2700 ciKlass* exact_klass = op->exact_klass();
2701 intptr_t current_klass = op->current_klass();
2702 bool not_null = op->not_null();
2703 bool no_conflict = op->no_conflict();
2704
2705 Label update, next, none;
2706
2707 bool do_null = !not_null;
2708 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2709 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2710
2711 assert(do_null || do_update, "why are we here?");
2712 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2713 assert(mdo_addr.base() != rscratch1, "wrong register");
2714
2715 __ verify_oop(obj);
2716
2717 if (tmp != obj) {
2718 __ mov(tmp, obj);
2719 }
2720 if (do_null) {
2721 __ cbnz(tmp, update);
2722 if (!TypeEntries::was_null_seen(current_klass)) {
2723 __ ldr(rscratch2, mdo_addr);
2724 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2725 __ str(rscratch2, mdo_addr);
2726 }
2727 if (do_update) {
2728 #ifndef ASSERT
2729 __ b(next);
2730 }
2731 #else
2732 __ b(next);
2733 }
2734 } else {
2735 __ cbnz(tmp, update);
2736 __ stop("unexpected null obj");
2737 #endif
2738 }
2739
2740 __ bind(update);
2741
2742 if (do_update) {
2743 #ifdef ASSERT
2744 if (exact_klass != NULL) {
2745 Label ok;
2746 __ load_klass(tmp, tmp);
2747 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2748 __ eor(rscratch1, tmp, rscratch1);
2749 __ cbz(rscratch1, ok);
2750 __ stop("exact klass and actual klass differ");
2751 __ bind(ok);
2752 }
2753 #endif
2754 if (!no_conflict) {
2755 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2756 if (exact_klass != NULL) {
2757 __ mov_metadata(tmp, exact_klass->constant_encoding());
2758 } else {
2759 __ load_klass(tmp, tmp);
2760 }
2761
2762 __ ldr(rscratch2, mdo_addr);
2763 __ eor(tmp, tmp, rscratch2);
2764 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2765 // klass seen before, nothing to do. The unknown bit may have been
2766 // set already but no need to check.
2767 __ cbz(rscratch1, next);
2768
2769 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2770
2771 if (TypeEntries::is_type_none(current_klass)) {
2772 __ cbz(rscratch2, none);
2773 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2774 __ br(Assembler::EQ, none);
2775 // There is a chance that the checks above (re-reading profiling
2776 // data from memory) fail if another thread has just set the
2777 // profiling to this obj's klass
2778 __ dmb(Assembler::ISHLD);
2779 __ ldr(rscratch2, mdo_addr);
2780 __ eor(tmp, tmp, rscratch2);
2781 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2782 __ cbz(rscratch1, next);
2783 }
2784 } else {
2785 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2786 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2787
2788 __ ldr(tmp, mdo_addr);
2789 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2790 }
2791
2792 // different than before. Cannot keep accurate profile.
2793 __ ldr(rscratch2, mdo_addr);
2794 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2795 __ str(rscratch2, mdo_addr);
2796
2797 if (TypeEntries::is_type_none(current_klass)) {
2798 __ b(next);
2799
2800 __ bind(none);
2801 // first time here. Set profile type.
2802 __ str(tmp, mdo_addr);
2803 }
2804 } else {
2805 // There's a single possible klass at this profile point
2806 assert(exact_klass != NULL, "should be");
2807 if (TypeEntries::is_type_none(current_klass)) {
2808 __ mov_metadata(tmp, exact_klass->constant_encoding());
2809 __ ldr(rscratch2, mdo_addr);
2810 __ eor(tmp, tmp, rscratch2);
2811 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2812 __ cbz(rscratch1, next);
2813 #ifdef ASSERT
2814 {
2815 Label ok;
2816 __ ldr(rscratch1, mdo_addr);
2817 __ cbz(rscratch1, ok);
2818 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2819 __ br(Assembler::EQ, ok);
2820 // may have been set by another thread
2821 __ dmb(Assembler::ISHLD);
2822 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2823 __ ldr(rscratch2, mdo_addr);
2824 __ eor(rscratch2, rscratch1, rscratch2);
2825 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2826 __ cbz(rscratch2, ok);
2827
2828 __ stop("unexpected profiling mismatch");
2829 __ bind(ok);
2830 }
2831 #endif
2832 // first time here. Set profile type.
2833 __ ldr(tmp, mdo_addr);
2834 } else {
2835 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2836 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2837
2838 __ ldr(tmp, mdo_addr);
2839 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2840
2841 __ orr(tmp, tmp, TypeEntries::type_unknown);
2842 __ str(tmp, mdo_addr);
2843 // FIXME: Write barrier needed here?
2844 }
2845 }
2846
2847 __ bind(next);
2848 }
2849 COMMENT("} emit_profile_type");
2850 }
2851
2852
2853 void LIR_Assembler::align_backward_branch_target() {
2854 }
2855
2856
2857 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2858 // tmp must be unused
2859 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2860
2861 if (left->is_single_cpu()) {
2862 assert(dest->is_single_cpu(), "expect single result reg");
2863 __ negw(dest->as_register(), left->as_register());
2864 } else if (left->is_double_cpu()) {
2865 assert(dest->is_double_cpu(), "expect double result reg");
2866 __ neg(dest->as_register_lo(), left->as_register_lo());
2867 } else if (left->is_single_fpu()) {
2868 assert(dest->is_single_fpu(), "expect single float result reg");
2869 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2870 } else {
2871 assert(left->is_double_fpu(), "expect double float operand reg");
2872 assert(dest->is_double_fpu(), "expect double float result reg");
2873 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2874 }
2875 }
2876
2877
2878 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2879 if (patch_code != lir_patch_none) {
2880 deoptimize_trap(info);
2881 return;
2882 }
2883
2884 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2885 }
2886
2887
2888 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2889 assert(!tmp->is_valid(), "don't need temporary");
2890
2891 CodeBlob *cb = CodeCache::find_blob(dest);
2892 if (cb) {
2893 __ far_call(RuntimeAddress(dest));
2894 } else {
2895 __ mov(rscratch1, RuntimeAddress(dest));
2896 __ blr(rscratch1);
2897 }
2898
2899 if (info != NULL) {
2900 add_call_info_here(info);
2901 }
2902 __ maybe_isb();
2903 }
2904
2905 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2906 if (dest->is_address() || src->is_address()) {
2907 move_op(src, dest, type, lir_patch_none, info,
2908 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2909 } else {
2910 ShouldNotReachHere();
2911 }
2912 }
2913
2914 #ifdef ASSERT
2915 // emit run-time assertion
2916 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2917 assert(op->code() == lir_assert, "must be");
2918
2919 if (op->in_opr1()->is_valid()) {
2920 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2921 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2922 } else {
2923 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2924 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2925 }
2926
2927 Label ok;
2928 if (op->condition() != lir_cond_always) {
2929 Assembler::Condition acond = Assembler::AL;
2930 switch (op->condition()) {
2931 case lir_cond_equal: acond = Assembler::EQ; break;
2932 case lir_cond_notEqual: acond = Assembler::NE; break;
2933 case lir_cond_less: acond = Assembler::LT; break;
2934 case lir_cond_lessEqual: acond = Assembler::LE; break;
2935 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2936 case lir_cond_greater: acond = Assembler::GT; break;
2937 case lir_cond_belowEqual: acond = Assembler::LS; break;
2938 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2939 default: ShouldNotReachHere();
2940 }
2941 __ br(acond, ok);
2942 }
2943 if (op->halt()) {
2944 const char* str = __ code_string(op->msg());
2945 __ stop(str);
2946 } else {
2947 breakpoint();
2948 }
2949 __ bind(ok);
2950 }
2951 #endif
2952
2953 #ifndef PRODUCT
2954 #define COMMENT(x) do { __ block_comment(x); } while (0)
2955 #else
2956 #define COMMENT(x)
2957 #endif
2958
2959 void LIR_Assembler::membar() {
2960 COMMENT("membar");
2961 __ membar(MacroAssembler::AnyAny);
2962 }
2963
2964 void LIR_Assembler::membar_acquire() {
2965 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2966 }
2967
2968 void LIR_Assembler::membar_release() {
2969 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2970 }
2971
2972 void LIR_Assembler::membar_loadload() {
2973 __ membar(Assembler::LoadLoad);
2974 }
2975
2976 void LIR_Assembler::membar_storestore() {
2977 __ membar(MacroAssembler::StoreStore);
2978 }
2979
2980 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2981
2982 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2983
2984 void LIR_Assembler::on_spin_wait() {
2985 Unimplemented();
2986 }
2987
2988 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2989 __ mov(result_reg->as_register(), rthread);
2990 }
2991
2992
2993 void LIR_Assembler::peephole(LIR_List *lir) {
2994 #if 0
2995 if (tableswitch_count >= max_tableswitches)
2996 return;
2997
2998 /*
2999 This finite-state automaton recognizes sequences of compare-and-
3000 branch instructions. We will turn them into a tableswitch. You
3001 could argue that C1 really shouldn't be doing this sort of
3002 optimization, but without it the code is really horrible.
3003 */
3004
3005 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3006 int first_key, last_key = -2147483648;
3007 int next_key = 0;
3008 int start_insn = -1;
3009 int last_insn = -1;
3010 Register reg = noreg;
3011 LIR_Opr reg_opr;
3012 state = start_s;
3013
3014 LIR_OpList* inst = lir->instructions_list();
3015 for (int i = 0; i < inst->length(); i++) {
3016 LIR_Op* op = inst->at(i);
3017 switch (state) {
3018 case start_s:
3019 first_key = -1;
3020 start_insn = i;
3021 switch (op->code()) {
3022 case lir_cmp:
3023 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3024 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3025 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3026 && opr2->is_constant()
3027 && opr2->type() == T_INT) {
3028 reg_opr = opr1;
3029 reg = opr1->as_register();
3030 first_key = opr2->as_constant_ptr()->as_jint();
3031 next_key = first_key + 1;
3032 state = cmp_s;
3033 goto next_state;
3034 }
3035 break;
3036 }
3037 break;
3038 case cmp_s:
3039 switch (op->code()) {
3040 case lir_branch:
3041 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3042 state = beq_s;
3043 last_insn = i;
3044 goto next_state;
3045 }
3046 }
3047 state = start_s;
3048 break;
3049 case beq_s:
3050 switch (op->code()) {
3051 case lir_cmp: {
3052 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3053 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3054 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3055 && opr1->as_register() == reg
3056 && opr2->is_constant()
3057 && opr2->type() == T_INT
3058 && opr2->as_constant_ptr()->as_jint() == next_key) {
3059 last_key = next_key;
3060 next_key++;
3061 state = cmp_s;
3062 goto next_state;
3063 }
3064 }
3065 }
3066 last_key = next_key;
3067 state = start_s;
3068 break;
3069 default:
3070 assert(false, "impossible state");
3071 }
3072 if (state == start_s) {
3073 if (first_key < last_key - 5L && reg != noreg) {
3074 {
3075 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3076 // reg->encoding(),
3077 // start_insn, first_key, last_key);
3078 // for (int i = 0; i < inst->length(); i++) {
3079 // inst->at(i)->print();
3080 // tty->print("\n");
3081 // }
3082 // tty->print("\n");
3083 }
3084
3085 struct tableswitch *sw = &switches[tableswitch_count];
3086 sw->_insn_index = start_insn, sw->_first_key = first_key,
3087 sw->_last_key = last_key, sw->_reg = reg;
3088 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3089 {
3090 // Insert the new table of branches
3091 int offset = last_insn;
3092 for (int n = first_key; n < last_key; n++) {
3093 inst->insert_before
3094 (last_insn + 1,
3095 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3096 inst->at(offset)->as_OpBranch()->label()));
3097 offset -= 2, i++;
3098 }
3099 }
3100 // Delete all the old compare-and-branch instructions
3101 for (int n = first_key; n < last_key; n++) {
3102 inst->remove_at(start_insn);
3103 inst->remove_at(start_insn);
3104 }
3105 // Insert the tableswitch instruction
3106 inst->insert_before(start_insn,
3107 new LIR_Op2(lir_cmp, lir_cond_always,
3108 LIR_OprFact::intConst(tableswitch_count),
3109 reg_opr));
3110 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3111 tableswitch_count++;
3112 }
3113 reg = noreg;
3114 last_key = -2147483648;
3115 }
3116 next_state:
3117 ;
3118 }
3119 #endif
3120 }
3121
3122 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3123 Address addr = as_Address(src->as_address_ptr());
3124 BasicType type = src->type();
3125 bool is_oop = is_reference_type(type);
3126
3127 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3128 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3129
3130 switch(type) {
3131 case T_INT:
3132 xchg = &MacroAssembler::atomic_xchgalw;
3133 add = &MacroAssembler::atomic_addalw;
3134 break;
3135 case T_LONG:
3136 xchg = &MacroAssembler::atomic_xchgal;
3137 add = &MacroAssembler::atomic_addal;
3138 break;
3139 case T_OBJECT:
3140 case T_ARRAY:
3141 if (UseCompressedOops) {
3142 xchg = &MacroAssembler::atomic_xchgalw;
3143 add = &MacroAssembler::atomic_addalw;
3144 } else {
3145 xchg = &MacroAssembler::atomic_xchgal;
3146 add = &MacroAssembler::atomic_addal;
3147 }
3148 break;
3149 default:
3150 ShouldNotReachHere();
3151 xchg = &MacroAssembler::atomic_xchgal;
3152 add = &MacroAssembler::atomic_addal; // unreachable
3153 }
3154
3155 switch (code) {
3156 case lir_xadd:
3157 {
3158 RegisterOrConstant inc;
3159 Register tmp = as_reg(tmp_op);
3160 Register dst = as_reg(dest);
3161 if (data->is_constant()) {
3162 inc = RegisterOrConstant(as_long(data));
3163 assert_different_registers(dst, addr.base(), tmp,
3164 rscratch1, rscratch2);
3165 } else {
3166 inc = RegisterOrConstant(as_reg(data));
3167 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3168 rscratch1, rscratch2);
3169 }
3170 __ lea(tmp, addr);
3171 (_masm->*add)(dst, inc, tmp);
3172 break;
3173 }
3174 case lir_xchg:
3175 {
3176 Register tmp = tmp_op->as_register();
3177 Register obj = as_reg(data);
3178 Register dst = as_reg(dest);
3179 if (is_oop && UseCompressedOops) {
3180 __ encode_heap_oop(rscratch2, obj);
3181 obj = rscratch2;
3182 }
3183 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3184 __ lea(tmp, addr);
3185 (_masm->*xchg)(dst, obj, tmp);
3186 if (is_oop && UseCompressedOops) {
3187 __ decode_heap_oop(dst);
3188 }
3189 }
3190 break;
3191 default:
3192 ShouldNotReachHere();
3193 }
3194 __ membar(__ AnyAny);
3195 }
3196
3197 #undef __