1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2019, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "gc/shared/barrierSet.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "memory/universe.hpp"
39 #include "nativeInst_ppc.hpp"
40 #include "oops/compressedOops.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/safepointMechanism.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45
46 #define __ _masm->
47
48
49 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
50
51
52 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
53 Unimplemented(); return false; // Currently not used on this platform.
54 }
55
56
57 LIR_Opr LIR_Assembler::receiverOpr() {
58 return FrameMap::R3_oop_opr;
59 }
60
61
62 LIR_Opr LIR_Assembler::osrBufferPointer() {
63 return FrameMap::R3_opr;
64 }
65
66
67 // This specifies the stack pointer decrement needed to build the frame.
68 int LIR_Assembler::initial_frame_size_in_bytes() const {
69 return in_bytes(frame_map()->framesize_in_bytes());
70 }
71
72
73 // Inline cache check: the inline cached class is in inline_cache_reg;
74 // we fetch the class of the receiver and compare it with the cached class.
75 // If they do not match we jump to slow case.
76 int LIR_Assembler::check_icache() {
77 int offset = __ offset();
78 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
79 return offset;
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = R20;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
92 __ mtctr(klass);
93 __ bctr();
94
95 __ bind(L_skip_barrier);
96 }
97
98 void LIR_Assembler::osr_entry() {
99 // On-stack-replacement entry sequence:
100 //
101 // 1. Create a new compiled activation.
102 // 2. Initialize local variables in the compiled activation. The expression
103 // stack must be empty at the osr_bci; it is not initialized.
104 // 3. Jump to the continuation address in compiled code to resume execution.
105
106 // OSR entry point
107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
108 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
109 ValueStack* entry_state = osr_entry->end()->state();
110 int number_of_locks = entry_state->locks_size();
111
112 // Create a frame for the compiled activation.
113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
114
115 // OSR buffer is
116 //
117 // locals[nlocals-1..0]
118 // monitors[number_of_locks-1..0]
119 //
120 // Locals is a direct copy of the interpreter frame so in the osr buffer
121 // the first slot in the local array is the last local from the interpreter
122 // and the last slot is local[0] (receiver) from the interpreter.
123 //
124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
126 // in the interpreter frame (the method lock if a sync method).
127
128 // Initialize monitors in the compiled activation.
129 // R3: pointer to osr buffer
130 //
131 // All other registers are dead at this point and the locals will be
132 // copied into place by code emitted in the IR.
133
134 Register OSR_buf = osrBufferPointer()->as_register();
135 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
136 int monitor_offset = BytesPerWord * method()->max_locals() +
137 (2 * BytesPerWord) * (number_of_locks - 1);
138 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
139 // the OSR buffer using 2 word entries: first the lock and then
140 // the oop.
141 for (int i = 0; i < number_of_locks; i++) {
142 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
143 #ifdef ASSERT
144 // Verify the interpreter's monitor has a non-null object.
145 {
146 Label L;
147 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
148 __ cmpdi(CCR0, R0, 0);
149 __ bne(CCR0, L);
150 __ stop("locked object is NULL");
151 __ bind(L);
152 }
153 #endif // ASSERT
154 // Copy the lock field into the compiled activation.
155 Address ml = frame_map()->address_for_monitor_lock(i),
156 mo = frame_map()->address_for_monitor_object(i);
157 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
158 __ ld(R0, slot_offset + 0, OSR_buf);
159 __ std(R0, ml.disp(), ml.base());
160 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
161 __ std(R0, mo.disp(), mo.base());
162 }
163 }
164 }
165
166
167 int LIR_Assembler::emit_exception_handler() {
168 // If the last instruction is a call (typically to do a throw which
169 // is coming at the end after block reordering) the return address
170 // must still point into the code area in order to avoid assertion
171 // failures when searching for the corresponding bci => add a nop
172 // (was bug 5/14/1999 - gri).
173 __ nop();
174
175 // Generate code for the exception handler.
176 address handler_base = __ start_a_stub(exception_handler_size());
177
178 if (handler_base == NULL) {
179 // Not enough space left for the handler.
180 bailout("exception handler overflow");
181 return -1;
182 }
183
184 int offset = code_offset();
185 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
186 //__ load_const_optimized(R0, entry_point);
187 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
188 __ mtctr(R0);
189 __ bctr();
190
191 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
192 __ end_a_stub();
193
194 return offset;
195 }
196
197
198 // Emit the code to remove the frame from the stack in the exception
199 // unwind path.
200 int LIR_Assembler::emit_unwind_handler() {
201 _masm->block_comment("Unwind handler");
202
203 int offset = code_offset();
204 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
205 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
206
207 // Fetch the exception from TLS and clear out exception related thread state.
208 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
209 __ li(R0, 0);
210 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
211 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
212
213 __ bind(_unwind_handler_entry);
214 __ verify_not_null_oop(Rexception);
215 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
216
217 // Perform needed unlocking
218 MonitorExitStub* stub = NULL;
219 if (method()->is_synchronized()) {
220 monitor_address(0, FrameMap::R4_opr);
221 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
222 __ unlock_object(R5, R6, R4, *stub->entry());
223 __ bind(*stub->continuation());
224 }
225
226 if (compilation()->env()->dtrace_method_probes()) {
227 Unimplemented();
228 }
229
230 // Dispatch to the unwind logic.
231 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
232 //__ load_const_optimized(R0, unwind_stub);
233 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
234 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
235 __ mtctr(R0);
236 __ bctr();
237
238 // Emit the slow path assembly.
239 if (stub != NULL) {
240 stub->emit_code(this);
241 }
242
243 return offset;
244 }
245
246
247 int LIR_Assembler::emit_deopt_handler() {
248 // If the last instruction is a call (typically to do a throw which
249 // is coming at the end after block reordering) the return address
250 // must still point into the code area in order to avoid assertion
251 // failures when searching for the corresponding bci => add a nop
252 // (was bug 5/14/1999 - gri).
253 __ nop();
254
255 // Generate code for deopt handler.
256 address handler_base = __ start_a_stub(deopt_handler_size());
257
258 if (handler_base == NULL) {
259 // Not enough space left for the handler.
260 bailout("deopt handler overflow");
261 return -1;
262 }
263
264 int offset = code_offset();
265 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
266
267 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
268 __ end_a_stub();
269
270 return offset;
271 }
272
273
274 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
275 if (o == NULL) {
276 __ li(reg, 0);
277 } else {
278 AddressLiteral addrlit = __ constant_oop_address(o);
279 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
280 }
281 }
282
283
284 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
285 // Allocate a new index in table to hold the object once it's been patched.
286 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
287 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
288
289 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
290 __ load_const(reg, addrlit, R0);
291
292 patching_epilog(patch, lir_patch_normal, reg, info);
293 }
294
295
296 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
297 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
298 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
299 }
300
301
302 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
303 // Allocate a new index in table to hold the klass once it's been patched.
304 int index = __ oop_recorder()->allocate_metadata_index(NULL);
305 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
306
307 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
308 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
309 __ load_const(reg, addrlit, R0);
310
311 patching_epilog(patch, lir_patch_normal, reg, info);
312 }
313
314
315 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
316 const bool is_int = result->is_single_cpu();
317 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
318 Register Rdivisor = noreg;
319 Register Rscratch = temp->as_register();
320 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
321 long divisor = -1;
322
323 if (right->is_register()) {
324 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
325 } else {
326 divisor = is_int ? right->as_constant_ptr()->as_jint()
327 : right->as_constant_ptr()->as_jlong();
328 }
329
330 assert(Rdividend != Rscratch, "");
331 assert(Rdivisor != Rscratch, "");
332 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
333
334 if (Rdivisor == noreg) {
335 if (divisor == 1) { // stupid, but can happen
336 if (code == lir_idiv) {
337 __ mr_if_needed(Rresult, Rdividend);
338 } else {
339 __ li(Rresult, 0);
340 }
341
342 } else if (is_power_of_2(divisor)) {
343 // Convert division by a power of two into some shifts and logical operations.
344 int log2 = log2_intptr(divisor);
345
346 // Round towards 0.
347 if (divisor == 2) {
348 if (is_int) {
349 __ srwi(Rscratch, Rdividend, 31);
350 } else {
351 __ srdi(Rscratch, Rdividend, 63);
352 }
353 } else {
354 if (is_int) {
355 __ srawi(Rscratch, Rdividend, 31);
356 } else {
357 __ sradi(Rscratch, Rdividend, 63);
358 }
359 __ clrldi(Rscratch, Rscratch, 64-log2);
360 }
361 __ add(Rscratch, Rdividend, Rscratch);
362
363 if (code == lir_idiv) {
364 if (is_int) {
365 __ srawi(Rresult, Rscratch, log2);
366 } else {
367 __ sradi(Rresult, Rscratch, log2);
368 }
369 } else { // lir_irem
370 __ clrrdi(Rscratch, Rscratch, log2);
371 __ sub(Rresult, Rdividend, Rscratch);
372 }
373
374 } else if (divisor == -1) {
375 if (code == lir_idiv) {
376 __ neg(Rresult, Rdividend);
377 } else {
378 __ li(Rresult, 0);
379 }
380
381 } else {
382 __ load_const_optimized(Rscratch, divisor);
383 if (code == lir_idiv) {
384 if (is_int) {
385 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
386 } else {
387 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
388 }
389 } else {
390 assert(Rscratch != R0, "need both");
391 if (is_int) {
392 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
393 __ mullw(Rscratch, R0, Rscratch);
394 } else {
395 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
396 __ mulld(Rscratch, R0, Rscratch);
397 }
398 __ sub(Rresult, Rdividend, Rscratch);
399 }
400
401 }
402 return;
403 }
404
405 Label regular, done;
406 if (is_int) {
407 __ cmpwi(CCR0, Rdivisor, -1);
408 } else {
409 __ cmpdi(CCR0, Rdivisor, -1);
410 }
411 __ bne(CCR0, regular);
412 if (code == lir_idiv) {
413 __ neg(Rresult, Rdividend);
414 __ b(done);
415 __ bind(regular);
416 if (is_int) {
417 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
418 } else {
419 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
420 }
421 } else { // lir_irem
422 __ li(Rresult, 0);
423 __ b(done);
424 __ bind(regular);
425 if (is_int) {
426 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
427 __ mullw(Rscratch, Rscratch, Rdivisor);
428 } else {
429 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
430 __ mulld(Rscratch, Rscratch, Rdivisor);
431 }
432 __ sub(Rresult, Rdividend, Rscratch);
433 }
434 __ bind(done);
435 }
436
437
438 void LIR_Assembler::emit_op3(LIR_Op3* op) {
439 switch (op->code()) {
440 case lir_idiv:
441 case lir_irem:
442 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
443 op->result_opr(), op->info());
444 break;
445 case lir_fmad:
446 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
447 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
448 break;
449 case lir_fmaf:
450 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
451 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
452 break;
453 default: ShouldNotReachHere(); break;
454 }
455 }
456
457
458 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
459 #ifdef ASSERT
460 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
461 if (op->block() != NULL) _branch_target_blocks.append(op->block());
462 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
463 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
464 #endif
465
466 Label *L = op->label();
467 if (op->cond() == lir_cond_always) {
468 __ b(*L);
469 } else {
470 Label done;
471 bool is_unordered = false;
472 if (op->code() == lir_cond_float_branch) {
473 assert(op->ublock() != NULL, "must have unordered successor");
474 is_unordered = true;
475 } else {
476 assert(op->code() == lir_branch, "just checking");
477 }
478
479 bool positive = false;
480 Assembler::Condition cond = Assembler::equal;
481 switch (op->cond()) {
482 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
483 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
484 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
485 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
486 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
487 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
488 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
489 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
490 default: ShouldNotReachHere();
491 }
492 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
493 int bi = Assembler::bi0(BOOL_RESULT, cond);
494 if (is_unordered) {
495 if (positive) {
496 if (op->ublock() == op->block()) {
497 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
498 }
499 } else {
500 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
501 }
502 }
503 __ bc_far_optimized(bo, bi, *L);
504 __ bind(done);
505 }
506 }
507
508
509 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
510 Bytecodes::Code code = op->bytecode();
511 LIR_Opr src = op->in_opr(),
512 dst = op->result_opr();
513
514 switch(code) {
515 case Bytecodes::_i2l: {
516 __ extsw(dst->as_register_lo(), src->as_register());
517 break;
518 }
519 case Bytecodes::_l2i: {
520 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
521 break;
522 }
523 case Bytecodes::_i2b: {
524 __ extsb(dst->as_register(), src->as_register());
525 break;
526 }
527 case Bytecodes::_i2c: {
528 __ clrldi(dst->as_register(), src->as_register(), 64-16);
529 break;
530 }
531 case Bytecodes::_i2s: {
532 __ extsh(dst->as_register(), src->as_register());
533 break;
534 }
535 case Bytecodes::_i2d:
536 case Bytecodes::_l2d: {
537 bool src_in_memory = !VM_Version::has_mtfprd();
538 FloatRegister rdst = dst->as_double_reg();
539 FloatRegister rsrc;
540 if (src_in_memory) {
541 rsrc = src->as_double_reg(); // via mem
542 } else {
543 // move src to dst register
544 if (code == Bytecodes::_i2d) {
545 __ mtfprwa(rdst, src->as_register());
546 } else {
547 __ mtfprd(rdst, src->as_register_lo());
548 }
549 rsrc = rdst;
550 }
551 __ fcfid(rdst, rsrc);
552 break;
553 }
554 case Bytecodes::_i2f:
555 case Bytecodes::_l2f: {
556 bool src_in_memory = !VM_Version::has_mtfprd();
557 FloatRegister rdst = dst->as_float_reg();
558 FloatRegister rsrc;
559 if (src_in_memory) {
560 rsrc = src->as_double_reg(); // via mem
561 } else {
562 // move src to dst register
563 if (code == Bytecodes::_i2f) {
564 __ mtfprwa(rdst, src->as_register());
565 } else {
566 __ mtfprd(rdst, src->as_register_lo());
567 }
568 rsrc = rdst;
569 }
570 if (VM_Version::has_fcfids()) {
571 __ fcfids(rdst, rsrc);
572 } else {
573 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
574 __ fcfid(rdst, rsrc);
575 __ frsp(rdst, rdst);
576 }
577 break;
578 }
579 case Bytecodes::_f2d: {
580 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
581 break;
582 }
583 case Bytecodes::_d2f: {
584 __ frsp(dst->as_float_reg(), src->as_double_reg());
585 break;
586 }
587 case Bytecodes::_d2i:
588 case Bytecodes::_f2i: {
589 bool dst_in_memory = !VM_Version::has_mtfprd();
590 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
591 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
592 Label L;
593 // Result must be 0 if value is NaN; test by comparing value to itself.
594 __ fcmpu(CCR0, rsrc, rsrc);
595 if (dst_in_memory) {
596 __ li(R0, 0); // 0 in case of NAN
597 __ std(R0, addr.disp(), addr.base());
598 } else {
599 __ li(dst->as_register(), 0);
600 }
601 __ bso(CCR0, L);
602 __ fctiwz(rsrc, rsrc); // USE_KILL
603 if (dst_in_memory) {
604 __ stfd(rsrc, addr.disp(), addr.base());
605 } else {
606 __ mffprd(dst->as_register(), rsrc);
607 }
608 __ bind(L);
609 break;
610 }
611 case Bytecodes::_d2l:
612 case Bytecodes::_f2l: {
613 bool dst_in_memory = !VM_Version::has_mtfprd();
614 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
615 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
616 Label L;
617 // Result must be 0 if value is NaN; test by comparing value to itself.
618 __ fcmpu(CCR0, rsrc, rsrc);
619 if (dst_in_memory) {
620 __ li(R0, 0); // 0 in case of NAN
621 __ std(R0, addr.disp(), addr.base());
622 } else {
623 __ li(dst->as_register_lo(), 0);
624 }
625 __ bso(CCR0, L);
626 __ fctidz(rsrc, rsrc); // USE_KILL
627 if (dst_in_memory) {
628 __ stfd(rsrc, addr.disp(), addr.base());
629 } else {
630 __ mffprd(dst->as_register_lo(), rsrc);
631 }
632 __ bind(L);
633 break;
634 }
635
636 default: ShouldNotReachHere();
637 }
638 }
639
640
641 void LIR_Assembler::align_call(LIR_Code) {
642 // do nothing since all instructions are word aligned on ppc
643 }
644
645
646 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
647 int start_offset = __ offset();
648 // Put the entry point as a constant into the constant pool.
649 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
650 if (entry_point_toc_addr == NULL) {
651 bailout("const section overflow");
652 return false;
653 }
654 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
655
656 // Emit the trampoline stub which will be related to the branch-and-link below.
657 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
658 if (!stub) {
659 bailout("no space for trampoline stub");
660 return false;
661 }
662 return true;
663 }
664
665
666 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
667 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
668
669 bool success = emit_trampoline_stub_for_call(op->addr());
670 if (!success) { return; }
671
672 __ relocate(rtype);
673 // Note: At this point we do not have the address of the trampoline
674 // stub, and the entry point might be too far away for bl, so __ pc()
675 // serves as dummy and the bl will be patched later.
676 __ code()->set_insts_mark();
677 __ bl(__ pc());
678 add_call_info(code_offset(), op->info());
679 }
680
681
682 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
683 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
684
685 // Virtual call relocation will point to ic load.
686 address virtual_call_meta_addr = __ pc();
687 // Load a clear inline cache.
688 AddressLiteral empty_ic((address) Universe::non_oop_word());
689 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
690 if (!success) {
691 bailout("const section overflow");
692 return;
693 }
694 // Call to fixup routine. Fixup routine uses ScopeDesc info
695 // to determine who we intended to call.
696 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
697
698 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
699 if (!success) { return; }
700
701 // Note: At this point we do not have the address of the trampoline
702 // stub, and the entry point might be too far away for bl, so __ pc()
703 // serves as dummy and the bl will be patched later.
704 __ bl(__ pc());
705 add_call_info(code_offset(), op->info());
706 }
707
708
709 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
710 ShouldNotReachHere(); // ic_call is used instead.
711 }
712
713
714 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
715 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
716 __ null_check(addr, stub->entry());
717 append_code_stub(stub);
718 }
719
720
721 // Attention: caller must encode oop if needed
722 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
723 int store_offset;
724 if (!Assembler::is_simm16(offset)) {
725 // For offsets larger than a simm16 we setup the offset.
726 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
727 __ load_const_optimized(R0, offset);
728 store_offset = store(from_reg, base, R0, type, wide);
729 } else {
730 store_offset = code_offset();
731 switch (type) {
732 case T_BOOLEAN: // fall through
733 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
734 case T_CHAR :
735 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
736 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
737 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
738 case T_ADDRESS:
739 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
740 case T_ARRAY : // fall through
741 case T_OBJECT:
742 {
743 if (UseCompressedOops && !wide) {
744 // Encoding done in caller
745 __ stw(from_reg->as_register(), offset, base);
746 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
747 } else {
748 __ std(from_reg->as_register(), offset, base);
749 __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
750 }
751 break;
752 }
753 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
754 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
755 default : ShouldNotReachHere();
756 }
757 }
758 return store_offset;
759 }
760
761
762 // Attention: caller must encode oop if needed
763 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
764 int store_offset = code_offset();
765 switch (type) {
766 case T_BOOLEAN: // fall through
767 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
768 case T_CHAR :
769 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
770 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
771 case T_LONG :
772 #ifdef _LP64
773 __ stdx(from_reg->as_register_lo(), base, disp);
774 #else
775 Unimplemented();
776 #endif
777 break;
778 case T_ADDRESS:
779 __ stdx(from_reg->as_register(), base, disp);
780 break;
781 case T_ARRAY : // fall through
782 case T_OBJECT:
783 {
784 if (UseCompressedOops && !wide) {
785 // Encoding done in caller.
786 __ stwx(from_reg->as_register(), base, disp);
787 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
788 } else {
789 __ stdx(from_reg->as_register(), base, disp);
790 __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
791 }
792 break;
793 }
794 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
795 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
796 default : ShouldNotReachHere();
797 }
798 return store_offset;
799 }
800
801
802 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
803 int load_offset;
804 if (!Assembler::is_simm16(offset)) {
805 // For offsets larger than a simm16 we setup the offset.
806 __ load_const_optimized(R0, offset);
807 load_offset = load(base, R0, to_reg, type, wide);
808 } else {
809 load_offset = code_offset();
810 switch(type) {
811 case T_BOOLEAN: // fall through
812 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
813 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
814 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
815 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
816 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
817 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
818 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
819 case T_ADDRESS:
820 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
821 __ lwz(to_reg->as_register(), offset, base);
822 __ decode_klass_not_null(to_reg->as_register());
823 } else {
824 __ ld(to_reg->as_register(), offset, base);
825 }
826 break;
827 case T_ARRAY : // fall through
828 case T_OBJECT:
829 {
830 if (UseCompressedOops && !wide) {
831 __ lwz(to_reg->as_register(), offset, base);
832 __ decode_heap_oop(to_reg->as_register());
833 } else {
834 __ ld(to_reg->as_register(), offset, base);
835 }
836 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
837 break;
838 }
839 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
840 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
841 default : ShouldNotReachHere();
842 }
843 }
844 return load_offset;
845 }
846
847
848 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
849 int load_offset = code_offset();
850 switch(type) {
851 case T_BOOLEAN: // fall through
852 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
853 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
854 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
855 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
856 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
857 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
858 case T_ARRAY : // fall through
859 case T_OBJECT:
860 {
861 if (UseCompressedOops && !wide) {
862 __ lwzx(to_reg->as_register(), base, disp);
863 __ decode_heap_oop(to_reg->as_register());
864 } else {
865 __ ldx(to_reg->as_register(), base, disp);
866 }
867 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
868 break;
869 }
870 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
871 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
872 case T_LONG :
873 #ifdef _LP64
874 __ ldx(to_reg->as_register_lo(), base, disp);
875 #else
876 Unimplemented();
877 #endif
878 break;
879 default : ShouldNotReachHere();
880 }
881 return load_offset;
882 }
883
884
885 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
886 LIR_Const* c = src->as_constant_ptr();
887 Register src_reg = R0;
888 switch (c->type()) {
889 case T_INT:
890 case T_FLOAT: {
891 int value = c->as_jint_bits();
892 __ load_const_optimized(src_reg, value);
893 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
894 __ stw(src_reg, addr.disp(), addr.base());
895 break;
896 }
897 case T_ADDRESS: {
898 int value = c->as_jint_bits();
899 __ load_const_optimized(src_reg, value);
900 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
901 __ std(src_reg, addr.disp(), addr.base());
902 break;
903 }
904 case T_OBJECT: {
905 jobject2reg(c->as_jobject(), src_reg);
906 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
907 __ std(src_reg, addr.disp(), addr.base());
908 break;
909 }
910 case T_LONG:
911 case T_DOUBLE: {
912 int value = c->as_jlong_bits();
913 __ load_const_optimized(src_reg, value);
914 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
915 __ std(src_reg, addr.disp(), addr.base());
916 break;
917 }
918 default:
919 Unimplemented();
920 }
921 }
922
923
924 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
925 LIR_Const* c = src->as_constant_ptr();
926 LIR_Address* addr = dest->as_address_ptr();
927 Register base = addr->base()->as_pointer_register();
928 LIR_Opr tmp = LIR_OprFact::illegalOpr;
929 int offset = -1;
930 // Null check for large offsets in LIRGenerator::do_StoreField.
931 bool needs_explicit_null_check = !ImplicitNullChecks;
932
933 if (info != NULL && needs_explicit_null_check) {
934 explicit_null_check(base, info);
935 }
936
937 switch (c->type()) {
938 case T_FLOAT: type = T_INT;
939 case T_INT:
940 case T_ADDRESS: {
941 tmp = FrameMap::R0_opr;
942 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
943 break;
944 }
945 case T_DOUBLE: type = T_LONG;
946 case T_LONG: {
947 tmp = FrameMap::R0_long_opr;
948 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
949 break;
950 }
951 case T_OBJECT: {
952 tmp = FrameMap::R0_opr;
953 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
954 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
955 __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
956 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
957 __ ori(R0, R0, oop_addr.value() & 0xffff);
958 } else {
959 jobject2reg(c->as_jobject(), R0);
960 }
961 break;
962 }
963 default:
964 Unimplemented();
965 }
966
967 // Handle either reg+reg or reg+disp address.
968 if (addr->index()->is_valid()) {
969 assert(addr->disp() == 0, "must be zero");
970 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
971 } else {
972 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
973 offset = store(tmp, base, addr->disp(), type, wide, false);
974 }
975
976 if (info != NULL) {
977 assert(offset != -1, "offset should've been set");
978 if (!needs_explicit_null_check) {
979 add_debug_info_for_null_check(offset, info);
980 }
981 }
982 }
983
984
985 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
986 LIR_Const* c = src->as_constant_ptr();
987 LIR_Opr to_reg = dest;
988
989 switch (c->type()) {
990 case T_INT: {
991 assert(patch_code == lir_patch_none, "no patching handled here");
992 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
993 break;
994 }
995 case T_ADDRESS: {
996 assert(patch_code == lir_patch_none, "no patching handled here");
997 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
998 break;
999 }
1000 case T_LONG: {
1001 assert(patch_code == lir_patch_none, "no patching handled here");
1002 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
1003 break;
1004 }
1005
1006 case T_OBJECT: {
1007 if (patch_code == lir_patch_none) {
1008 jobject2reg(c->as_jobject(), to_reg->as_register());
1009 } else {
1010 jobject2reg_with_patching(to_reg->as_register(), info);
1011 }
1012 break;
1013 }
1014
1015 case T_METADATA:
1016 {
1017 if (patch_code == lir_patch_none) {
1018 metadata2reg(c->as_metadata(), to_reg->as_register());
1019 } else {
1020 klass2reg_with_patching(to_reg->as_register(), info);
1021 }
1022 }
1023 break;
1024
1025 case T_FLOAT:
1026 {
1027 if (to_reg->is_single_fpu()) {
1028 address const_addr = __ float_constant(c->as_jfloat());
1029 if (const_addr == NULL) {
1030 bailout("const section overflow");
1031 break;
1032 }
1033 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1034 __ relocate(rspec);
1035 __ load_const(R0, const_addr);
1036 __ lfsx(to_reg->as_float_reg(), R0);
1037 } else {
1038 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1039 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1040 }
1041 }
1042 break;
1043
1044 case T_DOUBLE:
1045 {
1046 if (to_reg->is_double_fpu()) {
1047 address const_addr = __ double_constant(c->as_jdouble());
1048 if (const_addr == NULL) {
1049 bailout("const section overflow");
1050 break;
1051 }
1052 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1053 __ relocate(rspec);
1054 __ load_const(R0, const_addr);
1055 __ lfdx(to_reg->as_double_reg(), R0);
1056 } else {
1057 assert(to_reg->is_double_cpu(), "Must be a long register.");
1058 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1059 }
1060 }
1061 break;
1062
1063 default:
1064 ShouldNotReachHere();
1065 }
1066 }
1067
1068
1069 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1070 Unimplemented(); return Address();
1071 }
1072
1073
1074 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1075 if (addr->index()->is_illegal()) {
1076 return (RegisterOrConstant)(addr->disp());
1077 } else {
1078 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1079 }
1080 }
1081
1082
1083 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1084 const Register tmp = R0;
1085 switch (type) {
1086 case T_INT:
1087 case T_FLOAT: {
1088 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1089 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1090 __ lwz(tmp, from.disp(), from.base());
1091 __ stw(tmp, to.disp(), to.base());
1092 break;
1093 }
1094 case T_ADDRESS:
1095 case T_OBJECT: {
1096 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1097 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1098 __ ld(tmp, from.disp(), from.base());
1099 __ std(tmp, to.disp(), to.base());
1100 break;
1101 }
1102 case T_LONG:
1103 case T_DOUBLE: {
1104 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1105 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1106 __ ld(tmp, from.disp(), from.base());
1107 __ std(tmp, to.disp(), to.base());
1108 break;
1109 }
1110
1111 default:
1112 ShouldNotReachHere();
1113 }
1114 }
1115
1116
1117 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1118 Unimplemented(); return Address();
1119 }
1120
1121
1122 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1123 Unimplemented(); return Address();
1124 }
1125
1126
1127 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1128 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1129
1130 assert(type != T_METADATA, "load of metadata ptr not supported");
1131 LIR_Address* addr = src_opr->as_address_ptr();
1132 LIR_Opr to_reg = dest;
1133
1134 Register src = addr->base()->as_pointer_register();
1135 Register disp_reg = noreg;
1136 int disp_value = addr->disp();
1137 bool needs_patching = (patch_code != lir_patch_none);
1138 // null check for large offsets in LIRGenerator::do_LoadField
1139 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1140
1141 if (info != NULL && needs_explicit_null_check) {
1142 explicit_null_check(src, info);
1143 }
1144
1145 if (addr->base()->type() == T_OBJECT) {
1146 __ verify_oop(src, FILE_AND_LINE);
1147 }
1148
1149 PatchingStub* patch = NULL;
1150 if (needs_patching) {
1151 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1152 assert(!to_reg->is_double_cpu() ||
1153 patch_code == lir_patch_none ||
1154 patch_code == lir_patch_normal, "patching doesn't match register");
1155 }
1156
1157 if (addr->index()->is_illegal()) {
1158 if (!Assembler::is_simm16(disp_value)) {
1159 if (needs_patching) {
1160 __ load_const32(R0, 0); // patchable int
1161 } else {
1162 __ load_const_optimized(R0, disp_value);
1163 }
1164 disp_reg = R0;
1165 }
1166 } else {
1167 disp_reg = addr->index()->as_pointer_register();
1168 assert(disp_value == 0, "can't handle 3 operand addresses");
1169 }
1170
1171 // Remember the offset of the load. The patching_epilog must be done
1172 // before the call to add_debug_info, otherwise the PcDescs don't get
1173 // entered in increasing order.
1174 int offset;
1175
1176 if (disp_reg == noreg) {
1177 assert(Assembler::is_simm16(disp_value), "should have set this up");
1178 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1179 } else {
1180 assert(!unaligned, "unexpected");
1181 offset = load(src, disp_reg, to_reg, type, wide);
1182 }
1183
1184 if (patch != NULL) {
1185 patching_epilog(patch, patch_code, src, info);
1186 }
1187 if (info != NULL && !needs_explicit_null_check) {
1188 add_debug_info_for_null_check(offset, info);
1189 }
1190 }
1191
1192
1193 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1194 Address addr;
1195 if (src->is_single_word()) {
1196 addr = frame_map()->address_for_slot(src->single_stack_ix());
1197 } else if (src->is_double_word()) {
1198 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1199 }
1200
1201 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1202 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1203 }
1204
1205
1206 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1207 Address addr;
1208 if (dest->is_single_word()) {
1209 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1210 } else if (dest->is_double_word()) {
1211 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1212 }
1213 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1214 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1215 }
1216
1217
1218 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1219 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1220 if (from_reg->is_double_fpu()) {
1221 // double to double moves
1222 assert(to_reg->is_double_fpu(), "should match");
1223 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1224 } else {
1225 // float to float moves
1226 assert(to_reg->is_single_fpu(), "should match");
1227 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1228 }
1229 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1230 if (from_reg->is_double_cpu()) {
1231 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1232 } else if (to_reg->is_double_cpu()) {
1233 // int to int moves
1234 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1235 } else {
1236 // int to int moves
1237 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1238 }
1239 } else {
1240 ShouldNotReachHere();
1241 }
1242 if (is_reference_type(to_reg->type())) {
1243 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1244 }
1245 }
1246
1247
1248 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1249 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1250 bool wide, bool unaligned) {
1251 assert(type != T_METADATA, "store of metadata ptr not supported");
1252 LIR_Address* addr = dest->as_address_ptr();
1253
1254 Register src = addr->base()->as_pointer_register();
1255 Register disp_reg = noreg;
1256 int disp_value = addr->disp();
1257 bool needs_patching = (patch_code != lir_patch_none);
1258 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1259 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1260 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1261 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1262 // Null check for large offsets in LIRGenerator::do_StoreField.
1263 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1264
1265 if (info != NULL && needs_explicit_null_check) {
1266 explicit_null_check(src, info);
1267 }
1268
1269 if (addr->base()->is_oop_register()) {
1270 __ verify_oop(src, FILE_AND_LINE);
1271 }
1272
1273 PatchingStub* patch = NULL;
1274 if (needs_patching) {
1275 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1276 assert(!from_reg->is_double_cpu() ||
1277 patch_code == lir_patch_none ||
1278 patch_code == lir_patch_normal, "patching doesn't match register");
1279 }
1280
1281 if (addr->index()->is_illegal()) {
1282 if (load_disp) {
1283 disp_reg = use_R29 ? R29_TOC : R0;
1284 if (needs_patching) {
1285 __ load_const32(disp_reg, 0); // patchable int
1286 } else {
1287 __ load_const_optimized(disp_reg, disp_value);
1288 }
1289 }
1290 } else {
1291 disp_reg = addr->index()->as_pointer_register();
1292 assert(disp_value == 0, "can't handle 3 operand addresses");
1293 }
1294
1295 // remember the offset of the store. The patching_epilog must be done
1296 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1297 // entered in increasing order.
1298 int offset;
1299
1300 if (compress_oop) {
1301 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1302 from_reg = FrameMap::as_opr(co);
1303 }
1304
1305 if (disp_reg == noreg) {
1306 assert(Assembler::is_simm16(disp_value), "should have set this up");
1307 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1308 } else {
1309 assert(!unaligned, "unexpected");
1310 offset = store(from_reg, src, disp_reg, type, wide);
1311 }
1312
1313 if (use_R29) {
1314 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1315 }
1316
1317 if (patch != NULL) {
1318 patching_epilog(patch, patch_code, src, info);
1319 }
1320
1321 if (info != NULL && !needs_explicit_null_check) {
1322 add_debug_info_for_null_check(offset, info);
1323 }
1324 }
1325
1326
1327 void LIR_Assembler::return_op(LIR_Opr result) {
1328 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1329 const Register polling_page = R12;
1330
1331 // Pop the stack before the safepoint code.
1332 int frame_size = initial_frame_size_in_bytes();
1333 if (Assembler::is_simm(frame_size, 16)) {
1334 __ addi(R1_SP, R1_SP, frame_size);
1335 } else {
1336 __ pop_frame();
1337 }
1338
1339 if (SafepointMechanism::uses_thread_local_poll()) {
1340 __ ld(polling_page, in_bytes(Thread::polling_page_offset()), R16_thread);
1341 } else {
1342 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0);
1343 }
1344
1345 // Restore return pc relative to callers' sp.
1346 __ ld(return_pc, _abi(lr), R1_SP);
1347 // Move return pc to LR.
1348 __ mtlr(return_pc);
1349
1350 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1351 __ reserved_stack_check(return_pc);
1352 }
1353
1354 // We need to mark the code position where the load from the safepoint
1355 // polling page was emitted as relocInfo::poll_return_type here.
1356 __ relocate(relocInfo::poll_return_type);
1357 __ load_from_polling_page(polling_page);
1358
1359 // Return.
1360 __ blr();
1361 }
1362
1363
1364 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1365 const Register poll_addr = tmp->as_register();
1366 if (SafepointMechanism::uses_thread_local_poll()) {
1367 __ ld(poll_addr, in_bytes(Thread::polling_page_offset()), R16_thread);
1368 } else {
1369 __ load_const_optimized(poll_addr, (intptr_t)os::get_polling_page(), R0);
1370 }
1371 if (info != NULL) {
1372 add_debug_info_for_branch(info);
1373 }
1374 int offset = __ offset();
1375 __ relocate(relocInfo::poll_type);
1376 __ load_from_polling_page(poll_addr);
1377
1378 return offset;
1379 }
1380
1381
1382 void LIR_Assembler::emit_static_call_stub() {
1383 address call_pc = __ pc();
1384 address stub = __ start_a_stub(static_call_stub_size());
1385 if (stub == NULL) {
1386 bailout("static call stub overflow");
1387 return;
1388 }
1389
1390 // For java_to_interp stubs we use R11_scratch1 as scratch register
1391 // and in call trampoline stubs we use R12_scratch2. This way we
1392 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1393 const Register reg_scratch = R11_scratch1;
1394
1395 // Create a static stub relocation which relates this stub
1396 // with the call instruction at insts_call_instruction_offset in the
1397 // instructions code-section.
1398 int start = __ offset();
1399 __ relocate(static_stub_Relocation::spec(call_pc));
1400
1401 // Now, create the stub's code:
1402 // - load the TOC
1403 // - load the inline cache oop from the constant pool
1404 // - load the call target from the constant pool
1405 // - call
1406 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1407 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1408 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1409
1410 if (ReoptimizeCallSequences) {
1411 __ b64_patchable((address)-1, relocInfo::none);
1412 } else {
1413 AddressLiteral a((address)-1);
1414 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1415 __ mtctr(reg_scratch);
1416 __ bctr();
1417 }
1418 if (!success) {
1419 bailout("const section overflow");
1420 return;
1421 }
1422
1423 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1424 __ end_a_stub();
1425 }
1426
1427
1428 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1429 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1430 if (opr1->is_single_fpu()) {
1431 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1432 } else if (opr1->is_double_fpu()) {
1433 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1434 } else if (opr1->is_single_cpu()) {
1435 if (opr2->is_constant()) {
1436 switch (opr2->as_constant_ptr()->type()) {
1437 case T_INT:
1438 {
1439 jint con = opr2->as_constant_ptr()->as_jint();
1440 if (unsigned_comp) {
1441 if (Assembler::is_uimm(con, 16)) {
1442 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1443 } else {
1444 __ load_const_optimized(R0, con);
1445 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1446 }
1447 } else {
1448 if (Assembler::is_simm(con, 16)) {
1449 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1450 } else {
1451 __ load_const_optimized(R0, con);
1452 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1453 }
1454 }
1455 }
1456 break;
1457
1458 case T_OBJECT:
1459 // There are only equal/notequal comparisons on objects.
1460 {
1461 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1462 jobject con = opr2->as_constant_ptr()->as_jobject();
1463 if (con == NULL) {
1464 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1465 } else {
1466 jobject2reg(con, R0);
1467 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1468 }
1469 }
1470 break;
1471
1472 case T_METADATA:
1473 // We only need, for now, comparison with NULL for metadata.
1474 {
1475 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1476 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1477 if (p == NULL) {
1478 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1479 } else {
1480 ShouldNotReachHere();
1481 }
1482 }
1483 break;
1484
1485 default:
1486 ShouldNotReachHere();
1487 break;
1488 }
1489 } else {
1490 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1491 if (is_reference_type(opr1->type())) {
1492 // There are only equal/notequal comparisons on objects.
1493 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1494 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1495 } else {
1496 if (unsigned_comp) {
1497 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1498 } else {
1499 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1500 }
1501 }
1502 }
1503 } else if (opr1->is_double_cpu()) {
1504 if (opr2->is_constant()) {
1505 jlong con = opr2->as_constant_ptr()->as_jlong();
1506 if (unsigned_comp) {
1507 if (Assembler::is_uimm(con, 16)) {
1508 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1509 } else {
1510 __ load_const_optimized(R0, con);
1511 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1512 }
1513 } else {
1514 if (Assembler::is_simm(con, 16)) {
1515 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1516 } else {
1517 __ load_const_optimized(R0, con);
1518 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1519 }
1520 }
1521 } else if (opr2->is_register()) {
1522 if (unsigned_comp) {
1523 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1524 } else {
1525 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1526 }
1527 } else {
1528 ShouldNotReachHere();
1529 }
1530 } else {
1531 ShouldNotReachHere();
1532 }
1533 }
1534
1535
1536 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1537 const Register Rdst = dst->as_register();
1538 Label done;
1539 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1540 bool is_unordered_less = (code == lir_ucmp_fd2i);
1541 if (left->is_single_fpu()) {
1542 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1543 } else if (left->is_double_fpu()) {
1544 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1545 } else {
1546 ShouldNotReachHere();
1547 }
1548 __ li(Rdst, is_unordered_less ? -1 : 1);
1549 __ bso(CCR0, done);
1550 } else if (code == lir_cmp_l2i) {
1551 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1552 } else {
1553 ShouldNotReachHere();
1554 }
1555 __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01
1556 __ srwi(Rdst, R0, 30);
1557 __ srawi(R0, R0, 31);
1558 __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1
1559 __ bind(done);
1560 }
1561
1562
1563 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1564 if (src->is_constant()) {
1565 lasm->const2reg(src, dst, lir_patch_none, NULL);
1566 } else if (src->is_register()) {
1567 lasm->reg2reg(src, dst);
1568 } else if (src->is_stack()) {
1569 lasm->stack2reg(src, dst, dst->type());
1570 } else {
1571 ShouldNotReachHere();
1572 }
1573 }
1574
1575
1576 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1577 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1578 load_to_reg(this, opr1, result); // Condition doesn't matter.
1579 return;
1580 }
1581
1582 bool positive = false;
1583 Assembler::Condition cond = Assembler::equal;
1584 switch (condition) {
1585 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1586 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1587 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1588 case lir_cond_belowEqual:
1589 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1590 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1591 case lir_cond_aboveEqual:
1592 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1593 default: ShouldNotReachHere();
1594 }
1595
1596 // Try to use isel on >=Power7.
1597 if (VM_Version::has_isel() && result->is_cpu_register()) {
1598 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1599 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1600
1601 // We can use result_reg to load one operand if not already in register.
1602 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1603 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1604
1605 if (first != second) {
1606 if (!o1_is_reg) {
1607 load_to_reg(this, opr1, result);
1608 }
1609
1610 if (!o2_is_reg) {
1611 load_to_reg(this, opr2, result);
1612 }
1613
1614 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1615 return;
1616 }
1617 } // isel
1618
1619 load_to_reg(this, opr1, result);
1620
1621 Label skip;
1622 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1623 int bi = Assembler::bi0(BOOL_RESULT, cond);
1624 __ bc(bo, bi, skip);
1625
1626 load_to_reg(this, opr2, result);
1627 __ bind(skip);
1628 }
1629
1630
1631 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1632 CodeEmitInfo* info, bool pop_fpu_stack) {
1633 assert(info == NULL, "unused on this code path");
1634 assert(left->is_register(), "wrong items state");
1635 assert(dest->is_register(), "wrong items state");
1636
1637 if (right->is_register()) {
1638 if (dest->is_float_kind()) {
1639
1640 FloatRegister lreg, rreg, res;
1641 if (right->is_single_fpu()) {
1642 lreg = left->as_float_reg();
1643 rreg = right->as_float_reg();
1644 res = dest->as_float_reg();
1645 switch (code) {
1646 case lir_add: __ fadds(res, lreg, rreg); break;
1647 case lir_sub: __ fsubs(res, lreg, rreg); break;
1648 case lir_mul: // fall through
1649 case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break;
1650 case lir_div: // fall through
1651 case lir_div_strictfp: __ fdivs(res, lreg, rreg); break;
1652 default: ShouldNotReachHere();
1653 }
1654 } else {
1655 lreg = left->as_double_reg();
1656 rreg = right->as_double_reg();
1657 res = dest->as_double_reg();
1658 switch (code) {
1659 case lir_add: __ fadd(res, lreg, rreg); break;
1660 case lir_sub: __ fsub(res, lreg, rreg); break;
1661 case lir_mul: // fall through
1662 case lir_mul_strictfp: __ fmul(res, lreg, rreg); break;
1663 case lir_div: // fall through
1664 case lir_div_strictfp: __ fdiv(res, lreg, rreg); break;
1665 default: ShouldNotReachHere();
1666 }
1667 }
1668
1669 } else if (dest->is_double_cpu()) {
1670
1671 Register dst_lo = dest->as_register_lo();
1672 Register op1_lo = left->as_pointer_register();
1673 Register op2_lo = right->as_pointer_register();
1674
1675 switch (code) {
1676 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1677 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1678 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1679 default: ShouldNotReachHere();
1680 }
1681 } else {
1682 assert (right->is_single_cpu(), "Just Checking");
1683
1684 Register lreg = left->as_register();
1685 Register res = dest->as_register();
1686 Register rreg = right->as_register();
1687 switch (code) {
1688 case lir_add: __ add (res, lreg, rreg); break;
1689 case lir_sub: __ sub (res, lreg, rreg); break;
1690 case lir_mul: __ mullw(res, lreg, rreg); break;
1691 default: ShouldNotReachHere();
1692 }
1693 }
1694 } else {
1695 assert (right->is_constant(), "must be constant");
1696
1697 if (dest->is_single_cpu()) {
1698 Register lreg = left->as_register();
1699 Register res = dest->as_register();
1700 int simm16 = right->as_constant_ptr()->as_jint();
1701
1702 switch (code) {
1703 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1704 simm16 = -simm16;
1705 case lir_add: if (res == lreg && simm16 == 0) break;
1706 __ addi(res, lreg, simm16); break;
1707 case lir_mul: if (res == lreg && simm16 == 1) break;
1708 __ mulli(res, lreg, simm16); break;
1709 default: ShouldNotReachHere();
1710 }
1711 } else {
1712 Register lreg = left->as_pointer_register();
1713 Register res = dest->as_register_lo();
1714 long con = right->as_constant_ptr()->as_jlong();
1715 assert(Assembler::is_simm16(con), "must be simm16");
1716
1717 switch (code) {
1718 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1719 con = -con;
1720 case lir_add: if (res == lreg && con == 0) break;
1721 __ addi(res, lreg, (int)con); break;
1722 case lir_mul: if (res == lreg && con == 1) break;
1723 __ mulli(res, lreg, (int)con); break;
1724 default: ShouldNotReachHere();
1725 }
1726 }
1727 }
1728 }
1729
1730
1731 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1732 switch (code) {
1733 case lir_sqrt: {
1734 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1735 break;
1736 }
1737 case lir_abs: {
1738 __ fabs(dest->as_double_reg(), value->as_double_reg());
1739 break;
1740 }
1741 default: {
1742 ShouldNotReachHere();
1743 break;
1744 }
1745 }
1746 }
1747
1748
1749 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1750 if (right->is_constant()) { // see do_LogicOp
1751 long uimm;
1752 Register d, l;
1753 if (dest->is_single_cpu()) {
1754 uimm = right->as_constant_ptr()->as_jint();
1755 d = dest->as_register();
1756 l = left->as_register();
1757 } else {
1758 uimm = right->as_constant_ptr()->as_jlong();
1759 d = dest->as_register_lo();
1760 l = left->as_register_lo();
1761 }
1762 long uimms = (unsigned long)uimm >> 16,
1763 uimmss = (unsigned long)uimm >> 32;
1764
1765 switch (code) {
1766 case lir_logic_and:
1767 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) {
1768 __ andi(d, l, uimm); // special cases
1769 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1770 else { __ andi_(d, l, uimm); }
1771 break;
1772
1773 case lir_logic_or:
1774 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1775 else { __ ori(d, l, uimm); }
1776 break;
1777
1778 case lir_logic_xor:
1779 if (uimm == -1) { __ nand(d, l, l); } // special case
1780 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1781 else { __ xori(d, l, uimm); }
1782 break;
1783
1784 default: ShouldNotReachHere();
1785 }
1786 } else {
1787 assert(right->is_register(), "right should be in register");
1788
1789 if (dest->is_single_cpu()) {
1790 switch (code) {
1791 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1792 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1793 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1794 default: ShouldNotReachHere();
1795 }
1796 } else {
1797 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1798 left->as_register_lo();
1799 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1800 right->as_register_lo();
1801
1802 switch (code) {
1803 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1804 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1805 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1806 default: ShouldNotReachHere();
1807 }
1808 }
1809 }
1810 }
1811
1812
1813 int LIR_Assembler::shift_amount(BasicType t) {
1814 int elem_size = type2aelembytes(t);
1815 switch (elem_size) {
1816 case 1 : return 0;
1817 case 2 : return 1;
1818 case 4 : return 2;
1819 case 8 : return 3;
1820 }
1821 ShouldNotReachHere();
1822 return -1;
1823 }
1824
1825
1826 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1827 info->add_register_oop(exceptionOop);
1828
1829 // Reuse the debug info from the safepoint poll for the throw op itself.
1830 address pc_for_athrow = __ pc();
1831 int pc_for_athrow_offset = __ offset();
1832 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1833 //__ relocate(rspec);
1834 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1835 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1836 add_call_info(pc_for_athrow_offset, info); // for exception handler
1837
1838 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1839 : Runtime1::handle_exception_nofpu_id);
1840 //__ load_const_optimized(R0, stub);
1841 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1842 __ mtctr(R0);
1843 __ bctr();
1844 }
1845
1846
1847 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1848 // Note: Not used with EnableDebuggingOnDemand.
1849 assert(exceptionOop->as_register() == R3, "should match");
1850 __ b(_unwind_handler_entry);
1851 }
1852
1853
1854 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1855 Register src = op->src()->as_register();
1856 Register dst = op->dst()->as_register();
1857 Register src_pos = op->src_pos()->as_register();
1858 Register dst_pos = op->dst_pos()->as_register();
1859 Register length = op->length()->as_register();
1860 Register tmp = op->tmp()->as_register();
1861 Register tmp2 = R0;
1862
1863 int flags = op->flags();
1864 ciArrayKlass* default_type = op->expected_type();
1865 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1866 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1867
1868 // Set up the arraycopy stub information.
1869 ArrayCopyStub* stub = op->stub();
1870 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1871
1872 // Always do stub if no type information is available. It's ok if
1873 // the known type isn't loaded since the code sanity checks
1874 // in debug mode and the type isn't required when we know the exact type
1875 // also check that the type is an array type.
1876 if (op->expected_type() == NULL) {
1877 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1878 length->is_nonvolatile(), "must preserve");
1879 address copyfunc_addr = StubRoutines::generic_arraycopy();
1880 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1881
1882 // 3 parms are int. Convert to long.
1883 __ mr(R3_ARG1, src);
1884 __ extsw(R4_ARG2, src_pos);
1885 __ mr(R5_ARG3, dst);
1886 __ extsw(R6_ARG4, dst_pos);
1887 __ extsw(R7_ARG5, length);
1888
1889 #ifndef PRODUCT
1890 if (PrintC1Statistics) {
1891 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1892 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1893 __ lwz(R11_scratch1, simm16_offs, tmp);
1894 __ addi(R11_scratch1, R11_scratch1, 1);
1895 __ stw(R11_scratch1, simm16_offs, tmp);
1896 }
1897 #endif
1898 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1899
1900 __ nand(tmp, R3_RET, R3_RET);
1901 __ subf(length, tmp, length);
1902 __ add(src_pos, tmp, src_pos);
1903 __ add(dst_pos, tmp, dst_pos);
1904
1905 __ cmpwi(CCR0, R3_RET, 0);
1906 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1907 __ bind(*stub->continuation());
1908 return;
1909 }
1910
1911 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1912 Label cont, slow, copyfunc;
1913
1914 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1915 LIR_OpArrayCopy::dst_null_check |
1916 LIR_OpArrayCopy::src_pos_positive_check |
1917 LIR_OpArrayCopy::dst_pos_positive_check |
1918 LIR_OpArrayCopy::length_positive_check);
1919
1920 // Use only one conditional branch for simple checks.
1921 if (simple_check_flag_set) {
1922 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1923
1924 // Make sure src and dst are non-null.
1925 if (flags & LIR_OpArrayCopy::src_null_check) {
1926 __ cmpdi(combined_check, src, 0);
1927 tmp_check = CCR0;
1928 }
1929
1930 if (flags & LIR_OpArrayCopy::dst_null_check) {
1931 __ cmpdi(tmp_check, dst, 0);
1932 if (tmp_check != combined_check) {
1933 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1934 }
1935 tmp_check = CCR0;
1936 }
1937
1938 // Clear combined_check.eq if not already used.
1939 if (tmp_check == combined_check) {
1940 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1941 tmp_check = CCR0;
1942 }
1943
1944 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1945 // Test src_pos register.
1946 __ cmpwi(tmp_check, src_pos, 0);
1947 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1948 }
1949
1950 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1951 // Test dst_pos register.
1952 __ cmpwi(tmp_check, dst_pos, 0);
1953 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1954 }
1955
1956 if (flags & LIR_OpArrayCopy::length_positive_check) {
1957 // Make sure length isn't negative.
1958 __ cmpwi(tmp_check, length, 0);
1959 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1960 }
1961
1962 __ beq(combined_check, slow);
1963 }
1964
1965 // If the compiler was not able to prove that exact type of the source or the destination
1966 // of the arraycopy is an array type, check at runtime if the source or the destination is
1967 // an instance type.
1968 if (flags & LIR_OpArrayCopy::type_check) {
1969 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1970 __ load_klass(tmp, dst);
1971 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1972 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1973 __ bge(CCR0, slow);
1974 }
1975
1976 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1977 __ load_klass(tmp, src);
1978 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1979 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1980 __ bge(CCR0, slow);
1981 }
1982 }
1983
1984 // Higher 32bits must be null.
1985 __ extsw(length, length);
1986
1987 __ extsw(src_pos, src_pos);
1988 if (flags & LIR_OpArrayCopy::src_range_check) {
1989 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1990 __ add(tmp, length, src_pos);
1991 __ cmpld(CCR0, tmp2, tmp);
1992 __ ble(CCR0, slow);
1993 }
1994
1995 __ extsw(dst_pos, dst_pos);
1996 if (flags & LIR_OpArrayCopy::dst_range_check) {
1997 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1998 __ add(tmp, length, dst_pos);
1999 __ cmpld(CCR0, tmp2, tmp);
2000 __ ble(CCR0, slow);
2001 }
2002
2003 int shift = shift_amount(basic_type);
2004
2005 if (!(flags & LIR_OpArrayCopy::type_check)) {
2006 __ b(cont);
2007 } else {
2008 // We don't know the array types are compatible.
2009 if (basic_type != T_OBJECT) {
2010 // Simple test for basic type arrays.
2011 if (UseCompressedClassPointers) {
2012 // We don't need decode because we just need to compare.
2013 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
2014 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2015 __ cmpw(CCR0, tmp, tmp2);
2016 } else {
2017 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
2018 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2019 __ cmpd(CCR0, tmp, tmp2);
2020 }
2021 __ beq(CCR0, cont);
2022 } else {
2023 // For object arrays, if src is a sub class of dst then we can
2024 // safely do the copy.
2025 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2026
2027 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2028 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2029
2030 __ load_klass(sub_klass, src);
2031 __ load_klass(super_klass, dst);
2032
2033 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2034 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
2035
2036 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2037 //__ load_const_optimized(tmp, slow_stc, tmp2);
2038 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2039 __ mtctr(tmp);
2040 __ bctrl(); // sets CR0
2041 __ beq(CCR0, cont);
2042
2043 if (copyfunc_addr != NULL) { // Use stub if available.
2044 __ bind(copyfunc);
2045 // Src is not a sub class of dst so we have to do a
2046 // per-element check.
2047 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2048 if ((flags & mask) != mask) {
2049 assert(flags & mask, "one of the two should be known to be an object array");
2050
2051 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2052 __ load_klass(tmp, src);
2053 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2054 __ load_klass(tmp, dst);
2055 }
2056
2057 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2058
2059 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2060 __ load_const_optimized(tmp, objArray_lh);
2061 __ cmpw(CCR0, tmp, tmp2);
2062 __ bne(CCR0, slow);
2063 }
2064
2065 Register src_ptr = R3_ARG1;
2066 Register dst_ptr = R4_ARG2;
2067 Register len = R5_ARG3;
2068 Register chk_off = R6_ARG4;
2069 Register super_k = R7_ARG5;
2070
2071 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2072 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2073 if (shift == 0) {
2074 __ add(src_ptr, src_pos, src_ptr);
2075 __ add(dst_ptr, dst_pos, dst_ptr);
2076 } else {
2077 __ sldi(tmp, src_pos, shift);
2078 __ sldi(tmp2, dst_pos, shift);
2079 __ add(src_ptr, tmp, src_ptr);
2080 __ add(dst_ptr, tmp2, dst_ptr);
2081 }
2082
2083 __ load_klass(tmp, dst);
2084 __ mr(len, length);
2085
2086 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2087 __ ld(super_k, ek_offset, tmp);
2088
2089 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2090 __ lwz(chk_off, sco_offset, super_k);
2091
2092 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2093
2094 #ifndef PRODUCT
2095 if (PrintC1Statistics) {
2096 Label failed;
2097 __ cmpwi(CCR0, R3_RET, 0);
2098 __ bne(CCR0, failed);
2099 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2100 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2101 __ lwz(R11_scratch1, simm16_offs, tmp);
2102 __ addi(R11_scratch1, R11_scratch1, 1);
2103 __ stw(R11_scratch1, simm16_offs, tmp);
2104 __ bind(failed);
2105 }
2106 #endif
2107
2108 __ nand(tmp, R3_RET, R3_RET);
2109 __ cmpwi(CCR0, R3_RET, 0);
2110 __ beq(CCR0, *stub->continuation());
2111
2112 #ifndef PRODUCT
2113 if (PrintC1Statistics) {
2114 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2115 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2116 __ lwz(R11_scratch1, simm16_offs, tmp);
2117 __ addi(R11_scratch1, R11_scratch1, 1);
2118 __ stw(R11_scratch1, simm16_offs, tmp);
2119 }
2120 #endif
2121
2122 __ subf(length, tmp, length);
2123 __ add(src_pos, tmp, src_pos);
2124 __ add(dst_pos, tmp, dst_pos);
2125 }
2126 }
2127 }
2128 __ bind(slow);
2129 __ b(*stub->entry());
2130 __ bind(cont);
2131
2132 #ifdef ASSERT
2133 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2134 // Sanity check the known type with the incoming class. For the
2135 // primitive case the types must match exactly with src.klass and
2136 // dst.klass each exactly matching the default type. For the
2137 // object array case, if no type check is needed then either the
2138 // dst type is exactly the expected type and the src type is a
2139 // subtype which we can't check or src is the same array as dst
2140 // but not necessarily exactly of type default_type.
2141 Label known_ok, halt;
2142 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2143 if (UseCompressedClassPointers) {
2144 // Tmp holds the default type. It currently comes uncompressed after the
2145 // load of a constant, so encode it.
2146 __ encode_klass_not_null(tmp);
2147 // Load the raw value of the dst klass, since we will be comparing
2148 // uncompressed values directly.
2149 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2150 __ cmpw(CCR0, tmp, tmp2);
2151 if (basic_type != T_OBJECT) {
2152 __ bne(CCR0, halt);
2153 // Load the raw value of the src klass.
2154 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2155 __ cmpw(CCR0, tmp, tmp2);
2156 __ beq(CCR0, known_ok);
2157 } else {
2158 __ beq(CCR0, known_ok);
2159 __ cmpw(CCR0, src, dst);
2160 __ beq(CCR0, known_ok);
2161 }
2162 } else {
2163 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2164 __ cmpd(CCR0, tmp, tmp2);
2165 if (basic_type != T_OBJECT) {
2166 __ bne(CCR0, halt);
2167 // Load the raw value of the src klass.
2168 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2169 __ cmpd(CCR0, tmp, tmp2);
2170 __ beq(CCR0, known_ok);
2171 } else {
2172 __ beq(CCR0, known_ok);
2173 __ cmpd(CCR0, src, dst);
2174 __ beq(CCR0, known_ok);
2175 }
2176 }
2177 __ bind(halt);
2178 __ stop("incorrect type information in arraycopy");
2179 __ bind(known_ok);
2180 }
2181 #endif
2182
2183 #ifndef PRODUCT
2184 if (PrintC1Statistics) {
2185 address counter = Runtime1::arraycopy_count_address(basic_type);
2186 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2187 __ lwz(R11_scratch1, simm16_offs, tmp);
2188 __ addi(R11_scratch1, R11_scratch1, 1);
2189 __ stw(R11_scratch1, simm16_offs, tmp);
2190 }
2191 #endif
2192
2193 Register src_ptr = R3_ARG1;
2194 Register dst_ptr = R4_ARG2;
2195 Register len = R5_ARG3;
2196
2197 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2198 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2199 if (shift == 0) {
2200 __ add(src_ptr, src_pos, src_ptr);
2201 __ add(dst_ptr, dst_pos, dst_ptr);
2202 } else {
2203 __ sldi(tmp, src_pos, shift);
2204 __ sldi(tmp2, dst_pos, shift);
2205 __ add(src_ptr, tmp, src_ptr);
2206 __ add(dst_ptr, tmp2, dst_ptr);
2207 }
2208
2209 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2210 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2211 const char *name;
2212 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2213
2214 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2215 __ mr(len, length);
2216 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2217
2218 __ bind(*stub->continuation());
2219 }
2220
2221
2222 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2223 if (dest->is_single_cpu()) {
2224 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2225 #ifdef _LP64
2226 if (left->type() == T_OBJECT) {
2227 switch (code) {
2228 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2229 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2230 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2231 default: ShouldNotReachHere();
2232 }
2233 } else
2234 #endif
2235 switch (code) {
2236 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2237 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2238 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2239 default: ShouldNotReachHere();
2240 }
2241 } else {
2242 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2243 switch (code) {
2244 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2245 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2246 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2247 default: ShouldNotReachHere();
2248 }
2249 }
2250 }
2251
2252
2253 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2254 #ifdef _LP64
2255 if (left->type() == T_OBJECT) {
2256 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2257 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2258 else {
2259 switch (code) {
2260 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2261 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2262 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2263 default: ShouldNotReachHere();
2264 }
2265 }
2266 return;
2267 }
2268 #endif
2269
2270 if (dest->is_single_cpu()) {
2271 count = count & 0x1F; // Java spec
2272 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2273 else {
2274 switch (code) {
2275 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2276 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2277 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2278 default: ShouldNotReachHere();
2279 }
2280 }
2281 } else if (dest->is_double_cpu()) {
2282 count = count & 63; // Java spec
2283 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2284 else {
2285 switch (code) {
2286 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2287 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2288 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2289 default: ShouldNotReachHere();
2290 }
2291 }
2292 } else {
2293 ShouldNotReachHere();
2294 }
2295 }
2296
2297
2298 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2299 if (op->init_check()) {
2300 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2301 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2302 } else {
2303 add_debug_info_for_null_check_here(op->stub()->info());
2304 }
2305 __ lbz(op->tmp1()->as_register(),
2306 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2307 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2308 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2309 }
2310 __ allocate_object(op->obj()->as_register(),
2311 op->tmp1()->as_register(),
2312 op->tmp2()->as_register(),
2313 op->tmp3()->as_register(),
2314 op->header_size(),
2315 op->object_size(),
2316 op->klass()->as_register(),
2317 *op->stub()->entry());
2318
2319 __ bind(*op->stub()->continuation());
2320 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2321 }
2322
2323
2324 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2325 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2326 if (UseSlowPath ||
2327 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2328 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2329 __ b(*op->stub()->entry());
2330 } else {
2331 __ allocate_array(op->obj()->as_register(),
2332 op->len()->as_register(),
2333 op->tmp1()->as_register(),
2334 op->tmp2()->as_register(),
2335 op->tmp3()->as_register(),
2336 arrayOopDesc::header_size(op->type()),
2337 type2aelembytes(op->type()),
2338 op->klass()->as_register(),
2339 *op->stub()->entry());
2340 }
2341 __ bind(*op->stub()->continuation());
2342 }
2343
2344
2345 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2346 ciMethodData *md, ciProfileData *data,
2347 Register recv, Register tmp1, Label* update_done) {
2348 uint i;
2349 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2350 Label next_test;
2351 // See if the receiver is receiver[n].
2352 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2353 __ verify_klass_ptr(tmp1);
2354 __ cmpd(CCR0, recv, tmp1);
2355 __ bne(CCR0, next_test);
2356
2357 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2358 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2359 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2360 __ b(*update_done);
2361
2362 __ bind(next_test);
2363 }
2364
2365 // Didn't find receiver; find next empty slot and fill it in.
2366 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2367 Label next_test;
2368 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2369 __ cmpdi(CCR0, tmp1, 0);
2370 __ bne(CCR0, next_test);
2371 __ li(tmp1, DataLayout::counter_increment);
2372 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2373 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2374 __ b(*update_done);
2375
2376 __ bind(next_test);
2377 }
2378 }
2379
2380
2381 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2382 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2383 md = method->method_data_or_null();
2384 assert(md != NULL, "Sanity");
2385 data = md->bci_to_data(bci);
2386 assert(data != NULL, "need data for checkcast");
2387 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2388 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2389 // The offset is large so bias the mdo by the base of the slot so
2390 // that the ld can use simm16s to reference the slots of the data.
2391 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2392 }
2393 }
2394
2395
2396 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2397 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2398 Register k_RInfo = op->tmp1()->as_register();
2399 Register klass_RInfo = op->tmp2()->as_register();
2400 Register Rtmp1 = op->tmp3()->as_register();
2401 Register dst = op->result_opr()->as_register();
2402 ciKlass* k = op->klass();
2403 bool should_profile = op->should_profile();
2404 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2405 bool reg_conflict = false;
2406 if (obj == k_RInfo) {
2407 k_RInfo = dst;
2408 reg_conflict = true;
2409 } else if (obj == klass_RInfo) {
2410 klass_RInfo = dst;
2411 reg_conflict = true;
2412 } else if (obj == Rtmp1) {
2413 Rtmp1 = dst;
2414 reg_conflict = true;
2415 }
2416 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2417
2418 __ cmpdi(CCR0, obj, 0);
2419
2420 ciMethodData* md = NULL;
2421 ciProfileData* data = NULL;
2422 int mdo_offset_bias = 0;
2423 if (should_profile) {
2424 ciMethod* method = op->profiled_method();
2425 assert(method != NULL, "Should have method");
2426 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2427
2428 Register mdo = k_RInfo;
2429 Register data_val = Rtmp1;
2430 Label not_null;
2431 __ bne(CCR0, not_null);
2432 metadata2reg(md->constant_encoding(), mdo);
2433 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2434 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2435 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2436 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2437 __ b(*obj_is_null);
2438 __ bind(not_null);
2439 } else {
2440 __ beq(CCR0, *obj_is_null);
2441 }
2442
2443 // get object class
2444 __ load_klass(klass_RInfo, obj);
2445
2446 if (k->is_loaded()) {
2447 metadata2reg(k->constant_encoding(), k_RInfo);
2448 } else {
2449 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2450 }
2451
2452 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2453 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2454 Label *success_target = should_profile ? &profile_cast_success : success;
2455
2456 if (op->fast_check()) {
2457 assert_different_registers(klass_RInfo, k_RInfo);
2458 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2459 if (should_profile) {
2460 __ bne(CCR0, *failure_target);
2461 // Fall through to success case.
2462 } else {
2463 __ beq(CCR0, *success);
2464 // Fall through to failure case.
2465 }
2466 } else {
2467 bool need_slow_path = true;
2468 if (k->is_loaded()) {
2469 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2470 need_slow_path = false;
2471 }
2472 // Perform the fast part of the checking logic.
2473 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2474 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2475 } else {
2476 // Perform the fast part of the checking logic.
2477 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2478 }
2479 if (!need_slow_path) {
2480 if (!should_profile) { __ b(*success); }
2481 } else {
2482 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2483 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2484 // Stub needs fixed registers (tmp1-3).
2485 Register original_k_RInfo = op->tmp1()->as_register();
2486 Register original_klass_RInfo = op->tmp2()->as_register();
2487 Register original_Rtmp1 = op->tmp3()->as_register();
2488 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2489 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2490 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2491 __ mr_if_needed(original_k_RInfo, k_RInfo);
2492 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2493 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2494 //__ load_const_optimized(original_Rtmp1, entry, R0);
2495 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2496 __ mtctr(original_Rtmp1);
2497 __ bctrl(); // sets CR0
2498 if (keep_obj_alive) {
2499 if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2500 __ mr(obj, dst);
2501 }
2502 if (should_profile) {
2503 __ bne(CCR0, *failure_target);
2504 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2505 // Fall through to success case.
2506 } else {
2507 __ beq(CCR0, *success);
2508 // Fall through to failure case.
2509 }
2510 }
2511 }
2512
2513 if (should_profile) {
2514 Register mdo = k_RInfo, recv = klass_RInfo;
2515 assert_different_registers(mdo, recv, Rtmp1);
2516 __ bind(profile_cast_success);
2517 metadata2reg(md->constant_encoding(), mdo);
2518 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2519 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2520 __ b(*success);
2521
2522 // Cast failure case.
2523 __ bind(profile_cast_failure);
2524 metadata2reg(md->constant_encoding(), mdo);
2525 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2526 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2527 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2528 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2529 }
2530
2531 __ bind(*failure);
2532 }
2533
2534
2535 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2536 LIR_Code code = op->code();
2537 if (code == lir_store_check) {
2538 Register value = op->object()->as_register();
2539 Register array = op->array()->as_register();
2540 Register k_RInfo = op->tmp1()->as_register();
2541 Register klass_RInfo = op->tmp2()->as_register();
2542 Register Rtmp1 = op->tmp3()->as_register();
2543 bool should_profile = op->should_profile();
2544
2545 __ verify_oop(value, FILE_AND_LINE);
2546 CodeStub* stub = op->stub();
2547 // Check if it needs to be profiled.
2548 ciMethodData* md = NULL;
2549 ciProfileData* data = NULL;
2550 int mdo_offset_bias = 0;
2551 if (should_profile) {
2552 ciMethod* method = op->profiled_method();
2553 assert(method != NULL, "Should have method");
2554 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2555 }
2556 Label profile_cast_success, failure, done;
2557 Label *success_target = should_profile ? &profile_cast_success : &done;
2558
2559 __ cmpdi(CCR0, value, 0);
2560 if (should_profile) {
2561 Label not_null;
2562 __ bne(CCR0, not_null);
2563 Register mdo = k_RInfo;
2564 Register data_val = Rtmp1;
2565 metadata2reg(md->constant_encoding(), mdo);
2566 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2567 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2568 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2569 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2570 __ b(done);
2571 __ bind(not_null);
2572 } else {
2573 __ beq(CCR0, done);
2574 }
2575 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2576 explicit_null_check(array, op->info_for_exception());
2577 } else {
2578 add_debug_info_for_null_check_here(op->info_for_exception());
2579 }
2580 __ load_klass(k_RInfo, array);
2581 __ load_klass(klass_RInfo, value);
2582
2583 // Get instance klass.
2584 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2585 // Perform the fast part of the checking logic.
2586 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2587
2588 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2589 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2590 //__ load_const_optimized(R0, slow_path);
2591 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2592 __ mtctr(R0);
2593 __ bctrl(); // sets CR0
2594 if (!should_profile) {
2595 __ beq(CCR0, done);
2596 __ bind(failure);
2597 } else {
2598 __ bne(CCR0, failure);
2599 // Fall through to the success case.
2600
2601 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2602 assert_different_registers(value, mdo, recv, tmp1);
2603 __ bind(profile_cast_success);
2604 metadata2reg(md->constant_encoding(), mdo);
2605 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2606 __ load_klass(recv, value);
2607 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2608 __ b(done);
2609
2610 // Cast failure case.
2611 __ bind(failure);
2612 metadata2reg(md->constant_encoding(), mdo);
2613 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2614 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2615 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2616 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2617 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2618 }
2619 __ b(*stub->entry());
2620 __ bind(done);
2621
2622 } else if (code == lir_checkcast) {
2623 Label success, failure;
2624 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2625 __ b(*op->stub()->entry());
2626 __ align(32, 12);
2627 __ bind(success);
2628 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2629 } else if (code == lir_instanceof) {
2630 Register dst = op->result_opr()->as_register();
2631 Label success, failure, done;
2632 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2633 __ li(dst, 0);
2634 __ b(done);
2635 __ align(32, 12);
2636 __ bind(success);
2637 __ li(dst, 1);
2638 __ bind(done);
2639 } else {
2640 ShouldNotReachHere();
2641 }
2642 }
2643
2644
2645 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2646 Register addr = op->addr()->as_pointer_register();
2647 Register cmp_value = noreg, new_value = noreg;
2648 bool is_64bit = false;
2649
2650 if (op->code() == lir_cas_long) {
2651 cmp_value = op->cmp_value()->as_register_lo();
2652 new_value = op->new_value()->as_register_lo();
2653 is_64bit = true;
2654 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2655 cmp_value = op->cmp_value()->as_register();
2656 new_value = op->new_value()->as_register();
2657 if (op->code() == lir_cas_obj) {
2658 if (UseCompressedOops) {
2659 Register t1 = op->tmp1()->as_register();
2660 Register t2 = op->tmp2()->as_register();
2661 cmp_value = __ encode_heap_oop(t1, cmp_value);
2662 new_value = __ encode_heap_oop(t2, new_value);
2663 } else {
2664 is_64bit = true;
2665 }
2666 }
2667 } else {
2668 Unimplemented();
2669 }
2670
2671 if (is_64bit) {
2672 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2673 MacroAssembler::MemBarNone,
2674 MacroAssembler::cmpxchgx_hint_atomic_update(),
2675 noreg, NULL, /*check without ldarx first*/true);
2676 } else {
2677 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2678 MacroAssembler::MemBarNone,
2679 MacroAssembler::cmpxchgx_hint_atomic_update(),
2680 noreg, /*check without ldarx first*/true);
2681 }
2682
2683 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2684 __ isync();
2685 } else {
2686 __ sync();
2687 }
2688 }
2689
2690 void LIR_Assembler::breakpoint() {
2691 __ illtrap();
2692 }
2693
2694
2695 void LIR_Assembler::push(LIR_Opr opr) {
2696 Unimplemented();
2697 }
2698
2699 void LIR_Assembler::pop(LIR_Opr opr) {
2700 Unimplemented();
2701 }
2702
2703
2704 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2705 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2706 Register dst = dst_opr->as_register();
2707 Register reg = mon_addr.base();
2708 int offset = mon_addr.disp();
2709 // Compute pointer to BasicLock.
2710 __ add_const_optimized(dst, reg, offset);
2711 }
2712
2713
2714 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2715 Register obj = op->obj_opr()->as_register();
2716 Register hdr = op->hdr_opr()->as_register();
2717 Register lock = op->lock_opr()->as_register();
2718
2719 // Obj may not be an oop.
2720 if (op->code() == lir_lock) {
2721 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2722 if (UseFastLocking) {
2723 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2724 // Add debug info for NullPointerException only if one is possible.
2725 if (op->info() != NULL) {
2726 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2727 explicit_null_check(obj, op->info());
2728 } else {
2729 add_debug_info_for_null_check_here(op->info());
2730 }
2731 }
2732 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2733 } else {
2734 // always do slow locking
2735 // note: The slow locking code could be inlined here, however if we use
2736 // slow locking, speed doesn't matter anyway and this solution is
2737 // simpler and requires less duplicated code - additionally, the
2738 // slow locking code is the same in either case which simplifies
2739 // debugging.
2740 __ b(*op->stub()->entry());
2741 }
2742 } else {
2743 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2744 if (UseFastLocking) {
2745 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2746 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2747 } else {
2748 // always do slow unlocking
2749 // note: The slow unlocking code could be inlined here, however if we use
2750 // slow unlocking, speed doesn't matter anyway and this solution is
2751 // simpler and requires less duplicated code - additionally, the
2752 // slow unlocking code is the same in either case which simplifies
2753 // debugging.
2754 __ b(*op->stub()->entry());
2755 }
2756 }
2757 __ bind(*op->stub()->continuation());
2758 }
2759
2760
2761 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2762 ciMethod* method = op->profiled_method();
2763 int bci = op->profiled_bci();
2764 ciMethod* callee = op->profiled_callee();
2765
2766 // Update counter for all call types.
2767 ciMethodData* md = method->method_data_or_null();
2768 assert(md != NULL, "Sanity");
2769 ciProfileData* data = md->bci_to_data(bci);
2770 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2771 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2772 Register mdo = op->mdo()->as_register();
2773 #ifdef _LP64
2774 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2775 Register tmp1 = op->tmp1()->as_register_lo();
2776 #else
2777 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2778 Register tmp1 = op->tmp1()->as_register();
2779 #endif
2780 metadata2reg(md->constant_encoding(), mdo);
2781 int mdo_offset_bias = 0;
2782 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2783 data->size_in_bytes())) {
2784 // The offset is large so bias the mdo by the base of the slot so
2785 // that the ld can use simm16s to reference the slots of the data.
2786 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2787 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2788 }
2789
2790 // Perform additional virtual call profiling for invokevirtual and
2791 // invokeinterface bytecodes
2792 if (op->should_profile_receiver_type()) {
2793 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2794 Register recv = op->recv()->as_register();
2795 assert_different_registers(mdo, tmp1, recv);
2796 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2797 ciKlass* known_klass = op->known_holder();
2798 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2799 // We know the type that will be seen at this call site; we can
2800 // statically update the MethodData* rather than needing to do
2801 // dynamic tests on the receiver type.
2802
2803 // NOTE: we should probably put a lock around this search to
2804 // avoid collisions by concurrent compilations.
2805 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2806 uint i;
2807 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2808 ciKlass* receiver = vc_data->receiver(i);
2809 if (known_klass->equals(receiver)) {
2810 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2811 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2812 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2813 return;
2814 }
2815 }
2816
2817 // Receiver type not found in profile data; select an empty slot.
2818
2819 // Note that this is less efficient than it should be because it
2820 // always does a write to the receiver part of the
2821 // VirtualCallData rather than just the first time.
2822 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2823 ciKlass* receiver = vc_data->receiver(i);
2824 if (receiver == NULL) {
2825 metadata2reg(known_klass->constant_encoding(), tmp1);
2826 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2827
2828 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2829 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2830 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2831 return;
2832 }
2833 }
2834 } else {
2835 __ load_klass(recv, recv);
2836 Label update_done;
2837 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2838 // Receiver did not match any saved receiver and there is no empty row for it.
2839 // Increment total counter to indicate polymorphic case.
2840 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2841 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2842 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2843
2844 __ bind(update_done);
2845 }
2846 } else {
2847 // Static call
2848 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2849 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2850 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2851 }
2852 }
2853
2854
2855 void LIR_Assembler::align_backward_branch_target() {
2856 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2857 }
2858
2859
2860 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2861 Unimplemented();
2862 }
2863
2864
2865 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2866 // tmp must be unused
2867 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2868 assert(left->is_register(), "can only handle registers");
2869
2870 if (left->is_single_cpu()) {
2871 __ neg(dest->as_register(), left->as_register());
2872 } else if (left->is_single_fpu()) {
2873 __ fneg(dest->as_float_reg(), left->as_float_reg());
2874 } else if (left->is_double_fpu()) {
2875 __ fneg(dest->as_double_reg(), left->as_double_reg());
2876 } else {
2877 assert (left->is_double_cpu(), "Must be a long");
2878 __ neg(dest->as_register_lo(), left->as_register_lo());
2879 }
2880 }
2881
2882
2883 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2884 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2885 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2886 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2887 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2888 //__ load_const_optimized(R0, dest);
2889 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2890 __ mtctr(R0);
2891 __ bctrl();
2892 assert(info != NULL, "sanity");
2893 add_call_info_here(info);
2894 return;
2895 }
2896
2897 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2898 if (info != NULL) {
2899 add_call_info_here(info);
2900 }
2901 }
2902
2903
2904 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2905 ShouldNotReachHere(); // Not needed on _LP64.
2906 }
2907
2908 void LIR_Assembler::membar() {
2909 __ fence();
2910 }
2911
2912 void LIR_Assembler::membar_acquire() {
2913 __ acquire();
2914 }
2915
2916 void LIR_Assembler::membar_release() {
2917 __ release();
2918 }
2919
2920 void LIR_Assembler::membar_loadload() {
2921 __ membar(Assembler::LoadLoad);
2922 }
2923
2924 void LIR_Assembler::membar_storestore() {
2925 __ membar(Assembler::StoreStore);
2926 }
2927
2928 void LIR_Assembler::membar_loadstore() {
2929 __ membar(Assembler::LoadStore);
2930 }
2931
2932 void LIR_Assembler::membar_storeload() {
2933 __ membar(Assembler::StoreLoad);
2934 }
2935
2936 void LIR_Assembler::on_spin_wait() {
2937 Unimplemented();
2938 }
2939
2940 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2941 assert(patch_code == lir_patch_none, "Patch code not supported");
2942 LIR_Address* addr = addr_opr->as_address_ptr();
2943 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2944 if (addr->index()->is_illegal()) {
2945 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2946 } else {
2947 assert(addr->disp() == 0, "can't have both: index and disp");
2948 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2949 }
2950 }
2951
2952
2953 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2954 ShouldNotReachHere();
2955 }
2956
2957
2958 #ifdef ASSERT
2959 // Emit run-time assertion.
2960 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2961 Unimplemented();
2962 }
2963 #endif
2964
2965
2966 void LIR_Assembler::peephole(LIR_List* lir) {
2967 // Optimize instruction pairs before emitting.
2968 LIR_OpList* inst = lir->instructions_list();
2969 for (int i = 1; i < inst->length(); i++) {
2970 LIR_Op* op = inst->at(i);
2971
2972 // 2 register-register-moves
2973 if (op->code() == lir_move) {
2974 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2975 res2 = ((LIR_Op1*)op)->result_opr();
2976 if (in2->is_register() && res2->is_register()) {
2977 LIR_Op* prev = inst->at(i - 1);
2978 if (prev && prev->code() == lir_move) {
2979 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2980 res1 = ((LIR_Op1*)prev)->result_opr();
2981 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2982 inst->remove_at(i);
2983 }
2984 }
2985 }
2986 }
2987
2988 }
2989 return;
2990 }
2991
2992
2993 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2994 const LIR_Address *addr = src->as_address_ptr();
2995 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2996 const Register Rptr = addr->base()->as_pointer_register(),
2997 Rtmp = tmp->as_register();
2998 Register Rco = noreg;
2999 if (UseCompressedOops && data->is_oop()) {
3000 Rco = __ encode_heap_oop(Rtmp, data->as_register());
3001 }
3002
3003 Label Lretry;
3004 __ bind(Lretry);
3005
3006 if (data->type() == T_INT) {
3007 const Register Rold = dest->as_register(),
3008 Rsrc = data->as_register();
3009 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3010 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3011 if (code == lir_xadd) {
3012 __ add(Rtmp, Rsrc, Rold);
3013 __ stwcx_(Rtmp, Rptr);
3014 } else {
3015 __ stwcx_(Rsrc, Rptr);
3016 }
3017 } else if (data->is_oop()) {
3018 assert(code == lir_xchg, "xadd for oops");
3019 const Register Rold = dest->as_register();
3020 if (UseCompressedOops) {
3021 assert_different_registers(Rptr, Rold, Rco);
3022 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3023 __ stwcx_(Rco, Rptr);
3024 } else {
3025 const Register Robj = data->as_register();
3026 assert_different_registers(Rptr, Rold, Robj);
3027 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3028 __ stdcx_(Robj, Rptr);
3029 }
3030 } else if (data->type() == T_LONG) {
3031 const Register Rold = dest->as_register_lo(),
3032 Rsrc = data->as_register_lo();
3033 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3034 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3035 if (code == lir_xadd) {
3036 __ add(Rtmp, Rsrc, Rold);
3037 __ stdcx_(Rtmp, Rptr);
3038 } else {
3039 __ stdcx_(Rsrc, Rptr);
3040 }
3041 } else {
3042 ShouldNotReachHere();
3043 }
3044
3045 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3046 __ bne_predict_not_taken(CCR0, Lretry);
3047 } else {
3048 __ bne( CCR0, Lretry);
3049 }
3050
3051 if (UseCompressedOops && data->is_oop()) {
3052 __ decode_heap_oop(dest->as_register());
3053 }
3054 }
3055
3056
3057 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3058 Register obj = op->obj()->as_register();
3059 Register tmp = op->tmp()->as_pointer_register();
3060 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3061 ciKlass* exact_klass = op->exact_klass();
3062 intptr_t current_klass = op->current_klass();
3063 bool not_null = op->not_null();
3064 bool no_conflict = op->no_conflict();
3065
3066 Label Lupdate, Ldo_update, Ldone;
3067
3068 bool do_null = !not_null;
3069 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3070 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3071
3072 assert(do_null || do_update, "why are we here?");
3073 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3074
3075 __ verify_oop(obj, FILE_AND_LINE);
3076
3077 if (do_null) {
3078 if (!TypeEntries::was_null_seen(current_klass)) {
3079 __ cmpdi(CCR0, obj, 0);
3080 __ bne(CCR0, Lupdate);
3081 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3082 __ ori(R0, R0, TypeEntries::null_seen);
3083 if (do_update) {
3084 __ b(Ldo_update);
3085 } else {
3086 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3087 }
3088 } else {
3089 if (do_update) {
3090 __ cmpdi(CCR0, obj, 0);
3091 __ beq(CCR0, Ldone);
3092 }
3093 }
3094 #ifdef ASSERT
3095 } else {
3096 __ cmpdi(CCR0, obj, 0);
3097 __ bne(CCR0, Lupdate);
3098 __ stop("unexpect null obj", 0x9652);
3099 #endif
3100 }
3101
3102 __ bind(Lupdate);
3103 if (do_update) {
3104 Label Lnext;
3105 const Register klass = R29_TOC; // kill and reload
3106 bool klass_reg_used = false;
3107 #ifdef ASSERT
3108 if (exact_klass != NULL) {
3109 Label ok;
3110 klass_reg_used = true;
3111 __ load_klass(klass, obj);
3112 metadata2reg(exact_klass->constant_encoding(), R0);
3113 __ cmpd(CCR0, klass, R0);
3114 __ beq(CCR0, ok);
3115 __ stop("exact klass and actual klass differ", 0x8564);
3116 __ bind(ok);
3117 }
3118 #endif
3119
3120 if (!no_conflict) {
3121 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3122 klass_reg_used = true;
3123 if (exact_klass != NULL) {
3124 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3125 metadata2reg(exact_klass->constant_encoding(), klass);
3126 } else {
3127 __ load_klass(klass, obj);
3128 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3129 }
3130
3131 // Like InterpreterMacroAssembler::profile_obj_type
3132 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3133 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3134 __ cmpd(CCR1, R0, klass);
3135 // Klass seen before, nothing to do (regardless of unknown bit).
3136 //beq(CCR1, do_nothing);
3137
3138 __ andi_(R0, klass, TypeEntries::type_unknown);
3139 // Already unknown. Nothing to do anymore.
3140 //bne(CCR0, do_nothing);
3141 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3142 __ beq(CCR0, Lnext);
3143
3144 if (TypeEntries::is_type_none(current_klass)) {
3145 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3146 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3147 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3148 }
3149
3150 } else {
3151 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3152 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3153
3154 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3155 __ andi_(R0, tmp, TypeEntries::type_unknown);
3156 // Already unknown. Nothing to do anymore.
3157 __ bne(CCR0, Lnext);
3158 }
3159
3160 // Different than before. Cannot keep accurate profile.
3161 __ ori(R0, tmp, TypeEntries::type_unknown);
3162 } else {
3163 // There's a single possible klass at this profile point
3164 assert(exact_klass != NULL, "should be");
3165 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3166
3167 if (TypeEntries::is_type_none(current_klass)) {
3168 klass_reg_used = true;
3169 metadata2reg(exact_klass->constant_encoding(), klass);
3170
3171 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3172 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3173 __ cmpd(CCR1, R0, klass);
3174 // Klass seen before, nothing to do (regardless of unknown bit).
3175 __ beq(CCR1, Lnext);
3176 #ifdef ASSERT
3177 {
3178 Label ok;
3179 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3180 __ beq(CCR0, ok); // First time here.
3181
3182 __ stop("unexpected profiling mismatch", 0x7865);
3183 __ bind(ok);
3184 }
3185 #endif
3186 // First time here. Set profile type.
3187 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3188 } else {
3189 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3190 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3191
3192 // Already unknown. Nothing to do anymore.
3193 __ andi_(R0, tmp, TypeEntries::type_unknown);
3194 __ bne(CCR0, Lnext);
3195
3196 // Different than before. Cannot keep accurate profile.
3197 __ ori(R0, tmp, TypeEntries::type_unknown);
3198 }
3199 }
3200
3201 __ bind(Ldo_update);
3202 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3203
3204 __ bind(Lnext);
3205 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3206 }
3207 __ bind(Ldone);
3208 }
3209
3210
3211 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3212 assert(op->crc()->is_single_cpu(), "crc must be register");
3213 assert(op->val()->is_single_cpu(), "byte value must be register");
3214 assert(op->result_opr()->is_single_cpu(), "result must be register");
3215 Register crc = op->crc()->as_register();
3216 Register val = op->val()->as_register();
3217 Register res = op->result_opr()->as_register();
3218
3219 assert_different_registers(val, crc, res);
3220
3221 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3222 __ kernel_crc32_singleByteReg(crc, val, res, true);
3223 __ mr(res, crc);
3224 }
3225
3226 #undef __