1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
26 #define CPU_X86_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class BiasedLockingCounters;
32
33 // Contains all the definitions needed for x86 assembly code generation.
34
35 // Calling convention
36 class Argument {
37 public:
38 enum {
39 #ifdef _LP64
40 #ifdef _WIN64
41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 #endif // _WIN64
47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
49 #else
50 n_register_parameters = 0 // 0 registers used to pass arguments
51 #endif // _LP64
52 };
53 };
54
55
56 #ifdef _LP64
57 // Symbolically name the register arguments used by the c calling convention.
58 // Windows is different from linux/solaris. So much for standards...
59
60 #ifdef _WIN64
61
62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
64 REGISTER_DECLARATION(Register, c_rarg2, r8);
65 REGISTER_DECLARATION(Register, c_rarg3, r9);
66
67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71
72 #else
73
74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
78 REGISTER_DECLARATION(Register, c_rarg4, r8);
79 REGISTER_DECLARATION(Register, c_rarg5, r9);
80
81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89
90 #endif // _WIN64
91
92 // Symbolically name the register arguments used by the Java calling convention.
93 // We have control over the convention for java so we can do what we please.
94 // What pleases us is to offset the java calling convention so that when
95 // we call a suitable jni method the arguments are lined up and we don't
96 // have to do little shuffling. A suitable jni method is non-static and a
97 // small number of arguments (two fewer args on windows)
98 //
99 // |-------------------------------------------------------|
100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
101 // |-------------------------------------------------------|
102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
103 // | rdi rsi rdx rcx r8 r9 | solaris/linux
104 // |-------------------------------------------------------|
105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
106 // |-------------------------------------------------------|
107
108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
111 // Windows runs out of register args here
112 #ifdef _WIN64
113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
115 #else
116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
118 #endif /* _WIN64 */
119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120
121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129
130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132
133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135
136 #else
137 // rscratch1 will apear in 32bit code that is dead but of course must compile
138 // Using noreg ensures if the dead code is incorrectly live and executed it
139 // will cause an assertion failure
140 #define rscratch1 noreg
141 #define rscratch2 noreg
142
143 #endif // _LP64
144
145 // JSR 292
146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
149
150 // Address is an abstraction used to represent a memory location
151 // using any of the amd64 addressing modes with one object.
152 //
153 // Note: A register location is represented via a Register, not
154 // via an address for efficiency & simplicity reasons.
155
156 class ArrayAddress;
157
158 class Address {
159 public:
160 enum ScaleFactor {
161 no_scale = -1,
162 times_1 = 0,
163 times_2 = 1,
164 times_4 = 2,
165 times_8 = 3,
166 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
167 };
168 static ScaleFactor times(int size) {
169 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
170 if (size == 8) return times_8;
171 if (size == 4) return times_4;
172 if (size == 2) return times_2;
173 return times_1;
174 }
175 static int scale_size(ScaleFactor scale) {
176 assert(scale != no_scale, "");
177 assert(((1 << (int)times_1) == 1 &&
178 (1 << (int)times_2) == 2 &&
179 (1 << (int)times_4) == 4 &&
180 (1 << (int)times_8) == 8), "");
181 return (1 << (int)scale);
182 }
183
184 private:
185 Register _base;
186 Register _index;
187 XMMRegister _xmmindex;
188 ScaleFactor _scale;
189 int _disp;
190 bool _isxmmindex;
191 RelocationHolder _rspec;
192
193 // Easily misused constructors make them private
194 // %%% can we make these go away?
195 NOT_LP64(Address(address loc, RelocationHolder spec);)
196 Address(int disp, address loc, relocInfo::relocType rtype);
197 Address(int disp, address loc, RelocationHolder spec);
198
199 public:
200
201 int disp() { return _disp; }
202 // creation
203 Address()
204 : _base(noreg),
205 _index(noreg),
206 _xmmindex(xnoreg),
207 _scale(no_scale),
208 _disp(0),
209 _isxmmindex(false){
210 }
211
212 // No default displacement otherwise Register can be implicitly
213 // converted to 0(Register) which is quite a different animal.
214
215 Address(Register base, int disp)
216 : _base(base),
217 _index(noreg),
218 _xmmindex(xnoreg),
219 _scale(no_scale),
220 _disp(disp),
221 _isxmmindex(false){
222 }
223
224 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
225 : _base (base),
226 _index(index),
227 _xmmindex(xnoreg),
228 _scale(scale),
229 _disp (disp),
230 _isxmmindex(false) {
231 assert(!index->is_valid() == (scale == Address::no_scale),
232 "inconsistent address");
233 }
234
235 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
236 : _base (base),
237 _index(index.register_or_noreg()),
238 _xmmindex(xnoreg),
239 _scale(scale),
240 _disp (disp + (index.constant_or_zero() * scale_size(scale))),
241 _isxmmindex(false){
242 if (!index.is_register()) scale = Address::no_scale;
243 assert(!_index->is_valid() == (scale == Address::no_scale),
244 "inconsistent address");
245 }
246
247 Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
248 : _base (base),
249 _index(noreg),
250 _xmmindex(index),
251 _scale(scale),
252 _disp(disp),
253 _isxmmindex(true) {
254 assert(!index->is_valid() == (scale == Address::no_scale),
255 "inconsistent address");
256 }
257
258 Address plus_disp(int disp) const {
259 Address a = (*this);
260 a._disp += disp;
261 return a;
262 }
263 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
264 Address a = (*this);
265 a._disp += disp.constant_or_zero() * scale_size(scale);
266 if (disp.is_register()) {
267 assert(!a.index()->is_valid(), "competing indexes");
268 a._index = disp.as_register();
269 a._scale = scale;
270 }
271 return a;
272 }
273 bool is_same_address(Address a) const {
274 // disregard _rspec
275 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
276 }
277
278 // The following two overloads are used in connection with the
279 // ByteSize type (see sizes.hpp). They simplify the use of
280 // ByteSize'd arguments in assembly code. Note that their equivalent
281 // for the optimized build are the member functions with int disp
282 // argument since ByteSize is mapped to an int type in that case.
283 //
284 // Note: DO NOT introduce similar overloaded functions for WordSize
285 // arguments as in the optimized mode, both ByteSize and WordSize
286 // are mapped to the same type and thus the compiler cannot make a
287 // distinction anymore (=> compiler errors).
288
289 #ifdef ASSERT
290 Address(Register base, ByteSize disp)
291 : _base(base),
292 _index(noreg),
293 _xmmindex(xnoreg),
294 _scale(no_scale),
295 _disp(in_bytes(disp)),
296 _isxmmindex(false){
297 }
298
299 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
300 : _base(base),
301 _index(index),
302 _xmmindex(xnoreg),
303 _scale(scale),
304 _disp(in_bytes(disp)),
305 _isxmmindex(false){
306 assert(!index->is_valid() == (scale == Address::no_scale),
307 "inconsistent address");
308 }
309 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
310 : _base (base),
311 _index(index.register_or_noreg()),
312 _xmmindex(xnoreg),
313 _scale(scale),
314 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
315 _isxmmindex(false) {
316 if (!index.is_register()) scale = Address::no_scale;
317 assert(!_index->is_valid() == (scale == Address::no_scale),
318 "inconsistent address");
319 }
320
321 #endif // ASSERT
322
323 // accessors
324 bool uses(Register reg) const { return _base == reg || _index == reg; }
325 Register base() const { return _base; }
326 Register index() const { return _index; }
327 XMMRegister xmmindex() const { return _xmmindex; }
328 ScaleFactor scale() const { return _scale; }
329 int disp() const { return _disp; }
330 bool isxmmindex() const { return _isxmmindex; }
331
332 // Convert the raw encoding form into the form expected by the constructor for
333 // Address. An index of 4 (rsp) corresponds to having no index, so convert
334 // that to noreg for the Address constructor.
335 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
336
337 static Address make_array(ArrayAddress);
338
339 private:
340 bool base_needs_rex() const {
341 return _base != noreg && _base->encoding() >= 8;
342 }
343
344 bool index_needs_rex() const {
345 return _index != noreg &&_index->encoding() >= 8;
346 }
347
348 bool xmmindex_needs_rex() const {
349 return _xmmindex != xnoreg && _xmmindex->encoding() >= 8;
350 }
351
352 relocInfo::relocType reloc() const { return _rspec.type(); }
353
354 friend class Assembler;
355 friend class MacroAssembler;
356 friend class LIR_Assembler; // base/index/scale/disp
357 };
358
359 //
360 // AddressLiteral has been split out from Address because operands of this type
361 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
362 // the few instructions that need to deal with address literals are unique and the
363 // MacroAssembler does not have to implement every instruction in the Assembler
364 // in order to search for address literals that may need special handling depending
365 // on the instruction and the platform. As small step on the way to merging i486/amd64
366 // directories.
367 //
368 class AddressLiteral {
369 friend class ArrayAddress;
370 RelocationHolder _rspec;
371 // Typically we use AddressLiterals we want to use their rval
372 // However in some situations we want the lval (effect address) of the item.
373 // We provide a special factory for making those lvals.
374 bool _is_lval;
375
376 // If the target is far we'll need to load the ea of this to
377 // a register to reach it. Otherwise if near we can do rip
378 // relative addressing.
379
380 address _target;
381
382 protected:
383 // creation
384 AddressLiteral()
385 : _is_lval(false),
386 _target(NULL)
387 {}
388
389 public:
390
391
392 AddressLiteral(address target, relocInfo::relocType rtype);
393
394 AddressLiteral(address target, RelocationHolder const& rspec)
395 : _rspec(rspec),
396 _is_lval(false),
397 _target(target)
398 {}
399
400 AddressLiteral addr() {
401 AddressLiteral ret = *this;
402 ret._is_lval = true;
403 return ret;
404 }
405
406
407 private:
408
409 address target() { return _target; }
410 bool is_lval() { return _is_lval; }
411
412 relocInfo::relocType reloc() const { return _rspec.type(); }
413 const RelocationHolder& rspec() const { return _rspec; }
414
415 friend class Assembler;
416 friend class MacroAssembler;
417 friend class Address;
418 friend class LIR_Assembler;
419 };
420
421 // Convience classes
422 class RuntimeAddress: public AddressLiteral {
423
424 public:
425
426 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
427
428 };
429
430 class ExternalAddress: public AddressLiteral {
431 private:
432 static relocInfo::relocType reloc_for_target(address target) {
433 // Sometimes ExternalAddress is used for values which aren't
434 // exactly addresses, like the card table base.
435 // external_word_type can't be used for values in the first page
436 // so just skip the reloc in that case.
437 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
438 }
439
440 public:
441
442 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
443
444 };
445
446 class InternalAddress: public AddressLiteral {
447
448 public:
449
450 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
451
452 };
453
454 // x86 can do array addressing as a single operation since disp can be an absolute
455 // address amd64 can't. We create a class that expresses the concept but does extra
456 // magic on amd64 to get the final result
457
458 class ArrayAddress {
459 private:
460
461 AddressLiteral _base;
462 Address _index;
463
464 public:
465
466 ArrayAddress() {};
467 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
468 AddressLiteral base() { return _base; }
469 Address index() { return _index; }
470
471 };
472
473 class InstructionAttr;
474
475 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
476 // See fxsave and xsave(EVEX enabled) documentation for layout
477 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
478
479 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
480 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
481 // is what you get. The Assembler is generating code into a CodeBuffer.
482
483 class Assembler : public AbstractAssembler {
484 friend class AbstractAssembler; // for the non-virtual hack
485 friend class LIR_Assembler; // as_Address()
486 friend class StubGenerator;
487
488 public:
489 enum Condition { // The x86 condition codes used for conditional jumps/moves.
490 zero = 0x4,
491 notZero = 0x5,
492 equal = 0x4,
493 notEqual = 0x5,
494 less = 0xc,
495 lessEqual = 0xe,
496 greater = 0xf,
497 greaterEqual = 0xd,
498 below = 0x2,
499 belowEqual = 0x6,
500 above = 0x7,
501 aboveEqual = 0x3,
502 overflow = 0x0,
503 noOverflow = 0x1,
504 carrySet = 0x2,
505 carryClear = 0x3,
506 negative = 0x8,
507 positive = 0x9,
508 parity = 0xa,
509 noParity = 0xb
510 };
511
512 enum Prefix {
513 // segment overrides
514 CS_segment = 0x2e,
515 SS_segment = 0x36,
516 DS_segment = 0x3e,
517 ES_segment = 0x26,
518 FS_segment = 0x64,
519 GS_segment = 0x65,
520
521 REX = 0x40,
522
523 REX_B = 0x41,
524 REX_X = 0x42,
525 REX_XB = 0x43,
526 REX_R = 0x44,
527 REX_RB = 0x45,
528 REX_RX = 0x46,
529 REX_RXB = 0x47,
530
531 REX_W = 0x48,
532
533 REX_WB = 0x49,
534 REX_WX = 0x4A,
535 REX_WXB = 0x4B,
536 REX_WR = 0x4C,
537 REX_WRB = 0x4D,
538 REX_WRX = 0x4E,
539 REX_WRXB = 0x4F,
540
541 VEX_3bytes = 0xC4,
542 VEX_2bytes = 0xC5,
543 EVEX_4bytes = 0x62,
544 Prefix_EMPTY = 0x0
545 };
546
547 enum VexPrefix {
548 VEX_B = 0x20,
549 VEX_X = 0x40,
550 VEX_R = 0x80,
551 VEX_W = 0x80
552 };
553
554 enum ExexPrefix {
555 EVEX_F = 0x04,
556 EVEX_V = 0x08,
557 EVEX_Rb = 0x10,
558 EVEX_X = 0x40,
559 EVEX_Z = 0x80
560 };
561
562 enum VexSimdPrefix {
563 VEX_SIMD_NONE = 0x0,
564 VEX_SIMD_66 = 0x1,
565 VEX_SIMD_F3 = 0x2,
566 VEX_SIMD_F2 = 0x3
567 };
568
569 enum VexOpcode {
570 VEX_OPCODE_NONE = 0x0,
571 VEX_OPCODE_0F = 0x1,
572 VEX_OPCODE_0F_38 = 0x2,
573 VEX_OPCODE_0F_3A = 0x3,
574 VEX_OPCODE_MASK = 0x1F
575 };
576
577 enum AvxVectorLen {
578 AVX_128bit = 0x0,
579 AVX_256bit = 0x1,
580 AVX_512bit = 0x2,
581 AVX_NoVec = 0x4
582 };
583
584 enum EvexTupleType {
585 EVEX_FV = 0,
586 EVEX_HV = 4,
587 EVEX_FVM = 6,
588 EVEX_T1S = 7,
589 EVEX_T1F = 11,
590 EVEX_T2 = 13,
591 EVEX_T4 = 15,
592 EVEX_T8 = 17,
593 EVEX_HVM = 18,
594 EVEX_QVM = 19,
595 EVEX_OVM = 20,
596 EVEX_M128 = 21,
597 EVEX_DUP = 22,
598 EVEX_ETUP = 23
599 };
600
601 enum EvexInputSizeInBits {
602 EVEX_8bit = 0,
603 EVEX_16bit = 1,
604 EVEX_32bit = 2,
605 EVEX_64bit = 3,
606 EVEX_NObit = 4
607 };
608
609 enum WhichOperand {
610 // input to locate_operand, and format code for relocations
611 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
612 disp32_operand = 1, // embedded 32-bit displacement or address
613 call32_operand = 2, // embedded 32-bit self-relative displacement
614 #ifndef _LP64
615 _WhichOperand_limit = 3
616 #else
617 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
618 _WhichOperand_limit = 4
619 #endif
620 };
621
622 enum ComparisonPredicate {
623 eq = 0,
624 lt = 1,
625 le = 2,
626 _false = 3,
627 neq = 4,
628 nlt = 5,
629 nle = 6,
630 _true = 7
631 };
632
633 //---< calculate length of instruction >---
634 // As instruction size can't be found out easily on x86/x64,
635 // we just use '4' for len and maxlen.
636 // instruction must start at passed address
637 static unsigned int instr_len(unsigned char *instr) { return 4; }
638
639 //---< longest instructions >---
640 // Max instruction length is not specified in architecture documentation.
641 // We could use a "safe enough" estimate (15), but just default to
642 // instruction length guess from above.
643 static unsigned int instr_maxlen() { return 4; }
644
645 // NOTE: The general philopsophy of the declarations here is that 64bit versions
646 // of instructions are freely declared without the need for wrapping them an ifdef.
647 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
648 // In the .cpp file the implementations are wrapped so that they are dropped out
649 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
650 // to the size it was prior to merging up the 32bit and 64bit assemblers.
651 //
652 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
653 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
654
655 private:
656
657 bool _legacy_mode_bw;
658 bool _legacy_mode_dq;
659 bool _legacy_mode_vl;
660 bool _legacy_mode_vlbw;
661 bool _is_managed;
662 bool _vector_masking; // For stub code use only
663
664 class InstructionAttr *_attributes;
665
666 // 64bit prefixes
667 int prefix_and_encode(int reg_enc, bool byteinst = false);
668 int prefixq_and_encode(int reg_enc);
669
670 int prefix_and_encode(int dst_enc, int src_enc) {
671 return prefix_and_encode(dst_enc, false, src_enc, false);
672 }
673 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
674 int prefixq_and_encode(int dst_enc, int src_enc);
675
676 void prefix(Register reg);
677 void prefix(Register dst, Register src, Prefix p);
678 void prefix(Register dst, Address adr, Prefix p);
679 void prefix(Address adr);
680 void prefixq(Address adr);
681
682 void prefix(Address adr, Register reg, bool byteinst = false);
683 void prefix(Address adr, XMMRegister reg);
684 void prefixq(Address adr, Register reg);
685 void prefixq(Address adr, XMMRegister reg);
686
687 void prefetch_prefix(Address src);
688
689 void rex_prefix(Address adr, XMMRegister xreg,
690 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
691 int rex_prefix_and_encode(int dst_enc, int src_enc,
692 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
693
694 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
695
696 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
697 int nds_enc, VexSimdPrefix pre, VexOpcode opc);
698
699 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
700 VexSimdPrefix pre, VexOpcode opc,
701 InstructionAttr *attributes);
702
703 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
704 VexSimdPrefix pre, VexOpcode opc,
705 InstructionAttr *attributes);
706
707 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
708 VexOpcode opc, InstructionAttr *attributes);
709
710 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
711 VexOpcode opc, InstructionAttr *attributes);
712
713 // Helper functions for groups of instructions
714 void emit_arith_b(int op1, int op2, Register dst, int imm8);
715
716 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
717 // Force generation of a 4 byte immediate value even if it fits into 8bit
718 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
719 void emit_arith(int op1, int op2, Register dst, Register src);
720
721 bool emit_compressed_disp_byte(int &disp);
722
723 void emit_operand(Register reg,
724 Register base, Register index, Address::ScaleFactor scale,
725 int disp,
726 RelocationHolder const& rspec,
727 int rip_relative_correction = 0);
728
729 void emit_operand(XMMRegister reg, Register base, XMMRegister index,
730 Address::ScaleFactor scale,
731 int disp, RelocationHolder const& rspec);
732
733 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
734
735 // operands that only take the original 32bit registers
736 void emit_operand32(Register reg, Address adr);
737
738 void emit_operand(XMMRegister reg,
739 Register base, Register index, Address::ScaleFactor scale,
740 int disp,
741 RelocationHolder const& rspec);
742
743 void emit_operand(XMMRegister reg, Address adr);
744
745 void emit_operand(MMXRegister reg, Address adr);
746
747 // workaround gcc (3.2.1-7) bug
748 void emit_operand(Address adr, MMXRegister reg);
749
750
751 // Immediate-to-memory forms
752 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
753
754 void emit_farith(int b1, int b2, int i);
755
756
757 protected:
758 #ifdef ASSERT
759 void check_relocation(RelocationHolder const& rspec, int format);
760 #endif
761
762 void emit_data(jint data, relocInfo::relocType rtype, int format);
763 void emit_data(jint data, RelocationHolder const& rspec, int format);
764 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
765 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
766
767 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
768
769 // These are all easily abused and hence protected
770
771 // 32BIT ONLY SECTION
772 #ifndef _LP64
773 // Make these disappear in 64bit mode since they would never be correct
774 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
775 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
776
777 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
778 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
779
780 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
781 #else
782 // 64BIT ONLY SECTION
783 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
784
785 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
786 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
787
788 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
789 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
790 #endif // _LP64
791
792 // These are unique in that we are ensured by the caller that the 32bit
793 // relative in these instructions will always be able to reach the potentially
794 // 64bit address described by entry. Since they can take a 64bit address they
795 // don't have the 32 suffix like the other instructions in this class.
796
797 void call_literal(address entry, RelocationHolder const& rspec);
798 void jmp_literal(address entry, RelocationHolder const& rspec);
799
800 // Avoid using directly section
801 // Instructions in this section are actually usable by anyone without danger
802 // of failure but have performance issues that are addressed my enhanced
803 // instructions which will do the proper thing base on the particular cpu.
804 // We protect them because we don't trust you...
805
806 // Don't use next inc() and dec() methods directly. INC & DEC instructions
807 // could cause a partial flag stall since they don't set CF flag.
808 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
809 // which call inc() & dec() or add() & sub() in accordance with
810 // the product flag UseIncDec value.
811
812 void decl(Register dst);
813 void decl(Address dst);
814 void decq(Register dst);
815 void decq(Address dst);
816
817 void incl(Register dst);
818 void incl(Address dst);
819 void incq(Register dst);
820 void incq(Address dst);
821
822 // New cpus require use of movsd and movss to avoid partial register stall
823 // when loading from memory. But for old Opteron use movlpd instead of movsd.
824 // The selection is done in MacroAssembler::movdbl() and movflt().
825
826 // Move Scalar Single-Precision Floating-Point Values
827 void movss(XMMRegister dst, Address src);
828 void movss(XMMRegister dst, XMMRegister src);
829 void movss(Address dst, XMMRegister src);
830
831 // Move Scalar Double-Precision Floating-Point Values
832 void movsd(XMMRegister dst, Address src);
833 void movsd(XMMRegister dst, XMMRegister src);
834 void movsd(Address dst, XMMRegister src);
835 void movlpd(XMMRegister dst, Address src);
836
837 // New cpus require use of movaps and movapd to avoid partial register stall
838 // when moving between registers.
839 void movaps(XMMRegister dst, XMMRegister src);
840 void movapd(XMMRegister dst, XMMRegister src);
841
842 // End avoid using directly
843
844
845 // Instruction prefixes
846 void prefix(Prefix p);
847
848 public:
849
850 // Creation
851 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
852 init_attributes();
853 }
854
855 // Decoding
856 static address locate_operand(address inst, WhichOperand which);
857 static address locate_next_instruction(address inst);
858
859 // Utilities
860 static bool is_polling_page_far() NOT_LP64({ return false;});
861 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
862 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
863
864 // Generic instructions
865 // Does 32bit or 64bit as needed for the platform. In some sense these
866 // belong in macro assembler but there is no need for both varieties to exist
867
868 void init_attributes(void) {
869 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
870 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
871 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
872 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
873 _is_managed = false;
874 _vector_masking = false;
875 _attributes = NULL;
876 }
877
878 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
879 void clear_attributes(void) { _attributes = NULL; }
880
881 void set_managed(void) { _is_managed = true; }
882 void clear_managed(void) { _is_managed = false; }
883 bool is_managed(void) { return _is_managed; }
884
885 void lea(Register dst, Address src);
886
887 void mov(Register dst, Register src);
888
889 void pusha();
890 void popa();
891
892 void pushf();
893 void popf();
894
895 void push(int32_t imm32);
896
897 void push(Register src);
898
899 void pop(Register dst);
900
901 // These are dummies to prevent surprise implicit conversions to Register
902 void push(void* v);
903 void pop(void* v);
904
905 // These do register sized moves/scans
906 void rep_mov();
907 void rep_stos();
908 void rep_stosb();
909 void repne_scan();
910 #ifdef _LP64
911 void repne_scanl();
912 #endif
913
914 // Vanilla instructions in lexical order
915
916 void adcl(Address dst, int32_t imm32);
917 void adcl(Address dst, Register src);
918 void adcl(Register dst, int32_t imm32);
919 void adcl(Register dst, Address src);
920 void adcl(Register dst, Register src);
921
922 void adcq(Register dst, int32_t imm32);
923 void adcq(Register dst, Address src);
924 void adcq(Register dst, Register src);
925
926 void addb(Address dst, int imm8);
927 void addw(Address dst, int imm16);
928
929 void addl(Address dst, int32_t imm32);
930 void addl(Address dst, Register src);
931 void addl(Register dst, int32_t imm32);
932 void addl(Register dst, Address src);
933 void addl(Register dst, Register src);
934
935 void addq(Address dst, int32_t imm32);
936 void addq(Address dst, Register src);
937 void addq(Register dst, int32_t imm32);
938 void addq(Register dst, Address src);
939 void addq(Register dst, Register src);
940
941 #ifdef _LP64
942 //Add Unsigned Integers with Carry Flag
943 void adcxq(Register dst, Register src);
944
945 //Add Unsigned Integers with Overflow Flag
946 void adoxq(Register dst, Register src);
947 #endif
948
949 void addr_nop_4();
950 void addr_nop_5();
951 void addr_nop_7();
952 void addr_nop_8();
953
954 // Add Scalar Double-Precision Floating-Point Values
955 void addsd(XMMRegister dst, Address src);
956 void addsd(XMMRegister dst, XMMRegister src);
957
958 // Add Scalar Single-Precision Floating-Point Values
959 void addss(XMMRegister dst, Address src);
960 void addss(XMMRegister dst, XMMRegister src);
961
962 // AES instructions
963 void aesdec(XMMRegister dst, Address src);
964 void aesdec(XMMRegister dst, XMMRegister src);
965 void aesdeclast(XMMRegister dst, Address src);
966 void aesdeclast(XMMRegister dst, XMMRegister src);
967 void aesenc(XMMRegister dst, Address src);
968 void aesenc(XMMRegister dst, XMMRegister src);
969 void aesenclast(XMMRegister dst, Address src);
970 void aesenclast(XMMRegister dst, XMMRegister src);
971 // Vector AES instructions
972 void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
973 void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
974 void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
975 void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
976
977 void andl(Address dst, int32_t imm32);
978 void andl(Register dst, int32_t imm32);
979 void andl(Register dst, Address src);
980 void andl(Register dst, Register src);
981
982 void andq(Address dst, int32_t imm32);
983 void andq(Register dst, int32_t imm32);
984 void andq(Register dst, Address src);
985 void andq(Register dst, Register src);
986
987 // BMI instructions
988 void andnl(Register dst, Register src1, Register src2);
989 void andnl(Register dst, Register src1, Address src2);
990 void andnq(Register dst, Register src1, Register src2);
991 void andnq(Register dst, Register src1, Address src2);
992
993 void blsil(Register dst, Register src);
994 void blsil(Register dst, Address src);
995 void blsiq(Register dst, Register src);
996 void blsiq(Register dst, Address src);
997
998 void blsmskl(Register dst, Register src);
999 void blsmskl(Register dst, Address src);
1000 void blsmskq(Register dst, Register src);
1001 void blsmskq(Register dst, Address src);
1002
1003 void blsrl(Register dst, Register src);
1004 void blsrl(Register dst, Address src);
1005 void blsrq(Register dst, Register src);
1006 void blsrq(Register dst, Address src);
1007
1008 void bsfl(Register dst, Register src);
1009 void bsrl(Register dst, Register src);
1010
1011 #ifdef _LP64
1012 void bsfq(Register dst, Register src);
1013 void bsrq(Register dst, Register src);
1014 #endif
1015
1016 void bswapl(Register reg);
1017
1018 void bswapq(Register reg);
1019
1020 void call(Label& L, relocInfo::relocType rtype);
1021 void call(Register reg); // push pc; pc <- reg
1022 void call(Address adr); // push pc; pc <- adr
1023
1024 void cdql();
1025
1026 void cdqq();
1027
1028 void cld();
1029
1030 void clflush(Address adr);
1031 void clflushopt(Address adr);
1032 void clwb(Address adr);
1033
1034 void cmovl(Condition cc, Register dst, Register src);
1035 void cmovl(Condition cc, Register dst, Address src);
1036
1037 void cmovq(Condition cc, Register dst, Register src);
1038 void cmovq(Condition cc, Register dst, Address src);
1039
1040
1041 void cmpb(Address dst, int imm8);
1042
1043 void cmpl(Address dst, int32_t imm32);
1044
1045 void cmpl(Register dst, int32_t imm32);
1046 void cmpl(Register dst, Register src);
1047 void cmpl(Register dst, Address src);
1048
1049 void cmpq(Address dst, int32_t imm32);
1050 void cmpq(Address dst, Register src);
1051
1052 void cmpq(Register dst, int32_t imm32);
1053 void cmpq(Register dst, Register src);
1054 void cmpq(Register dst, Address src);
1055
1056 // these are dummies used to catch attempting to convert NULL to Register
1057 void cmpl(Register dst, void* junk); // dummy
1058 void cmpq(Register dst, void* junk); // dummy
1059
1060 void cmpw(Address dst, int imm16);
1061
1062 void cmpxchg8 (Address adr);
1063
1064 void cmpxchgb(Register reg, Address adr);
1065 void cmpxchgl(Register reg, Address adr);
1066
1067 void cmpxchgq(Register reg, Address adr);
1068
1069 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1070 void comisd(XMMRegister dst, Address src);
1071 void comisd(XMMRegister dst, XMMRegister src);
1072
1073 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1074 void comiss(XMMRegister dst, Address src);
1075 void comiss(XMMRegister dst, XMMRegister src);
1076
1077 // Identify processor type and features
1078 void cpuid();
1079
1080 // CRC32C
1081 void crc32(Register crc, Register v, int8_t sizeInBytes);
1082 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1083
1084 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1085 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1086 void cvtsd2ss(XMMRegister dst, Address src);
1087
1088 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1089 void cvtsi2sdl(XMMRegister dst, Register src);
1090 void cvtsi2sdl(XMMRegister dst, Address src);
1091 void cvtsi2sdq(XMMRegister dst, Register src);
1092 void cvtsi2sdq(XMMRegister dst, Address src);
1093
1094 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1095 void cvtsi2ssl(XMMRegister dst, Register src);
1096 void cvtsi2ssl(XMMRegister dst, Address src);
1097 void cvtsi2ssq(XMMRegister dst, Register src);
1098 void cvtsi2ssq(XMMRegister dst, Address src);
1099
1100 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1101 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1102
1103 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1104 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1105
1106 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1107 void cvtss2sd(XMMRegister dst, XMMRegister src);
1108 void cvtss2sd(XMMRegister dst, Address src);
1109
1110 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1111 void cvttsd2sil(Register dst, Address src);
1112 void cvttsd2sil(Register dst, XMMRegister src);
1113 void cvttsd2siq(Register dst, Address src);
1114 void cvttsd2siq(Register dst, XMMRegister src);
1115
1116 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1117 void cvttss2sil(Register dst, XMMRegister src);
1118 void cvttss2siq(Register dst, XMMRegister src);
1119
1120 void cvttpd2dq(XMMRegister dst, XMMRegister src);
1121
1122 //Abs of packed Integer values
1123 void pabsb(XMMRegister dst, XMMRegister src);
1124 void pabsw(XMMRegister dst, XMMRegister src);
1125 void pabsd(XMMRegister dst, XMMRegister src);
1126 void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1127 void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1128 void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1129 void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1130
1131 // Divide Scalar Double-Precision Floating-Point Values
1132 void divsd(XMMRegister dst, Address src);
1133 void divsd(XMMRegister dst, XMMRegister src);
1134
1135 // Divide Scalar Single-Precision Floating-Point Values
1136 void divss(XMMRegister dst, Address src);
1137 void divss(XMMRegister dst, XMMRegister src);
1138
1139 void emms();
1140
1141 #ifndef _LP64
1142 void fabs();
1143
1144 void fadd(int i);
1145
1146 void fadd_d(Address src);
1147 void fadd_s(Address src);
1148
1149 // "Alternate" versions of x87 instructions place result down in FPU
1150 // stack instead of on TOS
1151
1152 void fadda(int i); // "alternate" fadd
1153 void faddp(int i = 1);
1154
1155 void fchs();
1156
1157 void fcom(int i);
1158
1159 void fcomp(int i = 1);
1160 void fcomp_d(Address src);
1161 void fcomp_s(Address src);
1162
1163 void fcompp();
1164
1165 void fcos();
1166
1167 void fdecstp();
1168
1169 void fdiv(int i);
1170 void fdiv_d(Address src);
1171 void fdivr_s(Address src);
1172 void fdiva(int i); // "alternate" fdiv
1173 void fdivp(int i = 1);
1174
1175 void fdivr(int i);
1176 void fdivr_d(Address src);
1177 void fdiv_s(Address src);
1178
1179 void fdivra(int i); // "alternate" reversed fdiv
1180
1181 void fdivrp(int i = 1);
1182
1183 void ffree(int i = 0);
1184
1185 void fild_d(Address adr);
1186 void fild_s(Address adr);
1187
1188 void fincstp();
1189
1190 void finit();
1191
1192 void fist_s (Address adr);
1193 void fistp_d(Address adr);
1194 void fistp_s(Address adr);
1195
1196 void fld1();
1197
1198 void fld_d(Address adr);
1199 void fld_s(Address adr);
1200 void fld_s(int index);
1201 void fld_x(Address adr); // extended-precision (80-bit) format
1202
1203 void fldcw(Address src);
1204
1205 void fldenv(Address src);
1206
1207 void fldlg2();
1208
1209 void fldln2();
1210
1211 void fldz();
1212
1213 void flog();
1214 void flog10();
1215
1216 void fmul(int i);
1217
1218 void fmul_d(Address src);
1219 void fmul_s(Address src);
1220
1221 void fmula(int i); // "alternate" fmul
1222
1223 void fmulp(int i = 1);
1224
1225 void fnsave(Address dst);
1226
1227 void fnstcw(Address src);
1228
1229 void fnstsw_ax();
1230
1231 void fprem();
1232 void fprem1();
1233
1234 void frstor(Address src);
1235
1236 void fsin();
1237
1238 void fsqrt();
1239
1240 void fst_d(Address adr);
1241 void fst_s(Address adr);
1242
1243 void fstp_d(Address adr);
1244 void fstp_d(int index);
1245 void fstp_s(Address adr);
1246 void fstp_x(Address adr); // extended-precision (80-bit) format
1247
1248 void fsub(int i);
1249 void fsub_d(Address src);
1250 void fsub_s(Address src);
1251
1252 void fsuba(int i); // "alternate" fsub
1253
1254 void fsubp(int i = 1);
1255
1256 void fsubr(int i);
1257 void fsubr_d(Address src);
1258 void fsubr_s(Address src);
1259
1260 void fsubra(int i); // "alternate" reversed fsub
1261
1262 void fsubrp(int i = 1);
1263
1264 void ftan();
1265
1266 void ftst();
1267
1268 void fucomi(int i = 1);
1269 void fucomip(int i = 1);
1270
1271 void fwait();
1272
1273 void fxch(int i = 1);
1274
1275 void fyl2x();
1276 void frndint();
1277 void f2xm1();
1278 void fldl2e();
1279 #endif // !_LP64
1280
1281 void fxrstor(Address src);
1282 void xrstor(Address src);
1283
1284 void fxsave(Address dst);
1285 void xsave(Address dst);
1286
1287 void hlt();
1288
1289 void idivl(Register src);
1290 void divl(Register src); // Unsigned division
1291
1292 #ifdef _LP64
1293 void idivq(Register src);
1294 #endif
1295
1296 void imull(Register src);
1297 void imull(Register dst, Register src);
1298 void imull(Register dst, Register src, int value);
1299 void imull(Register dst, Address src);
1300
1301 #ifdef _LP64
1302 void imulq(Register dst, Register src);
1303 void imulq(Register dst, Register src, int value);
1304 void imulq(Register dst, Address src);
1305 #endif
1306
1307 // jcc is the generic conditional branch generator to run-
1308 // time routines, jcc is used for branches to labels. jcc
1309 // takes a branch opcode (cc) and a label (L) and generates
1310 // either a backward branch or a forward branch and links it
1311 // to the label fixup chain. Usage:
1312 //
1313 // Label L; // unbound label
1314 // jcc(cc, L); // forward branch to unbound label
1315 // bind(L); // bind label to the current pc
1316 // jcc(cc, L); // backward branch to bound label
1317 // bind(L); // illegal: a label may be bound only once
1318 //
1319 // Note: The same Label can be used for forward and backward branches
1320 // but it may be bound only once.
1321
1322 void jcc(Condition cc, Label& L, bool maybe_short = true);
1323
1324 // Conditional jump to a 8-bit offset to L.
1325 // WARNING: be very careful using this for forward jumps. If the label is
1326 // not bound within an 8-bit offset of this instruction, a run-time error
1327 // will occur.
1328
1329 // Use macro to record file and line number.
1330 #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1331
1332 void jccb_0(Condition cc, Label& L, const char* file, int line);
1333
1334 void jmp(Address entry); // pc <- entry
1335
1336 // Label operations & relative jumps (PPUM Appendix D)
1337 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1338
1339 void jmp(Register entry); // pc <- entry
1340
1341 // Unconditional 8-bit offset jump to L.
1342 // WARNING: be very careful using this for forward jumps. If the label is
1343 // not bound within an 8-bit offset of this instruction, a run-time error
1344 // will occur.
1345
1346 // Use macro to record file and line number.
1347 #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1348
1349 void jmpb_0(Label& L, const char* file, int line);
1350
1351 void ldmxcsr( Address src );
1352
1353 void leal(Register dst, Address src);
1354
1355 void leaq(Register dst, Address src);
1356
1357 void lfence();
1358
1359 void lock();
1360
1361 void lzcntl(Register dst, Register src);
1362
1363 #ifdef _LP64
1364 void lzcntq(Register dst, Register src);
1365 #endif
1366
1367 enum Membar_mask_bits {
1368 StoreStore = 1 << 3,
1369 LoadStore = 1 << 2,
1370 StoreLoad = 1 << 1,
1371 LoadLoad = 1 << 0
1372 };
1373
1374 // Serializes memory and blows flags
1375 void membar(Membar_mask_bits order_constraint) {
1376 // We only have to handle StoreLoad
1377 if (order_constraint & StoreLoad) {
1378 // All usable chips support "locked" instructions which suffice
1379 // as barriers, and are much faster than the alternative of
1380 // using cpuid instruction. We use here a locked add [esp-C],0.
1381 // This is conveniently otherwise a no-op except for blowing
1382 // flags, and introducing a false dependency on target memory
1383 // location. We can't do anything with flags, but we can avoid
1384 // memory dependencies in the current method by locked-adding
1385 // somewhere else on the stack. Doing [esp+C] will collide with
1386 // something on stack in current method, hence we go for [esp-C].
1387 // It is convenient since it is almost always in data cache, for
1388 // any small C. We need to step back from SP to avoid data
1389 // dependencies with other things on below SP (callee-saves, for
1390 // example). Without a clear way to figure out the minimal safe
1391 // distance from SP, it makes sense to step back the complete
1392 // cache line, as this will also avoid possible second-order effects
1393 // with locked ops against the cache line. Our choice of offset
1394 // is bounded by x86 operand encoding, which should stay within
1395 // [-128; +127] to have the 8-byte displacement encoding.
1396 //
1397 // Any change to this code may need to revisit other places in
1398 // the code where this idiom is used, in particular the
1399 // orderAccess code.
1400
1401 int offset = -VM_Version::L1_line_size();
1402 if (offset < -128) {
1403 offset = -128;
1404 }
1405
1406 lock();
1407 addl(Address(rsp, offset), 0);// Assert the lock# signal here
1408 }
1409 }
1410
1411 void mfence();
1412 void sfence();
1413
1414 // Moves
1415
1416 void mov64(Register dst, int64_t imm64);
1417
1418 void movb(Address dst, Register src);
1419 void movb(Address dst, int imm8);
1420 void movb(Register dst, Address src);
1421
1422 void movddup(XMMRegister dst, XMMRegister src);
1423
1424 void kmovbl(KRegister dst, Register src);
1425 void kmovbl(Register dst, KRegister src);
1426 void kmovwl(KRegister dst, Register src);
1427 void kmovwl(KRegister dst, Address src);
1428 void kmovwl(Register dst, KRegister src);
1429 void kmovdl(KRegister dst, Register src);
1430 void kmovdl(Register dst, KRegister src);
1431 void kmovql(KRegister dst, KRegister src);
1432 void kmovql(Address dst, KRegister src);
1433 void kmovql(KRegister dst, Address src);
1434 void kmovql(KRegister dst, Register src);
1435 void kmovql(Register dst, KRegister src);
1436
1437 void knotwl(KRegister dst, KRegister src);
1438
1439 void kortestbl(KRegister dst, KRegister src);
1440 void kortestwl(KRegister dst, KRegister src);
1441 void kortestdl(KRegister dst, KRegister src);
1442 void kortestql(KRegister dst, KRegister src);
1443
1444 void ktestq(KRegister src1, KRegister src2);
1445 void ktestd(KRegister src1, KRegister src2);
1446
1447 void ktestql(KRegister dst, KRegister src);
1448
1449 void movdl(XMMRegister dst, Register src);
1450 void movdl(Register dst, XMMRegister src);
1451 void movdl(XMMRegister dst, Address src);
1452 void movdl(Address dst, XMMRegister src);
1453
1454 // Move Double Quadword
1455 void movdq(XMMRegister dst, Register src);
1456 void movdq(Register dst, XMMRegister src);
1457
1458 // Move Aligned Double Quadword
1459 void movdqa(XMMRegister dst, XMMRegister src);
1460 void movdqa(XMMRegister dst, Address src);
1461
1462 // Move Unaligned Double Quadword
1463 void movdqu(Address dst, XMMRegister src);
1464 void movdqu(XMMRegister dst, Address src);
1465 void movdqu(XMMRegister dst, XMMRegister src);
1466
1467 // Move Unaligned 256bit Vector
1468 void vmovdqu(Address dst, XMMRegister src);
1469 void vmovdqu(XMMRegister dst, Address src);
1470 void vmovdqu(XMMRegister dst, XMMRegister src);
1471
1472 // Move Unaligned 512bit Vector
1473 void evmovdqub(Address dst, XMMRegister src, int vector_len);
1474 void evmovdqub(XMMRegister dst, Address src, int vector_len);
1475 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1476 void evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len);
1477 void evmovdquw(Address dst, XMMRegister src, int vector_len);
1478 void evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len);
1479 void evmovdquw(XMMRegister dst, Address src, int vector_len);
1480 void evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1481 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1482 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1483 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1484 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1485 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1486 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1487
1488 // Move lower 64bit to high 64bit in 128bit register
1489 void movlhps(XMMRegister dst, XMMRegister src);
1490
1491 void movl(Register dst, int32_t imm32);
1492 void movl(Address dst, int32_t imm32);
1493 void movl(Register dst, Register src);
1494 void movl(Register dst, Address src);
1495 void movl(Address dst, Register src);
1496
1497 // These dummies prevent using movl from converting a zero (like NULL) into Register
1498 // by giving the compiler two choices it can't resolve
1499
1500 void movl(Address dst, void* junk);
1501 void movl(Register dst, void* junk);
1502
1503 #ifdef _LP64
1504 void movq(Register dst, Register src);
1505 void movq(Register dst, Address src);
1506 void movq(Address dst, Register src);
1507 #endif
1508
1509 void movq(Address dst, MMXRegister src );
1510 void movq(MMXRegister dst, Address src );
1511
1512 #ifdef _LP64
1513 // These dummies prevent using movq from converting a zero (like NULL) into Register
1514 // by giving the compiler two choices it can't resolve
1515
1516 void movq(Address dst, void* dummy);
1517 void movq(Register dst, void* dummy);
1518 #endif
1519
1520 // Move Quadword
1521 void movq(Address dst, XMMRegister src);
1522 void movq(XMMRegister dst, Address src);
1523
1524 void movsbl(Register dst, Address src);
1525 void movsbl(Register dst, Register src);
1526
1527 #ifdef _LP64
1528 void movsbq(Register dst, Address src);
1529 void movsbq(Register dst, Register src);
1530
1531 // Move signed 32bit immediate to 64bit extending sign
1532 void movslq(Address dst, int32_t imm64);
1533 void movslq(Register dst, int32_t imm64);
1534
1535 void movslq(Register dst, Address src);
1536 void movslq(Register dst, Register src);
1537 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1538 #endif
1539
1540 void movswl(Register dst, Address src);
1541 void movswl(Register dst, Register src);
1542
1543 #ifdef _LP64
1544 void movswq(Register dst, Address src);
1545 void movswq(Register dst, Register src);
1546 #endif
1547
1548 void movw(Address dst, int imm16);
1549 void movw(Register dst, Address src);
1550 void movw(Address dst, Register src);
1551
1552 void movzbl(Register dst, Address src);
1553 void movzbl(Register dst, Register src);
1554
1555 #ifdef _LP64
1556 void movzbq(Register dst, Address src);
1557 void movzbq(Register dst, Register src);
1558 #endif
1559
1560 void movzwl(Register dst, Address src);
1561 void movzwl(Register dst, Register src);
1562
1563 #ifdef _LP64
1564 void movzwq(Register dst, Address src);
1565 void movzwq(Register dst, Register src);
1566 #endif
1567
1568 // Unsigned multiply with RAX destination register
1569 void mull(Address src);
1570 void mull(Register src);
1571
1572 #ifdef _LP64
1573 void mulq(Address src);
1574 void mulq(Register src);
1575 void mulxq(Register dst1, Register dst2, Register src);
1576 #endif
1577
1578 // Multiply Scalar Double-Precision Floating-Point Values
1579 void mulsd(XMMRegister dst, Address src);
1580 void mulsd(XMMRegister dst, XMMRegister src);
1581
1582 // Multiply Scalar Single-Precision Floating-Point Values
1583 void mulss(XMMRegister dst, Address src);
1584 void mulss(XMMRegister dst, XMMRegister src);
1585
1586 void negl(Register dst);
1587
1588 #ifdef _LP64
1589 void negq(Register dst);
1590 #endif
1591
1592 void nop(int i = 1);
1593
1594 void notl(Register dst);
1595
1596 #ifdef _LP64
1597 void notq(Register dst);
1598
1599 void btsq(Address dst, int imm8);
1600 void btrq(Address dst, int imm8);
1601 #endif
1602
1603 void orl(Address dst, int32_t imm32);
1604 void orl(Register dst, int32_t imm32);
1605 void orl(Register dst, Address src);
1606 void orl(Register dst, Register src);
1607 void orl(Address dst, Register src);
1608
1609 void orb(Address dst, int imm8);
1610
1611 void orq(Address dst, int32_t imm32);
1612 void orq(Register dst, int32_t imm32);
1613 void orq(Register dst, Address src);
1614 void orq(Register dst, Register src);
1615
1616 // Pack with unsigned saturation
1617 void packuswb(XMMRegister dst, XMMRegister src);
1618 void packuswb(XMMRegister dst, Address src);
1619 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1620
1621 // Pemutation of 64bit words
1622 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1623 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1624 void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1625 void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1626 void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1627 void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1628
1629 void pause();
1630
1631 // Undefined Instruction
1632 void ud2();
1633
1634 // SSE4.2 string instructions
1635 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1636 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1637
1638 void pcmpeqb(XMMRegister dst, XMMRegister src);
1639 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1640 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1641 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1642 void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1643
1644 void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1645 void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1646
1647 void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1648 void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len);
1649 void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1650
1651 void pcmpeqw(XMMRegister dst, XMMRegister src);
1652 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1653 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1654 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1655
1656 void pcmpeqd(XMMRegister dst, XMMRegister src);
1657 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1658 void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1659 void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1660
1661 void pcmpeqq(XMMRegister dst, XMMRegister src);
1662 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1663 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1664 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1665
1666 void pmovmskb(Register dst, XMMRegister src);
1667 void vpmovmskb(Register dst, XMMRegister src);
1668
1669 // SSE 4.1 extract
1670 void pextrd(Register dst, XMMRegister src, int imm8);
1671 void pextrq(Register dst, XMMRegister src, int imm8);
1672 void pextrd(Address dst, XMMRegister src, int imm8);
1673 void pextrq(Address dst, XMMRegister src, int imm8);
1674 void pextrb(Address dst, XMMRegister src, int imm8);
1675 // SSE 2 extract
1676 void pextrw(Register dst, XMMRegister src, int imm8);
1677 void pextrw(Address dst, XMMRegister src, int imm8);
1678
1679 // SSE 4.1 insert
1680 void pinsrd(XMMRegister dst, Register src, int imm8);
1681 void pinsrq(XMMRegister dst, Register src, int imm8);
1682 void pinsrd(XMMRegister dst, Address src, int imm8);
1683 void pinsrq(XMMRegister dst, Address src, int imm8);
1684 void pinsrb(XMMRegister dst, Address src, int imm8);
1685 // SSE 2 insert
1686 void pinsrw(XMMRegister dst, Register src, int imm8);
1687 void pinsrw(XMMRegister dst, Address src, int imm8);
1688
1689 // SSE4.1 packed move
1690 void pmovzxbw(XMMRegister dst, XMMRegister src);
1691 void pmovzxbw(XMMRegister dst, Address src);
1692
1693 void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1694 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1695 void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1696
1697 void evpmovwb(Address dst, XMMRegister src, int vector_len);
1698 void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1699
1700 void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1701
1702 void evpmovdb(Address dst, XMMRegister src, int vector_len);
1703
1704 // Sign extend moves
1705 void pmovsxbw(XMMRegister dst, XMMRegister src);
1706 void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1707
1708 // Multiply add
1709 void pmaddwd(XMMRegister dst, XMMRegister src);
1710 void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1711 // Multiply add accumulate
1712 void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1713
1714 #ifndef _LP64 // no 32bit push/pop on amd64
1715 void popl(Address dst);
1716 #endif
1717
1718 #ifdef _LP64
1719 void popq(Address dst);
1720 #endif
1721
1722 void popcntl(Register dst, Address src);
1723 void popcntl(Register dst, Register src);
1724
1725 void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1726
1727 #ifdef _LP64
1728 void popcntq(Register dst, Address src);
1729 void popcntq(Register dst, Register src);
1730 #endif
1731
1732 // Prefetches (SSE, SSE2, 3DNOW only)
1733
1734 void prefetchnta(Address src);
1735 void prefetchr(Address src);
1736 void prefetcht0(Address src);
1737 void prefetcht1(Address src);
1738 void prefetcht2(Address src);
1739 void prefetchw(Address src);
1740
1741 // Shuffle Bytes
1742 void pshufb(XMMRegister dst, XMMRegister src);
1743 void pshufb(XMMRegister dst, Address src);
1744 void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1745
1746 // Shuffle Packed Doublewords
1747 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1748 void pshufd(XMMRegister dst, Address src, int mode);
1749 void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1750
1751 // Shuffle Packed Low Words
1752 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1753 void pshuflw(XMMRegister dst, Address src, int mode);
1754
1755 // Shuffle packed values at 128 bit granularity
1756 void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1757
1758 // Shift Right by bytes Logical DoubleQuadword Immediate
1759 void psrldq(XMMRegister dst, int shift);
1760 // Shift Left by bytes Logical DoubleQuadword Immediate
1761 void pslldq(XMMRegister dst, int shift);
1762
1763 // Logical Compare 128bit
1764 void ptest(XMMRegister dst, XMMRegister src);
1765 void ptest(XMMRegister dst, Address src);
1766 // Logical Compare 256bit
1767 void vptest(XMMRegister dst, XMMRegister src);
1768 void vptest(XMMRegister dst, Address src);
1769
1770 // Interleave Low Bytes
1771 void punpcklbw(XMMRegister dst, XMMRegister src);
1772 void punpcklbw(XMMRegister dst, Address src);
1773
1774 // Interleave Low Doublewords
1775 void punpckldq(XMMRegister dst, XMMRegister src);
1776 void punpckldq(XMMRegister dst, Address src);
1777
1778 // Interleave Low Quadwords
1779 void punpcklqdq(XMMRegister dst, XMMRegister src);
1780
1781 #ifndef _LP64 // no 32bit push/pop on amd64
1782 void pushl(Address src);
1783 #endif
1784
1785 void pushq(Address src);
1786
1787 void rcll(Register dst, int imm8);
1788
1789 void rclq(Register dst, int imm8);
1790
1791 void rcrq(Register dst, int imm8);
1792
1793 void rcpps(XMMRegister dst, XMMRegister src);
1794
1795 void rcpss(XMMRegister dst, XMMRegister src);
1796
1797 void rdtsc();
1798
1799 void ret(int imm16);
1800
1801 #ifdef _LP64
1802 void rorq(Register dst, int imm8);
1803 void rorxq(Register dst, Register src, int imm8);
1804 void rorxd(Register dst, Register src, int imm8);
1805 #endif
1806
1807 void sahf();
1808
1809 void sarl(Register dst, int imm8);
1810 void sarl(Register dst);
1811
1812 void sarq(Register dst, int imm8);
1813 void sarq(Register dst);
1814
1815 void sbbl(Address dst, int32_t imm32);
1816 void sbbl(Register dst, int32_t imm32);
1817 void sbbl(Register dst, Address src);
1818 void sbbl(Register dst, Register src);
1819
1820 void sbbq(Address dst, int32_t imm32);
1821 void sbbq(Register dst, int32_t imm32);
1822 void sbbq(Register dst, Address src);
1823 void sbbq(Register dst, Register src);
1824
1825 void setb(Condition cc, Register dst);
1826
1827 void palignr(XMMRegister dst, XMMRegister src, int imm8);
1828 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
1829 void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1830
1831 void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1832
1833 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1834 void sha1nexte(XMMRegister dst, XMMRegister src);
1835 void sha1msg1(XMMRegister dst, XMMRegister src);
1836 void sha1msg2(XMMRegister dst, XMMRegister src);
1837 // xmm0 is implicit additional source to the following instruction.
1838 void sha256rnds2(XMMRegister dst, XMMRegister src);
1839 void sha256msg1(XMMRegister dst, XMMRegister src);
1840 void sha256msg2(XMMRegister dst, XMMRegister src);
1841
1842 void shldl(Register dst, Register src);
1843 void shldl(Register dst, Register src, int8_t imm8);
1844
1845 void shll(Register dst, int imm8);
1846 void shll(Register dst);
1847
1848 void shlq(Register dst, int imm8);
1849 void shlq(Register dst);
1850
1851 void shrdl(Register dst, Register src);
1852
1853 void shrl(Register dst, int imm8);
1854 void shrl(Register dst);
1855
1856 void shrq(Register dst, int imm8);
1857 void shrq(Register dst);
1858
1859 void smovl(); // QQQ generic?
1860
1861 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1862 void sqrtsd(XMMRegister dst, Address src);
1863 void sqrtsd(XMMRegister dst, XMMRegister src);
1864
1865 void roundsd(XMMRegister dst, Address src, int32_t rmode);
1866 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
1867
1868 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1869 void sqrtss(XMMRegister dst, Address src);
1870 void sqrtss(XMMRegister dst, XMMRegister src);
1871
1872 void std();
1873
1874 void stmxcsr( Address dst );
1875
1876 void subl(Address dst, int32_t imm32);
1877 void subl(Address dst, Register src);
1878 void subl(Register dst, int32_t imm32);
1879 void subl(Register dst, Address src);
1880 void subl(Register dst, Register src);
1881
1882 void subq(Address dst, int32_t imm32);
1883 void subq(Address dst, Register src);
1884 void subq(Register dst, int32_t imm32);
1885 void subq(Register dst, Address src);
1886 void subq(Register dst, Register src);
1887
1888 // Force generation of a 4 byte immediate value even if it fits into 8bit
1889 void subl_imm32(Register dst, int32_t imm32);
1890 void subq_imm32(Register dst, int32_t imm32);
1891
1892 // Subtract Scalar Double-Precision Floating-Point Values
1893 void subsd(XMMRegister dst, Address src);
1894 void subsd(XMMRegister dst, XMMRegister src);
1895
1896 // Subtract Scalar Single-Precision Floating-Point Values
1897 void subss(XMMRegister dst, Address src);
1898 void subss(XMMRegister dst, XMMRegister src);
1899
1900 void testb(Register dst, int imm8);
1901 void testb(Address dst, int imm8);
1902
1903 void testl(Register dst, int32_t imm32);
1904 void testl(Register dst, Register src);
1905 void testl(Register dst, Address src);
1906
1907 void testq(Register dst, int32_t imm32);
1908 void testq(Register dst, Register src);
1909 void testq(Register dst, Address src);
1910
1911 // BMI - count trailing zeros
1912 void tzcntl(Register dst, Register src);
1913 void tzcntq(Register dst, Register src);
1914
1915 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1916 void ucomisd(XMMRegister dst, Address src);
1917 void ucomisd(XMMRegister dst, XMMRegister src);
1918
1919 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1920 void ucomiss(XMMRegister dst, Address src);
1921 void ucomiss(XMMRegister dst, XMMRegister src);
1922
1923 void xabort(int8_t imm8);
1924
1925 void xaddb(Address dst, Register src);
1926 void xaddw(Address dst, Register src);
1927 void xaddl(Address dst, Register src);
1928 void xaddq(Address dst, Register src);
1929
1930 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1931
1932 void xchgb(Register reg, Address adr);
1933 void xchgw(Register reg, Address adr);
1934 void xchgl(Register reg, Address adr);
1935 void xchgl(Register dst, Register src);
1936
1937 void xchgq(Register reg, Address adr);
1938 void xchgq(Register dst, Register src);
1939
1940 void xend();
1941
1942 // Get Value of Extended Control Register
1943 void xgetbv();
1944
1945 void xorl(Register dst, int32_t imm32);
1946 void xorl(Register dst, Address src);
1947 void xorl(Register dst, Register src);
1948
1949 void xorb(Register dst, Address src);
1950
1951 void xorq(Register dst, Address src);
1952 void xorq(Register dst, Register src);
1953
1954 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1955
1956 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1957
1958 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1959 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1960 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1961 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1962 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1963 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1964 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1965 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1966 void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1967 void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1968 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1969 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1970 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1971 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1972 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1973 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1974 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1975 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1976
1977 void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1978 void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1979 void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1980 void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1981
1982 void shlxl(Register dst, Register src1, Register src2);
1983 void shlxq(Register dst, Register src1, Register src2);
1984
1985 //====================VECTOR ARITHMETIC=====================================
1986
1987 // Add Packed Floating-Point Values
1988 void addpd(XMMRegister dst, XMMRegister src);
1989 void addpd(XMMRegister dst, Address src);
1990 void addps(XMMRegister dst, XMMRegister src);
1991 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1992 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1993 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1994 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1995
1996 // Subtract Packed Floating-Point Values
1997 void subpd(XMMRegister dst, XMMRegister src);
1998 void subps(XMMRegister dst, XMMRegister src);
1999 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2000 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2001 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2002 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2003
2004 // Multiply Packed Floating-Point Values
2005 void mulpd(XMMRegister dst, XMMRegister src);
2006 void mulpd(XMMRegister dst, Address src);
2007 void mulps(XMMRegister dst, XMMRegister src);
2008 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2009 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2010 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2011 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2012
2013 void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2014 void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2015 void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2016 void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2017
2018 // Divide Packed Floating-Point Values
2019 void divpd(XMMRegister dst, XMMRegister src);
2020 void divps(XMMRegister dst, XMMRegister src);
2021 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2022 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2023 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2024 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2025
2026 // Sqrt Packed Floating-Point Values
2027 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2028 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2029 void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2030 void vsqrtps(XMMRegister dst, Address src, int vector_len);
2031
2032 // Round Packed Double precision value.
2033 void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2034 void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2035 void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2036 void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2037
2038 // Bitwise Logical AND of Packed Floating-Point Values
2039 void andpd(XMMRegister dst, XMMRegister src);
2040 void andps(XMMRegister dst, XMMRegister src);
2041 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2042 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2043 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2044 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2045
2046 void unpckhpd(XMMRegister dst, XMMRegister src);
2047 void unpcklpd(XMMRegister dst, XMMRegister src);
2048
2049 // Bitwise Logical XOR of Packed Floating-Point Values
2050 void xorpd(XMMRegister dst, XMMRegister src);
2051 void xorps(XMMRegister dst, XMMRegister src);
2052 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2053 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2054 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2055 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2056
2057 // Add horizontal packed integers
2058 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2059 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2060 void phaddw(XMMRegister dst, XMMRegister src);
2061 void phaddd(XMMRegister dst, XMMRegister src);
2062
2063 // Add packed integers
2064 void paddb(XMMRegister dst, XMMRegister src);
2065 void paddw(XMMRegister dst, XMMRegister src);
2066 void paddd(XMMRegister dst, XMMRegister src);
2067 void paddd(XMMRegister dst, Address src);
2068 void paddq(XMMRegister dst, XMMRegister src);
2069 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2070 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2071 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2072 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2073 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2074 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2075 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2076 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2077
2078 // Sub packed integers
2079 void psubb(XMMRegister dst, XMMRegister src);
2080 void psubw(XMMRegister dst, XMMRegister src);
2081 void psubd(XMMRegister dst, XMMRegister src);
2082 void psubq(XMMRegister dst, XMMRegister src);
2083 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2084 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2085 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2086 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2087 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2088 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2089 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2090 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2091
2092 // Multiply packed integers (only shorts and ints)
2093 void pmullw(XMMRegister dst, XMMRegister src);
2094 void pmulld(XMMRegister dst, XMMRegister src);
2095 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2096 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2097 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2098 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2099 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2100 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2101
2102 // Shift left packed integers
2103 void psllw(XMMRegister dst, int shift);
2104 void pslld(XMMRegister dst, int shift);
2105 void psllq(XMMRegister dst, int shift);
2106 void psllw(XMMRegister dst, XMMRegister shift);
2107 void pslld(XMMRegister dst, XMMRegister shift);
2108 void psllq(XMMRegister dst, XMMRegister shift);
2109 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2110 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2111 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2112 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2113 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2114 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2115 void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2116
2117 // Logical shift right packed integers
2118 void psrlw(XMMRegister dst, int shift);
2119 void psrld(XMMRegister dst, int shift);
2120 void psrlq(XMMRegister dst, int shift);
2121 void psrlw(XMMRegister dst, XMMRegister shift);
2122 void psrld(XMMRegister dst, XMMRegister shift);
2123 void psrlq(XMMRegister dst, XMMRegister shift);
2124 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2125 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2126 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2127 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2128 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2129 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2130 void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2131 void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2132 void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2133
2134 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2135 void psraw(XMMRegister dst, int shift);
2136 void psrad(XMMRegister dst, int shift);
2137 void psraw(XMMRegister dst, XMMRegister shift);
2138 void psrad(XMMRegister dst, XMMRegister shift);
2139 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2140 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2141 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2142 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2143 void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2144 void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2145
2146 // And packed integers
2147 void pand(XMMRegister dst, XMMRegister src);
2148 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2149 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2150 void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2151
2152 // Andn packed integers
2153 void pandn(XMMRegister dst, XMMRegister src);
2154 void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2155
2156 // Or packed integers
2157 void por(XMMRegister dst, XMMRegister src);
2158 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2159 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2160 void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2161
2162 // Xor packed integers
2163 void pxor(XMMRegister dst, XMMRegister src);
2164 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2165 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2166 void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2167 void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2168
2169
2170 // vinserti forms
2171 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2172 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2173 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2174 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2175 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2176
2177 // vinsertf forms
2178 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2179 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2180 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2181 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2182 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2183 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2184
2185 // vextracti forms
2186 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2187 void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2188 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2189 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2190 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2191 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2192 void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2193
2194 // vextractf forms
2195 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2196 void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2197 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2198 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2199 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2200 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2201 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2202
2203 // xmm/mem sourced byte/word/dword/qword replicate
2204 void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2205 void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2206 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2207 void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2208 void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2209 void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2210 void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2211 void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2212
2213 void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2214 void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2215
2216 // scalar single/double precision replicate
2217 void vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2218 void vpbroadcastss(XMMRegister dst, Address src, int vector_len);
2219 void vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2220 void vpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2221
2222 // gpr sourced byte/word/dword/qword replicate
2223 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2224 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2225 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2226 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2227
2228 void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len);
2229
2230 // Carry-Less Multiplication Quadword
2231 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2232 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2233 void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2234 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2235 // to avoid transaction penalty between AVX and SSE states. There is no
2236 // penalty if legacy SSE instructions are encoded using VEX prefix because
2237 // they always clear upper 128 bits. It should be used before calling
2238 // runtime code and native libraries.
2239 void vzeroupper();
2240
2241 // AVX support for vectorized conditional move (float/double). The following two instructions used only coupled.
2242 void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2243 void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2244 void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2245 void blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2246 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2247
2248 protected:
2249 // Next instructions require address alignment 16 bytes SSE mode.
2250 // They should be called only from corresponding MacroAssembler instructions.
2251 void andpd(XMMRegister dst, Address src);
2252 void andps(XMMRegister dst, Address src);
2253 void xorpd(XMMRegister dst, Address src);
2254 void xorps(XMMRegister dst, Address src);
2255
2256 };
2257
2258 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2259 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2260 // are applied.
2261 class InstructionAttr {
2262 public:
2263 InstructionAttr(
2264 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
2265 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2266 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2267 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2268 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
2269 :
2270 _avx_vector_len(vector_len),
2271 _rex_vex_w(rex_vex_w),
2272 _rex_vex_w_reverted(false),
2273 _legacy_mode(legacy_mode),
2274 _no_reg_mask(no_reg_mask),
2275 _uses_vl(uses_vl),
2276 _tuple_type(Assembler::EVEX_ETUP),
2277 _input_size_in_bits(Assembler::EVEX_NObit),
2278 _is_evex_instruction(false),
2279 _evex_encoding(0),
2280 _is_clear_context(true),
2281 _is_extended_context(false),
2282 _embedded_opmask_register_specifier(0), // hard code k0
2283 _current_assembler(NULL) {
2284 if (UseAVX < 3) _legacy_mode = true;
2285 }
2286
2287 ~InstructionAttr() {
2288 if (_current_assembler != NULL) {
2289 _current_assembler->clear_attributes();
2290 }
2291 _current_assembler = NULL;
2292 }
2293
2294 private:
2295 int _avx_vector_len;
2296 bool _rex_vex_w;
2297 bool _rex_vex_w_reverted;
2298 bool _legacy_mode;
2299 bool _no_reg_mask;
2300 bool _uses_vl;
2301 int _tuple_type;
2302 int _input_size_in_bits;
2303 bool _is_evex_instruction;
2304 int _evex_encoding;
2305 bool _is_clear_context;
2306 bool _is_extended_context;
2307 int _embedded_opmask_register_specifier;
2308
2309 Assembler *_current_assembler;
2310
2311 public:
2312 // query functions for field accessors
2313 int get_vector_len(void) const { return _avx_vector_len; }
2314 bool is_rex_vex_w(void) const { return _rex_vex_w; }
2315 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2316 bool is_legacy_mode(void) const { return _legacy_mode; }
2317 bool is_no_reg_mask(void) const { return _no_reg_mask; }
2318 bool uses_vl(void) const { return _uses_vl; }
2319 int get_tuple_type(void) const { return _tuple_type; }
2320 int get_input_size(void) const { return _input_size_in_bits; }
2321 int is_evex_instruction(void) const { return _is_evex_instruction; }
2322 int get_evex_encoding(void) const { return _evex_encoding; }
2323 bool is_clear_context(void) const { return _is_clear_context; }
2324 bool is_extended_context(void) const { return _is_extended_context; }
2325 int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2326
2327 // Set the vector len manually
2328 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2329
2330 // Set revert rex_vex_w for avx encoding
2331 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2332
2333 // Set rex_vex_w based on state
2334 void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2335
2336 // Set the instruction to be encoded in AVX mode
2337 void set_is_legacy_mode(void) { _legacy_mode = true; }
2338
2339 // Set the current instuction to be encoded as an EVEX instuction
2340 void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2341
2342 // Internal encoding data used in compressed immediate offset programming
2343 void set_evex_encoding(int value) { _evex_encoding = value; }
2344
2345 // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2346 void reset_is_clear_context(void) { _is_clear_context = false; }
2347
2348 // Map back to current asembler so that we can manage object level assocation
2349 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2350
2351 // Address modifiers used for compressed displacement calculation
2352 void set_address_attributes(int tuple_type, int input_size_in_bits) {
2353 if (VM_Version::supports_evex()) {
2354 _tuple_type = tuple_type;
2355 _input_size_in_bits = input_size_in_bits;
2356 }
2357 }
2358
2359 // Set embedded opmask register specifier.
2360 void set_embedded_opmask_register_specifier(KRegister mask) {
2361 _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2362 }
2363
2364 };
2365
2366 #endif // CPU_X86_ASSEMBLER_X86_HPP