1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "vmreg_x86.inline.hpp"
44
45
46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
47 // instructions, to allow sign-masking or sign-bit flipping. They allow
48 // fast versions of NegF/NegD and AbsF/AbsD.
49
50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
53 // of 128-bits operands for SSE instructions.
54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
55 // Store the value to a 128-bits operand.
56 operand[0] = lo;
57 operand[1] = hi;
58 return operand;
59 }
60
61 // Buffer for 128-bits masks used by SSE instructions.
62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
63
64 // Static initialization during VM startup.
65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
69
70
71 NEEDS_CLEANUP // remove this definitions ?
72 const Register IC_Klass = rax; // where the IC klass is cached
73 const Register SYNC_header = rax; // synchronization header
74 const Register SHIFT_count = rcx; // where count for shift operations must be
75
76 #define __ _masm->
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp2 = extra;
89 }
90 assert_different_registers(preserve, tmp1, tmp2);
91 }
92
93
94
95 static void select_different_registers(Register preserve,
96 Register extra,
97 Register &tmp1,
98 Register &tmp2,
99 Register &tmp3) {
100 if (tmp1 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp1 = extra;
103 } else if (tmp2 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp2 = extra;
106 } else if (tmp3 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp3 = extra;
109 }
110 assert_different_registers(preserve, tmp1, tmp2, tmp3);
111 }
112
113
114
115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
116 if (opr->is_constant()) {
117 LIR_Const* constant = opr->as_constant_ptr();
118 switch (constant->type()) {
119 case T_INT: {
120 return true;
121 }
122
123 default:
124 return false;
125 }
126 }
127 return false;
128 }
129
130
131 LIR_Opr LIR_Assembler::receiverOpr() {
132 return FrameMap::receiver_opr;
133 }
134
135 LIR_Opr LIR_Assembler::osrBufferPointer() {
136 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
137 }
138
139 //--------------fpu register translations-----------------------
140
141
142 address LIR_Assembler::float_constant(float f) {
143 address const_addr = __ float_constant(f);
144 if (const_addr == NULL) {
145 bailout("const section overflow");
146 return __ code()->consts()->start();
147 } else {
148 return const_addr;
149 }
150 }
151
152
153 address LIR_Assembler::double_constant(double d) {
154 address const_addr = __ double_constant(d);
155 if (const_addr == NULL) {
156 bailout("const section overflow");
157 return __ code()->consts()->start();
158 } else {
159 return const_addr;
160 }
161 }
162
163 #ifndef _LP64
164 void LIR_Assembler::fpop() {
165 __ fpop();
166 }
167
168 void LIR_Assembler::fxch(int i) {
169 __ fxch(i);
170 }
171
172 void LIR_Assembler::fld(int i) {
173 __ fld_s(i);
174 }
175
176 void LIR_Assembler::ffree(int i) {
177 __ ffree(i);
178 }
179 #endif // !_LP64
180
181 void LIR_Assembler::breakpoint() {
182 __ int3();
183 }
184
185 void LIR_Assembler::push(LIR_Opr opr) {
186 if (opr->is_single_cpu()) {
187 __ push_reg(opr->as_register());
188 } else if (opr->is_double_cpu()) {
189 NOT_LP64(__ push_reg(opr->as_register_hi()));
190 __ push_reg(opr->as_register_lo());
191 } else if (opr->is_stack()) {
192 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
193 } else if (opr->is_constant()) {
194 LIR_Const* const_opr = opr->as_constant_ptr();
195 if (const_opr->type() == T_OBJECT) {
196 __ push_oop(const_opr->as_jobject());
197 } else if (const_opr->type() == T_INT) {
198 __ push_jint(const_opr->as_jint());
199 } else {
200 ShouldNotReachHere();
201 }
202
203 } else {
204 ShouldNotReachHere();
205 }
206 }
207
208 void LIR_Assembler::pop(LIR_Opr opr) {
209 if (opr->is_single_cpu()) {
210 __ pop_reg(opr->as_register());
211 } else {
212 ShouldNotReachHere();
213 }
214 }
215
216 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
217 return addr->base()->is_illegal() && addr->index()->is_illegal();
218 }
219
220 //-------------------------------------------
221
222 Address LIR_Assembler::as_Address(LIR_Address* addr) {
223 return as_Address(addr, rscratch1);
224 }
225
226 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
227 if (addr->base()->is_illegal()) {
228 assert(addr->index()->is_illegal(), "must be illegal too");
229 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
230 if (! __ reachable(laddr)) {
231 __ movptr(tmp, laddr.addr());
232 Address res(tmp, 0);
233 return res;
234 } else {
235 return __ as_Address(laddr);
236 }
237 }
238
239 Register base = addr->base()->as_pointer_register();
240
241 if (addr->index()->is_illegal()) {
242 return Address( base, addr->disp());
243 } else if (addr->index()->is_cpu_register()) {
244 Register index = addr->index()->as_pointer_register();
245 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
246 } else if (addr->index()->is_constant()) {
247 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
248 assert(Assembler::is_simm32(addr_offset), "must be");
249
250 return Address(base, addr_offset);
251 } else {
252 Unimplemented();
253 return Address();
254 }
255 }
256
257
258 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
259 Address base = as_Address(addr);
260 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
261 }
262
263
264 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
265 return as_Address(addr);
266 }
267
268
269 void LIR_Assembler::osr_entry() {
270 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
271 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
272 ValueStack* entry_state = osr_entry->state();
273 int number_of_locks = entry_state->locks_size();
274
275 // we jump here if osr happens with the interpreter
276 // state set up to continue at the beginning of the
277 // loop that triggered osr - in particular, we have
278 // the following registers setup:
279 //
280 // rcx: osr buffer
281 //
282
283 // build frame
284 ciMethod* m = compilation()->method();
285 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
286
287 // OSR buffer is
288 //
289 // locals[nlocals-1..0]
290 // monitors[0..number_of_locks]
291 //
292 // locals is a direct copy of the interpreter frame so in the osr buffer
293 // so first slot in the local array is the last local from the interpreter
294 // and last slot is local[0] (receiver) from the interpreter
295 //
296 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
297 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
298 // in the interpreter frame (the method lock if a sync method)
299
300 // Initialize monitors in the compiled activation.
301 // rcx: pointer to osr buffer
302 //
303 // All other registers are dead at this point and the locals will be
304 // copied into place by code emitted in the IR.
305
306 Register OSR_buf = osrBufferPointer()->as_pointer_register();
307 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
308 int monitor_offset = BytesPerWord * method()->max_locals() +
309 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
310 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
311 // the OSR buffer using 2 word entries: first the lock and then
312 // the oop.
313 for (int i = 0; i < number_of_locks; i++) {
314 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
315 #ifdef ASSERT
316 // verify the interpreter's monitor has a non-null object
317 {
318 Label L;
319 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
320 __ jcc(Assembler::notZero, L);
321 __ stop("locked object is NULL");
322 __ bind(L);
323 }
324 #endif
325 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
326 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
327 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
328 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
329 }
330 }
331 }
332
333
334 // inline cache check; done before the frame is built.
335 int LIR_Assembler::check_icache() {
336 Register receiver = FrameMap::receiver_opr->as_register();
337 Register ic_klass = IC_Klass;
338 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
339 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
340 if (!do_post_padding) {
341 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
342 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
343 }
344 int offset = __ offset();
345 __ inline_cache_check(receiver, IC_Klass);
346 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
347 if (do_post_padding) {
348 // force alignment after the cache check.
349 // It's been verified to be aligned if !VerifyOops
350 __ align(CodeEntryAlignment);
351 }
352 return offset;
353 }
354
355 void LIR_Assembler::clinit_barrier(ciMethod* method) {
356 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
357 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
358
359 Label L_skip_barrier;
360 Register klass = rscratch1;
361 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
362 assert(thread != noreg, "x86_32 not implemented");
363
364 __ mov_metadata(klass, method->holder()->constant_encoding());
365 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
366
367 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
368
369 __ bind(L_skip_barrier);
370 }
371
372 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
373 jobject o = NULL;
374 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
375 __ movoop(reg, o);
376 patching_epilog(patch, lir_patch_normal, reg, info);
377 }
378
379 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
380 Metadata* o = NULL;
381 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
382 __ mov_metadata(reg, o);
383 patching_epilog(patch, lir_patch_normal, reg, info);
384 }
385
386 // This specifies the rsp decrement needed to build the frame
387 int LIR_Assembler::initial_frame_size_in_bytes() const {
388 // if rounding, must let FrameMap know!
389
390 // The frame_map records size in slots (32bit word)
391
392 // subtract two words to account for return address and link
393 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
394 }
395
396
397 int LIR_Assembler::emit_exception_handler() {
398 // if the last instruction is a call (typically to do a throw which
399 // is coming at the end after block reordering) the return address
400 // must still point into the code area in order to avoid assertion
401 // failures when searching for the corresponding bci => add a nop
402 // (was bug 5/14/1999 - gri)
403 __ nop();
404
405 // generate code for exception handler
406 address handler_base = __ start_a_stub(exception_handler_size());
407 if (handler_base == NULL) {
408 // not enough space left for the handler
409 bailout("exception handler overflow");
410 return -1;
411 }
412
413 int offset = code_offset();
414
415 // the exception oop and pc are in rax, and rdx
416 // no other registers need to be preserved, so invalidate them
417 __ invalidate_registers(false, true, true, false, true, true);
418
419 // check that there is really an exception
420 __ verify_not_null_oop(rax);
421
422 // search an exception handler (rax: exception oop, rdx: throwing pc)
423 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
424 __ should_not_reach_here();
425 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
426 __ end_a_stub();
427
428 return offset;
429 }
430
431
432 // Emit the code to remove the frame from the stack in the exception
433 // unwind path.
434 int LIR_Assembler::emit_unwind_handler() {
435 #ifndef PRODUCT
436 if (CommentedAssembly) {
437 _masm->block_comment("Unwind handler");
438 }
439 #endif
440
441 int offset = code_offset();
442
443 // Fetch the exception from TLS and clear out exception related thread state
444 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
445 NOT_LP64(__ get_thread(rsi));
446 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
447 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
448 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
449
450 __ bind(_unwind_handler_entry);
451 __ verify_not_null_oop(rax);
452 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
453 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
454 }
455
456 // Preform needed unlocking
457 MonitorExitStub* stub = NULL;
458 if (method()->is_synchronized()) {
459 monitor_address(0, FrameMap::rax_opr);
460 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
461 __ unlock_object(rdi, rsi, rax, *stub->entry());
462 __ bind(*stub->continuation());
463 }
464
465 if (compilation()->env()->dtrace_method_probes()) {
466 #ifdef _LP64
467 __ mov(rdi, r15_thread);
468 __ mov_metadata(rsi, method()->constant_encoding());
469 #else
470 __ get_thread(rax);
471 __ movptr(Address(rsp, 0), rax);
472 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
473 #endif
474 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
475 }
476
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rax, rbx); // Restore the exception
479 }
480
481 // remove the activation and dispatch to the unwind handler
482 __ remove_frame(initial_frame_size_in_bytes());
483 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
484
485 // Emit the slow path assembly
486 if (stub != NULL) {
487 stub->emit_code(this);
488 }
489
490 return offset;
491 }
492
493
494 int LIR_Assembler::emit_deopt_handler() {
495 // if the last instruction is a call (typically to do a throw which
496 // is coming at the end after block reordering) the return address
497 // must still point into the code area in order to avoid assertion
498 // failures when searching for the corresponding bci => add a nop
499 // (was bug 5/14/1999 - gri)
500 __ nop();
501
502 // generate code for exception handler
503 address handler_base = __ start_a_stub(deopt_handler_size());
504 if (handler_base == NULL) {
505 // not enough space left for the handler
506 bailout("deopt handler overflow");
507 return -1;
508 }
509
510 int offset = code_offset();
511 InternalAddress here(__ pc());
512
513 __ pushptr(here.addr());
514 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
515 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
516 __ end_a_stub();
517
518 return offset;
519 }
520
521
522 void LIR_Assembler::return_op(LIR_Opr result) {
523 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
524 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
525 assert(result->fpu() == 0, "result must already be on TOS");
526 }
527
528 // Pop the stack before the safepoint code
529 __ remove_frame(initial_frame_size_in_bytes());
530
531 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
532 __ reserved_stack_check();
533 }
534
535 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
536
537 // Note: we do not need to round double result; float result has the right precision
538 // the poll sets the condition code, but no data registers
539
540 if (SafepointMechanism::uses_thread_local_poll()) {
541 #ifdef _LP64
542 const Register poll_addr = rscratch1;
543 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
544 #else
545 const Register poll_addr = rbx;
546 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
547 __ get_thread(poll_addr);
548 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
549 #endif
550 __ relocate(relocInfo::poll_return_type);
551 __ testl(rax, Address(poll_addr, 0));
552 } else {
553 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
554
555 if (Assembler::is_polling_page_far()) {
556 __ lea(rscratch1, polling_page);
557 __ relocate(relocInfo::poll_return_type);
558 __ testl(rax, Address(rscratch1, 0));
559 } else {
560 __ testl(rax, polling_page);
561 }
562 }
563 __ ret(0);
564 }
565
566
567 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
568 guarantee(info != NULL, "Shouldn't be NULL");
569 int offset = __ offset();
570 if (SafepointMechanism::uses_thread_local_poll()) {
571 #ifdef _LP64
572 const Register poll_addr = rscratch1;
573 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
574 #else
575 assert(tmp->is_cpu_register(), "needed");
576 const Register poll_addr = tmp->as_register();
577 __ get_thread(poll_addr);
578 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
579 #endif
580 add_debug_info_for_branch(info);
581 __ relocate(relocInfo::poll_type);
582 address pre_pc = __ pc();
583 __ testl(rax, Address(poll_addr, 0));
584 address post_pc = __ pc();
585 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
586 } else {
587 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
588 if (Assembler::is_polling_page_far()) {
589 __ lea(rscratch1, polling_page);
590 offset = __ offset();
591 add_debug_info_for_branch(info);
592 __ relocate(relocInfo::poll_type);
593 __ testl(rax, Address(rscratch1, 0));
594 } else {
595 add_debug_info_for_branch(info);
596 __ testl(rax, polling_page);
597 }
598 }
599 return offset;
600 }
601
602
603 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
604 if (from_reg != to_reg) __ mov(to_reg, from_reg);
605 }
606
607 void LIR_Assembler::swap_reg(Register a, Register b) {
608 __ xchgptr(a, b);
609 }
610
611
612 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
613 assert(src->is_constant(), "should not call otherwise");
614 assert(dest->is_register(), "should not call otherwise");
615 LIR_Const* c = src->as_constant_ptr();
616
617 switch (c->type()) {
618 case T_INT: {
619 assert(patch_code == lir_patch_none, "no patching handled here");
620 __ movl(dest->as_register(), c->as_jint());
621 break;
622 }
623
624 case T_ADDRESS: {
625 assert(patch_code == lir_patch_none, "no patching handled here");
626 __ movptr(dest->as_register(), c->as_jint());
627 break;
628 }
629
630 case T_LONG: {
631 assert(patch_code == lir_patch_none, "no patching handled here");
632 #ifdef _LP64
633 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
634 #else
635 __ movptr(dest->as_register_lo(), c->as_jint_lo());
636 __ movptr(dest->as_register_hi(), c->as_jint_hi());
637 #endif // _LP64
638 break;
639 }
640
641 case T_OBJECT: {
642 if (patch_code != lir_patch_none) {
643 jobject2reg_with_patching(dest->as_register(), info);
644 } else {
645 __ movoop(dest->as_register(), c->as_jobject());
646 }
647 break;
648 }
649
650 case T_METADATA: {
651 if (patch_code != lir_patch_none) {
652 klass2reg_with_patching(dest->as_register(), info);
653 } else {
654 __ mov_metadata(dest->as_register(), c->as_metadata());
655 }
656 break;
657 }
658
659 case T_FLOAT: {
660 if (dest->is_single_xmm()) {
661 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
662 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
663 } else {
664 __ movflt(dest->as_xmm_float_reg(),
665 InternalAddress(float_constant(c->as_jfloat())));
666 }
667 } else {
668 #ifndef _LP64
669 assert(dest->is_single_fpu(), "must be");
670 assert(dest->fpu_regnr() == 0, "dest must be TOS");
671 if (c->is_zero_float()) {
672 __ fldz();
673 } else if (c->is_one_float()) {
674 __ fld1();
675 } else {
676 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
677 }
678 #else
679 ShouldNotReachHere();
680 #endif // !_LP64
681 }
682 break;
683 }
684
685 case T_DOUBLE: {
686 if (dest->is_double_xmm()) {
687 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
688 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
689 } else {
690 __ movdbl(dest->as_xmm_double_reg(),
691 InternalAddress(double_constant(c->as_jdouble())));
692 }
693 } else {
694 #ifndef _LP64
695 assert(dest->is_double_fpu(), "must be");
696 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
697 if (c->is_zero_double()) {
698 __ fldz();
699 } else if (c->is_one_double()) {
700 __ fld1();
701 } else {
702 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
703 }
704 #else
705 ShouldNotReachHere();
706 #endif // !_LP64
707 }
708 break;
709 }
710
711 default:
712 ShouldNotReachHere();
713 }
714 }
715
716 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
717 assert(src->is_constant(), "should not call otherwise");
718 assert(dest->is_stack(), "should not call otherwise");
719 LIR_Const* c = src->as_constant_ptr();
720
721 switch (c->type()) {
722 case T_INT: // fall through
723 case T_FLOAT:
724 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
725 break;
726
727 case T_ADDRESS:
728 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
729 break;
730
731 case T_OBJECT:
732 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
733 break;
734
735 case T_LONG: // fall through
736 case T_DOUBLE:
737 #ifdef _LP64
738 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
739 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
740 #else
741 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
742 lo_word_offset_in_bytes), c->as_jint_lo_bits());
743 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
744 hi_word_offset_in_bytes), c->as_jint_hi_bits());
745 #endif // _LP64
746 break;
747
748 default:
749 ShouldNotReachHere();
750 }
751 }
752
753 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
754 assert(src->is_constant(), "should not call otherwise");
755 assert(dest->is_address(), "should not call otherwise");
756 LIR_Const* c = src->as_constant_ptr();
757 LIR_Address* addr = dest->as_address_ptr();
758
759 int null_check_here = code_offset();
760 switch (type) {
761 case T_INT: // fall through
762 case T_FLOAT:
763 __ movl(as_Address(addr), c->as_jint_bits());
764 break;
765
766 case T_ADDRESS:
767 __ movptr(as_Address(addr), c->as_jint_bits());
768 break;
769
770 case T_OBJECT: // fall through
771 case T_ARRAY:
772 if (c->as_jobject() == NULL) {
773 if (UseCompressedOops && !wide) {
774 __ movl(as_Address(addr), (int32_t)NULL_WORD);
775 } else {
776 #ifdef _LP64
777 __ xorptr(rscratch1, rscratch1);
778 null_check_here = code_offset();
779 __ movptr(as_Address(addr), rscratch1);
780 #else
781 __ movptr(as_Address(addr), NULL_WORD);
782 #endif
783 }
784 } else {
785 if (is_literal_address(addr)) {
786 ShouldNotReachHere();
787 __ movoop(as_Address(addr, noreg), c->as_jobject());
788 } else {
789 #ifdef _LP64
790 __ movoop(rscratch1, c->as_jobject());
791 if (UseCompressedOops && !wide) {
792 __ encode_heap_oop(rscratch1);
793 null_check_here = code_offset();
794 __ movl(as_Address_lo(addr), rscratch1);
795 } else {
796 null_check_here = code_offset();
797 __ movptr(as_Address_lo(addr), rscratch1);
798 }
799 #else
800 __ movoop(as_Address(addr), c->as_jobject());
801 #endif
802 }
803 }
804 break;
805
806 case T_LONG: // fall through
807 case T_DOUBLE:
808 #ifdef _LP64
809 if (is_literal_address(addr)) {
810 ShouldNotReachHere();
811 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
812 } else {
813 __ movptr(r10, (intptr_t)c->as_jlong_bits());
814 null_check_here = code_offset();
815 __ movptr(as_Address_lo(addr), r10);
816 }
817 #else
818 // Always reachable in 32bit so this doesn't produce useless move literal
819 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
820 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
821 #endif // _LP64
822 break;
823
824 case T_BOOLEAN: // fall through
825 case T_BYTE:
826 __ movb(as_Address(addr), c->as_jint() & 0xFF);
827 break;
828
829 case T_CHAR: // fall through
830 case T_SHORT:
831 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
832 break;
833
834 default:
835 ShouldNotReachHere();
836 };
837
838 if (info != NULL) {
839 add_debug_info_for_null_check(null_check_here, info);
840 }
841 }
842
843
844 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
845 assert(src->is_register(), "should not call otherwise");
846 assert(dest->is_register(), "should not call otherwise");
847
848 // move between cpu-registers
849 if (dest->is_single_cpu()) {
850 #ifdef _LP64
851 if (src->type() == T_LONG) {
852 // Can do LONG -> OBJECT
853 move_regs(src->as_register_lo(), dest->as_register());
854 return;
855 }
856 #endif
857 assert(src->is_single_cpu(), "must match");
858 if (src->type() == T_OBJECT) {
859 __ verify_oop(src->as_register());
860 }
861 move_regs(src->as_register(), dest->as_register());
862
863 } else if (dest->is_double_cpu()) {
864 #ifdef _LP64
865 if (is_reference_type(src->type())) {
866 // Surprising to me but we can see move of a long to t_object
867 __ verify_oop(src->as_register());
868 move_regs(src->as_register(), dest->as_register_lo());
869 return;
870 }
871 #endif
872 assert(src->is_double_cpu(), "must match");
873 Register f_lo = src->as_register_lo();
874 Register f_hi = src->as_register_hi();
875 Register t_lo = dest->as_register_lo();
876 Register t_hi = dest->as_register_hi();
877 #ifdef _LP64
878 assert(f_hi == f_lo, "must be same");
879 assert(t_hi == t_lo, "must be same");
880 move_regs(f_lo, t_lo);
881 #else
882 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
883
884
885 if (f_lo == t_hi && f_hi == t_lo) {
886 swap_reg(f_lo, f_hi);
887 } else if (f_hi == t_lo) {
888 assert(f_lo != t_hi, "overwriting register");
889 move_regs(f_hi, t_hi);
890 move_regs(f_lo, t_lo);
891 } else {
892 assert(f_hi != t_lo, "overwriting register");
893 move_regs(f_lo, t_lo);
894 move_regs(f_hi, t_hi);
895 }
896 #endif // LP64
897
898 #ifndef _LP64
899 // special moves from fpu-register to xmm-register
900 // necessary for method results
901 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
902 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
903 __ fld_s(Address(rsp, 0));
904 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
905 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
906 __ fld_d(Address(rsp, 0));
907 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
908 __ fstp_s(Address(rsp, 0));
909 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
910 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
911 __ fstp_d(Address(rsp, 0));
912 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
913
914 // move between fpu-registers (no instruction necessary because of fpu-stack)
915 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
916 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
917 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
918 #endif // !_LP64
919
920 // move between xmm-registers
921 } else if (dest->is_single_xmm()) {
922 assert(src->is_single_xmm(), "must match");
923 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
924 } else if (dest->is_double_xmm()) {
925 assert(src->is_double_xmm(), "must match");
926 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
927
928 } else {
929 ShouldNotReachHere();
930 }
931 }
932
933 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
934 assert(src->is_register(), "should not call otherwise");
935 assert(dest->is_stack(), "should not call otherwise");
936
937 if (src->is_single_cpu()) {
938 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
939 if (is_reference_type(type)) {
940 __ verify_oop(src->as_register());
941 __ movptr (dst, src->as_register());
942 } else if (type == T_METADATA) {
943 __ movptr (dst, src->as_register());
944 } else {
945 __ movl (dst, src->as_register());
946 }
947
948 } else if (src->is_double_cpu()) {
949 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
950 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
951 __ movptr (dstLO, src->as_register_lo());
952 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
953
954 } else if (src->is_single_xmm()) {
955 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
956 __ movflt(dst_addr, src->as_xmm_float_reg());
957
958 } else if (src->is_double_xmm()) {
959 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
960 __ movdbl(dst_addr, src->as_xmm_double_reg());
961
962 #ifndef _LP64
963 } else if (src->is_single_fpu()) {
964 assert(src->fpu_regnr() == 0, "argument must be on TOS");
965 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
966 if (pop_fpu_stack) __ fstp_s (dst_addr);
967 else __ fst_s (dst_addr);
968
969 } else if (src->is_double_fpu()) {
970 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
971 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
972 if (pop_fpu_stack) __ fstp_d (dst_addr);
973 else __ fst_d (dst_addr);
974 #endif // !_LP64
975
976 } else {
977 ShouldNotReachHere();
978 }
979 }
980
981
982 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
983 LIR_Address* to_addr = dest->as_address_ptr();
984 PatchingStub* patch = NULL;
985 Register compressed_src = rscratch1;
986
987 if (is_reference_type(type)) {
988 __ verify_oop(src->as_register());
989 #ifdef _LP64
990 if (UseCompressedOops && !wide) {
991 __ movptr(compressed_src, src->as_register());
992 __ encode_heap_oop(compressed_src);
993 if (patch_code != lir_patch_none) {
994 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
995 }
996 }
997 #endif
998 }
999
1000 if (patch_code != lir_patch_none) {
1001 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1002 Address toa = as_Address(to_addr);
1003 assert(toa.disp() != 0, "must have");
1004 }
1005
1006 int null_check_here = code_offset();
1007 switch (type) {
1008 case T_FLOAT: {
1009 #ifdef _LP64
1010 assert(src->is_single_xmm(), "not a float");
1011 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1012 #else
1013 if (src->is_single_xmm()) {
1014 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1015 } else {
1016 assert(src->is_single_fpu(), "must be");
1017 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1018 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1019 else __ fst_s (as_Address(to_addr));
1020 }
1021 #endif // _LP64
1022 break;
1023 }
1024
1025 case T_DOUBLE: {
1026 #ifdef _LP64
1027 assert(src->is_double_xmm(), "not a double");
1028 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1029 #else
1030 if (src->is_double_xmm()) {
1031 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1032 } else {
1033 assert(src->is_double_fpu(), "must be");
1034 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1035 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1036 else __ fst_d (as_Address(to_addr));
1037 }
1038 #endif // _LP64
1039 break;
1040 }
1041
1042 case T_ARRAY: // fall through
1043 case T_OBJECT: // fall through
1044 if (UseCompressedOops && !wide) {
1045 __ movl(as_Address(to_addr), compressed_src);
1046 } else {
1047 __ movptr(as_Address(to_addr), src->as_register());
1048 }
1049 break;
1050 case T_METADATA:
1051 // We get here to store a method pointer to the stack to pass to
1052 // a dtrace runtime call. This can't work on 64 bit with
1053 // compressed klass ptrs: T_METADATA can be a compressed klass
1054 // ptr or a 64 bit method pointer.
1055 LP64_ONLY(ShouldNotReachHere());
1056 __ movptr(as_Address(to_addr), src->as_register());
1057 break;
1058 case T_ADDRESS:
1059 __ movptr(as_Address(to_addr), src->as_register());
1060 break;
1061 case T_INT:
1062 __ movl(as_Address(to_addr), src->as_register());
1063 break;
1064
1065 case T_LONG: {
1066 Register from_lo = src->as_register_lo();
1067 Register from_hi = src->as_register_hi();
1068 #ifdef _LP64
1069 __ movptr(as_Address_lo(to_addr), from_lo);
1070 #else
1071 Register base = to_addr->base()->as_register();
1072 Register index = noreg;
1073 if (to_addr->index()->is_register()) {
1074 index = to_addr->index()->as_register();
1075 }
1076 if (base == from_lo || index == from_lo) {
1077 assert(base != from_hi, "can't be");
1078 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1079 __ movl(as_Address_hi(to_addr), from_hi);
1080 if (patch != NULL) {
1081 patching_epilog(patch, lir_patch_high, base, info);
1082 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1083 patch_code = lir_patch_low;
1084 }
1085 __ movl(as_Address_lo(to_addr), from_lo);
1086 } else {
1087 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1088 __ movl(as_Address_lo(to_addr), from_lo);
1089 if (patch != NULL) {
1090 patching_epilog(patch, lir_patch_low, base, info);
1091 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1092 patch_code = lir_patch_high;
1093 }
1094 __ movl(as_Address_hi(to_addr), from_hi);
1095 }
1096 #endif // _LP64
1097 break;
1098 }
1099
1100 case T_BYTE: // fall through
1101 case T_BOOLEAN: {
1102 Register src_reg = src->as_register();
1103 Address dst_addr = as_Address(to_addr);
1104 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1105 __ movb(dst_addr, src_reg);
1106 break;
1107 }
1108
1109 case T_CHAR: // fall through
1110 case T_SHORT:
1111 __ movw(as_Address(to_addr), src->as_register());
1112 break;
1113
1114 default:
1115 ShouldNotReachHere();
1116 }
1117 if (info != NULL) {
1118 add_debug_info_for_null_check(null_check_here, info);
1119 }
1120
1121 if (patch_code != lir_patch_none) {
1122 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1123 }
1124 }
1125
1126
1127 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1128 assert(src->is_stack(), "should not call otherwise");
1129 assert(dest->is_register(), "should not call otherwise");
1130
1131 if (dest->is_single_cpu()) {
1132 if (is_reference_type(type)) {
1133 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1134 __ verify_oop(dest->as_register());
1135 } else if (type == T_METADATA) {
1136 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1137 } else {
1138 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1139 }
1140
1141 } else if (dest->is_double_cpu()) {
1142 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1143 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1144 __ movptr(dest->as_register_lo(), src_addr_LO);
1145 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1146
1147 } else if (dest->is_single_xmm()) {
1148 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1149 __ movflt(dest->as_xmm_float_reg(), src_addr);
1150
1151 } else if (dest->is_double_xmm()) {
1152 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1153 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1154
1155 #ifndef _LP64
1156 } else if (dest->is_single_fpu()) {
1157 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1158 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1159 __ fld_s(src_addr);
1160
1161 } else if (dest->is_double_fpu()) {
1162 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1163 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1164 __ fld_d(src_addr);
1165 #endif // _LP64
1166
1167 } else {
1168 ShouldNotReachHere();
1169 }
1170 }
1171
1172
1173 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1174 if (src->is_single_stack()) {
1175 if (is_reference_type(type)) {
1176 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1177 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1178 } else {
1179 #ifndef _LP64
1180 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1181 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1182 #else
1183 //no pushl on 64bits
1184 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1185 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1186 #endif
1187 }
1188
1189 } else if (src->is_double_stack()) {
1190 #ifdef _LP64
1191 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1192 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1193 #else
1194 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1195 // push and pop the part at src + wordSize, adding wordSize for the previous push
1196 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1197 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1198 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1199 #endif // _LP64
1200
1201 } else {
1202 ShouldNotReachHere();
1203 }
1204 }
1205
1206
1207 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1208 assert(src->is_address(), "should not call otherwise");
1209 assert(dest->is_register(), "should not call otherwise");
1210
1211 LIR_Address* addr = src->as_address_ptr();
1212 Address from_addr = as_Address(addr);
1213
1214 if (addr->base()->type() == T_OBJECT) {
1215 __ verify_oop(addr->base()->as_pointer_register());
1216 }
1217
1218 switch (type) {
1219 case T_BOOLEAN: // fall through
1220 case T_BYTE: // fall through
1221 case T_CHAR: // fall through
1222 case T_SHORT:
1223 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1224 // on pre P6 processors we may get partial register stalls
1225 // so blow away the value of to_rinfo before loading a
1226 // partial word into it. Do it here so that it precedes
1227 // the potential patch point below.
1228 __ xorptr(dest->as_register(), dest->as_register());
1229 }
1230 break;
1231 default:
1232 break;
1233 }
1234
1235 PatchingStub* patch = NULL;
1236 if (patch_code != lir_patch_none) {
1237 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1238 assert(from_addr.disp() != 0, "must have");
1239 }
1240 if (info != NULL) {
1241 add_debug_info_for_null_check_here(info);
1242 }
1243
1244 switch (type) {
1245 case T_FLOAT: {
1246 if (dest->is_single_xmm()) {
1247 __ movflt(dest->as_xmm_float_reg(), from_addr);
1248 } else {
1249 #ifndef _LP64
1250 assert(dest->is_single_fpu(), "must be");
1251 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1252 __ fld_s(from_addr);
1253 #else
1254 ShouldNotReachHere();
1255 #endif // !LP64
1256 }
1257 break;
1258 }
1259
1260 case T_DOUBLE: {
1261 if (dest->is_double_xmm()) {
1262 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1263 } else {
1264 #ifndef _LP64
1265 assert(dest->is_double_fpu(), "must be");
1266 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1267 __ fld_d(from_addr);
1268 #else
1269 ShouldNotReachHere();
1270 #endif // !LP64
1271 }
1272 break;
1273 }
1274
1275 case T_OBJECT: // fall through
1276 case T_ARRAY: // fall through
1277 if (UseCompressedOops && !wide) {
1278 __ movl(dest->as_register(), from_addr);
1279 } else {
1280 __ movptr(dest->as_register(), from_addr);
1281 }
1282 break;
1283
1284 case T_ADDRESS:
1285 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1286 __ movl(dest->as_register(), from_addr);
1287 } else {
1288 __ movptr(dest->as_register(), from_addr);
1289 }
1290 break;
1291 case T_INT:
1292 __ movl(dest->as_register(), from_addr);
1293 break;
1294
1295 case T_LONG: {
1296 Register to_lo = dest->as_register_lo();
1297 Register to_hi = dest->as_register_hi();
1298 #ifdef _LP64
1299 __ movptr(to_lo, as_Address_lo(addr));
1300 #else
1301 Register base = addr->base()->as_register();
1302 Register index = noreg;
1303 if (addr->index()->is_register()) {
1304 index = addr->index()->as_register();
1305 }
1306 if ((base == to_lo && index == to_hi) ||
1307 (base == to_hi && index == to_lo)) {
1308 // addresses with 2 registers are only formed as a result of
1309 // array access so this code will never have to deal with
1310 // patches or null checks.
1311 assert(info == NULL && patch == NULL, "must be");
1312 __ lea(to_hi, as_Address(addr));
1313 __ movl(to_lo, Address(to_hi, 0));
1314 __ movl(to_hi, Address(to_hi, BytesPerWord));
1315 } else if (base == to_lo || index == to_lo) {
1316 assert(base != to_hi, "can't be");
1317 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1318 __ movl(to_hi, as_Address_hi(addr));
1319 if (patch != NULL) {
1320 patching_epilog(patch, lir_patch_high, base, info);
1321 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1322 patch_code = lir_patch_low;
1323 }
1324 __ movl(to_lo, as_Address_lo(addr));
1325 } else {
1326 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1327 __ movl(to_lo, as_Address_lo(addr));
1328 if (patch != NULL) {
1329 patching_epilog(patch, lir_patch_low, base, info);
1330 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1331 patch_code = lir_patch_high;
1332 }
1333 __ movl(to_hi, as_Address_hi(addr));
1334 }
1335 #endif // _LP64
1336 break;
1337 }
1338
1339 case T_BOOLEAN: // fall through
1340 case T_BYTE: {
1341 Register dest_reg = dest->as_register();
1342 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1343 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1344 __ movsbl(dest_reg, from_addr);
1345 } else {
1346 __ movb(dest_reg, from_addr);
1347 __ shll(dest_reg, 24);
1348 __ sarl(dest_reg, 24);
1349 }
1350 break;
1351 }
1352
1353 case T_CHAR: {
1354 Register dest_reg = dest->as_register();
1355 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1356 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1357 __ movzwl(dest_reg, from_addr);
1358 } else {
1359 __ movw(dest_reg, from_addr);
1360 }
1361 break;
1362 }
1363
1364 case T_SHORT: {
1365 Register dest_reg = dest->as_register();
1366 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1367 __ movswl(dest_reg, from_addr);
1368 } else {
1369 __ movw(dest_reg, from_addr);
1370 __ shll(dest_reg, 16);
1371 __ sarl(dest_reg, 16);
1372 }
1373 break;
1374 }
1375
1376 default:
1377 ShouldNotReachHere();
1378 }
1379
1380 if (patch != NULL) {
1381 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1382 }
1383
1384 if (is_reference_type(type)) {
1385 #ifdef _LP64
1386 if (UseCompressedOops && !wide) {
1387 __ decode_heap_oop(dest->as_register());
1388 }
1389 #endif
1390
1391 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1392 if (!UseZGC) {
1393 __ verify_oop(dest->as_register());
1394 }
1395 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1396 #ifdef _LP64
1397 if (UseCompressedClassPointers) {
1398 __ decode_klass_not_null(dest->as_register());
1399 }
1400 #endif
1401 }
1402 }
1403
1404
1405 NEEDS_CLEANUP; // This could be static?
1406 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1407 int elem_size = type2aelembytes(type);
1408 switch (elem_size) {
1409 case 1: return Address::times_1;
1410 case 2: return Address::times_2;
1411 case 4: return Address::times_4;
1412 case 8: return Address::times_8;
1413 }
1414 ShouldNotReachHere();
1415 return Address::no_scale;
1416 }
1417
1418
1419 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1420 switch (op->code()) {
1421 case lir_idiv:
1422 case lir_irem:
1423 arithmetic_idiv(op->code(),
1424 op->in_opr1(),
1425 op->in_opr2(),
1426 op->in_opr3(),
1427 op->result_opr(),
1428 op->info());
1429 break;
1430 case lir_fmad:
1431 __ fmad(op->result_opr()->as_xmm_double_reg(),
1432 op->in_opr1()->as_xmm_double_reg(),
1433 op->in_opr2()->as_xmm_double_reg(),
1434 op->in_opr3()->as_xmm_double_reg());
1435 break;
1436 case lir_fmaf:
1437 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1438 op->in_opr1()->as_xmm_float_reg(),
1439 op->in_opr2()->as_xmm_float_reg(),
1440 op->in_opr3()->as_xmm_float_reg());
1441 break;
1442 default: ShouldNotReachHere(); break;
1443 }
1444 }
1445
1446 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1447 #ifdef ASSERT
1448 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1449 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1450 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1451 #endif
1452
1453 if (op->cond() == lir_cond_always) {
1454 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1455 __ jmp (*(op->label()));
1456 } else {
1457 Assembler::Condition acond = Assembler::zero;
1458 if (op->code() == lir_cond_float_branch) {
1459 assert(op->ublock() != NULL, "must have unordered successor");
1460 __ jcc(Assembler::parity, *(op->ublock()->label()));
1461 switch(op->cond()) {
1462 case lir_cond_equal: acond = Assembler::equal; break;
1463 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1464 case lir_cond_less: acond = Assembler::below; break;
1465 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1466 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1467 case lir_cond_greater: acond = Assembler::above; break;
1468 default: ShouldNotReachHere();
1469 }
1470 } else {
1471 switch (op->cond()) {
1472 case lir_cond_equal: acond = Assembler::equal; break;
1473 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1474 case lir_cond_less: acond = Assembler::less; break;
1475 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1476 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1477 case lir_cond_greater: acond = Assembler::greater; break;
1478 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1479 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1480 default: ShouldNotReachHere();
1481 }
1482 }
1483 __ jcc(acond,*(op->label()));
1484 }
1485 }
1486
1487 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1488 LIR_Opr src = op->in_opr();
1489 LIR_Opr dest = op->result_opr();
1490
1491 switch (op->bytecode()) {
1492 case Bytecodes::_i2l:
1493 #ifdef _LP64
1494 __ movl2ptr(dest->as_register_lo(), src->as_register());
1495 #else
1496 move_regs(src->as_register(), dest->as_register_lo());
1497 move_regs(src->as_register(), dest->as_register_hi());
1498 __ sarl(dest->as_register_hi(), 31);
1499 #endif // LP64
1500 break;
1501
1502 case Bytecodes::_l2i:
1503 #ifdef _LP64
1504 __ movl(dest->as_register(), src->as_register_lo());
1505 #else
1506 move_regs(src->as_register_lo(), dest->as_register());
1507 #endif
1508 break;
1509
1510 case Bytecodes::_i2b:
1511 move_regs(src->as_register(), dest->as_register());
1512 __ sign_extend_byte(dest->as_register());
1513 break;
1514
1515 case Bytecodes::_i2c:
1516 move_regs(src->as_register(), dest->as_register());
1517 __ andl(dest->as_register(), 0xFFFF);
1518 break;
1519
1520 case Bytecodes::_i2s:
1521 move_regs(src->as_register(), dest->as_register());
1522 __ sign_extend_short(dest->as_register());
1523 break;
1524
1525
1526 #ifdef _LP64
1527 case Bytecodes::_f2d:
1528 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1529 break;
1530
1531 case Bytecodes::_d2f:
1532 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1533 break;
1534
1535 case Bytecodes::_i2f:
1536 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1537 break;
1538
1539 case Bytecodes::_i2d:
1540 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1541 break;
1542
1543 case Bytecodes::_l2f:
1544 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1545 break;
1546
1547 case Bytecodes::_l2d:
1548 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1549 break;
1550
1551 case Bytecodes::_f2i:
1552 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1553 break;
1554
1555 case Bytecodes::_d2i:
1556 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1557 break;
1558
1559 case Bytecodes::_f2l:
1560 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1561 break;
1562
1563 case Bytecodes::_d2l:
1564 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1565 break;
1566 #else
1567 case Bytecodes::_f2d:
1568 case Bytecodes::_d2f:
1569 if (dest->is_single_xmm()) {
1570 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1571 } else if (dest->is_double_xmm()) {
1572 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1573 } else {
1574 assert(src->fpu() == dest->fpu(), "register must be equal");
1575 // do nothing (float result is rounded later through spilling)
1576 }
1577 break;
1578
1579 case Bytecodes::_i2f:
1580 case Bytecodes::_i2d:
1581 if (dest->is_single_xmm()) {
1582 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1583 } else if (dest->is_double_xmm()) {
1584 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1585 } else {
1586 assert(dest->fpu() == 0, "result must be on TOS");
1587 __ movl(Address(rsp, 0), src->as_register());
1588 __ fild_s(Address(rsp, 0));
1589 }
1590 break;
1591
1592 case Bytecodes::_l2f:
1593 case Bytecodes::_l2d:
1594 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1595 assert(dest->fpu() == 0, "result must be on TOS");
1596 __ movptr(Address(rsp, 0), src->as_register_lo());
1597 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1598 __ fild_d(Address(rsp, 0));
1599 // float result is rounded later through spilling
1600
1601 case Bytecodes::_f2i:
1602 case Bytecodes::_d2i:
1603 if (src->is_single_xmm()) {
1604 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1605 } else if (src->is_double_xmm()) {
1606 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1607 } else {
1608 assert(src->fpu() == 0, "input must be on TOS");
1609 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1610 __ fist_s(Address(rsp, 0));
1611 __ movl(dest->as_register(), Address(rsp, 0));
1612 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1613 }
1614 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1615 assert(op->stub() != NULL, "stub required");
1616 __ cmpl(dest->as_register(), 0x80000000);
1617 __ jcc(Assembler::equal, *op->stub()->entry());
1618 __ bind(*op->stub()->continuation());
1619 break;
1620
1621 case Bytecodes::_f2l:
1622 case Bytecodes::_d2l:
1623 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1624 assert(src->fpu() == 0, "input must be on TOS");
1625 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1626
1627 // instruction sequence too long to inline it here
1628 {
1629 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1630 }
1631 break;
1632 #endif // _LP64
1633
1634 default: ShouldNotReachHere();
1635 }
1636 }
1637
1638 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1639 if (op->init_check()) {
1640 add_debug_info_for_null_check_here(op->stub()->info());
1641 __ cmpb(Address(op->klass()->as_register(),
1642 InstanceKlass::init_state_offset()),
1643 InstanceKlass::fully_initialized);
1644 __ jcc(Assembler::notEqual, *op->stub()->entry());
1645 }
1646 __ allocate_object(op->obj()->as_register(),
1647 op->tmp1()->as_register(),
1648 op->tmp2()->as_register(),
1649 op->header_size(),
1650 op->object_size(),
1651 op->klass()->as_register(),
1652 *op->stub()->entry());
1653 __ bind(*op->stub()->continuation());
1654 }
1655
1656 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1657 Register len = op->len()->as_register();
1658 LP64_ONLY( __ movslq(len, len); )
1659
1660 if (UseSlowPath ||
1661 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1662 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1663 __ jmp(*op->stub()->entry());
1664 } else {
1665 Register tmp1 = op->tmp1()->as_register();
1666 Register tmp2 = op->tmp2()->as_register();
1667 Register tmp3 = op->tmp3()->as_register();
1668 if (len == tmp1) {
1669 tmp1 = tmp3;
1670 } else if (len == tmp2) {
1671 tmp2 = tmp3;
1672 } else if (len == tmp3) {
1673 // everything is ok
1674 } else {
1675 __ mov(tmp3, len);
1676 }
1677 __ allocate_array(op->obj()->as_register(),
1678 len,
1679 tmp1,
1680 tmp2,
1681 arrayOopDesc::header_size(op->type()),
1682 array_element_size(op->type()),
1683 op->klass()->as_register(),
1684 *op->stub()->entry());
1685 }
1686 __ bind(*op->stub()->continuation());
1687 }
1688
1689 void LIR_Assembler::type_profile_helper(Register mdo,
1690 ciMethodData *md, ciProfileData *data,
1691 Register recv, Label* update_done) {
1692 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1693 Label next_test;
1694 // See if the receiver is receiver[n].
1695 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1696 __ jccb(Assembler::notEqual, next_test);
1697 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1698 __ addptr(data_addr, DataLayout::counter_increment);
1699 __ jmp(*update_done);
1700 __ bind(next_test);
1701 }
1702
1703 // Didn't find receiver; find next empty slot and fill it in
1704 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1705 Label next_test;
1706 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1707 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1708 __ jccb(Assembler::notEqual, next_test);
1709 __ movptr(recv_addr, recv);
1710 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1711 __ jmp(*update_done);
1712 __ bind(next_test);
1713 }
1714 }
1715
1716 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1717 // we always need a stub for the failure case.
1718 CodeStub* stub = op->stub();
1719 Register obj = op->object()->as_register();
1720 Register k_RInfo = op->tmp1()->as_register();
1721 Register klass_RInfo = op->tmp2()->as_register();
1722 Register dst = op->result_opr()->as_register();
1723 ciKlass* k = op->klass();
1724 Register Rtmp1 = noreg;
1725
1726 // check if it needs to be profiled
1727 ciMethodData* md = NULL;
1728 ciProfileData* data = NULL;
1729
1730 if (op->should_profile()) {
1731 ciMethod* method = op->profiled_method();
1732 assert(method != NULL, "Should have method");
1733 int bci = op->profiled_bci();
1734 md = method->method_data_or_null();
1735 assert(md != NULL, "Sanity");
1736 data = md->bci_to_data(bci);
1737 assert(data != NULL, "need data for type check");
1738 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1739 }
1740 Label profile_cast_success, profile_cast_failure;
1741 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1742 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1743
1744 if (obj == k_RInfo) {
1745 k_RInfo = dst;
1746 } else if (obj == klass_RInfo) {
1747 klass_RInfo = dst;
1748 }
1749 if (k->is_loaded() && !UseCompressedClassPointers) {
1750 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1751 } else {
1752 Rtmp1 = op->tmp3()->as_register();
1753 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1754 }
1755
1756 assert_different_registers(obj, k_RInfo, klass_RInfo);
1757
1758 __ cmpptr(obj, (int32_t)NULL_WORD);
1759 if (op->should_profile()) {
1760 Label not_null;
1761 __ jccb(Assembler::notEqual, not_null);
1762 // Object is null; update MDO and exit
1763 Register mdo = klass_RInfo;
1764 __ mov_metadata(mdo, md->constant_encoding());
1765 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1766 int header_bits = BitData::null_seen_byte_constant();
1767 __ orb(data_addr, header_bits);
1768 __ jmp(*obj_is_null);
1769 __ bind(not_null);
1770 } else {
1771 __ jcc(Assembler::equal, *obj_is_null);
1772 }
1773
1774 if (!k->is_loaded()) {
1775 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1776 } else {
1777 #ifdef _LP64
1778 __ mov_metadata(k_RInfo, k->constant_encoding());
1779 #endif // _LP64
1780 }
1781 __ verify_oop(obj);
1782
1783 if (op->fast_check()) {
1784 // get object class
1785 // not a safepoint as obj null check happens earlier
1786 #ifdef _LP64
1787 if (UseCompressedClassPointers) {
1788 __ load_klass(Rtmp1, obj);
1789 __ cmpptr(k_RInfo, Rtmp1);
1790 } else {
1791 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1792 }
1793 #else
1794 if (k->is_loaded()) {
1795 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1796 } else {
1797 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1798 }
1799 #endif
1800 __ jcc(Assembler::notEqual, *failure_target);
1801 // successful cast, fall through to profile or jump
1802 } else {
1803 // get object class
1804 // not a safepoint as obj null check happens earlier
1805 __ load_klass(klass_RInfo, obj);
1806 if (k->is_loaded()) {
1807 // See if we get an immediate positive hit
1808 #ifdef _LP64
1809 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1810 #else
1811 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1812 #endif // _LP64
1813 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1814 __ jcc(Assembler::notEqual, *failure_target);
1815 // successful cast, fall through to profile or jump
1816 } else {
1817 // See if we get an immediate positive hit
1818 __ jcc(Assembler::equal, *success_target);
1819 // check for self
1820 #ifdef _LP64
1821 __ cmpptr(klass_RInfo, k_RInfo);
1822 #else
1823 __ cmpklass(klass_RInfo, k->constant_encoding());
1824 #endif // _LP64
1825 __ jcc(Assembler::equal, *success_target);
1826
1827 __ push(klass_RInfo);
1828 #ifdef _LP64
1829 __ push(k_RInfo);
1830 #else
1831 __ pushklass(k->constant_encoding());
1832 #endif // _LP64
1833 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1834 __ pop(klass_RInfo);
1835 __ pop(klass_RInfo);
1836 // result is a boolean
1837 __ cmpl(klass_RInfo, 0);
1838 __ jcc(Assembler::equal, *failure_target);
1839 // successful cast, fall through to profile or jump
1840 }
1841 } else {
1842 // perform the fast part of the checking logic
1843 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1844 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1845 __ push(klass_RInfo);
1846 __ push(k_RInfo);
1847 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1848 __ pop(klass_RInfo);
1849 __ pop(k_RInfo);
1850 // result is a boolean
1851 __ cmpl(k_RInfo, 0);
1852 __ jcc(Assembler::equal, *failure_target);
1853 // successful cast, fall through to profile or jump
1854 }
1855 }
1856 if (op->should_profile()) {
1857 Register mdo = klass_RInfo, recv = k_RInfo;
1858 __ bind(profile_cast_success);
1859 __ mov_metadata(mdo, md->constant_encoding());
1860 __ load_klass(recv, obj);
1861 type_profile_helper(mdo, md, data, recv, success);
1862 __ jmp(*success);
1863
1864 __ bind(profile_cast_failure);
1865 __ mov_metadata(mdo, md->constant_encoding());
1866 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1867 __ subptr(counter_addr, DataLayout::counter_increment);
1868 __ jmp(*failure);
1869 }
1870 __ jmp(*success);
1871 }
1872
1873
1874 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1875 LIR_Code code = op->code();
1876 if (code == lir_store_check) {
1877 Register value = op->object()->as_register();
1878 Register array = op->array()->as_register();
1879 Register k_RInfo = op->tmp1()->as_register();
1880 Register klass_RInfo = op->tmp2()->as_register();
1881 Register Rtmp1 = op->tmp3()->as_register();
1882
1883 CodeStub* stub = op->stub();
1884
1885 // check if it needs to be profiled
1886 ciMethodData* md = NULL;
1887 ciProfileData* data = NULL;
1888
1889 if (op->should_profile()) {
1890 ciMethod* method = op->profiled_method();
1891 assert(method != NULL, "Should have method");
1892 int bci = op->profiled_bci();
1893 md = method->method_data_or_null();
1894 assert(md != NULL, "Sanity");
1895 data = md->bci_to_data(bci);
1896 assert(data != NULL, "need data for type check");
1897 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1898 }
1899 Label profile_cast_success, profile_cast_failure, done;
1900 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1901 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1902
1903 __ cmpptr(value, (int32_t)NULL_WORD);
1904 if (op->should_profile()) {
1905 Label not_null;
1906 __ jccb(Assembler::notEqual, not_null);
1907 // Object is null; update MDO and exit
1908 Register mdo = klass_RInfo;
1909 __ mov_metadata(mdo, md->constant_encoding());
1910 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1911 int header_bits = BitData::null_seen_byte_constant();
1912 __ orb(data_addr, header_bits);
1913 __ jmp(done);
1914 __ bind(not_null);
1915 } else {
1916 __ jcc(Assembler::equal, done);
1917 }
1918
1919 add_debug_info_for_null_check_here(op->info_for_exception());
1920 __ load_klass(k_RInfo, array);
1921 __ load_klass(klass_RInfo, value);
1922
1923 // get instance klass (it's already uncompressed)
1924 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1925 // perform the fast part of the checking logic
1926 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1927 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1928 __ push(klass_RInfo);
1929 __ push(k_RInfo);
1930 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1931 __ pop(klass_RInfo);
1932 __ pop(k_RInfo);
1933 // result is a boolean
1934 __ cmpl(k_RInfo, 0);
1935 __ jcc(Assembler::equal, *failure_target);
1936 // fall through to the success case
1937
1938 if (op->should_profile()) {
1939 Register mdo = klass_RInfo, recv = k_RInfo;
1940 __ bind(profile_cast_success);
1941 __ mov_metadata(mdo, md->constant_encoding());
1942 __ load_klass(recv, value);
1943 type_profile_helper(mdo, md, data, recv, &done);
1944 __ jmpb(done);
1945
1946 __ bind(profile_cast_failure);
1947 __ mov_metadata(mdo, md->constant_encoding());
1948 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1949 __ subptr(counter_addr, DataLayout::counter_increment);
1950 __ jmp(*stub->entry());
1951 }
1952
1953 __ bind(done);
1954 } else
1955 if (code == lir_checkcast) {
1956 Register obj = op->object()->as_register();
1957 Register dst = op->result_opr()->as_register();
1958 Label success;
1959 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1960 __ bind(success);
1961 if (dst != obj) {
1962 __ mov(dst, obj);
1963 }
1964 } else
1965 if (code == lir_instanceof) {
1966 Register obj = op->object()->as_register();
1967 Register dst = op->result_opr()->as_register();
1968 Label success, failure, done;
1969 emit_typecheck_helper(op, &success, &failure, &failure);
1970 __ bind(failure);
1971 __ xorptr(dst, dst);
1972 __ jmpb(done);
1973 __ bind(success);
1974 __ movptr(dst, 1);
1975 __ bind(done);
1976 } else {
1977 ShouldNotReachHere();
1978 }
1979
1980 }
1981
1982
1983 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1984 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1985 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1986 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1987 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1988 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1989 Register addr = op->addr()->as_register();
1990 __ lock();
1991 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1992
1993 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1994 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1995 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1996 Register newval = op->new_value()->as_register();
1997 Register cmpval = op->cmp_value()->as_register();
1998 assert(cmpval == rax, "wrong register");
1999 assert(newval != NULL, "new val must be register");
2000 assert(cmpval != newval, "cmp and new values must be in different registers");
2001 assert(cmpval != addr, "cmp and addr must be in different registers");
2002 assert(newval != addr, "new value and addr must be in different registers");
2003
2004 if ( op->code() == lir_cas_obj) {
2005 #ifdef _LP64
2006 if (UseCompressedOops) {
2007 __ encode_heap_oop(cmpval);
2008 __ mov(rscratch1, newval);
2009 __ encode_heap_oop(rscratch1);
2010 __ lock();
2011 // cmpval (rax) is implicitly used by this instruction
2012 __ cmpxchgl(rscratch1, Address(addr, 0));
2013 } else
2014 #endif
2015 {
2016 __ lock();
2017 __ cmpxchgptr(newval, Address(addr, 0));
2018 }
2019 } else {
2020 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2021 __ lock();
2022 __ cmpxchgl(newval, Address(addr, 0));
2023 }
2024 #ifdef _LP64
2025 } else if (op->code() == lir_cas_long) {
2026 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2027 Register newval = op->new_value()->as_register_lo();
2028 Register cmpval = op->cmp_value()->as_register_lo();
2029 assert(cmpval == rax, "wrong register");
2030 assert(newval != NULL, "new val must be register");
2031 assert(cmpval != newval, "cmp and new values must be in different registers");
2032 assert(cmpval != addr, "cmp and addr must be in different registers");
2033 assert(newval != addr, "new value and addr must be in different registers");
2034 __ lock();
2035 __ cmpxchgq(newval, Address(addr, 0));
2036 #endif // _LP64
2037 } else {
2038 Unimplemented();
2039 }
2040 }
2041
2042 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2043 Assembler::Condition acond, ncond;
2044 switch (condition) {
2045 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2046 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2047 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2048 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2049 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2050 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2051 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2052 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2053 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2054 ShouldNotReachHere();
2055 }
2056
2057 if (opr1->is_cpu_register()) {
2058 reg2reg(opr1, result);
2059 } else if (opr1->is_stack()) {
2060 stack2reg(opr1, result, result->type());
2061 } else if (opr1->is_constant()) {
2062 const2reg(opr1, result, lir_patch_none, NULL);
2063 } else {
2064 ShouldNotReachHere();
2065 }
2066
2067 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2068 // optimized version that does not require a branch
2069 if (opr2->is_single_cpu()) {
2070 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2071 __ cmov(ncond, result->as_register(), opr2->as_register());
2072 } else if (opr2->is_double_cpu()) {
2073 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2074 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2075 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2076 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2077 } else if (opr2->is_single_stack()) {
2078 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2079 } else if (opr2->is_double_stack()) {
2080 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2081 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2082 } else {
2083 ShouldNotReachHere();
2084 }
2085
2086 } else {
2087 Label skip;
2088 __ jcc (acond, skip);
2089 if (opr2->is_cpu_register()) {
2090 reg2reg(opr2, result);
2091 } else if (opr2->is_stack()) {
2092 stack2reg(opr2, result, result->type());
2093 } else if (opr2->is_constant()) {
2094 const2reg(opr2, result, lir_patch_none, NULL);
2095 } else {
2096 ShouldNotReachHere();
2097 }
2098 __ bind(skip);
2099 }
2100 }
2101
2102
2103 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2104 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2105
2106 if (left->is_single_cpu()) {
2107 assert(left == dest, "left and dest must be equal");
2108 Register lreg = left->as_register();
2109
2110 if (right->is_single_cpu()) {
2111 // cpu register - cpu register
2112 Register rreg = right->as_register();
2113 switch (code) {
2114 case lir_add: __ addl (lreg, rreg); break;
2115 case lir_sub: __ subl (lreg, rreg); break;
2116 case lir_mul: __ imull(lreg, rreg); break;
2117 default: ShouldNotReachHere();
2118 }
2119
2120 } else if (right->is_stack()) {
2121 // cpu register - stack
2122 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2123 switch (code) {
2124 case lir_add: __ addl(lreg, raddr); break;
2125 case lir_sub: __ subl(lreg, raddr); break;
2126 default: ShouldNotReachHere();
2127 }
2128
2129 } else if (right->is_constant()) {
2130 // cpu register - constant
2131 jint c = right->as_constant_ptr()->as_jint();
2132 switch (code) {
2133 case lir_add: {
2134 __ incrementl(lreg, c);
2135 break;
2136 }
2137 case lir_sub: {
2138 __ decrementl(lreg, c);
2139 break;
2140 }
2141 default: ShouldNotReachHere();
2142 }
2143
2144 } else {
2145 ShouldNotReachHere();
2146 }
2147
2148 } else if (left->is_double_cpu()) {
2149 assert(left == dest, "left and dest must be equal");
2150 Register lreg_lo = left->as_register_lo();
2151 Register lreg_hi = left->as_register_hi();
2152
2153 if (right->is_double_cpu()) {
2154 // cpu register - cpu register
2155 Register rreg_lo = right->as_register_lo();
2156 Register rreg_hi = right->as_register_hi();
2157 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2158 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2159 switch (code) {
2160 case lir_add:
2161 __ addptr(lreg_lo, rreg_lo);
2162 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2163 break;
2164 case lir_sub:
2165 __ subptr(lreg_lo, rreg_lo);
2166 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2167 break;
2168 case lir_mul:
2169 #ifdef _LP64
2170 __ imulq(lreg_lo, rreg_lo);
2171 #else
2172 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2173 __ imull(lreg_hi, rreg_lo);
2174 __ imull(rreg_hi, lreg_lo);
2175 __ addl (rreg_hi, lreg_hi);
2176 __ mull (rreg_lo);
2177 __ addl (lreg_hi, rreg_hi);
2178 #endif // _LP64
2179 break;
2180 default:
2181 ShouldNotReachHere();
2182 }
2183
2184 } else if (right->is_constant()) {
2185 // cpu register - constant
2186 #ifdef _LP64
2187 jlong c = right->as_constant_ptr()->as_jlong_bits();
2188 __ movptr(r10, (intptr_t) c);
2189 switch (code) {
2190 case lir_add:
2191 __ addptr(lreg_lo, r10);
2192 break;
2193 case lir_sub:
2194 __ subptr(lreg_lo, r10);
2195 break;
2196 default:
2197 ShouldNotReachHere();
2198 }
2199 #else
2200 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2201 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2202 switch (code) {
2203 case lir_add:
2204 __ addptr(lreg_lo, c_lo);
2205 __ adcl(lreg_hi, c_hi);
2206 break;
2207 case lir_sub:
2208 __ subptr(lreg_lo, c_lo);
2209 __ sbbl(lreg_hi, c_hi);
2210 break;
2211 default:
2212 ShouldNotReachHere();
2213 }
2214 #endif // _LP64
2215
2216 } else {
2217 ShouldNotReachHere();
2218 }
2219
2220 } else if (left->is_single_xmm()) {
2221 assert(left == dest, "left and dest must be equal");
2222 XMMRegister lreg = left->as_xmm_float_reg();
2223
2224 if (right->is_single_xmm()) {
2225 XMMRegister rreg = right->as_xmm_float_reg();
2226 switch (code) {
2227 case lir_add: __ addss(lreg, rreg); break;
2228 case lir_sub: __ subss(lreg, rreg); break;
2229 case lir_mul_strictfp: // fall through
2230 case lir_mul: __ mulss(lreg, rreg); break;
2231 case lir_div_strictfp: // fall through
2232 case lir_div: __ divss(lreg, rreg); break;
2233 default: ShouldNotReachHere();
2234 }
2235 } else {
2236 Address raddr;
2237 if (right->is_single_stack()) {
2238 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2239 } else if (right->is_constant()) {
2240 // hack for now
2241 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2242 } else {
2243 ShouldNotReachHere();
2244 }
2245 switch (code) {
2246 case lir_add: __ addss(lreg, raddr); break;
2247 case lir_sub: __ subss(lreg, raddr); break;
2248 case lir_mul_strictfp: // fall through
2249 case lir_mul: __ mulss(lreg, raddr); break;
2250 case lir_div_strictfp: // fall through
2251 case lir_div: __ divss(lreg, raddr); break;
2252 default: ShouldNotReachHere();
2253 }
2254 }
2255
2256 } else if (left->is_double_xmm()) {
2257 assert(left == dest, "left and dest must be equal");
2258
2259 XMMRegister lreg = left->as_xmm_double_reg();
2260 if (right->is_double_xmm()) {
2261 XMMRegister rreg = right->as_xmm_double_reg();
2262 switch (code) {
2263 case lir_add: __ addsd(lreg, rreg); break;
2264 case lir_sub: __ subsd(lreg, rreg); break;
2265 case lir_mul_strictfp: // fall through
2266 case lir_mul: __ mulsd(lreg, rreg); break;
2267 case lir_div_strictfp: // fall through
2268 case lir_div: __ divsd(lreg, rreg); break;
2269 default: ShouldNotReachHere();
2270 }
2271 } else {
2272 Address raddr;
2273 if (right->is_double_stack()) {
2274 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2275 } else if (right->is_constant()) {
2276 // hack for now
2277 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2278 } else {
2279 ShouldNotReachHere();
2280 }
2281 switch (code) {
2282 case lir_add: __ addsd(lreg, raddr); break;
2283 case lir_sub: __ subsd(lreg, raddr); break;
2284 case lir_mul_strictfp: // fall through
2285 case lir_mul: __ mulsd(lreg, raddr); break;
2286 case lir_div_strictfp: // fall through
2287 case lir_div: __ divsd(lreg, raddr); break;
2288 default: ShouldNotReachHere();
2289 }
2290 }
2291
2292 #ifndef _LP64
2293 } else if (left->is_single_fpu()) {
2294 assert(dest->is_single_fpu(), "fpu stack allocation required");
2295
2296 if (right->is_single_fpu()) {
2297 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2298
2299 } else {
2300 assert(left->fpu_regnr() == 0, "left must be on TOS");
2301 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2302
2303 Address raddr;
2304 if (right->is_single_stack()) {
2305 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2306 } else if (right->is_constant()) {
2307 address const_addr = float_constant(right->as_jfloat());
2308 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2309 // hack for now
2310 raddr = __ as_Address(InternalAddress(const_addr));
2311 } else {
2312 ShouldNotReachHere();
2313 }
2314
2315 switch (code) {
2316 case lir_add: __ fadd_s(raddr); break;
2317 case lir_sub: __ fsub_s(raddr); break;
2318 case lir_mul_strictfp: // fall through
2319 case lir_mul: __ fmul_s(raddr); break;
2320 case lir_div_strictfp: // fall through
2321 case lir_div: __ fdiv_s(raddr); break;
2322 default: ShouldNotReachHere();
2323 }
2324 }
2325
2326 } else if (left->is_double_fpu()) {
2327 assert(dest->is_double_fpu(), "fpu stack allocation required");
2328
2329 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2330 // Double values require special handling for strictfp mul/div on x86
2331 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2332 __ fmulp(left->fpu_regnrLo() + 1);
2333 }
2334
2335 if (right->is_double_fpu()) {
2336 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2337
2338 } else {
2339 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2340 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2341
2342 Address raddr;
2343 if (right->is_double_stack()) {
2344 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2345 } else if (right->is_constant()) {
2346 // hack for now
2347 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2348 } else {
2349 ShouldNotReachHere();
2350 }
2351
2352 switch (code) {
2353 case lir_add: __ fadd_d(raddr); break;
2354 case lir_sub: __ fsub_d(raddr); break;
2355 case lir_mul_strictfp: // fall through
2356 case lir_mul: __ fmul_d(raddr); break;
2357 case lir_div_strictfp: // fall through
2358 case lir_div: __ fdiv_d(raddr); break;
2359 default: ShouldNotReachHere();
2360 }
2361 }
2362
2363 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2364 // Double values require special handling for strictfp mul/div on x86
2365 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2366 __ fmulp(dest->fpu_regnrLo() + 1);
2367 }
2368 #endif // !_LP64
2369
2370 } else if (left->is_single_stack() || left->is_address()) {
2371 assert(left == dest, "left and dest must be equal");
2372
2373 Address laddr;
2374 if (left->is_single_stack()) {
2375 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2376 } else if (left->is_address()) {
2377 laddr = as_Address(left->as_address_ptr());
2378 } else {
2379 ShouldNotReachHere();
2380 }
2381
2382 if (right->is_single_cpu()) {
2383 Register rreg = right->as_register();
2384 switch (code) {
2385 case lir_add: __ addl(laddr, rreg); break;
2386 case lir_sub: __ subl(laddr, rreg); break;
2387 default: ShouldNotReachHere();
2388 }
2389 } else if (right->is_constant()) {
2390 jint c = right->as_constant_ptr()->as_jint();
2391 switch (code) {
2392 case lir_add: {
2393 __ incrementl(laddr, c);
2394 break;
2395 }
2396 case lir_sub: {
2397 __ decrementl(laddr, c);
2398 break;
2399 }
2400 default: ShouldNotReachHere();
2401 }
2402 } else {
2403 ShouldNotReachHere();
2404 }
2405
2406 } else {
2407 ShouldNotReachHere();
2408 }
2409 }
2410
2411 #ifndef _LP64
2412 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2413 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2414 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2415 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2416
2417 bool left_is_tos = (left_index == 0);
2418 bool dest_is_tos = (dest_index == 0);
2419 int non_tos_index = (left_is_tos ? right_index : left_index);
2420
2421 switch (code) {
2422 case lir_add:
2423 if (pop_fpu_stack) __ faddp(non_tos_index);
2424 else if (dest_is_tos) __ fadd (non_tos_index);
2425 else __ fadda(non_tos_index);
2426 break;
2427
2428 case lir_sub:
2429 if (left_is_tos) {
2430 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2431 else if (dest_is_tos) __ fsub (non_tos_index);
2432 else __ fsubra(non_tos_index);
2433 } else {
2434 if (pop_fpu_stack) __ fsubp (non_tos_index);
2435 else if (dest_is_tos) __ fsubr (non_tos_index);
2436 else __ fsuba (non_tos_index);
2437 }
2438 break;
2439
2440 case lir_mul_strictfp: // fall through
2441 case lir_mul:
2442 if (pop_fpu_stack) __ fmulp(non_tos_index);
2443 else if (dest_is_tos) __ fmul (non_tos_index);
2444 else __ fmula(non_tos_index);
2445 break;
2446
2447 case lir_div_strictfp: // fall through
2448 case lir_div:
2449 if (left_is_tos) {
2450 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2451 else if (dest_is_tos) __ fdiv (non_tos_index);
2452 else __ fdivra(non_tos_index);
2453 } else {
2454 if (pop_fpu_stack) __ fdivp (non_tos_index);
2455 else if (dest_is_tos) __ fdivr (non_tos_index);
2456 else __ fdiva (non_tos_index);
2457 }
2458 break;
2459
2460 case lir_rem:
2461 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2462 __ fremr(noreg);
2463 break;
2464
2465 default:
2466 ShouldNotReachHere();
2467 }
2468 }
2469 #endif // _LP64
2470
2471
2472 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2473 if (value->is_double_xmm()) {
2474 switch(code) {
2475 case lir_abs :
2476 {
2477 #ifdef _LP64
2478 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2479 assert(tmp->is_valid(), "need temporary");
2480 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2481 } else
2482 #endif
2483 {
2484 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2485 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2486 }
2487 assert(!tmp->is_valid(), "do not need temporary");
2488 __ andpd(dest->as_xmm_double_reg(),
2489 ExternalAddress((address)double_signmask_pool));
2490 }
2491 }
2492 break;
2493
2494 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2495 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2496 default : ShouldNotReachHere();
2497 }
2498
2499 #ifndef _LP64
2500 } else if (value->is_double_fpu()) {
2501 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2502 switch(code) {
2503 case lir_abs : __ fabs() ; break;
2504 case lir_sqrt : __ fsqrt(); break;
2505 default : ShouldNotReachHere();
2506 }
2507 #endif // !_LP64
2508 } else {
2509 Unimplemented();
2510 }
2511 }
2512
2513 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2514 // assert(left->destroys_register(), "check");
2515 if (left->is_single_cpu()) {
2516 Register reg = left->as_register();
2517 if (right->is_constant()) {
2518 int val = right->as_constant_ptr()->as_jint();
2519 switch (code) {
2520 case lir_logic_and: __ andl (reg, val); break;
2521 case lir_logic_or: __ orl (reg, val); break;
2522 case lir_logic_xor: __ xorl (reg, val); break;
2523 default: ShouldNotReachHere();
2524 }
2525 } else if (right->is_stack()) {
2526 // added support for stack operands
2527 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2528 switch (code) {
2529 case lir_logic_and: __ andl (reg, raddr); break;
2530 case lir_logic_or: __ orl (reg, raddr); break;
2531 case lir_logic_xor: __ xorl (reg, raddr); break;
2532 default: ShouldNotReachHere();
2533 }
2534 } else {
2535 Register rright = right->as_register();
2536 switch (code) {
2537 case lir_logic_and: __ andptr (reg, rright); break;
2538 case lir_logic_or : __ orptr (reg, rright); break;
2539 case lir_logic_xor: __ xorptr (reg, rright); break;
2540 default: ShouldNotReachHere();
2541 }
2542 }
2543 move_regs(reg, dst->as_register());
2544 } else {
2545 Register l_lo = left->as_register_lo();
2546 Register l_hi = left->as_register_hi();
2547 if (right->is_constant()) {
2548 #ifdef _LP64
2549 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2550 switch (code) {
2551 case lir_logic_and:
2552 __ andq(l_lo, rscratch1);
2553 break;
2554 case lir_logic_or:
2555 __ orq(l_lo, rscratch1);
2556 break;
2557 case lir_logic_xor:
2558 __ xorq(l_lo, rscratch1);
2559 break;
2560 default: ShouldNotReachHere();
2561 }
2562 #else
2563 int r_lo = right->as_constant_ptr()->as_jint_lo();
2564 int r_hi = right->as_constant_ptr()->as_jint_hi();
2565 switch (code) {
2566 case lir_logic_and:
2567 __ andl(l_lo, r_lo);
2568 __ andl(l_hi, r_hi);
2569 break;
2570 case lir_logic_or:
2571 __ orl(l_lo, r_lo);
2572 __ orl(l_hi, r_hi);
2573 break;
2574 case lir_logic_xor:
2575 __ xorl(l_lo, r_lo);
2576 __ xorl(l_hi, r_hi);
2577 break;
2578 default: ShouldNotReachHere();
2579 }
2580 #endif // _LP64
2581 } else {
2582 #ifdef _LP64
2583 Register r_lo;
2584 if (is_reference_type(right->type())) {
2585 r_lo = right->as_register();
2586 } else {
2587 r_lo = right->as_register_lo();
2588 }
2589 #else
2590 Register r_lo = right->as_register_lo();
2591 Register r_hi = right->as_register_hi();
2592 assert(l_lo != r_hi, "overwriting registers");
2593 #endif
2594 switch (code) {
2595 case lir_logic_and:
2596 __ andptr(l_lo, r_lo);
2597 NOT_LP64(__ andptr(l_hi, r_hi);)
2598 break;
2599 case lir_logic_or:
2600 __ orptr(l_lo, r_lo);
2601 NOT_LP64(__ orptr(l_hi, r_hi);)
2602 break;
2603 case lir_logic_xor:
2604 __ xorptr(l_lo, r_lo);
2605 NOT_LP64(__ xorptr(l_hi, r_hi);)
2606 break;
2607 default: ShouldNotReachHere();
2608 }
2609 }
2610
2611 Register dst_lo = dst->as_register_lo();
2612 Register dst_hi = dst->as_register_hi();
2613
2614 #ifdef _LP64
2615 move_regs(l_lo, dst_lo);
2616 #else
2617 if (dst_lo == l_hi) {
2618 assert(dst_hi != l_lo, "overwriting registers");
2619 move_regs(l_hi, dst_hi);
2620 move_regs(l_lo, dst_lo);
2621 } else {
2622 assert(dst_lo != l_hi, "overwriting registers");
2623 move_regs(l_lo, dst_lo);
2624 move_regs(l_hi, dst_hi);
2625 }
2626 #endif // _LP64
2627 }
2628 }
2629
2630
2631 // we assume that rax, and rdx can be overwritten
2632 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2633
2634 assert(left->is_single_cpu(), "left must be register");
2635 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2636 assert(result->is_single_cpu(), "result must be register");
2637
2638 // assert(left->destroys_register(), "check");
2639 // assert(right->destroys_register(), "check");
2640
2641 Register lreg = left->as_register();
2642 Register dreg = result->as_register();
2643
2644 if (right->is_constant()) {
2645 jint divisor = right->as_constant_ptr()->as_jint();
2646 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2647 if (code == lir_idiv) {
2648 assert(lreg == rax, "must be rax,");
2649 assert(temp->as_register() == rdx, "tmp register must be rdx");
2650 __ cdql(); // sign extend into rdx:rax
2651 if (divisor == 2) {
2652 __ subl(lreg, rdx);
2653 } else {
2654 __ andl(rdx, divisor - 1);
2655 __ addl(lreg, rdx);
2656 }
2657 __ sarl(lreg, log2_jint(divisor));
2658 move_regs(lreg, dreg);
2659 } else if (code == lir_irem) {
2660 Label done;
2661 __ mov(dreg, lreg);
2662 __ andl(dreg, 0x80000000 | (divisor - 1));
2663 __ jcc(Assembler::positive, done);
2664 __ decrement(dreg);
2665 __ orl(dreg, ~(divisor - 1));
2666 __ increment(dreg);
2667 __ bind(done);
2668 } else {
2669 ShouldNotReachHere();
2670 }
2671 } else {
2672 Register rreg = right->as_register();
2673 assert(lreg == rax, "left register must be rax,");
2674 assert(rreg != rdx, "right register must not be rdx");
2675 assert(temp->as_register() == rdx, "tmp register must be rdx");
2676
2677 move_regs(lreg, rax);
2678
2679 int idivl_offset = __ corrected_idivl(rreg);
2680 if (ImplicitDiv0Checks) {
2681 add_debug_info_for_div0(idivl_offset, info);
2682 }
2683 if (code == lir_irem) {
2684 move_regs(rdx, dreg); // result is in rdx
2685 } else {
2686 move_regs(rax, dreg);
2687 }
2688 }
2689 }
2690
2691
2692 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2693 if (opr1->is_single_cpu()) {
2694 Register reg1 = opr1->as_register();
2695 if (opr2->is_single_cpu()) {
2696 // cpu register - cpu register
2697 if (is_reference_type(opr1->type())) {
2698 __ cmpoop(reg1, opr2->as_register());
2699 } else {
2700 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2701 __ cmpl(reg1, opr2->as_register());
2702 }
2703 } else if (opr2->is_stack()) {
2704 // cpu register - stack
2705 if (is_reference_type(opr1->type())) {
2706 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2707 } else {
2708 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2709 }
2710 } else if (opr2->is_constant()) {
2711 // cpu register - constant
2712 LIR_Const* c = opr2->as_constant_ptr();
2713 if (c->type() == T_INT) {
2714 __ cmpl(reg1, c->as_jint());
2715 } else if (c->type() == T_METADATA) {
2716 // All we need for now is a comparison with NULL for equality.
2717 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2718 Metadata* m = c->as_metadata();
2719 if (m == NULL) {
2720 __ cmpptr(reg1, (int32_t)0);
2721 } else {
2722 ShouldNotReachHere();
2723 }
2724 } else if (is_reference_type(c->type())) {
2725 // In 64bit oops are single register
2726 jobject o = c->as_jobject();
2727 if (o == NULL) {
2728 __ cmpptr(reg1, (int32_t)NULL_WORD);
2729 } else {
2730 __ cmpoop(reg1, o);
2731 }
2732 } else {
2733 fatal("unexpected type: %s", basictype_to_str(c->type()));
2734 }
2735 // cpu register - address
2736 } else if (opr2->is_address()) {
2737 if (op->info() != NULL) {
2738 add_debug_info_for_null_check_here(op->info());
2739 }
2740 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2741 } else {
2742 ShouldNotReachHere();
2743 }
2744
2745 } else if(opr1->is_double_cpu()) {
2746 Register xlo = opr1->as_register_lo();
2747 Register xhi = opr1->as_register_hi();
2748 if (opr2->is_double_cpu()) {
2749 #ifdef _LP64
2750 __ cmpptr(xlo, opr2->as_register_lo());
2751 #else
2752 // cpu register - cpu register
2753 Register ylo = opr2->as_register_lo();
2754 Register yhi = opr2->as_register_hi();
2755 __ subl(xlo, ylo);
2756 __ sbbl(xhi, yhi);
2757 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2758 __ orl(xhi, xlo);
2759 }
2760 #endif // _LP64
2761 } else if (opr2->is_constant()) {
2762 // cpu register - constant 0
2763 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2764 #ifdef _LP64
2765 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2766 #else
2767 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2768 __ orl(xhi, xlo);
2769 #endif // _LP64
2770 } else {
2771 ShouldNotReachHere();
2772 }
2773
2774 } else if (opr1->is_single_xmm()) {
2775 XMMRegister reg1 = opr1->as_xmm_float_reg();
2776 if (opr2->is_single_xmm()) {
2777 // xmm register - xmm register
2778 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2779 } else if (opr2->is_stack()) {
2780 // xmm register - stack
2781 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2782 } else if (opr2->is_constant()) {
2783 // xmm register - constant
2784 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2785 } else if (opr2->is_address()) {
2786 // xmm register - address
2787 if (op->info() != NULL) {
2788 add_debug_info_for_null_check_here(op->info());
2789 }
2790 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2791 } else {
2792 ShouldNotReachHere();
2793 }
2794
2795 } else if (opr1->is_double_xmm()) {
2796 XMMRegister reg1 = opr1->as_xmm_double_reg();
2797 if (opr2->is_double_xmm()) {
2798 // xmm register - xmm register
2799 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2800 } else if (opr2->is_stack()) {
2801 // xmm register - stack
2802 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2803 } else if (opr2->is_constant()) {
2804 // xmm register - constant
2805 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2806 } else if (opr2->is_address()) {
2807 // xmm register - address
2808 if (op->info() != NULL) {
2809 add_debug_info_for_null_check_here(op->info());
2810 }
2811 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2812 } else {
2813 ShouldNotReachHere();
2814 }
2815
2816 #ifndef _LP64
2817 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2818 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2819 assert(opr2->is_fpu_register(), "both must be registers");
2820 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2821 #endif // LP64
2822
2823 } else if (opr1->is_address() && opr2->is_constant()) {
2824 LIR_Const* c = opr2->as_constant_ptr();
2825 #ifdef _LP64
2826 if (is_reference_type(c->type())) {
2827 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2828 __ movoop(rscratch1, c->as_jobject());
2829 }
2830 #endif // LP64
2831 if (op->info() != NULL) {
2832 add_debug_info_for_null_check_here(op->info());
2833 }
2834 // special case: address - constant
2835 LIR_Address* addr = opr1->as_address_ptr();
2836 if (c->type() == T_INT) {
2837 __ cmpl(as_Address(addr), c->as_jint());
2838 } else if (is_reference_type(c->type())) {
2839 #ifdef _LP64
2840 // %%% Make this explode if addr isn't reachable until we figure out a
2841 // better strategy by giving noreg as the temp for as_Address
2842 __ cmpoop(rscratch1, as_Address(addr, noreg));
2843 #else
2844 __ cmpoop(as_Address(addr), c->as_jobject());
2845 #endif // _LP64
2846 } else {
2847 ShouldNotReachHere();
2848 }
2849
2850 } else {
2851 ShouldNotReachHere();
2852 }
2853 }
2854
2855 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2856 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2857 if (left->is_single_xmm()) {
2858 assert(right->is_single_xmm(), "must match");
2859 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2860 } else if (left->is_double_xmm()) {
2861 assert(right->is_double_xmm(), "must match");
2862 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2863
2864 } else {
2865 #ifdef _LP64
2866 ShouldNotReachHere();
2867 #else
2868 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2869 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2870
2871 assert(left->fpu() == 0, "left must be on TOS");
2872 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2873 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2874 #endif // LP64
2875 }
2876 } else {
2877 assert(code == lir_cmp_l2i, "check");
2878 #ifdef _LP64
2879 Label done;
2880 Register dest = dst->as_register();
2881 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2882 __ movl(dest, -1);
2883 __ jccb(Assembler::less, done);
2884 __ set_byte_if_not_zero(dest);
2885 __ movzbl(dest, dest);
2886 __ bind(done);
2887 #else
2888 __ lcmp2int(left->as_register_hi(),
2889 left->as_register_lo(),
2890 right->as_register_hi(),
2891 right->as_register_lo());
2892 move_regs(left->as_register_hi(), dst->as_register());
2893 #endif // _LP64
2894 }
2895 }
2896
2897
2898 void LIR_Assembler::align_call(LIR_Code code) {
2899 // make sure that the displacement word of the call ends up word aligned
2900 int offset = __ offset();
2901 switch (code) {
2902 case lir_static_call:
2903 case lir_optvirtual_call:
2904 case lir_dynamic_call:
2905 offset += NativeCall::displacement_offset;
2906 break;
2907 case lir_icvirtual_call:
2908 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2909 break;
2910 case lir_virtual_call: // currently, sparc-specific for niagara
2911 default: ShouldNotReachHere();
2912 }
2913 __ align(BytesPerWord, offset);
2914 }
2915
2916
2917 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2918 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2919 "must be aligned");
2920 __ call(AddressLiteral(op->addr(), rtype));
2921 add_call_info(code_offset(), op->info());
2922 }
2923
2924
2925 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2926 __ ic_call(op->addr());
2927 add_call_info(code_offset(), op->info());
2928 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2929 "must be aligned");
2930 }
2931
2932
2933 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2934 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2935 ShouldNotReachHere();
2936 }
2937
2938
2939 void LIR_Assembler::emit_static_call_stub() {
2940 address call_pc = __ pc();
2941 address stub = __ start_a_stub(call_stub_size());
2942 if (stub == NULL) {
2943 bailout("static call stub overflow");
2944 return;
2945 }
2946
2947 int start = __ offset();
2948
2949 // make sure that the displacement word of the call ends up word aligned
2950 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2951 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2952 __ mov_metadata(rbx, (Metadata*)NULL);
2953 // must be set to -1 at code generation time
2954 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2955 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2956 __ jump(RuntimeAddress(__ pc()));
2957
2958 if (UseAOT) {
2959 // Trampoline to aot code
2960 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2961 #ifdef _LP64
2962 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2963 #else
2964 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2965 #endif
2966 __ jmp(rax);
2967 }
2968 assert(__ offset() - start <= call_stub_size(), "stub too big");
2969 __ end_a_stub();
2970 }
2971
2972
2973 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2974 assert(exceptionOop->as_register() == rax, "must match");
2975 assert(exceptionPC->as_register() == rdx, "must match");
2976
2977 // exception object is not added to oop map by LinearScan
2978 // (LinearScan assumes that no oops are in fixed registers)
2979 info->add_register_oop(exceptionOop);
2980 Runtime1::StubID unwind_id;
2981
2982 // get current pc information
2983 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2984 int pc_for_athrow_offset = __ offset();
2985 InternalAddress pc_for_athrow(__ pc());
2986 __ lea(exceptionPC->as_register(), pc_for_athrow);
2987 add_call_info(pc_for_athrow_offset, info); // for exception handler
2988
2989 __ verify_not_null_oop(rax);
2990 // search an exception handler (rax: exception oop, rdx: throwing pc)
2991 if (compilation()->has_fpu_code()) {
2992 unwind_id = Runtime1::handle_exception_id;
2993 } else {
2994 unwind_id = Runtime1::handle_exception_nofpu_id;
2995 }
2996 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2997
2998 // enough room for two byte trap
2999 __ nop();
3000 }
3001
3002
3003 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
3004 assert(exceptionOop->as_register() == rax, "must match");
3005
3006 __ jmp(_unwind_handler_entry);
3007 }
3008
3009
3010 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3011
3012 // optimized version for linear scan:
3013 // * count must be already in ECX (guaranteed by LinearScan)
3014 // * left and dest must be equal
3015 // * tmp must be unused
3016 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3017 assert(left == dest, "left and dest must be equal");
3018 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3019
3020 if (left->is_single_cpu()) {
3021 Register value = left->as_register();
3022 assert(value != SHIFT_count, "left cannot be ECX");
3023
3024 switch (code) {
3025 case lir_shl: __ shll(value); break;
3026 case lir_shr: __ sarl(value); break;
3027 case lir_ushr: __ shrl(value); break;
3028 default: ShouldNotReachHere();
3029 }
3030 } else if (left->is_double_cpu()) {
3031 Register lo = left->as_register_lo();
3032 Register hi = left->as_register_hi();
3033 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3034 #ifdef _LP64
3035 switch (code) {
3036 case lir_shl: __ shlptr(lo); break;
3037 case lir_shr: __ sarptr(lo); break;
3038 case lir_ushr: __ shrptr(lo); break;
3039 default: ShouldNotReachHere();
3040 }
3041 #else
3042
3043 switch (code) {
3044 case lir_shl: __ lshl(hi, lo); break;
3045 case lir_shr: __ lshr(hi, lo, true); break;
3046 case lir_ushr: __ lshr(hi, lo, false); break;
3047 default: ShouldNotReachHere();
3048 }
3049 #endif // LP64
3050 } else {
3051 ShouldNotReachHere();
3052 }
3053 }
3054
3055
3056 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3057 if (dest->is_single_cpu()) {
3058 // first move left into dest so that left is not destroyed by the shift
3059 Register value = dest->as_register();
3060 count = count & 0x1F; // Java spec
3061
3062 move_regs(left->as_register(), value);
3063 switch (code) {
3064 case lir_shl: __ shll(value, count); break;
3065 case lir_shr: __ sarl(value, count); break;
3066 case lir_ushr: __ shrl(value, count); break;
3067 default: ShouldNotReachHere();
3068 }
3069 } else if (dest->is_double_cpu()) {
3070 #ifndef _LP64
3071 Unimplemented();
3072 #else
3073 // first move left into dest so that left is not destroyed by the shift
3074 Register value = dest->as_register_lo();
3075 count = count & 0x1F; // Java spec
3076
3077 move_regs(left->as_register_lo(), value);
3078 switch (code) {
3079 case lir_shl: __ shlptr(value, count); break;
3080 case lir_shr: __ sarptr(value, count); break;
3081 case lir_ushr: __ shrptr(value, count); break;
3082 default: ShouldNotReachHere();
3083 }
3084 #endif // _LP64
3085 } else {
3086 ShouldNotReachHere();
3087 }
3088 }
3089
3090
3091 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3092 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3093 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3094 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3095 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3096 }
3097
3098
3099 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3100 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3101 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3102 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3103 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3104 }
3105
3106
3107 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3108 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3109 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3110 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3111 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3112 }
3113
3114
3115 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3116 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3117 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3118 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3119 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3120 }
3121
3122
3123 // This code replaces a call to arraycopy; no exception may
3124 // be thrown in this code, they must be thrown in the System.arraycopy
3125 // activation frame; we could save some checks if this would not be the case
3126 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3127 ciArrayKlass* default_type = op->expected_type();
3128 Register src = op->src()->as_register();
3129 Register dst = op->dst()->as_register();
3130 Register src_pos = op->src_pos()->as_register();
3131 Register dst_pos = op->dst_pos()->as_register();
3132 Register length = op->length()->as_register();
3133 Register tmp = op->tmp()->as_register();
3134
3135 __ resolve(ACCESS_READ, src);
3136 __ resolve(ACCESS_WRITE, dst);
3137
3138 CodeStub* stub = op->stub();
3139 int flags = op->flags();
3140 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3141 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3142
3143 // if we don't know anything, just go through the generic arraycopy
3144 if (default_type == NULL) {
3145 // save outgoing arguments on stack in case call to System.arraycopy is needed
3146 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3147 // for interpreter calling conventions. Now we have to do it in new style conventions.
3148 // For the moment until C1 gets the new register allocator I just force all the
3149 // args to the right place (except the register args) and then on the back side
3150 // reload the register args properly if we go slow path. Yuck
3151
3152 // These are proper for the calling convention
3153 store_parameter(length, 2);
3154 store_parameter(dst_pos, 1);
3155 store_parameter(dst, 0);
3156
3157 // these are just temporary placements until we need to reload
3158 store_parameter(src_pos, 3);
3159 store_parameter(src, 4);
3160 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3161
3162 address copyfunc_addr = StubRoutines::generic_arraycopy();
3163 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3164
3165 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3166 #ifdef _LP64
3167 // The arguments are in java calling convention so we can trivially shift them to C
3168 // convention
3169 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3170 __ mov(c_rarg0, j_rarg0);
3171 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3172 __ mov(c_rarg1, j_rarg1);
3173 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3174 __ mov(c_rarg2, j_rarg2);
3175 assert_different_registers(c_rarg3, j_rarg4);
3176 __ mov(c_rarg3, j_rarg3);
3177 #ifdef _WIN64
3178 // Allocate abi space for args but be sure to keep stack aligned
3179 __ subptr(rsp, 6*wordSize);
3180 store_parameter(j_rarg4, 4);
3181 #ifndef PRODUCT
3182 if (PrintC1Statistics) {
3183 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3184 }
3185 #endif
3186 __ call(RuntimeAddress(copyfunc_addr));
3187 __ addptr(rsp, 6*wordSize);
3188 #else
3189 __ mov(c_rarg4, j_rarg4);
3190 #ifndef PRODUCT
3191 if (PrintC1Statistics) {
3192 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3193 }
3194 #endif
3195 __ call(RuntimeAddress(copyfunc_addr));
3196 #endif // _WIN64
3197 #else
3198 __ push(length);
3199 __ push(dst_pos);
3200 __ push(dst);
3201 __ push(src_pos);
3202 __ push(src);
3203
3204 #ifndef PRODUCT
3205 if (PrintC1Statistics) {
3206 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3207 }
3208 #endif
3209 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3210
3211 #endif // _LP64
3212
3213 __ cmpl(rax, 0);
3214 __ jcc(Assembler::equal, *stub->continuation());
3215
3216 __ mov(tmp, rax);
3217 __ xorl(tmp, -1);
3218
3219 // Reload values from the stack so they are where the stub
3220 // expects them.
3221 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3222 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3223 __ movptr (length, Address(rsp, 2*BytesPerWord));
3224 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3225 __ movptr (src, Address(rsp, 4*BytesPerWord));
3226
3227 __ subl(length, tmp);
3228 __ addl(src_pos, tmp);
3229 __ addl(dst_pos, tmp);
3230 __ jmp(*stub->entry());
3231
3232 __ bind(*stub->continuation());
3233 return;
3234 }
3235
3236 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3237
3238 int elem_size = type2aelembytes(basic_type);
3239 Address::ScaleFactor scale;
3240
3241 switch (elem_size) {
3242 case 1 :
3243 scale = Address::times_1;
3244 break;
3245 case 2 :
3246 scale = Address::times_2;
3247 break;
3248 case 4 :
3249 scale = Address::times_4;
3250 break;
3251 case 8 :
3252 scale = Address::times_8;
3253 break;
3254 default:
3255 scale = Address::no_scale;
3256 ShouldNotReachHere();
3257 }
3258
3259 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3260 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3261 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3262 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3263
3264 // length and pos's are all sign extended at this point on 64bit
3265
3266 // test for NULL
3267 if (flags & LIR_OpArrayCopy::src_null_check) {
3268 __ testptr(src, src);
3269 __ jcc(Assembler::zero, *stub->entry());
3270 }
3271 if (flags & LIR_OpArrayCopy::dst_null_check) {
3272 __ testptr(dst, dst);
3273 __ jcc(Assembler::zero, *stub->entry());
3274 }
3275
3276 // If the compiler was not able to prove that exact type of the source or the destination
3277 // of the arraycopy is an array type, check at runtime if the source or the destination is
3278 // an instance type.
3279 if (flags & LIR_OpArrayCopy::type_check) {
3280 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3281 __ load_klass(tmp, dst);
3282 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3283 __ jcc(Assembler::greaterEqual, *stub->entry());
3284 }
3285
3286 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3287 __ load_klass(tmp, src);
3288 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3289 __ jcc(Assembler::greaterEqual, *stub->entry());
3290 }
3291 }
3292
3293 // check if negative
3294 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3295 __ testl(src_pos, src_pos);
3296 __ jcc(Assembler::less, *stub->entry());
3297 }
3298 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3299 __ testl(dst_pos, dst_pos);
3300 __ jcc(Assembler::less, *stub->entry());
3301 }
3302
3303 if (flags & LIR_OpArrayCopy::src_range_check) {
3304 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3305 __ cmpl(tmp, src_length_addr);
3306 __ jcc(Assembler::above, *stub->entry());
3307 }
3308 if (flags & LIR_OpArrayCopy::dst_range_check) {
3309 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3310 __ cmpl(tmp, dst_length_addr);
3311 __ jcc(Assembler::above, *stub->entry());
3312 }
3313
3314 if (flags & LIR_OpArrayCopy::length_positive_check) {
3315 __ testl(length, length);
3316 __ jcc(Assembler::less, *stub->entry());
3317 }
3318
3319 #ifdef _LP64
3320 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3321 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3322 #endif
3323
3324 if (flags & LIR_OpArrayCopy::type_check) {
3325 // We don't know the array types are compatible
3326 if (basic_type != T_OBJECT) {
3327 // Simple test for basic type arrays
3328 if (UseCompressedClassPointers) {
3329 __ movl(tmp, src_klass_addr);
3330 __ cmpl(tmp, dst_klass_addr);
3331 } else {
3332 __ movptr(tmp, src_klass_addr);
3333 __ cmpptr(tmp, dst_klass_addr);
3334 }
3335 __ jcc(Assembler::notEqual, *stub->entry());
3336 } else {
3337 // For object arrays, if src is a sub class of dst then we can
3338 // safely do the copy.
3339 Label cont, slow;
3340
3341 __ push(src);
3342 __ push(dst);
3343
3344 __ load_klass(src, src);
3345 __ load_klass(dst, dst);
3346
3347 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3348
3349 __ push(src);
3350 __ push(dst);
3351 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3352 __ pop(dst);
3353 __ pop(src);
3354
3355 __ cmpl(src, 0);
3356 __ jcc(Assembler::notEqual, cont);
3357
3358 __ bind(slow);
3359 __ pop(dst);
3360 __ pop(src);
3361
3362 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3363 if (copyfunc_addr != NULL) { // use stub if available
3364 // src is not a sub class of dst so we have to do a
3365 // per-element check.
3366
3367 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3368 if ((flags & mask) != mask) {
3369 // Check that at least both of them object arrays.
3370 assert(flags & mask, "one of the two should be known to be an object array");
3371
3372 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3373 __ load_klass(tmp, src);
3374 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3375 __ load_klass(tmp, dst);
3376 }
3377 int lh_offset = in_bytes(Klass::layout_helper_offset());
3378 Address klass_lh_addr(tmp, lh_offset);
3379 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3380 __ cmpl(klass_lh_addr, objArray_lh);
3381 __ jcc(Assembler::notEqual, *stub->entry());
3382 }
3383
3384 // Spill because stubs can use any register they like and it's
3385 // easier to restore just those that we care about.
3386 store_parameter(dst, 0);
3387 store_parameter(dst_pos, 1);
3388 store_parameter(length, 2);
3389 store_parameter(src_pos, 3);
3390 store_parameter(src, 4);
3391
3392 #ifndef _LP64
3393 __ movptr(tmp, dst_klass_addr);
3394 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3395 __ push(tmp);
3396 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3397 __ push(tmp);
3398 __ push(length);
3399 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3400 __ push(tmp);
3401 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3402 __ push(tmp);
3403
3404 __ call_VM_leaf(copyfunc_addr, 5);
3405 #else
3406 __ movl2ptr(length, length); //higher 32bits must be null
3407
3408 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3409 assert_different_registers(c_rarg0, dst, dst_pos, length);
3410 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3411 assert_different_registers(c_rarg1, dst, length);
3412
3413 __ mov(c_rarg2, length);
3414 assert_different_registers(c_rarg2, dst);
3415
3416 #ifdef _WIN64
3417 // Allocate abi space for args but be sure to keep stack aligned
3418 __ subptr(rsp, 6*wordSize);
3419 __ load_klass(c_rarg3, dst);
3420 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3421 store_parameter(c_rarg3, 4);
3422 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3423 __ call(RuntimeAddress(copyfunc_addr));
3424 __ addptr(rsp, 6*wordSize);
3425 #else
3426 __ load_klass(c_rarg4, dst);
3427 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3428 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3429 __ call(RuntimeAddress(copyfunc_addr));
3430 #endif
3431
3432 #endif
3433
3434 #ifndef PRODUCT
3435 if (PrintC1Statistics) {
3436 Label failed;
3437 __ testl(rax, rax);
3438 __ jcc(Assembler::notZero, failed);
3439 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3440 __ bind(failed);
3441 }
3442 #endif
3443
3444 __ testl(rax, rax);
3445 __ jcc(Assembler::zero, *stub->continuation());
3446
3447 #ifndef PRODUCT
3448 if (PrintC1Statistics) {
3449 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3450 }
3451 #endif
3452
3453 __ mov(tmp, rax);
3454
3455 __ xorl(tmp, -1);
3456
3457 // Restore previously spilled arguments
3458 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3459 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3460 __ movptr (length, Address(rsp, 2*BytesPerWord));
3461 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3462 __ movptr (src, Address(rsp, 4*BytesPerWord));
3463
3464
3465 __ subl(length, tmp);
3466 __ addl(src_pos, tmp);
3467 __ addl(dst_pos, tmp);
3468 }
3469
3470 __ jmp(*stub->entry());
3471
3472 __ bind(cont);
3473 __ pop(dst);
3474 __ pop(src);
3475 }
3476 }
3477
3478 #ifdef ASSERT
3479 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3480 // Sanity check the known type with the incoming class. For the
3481 // primitive case the types must match exactly with src.klass and
3482 // dst.klass each exactly matching the default type. For the
3483 // object array case, if no type check is needed then either the
3484 // dst type is exactly the expected type and the src type is a
3485 // subtype which we can't check or src is the same array as dst
3486 // but not necessarily exactly of type default_type.
3487 Label known_ok, halt;
3488 __ mov_metadata(tmp, default_type->constant_encoding());
3489 #ifdef _LP64
3490 if (UseCompressedClassPointers) {
3491 __ encode_klass_not_null(tmp);
3492 }
3493 #endif
3494
3495 if (basic_type != T_OBJECT) {
3496
3497 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3498 else __ cmpptr(tmp, dst_klass_addr);
3499 __ jcc(Assembler::notEqual, halt);
3500 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3501 else __ cmpptr(tmp, src_klass_addr);
3502 __ jcc(Assembler::equal, known_ok);
3503 } else {
3504 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3505 else __ cmpptr(tmp, dst_klass_addr);
3506 __ jcc(Assembler::equal, known_ok);
3507 __ cmpptr(src, dst);
3508 __ jcc(Assembler::equal, known_ok);
3509 }
3510 __ bind(halt);
3511 __ stop("incorrect type information in arraycopy");
3512 __ bind(known_ok);
3513 }
3514 #endif
3515
3516 #ifndef PRODUCT
3517 if (PrintC1Statistics) {
3518 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3519 }
3520 #endif
3521
3522 #ifdef _LP64
3523 assert_different_registers(c_rarg0, dst, dst_pos, length);
3524 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3525 assert_different_registers(c_rarg1, length);
3526 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3527 __ mov(c_rarg2, length);
3528
3529 #else
3530 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3531 store_parameter(tmp, 0);
3532 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3533 store_parameter(tmp, 1);
3534 store_parameter(length, 2);
3535 #endif // _LP64
3536
3537 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3538 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3539 const char *name;
3540 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3541 __ call_VM_leaf(entry, 0);
3542
3543 __ bind(*stub->continuation());
3544 }
3545
3546 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3547 assert(op->crc()->is_single_cpu(), "crc must be register");
3548 assert(op->val()->is_single_cpu(), "byte value must be register");
3549 assert(op->result_opr()->is_single_cpu(), "result must be register");
3550 Register crc = op->crc()->as_register();
3551 Register val = op->val()->as_register();
3552 Register res = op->result_opr()->as_register();
3553
3554 assert_different_registers(val, crc, res);
3555
3556 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3557 __ notl(crc); // ~crc
3558 __ update_byte_crc32(crc, val, res);
3559 __ notl(crc); // ~crc
3560 __ mov(res, crc);
3561 }
3562
3563 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3564 Register obj = op->obj_opr()->as_register(); // may not be an oop
3565 Register hdr = op->hdr_opr()->as_register();
3566 Register lock = op->lock_opr()->as_register();
3567 if (!UseFastLocking) {
3568 __ jmp(*op->stub()->entry());
3569 } else if (op->code() == lir_lock) {
3570 Register scratch = noreg;
3571 if (UseBiasedLocking) {
3572 scratch = op->scratch_opr()->as_register();
3573 }
3574 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3575 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3576 // add debug info for NullPointerException only if one is possible
3577 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3578 if (op->info() != NULL) {
3579 add_debug_info_for_null_check(null_check_offset, op->info());
3580 }
3581 // done
3582 } else if (op->code() == lir_unlock) {
3583 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3584 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3585 } else {
3586 Unimplemented();
3587 }
3588 __ bind(*op->stub()->continuation());
3589 }
3590
3591
3592 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3593 ciMethod* method = op->profiled_method();
3594 int bci = op->profiled_bci();
3595 ciMethod* callee = op->profiled_callee();
3596
3597 // Update counter for all call types
3598 ciMethodData* md = method->method_data_or_null();
3599 assert(md != NULL, "Sanity");
3600 ciProfileData* data = md->bci_to_data(bci);
3601 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3602 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3603 Register mdo = op->mdo()->as_register();
3604 __ mov_metadata(mdo, md->constant_encoding());
3605 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3606 // Perform additional virtual call profiling for invokevirtual and
3607 // invokeinterface bytecodes
3608 if (op->should_profile_receiver_type()) {
3609 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3610 Register recv = op->recv()->as_register();
3611 assert_different_registers(mdo, recv);
3612 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3613 ciKlass* known_klass = op->known_holder();
3614 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3615 // We know the type that will be seen at this call site; we can
3616 // statically update the MethodData* rather than needing to do
3617 // dynamic tests on the receiver type
3618
3619 // NOTE: we should probably put a lock around this search to
3620 // avoid collisions by concurrent compilations
3621 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3622 uint i;
3623 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3624 ciKlass* receiver = vc_data->receiver(i);
3625 if (known_klass->equals(receiver)) {
3626 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3627 __ addptr(data_addr, DataLayout::counter_increment);
3628 return;
3629 }
3630 }
3631
3632 // Receiver type not found in profile data; select an empty slot
3633
3634 // Note that this is less efficient than it should be because it
3635 // always does a write to the receiver part of the
3636 // VirtualCallData rather than just the first time
3637 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3638 ciKlass* receiver = vc_data->receiver(i);
3639 if (receiver == NULL) {
3640 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3641 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3642 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3643 __ addptr(data_addr, DataLayout::counter_increment);
3644 return;
3645 }
3646 }
3647 } else {
3648 __ load_klass(recv, recv);
3649 Label update_done;
3650 type_profile_helper(mdo, md, data, recv, &update_done);
3651 // Receiver did not match any saved receiver and there is no empty row for it.
3652 // Increment total counter to indicate polymorphic case.
3653 __ addptr(counter_addr, DataLayout::counter_increment);
3654
3655 __ bind(update_done);
3656 }
3657 } else {
3658 // Static call
3659 __ addptr(counter_addr, DataLayout::counter_increment);
3660 }
3661 }
3662
3663 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3664 Register obj = op->obj()->as_register();
3665 Register tmp = op->tmp()->as_pointer_register();
3666 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3667 ciKlass* exact_klass = op->exact_klass();
3668 intptr_t current_klass = op->current_klass();
3669 bool not_null = op->not_null();
3670 bool no_conflict = op->no_conflict();
3671
3672 Label update, next, none;
3673
3674 bool do_null = !not_null;
3675 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3676 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3677
3678 assert(do_null || do_update, "why are we here?");
3679 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3680
3681 __ verify_oop(obj);
3682
3683 if (tmp != obj) {
3684 __ mov(tmp, obj);
3685 }
3686 if (do_null) {
3687 __ testptr(tmp, tmp);
3688 __ jccb(Assembler::notZero, update);
3689 if (!TypeEntries::was_null_seen(current_klass)) {
3690 __ orptr(mdo_addr, TypeEntries::null_seen);
3691 }
3692 if (do_update) {
3693 #ifndef ASSERT
3694 __ jmpb(next);
3695 }
3696 #else
3697 __ jmp(next);
3698 }
3699 } else {
3700 __ testptr(tmp, tmp);
3701 __ jcc(Assembler::notZero, update);
3702 __ stop("unexpect null obj");
3703 #endif
3704 }
3705
3706 __ bind(update);
3707
3708 if (do_update) {
3709 #ifdef ASSERT
3710 if (exact_klass != NULL) {
3711 Label ok;
3712 __ load_klass(tmp, tmp);
3713 __ push(tmp);
3714 __ mov_metadata(tmp, exact_klass->constant_encoding());
3715 __ cmpptr(tmp, Address(rsp, 0));
3716 __ jcc(Assembler::equal, ok);
3717 __ stop("exact klass and actual klass differ");
3718 __ bind(ok);
3719 __ pop(tmp);
3720 }
3721 #endif
3722 if (!no_conflict) {
3723 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3724 if (exact_klass != NULL) {
3725 __ mov_metadata(tmp, exact_klass->constant_encoding());
3726 } else {
3727 __ load_klass(tmp, tmp);
3728 }
3729
3730 __ xorptr(tmp, mdo_addr);
3731 __ testptr(tmp, TypeEntries::type_klass_mask);
3732 // klass seen before, nothing to do. The unknown bit may have been
3733 // set already but no need to check.
3734 __ jccb(Assembler::zero, next);
3735
3736 __ testptr(tmp, TypeEntries::type_unknown);
3737 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3738
3739 if (TypeEntries::is_type_none(current_klass)) {
3740 __ cmpptr(mdo_addr, 0);
3741 __ jccb(Assembler::equal, none);
3742 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3743 __ jccb(Assembler::equal, none);
3744 // There is a chance that the checks above (re-reading profiling
3745 // data from memory) fail if another thread has just set the
3746 // profiling to this obj's klass
3747 __ xorptr(tmp, mdo_addr);
3748 __ testptr(tmp, TypeEntries::type_klass_mask);
3749 __ jccb(Assembler::zero, next);
3750 }
3751 } else {
3752 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3753 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3754
3755 __ movptr(tmp, mdo_addr);
3756 __ testptr(tmp, TypeEntries::type_unknown);
3757 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3758 }
3759
3760 // different than before. Cannot keep accurate profile.
3761 __ orptr(mdo_addr, TypeEntries::type_unknown);
3762
3763 if (TypeEntries::is_type_none(current_klass)) {
3764 __ jmpb(next);
3765
3766 __ bind(none);
3767 // first time here. Set profile type.
3768 __ movptr(mdo_addr, tmp);
3769 }
3770 } else {
3771 // There's a single possible klass at this profile point
3772 assert(exact_klass != NULL, "should be");
3773 if (TypeEntries::is_type_none(current_klass)) {
3774 __ mov_metadata(tmp, exact_klass->constant_encoding());
3775 __ xorptr(tmp, mdo_addr);
3776 __ testptr(tmp, TypeEntries::type_klass_mask);
3777 #ifdef ASSERT
3778 __ jcc(Assembler::zero, next);
3779
3780 {
3781 Label ok;
3782 __ push(tmp);
3783 __ cmpptr(mdo_addr, 0);
3784 __ jcc(Assembler::equal, ok);
3785 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3786 __ jcc(Assembler::equal, ok);
3787 // may have been set by another thread
3788 __ mov_metadata(tmp, exact_klass->constant_encoding());
3789 __ xorptr(tmp, mdo_addr);
3790 __ testptr(tmp, TypeEntries::type_mask);
3791 __ jcc(Assembler::zero, ok);
3792
3793 __ stop("unexpected profiling mismatch");
3794 __ bind(ok);
3795 __ pop(tmp);
3796 }
3797 #else
3798 __ jccb(Assembler::zero, next);
3799 #endif
3800 // first time here. Set profile type.
3801 __ movptr(mdo_addr, tmp);
3802 } else {
3803 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3804 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3805
3806 __ movptr(tmp, mdo_addr);
3807 __ testptr(tmp, TypeEntries::type_unknown);
3808 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3809
3810 __ orptr(mdo_addr, TypeEntries::type_unknown);
3811 }
3812 }
3813
3814 __ bind(next);
3815 }
3816 }
3817
3818 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3819 Unimplemented();
3820 }
3821
3822
3823 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3824 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3825 }
3826
3827
3828 void LIR_Assembler::align_backward_branch_target() {
3829 __ align(BytesPerWord);
3830 }
3831
3832
3833 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3834 if (left->is_single_cpu()) {
3835 __ negl(left->as_register());
3836 move_regs(left->as_register(), dest->as_register());
3837
3838 } else if (left->is_double_cpu()) {
3839 Register lo = left->as_register_lo();
3840 #ifdef _LP64
3841 Register dst = dest->as_register_lo();
3842 __ movptr(dst, lo);
3843 __ negptr(dst);
3844 #else
3845 Register hi = left->as_register_hi();
3846 __ lneg(hi, lo);
3847 if (dest->as_register_lo() == hi) {
3848 assert(dest->as_register_hi() != lo, "destroying register");
3849 move_regs(hi, dest->as_register_hi());
3850 move_regs(lo, dest->as_register_lo());
3851 } else {
3852 move_regs(lo, dest->as_register_lo());
3853 move_regs(hi, dest->as_register_hi());
3854 }
3855 #endif // _LP64
3856
3857 } else if (dest->is_single_xmm()) {
3858 #ifdef _LP64
3859 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3860 assert(tmp->is_valid(), "need temporary");
3861 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3862 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3863 }
3864 else
3865 #endif
3866 {
3867 assert(!tmp->is_valid(), "do not need temporary");
3868 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3869 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3870 }
3871 __ xorps(dest->as_xmm_float_reg(),
3872 ExternalAddress((address)float_signflip_pool));
3873 }
3874 } else if (dest->is_double_xmm()) {
3875 #ifdef _LP64
3876 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3877 assert(tmp->is_valid(), "need temporary");
3878 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3879 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3880 }
3881 else
3882 #endif
3883 {
3884 assert(!tmp->is_valid(), "do not need temporary");
3885 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3886 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3887 }
3888 __ xorpd(dest->as_xmm_double_reg(),
3889 ExternalAddress((address)double_signflip_pool));
3890 }
3891 #ifndef _LP64
3892 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3893 assert(left->fpu() == 0, "arg must be on TOS");
3894 assert(dest->fpu() == 0, "dest must be TOS");
3895 __ fchs();
3896 #endif // !_LP64
3897
3898 } else {
3899 ShouldNotReachHere();
3900 }
3901 }
3902
3903
3904 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3905 assert(src->is_address(), "must be an address");
3906 assert(dest->is_register(), "must be a register");
3907
3908 PatchingStub* patch = NULL;
3909 if (patch_code != lir_patch_none) {
3910 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3911 }
3912
3913 Register reg = dest->as_pointer_register();
3914 LIR_Address* addr = src->as_address_ptr();
3915 __ lea(reg, as_Address(addr));
3916
3917 if (patch != NULL) {
3918 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3919 }
3920 }
3921
3922
3923
3924 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3925 assert(!tmp->is_valid(), "don't need temporary");
3926 __ call(RuntimeAddress(dest));
3927 if (info != NULL) {
3928 add_call_info_here(info);
3929 }
3930 }
3931
3932
3933 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3934 assert(type == T_LONG, "only for volatile long fields");
3935
3936 if (info != NULL) {
3937 add_debug_info_for_null_check_here(info);
3938 }
3939
3940 if (src->is_double_xmm()) {
3941 if (dest->is_double_cpu()) {
3942 #ifdef _LP64
3943 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3944 #else
3945 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3946 __ psrlq(src->as_xmm_double_reg(), 32);
3947 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3948 #endif // _LP64
3949 } else if (dest->is_double_stack()) {
3950 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3951 } else if (dest->is_address()) {
3952 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3953 } else {
3954 ShouldNotReachHere();
3955 }
3956
3957 } else if (dest->is_double_xmm()) {
3958 if (src->is_double_stack()) {
3959 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3960 } else if (src->is_address()) {
3961 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3962 } else {
3963 ShouldNotReachHere();
3964 }
3965
3966 #ifndef _LP64
3967 } else if (src->is_double_fpu()) {
3968 assert(src->fpu_regnrLo() == 0, "must be TOS");
3969 if (dest->is_double_stack()) {
3970 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3971 } else if (dest->is_address()) {
3972 __ fistp_d(as_Address(dest->as_address_ptr()));
3973 } else {
3974 ShouldNotReachHere();
3975 }
3976
3977 } else if (dest->is_double_fpu()) {
3978 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3979 if (src->is_double_stack()) {
3980 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3981 } else if (src->is_address()) {
3982 __ fild_d(as_Address(src->as_address_ptr()));
3983 } else {
3984 ShouldNotReachHere();
3985 }
3986 #endif // !_LP64
3987
3988 } else {
3989 ShouldNotReachHere();
3990 }
3991 }
3992
3993 #ifdef ASSERT
3994 // emit run-time assertion
3995 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3996 assert(op->code() == lir_assert, "must be");
3997
3998 if (op->in_opr1()->is_valid()) {
3999 assert(op->in_opr2()->is_valid(), "both operands must be valid");
4000 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
4001 } else {
4002 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
4003 assert(op->condition() == lir_cond_always, "no other conditions allowed");
4004 }
4005
4006 Label ok;
4007 if (op->condition() != lir_cond_always) {
4008 Assembler::Condition acond = Assembler::zero;
4009 switch (op->condition()) {
4010 case lir_cond_equal: acond = Assembler::equal; break;
4011 case lir_cond_notEqual: acond = Assembler::notEqual; break;
4012 case lir_cond_less: acond = Assembler::less; break;
4013 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
4014 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
4015 case lir_cond_greater: acond = Assembler::greater; break;
4016 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
4017 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
4018 default: ShouldNotReachHere();
4019 }
4020 __ jcc(acond, ok);
4021 }
4022 if (op->halt()) {
4023 const char* str = __ code_string(op->msg());
4024 __ stop(str);
4025 } else {
4026 breakpoint();
4027 }
4028 __ bind(ok);
4029 }
4030 #endif
4031
4032 void LIR_Assembler::membar() {
4033 // QQQ sparc TSO uses this,
4034 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4035 }
4036
4037 void LIR_Assembler::membar_acquire() {
4038 // No x86 machines currently require load fences
4039 }
4040
4041 void LIR_Assembler::membar_release() {
4042 // No x86 machines currently require store fences
4043 }
4044
4045 void LIR_Assembler::membar_loadload() {
4046 // no-op
4047 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4048 }
4049
4050 void LIR_Assembler::membar_storestore() {
4051 // no-op
4052 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4053 }
4054
4055 void LIR_Assembler::membar_loadstore() {
4056 // no-op
4057 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4058 }
4059
4060 void LIR_Assembler::membar_storeload() {
4061 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4062 }
4063
4064 void LIR_Assembler::on_spin_wait() {
4065 __ pause ();
4066 }
4067
4068 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4069 assert(result_reg->is_register(), "check");
4070 #ifdef _LP64
4071 // __ get_thread(result_reg->as_register_lo());
4072 __ mov(result_reg->as_register(), r15_thread);
4073 #else
4074 __ get_thread(result_reg->as_register());
4075 #endif // _LP64
4076 }
4077
4078
4079 void LIR_Assembler::peephole(LIR_List*) {
4080 // do nothing for now
4081 }
4082
4083 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4084 assert(data == dest, "xchg/xadd uses only 2 operands");
4085
4086 if (data->type() == T_INT) {
4087 if (code == lir_xadd) {
4088 __ lock();
4089 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4090 } else {
4091 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4092 }
4093 } else if (data->is_oop()) {
4094 assert (code == lir_xchg, "xadd for oops");
4095 Register obj = data->as_register();
4096 #ifdef _LP64
4097 if (UseCompressedOops) {
4098 __ encode_heap_oop(obj);
4099 __ xchgl(obj, as_Address(src->as_address_ptr()));
4100 __ decode_heap_oop(obj);
4101 } else {
4102 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4103 }
4104 #else
4105 __ xchgl(obj, as_Address(src->as_address_ptr()));
4106 #endif
4107 } else if (data->type() == T_LONG) {
4108 #ifdef _LP64
4109 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4110 if (code == lir_xadd) {
4111 __ lock();
4112 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4113 } else {
4114 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4115 }
4116 #else
4117 ShouldNotReachHere();
4118 #endif
4119 } else {
4120 ShouldNotReachHere();
4121 }
4122 }
4123
4124 #undef __