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src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
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@@ -158,19 +158,11 @@
} else {
return const_addr;
}
}
-
-void LIR_Assembler::set_24bit_FPU() {
- __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
-}
-
-void LIR_Assembler::reset_FPU() {
- __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
-}
-
+#ifndef _LP64
void LIR_Assembler::fpop() {
__ fpop();
}
void LIR_Assembler::fxch(int i) {
@@ -182,10 +174,11 @@
}
void LIR_Assembler::ffree(int i) {
__ ffree(i);
}
+#endif // !_LP64
void LIR_Assembler::breakpoint() {
__ int3();
}
@@ -670,19 +663,23 @@
} else {
__ movflt(dest->as_xmm_float_reg(),
InternalAddress(float_constant(c->as_jfloat())));
}
} else {
+#ifndef _LP64
assert(dest->is_single_fpu(), "must be");
assert(dest->fpu_regnr() == 0, "dest must be TOS");
if (c->is_zero_float()) {
__ fldz();
} else if (c->is_one_float()) {
__ fld1();
} else {
__ fld_s (InternalAddress(float_constant(c->as_jfloat())));
}
+#else
+ ShouldNotReachHere();
+#endif // !_LP64
}
break;
}
case T_DOUBLE: {
@@ -692,19 +689,23 @@
} else {
__ movdbl(dest->as_xmm_double_reg(),
InternalAddress(double_constant(c->as_jdouble())));
}
} else {
+#ifndef _LP64
assert(dest->is_double_fpu(), "must be");
assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
if (c->is_zero_double()) {
__ fldz();
} else if (c->is_one_double()) {
__ fld1();
} else {
__ fld_d (InternalAddress(double_constant(c->as_jdouble())));
}
+#else
+ ShouldNotReachHere();
+#endif // !_LP64
}
break;
}
default:
@@ -892,10 +893,11 @@
move_regs(f_lo, t_lo);
move_regs(f_hi, t_hi);
}
#endif // LP64
+#ifndef _LP64
// special moves from fpu-register to xmm-register
// necessary for method results
} else if (src->is_single_xmm() && !dest->is_single_xmm()) {
__ movflt(Address(rsp, 0), src->as_xmm_float_reg());
__ fld_s(Address(rsp, 0));
@@ -907,22 +909,24 @@
__ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
} else if (dest->is_double_xmm() && !src->is_double_xmm()) {
__ fstp_d(Address(rsp, 0));
__ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
+ // move between fpu-registers (no instruction necessary because of fpu-stack)
+ } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
+ assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
+ assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
+#endif // !_LP64
+
// move between xmm-registers
} else if (dest->is_single_xmm()) {
assert(src->is_single_xmm(), "must match");
__ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
} else if (dest->is_double_xmm()) {
assert(src->is_double_xmm(), "must match");
__ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
- // move between fpu-registers (no instruction necessary because of fpu-stack)
- } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
- assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
- assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
} else {
ShouldNotReachHere();
}
}
@@ -953,10 +957,11 @@
} else if (src->is_double_xmm()) {
Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
__ movdbl(dst_addr, src->as_xmm_double_reg());
+#ifndef _LP64
} else if (src->is_single_fpu()) {
assert(src->fpu_regnr() == 0, "argument must be on TOS");
Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
if (pop_fpu_stack) __ fstp_s (dst_addr);
else __ fst_s (dst_addr);
@@ -964,10 +969,11 @@
} else if (src->is_double_fpu()) {
assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
if (pop_fpu_stack) __ fstp_d (dst_addr);
else __ fst_d (dst_addr);
+#endif // !_LP64
} else {
ShouldNotReachHere();
}
}
@@ -998,30 +1004,40 @@
}
int null_check_here = code_offset();
switch (type) {
case T_FLOAT: {
+#ifdef _LP64
+ assert(src->is_single_xmm(), "not a float");
+ __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
+#else
if (src->is_single_xmm()) {
__ movflt(as_Address(to_addr), src->as_xmm_float_reg());
} else {
assert(src->is_single_fpu(), "must be");
assert(src->fpu_regnr() == 0, "argument must be on TOS");
if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
else __ fst_s (as_Address(to_addr));
}
+#endif // _LP64
break;
}
case T_DOUBLE: {
+#ifdef _LP64
+ assert(src->is_double_xmm(), "not a double");
+ __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
+#else
if (src->is_double_xmm()) {
__ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
} else {
assert(src->is_double_fpu(), "must be");
assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
else __ fst_d (as_Address(to_addr));
}
+#endif // _LP64
break;
}
case T_ARRAY: // fall through
case T_OBJECT: // fall through
@@ -1134,19 +1150,21 @@
} else if (dest->is_double_xmm()) {
Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
__ movdbl(dest->as_xmm_double_reg(), src_addr);
+#ifndef _LP64
} else if (dest->is_single_fpu()) {
assert(dest->fpu_regnr() == 0, "dest must be TOS");
Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
__ fld_s(src_addr);
} else if (dest->is_double_fpu()) {
assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
__ fld_d(src_addr);
+#endif // _LP64
} else {
ShouldNotReachHere();
}
}
@@ -1226,24 +1244,32 @@
switch (type) {
case T_FLOAT: {
if (dest->is_single_xmm()) {
__ movflt(dest->as_xmm_float_reg(), from_addr);
} else {
+#ifndef _LP64
assert(dest->is_single_fpu(), "must be");
assert(dest->fpu_regnr() == 0, "dest must be TOS");
__ fld_s(from_addr);
+#else
+ ShouldNotReachHere();
+#endif // !LP64
}
break;
}
case T_DOUBLE: {
if (dest->is_double_xmm()) {
__ movdbl(dest->as_xmm_double_reg(), from_addr);
} else {
+#ifndef _LP64
assert(dest->is_double_fpu(), "must be");
assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
__ fld_d(from_addr);
+#else
+ ShouldNotReachHere();
+#endif // !LP64
}
break;
}
case T_OBJECT: // fall through
@@ -1495,10 +1521,51 @@
move_regs(src->as_register(), dest->as_register());
__ sign_extend_short(dest->as_register());
break;
+#ifdef _LP64
+ case Bytecodes::_f2d:
+ __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
+ break;
+
+ case Bytecodes::_d2f:
+ __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
+ break;
+
+ case Bytecodes::_i2f:
+ __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
+ break;
+
+ case Bytecodes::_i2d:
+ __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
+ break;
+
+ case Bytecodes::_l2f:
+ __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
+ break;
+
+ case Bytecodes::_l2d:
+ __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
+ break;
+
+ case Bytecodes::_f2i:
+ __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
+ break;
+
+ case Bytecodes::_d2i:
+ __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
+ break;
+
+ case Bytecodes::_f2l:
+ __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
+ break;
+
+ case Bytecodes::_d2l:
+ __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
+ break;
+#else
case Bytecodes::_f2d:
case Bytecodes::_d2f:
if (dest->is_single_xmm()) {
__ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
} else if (dest->is_double_xmm()) {
@@ -1520,10 +1587,19 @@
__ movl(Address(rsp, 0), src->as_register());
__ fild_s(Address(rsp, 0));
}
break;
+ case Bytecodes::_l2f:
+ case Bytecodes::_l2d:
+ assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
+ assert(dest->fpu() == 0, "result must be on TOS");
+ __ movptr(Address(rsp, 0), src->as_register_lo());
+ __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
+ __ fild_d(Address(rsp, 0));
+ // float result is rounded later through spilling
+
case Bytecodes::_f2i:
case Bytecodes::_d2i:
if (src->is_single_xmm()) {
__ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
} else if (src->is_double_xmm()) {
@@ -1533,29 +1609,17 @@
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
__ fist_s(Address(rsp, 0));
__ movl(dest->as_register(), Address(rsp, 0));
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
}
-
// IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
assert(op->stub() != NULL, "stub required");
__ cmpl(dest->as_register(), 0x80000000);
__ jcc(Assembler::equal, *op->stub()->entry());
__ bind(*op->stub()->continuation());
break;
- case Bytecodes::_l2f:
- case Bytecodes::_l2d:
- assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
- assert(dest->fpu() == 0, "result must be on TOS");
-
- __ movptr(Address(rsp, 0), src->as_register_lo());
- NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
- __ fild_d(Address(rsp, 0));
- // float result is rounded later through spilling
- break;
-
case Bytecodes::_f2l:
case Bytecodes::_d2l:
assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
assert(src->fpu() == 0, "input must be on TOS");
assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
@@ -1563,10 +1627,11 @@
// instruction sequence too long to inline it here
{
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
}
break;
+#endif // _LP64
default: ShouldNotReachHere();
}
}
@@ -2222,10 +2287,11 @@
case lir_div: __ divsd(lreg, raddr); break;
default: ShouldNotReachHere();
}
}
+#ifndef _LP64
} else if (left->is_single_fpu()) {
assert(dest->is_single_fpu(), "fpu stack allocation required");
if (right->is_single_fpu()) {
arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
@@ -2297,10 +2363,11 @@
if (code == lir_mul_strictfp || code == lir_div_strictfp) {
// Double values require special handling for strictfp mul/div on x86
__ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
__ fmulp(dest->fpu_regnrLo() + 1);
}
+#endif // !_LP64
} else if (left->is_single_stack() || left->is_address()) {
assert(left == dest, "left and dest must be equal");
Address laddr;
@@ -2339,10 +2406,11 @@
} else {
ShouldNotReachHere();
}
}
+#ifndef _LP64
void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
assert(left_index == 0 || right_index == 0, "either must be on top of stack");
@@ -2396,10 +2464,11 @@
default:
ShouldNotReachHere();
}
}
+#endif // _LP64
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
if (value->is_double_xmm()) {
switch(code) {
@@ -2425,17 +2494,19 @@
case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
// all other intrinsics are not available in the SSE instruction set, so FPU is used
default : ShouldNotReachHere();
}
+#ifndef _LP64
} else if (value->is_double_fpu()) {
assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
switch(code) {
case lir_abs : __ fabs() ; break;
case lir_sqrt : __ fsqrt(); break;
default : ShouldNotReachHere();
}
+#endif // !_LP64
} else {
Unimplemented();
}
}
@@ -2740,14 +2811,16 @@
__ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
} else {
ShouldNotReachHere();
}
+#ifndef _LP64
} else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
assert(opr2->is_fpu_register(), "both must be registers");
__ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
+#endif // LP64
} else if (opr1->is_address() && opr2->is_constant()) {
LIR_Const* c = opr2->as_constant_ptr();
#ifdef _LP64
if (is_reference_type(c->type())) {
@@ -2787,16 +2860,20 @@
} else if (left->is_double_xmm()) {
assert(right->is_double_xmm(), "must match");
__ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
} else {
+#ifdef _LP64
+ ShouldNotReachHere();
+#else
assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
assert(left->fpu() == 0, "left must be on TOS");
__ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
+#endif // LP64
}
} else {
assert(code == lir_cmp_l2i, "check");
#ifdef _LP64
Label done;
@@ -3809,14 +3886,16 @@
__ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
}
__ xorpd(dest->as_xmm_double_reg(),
ExternalAddress((address)double_signflip_pool));
}
+#ifndef _LP64
} else if (left->is_single_fpu() || left->is_double_fpu()) {
assert(left->fpu() == 0, "arg must be on TOS");
assert(dest->fpu() == 0, "dest must be TOS");
__ fchs();
+#endif // !_LP64
} else {
ShouldNotReachHere();
}
}
@@ -3882,10 +3961,11 @@
__ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
} else {
ShouldNotReachHere();
}
+#ifndef _LP64
} else if (src->is_double_fpu()) {
assert(src->fpu_regnrLo() == 0, "must be TOS");
if (dest->is_double_stack()) {
__ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
} else if (dest->is_address()) {
@@ -3901,10 +3981,12 @@
} else if (src->is_address()) {
__ fild_d(as_Address(src->as_address_ptr()));
} else {
ShouldNotReachHere();
}
+#endif // !_LP64
+
} else {
ShouldNotReachHere();
}
}
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