1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/compressedOops.inline.hpp"
38 #include "oops/klass.inline.hpp"
39 #include "prims/methodHandles.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/flags/flagSetting.hpp"
42 #include "runtime/interfaceSupport.inline.hpp"
43 #include "runtime/objectMonitor.hpp"
44 #include "runtime/os.hpp"
45 #include "runtime/safepoint.hpp"
46 #include "runtime/safepointMechanism.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/stubRoutines.hpp"
49 #include "runtime/thread.hpp"
50 #include "utilities/macros.hpp"
51 #include "crc32c.h"
52 #ifdef COMPILER2
53 #include "opto/intrinsicnode.hpp"
54 #endif
55
56 #ifdef PRODUCT
57 #define BLOCK_COMMENT(str) /* nothing */
58 #define STOP(error) stop(error)
59 #else
60 #define BLOCK_COMMENT(str) block_comment(str)
61 #define STOP(error) block_comment(error); stop(error)
62 #endif
63
64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
65
66 #ifdef ASSERT
67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
68 #endif
69
70 static Assembler::Condition reverse[] = {
71 Assembler::noOverflow /* overflow = 0x0 */ ,
72 Assembler::overflow /* noOverflow = 0x1 */ ,
73 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
74 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
75 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
76 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
77 Assembler::above /* belowEqual = 0x6 */ ,
78 Assembler::belowEqual /* above = 0x7 */ ,
79 Assembler::positive /* negative = 0x8 */ ,
80 Assembler::negative /* positive = 0x9 */ ,
81 Assembler::noParity /* parity = 0xa */ ,
82 Assembler::parity /* noParity = 0xb */ ,
83 Assembler::greaterEqual /* less = 0xc */ ,
84 Assembler::less /* greaterEqual = 0xd */ ,
85 Assembler::greater /* lessEqual = 0xe */ ,
86 Assembler::lessEqual /* greater = 0xf, */
87
88 };
89
90
91 // Implementation of MacroAssembler
92
93 // First all the versions that have distinct versions depending on 32/64 bit
94 // Unless the difference is trivial (1 line or so).
95
96 #ifndef _LP64
97
98 // 32bit versions
99
100 Address MacroAssembler::as_Address(AddressLiteral adr) {
101 return Address(adr.target(), adr.rspec());
102 }
103
104 Address MacroAssembler::as_Address(ArrayAddress adr) {
105 return Address::make_array(adr);
106 }
107
108 void MacroAssembler::call_VM_leaf_base(address entry_point,
109 int number_of_arguments) {
110 call(RuntimeAddress(entry_point));
111 increment(rsp, number_of_arguments * wordSize);
112 }
113
114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
118 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
124 }
125
126 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
127 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
128 }
129
130 void MacroAssembler::cmpoop(Address src1, jobject obj) {
131 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
132 bs->obj_equals(this, src1, obj);
133 }
134
135 void MacroAssembler::cmpoop(Register src1, jobject obj) {
136 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
137 bs->obj_equals(this, src1, obj);
138 }
139
140 void MacroAssembler::extend_sign(Register hi, Register lo) {
141 // According to Intel Doc. AP-526, "Integer Divide", p.18.
142 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
143 cdql();
144 } else {
145 movl(hi, lo);
146 sarl(hi, 31);
147 }
148 }
149
150 void MacroAssembler::jC2(Register tmp, Label& L) {
151 // set parity bit if FPU flag C2 is set (via rax)
152 save_rax(tmp);
153 fwait(); fnstsw_ax();
154 sahf();
155 restore_rax(tmp);
156 // branch
157 jcc(Assembler::parity, L);
158 }
159
160 void MacroAssembler::jnC2(Register tmp, Label& L) {
161 // set parity bit if FPU flag C2 is set (via rax)
162 save_rax(tmp);
163 fwait(); fnstsw_ax();
164 sahf();
165 restore_rax(tmp);
166 // branch
167 jcc(Assembler::noParity, L);
168 }
169
170 // 32bit can do a case table jump in one instruction but we no longer allow the base
171 // to be installed in the Address class
172 void MacroAssembler::jump(ArrayAddress entry) {
173 jmp(as_Address(entry));
174 }
175
176 // Note: y_lo will be destroyed
177 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
178 // Long compare for Java (semantics as described in JVM spec.)
179 Label high, low, done;
180
181 cmpl(x_hi, y_hi);
182 jcc(Assembler::less, low);
183 jcc(Assembler::greater, high);
184 // x_hi is the return register
185 xorl(x_hi, x_hi);
186 cmpl(x_lo, y_lo);
187 jcc(Assembler::below, low);
188 jcc(Assembler::equal, done);
189
190 bind(high);
191 xorl(x_hi, x_hi);
192 increment(x_hi);
193 jmp(done);
194
195 bind(low);
196 xorl(x_hi, x_hi);
197 decrementl(x_hi);
198
199 bind(done);
200 }
201
202 void MacroAssembler::lea(Register dst, AddressLiteral src) {
203 mov_literal32(dst, (int32_t)src.target(), src.rspec());
204 }
205
206 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj) {
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
318 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
319 }
320
321 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
322 // scratch register is not used,
323 // it is defined to match parameters of 64-bit version of this method.
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
332 movl(as_Address(dst), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src));
337 }
338
339 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
340 void MacroAssembler::movptr(Address dst, intptr_t src) {
341 movl(dst, src);
342 }
343
344
345 void MacroAssembler::pop_callee_saved_registers() {
346 pop(rcx);
347 pop(rdx);
348 pop(rdi);
349 pop(rsi);
350 }
351
352 void MacroAssembler::pop_fTOS() {
353 fld_d(Address(rsp, 0));
354 addl(rsp, 2 * wordSize);
355 }
356
357 void MacroAssembler::push_callee_saved_registers() {
358 push(rsi);
359 push(rdi);
360 push(rdx);
361 push(rcx);
362 }
363
364 void MacroAssembler::push_fTOS() {
365 subl(rsp, 2 * wordSize);
366 fstp_d(Address(rsp, 0));
367 }
368
369
370 void MacroAssembler::pushoop(jobject obj) {
371 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
372 }
373
374 void MacroAssembler::pushklass(Metadata* obj) {
375 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
376 }
377
378 void MacroAssembler::pushptr(AddressLiteral src) {
379 if (src.is_lval()) {
380 push_literal32((int32_t)src.target(), src.rspec());
381 } else {
382 pushl(as_Address(src));
383 }
384 }
385
386 void MacroAssembler::set_word_if_not_zero(Register dst) {
387 xorl(dst, dst);
388 set_byte_if_not_zero(dst);
389 }
390
391 static void pass_arg0(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 static void pass_arg1(MacroAssembler* masm, Register arg) {
396 masm->push(arg);
397 }
398
399 static void pass_arg2(MacroAssembler* masm, Register arg) {
400 masm->push(arg);
401 }
402
403 static void pass_arg3(MacroAssembler* masm, Register arg) {
404 masm->push(arg);
405 }
406
407 #ifndef PRODUCT
408 extern "C" void findpc(intptr_t x);
409 #endif
410
411 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
412 // In order to get locks to work, we need to fake a in_VM state
413 JavaThread* thread = JavaThread::current();
414 JavaThreadState saved_state = thread->thread_state();
415 thread->set_thread_state(_thread_in_vm);
416 if (ShowMessageBoxOnError) {
417 JavaThread* thread = JavaThread::current();
418 JavaThreadState saved_state = thread->thread_state();
419 thread->set_thread_state(_thread_in_vm);
420 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
421 ttyLocker ttyl;
422 BytecodeCounter::print();
423 }
424 // To see where a verify_oop failed, get $ebx+40/X for this frame.
425 // This is the value of eip which points to where verify_oop will return.
426 if (os::message_box(msg, "Execution stopped, print registers?")) {
427 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
428 BREAKPOINT;
429 }
430 }
431 fatal("DEBUG MESSAGE: %s", msg);
432 }
433
434 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
435 ttyLocker ttyl;
436 FlagSetting fs(Debugging, true);
437 tty->print_cr("eip = 0x%08x", eip);
438 #ifndef PRODUCT
439 if ((WizardMode || Verbose) && PrintMiscellaneous) {
440 tty->cr();
441 findpc(eip);
442 tty->cr();
443 }
444 #endif
445 #define PRINT_REG(rax) \
446 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
447 PRINT_REG(rax);
448 PRINT_REG(rbx);
449 PRINT_REG(rcx);
450 PRINT_REG(rdx);
451 PRINT_REG(rdi);
452 PRINT_REG(rsi);
453 PRINT_REG(rbp);
454 PRINT_REG(rsp);
455 #undef PRINT_REG
456 // Print some words near top of staack.
457 int* dump_sp = (int*) rsp;
458 for (int col1 = 0; col1 < 8; col1++) {
459 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
460 os::print_location(tty, *dump_sp++);
461 }
462 for (int row = 0; row < 16; row++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 for (int col = 0; col < 8; col++) {
465 tty->print(" 0x%08x", *dump_sp++);
466 }
467 tty->cr();
468 }
469 // Print some instructions around pc:
470 Disassembler::decode((address)eip-64, (address)eip);
471 tty->print_cr("--------");
472 Disassembler::decode((address)eip, (address)eip+32);
473 }
474
475 void MacroAssembler::stop(const char* msg) {
476 ExternalAddress message((address)msg);
477 // push address of message
478 pushptr(message.addr());
479 { Label L; call(L, relocInfo::none); bind(L); } // push eip
480 pusha(); // push registers
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
482 hlt();
483 }
484
485 void MacroAssembler::warn(const char* msg) {
486 push_CPU_state();
487
488 ExternalAddress message((address) msg);
489 // push address of message
490 pushptr(message.addr());
491
492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
493 addl(rsp, wordSize); // discard argument
494 pop_CPU_state();
495 }
496
497 void MacroAssembler::print_state() {
498 { Label L; call(L, relocInfo::none); bind(L); } // push eip
499 pusha(); // push registers
500
501 push_CPU_state();
502 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
503 pop_CPU_state();
504
505 popa();
506 addl(rsp, wordSize);
507 }
508
509 #else // _LP64
510
511 // 64 bit versions
512
513 Address MacroAssembler::as_Address(AddressLiteral adr) {
514 // amd64 always does this as a pc-rel
515 // we can be absolute or disp based on the instruction type
516 // jmp/call are displacements others are absolute
517 assert(!adr.is_lval(), "must be rval");
518 assert(reachable(adr), "must be");
519 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
520
521 }
522
523 Address MacroAssembler::as_Address(ArrayAddress adr) {
524 AddressLiteral base = adr.base();
525 lea(rscratch1, base);
526 Address index = adr.index();
527 assert(index._disp == 0, "must not have disp"); // maybe it can?
528 Address array(rscratch1, index._index, index._scale, index._disp);
529 return array;
530 }
531
532 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
533 Label L, E;
534
535 #ifdef _WIN64
536 // Windows always allocates space for it's register args
537 assert(num_args <= 4, "only register arguments supported");
538 subq(rsp, frame::arg_reg_save_area_bytes);
539 #endif
540
541 // Align stack if necessary
542 testl(rsp, 15);
543 jcc(Assembler::zero, L);
544
545 subq(rsp, 8);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549 addq(rsp, 8);
550 jmp(E);
551
552 bind(L);
553 {
554 call(RuntimeAddress(entry_point));
555 }
556
557 bind(E);
558
559 #ifdef _WIN64
560 // restore stack pointer
561 addq(rsp, frame::arg_reg_save_area_bytes);
562 #endif
563
564 }
565
566 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
567 assert(!src2.is_lval(), "should use cmpptr");
568
569 if (reachable(src2)) {
570 cmpq(src1, as_Address(src2));
571 } else {
572 lea(rscratch1, src2);
573 Assembler::cmpq(src1, Address(rscratch1, 0));
574 }
575 }
576
577 int MacroAssembler::corrected_idivq(Register reg) {
578 // Full implementation of Java ldiv and lrem; checks for special
579 // case as described in JVM spec., p.243 & p.271. The function
580 // returns the (pc) offset of the idivl instruction - may be needed
581 // for implicit exceptions.
582 //
583 // normal case special case
584 //
585 // input : rax: dividend min_long
586 // reg: divisor (may not be eax/edx) -1
587 //
588 // output: rax: quotient (= rax idiv reg) min_long
589 // rdx: remainder (= rax irem reg) 0
590 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
591 static const int64_t min_long = 0x8000000000000000;
592 Label normal_case, special_case;
593
594 // check for special case
595 cmp64(rax, ExternalAddress((address) &min_long));
596 jcc(Assembler::notEqual, normal_case);
597 xorl(rdx, rdx); // prepare rdx for possible special case (where
598 // remainder = 0)
599 cmpq(reg, -1);
600 jcc(Assembler::equal, special_case);
601
602 // handle normal case
603 bind(normal_case);
604 cdqq();
605 int idivq_offset = offset();
606 idivq(reg);
607
608 // normal and special case exit
609 bind(special_case);
610
611 return idivq_offset;
612 }
613
614 void MacroAssembler::decrementq(Register reg, int value) {
615 if (value == min_jint) { subq(reg, value); return; }
616 if (value < 0) { incrementq(reg, -value); return; }
617 if (value == 0) { ; return; }
618 if (value == 1 && UseIncDec) { decq(reg) ; return; }
619 /* else */ { subq(reg, value) ; return; }
620 }
621
622 void MacroAssembler::decrementq(Address dst, int value) {
623 if (value == min_jint) { subq(dst, value); return; }
624 if (value < 0) { incrementq(dst, -value); return; }
625 if (value == 0) { ; return; }
626 if (value == 1 && UseIncDec) { decq(dst) ; return; }
627 /* else */ { subq(dst, value) ; return; }
628 }
629
630 void MacroAssembler::incrementq(AddressLiteral dst) {
631 if (reachable(dst)) {
632 incrementq(as_Address(dst));
633 } else {
634 lea(rscratch1, dst);
635 incrementq(Address(rscratch1, 0));
636 }
637 }
638
639 void MacroAssembler::incrementq(Register reg, int value) {
640 if (value == min_jint) { addq(reg, value); return; }
641 if (value < 0) { decrementq(reg, -value); return; }
642 if (value == 0) { ; return; }
643 if (value == 1 && UseIncDec) { incq(reg) ; return; }
644 /* else */ { addq(reg, value) ; return; }
645 }
646
647 void MacroAssembler::incrementq(Address dst, int value) {
648 if (value == min_jint) { addq(dst, value); return; }
649 if (value < 0) { decrementq(dst, -value); return; }
650 if (value == 0) { ; return; }
651 if (value == 1 && UseIncDec) { incq(dst) ; return; }
652 /* else */ { addq(dst, value) ; return; }
653 }
654
655 // 32bit can do a case table jump in one instruction but we no longer allow the base
656 // to be installed in the Address class
657 void MacroAssembler::jump(ArrayAddress entry) {
658 lea(rscratch1, entry.base());
659 Address dispatch = entry.index();
660 assert(dispatch._base == noreg, "must be");
661 dispatch._base = rscratch1;
662 jmp(dispatch);
663 }
664
665 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
666 ShouldNotReachHere(); // 64bit doesn't use two regs
667 cmpq(x_lo, y_lo);
668 }
669
670 void MacroAssembler::lea(Register dst, AddressLiteral src) {
671 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
672 }
673
674 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
675 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
676 movptr(dst, rscratch1);
677 }
678
679 void MacroAssembler::leave() {
680 // %%% is this really better? Why not on 32bit too?
681 emit_int8((unsigned char)0xC9); // LEAVE
682 }
683
684 void MacroAssembler::lneg(Register hi, Register lo) {
685 ShouldNotReachHere(); // 64bit doesn't use two regs
686 negq(lo);
687 }
688
689 void MacroAssembler::movoop(Register dst, jobject obj) {
690 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
691 }
692
693 void MacroAssembler::movoop(Address dst, jobject obj) {
694 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 movq(dst, rscratch1);
696 }
697
698 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
699 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
700 }
701
702 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
703 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 movq(dst, rscratch1);
705 }
706
707 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
708 if (src.is_lval()) {
709 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
710 } else {
711 if (reachable(src)) {
712 movq(dst, as_Address(src));
713 } else {
714 lea(scratch, src);
715 movq(dst, Address(scratch, 0));
716 }
717 }
718 }
719
720 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
721 movq(as_Address(dst), src);
722 }
723
724 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
725 movq(dst, as_Address(src));
726 }
727
728 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
729 void MacroAssembler::movptr(Address dst, intptr_t src) {
730 mov64(rscratch1, src);
731 movq(dst, rscratch1);
732 }
733
734 // These are mostly for initializing NULL
735 void MacroAssembler::movptr(Address dst, int32_t src) {
736 movslq(dst, src);
737 }
738
739 void MacroAssembler::movptr(Register dst, int32_t src) {
740 mov64(dst, (intptr_t)src);
741 }
742
743 void MacroAssembler::pushoop(jobject obj) {
744 movoop(rscratch1, obj);
745 push(rscratch1);
746 }
747
748 void MacroAssembler::pushklass(Metadata* obj) {
749 mov_metadata(rscratch1, obj);
750 push(rscratch1);
751 }
752
753 void MacroAssembler::pushptr(AddressLiteral src) {
754 lea(rscratch1, src);
755 if (src.is_lval()) {
756 push(rscratch1);
757 } else {
758 pushq(Address(rscratch1, 0));
759 }
760 }
761
762 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
763 // we must set sp to zero to clear frame
764 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
765 // must clear fp, so that compiled frames are not confused; it is
766 // possible that we need it only for debugging
767 if (clear_fp) {
768 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
769 }
770
771 // Always clear the pc because it could have been set by make_walkable()
772 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
773 vzeroupper();
774 }
775
776 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
777 Register last_java_fp,
778 address last_java_pc) {
779 vzeroupper();
780 // determine last_java_sp register
781 if (!last_java_sp->is_valid()) {
782 last_java_sp = rsp;
783 }
784
785 // last_java_fp is optional
786 if (last_java_fp->is_valid()) {
787 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
788 last_java_fp);
789 }
790
791 // last_java_pc is optional
792 if (last_java_pc != NULL) {
793 Address java_pc(r15_thread,
794 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
795 lea(rscratch1, InternalAddress(last_java_pc));
796 movptr(java_pc, rscratch1);
797 }
798
799 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
800 }
801
802 static void pass_arg0(MacroAssembler* masm, Register arg) {
803 if (c_rarg0 != arg ) {
804 masm->mov(c_rarg0, arg);
805 }
806 }
807
808 static void pass_arg1(MacroAssembler* masm, Register arg) {
809 if (c_rarg1 != arg ) {
810 masm->mov(c_rarg1, arg);
811 }
812 }
813
814 static void pass_arg2(MacroAssembler* masm, Register arg) {
815 if (c_rarg2 != arg ) {
816 masm->mov(c_rarg2, arg);
817 }
818 }
819
820 static void pass_arg3(MacroAssembler* masm, Register arg) {
821 if (c_rarg3 != arg ) {
822 masm->mov(c_rarg3, arg);
823 }
824 }
825
826 void MacroAssembler::stop(const char* msg) {
827 if (ShowMessageBoxOnError) {
828 address rip = pc();
829 pusha(); // get regs on stack
830 lea(c_rarg1, InternalAddress(rip));
831 movq(c_rarg2, rsp); // pass pointer to regs array
832 }
833 lea(c_rarg0, ExternalAddress((address) msg));
834 andq(rsp, -16); // align stack as required by ABI
835 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
836 hlt();
837 }
838
839 void MacroAssembler::warn(const char* msg) {
840 push(rbp);
841 movq(rbp, rsp);
842 andq(rsp, -16); // align stack as required by push_CPU_state and call
843 push_CPU_state(); // keeps alignment at 16 bytes
844 lea(c_rarg0, ExternalAddress((address) msg));
845 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
846 call(rax);
847 pop_CPU_state();
848 mov(rsp, rbp);
849 pop(rbp);
850 }
851
852 void MacroAssembler::print_state() {
853 address rip = pc();
854 pusha(); // get regs on stack
855 push(rbp);
856 movq(rbp, rsp);
857 andq(rsp, -16); // align stack as required by push_CPU_state and call
858 push_CPU_state(); // keeps alignment at 16 bytes
859
860 lea(c_rarg0, InternalAddress(rip));
861 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
862 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
863
864 pop_CPU_state();
865 mov(rsp, rbp);
866 pop(rbp);
867 popa();
868 }
869
870 #ifndef PRODUCT
871 extern "C" void findpc(intptr_t x);
872 #endif
873
874 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
875 // In order to get locks to work, we need to fake a in_VM state
876 if (ShowMessageBoxOnError) {
877 JavaThread* thread = JavaThread::current();
878 JavaThreadState saved_state = thread->thread_state();
879 thread->set_thread_state(_thread_in_vm);
880 #ifndef PRODUCT
881 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
882 ttyLocker ttyl;
883 BytecodeCounter::print();
884 }
885 #endif
886 // To see where a verify_oop failed, get $ebx+40/X for this frame.
887 // XXX correct this offset for amd64
888 // This is the value of eip which points to where verify_oop will return.
889 if (os::message_box(msg, "Execution stopped, print registers?")) {
890 print_state64(pc, regs);
891 BREAKPOINT;
892 }
893 }
894 fatal("DEBUG MESSAGE: %s", msg);
895 }
896
897 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
898 ttyLocker ttyl;
899 FlagSetting fs(Debugging, true);
900 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
901 #ifndef PRODUCT
902 tty->cr();
903 findpc(pc);
904 tty->cr();
905 #endif
906 #define PRINT_REG(rax, value) \
907 { tty->print("%s = ", #rax); os::print_location(tty, value); }
908 PRINT_REG(rax, regs[15]);
909 PRINT_REG(rbx, regs[12]);
910 PRINT_REG(rcx, regs[14]);
911 PRINT_REG(rdx, regs[13]);
912 PRINT_REG(rdi, regs[8]);
913 PRINT_REG(rsi, regs[9]);
914 PRINT_REG(rbp, regs[10]);
915 PRINT_REG(rsp, regs[11]);
916 PRINT_REG(r8 , regs[7]);
917 PRINT_REG(r9 , regs[6]);
918 PRINT_REG(r10, regs[5]);
919 PRINT_REG(r11, regs[4]);
920 PRINT_REG(r12, regs[3]);
921 PRINT_REG(r13, regs[2]);
922 PRINT_REG(r14, regs[1]);
923 PRINT_REG(r15, regs[0]);
924 #undef PRINT_REG
925 // Print some words near top of staack.
926 int64_t* rsp = (int64_t*) regs[11];
927 int64_t* dump_sp = rsp;
928 for (int col1 = 0; col1 < 8; col1++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
930 os::print_location(tty, *dump_sp++);
931 }
932 for (int row = 0; row < 25; row++) {
933 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
934 for (int col = 0; col < 4; col++) {
935 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
936 }
937 tty->cr();
938 }
939 // Print some instructions around pc:
940 Disassembler::decode((address)pc-64, (address)pc);
941 tty->print_cr("--------");
942 Disassembler::decode((address)pc, (address)pc+32);
943 }
944
945 #endif // _LP64
946
947 // Now versions that are common to 32/64 bit
948
949 void MacroAssembler::addptr(Register dst, int32_t imm32) {
950 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
951 }
952
953 void MacroAssembler::addptr(Register dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addptr(Address dst, Register src) {
958 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
959 }
960
961 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
962 if (reachable(src)) {
963 Assembler::addsd(dst, as_Address(src));
964 } else {
965 lea(rscratch1, src);
966 Assembler::addsd(dst, Address(rscratch1, 0));
967 }
968 }
969
970 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
971 if (reachable(src)) {
972 addss(dst, as_Address(src));
973 } else {
974 lea(rscratch1, src);
975 addss(dst, Address(rscratch1, 0));
976 }
977 }
978
979 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
980 if (reachable(src)) {
981 Assembler::addpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::addpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::align(int modulus) {
989 align(modulus, offset());
990 }
991
992 void MacroAssembler::align(int modulus, int target) {
993 if (target % modulus != 0) {
994 nop(modulus - (target % modulus));
995 }
996 }
997
998 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
999 // Used in sign-masking with aligned address.
1000 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1001 if (reachable(src)) {
1002 Assembler::andpd(dst, as_Address(src));
1003 } else {
1004 lea(scratch_reg, src);
1005 Assembler::andpd(dst, Address(scratch_reg, 0));
1006 }
1007 }
1008
1009 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1010 // Used in sign-masking with aligned address.
1011 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1012 if (reachable(src)) {
1013 Assembler::andps(dst, as_Address(src));
1014 } else {
1015 lea(scratch_reg, src);
1016 Assembler::andps(dst, Address(scratch_reg, 0));
1017 }
1018 }
1019
1020 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1021 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1022 }
1023
1024 void MacroAssembler::atomic_incl(Address counter_addr) {
1025 lock();
1026 incrementl(counter_addr);
1027 }
1028
1029 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1030 if (reachable(counter_addr)) {
1031 atomic_incl(as_Address(counter_addr));
1032 } else {
1033 lea(scr, counter_addr);
1034 atomic_incl(Address(scr, 0));
1035 }
1036 }
1037
1038 #ifdef _LP64
1039 void MacroAssembler::atomic_incq(Address counter_addr) {
1040 lock();
1041 incrementq(counter_addr);
1042 }
1043
1044 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1045 if (reachable(counter_addr)) {
1046 atomic_incq(as_Address(counter_addr));
1047 } else {
1048 lea(scr, counter_addr);
1049 atomic_incq(Address(scr, 0));
1050 }
1051 }
1052 #endif
1053
1054 // Writes to stack successive pages until offset reached to check for
1055 // stack overflow + shadow pages. This clobbers tmp.
1056 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1057 movptr(tmp, rsp);
1058 // Bang stack for total size given plus shadow page size.
1059 // Bang one page at a time because large size can bang beyond yellow and
1060 // red zones.
1061 Label loop;
1062 bind(loop);
1063 movl(Address(tmp, (-os::vm_page_size())), size );
1064 subptr(tmp, os::vm_page_size());
1065 subl(size, os::vm_page_size());
1066 jcc(Assembler::greater, loop);
1067
1068 // Bang down shadow pages too.
1069 // At this point, (tmp-0) is the last address touched, so don't
1070 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1071 // was post-decremented.) Skip this address by starting at i=1, and
1072 // touch a few more pages below. N.B. It is important to touch all
1073 // the way down including all pages in the shadow zone.
1074 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1075 // this could be any sized move but this is can be a debugging crumb
1076 // so the bigger the better.
1077 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1078 }
1079 }
1080
1081 void MacroAssembler::reserved_stack_check() {
1082 // testing if reserved zone needs to be enabled
1083 Label no_reserved_zone_enabling;
1084 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1085 NOT_LP64(get_thread(rsi);)
1086
1087 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1088 jcc(Assembler::below, no_reserved_zone_enabling);
1089
1090 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1091 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1092 should_not_reach_here();
1093
1094 bind(no_reserved_zone_enabling);
1095 }
1096
1097 int MacroAssembler::biased_locking_enter(Register lock_reg,
1098 Register obj_reg,
1099 Register swap_reg,
1100 Register tmp_reg,
1101 bool swap_reg_contains_mark,
1102 Label& done,
1103 Label* slow_case,
1104 BiasedLockingCounters* counters) {
1105 assert(UseBiasedLocking, "why call this otherwise?");
1106 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1107 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1108 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1109 assert(markWord::age_shift == markWord::lock_bits + markWord::biased_lock_bits, "biased locking makes assumptions about bit layout");
1110 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1111 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1112
1113 if (PrintBiasedLockingStatistics && counters == NULL) {
1114 counters = BiasedLocking::counters();
1115 }
1116 // Biased locking
1117 // See whether the lock is currently biased toward our thread and
1118 // whether the epoch is still valid
1119 // Note that the runtime guarantees sufficient alignment of JavaThread
1120 // pointers to allow age to be placed into low bits
1121 // First check to see whether biasing is even enabled for this object
1122 Label cas_label;
1123 int null_check_offset = -1;
1124 if (!swap_reg_contains_mark) {
1125 null_check_offset = offset();
1126 movptr(swap_reg, mark_addr);
1127 }
1128 movptr(tmp_reg, swap_reg);
1129 andptr(tmp_reg, markWord::biased_lock_mask_in_place);
1130 cmpptr(tmp_reg, markWord::biased_lock_pattern);
1131 jcc(Assembler::notEqual, cas_label);
1132 // The bias pattern is present in the object's header. Need to check
1133 // whether the bias owner and the epoch are both still current.
1134 #ifndef _LP64
1135 // Note that because there is no current thread register on x86_32 we
1136 // need to store off the mark word we read out of the object to
1137 // avoid reloading it and needing to recheck invariants below. This
1138 // store is unfortunate but it makes the overall code shorter and
1139 // simpler.
1140 movptr(saved_mark_addr, swap_reg);
1141 #endif
1142 if (swap_reg_contains_mark) {
1143 null_check_offset = offset();
1144 }
1145 load_prototype_header(tmp_reg, obj_reg);
1146 #ifdef _LP64
1147 orptr(tmp_reg, r15_thread);
1148 xorptr(tmp_reg, swap_reg);
1149 Register header_reg = tmp_reg;
1150 #else
1151 xorptr(tmp_reg, swap_reg);
1152 get_thread(swap_reg);
1153 xorptr(swap_reg, tmp_reg);
1154 Register header_reg = swap_reg;
1155 #endif
1156 andptr(header_reg, ~((int) markWord::age_mask_in_place));
1157 if (counters != NULL) {
1158 cond_inc32(Assembler::zero,
1159 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1160 }
1161 jcc(Assembler::equal, done);
1162
1163 Label try_revoke_bias;
1164 Label try_rebias;
1165
1166 // At this point we know that the header has the bias pattern and
1167 // that we are not the bias owner in the current epoch. We need to
1168 // figure out more details about the state of the header in order to
1169 // know what operations can be legally performed on the object's
1170 // header.
1171
1172 // If the low three bits in the xor result aren't clear, that means
1173 // the prototype header is no longer biased and we have to revoke
1174 // the bias on this object.
1175 testptr(header_reg, markWord::biased_lock_mask_in_place);
1176 jccb(Assembler::notZero, try_revoke_bias);
1177
1178 // Biasing is still enabled for this data type. See whether the
1179 // epoch of the current bias is still valid, meaning that the epoch
1180 // bits of the mark word are equal to the epoch bits of the
1181 // prototype header. (Note that the prototype header's epoch bits
1182 // only change at a safepoint.) If not, attempt to rebias the object
1183 // toward the current thread. Note that we must be absolutely sure
1184 // that the current epoch is invalid in order to do this because
1185 // otherwise the manipulations it performs on the mark word are
1186 // illegal.
1187 testptr(header_reg, markWord::epoch_mask_in_place);
1188 jccb(Assembler::notZero, try_rebias);
1189
1190 // The epoch of the current bias is still valid but we know nothing
1191 // about the owner; it might be set or it might be clear. Try to
1192 // acquire the bias of the object using an atomic operation. If this
1193 // fails we will go in to the runtime to revoke the object's bias.
1194 // Note that we first construct the presumed unbiased header so we
1195 // don't accidentally blow away another thread's valid bias.
1196 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1197 andptr(swap_reg,
1198 markWord::biased_lock_mask_in_place | markWord::age_mask_in_place | markWord::epoch_mask_in_place);
1199 #ifdef _LP64
1200 movptr(tmp_reg, swap_reg);
1201 orptr(tmp_reg, r15_thread);
1202 #else
1203 get_thread(tmp_reg);
1204 orptr(tmp_reg, swap_reg);
1205 #endif
1206 lock();
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 lock();
1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 load_prototype_header(tmp_reg, obj_reg);
1267 lock();
1268 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1269 // Fall through to the normal CAS-based lock, because no matter what
1270 // the result of the above CAS, some thread must have succeeded in
1271 // removing the bias bit from the object's header.
1272 if (counters != NULL) {
1273 cond_inc32(Assembler::zero,
1274 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1275 }
1276
1277 bind(cas_label);
1278
1279 return null_check_offset;
1280 }
1281
1282 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1283 assert(UseBiasedLocking, "why call this otherwise?");
1284
1285 // Check for biased locking unlock case, which is a no-op
1286 // Note: we do not have to check the thread ID for two reasons.
1287 // First, the interpreter checks for IllegalMonitorStateException at
1288 // a higher level. Second, if the bias was revoked while we held the
1289 // lock, the object could not be rebiased toward another thread, so
1290 // the bias bit would be clear.
1291 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1292 andptr(temp_reg, markWord::biased_lock_mask_in_place);
1293 cmpptr(temp_reg, markWord::biased_lock_pattern);
1294 jcc(Assembler::equal, done);
1295 }
1296
1297 #ifdef COMPILER2
1298
1299 #if INCLUDE_RTM_OPT
1300
1301 // Update rtm_counters based on abort status
1302 // input: abort_status
1303 // rtm_counters (RTMLockingCounters*)
1304 // flags are killed
1305 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1306
1307 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1308 if (PrintPreciseRTMLockingStatistics) {
1309 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1310 Label check_abort;
1311 testl(abort_status, (1<<i));
1312 jccb(Assembler::equal, check_abort);
1313 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1314 bind(check_abort);
1315 }
1316 }
1317 }
1318
1319 // Branch if (random & (count-1) != 0), count is 2^n
1320 // tmp, scr and flags are killed
1321 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1322 assert(tmp == rax, "");
1323 assert(scr == rdx, "");
1324 rdtsc(); // modifies EDX:EAX
1325 andptr(tmp, count-1);
1326 jccb(Assembler::notZero, brLabel);
1327 }
1328
1329 // Perform abort ratio calculation, set no_rtm bit if high ratio
1330 // input: rtm_counters_Reg (RTMLockingCounters* address)
1331 // tmpReg, rtm_counters_Reg and flags are killed
1332 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1333 Register rtm_counters_Reg,
1334 RTMLockingCounters* rtm_counters,
1335 Metadata* method_data) {
1336 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1337
1338 if (RTMLockingCalculationDelay > 0) {
1339 // Delay calculation
1340 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1341 testptr(tmpReg, tmpReg);
1342 jccb(Assembler::equal, L_done);
1343 }
1344 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1345 // Aborted transactions = abort_count * 100
1346 // All transactions = total_count * RTMTotalCountIncrRate
1347 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1348
1349 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1350 cmpptr(tmpReg, RTMAbortThreshold);
1351 jccb(Assembler::below, L_check_always_rtm2);
1352 imulptr(tmpReg, tmpReg, 100);
1353
1354 Register scrReg = rtm_counters_Reg;
1355 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1356 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1357 imulptr(scrReg, scrReg, RTMAbortRatio);
1358 cmpptr(tmpReg, scrReg);
1359 jccb(Assembler::below, L_check_always_rtm1);
1360 if (method_data != NULL) {
1361 // set rtm_state to "no rtm" in MDO
1362 mov_metadata(tmpReg, method_data);
1363 lock();
1364 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1365 }
1366 jmpb(L_done);
1367 bind(L_check_always_rtm1);
1368 // Reload RTMLockingCounters* address
1369 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1370 bind(L_check_always_rtm2);
1371 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1373 jccb(Assembler::below, L_done);
1374 if (method_data != NULL) {
1375 // set rtm_state to "always rtm" in MDO
1376 mov_metadata(tmpReg, method_data);
1377 lock();
1378 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1379 }
1380 bind(L_done);
1381 }
1382
1383 // Update counters and perform abort ratio calculation
1384 // input: abort_status_Reg
1385 // rtm_counters_Reg, flags are killed
1386 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1387 Register rtm_counters_Reg,
1388 RTMLockingCounters* rtm_counters,
1389 Metadata* method_data,
1390 bool profile_rtm) {
1391
1392 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1393 // update rtm counters based on rax value at abort
1394 // reads abort_status_Reg, updates flags
1395 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1396 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1397 if (profile_rtm) {
1398 // Save abort status because abort_status_Reg is used by following code.
1399 if (RTMRetryCount > 0) {
1400 push(abort_status_Reg);
1401 }
1402 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1403 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1404 // restore abort status
1405 if (RTMRetryCount > 0) {
1406 pop(abort_status_Reg);
1407 }
1408 }
1409 }
1410
1411 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1412 // inputs: retry_count_Reg
1413 // : abort_status_Reg
1414 // output: retry_count_Reg decremented by 1
1415 // flags are killed
1416 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1417 Label doneRetry;
1418 assert(abort_status_Reg == rax, "");
1419 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1420 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1421 // if reason is in 0x6 and retry count != 0 then retry
1422 andptr(abort_status_Reg, 0x6);
1423 jccb(Assembler::zero, doneRetry);
1424 testl(retry_count_Reg, retry_count_Reg);
1425 jccb(Assembler::zero, doneRetry);
1426 pause();
1427 decrementl(retry_count_Reg);
1428 jmp(retryLabel);
1429 bind(doneRetry);
1430 }
1431
1432 // Spin and retry if lock is busy,
1433 // inputs: box_Reg (monitor address)
1434 // : retry_count_Reg
1435 // output: retry_count_Reg decremented by 1
1436 // : clear z flag if retry count exceeded
1437 // tmp_Reg, scr_Reg, flags are killed
1438 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1439 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1440 Label SpinLoop, SpinExit, doneRetry;
1441 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1442
1443 testl(retry_count_Reg, retry_count_Reg);
1444 jccb(Assembler::zero, doneRetry);
1445 decrementl(retry_count_Reg);
1446 movptr(scr_Reg, RTMSpinLoopCount);
1447
1448 bind(SpinLoop);
1449 pause();
1450 decrementl(scr_Reg);
1451 jccb(Assembler::lessEqual, SpinExit);
1452 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1453 testptr(tmp_Reg, tmp_Reg);
1454 jccb(Assembler::notZero, SpinLoop);
1455
1456 bind(SpinExit);
1457 jmp(retryLabel);
1458 bind(doneRetry);
1459 incrementl(retry_count_Reg); // clear z flag
1460 }
1461
1462 // Use RTM for normal stack locks
1463 // Input: objReg (object to lock)
1464 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1465 Register retry_on_abort_count_Reg,
1466 RTMLockingCounters* stack_rtm_counters,
1467 Metadata* method_data, bool profile_rtm,
1468 Label& DONE_LABEL, Label& IsInflated) {
1469 assert(UseRTMForStackLocks, "why call this otherwise?");
1470 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1471 assert(tmpReg == rax, "");
1472 assert(scrReg == rdx, "");
1473 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1474
1475 if (RTMRetryCount > 0) {
1476 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1477 bind(L_rtm_retry);
1478 }
1479 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1480 testptr(tmpReg, markWord::monitor_value); // inflated vs stack-locked|neutral|biased
1481 jcc(Assembler::notZero, IsInflated);
1482
1483 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1484 Label L_noincrement;
1485 if (RTMTotalCountIncrRate > 1) {
1486 // tmpReg, scrReg and flags are killed
1487 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1488 }
1489 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1490 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1491 bind(L_noincrement);
1492 }
1493 xbegin(L_on_abort);
1494 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1495 andptr(tmpReg, markWord::biased_lock_mask_in_place); // look at 3 lock bits
1496 cmpptr(tmpReg, markWord::unlocked_value); // bits = 001 unlocked
1497 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1498
1499 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1500 if (UseRTMXendForLockBusy) {
1501 xend();
1502 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1503 jmp(L_decrement_retry);
1504 }
1505 else {
1506 xabort(0);
1507 }
1508 bind(L_on_abort);
1509 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1510 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1511 }
1512 bind(L_decrement_retry);
1513 if (RTMRetryCount > 0) {
1514 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1515 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1516 }
1517 }
1518
1519 // Use RTM for inflating locks
1520 // inputs: objReg (object to lock)
1521 // boxReg (on-stack box address (displaced header location) - KILLED)
1522 // tmpReg (ObjectMonitor address + markWord::monitor_value)
1523 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1524 Register scrReg, Register retry_on_busy_count_Reg,
1525 Register retry_on_abort_count_Reg,
1526 RTMLockingCounters* rtm_counters,
1527 Metadata* method_data, bool profile_rtm,
1528 Label& DONE_LABEL) {
1529 assert(UseRTMLocking, "why call this otherwise?");
1530 assert(tmpReg == rax, "");
1531 assert(scrReg == rdx, "");
1532 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1533 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1534
1535 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
1536 movptr(Address(boxReg, 0), (int32_t)intptr_t(markWord::unused_mark().value()));
1537 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1538
1539 if (RTMRetryCount > 0) {
1540 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1541 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1542 bind(L_rtm_retry);
1543 }
1544 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1545 Label L_noincrement;
1546 if (RTMTotalCountIncrRate > 1) {
1547 // tmpReg, scrReg and flags are killed
1548 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1549 }
1550 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1551 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1552 bind(L_noincrement);
1553 }
1554 xbegin(L_on_abort);
1555 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1556 movptr(tmpReg, Address(tmpReg, owner_offset));
1557 testptr(tmpReg, tmpReg);
1558 jcc(Assembler::zero, DONE_LABEL);
1559 if (UseRTMXendForLockBusy) {
1560 xend();
1561 jmp(L_decrement_retry);
1562 }
1563 else {
1564 xabort(0);
1565 }
1566 bind(L_on_abort);
1567 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1568 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1569 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1570 }
1571 if (RTMRetryCount > 0) {
1572 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1573 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1574 }
1575
1576 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1577 testptr(tmpReg, tmpReg) ;
1578 jccb(Assembler::notZero, L_decrement_retry) ;
1579
1580 // Appears unlocked - try to swing _owner from null to non-null.
1581 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1582 #ifdef _LP64
1583 Register threadReg = r15_thread;
1584 #else
1585 get_thread(scrReg);
1586 Register threadReg = scrReg;
1587 #endif
1588 lock();
1589 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1590
1591 if (RTMRetryCount > 0) {
1592 // success done else retry
1593 jccb(Assembler::equal, DONE_LABEL) ;
1594 bind(L_decrement_retry);
1595 // Spin and retry if lock is busy.
1596 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1597 }
1598 else {
1599 bind(L_decrement_retry);
1600 }
1601 }
1602
1603 #endif // INCLUDE_RTM_OPT
1604
1605 // fast_lock and fast_unlock used by C2
1606
1607 // Because the transitions from emitted code to the runtime
1608 // monitorenter/exit helper stubs are so slow it's critical that
1609 // we inline both the stack-locking fast path and the inflated fast path.
1610 //
1611 // See also: cmpFastLock and cmpFastUnlock.
1612 //
1613 // What follows is a specialized inline transliteration of the code
1614 // in enter() and exit(). If we're concerned about I$ bloat another
1615 // option would be to emit TrySlowEnter and TrySlowExit methods
1616 // at startup-time. These methods would accept arguments as
1617 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1618 // indications in the icc.ZFlag. fast_lock and fast_unlock would simply
1619 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1620 // In practice, however, the # of lock sites is bounded and is usually small.
1621 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1622 // if the processor uses simple bimodal branch predictors keyed by EIP
1623 // Since the helper routines would be called from multiple synchronization
1624 // sites.
1625 //
1626 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1627 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1628 // to those specialized methods. That'd give us a mostly platform-independent
1629 // implementation that the JITs could optimize and inline at their pleasure.
1630 // Done correctly, the only time we'd need to cross to native could would be
1631 // to park() or unpark() threads. We'd also need a few more unsafe operators
1632 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1633 // (b) explicit barriers or fence operations.
1634 //
1635 // TODO:
1636 //
1637 // * Arrange for C2 to pass "Self" into fast_lock and fast_unlock in one of the registers (scr).
1638 // This avoids manifesting the Self pointer in the fast_lock and fast_unlock terminals.
1639 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1640 // the lock operators would typically be faster than reifying Self.
1641 //
1642 // * Ideally I'd define the primitives as:
1643 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1644 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1645 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1646 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1647 // Furthermore the register assignments are overconstrained, possibly resulting in
1648 // sub-optimal code near the synchronization site.
1649 //
1650 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1651 // Alternately, use a better sp-proximity test.
1652 //
1653 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1654 // Either one is sufficient to uniquely identify a thread.
1655 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1656 //
1657 // * Intrinsify notify() and notifyAll() for the common cases where the
1658 // object is locked by the calling thread but the waitlist is empty.
1659 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1660 //
1661 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1662 // But beware of excessive branch density on AMD Opterons.
1663 //
1664 // * Both fast_lock and fast_unlock set the ICC.ZF to indicate success
1665 // or failure of the fast path. If the fast path fails then we pass
1666 // control to the slow path, typically in C. In fast_lock and
1667 // fast_unlock we often branch to DONE_LABEL, just to find that C2
1668 // will emit a conditional branch immediately after the node.
1669 // So we have branches to branches and lots of ICC.ZF games.
1670 // Instead, it might be better to have C2 pass a "FailureLabel"
1671 // into fast_lock and fast_unlock. In the case of success, control
1672 // will drop through the node. ICC.ZF is undefined at exit.
1673 // In the case of failure, the node will branch directly to the
1674 // FailureLabel
1675
1676
1677 // obj: object to lock
1678 // box: on-stack box address (displaced header location) - KILLED
1679 // rax,: tmp -- KILLED
1680 // scr: tmp -- KILLED
1681 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1682 Register scrReg, Register cx1Reg, Register cx2Reg,
1683 BiasedLockingCounters* counters,
1684 RTMLockingCounters* rtm_counters,
1685 RTMLockingCounters* stack_rtm_counters,
1686 Metadata* method_data,
1687 bool use_rtm, bool profile_rtm) {
1688 // Ensure the register assignments are disjoint
1689 assert(tmpReg == rax, "");
1690
1691 if (use_rtm) {
1692 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1693 } else {
1694 assert(cx1Reg == noreg, "");
1695 assert(cx2Reg == noreg, "");
1696 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1697 }
1698
1699 if (counters != NULL) {
1700 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1701 }
1702
1703 // Possible cases that we'll encounter in fast_lock
1704 // ------------------------------------------------
1705 // * Inflated
1706 // -- unlocked
1707 // -- Locked
1708 // = by self
1709 // = by other
1710 // * biased
1711 // -- by Self
1712 // -- by other
1713 // * neutral
1714 // * stack-locked
1715 // -- by self
1716 // = sp-proximity test hits
1717 // = sp-proximity test generates false-negative
1718 // -- by other
1719 //
1720
1721 Label IsInflated, DONE_LABEL;
1722
1723 // it's stack-locked, biased or neutral
1724 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1725 // order to reduce the number of conditional branches in the most common cases.
1726 // Beware -- there's a subtle invariant that fetch of the markword
1727 // at [FETCH], below, will never observe a biased encoding (*101b).
1728 // If this invariant is not held we risk exclusion (safety) failure.
1729 if (UseBiasedLocking && !UseOptoBiasInlining) {
1730 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1731 }
1732
1733 #if INCLUDE_RTM_OPT
1734 if (UseRTMForStackLocks && use_rtm) {
1735 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1736 stack_rtm_counters, method_data, profile_rtm,
1737 DONE_LABEL, IsInflated);
1738 }
1739 #endif // INCLUDE_RTM_OPT
1740
1741 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1742 testptr(tmpReg, markWord::monitor_value); // inflated vs stack-locked|neutral|biased
1743 jccb(Assembler::notZero, IsInflated);
1744
1745 // Attempt stack-locking ...
1746 orptr (tmpReg, markWord::unlocked_value);
1747 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1748 lock();
1749 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1750 if (counters != NULL) {
1751 cond_inc32(Assembler::equal,
1752 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1753 }
1754 jcc(Assembler::equal, DONE_LABEL); // Success
1755
1756 // Recursive locking.
1757 // The object is stack-locked: markword contains stack pointer to BasicLock.
1758 // Locked by current thread if difference with current SP is less than one page.
1759 subptr(tmpReg, rsp);
1760 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1761 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1762 movptr(Address(boxReg, 0), tmpReg);
1763 if (counters != NULL) {
1764 cond_inc32(Assembler::equal,
1765 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1766 }
1767 jmp(DONE_LABEL);
1768
1769 bind(IsInflated);
1770 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markWord::monitor_value
1771
1772 #if INCLUDE_RTM_OPT
1773 // Use the same RTM locking code in 32- and 64-bit VM.
1774 if (use_rtm) {
1775 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1776 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1777 } else {
1778 #endif // INCLUDE_RTM_OPT
1779
1780 #ifndef _LP64
1781 // The object is inflated.
1782
1783 // boxReg refers to the on-stack BasicLock in the current frame.
1784 // We'd like to write:
1785 // set box->_displaced_header = markWord::unused_mark(). Any non-0 value suffices.
1786 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1787 // additional latency as we have another ST in the store buffer that must drain.
1788
1789 // avoid ST-before-CAS
1790 // register juggle because we need tmpReg for cmpxchgptr below
1791 movptr(scrReg, boxReg);
1792 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1793
1794 // Optimistic form: consider XORL tmpReg,tmpReg
1795 movptr(tmpReg, NULL_WORD);
1796
1797 // Appears unlocked - try to swing _owner from null to non-null.
1798 // Ideally, I'd manifest "Self" with get_thread and then attempt
1799 // to CAS the register containing Self into m->Owner.
1800 // But we don't have enough registers, so instead we can either try to CAS
1801 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1802 // we later store "Self" into m->Owner. Transiently storing a stack address
1803 // (rsp or the address of the box) into m->owner is harmless.
1804 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1805 lock();
1806 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1807 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1808 // If we weren't able to swing _owner from NULL to the BasicLock
1809 // then take the slow path.
1810 jccb (Assembler::notZero, DONE_LABEL);
1811 // update _owner from BasicLock to thread
1812 get_thread (scrReg); // beware: clobbers ICCs
1813 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1814 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1815
1816 // If the CAS fails we can either retry or pass control to the slow path.
1817 // We use the latter tactic.
1818 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1819 // If the CAS was successful ...
1820 // Self has acquired the lock
1821 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1822 // Intentional fall-through into DONE_LABEL ...
1823 #else // _LP64
1824 // It's inflated and we use scrReg for ObjectMonitor* in this section.
1825 movq(scrReg, tmpReg);
1826 xorq(tmpReg, tmpReg);
1827 lock();
1828 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1829 // Unconditionally set box->_displaced_header = markWord::unused_mark().
1830 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
1831 movptr(Address(boxReg, 0), (int32_t)intptr_t(markWord::unused_mark().value()));
1832 // Intentional fall-through into DONE_LABEL ...
1833 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1834 #endif // _LP64
1835 #if INCLUDE_RTM_OPT
1836 } // use_rtm()
1837 #endif
1838 // DONE_LABEL is a hot target - we'd really like to place it at the
1839 // start of cache line by padding with NOPs.
1840 // See the AMD and Intel software optimization manuals for the
1841 // most efficient "long" NOP encodings.
1842 // Unfortunately none of our alignment mechanisms suffice.
1843 bind(DONE_LABEL);
1844
1845 // At DONE_LABEL the icc ZFlag is set as follows ...
1846 // fast_unlock uses the same protocol.
1847 // ZFlag == 1 -> Success
1848 // ZFlag == 0 -> Failure - force control through the slow path
1849 }
1850
1851 // obj: object to unlock
1852 // box: box address (displaced header location), killed. Must be EAX.
1853 // tmp: killed, cannot be obj nor box.
1854 //
1855 // Some commentary on balanced locking:
1856 //
1857 // fast_lock and fast_unlock are emitted only for provably balanced lock sites.
1858 // Methods that don't have provably balanced locking are forced to run in the
1859 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1860 // The interpreter provides two properties:
1861 // I1: At return-time the interpreter automatically and quietly unlocks any
1862 // objects acquired the current activation (frame). Recall that the
1863 // interpreter maintains an on-stack list of locks currently held by
1864 // a frame.
1865 // I2: If a method attempts to unlock an object that is not held by the
1866 // the frame the interpreter throws IMSX.
1867 //
1868 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1869 // B() doesn't have provably balanced locking so it runs in the interpreter.
1870 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1871 // is still locked by A().
1872 //
1873 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1874 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1875 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1876 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1877 // Arguably given that the spec legislates the JNI case as undefined our implementation
1878 // could reasonably *avoid* checking owner in fast_unlock().
1879 // In the interest of performance we elide m->Owner==Self check in unlock.
1880 // A perfectly viable alternative is to elide the owner check except when
1881 // Xcheck:jni is enabled.
1882
1883 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1884 assert(boxReg == rax, "");
1885 assert_different_registers(objReg, boxReg, tmpReg);
1886
1887 Label DONE_LABEL, Stacked, CheckSucc;
1888
1889 // Critically, the biased locking test must have precedence over
1890 // and appear before the (box->dhw == 0) recursive stack-lock test.
1891 if (UseBiasedLocking && !UseOptoBiasInlining) {
1892 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1893 }
1894
1895 #if INCLUDE_RTM_OPT
1896 if (UseRTMForStackLocks && use_rtm) {
1897 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1898 Label L_regular_unlock;
1899 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1900 andptr(tmpReg, markWord::biased_lock_mask_in_place); // look at 3 lock bits
1901 cmpptr(tmpReg, markWord::unlocked_value); // bits = 001 unlocked
1902 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1903 xend(); // otherwise end...
1904 jmp(DONE_LABEL); // ... and we're done
1905 bind(L_regular_unlock);
1906 }
1907 #endif
1908
1909 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1910 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1911 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
1912 testptr(tmpReg, markWord::monitor_value); // Inflated?
1913 jccb (Assembler::zero, Stacked);
1914
1915 // It's inflated.
1916 #if INCLUDE_RTM_OPT
1917 if (use_rtm) {
1918 Label L_regular_inflated_unlock;
1919 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1920 movptr(boxReg, Address(tmpReg, owner_offset));
1921 testptr(boxReg, boxReg);
1922 jccb(Assembler::notZero, L_regular_inflated_unlock);
1923 xend();
1924 jmpb(DONE_LABEL);
1925 bind(L_regular_inflated_unlock);
1926 }
1927 #endif
1928
1929 // Despite our balanced locking property we still check that m->_owner == Self
1930 // as java routines or native JNI code called by this thread might
1931 // have released the lock.
1932 // Refer to the comments in synchronizer.cpp for how we might encode extra
1933 // state in _succ so we can avoid fetching EntryList|cxq.
1934 //
1935 // I'd like to add more cases in fast_lock() and fast_unlock() --
1936 // such as recursive enter and exit -- but we have to be wary of
1937 // I$ bloat, T$ effects and BP$ effects.
1938 //
1939 // If there's no contention try a 1-0 exit. That is, exit without
1940 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
1941 // we detect and recover from the race that the 1-0 exit admits.
1942 //
1943 // Conceptually fast_unlock() must execute a STST|LDST "release" barrier
1944 // before it STs null into _owner, releasing the lock. Updates
1945 // to data protected by the critical section must be visible before
1946 // we drop the lock (and thus before any other thread could acquire
1947 // the lock and observe the fields protected by the lock).
1948 // IA32's memory-model is SPO, so STs are ordered with respect to
1949 // each other and there's no need for an explicit barrier (fence).
1950 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
1951 #ifndef _LP64
1952 get_thread (boxReg);
1953
1954 // Note that we could employ various encoding schemes to reduce
1955 // the number of loads below (currently 4) to just 2 or 3.
1956 // Refer to the comments in synchronizer.cpp.
1957 // In practice the chain of fetches doesn't seem to impact performance, however.
1958 xorptr(boxReg, boxReg);
1959 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1960 jccb (Assembler::notZero, DONE_LABEL);
1961 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
1962 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1963 jccb (Assembler::notZero, CheckSucc);
1964 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
1965 jmpb (DONE_LABEL);
1966
1967 bind (Stacked);
1968 // It's not inflated and it's not recursively stack-locked and it's not biased.
1969 // It must be stack-locked.
1970 // Try to reset the header to displaced header.
1971 // The "box" value on the stack is stable, so we can reload
1972 // and be assured we observe the same value as above.
1973 movptr(tmpReg, Address(boxReg, 0));
1974 lock();
1975 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
1976 // Intention fall-thru into DONE_LABEL
1977
1978 // DONE_LABEL is a hot target - we'd really like to place it at the
1979 // start of cache line by padding with NOPs.
1980 // See the AMD and Intel software optimization manuals for the
1981 // most efficient "long" NOP encodings.
1982 // Unfortunately none of our alignment mechanisms suffice.
1983 bind (CheckSucc);
1984 #else // _LP64
1985 // It's inflated
1986 xorptr(boxReg, boxReg);
1987 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1988 jccb (Assembler::notZero, DONE_LABEL);
1989 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1990 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
1991 jccb (Assembler::notZero, CheckSucc);
1992 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
1993 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
1994 jmpb (DONE_LABEL);
1995
1996 // Try to avoid passing control into the slow_path ...
1997 Label LSuccess, LGoSlowPath ;
1998 bind (CheckSucc);
1999
2000 // The following optional optimization can be elided if necessary
2001 // Effectively: if (succ == null) goto slow path
2002 // The code reduces the window for a race, however,
2003 // and thus benefits performance.
2004 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2005 jccb (Assembler::zero, LGoSlowPath);
2006
2007 xorptr(boxReg, boxReg);
2008 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
2009 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2010
2011 // Memory barrier/fence
2012 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2013 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2014 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2015 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2016 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2017 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2018 lock(); addl(Address(rsp, 0), 0);
2019
2020 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2021 jccb (Assembler::notZero, LSuccess);
2022
2023 // Rare inopportune interleaving - race.
2024 // The successor vanished in the small window above.
2025 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2026 // We need to ensure progress and succession.
2027 // Try to reacquire the lock.
2028 // If that fails then the new owner is responsible for succession and this
2029 // thread needs to take no further action and can exit via the fast path (success).
2030 // If the re-acquire succeeds then pass control into the slow path.
2031 // As implemented, this latter mode is horrible because we generated more
2032 // coherence traffic on the lock *and* artifically extended the critical section
2033 // length while by virtue of passing control into the slow path.
2034
2035 // box is really RAX -- the following CMPXCHG depends on that binding
2036 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2037 lock();
2038 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2039 // There's no successor so we tried to regrab the lock.
2040 // If that didn't work, then another thread grabbed the
2041 // lock so we're done (and exit was a success).
2042 jccb (Assembler::notEqual, LSuccess);
2043 // Intentional fall-through into slow path
2044
2045 bind (LGoSlowPath);
2046 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2047 jmpb (DONE_LABEL);
2048
2049 bind (LSuccess);
2050 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2051 jmpb (DONE_LABEL);
2052
2053 bind (Stacked);
2054 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2055 lock();
2056 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2057
2058 #endif
2059 bind(DONE_LABEL);
2060 }
2061 #endif // COMPILER2
2062
2063 void MacroAssembler::c2bool(Register x) {
2064 // implements x == 0 ? 0 : 1
2065 // note: must only look at least-significant byte of x
2066 // since C-style booleans are stored in one byte
2067 // only! (was bug)
2068 andl(x, 0xFF);
2069 setb(Assembler::notZero, x);
2070 }
2071
2072 // Wouldn't need if AddressLiteral version had new name
2073 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2074 Assembler::call(L, rtype);
2075 }
2076
2077 void MacroAssembler::call(Register entry) {
2078 Assembler::call(entry);
2079 }
2080
2081 void MacroAssembler::call(AddressLiteral entry) {
2082 if (reachable(entry)) {
2083 Assembler::call_literal(entry.target(), entry.rspec());
2084 } else {
2085 lea(rscratch1, entry);
2086 Assembler::call(rscratch1);
2087 }
2088 }
2089
2090 void MacroAssembler::ic_call(address entry, jint method_index) {
2091 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2092 movptr(rax, (intptr_t)Universe::non_oop_word());
2093 call(AddressLiteral(entry, rh));
2094 }
2095
2096 // Implementation of call_VM versions
2097
2098 void MacroAssembler::call_VM(Register oop_result,
2099 address entry_point,
2100 bool check_exceptions) {
2101 Label C, E;
2102 call(C, relocInfo::none);
2103 jmp(E);
2104
2105 bind(C);
2106 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2107 ret(0);
2108
2109 bind(E);
2110 }
2111
2112 void MacroAssembler::call_VM(Register oop_result,
2113 address entry_point,
2114 Register arg_1,
2115 bool check_exceptions) {
2116 Label C, E;
2117 call(C, relocInfo::none);
2118 jmp(E);
2119
2120 bind(C);
2121 pass_arg1(this, arg_1);
2122 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2123 ret(0);
2124
2125 bind(E);
2126 }
2127
2128 void MacroAssembler::call_VM(Register oop_result,
2129 address entry_point,
2130 Register arg_1,
2131 Register arg_2,
2132 bool check_exceptions) {
2133 Label C, E;
2134 call(C, relocInfo::none);
2135 jmp(E);
2136
2137 bind(C);
2138
2139 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2140
2141 pass_arg2(this, arg_2);
2142 pass_arg1(this, arg_1);
2143 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2144 ret(0);
2145
2146 bind(E);
2147 }
2148
2149 void MacroAssembler::call_VM(Register oop_result,
2150 address entry_point,
2151 Register arg_1,
2152 Register arg_2,
2153 Register arg_3,
2154 bool check_exceptions) {
2155 Label C, E;
2156 call(C, relocInfo::none);
2157 jmp(E);
2158
2159 bind(C);
2160
2161 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2162 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2163 pass_arg3(this, arg_3);
2164
2165 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2166 pass_arg2(this, arg_2);
2167
2168 pass_arg1(this, arg_1);
2169 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2170 ret(0);
2171
2172 bind(E);
2173 }
2174
2175 void MacroAssembler::call_VM(Register oop_result,
2176 Register last_java_sp,
2177 address entry_point,
2178 int number_of_arguments,
2179 bool check_exceptions) {
2180 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2181 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2182 }
2183
2184 void MacroAssembler::call_VM(Register oop_result,
2185 Register last_java_sp,
2186 address entry_point,
2187 Register arg_1,
2188 bool check_exceptions) {
2189 pass_arg1(this, arg_1);
2190 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2191 }
2192
2193 void MacroAssembler::call_VM(Register oop_result,
2194 Register last_java_sp,
2195 address entry_point,
2196 Register arg_1,
2197 Register arg_2,
2198 bool check_exceptions) {
2199
2200 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2201 pass_arg2(this, arg_2);
2202 pass_arg1(this, arg_1);
2203 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2204 }
2205
2206 void MacroAssembler::call_VM(Register oop_result,
2207 Register last_java_sp,
2208 address entry_point,
2209 Register arg_1,
2210 Register arg_2,
2211 Register arg_3,
2212 bool check_exceptions) {
2213 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2214 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2215 pass_arg3(this, arg_3);
2216 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2217 pass_arg2(this, arg_2);
2218 pass_arg1(this, arg_1);
2219 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2220 }
2221
2222 void MacroAssembler::super_call_VM(Register oop_result,
2223 Register last_java_sp,
2224 address entry_point,
2225 int number_of_arguments,
2226 bool check_exceptions) {
2227 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2228 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2229 }
2230
2231 void MacroAssembler::super_call_VM(Register oop_result,
2232 Register last_java_sp,
2233 address entry_point,
2234 Register arg_1,
2235 bool check_exceptions) {
2236 pass_arg1(this, arg_1);
2237 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2238 }
2239
2240 void MacroAssembler::super_call_VM(Register oop_result,
2241 Register last_java_sp,
2242 address entry_point,
2243 Register arg_1,
2244 Register arg_2,
2245 bool check_exceptions) {
2246
2247 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2248 pass_arg2(this, arg_2);
2249 pass_arg1(this, arg_1);
2250 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2251 }
2252
2253 void MacroAssembler::super_call_VM(Register oop_result,
2254 Register last_java_sp,
2255 address entry_point,
2256 Register arg_1,
2257 Register arg_2,
2258 Register arg_3,
2259 bool check_exceptions) {
2260 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2261 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2262 pass_arg3(this, arg_3);
2263 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2264 pass_arg2(this, arg_2);
2265 pass_arg1(this, arg_1);
2266 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2267 }
2268
2269 void MacroAssembler::call_VM_base(Register oop_result,
2270 Register java_thread,
2271 Register last_java_sp,
2272 address entry_point,
2273 int number_of_arguments,
2274 bool check_exceptions) {
2275 // determine java_thread register
2276 if (!java_thread->is_valid()) {
2277 #ifdef _LP64
2278 java_thread = r15_thread;
2279 #else
2280 java_thread = rdi;
2281 get_thread(java_thread);
2282 #endif // LP64
2283 }
2284 // determine last_java_sp register
2285 if (!last_java_sp->is_valid()) {
2286 last_java_sp = rsp;
2287 }
2288 // debugging support
2289 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2290 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2291 #ifdef ASSERT
2292 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2293 // r12 is the heapbase.
2294 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2295 #endif // ASSERT
2296
2297 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2298 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2299
2300 // push java thread (becomes first argument of C function)
2301
2302 NOT_LP64(push(java_thread); number_of_arguments++);
2303 LP64_ONLY(mov(c_rarg0, r15_thread));
2304
2305 // set last Java frame before call
2306 assert(last_java_sp != rbp, "can't use ebp/rbp");
2307
2308 // Only interpreter should have to set fp
2309 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2310
2311 // do the call, remove parameters
2312 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2313
2314 // restore the thread (cannot use the pushed argument since arguments
2315 // may be overwritten by C code generated by an optimizing compiler);
2316 // however can use the register value directly if it is callee saved.
2317 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2318 // rdi & rsi (also r15) are callee saved -> nothing to do
2319 #ifdef ASSERT
2320 guarantee(java_thread != rax, "change this code");
2321 push(rax);
2322 { Label L;
2323 get_thread(rax);
2324 cmpptr(java_thread, rax);
2325 jcc(Assembler::equal, L);
2326 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2327 bind(L);
2328 }
2329 pop(rax);
2330 #endif
2331 } else {
2332 get_thread(java_thread);
2333 }
2334 // reset last Java frame
2335 // Only interpreter should have to clear fp
2336 reset_last_Java_frame(java_thread, true);
2337
2338 // C++ interp handles this in the interpreter
2339 check_and_handle_popframe(java_thread);
2340 check_and_handle_earlyret(java_thread);
2341
2342 if (check_exceptions) {
2343 // check for pending exceptions (java_thread is set upon return)
2344 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2345 #ifndef _LP64
2346 jump_cc(Assembler::notEqual,
2347 RuntimeAddress(StubRoutines::forward_exception_entry()));
2348 #else
2349 // This used to conditionally jump to forward_exception however it is
2350 // possible if we relocate that the branch will not reach. So we must jump
2351 // around so we can always reach
2352
2353 Label ok;
2354 jcc(Assembler::equal, ok);
2355 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2356 bind(ok);
2357 #endif // LP64
2358 }
2359
2360 // get oop result if there is one and reset the value in the thread
2361 if (oop_result->is_valid()) {
2362 get_vm_result(oop_result, java_thread);
2363 }
2364 }
2365
2366 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2367
2368 // Calculate the value for last_Java_sp
2369 // somewhat subtle. call_VM does an intermediate call
2370 // which places a return address on the stack just under the
2371 // stack pointer as the user finsihed with it. This allows
2372 // use to retrieve last_Java_pc from last_Java_sp[-1].
2373 // On 32bit we then have to push additional args on the stack to accomplish
2374 // the actual requested call. On 64bit call_VM only can use register args
2375 // so the only extra space is the return address that call_VM created.
2376 // This hopefully explains the calculations here.
2377
2378 #ifdef _LP64
2379 // We've pushed one address, correct last_Java_sp
2380 lea(rax, Address(rsp, wordSize));
2381 #else
2382 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2383 #endif // LP64
2384
2385 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2386
2387 }
2388
2389 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2390 void MacroAssembler::call_VM_leaf0(address entry_point) {
2391 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2392 }
2393
2394 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2395 call_VM_leaf_base(entry_point, number_of_arguments);
2396 }
2397
2398 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2399 pass_arg0(this, arg_0);
2400 call_VM_leaf(entry_point, 1);
2401 }
2402
2403 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2404
2405 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2406 pass_arg1(this, arg_1);
2407 pass_arg0(this, arg_0);
2408 call_VM_leaf(entry_point, 2);
2409 }
2410
2411 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2412 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2413 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2414 pass_arg2(this, arg_2);
2415 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2416 pass_arg1(this, arg_1);
2417 pass_arg0(this, arg_0);
2418 call_VM_leaf(entry_point, 3);
2419 }
2420
2421 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2422 pass_arg0(this, arg_0);
2423 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2424 }
2425
2426 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2427
2428 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2429 pass_arg1(this, arg_1);
2430 pass_arg0(this, arg_0);
2431 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2432 }
2433
2434 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2435 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2436 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2437 pass_arg2(this, arg_2);
2438 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2439 pass_arg1(this, arg_1);
2440 pass_arg0(this, arg_0);
2441 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2442 }
2443
2444 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2445 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2446 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2447 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2448 pass_arg3(this, arg_3);
2449 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2450 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2451 pass_arg2(this, arg_2);
2452 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2453 pass_arg1(this, arg_1);
2454 pass_arg0(this, arg_0);
2455 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2456 }
2457
2458 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2459 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2460 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2461 verify_oop(oop_result, "broken oop in call_VM_base");
2462 }
2463
2464 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2465 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2466 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2467 }
2468
2469 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2470 }
2471
2472 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2473 }
2474
2475 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2476 if (reachable(src1)) {
2477 cmpl(as_Address(src1), imm);
2478 } else {
2479 lea(rscratch1, src1);
2480 cmpl(Address(rscratch1, 0), imm);
2481 }
2482 }
2483
2484 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2485 assert(!src2.is_lval(), "use cmpptr");
2486 if (reachable(src2)) {
2487 cmpl(src1, as_Address(src2));
2488 } else {
2489 lea(rscratch1, src2);
2490 cmpl(src1, Address(rscratch1, 0));
2491 }
2492 }
2493
2494 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2495 Assembler::cmpl(src1, imm);
2496 }
2497
2498 void MacroAssembler::cmp32(Register src1, Address src2) {
2499 Assembler::cmpl(src1, src2);
2500 }
2501
2502 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2503 ucomisd(opr1, opr2);
2504
2505 Label L;
2506 if (unordered_is_less) {
2507 movl(dst, -1);
2508 jcc(Assembler::parity, L);
2509 jcc(Assembler::below , L);
2510 movl(dst, 0);
2511 jcc(Assembler::equal , L);
2512 increment(dst);
2513 } else { // unordered is greater
2514 movl(dst, 1);
2515 jcc(Assembler::parity, L);
2516 jcc(Assembler::above , L);
2517 movl(dst, 0);
2518 jcc(Assembler::equal , L);
2519 decrementl(dst);
2520 }
2521 bind(L);
2522 }
2523
2524 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2525 ucomiss(opr1, opr2);
2526
2527 Label L;
2528 if (unordered_is_less) {
2529 movl(dst, -1);
2530 jcc(Assembler::parity, L);
2531 jcc(Assembler::below , L);
2532 movl(dst, 0);
2533 jcc(Assembler::equal , L);
2534 increment(dst);
2535 } else { // unordered is greater
2536 movl(dst, 1);
2537 jcc(Assembler::parity, L);
2538 jcc(Assembler::above , L);
2539 movl(dst, 0);
2540 jcc(Assembler::equal , L);
2541 decrementl(dst);
2542 }
2543 bind(L);
2544 }
2545
2546
2547 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2548 if (reachable(src1)) {
2549 cmpb(as_Address(src1), imm);
2550 } else {
2551 lea(rscratch1, src1);
2552 cmpb(Address(rscratch1, 0), imm);
2553 }
2554 }
2555
2556 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2557 #ifdef _LP64
2558 if (src2.is_lval()) {
2559 movptr(rscratch1, src2);
2560 Assembler::cmpq(src1, rscratch1);
2561 } else if (reachable(src2)) {
2562 cmpq(src1, as_Address(src2));
2563 } else {
2564 lea(rscratch1, src2);
2565 Assembler::cmpq(src1, Address(rscratch1, 0));
2566 }
2567 #else
2568 if (src2.is_lval()) {
2569 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2570 } else {
2571 cmpl(src1, as_Address(src2));
2572 }
2573 #endif // _LP64
2574 }
2575
2576 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2577 assert(src2.is_lval(), "not a mem-mem compare");
2578 #ifdef _LP64
2579 // moves src2's literal address
2580 movptr(rscratch1, src2);
2581 Assembler::cmpq(src1, rscratch1);
2582 #else
2583 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2584 #endif // _LP64
2585 }
2586
2587 void MacroAssembler::cmpoop(Register src1, Register src2) {
2588 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2589 bs->obj_equals(this, src1, src2);
2590 }
2591
2592 void MacroAssembler::cmpoop(Register src1, Address src2) {
2593 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2594 bs->obj_equals(this, src1, src2);
2595 }
2596
2597 #ifdef _LP64
2598 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2599 movoop(rscratch1, src2);
2600 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2601 bs->obj_equals(this, src1, rscratch1);
2602 }
2603 #endif
2604
2605 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2606 if (reachable(adr)) {
2607 lock();
2608 cmpxchgptr(reg, as_Address(adr));
2609 } else {
2610 lea(rscratch1, adr);
2611 lock();
2612 cmpxchgptr(reg, Address(rscratch1, 0));
2613 }
2614 }
2615
2616 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2617 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2618 }
2619
2620 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2621 if (reachable(src)) {
2622 Assembler::comisd(dst, as_Address(src));
2623 } else {
2624 lea(rscratch1, src);
2625 Assembler::comisd(dst, Address(rscratch1, 0));
2626 }
2627 }
2628
2629 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2630 if (reachable(src)) {
2631 Assembler::comiss(dst, as_Address(src));
2632 } else {
2633 lea(rscratch1, src);
2634 Assembler::comiss(dst, Address(rscratch1, 0));
2635 }
2636 }
2637
2638
2639 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2640 Condition negated_cond = negate_condition(cond);
2641 Label L;
2642 jcc(negated_cond, L);
2643 pushf(); // Preserve flags
2644 atomic_incl(counter_addr);
2645 popf();
2646 bind(L);
2647 }
2648
2649 int MacroAssembler::corrected_idivl(Register reg) {
2650 // Full implementation of Java idiv and irem; checks for
2651 // special case as described in JVM spec., p.243 & p.271.
2652 // The function returns the (pc) offset of the idivl
2653 // instruction - may be needed for implicit exceptions.
2654 //
2655 // normal case special case
2656 //
2657 // input : rax,: dividend min_int
2658 // reg: divisor (may not be rax,/rdx) -1
2659 //
2660 // output: rax,: quotient (= rax, idiv reg) min_int
2661 // rdx: remainder (= rax, irem reg) 0
2662 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2663 const int min_int = 0x80000000;
2664 Label normal_case, special_case;
2665
2666 // check for special case
2667 cmpl(rax, min_int);
2668 jcc(Assembler::notEqual, normal_case);
2669 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2670 cmpl(reg, -1);
2671 jcc(Assembler::equal, special_case);
2672
2673 // handle normal case
2674 bind(normal_case);
2675 cdql();
2676 int idivl_offset = offset();
2677 idivl(reg);
2678
2679 // normal and special case exit
2680 bind(special_case);
2681
2682 return idivl_offset;
2683 }
2684
2685
2686
2687 void MacroAssembler::decrementl(Register reg, int value) {
2688 if (value == min_jint) {subl(reg, value) ; return; }
2689 if (value < 0) { incrementl(reg, -value); return; }
2690 if (value == 0) { ; return; }
2691 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2692 /* else */ { subl(reg, value) ; return; }
2693 }
2694
2695 void MacroAssembler::decrementl(Address dst, int value) {
2696 if (value == min_jint) {subl(dst, value) ; return; }
2697 if (value < 0) { incrementl(dst, -value); return; }
2698 if (value == 0) { ; return; }
2699 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2700 /* else */ { subl(dst, value) ; return; }
2701 }
2702
2703 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2704 assert (shift_value > 0, "illegal shift value");
2705 Label _is_positive;
2706 testl (reg, reg);
2707 jcc (Assembler::positive, _is_positive);
2708 int offset = (1 << shift_value) - 1 ;
2709
2710 if (offset == 1) {
2711 incrementl(reg);
2712 } else {
2713 addl(reg, offset);
2714 }
2715
2716 bind (_is_positive);
2717 sarl(reg, shift_value);
2718 }
2719
2720 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2721 if (reachable(src)) {
2722 Assembler::divsd(dst, as_Address(src));
2723 } else {
2724 lea(rscratch1, src);
2725 Assembler::divsd(dst, Address(rscratch1, 0));
2726 }
2727 }
2728
2729 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2730 if (reachable(src)) {
2731 Assembler::divss(dst, as_Address(src));
2732 } else {
2733 lea(rscratch1, src);
2734 Assembler::divss(dst, Address(rscratch1, 0));
2735 }
2736 }
2737
2738 // !defined(COMPILER2) is because of stupid core builds
2739 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2740 void MacroAssembler::empty_FPU_stack() {
2741 if (VM_Version::supports_mmx()) {
2742 emms();
2743 } else {
2744 for (int i = 8; i-- > 0; ) ffree(i);
2745 }
2746 }
2747 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2748
2749
2750 void MacroAssembler::enter() {
2751 push(rbp);
2752 mov(rbp, rsp);
2753 }
2754
2755 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2756 void MacroAssembler::fat_nop() {
2757 if (UseAddressNop) {
2758 addr_nop_5();
2759 } else {
2760 emit_int8(0x26); // es:
2761 emit_int8(0x2e); // cs:
2762 emit_int8(0x64); // fs:
2763 emit_int8(0x65); // gs:
2764 emit_int8((unsigned char)0x90);
2765 }
2766 }
2767
2768 void MacroAssembler::fcmp(Register tmp) {
2769 fcmp(tmp, 1, true, true);
2770 }
2771
2772 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2773 assert(!pop_right || pop_left, "usage error");
2774 if (VM_Version::supports_cmov()) {
2775 assert(tmp == noreg, "unneeded temp");
2776 if (pop_left) {
2777 fucomip(index);
2778 } else {
2779 fucomi(index);
2780 }
2781 if (pop_right) {
2782 fpop();
2783 }
2784 } else {
2785 assert(tmp != noreg, "need temp");
2786 if (pop_left) {
2787 if (pop_right) {
2788 fcompp();
2789 } else {
2790 fcomp(index);
2791 }
2792 } else {
2793 fcom(index);
2794 }
2795 // convert FPU condition into eflags condition via rax,
2796 save_rax(tmp);
2797 fwait(); fnstsw_ax();
2798 sahf();
2799 restore_rax(tmp);
2800 }
2801 // condition codes set as follows:
2802 //
2803 // CF (corresponds to C0) if x < y
2804 // PF (corresponds to C2) if unordered
2805 // ZF (corresponds to C3) if x = y
2806 }
2807
2808 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2809 fcmp2int(dst, unordered_is_less, 1, true, true);
2810 }
2811
2812 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2813 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2814 Label L;
2815 if (unordered_is_less) {
2816 movl(dst, -1);
2817 jcc(Assembler::parity, L);
2818 jcc(Assembler::below , L);
2819 movl(dst, 0);
2820 jcc(Assembler::equal , L);
2821 increment(dst);
2822 } else { // unordered is greater
2823 movl(dst, 1);
2824 jcc(Assembler::parity, L);
2825 jcc(Assembler::above , L);
2826 movl(dst, 0);
2827 jcc(Assembler::equal , L);
2828 decrementl(dst);
2829 }
2830 bind(L);
2831 }
2832
2833 void MacroAssembler::fld_d(AddressLiteral src) {
2834 fld_d(as_Address(src));
2835 }
2836
2837 void MacroAssembler::fld_s(AddressLiteral src) {
2838 fld_s(as_Address(src));
2839 }
2840
2841 void MacroAssembler::fld_x(AddressLiteral src) {
2842 Assembler::fld_x(as_Address(src));
2843 }
2844
2845 void MacroAssembler::fldcw(AddressLiteral src) {
2846 Assembler::fldcw(as_Address(src));
2847 }
2848
2849 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2850 if (reachable(src)) {
2851 Assembler::mulpd(dst, as_Address(src));
2852 } else {
2853 lea(rscratch1, src);
2854 Assembler::mulpd(dst, Address(rscratch1, 0));
2855 }
2856 }
2857
2858 void MacroAssembler::increase_precision() {
2859 subptr(rsp, BytesPerWord);
2860 fnstcw(Address(rsp, 0));
2861 movl(rax, Address(rsp, 0));
2862 orl(rax, 0x300);
2863 push(rax);
2864 fldcw(Address(rsp, 0));
2865 pop(rax);
2866 }
2867
2868 void MacroAssembler::restore_precision() {
2869 fldcw(Address(rsp, 0));
2870 addptr(rsp, BytesPerWord);
2871 }
2872
2873 void MacroAssembler::fpop() {
2874 ffree();
2875 fincstp();
2876 }
2877
2878 void MacroAssembler::load_float(Address src) {
2879 if (UseSSE >= 1) {
2880 movflt(xmm0, src);
2881 } else {
2882 LP64_ONLY(ShouldNotReachHere());
2883 NOT_LP64(fld_s(src));
2884 }
2885 }
2886
2887 void MacroAssembler::store_float(Address dst) {
2888 if (UseSSE >= 1) {
2889 movflt(dst, xmm0);
2890 } else {
2891 LP64_ONLY(ShouldNotReachHere());
2892 NOT_LP64(fstp_s(dst));
2893 }
2894 }
2895
2896 void MacroAssembler::load_double(Address src) {
2897 if (UseSSE >= 2) {
2898 movdbl(xmm0, src);
2899 } else {
2900 LP64_ONLY(ShouldNotReachHere());
2901 NOT_LP64(fld_d(src));
2902 }
2903 }
2904
2905 void MacroAssembler::store_double(Address dst) {
2906 if (UseSSE >= 2) {
2907 movdbl(dst, xmm0);
2908 } else {
2909 LP64_ONLY(ShouldNotReachHere());
2910 NOT_LP64(fstp_d(dst));
2911 }
2912 }
2913
2914 void MacroAssembler::fremr(Register tmp) {
2915 save_rax(tmp);
2916 { Label L;
2917 bind(L);
2918 fprem();
2919 fwait(); fnstsw_ax();
2920 #ifdef _LP64
2921 testl(rax, 0x400);
2922 jcc(Assembler::notEqual, L);
2923 #else
2924 sahf();
2925 jcc(Assembler::parity, L);
2926 #endif // _LP64
2927 }
2928 restore_rax(tmp);
2929 // Result is in ST0.
2930 // Note: fxch & fpop to get rid of ST1
2931 // (otherwise FPU stack could overflow eventually)
2932 fxch(1);
2933 fpop();
2934 }
2935
2936 // dst = c = a * b + c
2937 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2938 Assembler::vfmadd231sd(c, a, b);
2939 if (dst != c) {
2940 movdbl(dst, c);
2941 }
2942 }
2943
2944 // dst = c = a * b + c
2945 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2946 Assembler::vfmadd231ss(c, a, b);
2947 if (dst != c) {
2948 movflt(dst, c);
2949 }
2950 }
2951
2952 // dst = c = a * b + c
2953 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2954 Assembler::vfmadd231pd(c, a, b, vector_len);
2955 if (dst != c) {
2956 vmovdqu(dst, c);
2957 }
2958 }
2959
2960 // dst = c = a * b + c
2961 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2962 Assembler::vfmadd231ps(c, a, b, vector_len);
2963 if (dst != c) {
2964 vmovdqu(dst, c);
2965 }
2966 }
2967
2968 // dst = c = a * b + c
2969 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2970 Assembler::vfmadd231pd(c, a, b, vector_len);
2971 if (dst != c) {
2972 vmovdqu(dst, c);
2973 }
2974 }
2975
2976 // dst = c = a * b + c
2977 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2978 Assembler::vfmadd231ps(c, a, b, vector_len);
2979 if (dst != c) {
2980 vmovdqu(dst, c);
2981 }
2982 }
2983
2984 void MacroAssembler::incrementl(AddressLiteral dst) {
2985 if (reachable(dst)) {
2986 incrementl(as_Address(dst));
2987 } else {
2988 lea(rscratch1, dst);
2989 incrementl(Address(rscratch1, 0));
2990 }
2991 }
2992
2993 void MacroAssembler::incrementl(ArrayAddress dst) {
2994 incrementl(as_Address(dst));
2995 }
2996
2997 void MacroAssembler::incrementl(Register reg, int value) {
2998 if (value == min_jint) {addl(reg, value) ; return; }
2999 if (value < 0) { decrementl(reg, -value); return; }
3000 if (value == 0) { ; return; }
3001 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3002 /* else */ { addl(reg, value) ; return; }
3003 }
3004
3005 void MacroAssembler::incrementl(Address dst, int value) {
3006 if (value == min_jint) {addl(dst, value) ; return; }
3007 if (value < 0) { decrementl(dst, -value); return; }
3008 if (value == 0) { ; return; }
3009 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3010 /* else */ { addl(dst, value) ; return; }
3011 }
3012
3013 void MacroAssembler::jump(AddressLiteral dst) {
3014 if (reachable(dst)) {
3015 jmp_literal(dst.target(), dst.rspec());
3016 } else {
3017 lea(rscratch1, dst);
3018 jmp(rscratch1);
3019 }
3020 }
3021
3022 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3023 if (reachable(dst)) {
3024 InstructionMark im(this);
3025 relocate(dst.reloc());
3026 const int short_size = 2;
3027 const int long_size = 6;
3028 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3029 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3030 // 0111 tttn #8-bit disp
3031 emit_int8(0x70 | cc);
3032 emit_int8((offs - short_size) & 0xFF);
3033 } else {
3034 // 0000 1111 1000 tttn #32-bit disp
3035 emit_int8(0x0F);
3036 emit_int8((unsigned char)(0x80 | cc));
3037 emit_int32(offs - long_size);
3038 }
3039 } else {
3040 #ifdef ASSERT
3041 warning("reversing conditional branch");
3042 #endif /* ASSERT */
3043 Label skip;
3044 jccb(reverse[cc], skip);
3045 lea(rscratch1, dst);
3046 Assembler::jmp(rscratch1);
3047 bind(skip);
3048 }
3049 }
3050
3051 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3052 if (reachable(src)) {
3053 Assembler::ldmxcsr(as_Address(src));
3054 } else {
3055 lea(rscratch1, src);
3056 Assembler::ldmxcsr(Address(rscratch1, 0));
3057 }
3058 }
3059
3060 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3061 int off;
3062 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3063 off = offset();
3064 movsbl(dst, src); // movsxb
3065 } else {
3066 off = load_unsigned_byte(dst, src);
3067 shll(dst, 24);
3068 sarl(dst, 24);
3069 }
3070 return off;
3071 }
3072
3073 // Note: load_signed_short used to be called load_signed_word.
3074 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3075 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3076 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3077 int MacroAssembler::load_signed_short(Register dst, Address src) {
3078 int off;
3079 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3080 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3081 // version but this is what 64bit has always done. This seems to imply
3082 // that users are only using 32bits worth.
3083 off = offset();
3084 movswl(dst, src); // movsxw
3085 } else {
3086 off = load_unsigned_short(dst, src);
3087 shll(dst, 16);
3088 sarl(dst, 16);
3089 }
3090 return off;
3091 }
3092
3093 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3094 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3095 // and "3.9 Partial Register Penalties", p. 22).
3096 int off;
3097 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3098 off = offset();
3099 movzbl(dst, src); // movzxb
3100 } else {
3101 xorl(dst, dst);
3102 off = offset();
3103 movb(dst, src);
3104 }
3105 return off;
3106 }
3107
3108 // Note: load_unsigned_short used to be called load_unsigned_word.
3109 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3110 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3111 // and "3.9 Partial Register Penalties", p. 22).
3112 int off;
3113 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3114 off = offset();
3115 movzwl(dst, src); // movzxw
3116 } else {
3117 xorl(dst, dst);
3118 off = offset();
3119 movw(dst, src);
3120 }
3121 return off;
3122 }
3123
3124 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3125 switch (size_in_bytes) {
3126 #ifndef _LP64
3127 case 8:
3128 assert(dst2 != noreg, "second dest register required");
3129 movl(dst, src);
3130 movl(dst2, src.plus_disp(BytesPerInt));
3131 break;
3132 #else
3133 case 8: movq(dst, src); break;
3134 #endif
3135 case 4: movl(dst, src); break;
3136 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3137 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3138 default: ShouldNotReachHere();
3139 }
3140 }
3141
3142 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3143 switch (size_in_bytes) {
3144 #ifndef _LP64
3145 case 8:
3146 assert(src2 != noreg, "second source register required");
3147 movl(dst, src);
3148 movl(dst.plus_disp(BytesPerInt), src2);
3149 break;
3150 #else
3151 case 8: movq(dst, src); break;
3152 #endif
3153 case 4: movl(dst, src); break;
3154 case 2: movw(dst, src); break;
3155 case 1: movb(dst, src); break;
3156 default: ShouldNotReachHere();
3157 }
3158 }
3159
3160 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3161 if (reachable(dst)) {
3162 movl(as_Address(dst), src);
3163 } else {
3164 lea(rscratch1, dst);
3165 movl(Address(rscratch1, 0), src);
3166 }
3167 }
3168
3169 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3170 if (reachable(src)) {
3171 movl(dst, as_Address(src));
3172 } else {
3173 lea(rscratch1, src);
3174 movl(dst, Address(rscratch1, 0));
3175 }
3176 }
3177
3178 // C++ bool manipulation
3179
3180 void MacroAssembler::movbool(Register dst, Address src) {
3181 if(sizeof(bool) == 1)
3182 movb(dst, src);
3183 else if(sizeof(bool) == 2)
3184 movw(dst, src);
3185 else if(sizeof(bool) == 4)
3186 movl(dst, src);
3187 else
3188 // unsupported
3189 ShouldNotReachHere();
3190 }
3191
3192 void MacroAssembler::movbool(Address dst, bool boolconst) {
3193 if(sizeof(bool) == 1)
3194 movb(dst, (int) boolconst);
3195 else if(sizeof(bool) == 2)
3196 movw(dst, (int) boolconst);
3197 else if(sizeof(bool) == 4)
3198 movl(dst, (int) boolconst);
3199 else
3200 // unsupported
3201 ShouldNotReachHere();
3202 }
3203
3204 void MacroAssembler::movbool(Address dst, Register src) {
3205 if(sizeof(bool) == 1)
3206 movb(dst, src);
3207 else if(sizeof(bool) == 2)
3208 movw(dst, src);
3209 else if(sizeof(bool) == 4)
3210 movl(dst, src);
3211 else
3212 // unsupported
3213 ShouldNotReachHere();
3214 }
3215
3216 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3217 movb(as_Address(dst), src);
3218 }
3219
3220 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3221 if (reachable(src)) {
3222 movdl(dst, as_Address(src));
3223 } else {
3224 lea(rscratch1, src);
3225 movdl(dst, Address(rscratch1, 0));
3226 }
3227 }
3228
3229 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3230 if (reachable(src)) {
3231 movq(dst, as_Address(src));
3232 } else {
3233 lea(rscratch1, src);
3234 movq(dst, Address(rscratch1, 0));
3235 }
3236 }
3237
3238 #ifdef COMPILER2
3239 void MacroAssembler::setvectmask(Register dst, Register src) {
3240 guarantee(PostLoopMultiversioning, "must be");
3241 Assembler::movl(dst, 1);
3242 Assembler::shlxl(dst, dst, src);
3243 Assembler::decl(dst);
3244 Assembler::kmovdl(k1, dst);
3245 Assembler::movl(dst, src);
3246 }
3247
3248 void MacroAssembler::restorevectmask() {
3249 guarantee(PostLoopMultiversioning, "must be");
3250 Assembler::knotwl(k1, k0);
3251 }
3252 #endif // COMPILER2
3253
3254 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3255 if (reachable(src)) {
3256 if (UseXmmLoadAndClearUpper) {
3257 movsd (dst, as_Address(src));
3258 } else {
3259 movlpd(dst, as_Address(src));
3260 }
3261 } else {
3262 lea(rscratch1, src);
3263 if (UseXmmLoadAndClearUpper) {
3264 movsd (dst, Address(rscratch1, 0));
3265 } else {
3266 movlpd(dst, Address(rscratch1, 0));
3267 }
3268 }
3269 }
3270
3271 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3272 if (reachable(src)) {
3273 movss(dst, as_Address(src));
3274 } else {
3275 lea(rscratch1, src);
3276 movss(dst, Address(rscratch1, 0));
3277 }
3278 }
3279
3280 void MacroAssembler::movptr(Register dst, Register src) {
3281 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3282 }
3283
3284 void MacroAssembler::movptr(Register dst, Address src) {
3285 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3286 }
3287
3288 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3289 void MacroAssembler::movptr(Register dst, intptr_t src) {
3290 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3291 }
3292
3293 void MacroAssembler::movptr(Address dst, Register src) {
3294 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3295 }
3296
3297 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3298 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3299 Assembler::movdqu(dst, src);
3300 }
3301
3302 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3303 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3304 Assembler::movdqu(dst, src);
3305 }
3306
3307 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3308 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3309 Assembler::movdqu(dst, src);
3310 }
3311
3312 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3313 if (reachable(src)) {
3314 movdqu(dst, as_Address(src));
3315 } else {
3316 lea(scratchReg, src);
3317 movdqu(dst, Address(scratchReg, 0));
3318 }
3319 }
3320
3321 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3322 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3323 Assembler::vmovdqu(dst, src);
3324 }
3325
3326 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3327 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3328 Assembler::vmovdqu(dst, src);
3329 }
3330
3331 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3332 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3333 Assembler::vmovdqu(dst, src);
3334 }
3335
3336 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3337 if (reachable(src)) {
3338 vmovdqu(dst, as_Address(src));
3339 }
3340 else {
3341 lea(scratch_reg, src);
3342 vmovdqu(dst, Address(scratch_reg, 0));
3343 }
3344 }
3345
3346 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3347 if (reachable(src)) {
3348 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3349 } else {
3350 lea(rscratch, src);
3351 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3352 }
3353 }
3354
3355 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3356 if (reachable(src)) {
3357 Assembler::movdqa(dst, as_Address(src));
3358 } else {
3359 lea(rscratch1, src);
3360 Assembler::movdqa(dst, Address(rscratch1, 0));
3361 }
3362 }
3363
3364 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3365 if (reachable(src)) {
3366 Assembler::movsd(dst, as_Address(src));
3367 } else {
3368 lea(rscratch1, src);
3369 Assembler::movsd(dst, Address(rscratch1, 0));
3370 }
3371 }
3372
3373 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3374 if (reachable(src)) {
3375 Assembler::movss(dst, as_Address(src));
3376 } else {
3377 lea(rscratch1, src);
3378 Assembler::movss(dst, Address(rscratch1, 0));
3379 }
3380 }
3381
3382 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3383 if (reachable(src)) {
3384 Assembler::mulsd(dst, as_Address(src));
3385 } else {
3386 lea(rscratch1, src);
3387 Assembler::mulsd(dst, Address(rscratch1, 0));
3388 }
3389 }
3390
3391 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3392 if (reachable(src)) {
3393 Assembler::mulss(dst, as_Address(src));
3394 } else {
3395 lea(rscratch1, src);
3396 Assembler::mulss(dst, Address(rscratch1, 0));
3397 }
3398 }
3399
3400 void MacroAssembler::null_check(Register reg, int offset) {
3401 if (needs_explicit_null_check(offset)) {
3402 // provoke OS NULL exception if reg = NULL by
3403 // accessing M[reg] w/o changing any (non-CC) registers
3404 // NOTE: cmpl is plenty here to provoke a segv
3405 cmpptr(rax, Address(reg, 0));
3406 // Note: should probably use testl(rax, Address(reg, 0));
3407 // may be shorter code (however, this version of
3408 // testl needs to be implemented first)
3409 } else {
3410 // nothing to do, (later) access of M[reg + offset]
3411 // will provoke OS NULL exception if reg = NULL
3412 }
3413 }
3414
3415 void MacroAssembler::os_breakpoint() {
3416 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3417 // (e.g., MSVC can't call ps() otherwise)
3418 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3419 }
3420
3421 void MacroAssembler::unimplemented(const char* what) {
3422 const char* buf = NULL;
3423 {
3424 ResourceMark rm;
3425 stringStream ss;
3426 ss.print("unimplemented: %s", what);
3427 buf = code_string(ss.as_string());
3428 }
3429 stop(buf);
3430 }
3431
3432 #ifdef _LP64
3433 #define XSTATE_BV 0x200
3434 #endif
3435
3436 void MacroAssembler::pop_CPU_state() {
3437 pop_FPU_state();
3438 pop_IU_state();
3439 }
3440
3441 void MacroAssembler::pop_FPU_state() {
3442 #ifndef _LP64
3443 frstor(Address(rsp, 0));
3444 #else
3445 fxrstor(Address(rsp, 0));
3446 #endif
3447 addptr(rsp, FPUStateSizeInWords * wordSize);
3448 }
3449
3450 void MacroAssembler::pop_IU_state() {
3451 popa();
3452 LP64_ONLY(addq(rsp, 8));
3453 popf();
3454 }
3455
3456 // Save Integer and Float state
3457 // Warning: Stack must be 16 byte aligned (64bit)
3458 void MacroAssembler::push_CPU_state() {
3459 push_IU_state();
3460 push_FPU_state();
3461 }
3462
3463 void MacroAssembler::push_FPU_state() {
3464 subptr(rsp, FPUStateSizeInWords * wordSize);
3465 #ifndef _LP64
3466 fnsave(Address(rsp, 0));
3467 fwait();
3468 #else
3469 fxsave(Address(rsp, 0));
3470 #endif // LP64
3471 }
3472
3473 void MacroAssembler::push_IU_state() {
3474 // Push flags first because pusha kills them
3475 pushf();
3476 // Make sure rsp stays 16-byte aligned
3477 LP64_ONLY(subq(rsp, 8));
3478 pusha();
3479 }
3480
3481 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3482 if (!java_thread->is_valid()) {
3483 java_thread = rdi;
3484 get_thread(java_thread);
3485 }
3486 // we must set sp to zero to clear frame
3487 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3488 if (clear_fp) {
3489 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3490 }
3491
3492 // Always clear the pc because it could have been set by make_walkable()
3493 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3494
3495 vzeroupper();
3496 }
3497
3498 void MacroAssembler::restore_rax(Register tmp) {
3499 if (tmp == noreg) pop(rax);
3500 else if (tmp != rax) mov(rax, tmp);
3501 }
3502
3503 void MacroAssembler::round_to(Register reg, int modulus) {
3504 addptr(reg, modulus - 1);
3505 andptr(reg, -modulus);
3506 }
3507
3508 void MacroAssembler::save_rax(Register tmp) {
3509 if (tmp == noreg) push(rax);
3510 else if (tmp != rax) mov(tmp, rax);
3511 }
3512
3513 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3514 if (SafepointMechanism::uses_thread_local_poll()) {
3515 #ifdef _LP64
3516 assert(thread_reg == r15_thread, "should be");
3517 #else
3518 if (thread_reg == noreg) {
3519 thread_reg = temp_reg;
3520 get_thread(thread_reg);
3521 }
3522 #endif
3523 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3524 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3525 } else {
3526 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3527 SafepointSynchronize::_not_synchronized);
3528 jcc(Assembler::notEqual, slow_path);
3529 }
3530 }
3531
3532 // Calls to C land
3533 //
3534 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3535 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3536 // has to be reset to 0. This is required to allow proper stack traversal.
3537 void MacroAssembler::set_last_Java_frame(Register java_thread,
3538 Register last_java_sp,
3539 Register last_java_fp,
3540 address last_java_pc) {
3541 vzeroupper();
3542 // determine java_thread register
3543 if (!java_thread->is_valid()) {
3544 java_thread = rdi;
3545 get_thread(java_thread);
3546 }
3547 // determine last_java_sp register
3548 if (!last_java_sp->is_valid()) {
3549 last_java_sp = rsp;
3550 }
3551
3552 // last_java_fp is optional
3553
3554 if (last_java_fp->is_valid()) {
3555 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3556 }
3557
3558 // last_java_pc is optional
3559
3560 if (last_java_pc != NULL) {
3561 lea(Address(java_thread,
3562 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3563 InternalAddress(last_java_pc));
3564
3565 }
3566 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3567 }
3568
3569 void MacroAssembler::shlptr(Register dst, int imm8) {
3570 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3571 }
3572
3573 void MacroAssembler::shrptr(Register dst, int imm8) {
3574 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3575 }
3576
3577 void MacroAssembler::sign_extend_byte(Register reg) {
3578 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3579 movsbl(reg, reg); // movsxb
3580 } else {
3581 shll(reg, 24);
3582 sarl(reg, 24);
3583 }
3584 }
3585
3586 void MacroAssembler::sign_extend_short(Register reg) {
3587 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3588 movswl(reg, reg); // movsxw
3589 } else {
3590 shll(reg, 16);
3591 sarl(reg, 16);
3592 }
3593 }
3594
3595 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3596 assert(reachable(src), "Address should be reachable");
3597 testl(dst, as_Address(src));
3598 }
3599
3600 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3601 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3602 Assembler::pcmpeqb(dst, src);
3603 }
3604
3605 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3606 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3607 Assembler::pcmpeqw(dst, src);
3608 }
3609
3610 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3611 assert((dst->encoding() < 16),"XMM register should be 0-15");
3612 Assembler::pcmpestri(dst, src, imm8);
3613 }
3614
3615 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3616 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3617 Assembler::pcmpestri(dst, src, imm8);
3618 }
3619
3620 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3621 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3622 Assembler::pmovzxbw(dst, src);
3623 }
3624
3625 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3626 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3627 Assembler::pmovzxbw(dst, src);
3628 }
3629
3630 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3631 assert((src->encoding() < 16),"XMM register should be 0-15");
3632 Assembler::pmovmskb(dst, src);
3633 }
3634
3635 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3636 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3637 Assembler::ptest(dst, src);
3638 }
3639
3640 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3641 if (reachable(src)) {
3642 Assembler::sqrtsd(dst, as_Address(src));
3643 } else {
3644 lea(rscratch1, src);
3645 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3646 }
3647 }
3648
3649 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3650 if (reachable(src)) {
3651 Assembler::sqrtss(dst, as_Address(src));
3652 } else {
3653 lea(rscratch1, src);
3654 Assembler::sqrtss(dst, Address(rscratch1, 0));
3655 }
3656 }
3657
3658 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3659 if (reachable(src)) {
3660 Assembler::subsd(dst, as_Address(src));
3661 } else {
3662 lea(rscratch1, src);
3663 Assembler::subsd(dst, Address(rscratch1, 0));
3664 }
3665 }
3666
3667 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
3668 if (reachable(src)) {
3669 Assembler::roundsd(dst, as_Address(src), rmode);
3670 } else {
3671 lea(scratch_reg, src);
3672 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
3673 }
3674 }
3675
3676 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3677 if (reachable(src)) {
3678 Assembler::subss(dst, as_Address(src));
3679 } else {
3680 lea(rscratch1, src);
3681 Assembler::subss(dst, Address(rscratch1, 0));
3682 }
3683 }
3684
3685 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3686 if (reachable(src)) {
3687 Assembler::ucomisd(dst, as_Address(src));
3688 } else {
3689 lea(rscratch1, src);
3690 Assembler::ucomisd(dst, Address(rscratch1, 0));
3691 }
3692 }
3693
3694 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3695 if (reachable(src)) {
3696 Assembler::ucomiss(dst, as_Address(src));
3697 } else {
3698 lea(rscratch1, src);
3699 Assembler::ucomiss(dst, Address(rscratch1, 0));
3700 }
3701 }
3702
3703 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3704 // Used in sign-bit flipping with aligned address.
3705 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3706 if (reachable(src)) {
3707 Assembler::xorpd(dst, as_Address(src));
3708 } else {
3709 lea(scratch_reg, src);
3710 Assembler::xorpd(dst, Address(scratch_reg, 0));
3711 }
3712 }
3713
3714 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3715 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3716 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3717 }
3718 else {
3719 Assembler::xorpd(dst, src);
3720 }
3721 }
3722
3723 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3724 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3725 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3726 } else {
3727 Assembler::xorps(dst, src);
3728 }
3729 }
3730
3731 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3732 // Used in sign-bit flipping with aligned address.
3733 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3734 if (reachable(src)) {
3735 Assembler::xorps(dst, as_Address(src));
3736 } else {
3737 lea(scratch_reg, src);
3738 Assembler::xorps(dst, Address(scratch_reg, 0));
3739 }
3740 }
3741
3742 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3743 // Used in sign-bit flipping with aligned address.
3744 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3745 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3746 if (reachable(src)) {
3747 Assembler::pshufb(dst, as_Address(src));
3748 } else {
3749 lea(rscratch1, src);
3750 Assembler::pshufb(dst, Address(rscratch1, 0));
3751 }
3752 }
3753
3754 // AVX 3-operands instructions
3755
3756 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3757 if (reachable(src)) {
3758 vaddsd(dst, nds, as_Address(src));
3759 } else {
3760 lea(rscratch1, src);
3761 vaddsd(dst, nds, Address(rscratch1, 0));
3762 }
3763 }
3764
3765 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3766 if (reachable(src)) {
3767 vaddss(dst, nds, as_Address(src));
3768 } else {
3769 lea(rscratch1, src);
3770 vaddss(dst, nds, Address(rscratch1, 0));
3771 }
3772 }
3773
3774 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3775 assert(UseAVX > 0, "requires some form of AVX");
3776 if (reachable(src)) {
3777 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3778 } else {
3779 lea(rscratch, src);
3780 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3781 }
3782 }
3783
3784 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3785 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3786 vandps(dst, nds, negate_field, vector_len);
3787 }
3788
3789 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3790 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3791 vandpd(dst, nds, negate_field, vector_len);
3792 }
3793
3794 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3795 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3796 Assembler::vpaddb(dst, nds, src, vector_len);
3797 }
3798
3799 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3800 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3801 Assembler::vpaddb(dst, nds, src, vector_len);
3802 }
3803
3804 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3805 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3806 Assembler::vpaddw(dst, nds, src, vector_len);
3807 }
3808
3809 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3810 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3811 Assembler::vpaddw(dst, nds, src, vector_len);
3812 }
3813
3814 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3815 if (reachable(src)) {
3816 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3817 } else {
3818 lea(scratch_reg, src);
3819 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3820 }
3821 }
3822
3823 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3824 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3825 Assembler::vpbroadcastw(dst, src, vector_len);
3826 }
3827
3828 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3829 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3830 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3831 }
3832
3833 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3834 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3835 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3836 }
3837
3838 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3839 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3840 Assembler::vpmovzxbw(dst, src, vector_len);
3841 }
3842
3843 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
3844 assert((src->encoding() < 16),"XMM register should be 0-15");
3845 Assembler::vpmovmskb(dst, src);
3846 }
3847
3848 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3849 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3850 Assembler::vpmullw(dst, nds, src, vector_len);
3851 }
3852
3853 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3854 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3855 Assembler::vpmullw(dst, nds, src, vector_len);
3856 }
3857
3858 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3859 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3860 Assembler::vpsubb(dst, nds, src, vector_len);
3861 }
3862
3863 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3864 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3865 Assembler::vpsubb(dst, nds, src, vector_len);
3866 }
3867
3868 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3869 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3870 Assembler::vpsubw(dst, nds, src, vector_len);
3871 }
3872
3873 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3874 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3875 Assembler::vpsubw(dst, nds, src, vector_len);
3876 }
3877
3878 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3879 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3880 Assembler::vpsraw(dst, nds, shift, vector_len);
3881 }
3882
3883 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3884 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3885 Assembler::vpsraw(dst, nds, shift, vector_len);
3886 }
3887
3888 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3889 assert(UseAVX > 2,"");
3890 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3891 vector_len = 2;
3892 }
3893 Assembler::evpsraq(dst, nds, shift, vector_len);
3894 }
3895
3896 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3897 assert(UseAVX > 2,"");
3898 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3899 vector_len = 2;
3900 }
3901 Assembler::evpsraq(dst, nds, shift, vector_len);
3902 }
3903
3904 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3905 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3906 Assembler::vpsrlw(dst, nds, shift, vector_len);
3907 }
3908
3909 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3910 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3911 Assembler::vpsrlw(dst, nds, shift, vector_len);
3912 }
3913
3914 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3915 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3916 Assembler::vpsllw(dst, nds, shift, vector_len);
3917 }
3918
3919 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3920 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3921 Assembler::vpsllw(dst, nds, shift, vector_len);
3922 }
3923
3924 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3925 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3926 Assembler::vptest(dst, src);
3927 }
3928
3929 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3930 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3931 Assembler::punpcklbw(dst, src);
3932 }
3933
3934 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3935 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3936 Assembler::pshufd(dst, src, mode);
3937 }
3938
3939 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3940 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3941 Assembler::pshuflw(dst, src, mode);
3942 }
3943
3944 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3945 if (reachable(src)) {
3946 vandpd(dst, nds, as_Address(src), vector_len);
3947 } else {
3948 lea(scratch_reg, src);
3949 vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3950 }
3951 }
3952
3953 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3954 if (reachable(src)) {
3955 vandps(dst, nds, as_Address(src), vector_len);
3956 } else {
3957 lea(scratch_reg, src);
3958 vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3959 }
3960 }
3961
3962 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3963 if (reachable(src)) {
3964 vdivsd(dst, nds, as_Address(src));
3965 } else {
3966 lea(rscratch1, src);
3967 vdivsd(dst, nds, Address(rscratch1, 0));
3968 }
3969 }
3970
3971 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3972 if (reachable(src)) {
3973 vdivss(dst, nds, as_Address(src));
3974 } else {
3975 lea(rscratch1, src);
3976 vdivss(dst, nds, Address(rscratch1, 0));
3977 }
3978 }
3979
3980 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3981 if (reachable(src)) {
3982 vmulsd(dst, nds, as_Address(src));
3983 } else {
3984 lea(rscratch1, src);
3985 vmulsd(dst, nds, Address(rscratch1, 0));
3986 }
3987 }
3988
3989 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3990 if (reachable(src)) {
3991 vmulss(dst, nds, as_Address(src));
3992 } else {
3993 lea(rscratch1, src);
3994 vmulss(dst, nds, Address(rscratch1, 0));
3995 }
3996 }
3997
3998 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3999 if (reachable(src)) {
4000 vsubsd(dst, nds, as_Address(src));
4001 } else {
4002 lea(rscratch1, src);
4003 vsubsd(dst, nds, Address(rscratch1, 0));
4004 }
4005 }
4006
4007 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4008 if (reachable(src)) {
4009 vsubss(dst, nds, as_Address(src));
4010 } else {
4011 lea(rscratch1, src);
4012 vsubss(dst, nds, Address(rscratch1, 0));
4013 }
4014 }
4015
4016 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4017 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4018 vxorps(dst, nds, src, Assembler::AVX_128bit);
4019 }
4020
4021 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4022 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4023 vxorpd(dst, nds, src, Assembler::AVX_128bit);
4024 }
4025
4026 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4027 if (reachable(src)) {
4028 vxorpd(dst, nds, as_Address(src), vector_len);
4029 } else {
4030 lea(scratch_reg, src);
4031 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
4032 }
4033 }
4034
4035 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4036 if (reachable(src)) {
4037 vxorps(dst, nds, as_Address(src), vector_len);
4038 } else {
4039 lea(scratch_reg, src);
4040 vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
4041 }
4042 }
4043
4044 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4045 if (UseAVX > 1 || (vector_len < 1)) {
4046 if (reachable(src)) {
4047 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4048 } else {
4049 lea(scratch_reg, src);
4050 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
4051 }
4052 }
4053 else {
4054 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
4055 }
4056 }
4057
4058 //-------------------------------------------------------------------------------------------
4059 #ifdef COMPILER2
4060 // Generic instructions support for use in .ad files C2 code generation
4061
4062 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, Register scr) {
4063 if (dst != src) {
4064 movdqu(dst, src);
4065 }
4066 if (opcode == Op_AbsVD) {
4067 andpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), scr);
4068 } else {
4069 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4070 xorpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), scr);
4071 }
4072 }
4073
4074 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4075 if (opcode == Op_AbsVD) {
4076 vandpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), vector_len, scr);
4077 } else {
4078 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4079 vxorpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), vector_len, scr);
4080 }
4081 }
4082
4083 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, Register scr) {
4084 if (dst != src) {
4085 movdqu(dst, src);
4086 }
4087 if (opcode == Op_AbsVF) {
4088 andps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), scr);
4089 } else {
4090 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4091 xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), scr);
4092 }
4093 }
4094
4095 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4096 if (opcode == Op_AbsVF) {
4097 vandps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), vector_len, scr);
4098 } else {
4099 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4100 vxorps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), vector_len, scr);
4101 }
4102 }
4103
4104 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src) {
4105 if (sign) {
4106 pmovsxbw(dst, src);
4107 } else {
4108 pmovzxbw(dst, src);
4109 }
4110 }
4111
4112 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len) {
4113 if (sign) {
4114 vpmovsxbw(dst, src, vector_len);
4115 } else {
4116 vpmovzxbw(dst, src, vector_len);
4117 }
4118 }
4119
4120 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister src) {
4121 if (opcode == Op_RShiftVI) {
4122 psrad(dst, src);
4123 } else if (opcode == Op_LShiftVI) {
4124 pslld(dst, src);
4125 } else {
4126 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4127 psrld(dst, src);
4128 }
4129 }
4130
4131 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4132 if (opcode == Op_RShiftVI) {
4133 vpsrad(dst, nds, src, vector_len);
4134 } else if (opcode == Op_LShiftVI) {
4135 vpslld(dst, nds, src, vector_len);
4136 } else {
4137 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4138 vpsrld(dst, nds, src, vector_len);
4139 }
4140 }
4141
4142 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister src) {
4143 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4144 psraw(dst, src);
4145 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4146 psllw(dst, src);
4147 } else {
4148 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4149 psrlw(dst, src);
4150 }
4151 }
4152
4153 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4154 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4155 vpsraw(dst, nds, src, vector_len);
4156 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4157 vpsllw(dst, nds, src, vector_len);
4158 } else {
4159 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4160 vpsrlw(dst, nds, src, vector_len);
4161 }
4162 }
4163
4164 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister src) {
4165 if (opcode == Op_RShiftVL) {
4166 psrlq(dst, src); // using srl to implement sra on pre-avs512 systems
4167 } else if (opcode == Op_LShiftVL) {
4168 psllq(dst, src);
4169 } else {
4170 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4171 psrlq(dst, src);
4172 }
4173 }
4174
4175 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4176 if (opcode == Op_RShiftVL) {
4177 evpsraq(dst, nds, src, vector_len);
4178 } else if (opcode == Op_LShiftVL) {
4179 vpsllq(dst, nds, src, vector_len);
4180 } else {
4181 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4182 vpsrlq(dst, nds, src, vector_len);
4183 }
4184 }
4185 #endif
4186 //-------------------------------------------------------------------------------------------
4187
4188 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4189 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4190 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4191 // The inverted mask is sign-extended
4192 andptr(possibly_jweak, inverted_jweak_mask);
4193 }
4194
4195 void MacroAssembler::resolve_jobject(Register value,
4196 Register thread,
4197 Register tmp) {
4198 assert_different_registers(value, thread, tmp);
4199 Label done, not_weak;
4200 testptr(value, value);
4201 jcc(Assembler::zero, done); // Use NULL as-is.
4202 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4203 jcc(Assembler::zero, not_weak);
4204 // Resolve jweak.
4205 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4206 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4207 verify_oop(value);
4208 jmp(done);
4209 bind(not_weak);
4210 // Resolve (untagged) jobject.
4211 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4212 verify_oop(value);
4213 bind(done);
4214 }
4215
4216 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4217 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4218 }
4219
4220 // Force generation of a 4 byte immediate value even if it fits into 8bit
4221 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4222 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4223 }
4224
4225 void MacroAssembler::subptr(Register dst, Register src) {
4226 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4227 }
4228
4229 // C++ bool manipulation
4230 void MacroAssembler::testbool(Register dst) {
4231 if(sizeof(bool) == 1)
4232 testb(dst, 0xff);
4233 else if(sizeof(bool) == 2) {
4234 // testw implementation needed for two byte bools
4235 ShouldNotReachHere();
4236 } else if(sizeof(bool) == 4)
4237 testl(dst, dst);
4238 else
4239 // unsupported
4240 ShouldNotReachHere();
4241 }
4242
4243 void MacroAssembler::testptr(Register dst, Register src) {
4244 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4245 }
4246
4247 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4248 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4249 Register var_size_in_bytes,
4250 int con_size_in_bytes,
4251 Register t1,
4252 Register t2,
4253 Label& slow_case) {
4254 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4255 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4256 }
4257
4258 // Defines obj, preserves var_size_in_bytes
4259 void MacroAssembler::eden_allocate(Register thread, Register obj,
4260 Register var_size_in_bytes,
4261 int con_size_in_bytes,
4262 Register t1,
4263 Label& slow_case) {
4264 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4265 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4266 }
4267
4268 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4269 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4270 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4271 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4272 Label done;
4273
4274 testptr(length_in_bytes, length_in_bytes);
4275 jcc(Assembler::zero, done);
4276
4277 // initialize topmost word, divide index by 2, check if odd and test if zero
4278 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4279 #ifdef ASSERT
4280 {
4281 Label L;
4282 testptr(length_in_bytes, BytesPerWord - 1);
4283 jcc(Assembler::zero, L);
4284 stop("length must be a multiple of BytesPerWord");
4285 bind(L);
4286 }
4287 #endif
4288 Register index = length_in_bytes;
4289 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4290 if (UseIncDec) {
4291 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4292 } else {
4293 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4294 shrptr(index, 1);
4295 }
4296 #ifndef _LP64
4297 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4298 {
4299 Label even;
4300 // note: if index was a multiple of 8, then it cannot
4301 // be 0 now otherwise it must have been 0 before
4302 // => if it is even, we don't need to check for 0 again
4303 jcc(Assembler::carryClear, even);
4304 // clear topmost word (no jump would be needed if conditional assignment worked here)
4305 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4306 // index could be 0 now, must check again
4307 jcc(Assembler::zero, done);
4308 bind(even);
4309 }
4310 #endif // !_LP64
4311 // initialize remaining object fields: index is a multiple of 2 now
4312 {
4313 Label loop;
4314 bind(loop);
4315 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4316 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4317 decrement(index);
4318 jcc(Assembler::notZero, loop);
4319 }
4320
4321 bind(done);
4322 }
4323
4324 // Look up the method for a megamorphic invokeinterface call.
4325 // The target method is determined by <intf_klass, itable_index>.
4326 // The receiver klass is in recv_klass.
4327 // On success, the result will be in method_result, and execution falls through.
4328 // On failure, execution transfers to the given label.
4329 void MacroAssembler::lookup_interface_method(Register recv_klass,
4330 Register intf_klass,
4331 RegisterOrConstant itable_index,
4332 Register method_result,
4333 Register scan_temp,
4334 Label& L_no_such_interface,
4335 bool return_method) {
4336 assert_different_registers(recv_klass, intf_klass, scan_temp);
4337 assert_different_registers(method_result, intf_klass, scan_temp);
4338 assert(recv_klass != method_result || !return_method,
4339 "recv_klass can be destroyed when method isn't needed");
4340
4341 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4342 "caller must use same register for non-constant itable index as for method");
4343
4344 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4345 int vtable_base = in_bytes(Klass::vtable_start_offset());
4346 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4347 int scan_step = itableOffsetEntry::size() * wordSize;
4348 int vte_size = vtableEntry::size_in_bytes();
4349 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4350 assert(vte_size == wordSize, "else adjust times_vte_scale");
4351
4352 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4353
4354 // %%% Could store the aligned, prescaled offset in the klassoop.
4355 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4356
4357 if (return_method) {
4358 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4359 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4360 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4361 }
4362
4363 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4364 // if (scan->interface() == intf) {
4365 // result = (klass + scan->offset() + itable_index);
4366 // }
4367 // }
4368 Label search, found_method;
4369
4370 for (int peel = 1; peel >= 0; peel--) {
4371 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4372 cmpptr(intf_klass, method_result);
4373
4374 if (peel) {
4375 jccb(Assembler::equal, found_method);
4376 } else {
4377 jccb(Assembler::notEqual, search);
4378 // (invert the test to fall through to found_method...)
4379 }
4380
4381 if (!peel) break;
4382
4383 bind(search);
4384
4385 // Check that the previous entry is non-null. A null entry means that
4386 // the receiver class doesn't implement the interface, and wasn't the
4387 // same as when the caller was compiled.
4388 testptr(method_result, method_result);
4389 jcc(Assembler::zero, L_no_such_interface);
4390 addptr(scan_temp, scan_step);
4391 }
4392
4393 bind(found_method);
4394
4395 if (return_method) {
4396 // Got a hit.
4397 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4398 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4399 }
4400 }
4401
4402
4403 // virtual method calling
4404 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4405 RegisterOrConstant vtable_index,
4406 Register method_result) {
4407 const int base = in_bytes(Klass::vtable_start_offset());
4408 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4409 Address vtable_entry_addr(recv_klass,
4410 vtable_index, Address::times_ptr,
4411 base + vtableEntry::method_offset_in_bytes());
4412 movptr(method_result, vtable_entry_addr);
4413 }
4414
4415
4416 void MacroAssembler::check_klass_subtype(Register sub_klass,
4417 Register super_klass,
4418 Register temp_reg,
4419 Label& L_success) {
4420 Label L_failure;
4421 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4422 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4423 bind(L_failure);
4424 }
4425
4426
4427 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4428 Register super_klass,
4429 Register temp_reg,
4430 Label* L_success,
4431 Label* L_failure,
4432 Label* L_slow_path,
4433 RegisterOrConstant super_check_offset) {
4434 assert_different_registers(sub_klass, super_klass, temp_reg);
4435 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4436 if (super_check_offset.is_register()) {
4437 assert_different_registers(sub_klass, super_klass,
4438 super_check_offset.as_register());
4439 } else if (must_load_sco) {
4440 assert(temp_reg != noreg, "supply either a temp or a register offset");
4441 }
4442
4443 Label L_fallthrough;
4444 int label_nulls = 0;
4445 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4446 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4447 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4448 assert(label_nulls <= 1, "at most one NULL in the batch");
4449
4450 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4451 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4452 Address super_check_offset_addr(super_klass, sco_offset);
4453
4454 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4455 // range of a jccb. If this routine grows larger, reconsider at
4456 // least some of these.
4457 #define local_jcc(assembler_cond, label) \
4458 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4459 else jcc( assembler_cond, label) /*omit semi*/
4460
4461 // Hacked jmp, which may only be used just before L_fallthrough.
4462 #define final_jmp(label) \
4463 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4464 else jmp(label) /*omit semi*/
4465
4466 // If the pointers are equal, we are done (e.g., String[] elements).
4467 // This self-check enables sharing of secondary supertype arrays among
4468 // non-primary types such as array-of-interface. Otherwise, each such
4469 // type would need its own customized SSA.
4470 // We move this check to the front of the fast path because many
4471 // type checks are in fact trivially successful in this manner,
4472 // so we get a nicely predicted branch right at the start of the check.
4473 cmpptr(sub_klass, super_klass);
4474 local_jcc(Assembler::equal, *L_success);
4475
4476 // Check the supertype display:
4477 if (must_load_sco) {
4478 // Positive movl does right thing on LP64.
4479 movl(temp_reg, super_check_offset_addr);
4480 super_check_offset = RegisterOrConstant(temp_reg);
4481 }
4482 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4483 cmpptr(super_klass, super_check_addr); // load displayed supertype
4484
4485 // This check has worked decisively for primary supers.
4486 // Secondary supers are sought in the super_cache ('super_cache_addr').
4487 // (Secondary supers are interfaces and very deeply nested subtypes.)
4488 // This works in the same check above because of a tricky aliasing
4489 // between the super_cache and the primary super display elements.
4490 // (The 'super_check_addr' can address either, as the case requires.)
4491 // Note that the cache is updated below if it does not help us find
4492 // what we need immediately.
4493 // So if it was a primary super, we can just fail immediately.
4494 // Otherwise, it's the slow path for us (no success at this point).
4495
4496 if (super_check_offset.is_register()) {
4497 local_jcc(Assembler::equal, *L_success);
4498 cmpl(super_check_offset.as_register(), sc_offset);
4499 if (L_failure == &L_fallthrough) {
4500 local_jcc(Assembler::equal, *L_slow_path);
4501 } else {
4502 local_jcc(Assembler::notEqual, *L_failure);
4503 final_jmp(*L_slow_path);
4504 }
4505 } else if (super_check_offset.as_constant() == sc_offset) {
4506 // Need a slow path; fast failure is impossible.
4507 if (L_slow_path == &L_fallthrough) {
4508 local_jcc(Assembler::equal, *L_success);
4509 } else {
4510 local_jcc(Assembler::notEqual, *L_slow_path);
4511 final_jmp(*L_success);
4512 }
4513 } else {
4514 // No slow path; it's a fast decision.
4515 if (L_failure == &L_fallthrough) {
4516 local_jcc(Assembler::equal, *L_success);
4517 } else {
4518 local_jcc(Assembler::notEqual, *L_failure);
4519 final_jmp(*L_success);
4520 }
4521 }
4522
4523 bind(L_fallthrough);
4524
4525 #undef local_jcc
4526 #undef final_jmp
4527 }
4528
4529
4530 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4531 Register super_klass,
4532 Register temp_reg,
4533 Register temp2_reg,
4534 Label* L_success,
4535 Label* L_failure,
4536 bool set_cond_codes) {
4537 assert_different_registers(sub_klass, super_klass, temp_reg);
4538 if (temp2_reg != noreg)
4539 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4540 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4541
4542 Label L_fallthrough;
4543 int label_nulls = 0;
4544 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4545 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4546 assert(label_nulls <= 1, "at most one NULL in the batch");
4547
4548 // a couple of useful fields in sub_klass:
4549 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4550 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4551 Address secondary_supers_addr(sub_klass, ss_offset);
4552 Address super_cache_addr( sub_klass, sc_offset);
4553
4554 // Do a linear scan of the secondary super-klass chain.
4555 // This code is rarely used, so simplicity is a virtue here.
4556 // The repne_scan instruction uses fixed registers, which we must spill.
4557 // Don't worry too much about pre-existing connections with the input regs.
4558
4559 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4560 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4561
4562 // Get super_klass value into rax (even if it was in rdi or rcx).
4563 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4564 if (super_klass != rax || UseCompressedOops) {
4565 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4566 mov(rax, super_klass);
4567 }
4568 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4569 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4570
4571 #ifndef PRODUCT
4572 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4573 ExternalAddress pst_counter_addr((address) pst_counter);
4574 NOT_LP64( incrementl(pst_counter_addr) );
4575 LP64_ONLY( lea(rcx, pst_counter_addr) );
4576 LP64_ONLY( incrementl(Address(rcx, 0)) );
4577 #endif //PRODUCT
4578
4579 // We will consult the secondary-super array.
4580 movptr(rdi, secondary_supers_addr);
4581 // Load the array length. (Positive movl does right thing on LP64.)
4582 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4583 // Skip to start of data.
4584 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4585
4586 // Scan RCX words at [RDI] for an occurrence of RAX.
4587 // Set NZ/Z based on last compare.
4588 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4589 // not change flags (only scas instruction which is repeated sets flags).
4590 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4591
4592 testptr(rax,rax); // Set Z = 0
4593 repne_scan();
4594
4595 // Unspill the temp. registers:
4596 if (pushed_rdi) pop(rdi);
4597 if (pushed_rcx) pop(rcx);
4598 if (pushed_rax) pop(rax);
4599
4600 if (set_cond_codes) {
4601 // Special hack for the AD files: rdi is guaranteed non-zero.
4602 assert(!pushed_rdi, "rdi must be left non-NULL");
4603 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4604 }
4605
4606 if (L_failure == &L_fallthrough)
4607 jccb(Assembler::notEqual, *L_failure);
4608 else jcc(Assembler::notEqual, *L_failure);
4609
4610 // Success. Cache the super we found and proceed in triumph.
4611 movptr(super_cache_addr, super_klass);
4612
4613 if (L_success != &L_fallthrough) {
4614 jmp(*L_success);
4615 }
4616
4617 #undef IS_A_TEMP
4618
4619 bind(L_fallthrough);
4620 }
4621
4622 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4623 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4624
4625 Label L_fallthrough;
4626 if (L_fast_path == NULL) {
4627 L_fast_path = &L_fallthrough;
4628 } else if (L_slow_path == NULL) {
4629 L_slow_path = &L_fallthrough;
4630 }
4631
4632 // Fast path check: class is fully initialized
4633 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4634 jcc(Assembler::equal, *L_fast_path);
4635
4636 // Fast path check: current thread is initializer thread
4637 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4638 if (L_slow_path == &L_fallthrough) {
4639 jcc(Assembler::equal, *L_fast_path);
4640 bind(*L_slow_path);
4641 } else if (L_fast_path == &L_fallthrough) {
4642 jcc(Assembler::notEqual, *L_slow_path);
4643 bind(*L_fast_path);
4644 } else {
4645 Unimplemented();
4646 }
4647 }
4648
4649 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4650 if (VM_Version::supports_cmov()) {
4651 cmovl(cc, dst, src);
4652 } else {
4653 Label L;
4654 jccb(negate_condition(cc), L);
4655 movl(dst, src);
4656 bind(L);
4657 }
4658 }
4659
4660 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4661 if (VM_Version::supports_cmov()) {
4662 cmovl(cc, dst, src);
4663 } else {
4664 Label L;
4665 jccb(negate_condition(cc), L);
4666 movl(dst, src);
4667 bind(L);
4668 }
4669 }
4670
4671 void MacroAssembler::verify_oop(Register reg, const char* s) {
4672 if (!VerifyOops) return;
4673
4674 // Pass register number to verify_oop_subroutine
4675 const char* b = NULL;
4676 {
4677 ResourceMark rm;
4678 stringStream ss;
4679 ss.print("verify_oop: %s: %s", reg->name(), s);
4680 b = code_string(ss.as_string());
4681 }
4682 BLOCK_COMMENT("verify_oop {");
4683 #ifdef _LP64
4684 push(rscratch1); // save r10, trashed by movptr()
4685 #endif
4686 push(rax); // save rax,
4687 push(reg); // pass register argument
4688 ExternalAddress buffer((address) b);
4689 // avoid using pushptr, as it modifies scratch registers
4690 // and our contract is not to modify anything
4691 movptr(rax, buffer.addr());
4692 push(rax);
4693 // call indirectly to solve generation ordering problem
4694 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4695 call(rax);
4696 // Caller pops the arguments (oop, message) and restores rax, r10
4697 BLOCK_COMMENT("} verify_oop");
4698 }
4699
4700
4701 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4702 Register tmp,
4703 int offset) {
4704 intptr_t value = *delayed_value_addr;
4705 if (value != 0)
4706 return RegisterOrConstant(value + offset);
4707
4708 // load indirectly to solve generation ordering problem
4709 movptr(tmp, ExternalAddress((address) delayed_value_addr));
4710
4711 #ifdef ASSERT
4712 { Label L;
4713 testptr(tmp, tmp);
4714 if (WizardMode) {
4715 const char* buf = NULL;
4716 {
4717 ResourceMark rm;
4718 stringStream ss;
4719 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4720 buf = code_string(ss.as_string());
4721 }
4722 jcc(Assembler::notZero, L);
4723 STOP(buf);
4724 } else {
4725 jccb(Assembler::notZero, L);
4726 hlt();
4727 }
4728 bind(L);
4729 }
4730 #endif
4731
4732 if (offset != 0)
4733 addptr(tmp, offset);
4734
4735 return RegisterOrConstant(tmp);
4736 }
4737
4738
4739 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4740 int extra_slot_offset) {
4741 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4742 int stackElementSize = Interpreter::stackElementSize;
4743 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4744 #ifdef ASSERT
4745 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4746 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4747 #endif
4748 Register scale_reg = noreg;
4749 Address::ScaleFactor scale_factor = Address::no_scale;
4750 if (arg_slot.is_constant()) {
4751 offset += arg_slot.as_constant() * stackElementSize;
4752 } else {
4753 scale_reg = arg_slot.as_register();
4754 scale_factor = Address::times(stackElementSize);
4755 }
4756 offset += wordSize; // return PC is on stack
4757 return Address(rsp, scale_reg, scale_factor, offset);
4758 }
4759
4760
4761 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4762 if (!VerifyOops) return;
4763
4764 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4765 // Pass register number to verify_oop_subroutine
4766 const char* b = NULL;
4767 {
4768 ResourceMark rm;
4769 stringStream ss;
4770 ss.print("verify_oop_addr: %s", s);
4771 b = code_string(ss.as_string());
4772 }
4773 #ifdef _LP64
4774 push(rscratch1); // save r10, trashed by movptr()
4775 #endif
4776 push(rax); // save rax,
4777 // addr may contain rsp so we will have to adjust it based on the push
4778 // we just did (and on 64 bit we do two pushes)
4779 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4780 // stores rax into addr which is backwards of what was intended.
4781 if (addr.uses(rsp)) {
4782 lea(rax, addr);
4783 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4784 } else {
4785 pushptr(addr);
4786 }
4787
4788 ExternalAddress buffer((address) b);
4789 // pass msg argument
4790 // avoid using pushptr, as it modifies scratch registers
4791 // and our contract is not to modify anything
4792 movptr(rax, buffer.addr());
4793 push(rax);
4794
4795 // call indirectly to solve generation ordering problem
4796 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4797 call(rax);
4798 // Caller pops the arguments (addr, message) and restores rax, r10.
4799 }
4800
4801 void MacroAssembler::verify_tlab() {
4802 #ifdef ASSERT
4803 if (UseTLAB && VerifyOops) {
4804 Label next, ok;
4805 Register t1 = rsi;
4806 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4807
4808 push(t1);
4809 NOT_LP64(push(thread_reg));
4810 NOT_LP64(get_thread(thread_reg));
4811
4812 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4813 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4814 jcc(Assembler::aboveEqual, next);
4815 STOP("assert(top >= start)");
4816 should_not_reach_here();
4817
4818 bind(next);
4819 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4820 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4821 jcc(Assembler::aboveEqual, ok);
4822 STOP("assert(top <= end)");
4823 should_not_reach_here();
4824
4825 bind(ok);
4826 NOT_LP64(pop(thread_reg));
4827 pop(t1);
4828 }
4829 #endif
4830 }
4831
4832 class ControlWord {
4833 public:
4834 int32_t _value;
4835
4836 int rounding_control() const { return (_value >> 10) & 3 ; }
4837 int precision_control() const { return (_value >> 8) & 3 ; }
4838 bool precision() const { return ((_value >> 5) & 1) != 0; }
4839 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4840 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4841 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4842 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4843 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4844
4845 void print() const {
4846 // rounding control
4847 const char* rc;
4848 switch (rounding_control()) {
4849 case 0: rc = "round near"; break;
4850 case 1: rc = "round down"; break;
4851 case 2: rc = "round up "; break;
4852 case 3: rc = "chop "; break;
4853 };
4854 // precision control
4855 const char* pc;
4856 switch (precision_control()) {
4857 case 0: pc = "24 bits "; break;
4858 case 1: pc = "reserved"; break;
4859 case 2: pc = "53 bits "; break;
4860 case 3: pc = "64 bits "; break;
4861 };
4862 // flags
4863 char f[9];
4864 f[0] = ' ';
4865 f[1] = ' ';
4866 f[2] = (precision ()) ? 'P' : 'p';
4867 f[3] = (underflow ()) ? 'U' : 'u';
4868 f[4] = (overflow ()) ? 'O' : 'o';
4869 f[5] = (zero_divide ()) ? 'Z' : 'z';
4870 f[6] = (denormalized()) ? 'D' : 'd';
4871 f[7] = (invalid ()) ? 'I' : 'i';
4872 f[8] = '\x0';
4873 // output
4874 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4875 }
4876
4877 };
4878
4879 class StatusWord {
4880 public:
4881 int32_t _value;
4882
4883 bool busy() const { return ((_value >> 15) & 1) != 0; }
4884 bool C3() const { return ((_value >> 14) & 1) != 0; }
4885 bool C2() const { return ((_value >> 10) & 1) != 0; }
4886 bool C1() const { return ((_value >> 9) & 1) != 0; }
4887 bool C0() const { return ((_value >> 8) & 1) != 0; }
4888 int top() const { return (_value >> 11) & 7 ; }
4889 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4890 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4891 bool precision() const { return ((_value >> 5) & 1) != 0; }
4892 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4893 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4894 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4895 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4896 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4897
4898 void print() const {
4899 // condition codes
4900 char c[5];
4901 c[0] = (C3()) ? '3' : '-';
4902 c[1] = (C2()) ? '2' : '-';
4903 c[2] = (C1()) ? '1' : '-';
4904 c[3] = (C0()) ? '0' : '-';
4905 c[4] = '\x0';
4906 // flags
4907 char f[9];
4908 f[0] = (error_status()) ? 'E' : '-';
4909 f[1] = (stack_fault ()) ? 'S' : '-';
4910 f[2] = (precision ()) ? 'P' : '-';
4911 f[3] = (underflow ()) ? 'U' : '-';
4912 f[4] = (overflow ()) ? 'O' : '-';
4913 f[5] = (zero_divide ()) ? 'Z' : '-';
4914 f[6] = (denormalized()) ? 'D' : '-';
4915 f[7] = (invalid ()) ? 'I' : '-';
4916 f[8] = '\x0';
4917 // output
4918 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4919 }
4920
4921 };
4922
4923 class TagWord {
4924 public:
4925 int32_t _value;
4926
4927 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4928
4929 void print() const {
4930 printf("%04x", _value & 0xFFFF);
4931 }
4932
4933 };
4934
4935 class FPU_Register {
4936 public:
4937 int32_t _m0;
4938 int32_t _m1;
4939 int16_t _ex;
4940
4941 bool is_indefinite() const {
4942 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4943 }
4944
4945 void print() const {
4946 char sign = (_ex < 0) ? '-' : '+';
4947 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4948 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4949 };
4950
4951 };
4952
4953 class FPU_State {
4954 public:
4955 enum {
4956 register_size = 10,
4957 number_of_registers = 8,
4958 register_mask = 7
4959 };
4960
4961 ControlWord _control_word;
4962 StatusWord _status_word;
4963 TagWord _tag_word;
4964 int32_t _error_offset;
4965 int32_t _error_selector;
4966 int32_t _data_offset;
4967 int32_t _data_selector;
4968 int8_t _register[register_size * number_of_registers];
4969
4970 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4971 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4972
4973 const char* tag_as_string(int tag) const {
4974 switch (tag) {
4975 case 0: return "valid";
4976 case 1: return "zero";
4977 case 2: return "special";
4978 case 3: return "empty";
4979 }
4980 ShouldNotReachHere();
4981 return NULL;
4982 }
4983
4984 void print() const {
4985 // print computation registers
4986 { int t = _status_word.top();
4987 for (int i = 0; i < number_of_registers; i++) {
4988 int j = (i - t) & register_mask;
4989 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4990 st(j)->print();
4991 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4992 }
4993 }
4994 printf("\n");
4995 // print control registers
4996 printf("ctrl = "); _control_word.print(); printf("\n");
4997 printf("stat = "); _status_word .print(); printf("\n");
4998 printf("tags = "); _tag_word .print(); printf("\n");
4999 }
5000
5001 };
5002
5003 class Flag_Register {
5004 public:
5005 int32_t _value;
5006
5007 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5008 bool direction() const { return ((_value >> 10) & 1) != 0; }
5009 bool sign() const { return ((_value >> 7) & 1) != 0; }
5010 bool zero() const { return ((_value >> 6) & 1) != 0; }
5011 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5012 bool parity() const { return ((_value >> 2) & 1) != 0; }
5013 bool carry() const { return ((_value >> 0) & 1) != 0; }
5014
5015 void print() const {
5016 // flags
5017 char f[8];
5018 f[0] = (overflow ()) ? 'O' : '-';
5019 f[1] = (direction ()) ? 'D' : '-';
5020 f[2] = (sign ()) ? 'S' : '-';
5021 f[3] = (zero ()) ? 'Z' : '-';
5022 f[4] = (auxiliary_carry()) ? 'A' : '-';
5023 f[5] = (parity ()) ? 'P' : '-';
5024 f[6] = (carry ()) ? 'C' : '-';
5025 f[7] = '\x0';
5026 // output
5027 printf("%08x flags = %s", _value, f);
5028 }
5029
5030 };
5031
5032 class IU_Register {
5033 public:
5034 int32_t _value;
5035
5036 void print() const {
5037 printf("%08x %11d", _value, _value);
5038 }
5039
5040 };
5041
5042 class IU_State {
5043 public:
5044 Flag_Register _eflags;
5045 IU_Register _rdi;
5046 IU_Register _rsi;
5047 IU_Register _rbp;
5048 IU_Register _rsp;
5049 IU_Register _rbx;
5050 IU_Register _rdx;
5051 IU_Register _rcx;
5052 IU_Register _rax;
5053
5054 void print() const {
5055 // computation registers
5056 printf("rax, = "); _rax.print(); printf("\n");
5057 printf("rbx, = "); _rbx.print(); printf("\n");
5058 printf("rcx = "); _rcx.print(); printf("\n");
5059 printf("rdx = "); _rdx.print(); printf("\n");
5060 printf("rdi = "); _rdi.print(); printf("\n");
5061 printf("rsi = "); _rsi.print(); printf("\n");
5062 printf("rbp, = "); _rbp.print(); printf("\n");
5063 printf("rsp = "); _rsp.print(); printf("\n");
5064 printf("\n");
5065 // control registers
5066 printf("flgs = "); _eflags.print(); printf("\n");
5067 }
5068 };
5069
5070
5071 class CPU_State {
5072 public:
5073 FPU_State _fpu_state;
5074 IU_State _iu_state;
5075
5076 void print() const {
5077 printf("--------------------------------------------------\n");
5078 _iu_state .print();
5079 printf("\n");
5080 _fpu_state.print();
5081 printf("--------------------------------------------------\n");
5082 }
5083
5084 };
5085
5086
5087 static void _print_CPU_state(CPU_State* state) {
5088 state->print();
5089 };
5090
5091
5092 void MacroAssembler::print_CPU_state() {
5093 push_CPU_state();
5094 push(rsp); // pass CPU state
5095 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5096 addptr(rsp, wordSize); // discard argument
5097 pop_CPU_state();
5098 }
5099
5100
5101 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5102 static int counter = 0;
5103 FPU_State* fs = &state->_fpu_state;
5104 counter++;
5105 // For leaf calls, only verify that the top few elements remain empty.
5106 // We only need 1 empty at the top for C2 code.
5107 if( stack_depth < 0 ) {
5108 if( fs->tag_for_st(7) != 3 ) {
5109 printf("FPR7 not empty\n");
5110 state->print();
5111 assert(false, "error");
5112 return false;
5113 }
5114 return true; // All other stack states do not matter
5115 }
5116
5117 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5118 "bad FPU control word");
5119
5120 // compute stack depth
5121 int i = 0;
5122 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5123 int d = i;
5124 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5125 // verify findings
5126 if (i != FPU_State::number_of_registers) {
5127 // stack not contiguous
5128 printf("%s: stack not contiguous at ST%d\n", s, i);
5129 state->print();
5130 assert(false, "error");
5131 return false;
5132 }
5133 // check if computed stack depth corresponds to expected stack depth
5134 if (stack_depth < 0) {
5135 // expected stack depth is -stack_depth or less
5136 if (d > -stack_depth) {
5137 // too many elements on the stack
5138 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5139 state->print();
5140 assert(false, "error");
5141 return false;
5142 }
5143 } else {
5144 // expected stack depth is stack_depth
5145 if (d != stack_depth) {
5146 // wrong stack depth
5147 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5148 state->print();
5149 assert(false, "error");
5150 return false;
5151 }
5152 }
5153 // everything is cool
5154 return true;
5155 }
5156
5157
5158 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5159 if (!VerifyFPU) return;
5160 push_CPU_state();
5161 push(rsp); // pass CPU state
5162 ExternalAddress msg((address) s);
5163 // pass message string s
5164 pushptr(msg.addr());
5165 push(stack_depth); // pass stack depth
5166 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5167 addptr(rsp, 3 * wordSize); // discard arguments
5168 // check for error
5169 { Label L;
5170 testl(rax, rax);
5171 jcc(Assembler::notZero, L);
5172 int3(); // break if error condition
5173 bind(L);
5174 }
5175 pop_CPU_state();
5176 }
5177
5178 void MacroAssembler::restore_cpu_control_state_after_jni() {
5179 // Either restore the MXCSR register after returning from the JNI Call
5180 // or verify that it wasn't changed (with -Xcheck:jni flag).
5181 if (VM_Version::supports_sse()) {
5182 if (RestoreMXCSROnJNICalls) {
5183 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5184 } else if (CheckJNICalls) {
5185 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5186 }
5187 }
5188 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5189 vzeroupper();
5190 // Reset k1 to 0xffff.
5191
5192 #ifdef COMPILER2
5193 if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5194 push(rcx);
5195 movl(rcx, 0xffff);
5196 kmovwl(k1, rcx);
5197 pop(rcx);
5198 }
5199 #endif // COMPILER2
5200
5201 #ifndef _LP64
5202 // Either restore the x87 floating pointer control word after returning
5203 // from the JNI call or verify that it wasn't changed.
5204 if (CheckJNICalls) {
5205 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5206 }
5207 #endif // _LP64
5208 }
5209
5210 // ((OopHandle)result).resolve();
5211 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5212 assert_different_registers(result, tmp);
5213
5214 // Only 64 bit platforms support GCs that require a tmp register
5215 // Only IN_HEAP loads require a thread_tmp register
5216 // OopHandle::resolve is an indirection like jobject.
5217 access_load_at(T_OBJECT, IN_NATIVE,
5218 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5219 }
5220
5221 // ((WeakHandle)result).resolve();
5222 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5223 assert_different_registers(rresult, rtmp);
5224 Label resolved;
5225
5226 // A null weak handle resolves to null.
5227 cmpptr(rresult, 0);
5228 jcc(Assembler::equal, resolved);
5229
5230 // Only 64 bit platforms support GCs that require a tmp register
5231 // Only IN_HEAP loads require a thread_tmp register
5232 // WeakHandle::resolve is an indirection like jweak.
5233 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5234 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5235 bind(resolved);
5236 }
5237
5238 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5239 // get mirror
5240 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5241 load_method_holder(mirror, method);
5242 movptr(mirror, Address(mirror, mirror_offset));
5243 resolve_oop_handle(mirror, tmp);
5244 }
5245
5246 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5247 load_method_holder(rresult, rmethod);
5248 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5249 }
5250
5251 void MacroAssembler::load_method_holder(Register holder, Register method) {
5252 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5253 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5254 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
5255 }
5256
5257 void MacroAssembler::load_klass(Register dst, Register src) {
5258 #ifdef _LP64
5259 if (UseCompressedClassPointers) {
5260 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5261 decode_klass_not_null(dst);
5262 } else
5263 #endif
5264 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5265 }
5266
5267 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5268 load_klass(dst, src);
5269 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5270 }
5271
5272 void MacroAssembler::store_klass(Register dst, Register src) {
5273 #ifdef _LP64
5274 if (UseCompressedClassPointers) {
5275 encode_klass_not_null(src);
5276 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5277 } else
5278 #endif
5279 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5280 }
5281
5282 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5283 Register tmp1, Register thread_tmp) {
5284 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5285 decorators = AccessInternal::decorator_fixup(decorators);
5286 bool as_raw = (decorators & AS_RAW) != 0;
5287 if (as_raw) {
5288 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5289 } else {
5290 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5291 }
5292 }
5293
5294 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5295 Register tmp1, Register tmp2) {
5296 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5297 decorators = AccessInternal::decorator_fixup(decorators);
5298 bool as_raw = (decorators & AS_RAW) != 0;
5299 if (as_raw) {
5300 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5301 } else {
5302 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5303 }
5304 }
5305
5306 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5307 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5308 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5309 decorators |= ACCESS_READ | ACCESS_WRITE;
5310 }
5311 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5312 return bs->resolve(this, decorators, obj);
5313 }
5314
5315 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5316 Register thread_tmp, DecoratorSet decorators) {
5317 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5318 }
5319
5320 // Doesn't do verfication, generates fixed size code
5321 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5322 Register thread_tmp, DecoratorSet decorators) {
5323 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5324 }
5325
5326 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5327 Register tmp2, DecoratorSet decorators) {
5328 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5329 }
5330
5331 // Used for storing NULLs.
5332 void MacroAssembler::store_heap_oop_null(Address dst) {
5333 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5334 }
5335
5336 #ifdef _LP64
5337 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5338 if (UseCompressedClassPointers) {
5339 // Store to klass gap in destination
5340 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5341 }
5342 }
5343
5344 #ifdef ASSERT
5345 void MacroAssembler::verify_heapbase(const char* msg) {
5346 assert (UseCompressedOops, "should be compressed");
5347 assert (Universe::heap() != NULL, "java heap should be initialized");
5348 if (CheckCompressedOops) {
5349 Label ok;
5350 push(rscratch1); // cmpptr trashes rscratch1
5351 cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5352 jcc(Assembler::equal, ok);
5353 STOP(msg);
5354 bind(ok);
5355 pop(rscratch1);
5356 }
5357 }
5358 #endif
5359
5360 // Algorithm must match oop.inline.hpp encode_heap_oop.
5361 void MacroAssembler::encode_heap_oop(Register r) {
5362 #ifdef ASSERT
5363 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5364 #endif
5365 verify_oop(r, "broken oop in encode_heap_oop");
5366 if (CompressedOops::base() == NULL) {
5367 if (CompressedOops::shift() != 0) {
5368 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5369 shrq(r, LogMinObjAlignmentInBytes);
5370 }
5371 return;
5372 }
5373 testq(r, r);
5374 cmovq(Assembler::equal, r, r12_heapbase);
5375 subq(r, r12_heapbase);
5376 shrq(r, LogMinObjAlignmentInBytes);
5377 }
5378
5379 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5380 #ifdef ASSERT
5381 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5382 if (CheckCompressedOops) {
5383 Label ok;
5384 testq(r, r);
5385 jcc(Assembler::notEqual, ok);
5386 STOP("null oop passed to encode_heap_oop_not_null");
5387 bind(ok);
5388 }
5389 #endif
5390 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5391 if (CompressedOops::base() != NULL) {
5392 subq(r, r12_heapbase);
5393 }
5394 if (CompressedOops::shift() != 0) {
5395 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5396 shrq(r, LogMinObjAlignmentInBytes);
5397 }
5398 }
5399
5400 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5401 #ifdef ASSERT
5402 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5403 if (CheckCompressedOops) {
5404 Label ok;
5405 testq(src, src);
5406 jcc(Assembler::notEqual, ok);
5407 STOP("null oop passed to encode_heap_oop_not_null2");
5408 bind(ok);
5409 }
5410 #endif
5411 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5412 if (dst != src) {
5413 movq(dst, src);
5414 }
5415 if (CompressedOops::base() != NULL) {
5416 subq(dst, r12_heapbase);
5417 }
5418 if (CompressedOops::shift() != 0) {
5419 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5420 shrq(dst, LogMinObjAlignmentInBytes);
5421 }
5422 }
5423
5424 void MacroAssembler::decode_heap_oop(Register r) {
5425 #ifdef ASSERT
5426 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5427 #endif
5428 if (CompressedOops::base() == NULL) {
5429 if (CompressedOops::shift() != 0) {
5430 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5431 shlq(r, LogMinObjAlignmentInBytes);
5432 }
5433 } else {
5434 Label done;
5435 shlq(r, LogMinObjAlignmentInBytes);
5436 jccb(Assembler::equal, done);
5437 addq(r, r12_heapbase);
5438 bind(done);
5439 }
5440 verify_oop(r, "broken oop in decode_heap_oop");
5441 }
5442
5443 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5444 // Note: it will change flags
5445 assert (UseCompressedOops, "should only be used for compressed headers");
5446 assert (Universe::heap() != NULL, "java heap should be initialized");
5447 // Cannot assert, unverified entry point counts instructions (see .ad file)
5448 // vtableStubs also counts instructions in pd_code_size_limit.
5449 // Also do not verify_oop as this is called by verify_oop.
5450 if (CompressedOops::shift() != 0) {
5451 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5452 shlq(r, LogMinObjAlignmentInBytes);
5453 if (CompressedOops::base() != NULL) {
5454 addq(r, r12_heapbase);
5455 }
5456 } else {
5457 assert (CompressedOops::base() == NULL, "sanity");
5458 }
5459 }
5460
5461 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5462 // Note: it will change flags
5463 assert (UseCompressedOops, "should only be used for compressed headers");
5464 assert (Universe::heap() != NULL, "java heap should be initialized");
5465 // Cannot assert, unverified entry point counts instructions (see .ad file)
5466 // vtableStubs also counts instructions in pd_code_size_limit.
5467 // Also do not verify_oop as this is called by verify_oop.
5468 if (CompressedOops::shift() != 0) {
5469 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5470 if (LogMinObjAlignmentInBytes == Address::times_8) {
5471 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5472 } else {
5473 if (dst != src) {
5474 movq(dst, src);
5475 }
5476 shlq(dst, LogMinObjAlignmentInBytes);
5477 if (CompressedOops::base() != NULL) {
5478 addq(dst, r12_heapbase);
5479 }
5480 }
5481 } else {
5482 assert (CompressedOops::base() == NULL, "sanity");
5483 if (dst != src) {
5484 movq(dst, src);
5485 }
5486 }
5487 }
5488
5489 void MacroAssembler::encode_klass_not_null(Register r) {
5490 if (CompressedKlassPointers::base() != NULL) {
5491 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5492 assert(r != r12_heapbase, "Encoding a klass in r12");
5493 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5494 subq(r, r12_heapbase);
5495 }
5496 if (CompressedKlassPointers::shift() != 0) {
5497 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5498 shrq(r, LogKlassAlignmentInBytes);
5499 }
5500 if (CompressedKlassPointers::base() != NULL) {
5501 reinit_heapbase();
5502 }
5503 }
5504
5505 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5506 if (dst == src) {
5507 encode_klass_not_null(src);
5508 } else {
5509 if (CompressedKlassPointers::base() != NULL) {
5510 mov64(dst, (int64_t)CompressedKlassPointers::base());
5511 negq(dst);
5512 addq(dst, src);
5513 } else {
5514 movptr(dst, src);
5515 }
5516 if (CompressedKlassPointers::shift() != 0) {
5517 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5518 shrq(dst, LogKlassAlignmentInBytes);
5519 }
5520 }
5521 }
5522
5523 // Function instr_size_for_decode_klass_not_null() counts the instructions
5524 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5525 // when (Universe::heap() != NULL). Hence, if the instructions they
5526 // generate change, then this method needs to be updated.
5527 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5528 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5529 if (CompressedKlassPointers::base() != NULL) {
5530 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5531 return (CompressedKlassPointers::shift() == 0 ? 20 : 24);
5532 } else {
5533 // longest load decode klass function, mov64, leaq
5534 return 16;
5535 }
5536 }
5537
5538 // !!! If the instructions that get generated here change then function
5539 // instr_size_for_decode_klass_not_null() needs to get updated.
5540 void MacroAssembler::decode_klass_not_null(Register r) {
5541 // Note: it will change flags
5542 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5543 assert(r != r12_heapbase, "Decoding a klass in r12");
5544 // Cannot assert, unverified entry point counts instructions (see .ad file)
5545 // vtableStubs also counts instructions in pd_code_size_limit.
5546 // Also do not verify_oop as this is called by verify_oop.
5547 if (CompressedKlassPointers::shift() != 0) {
5548 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5549 shlq(r, LogKlassAlignmentInBytes);
5550 }
5551 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5552 if (CompressedKlassPointers::base() != NULL) {
5553 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5554 addq(r, r12_heapbase);
5555 reinit_heapbase();
5556 }
5557 }
5558
5559 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5560 // Note: it will change flags
5561 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5562 if (dst == src) {
5563 decode_klass_not_null(dst);
5564 } else {
5565 // Cannot assert, unverified entry point counts instructions (see .ad file)
5566 // vtableStubs also counts instructions in pd_code_size_limit.
5567 // Also do not verify_oop as this is called by verify_oop.
5568 mov64(dst, (int64_t)CompressedKlassPointers::base());
5569 if (CompressedKlassPointers::shift() != 0) {
5570 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5571 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5572 leaq(dst, Address(dst, src, Address::times_8, 0));
5573 } else {
5574 addq(dst, src);
5575 }
5576 }
5577 }
5578
5579 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5580 assert (UseCompressedOops, "should only be used for compressed headers");
5581 assert (Universe::heap() != NULL, "java heap should be initialized");
5582 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5583 int oop_index = oop_recorder()->find_index(obj);
5584 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5585 mov_narrow_oop(dst, oop_index, rspec);
5586 }
5587
5588 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5589 assert (UseCompressedOops, "should only be used for compressed headers");
5590 assert (Universe::heap() != NULL, "java heap should be initialized");
5591 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5592 int oop_index = oop_recorder()->find_index(obj);
5593 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5594 mov_narrow_oop(dst, oop_index, rspec);
5595 }
5596
5597 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5598 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5599 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5600 int klass_index = oop_recorder()->find_index(k);
5601 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5602 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5603 }
5604
5605 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5606 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5607 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5608 int klass_index = oop_recorder()->find_index(k);
5609 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5610 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5611 }
5612
5613 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5614 assert (UseCompressedOops, "should only be used for compressed headers");
5615 assert (Universe::heap() != NULL, "java heap should be initialized");
5616 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5617 int oop_index = oop_recorder()->find_index(obj);
5618 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5619 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5620 }
5621
5622 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5623 assert (UseCompressedOops, "should only be used for compressed headers");
5624 assert (Universe::heap() != NULL, "java heap should be initialized");
5625 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5626 int oop_index = oop_recorder()->find_index(obj);
5627 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5628 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5629 }
5630
5631 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5632 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5633 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5634 int klass_index = oop_recorder()->find_index(k);
5635 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5636 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5637 }
5638
5639 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5640 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5641 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5642 int klass_index = oop_recorder()->find_index(k);
5643 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5644 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5645 }
5646
5647 void MacroAssembler::reinit_heapbase() {
5648 if (UseCompressedOops || UseCompressedClassPointers) {
5649 if (Universe::heap() != NULL) {
5650 if (CompressedOops::base() == NULL) {
5651 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5652 } else {
5653 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5654 }
5655 } else {
5656 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5657 }
5658 }
5659 }
5660
5661 #endif // _LP64
5662
5663 // C2 compiled method's prolog code.
5664 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5665
5666 // WARNING: Initial instruction MUST be 5 bytes or longer so that
5667 // NativeJump::patch_verified_entry will be able to patch out the entry
5668 // code safely. The push to verify stack depth is ok at 5 bytes,
5669 // the frame allocation can be either 3 or 6 bytes. So if we don't do
5670 // stack bang then we must use the 6 byte frame allocation even if
5671 // we have no frame. :-(
5672 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5673
5674 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5675 // Remove word for return addr
5676 framesize -= wordSize;
5677 stack_bang_size -= wordSize;
5678
5679 // Calls to C2R adapters often do not accept exceptional returns.
5680 // We require that their callers must bang for them. But be careful, because
5681 // some VM calls (such as call site linkage) can use several kilobytes of
5682 // stack. But the stack safety zone should account for that.
5683 // See bugs 4446381, 4468289, 4497237.
5684 if (stack_bang_size > 0) {
5685 generate_stack_overflow_check(stack_bang_size);
5686
5687 // We always push rbp, so that on return to interpreter rbp, will be
5688 // restored correctly and we can correct the stack.
5689 push(rbp);
5690 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5691 if (PreserveFramePointer) {
5692 mov(rbp, rsp);
5693 }
5694 // Remove word for ebp
5695 framesize -= wordSize;
5696
5697 // Create frame
5698 if (framesize) {
5699 subptr(rsp, framesize);
5700 }
5701 } else {
5702 // Create frame (force generation of a 4 byte immediate value)
5703 subptr_imm32(rsp, framesize);
5704
5705 // Save RBP register now.
5706 framesize -= wordSize;
5707 movptr(Address(rsp, framesize), rbp);
5708 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5709 if (PreserveFramePointer) {
5710 movptr(rbp, rsp);
5711 if (framesize > 0) {
5712 addptr(rbp, framesize);
5713 }
5714 }
5715 }
5716
5717 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5718 framesize -= wordSize;
5719 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5720 }
5721
5722 #ifndef _LP64
5723 // If method sets FPU control word do it now
5724 if (fp_mode_24b) {
5725 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5726 }
5727 if (UseSSE >= 2 && VerifyFPU) {
5728 verify_FPU(0, "FPU stack must be clean on entry");
5729 }
5730 #endif
5731
5732 #ifdef ASSERT
5733 if (VerifyStackAtCalls) {
5734 Label L;
5735 push(rax);
5736 mov(rax, rsp);
5737 andptr(rax, StackAlignmentInBytes-1);
5738 cmpptr(rax, StackAlignmentInBytes-wordSize);
5739 pop(rax);
5740 jcc(Assembler::equal, L);
5741 STOP("Stack is not properly aligned!");
5742 bind(L);
5743 }
5744 #endif
5745
5746 if (!is_stub) {
5747 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5748 bs->nmethod_entry_barrier(this);
5749 }
5750 }
5751
5752 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5753 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5754 // cnt - number of qwords (8-byte words).
5755 // base - start address, qword aligned.
5756 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5757 if (UseAVX >= 2) {
5758 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5759 } else {
5760 pxor(xtmp, xtmp);
5761 }
5762 jmp(L_zero_64_bytes);
5763
5764 BIND(L_loop);
5765 if (UseAVX >= 2) {
5766 vmovdqu(Address(base, 0), xtmp);
5767 vmovdqu(Address(base, 32), xtmp);
5768 } else {
5769 movdqu(Address(base, 0), xtmp);
5770 movdqu(Address(base, 16), xtmp);
5771 movdqu(Address(base, 32), xtmp);
5772 movdqu(Address(base, 48), xtmp);
5773 }
5774 addptr(base, 64);
5775
5776 BIND(L_zero_64_bytes);
5777 subptr(cnt, 8);
5778 jccb(Assembler::greaterEqual, L_loop);
5779 addptr(cnt, 4);
5780 jccb(Assembler::less, L_tail);
5781 // Copy trailing 32 bytes
5782 if (UseAVX >= 2) {
5783 vmovdqu(Address(base, 0), xtmp);
5784 } else {
5785 movdqu(Address(base, 0), xtmp);
5786 movdqu(Address(base, 16), xtmp);
5787 }
5788 addptr(base, 32);
5789 subptr(cnt, 4);
5790
5791 BIND(L_tail);
5792 addptr(cnt, 4);
5793 jccb(Assembler::lessEqual, L_end);
5794 decrement(cnt);
5795
5796 BIND(L_sloop);
5797 movq(Address(base, 0), xtmp);
5798 addptr(base, 8);
5799 decrement(cnt);
5800 jccb(Assembler::greaterEqual, L_sloop);
5801 BIND(L_end);
5802 }
5803
5804 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5805 // cnt - number of qwords (8-byte words).
5806 // base - start address, qword aligned.
5807 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5808 assert(base==rdi, "base register must be edi for rep stos");
5809 assert(tmp==rax, "tmp register must be eax for rep stos");
5810 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5811 assert(InitArrayShortSize % BytesPerLong == 0,
5812 "InitArrayShortSize should be the multiple of BytesPerLong");
5813
5814 Label DONE;
5815
5816 if (!is_large || !UseXMMForObjInit) {
5817 xorptr(tmp, tmp);
5818 }
5819
5820 if (!is_large) {
5821 Label LOOP, LONG;
5822 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5823 jccb(Assembler::greater, LONG);
5824
5825 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5826
5827 decrement(cnt);
5828 jccb(Assembler::negative, DONE); // Zero length
5829
5830 // Use individual pointer-sized stores for small counts:
5831 BIND(LOOP);
5832 movptr(Address(base, cnt, Address::times_ptr), tmp);
5833 decrement(cnt);
5834 jccb(Assembler::greaterEqual, LOOP);
5835 jmpb(DONE);
5836
5837 BIND(LONG);
5838 }
5839
5840 // Use longer rep-prefixed ops for non-small counts:
5841 if (UseFastStosb) {
5842 shlptr(cnt, 3); // convert to number of bytes
5843 rep_stosb();
5844 } else if (UseXMMForObjInit) {
5845 movptr(tmp, base);
5846 xmm_clear_mem(tmp, cnt, xtmp);
5847 } else {
5848 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5849 rep_stos();
5850 }
5851
5852 BIND(DONE);
5853 }
5854
5855 #ifdef COMPILER2
5856
5857 // IndexOf for constant substrings with size >= 8 chars
5858 // which don't need to be loaded through stack.
5859 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5860 Register cnt1, Register cnt2,
5861 int int_cnt2, Register result,
5862 XMMRegister vec, Register tmp,
5863 int ae) {
5864 ShortBranchVerifier sbv(this);
5865 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5866 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5867
5868 // This method uses the pcmpestri instruction with bound registers
5869 // inputs:
5870 // xmm - substring
5871 // rax - substring length (elements count)
5872 // mem - scanned string
5873 // rdx - string length (elements count)
5874 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5875 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5876 // outputs:
5877 // rcx - matched index in string
5878 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5879 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5880 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5881 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5882 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5883
5884 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5885 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5886 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5887
5888 // Note, inline_string_indexOf() generates checks:
5889 // if (substr.count > string.count) return -1;
5890 // if (substr.count == 0) return 0;
5891 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5892
5893 // Load substring.
5894 if (ae == StrIntrinsicNode::UL) {
5895 pmovzxbw(vec, Address(str2, 0));
5896 } else {
5897 movdqu(vec, Address(str2, 0));
5898 }
5899 movl(cnt2, int_cnt2);
5900 movptr(result, str1); // string addr
5901
5902 if (int_cnt2 > stride) {
5903 jmpb(SCAN_TO_SUBSTR);
5904
5905 // Reload substr for rescan, this code
5906 // is executed only for large substrings (> 8 chars)
5907 bind(RELOAD_SUBSTR);
5908 if (ae == StrIntrinsicNode::UL) {
5909 pmovzxbw(vec, Address(str2, 0));
5910 } else {
5911 movdqu(vec, Address(str2, 0));
5912 }
5913 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5914
5915 bind(RELOAD_STR);
5916 // We came here after the beginning of the substring was
5917 // matched but the rest of it was not so we need to search
5918 // again. Start from the next element after the previous match.
5919
5920 // cnt2 is number of substring reminding elements and
5921 // cnt1 is number of string reminding elements when cmp failed.
5922 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5923 subl(cnt1, cnt2);
5924 addl(cnt1, int_cnt2);
5925 movl(cnt2, int_cnt2); // Now restore cnt2
5926
5927 decrementl(cnt1); // Shift to next element
5928 cmpl(cnt1, cnt2);
5929 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5930
5931 addptr(result, (1<<scale1));
5932
5933 } // (int_cnt2 > 8)
5934
5935 // Scan string for start of substr in 16-byte vectors
5936 bind(SCAN_TO_SUBSTR);
5937 pcmpestri(vec, Address(result, 0), mode);
5938 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
5939 subl(cnt1, stride);
5940 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5941 cmpl(cnt1, cnt2);
5942 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5943 addptr(result, 16);
5944 jmpb(SCAN_TO_SUBSTR);
5945
5946 // Found a potential substr
5947 bind(FOUND_CANDIDATE);
5948 // Matched whole vector if first element matched (tmp(rcx) == 0).
5949 if (int_cnt2 == stride) {
5950 jccb(Assembler::overflow, RET_FOUND); // OF == 1
5951 } else { // int_cnt2 > 8
5952 jccb(Assembler::overflow, FOUND_SUBSTR);
5953 }
5954 // After pcmpestri tmp(rcx) contains matched element index
5955 // Compute start addr of substr
5956 lea(result, Address(result, tmp, scale1));
5957
5958 // Make sure string is still long enough
5959 subl(cnt1, tmp);
5960 cmpl(cnt1, cnt2);
5961 if (int_cnt2 == stride) {
5962 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5963 } else { // int_cnt2 > 8
5964 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5965 }
5966 // Left less then substring.
5967
5968 bind(RET_NOT_FOUND);
5969 movl(result, -1);
5970 jmp(EXIT);
5971
5972 if (int_cnt2 > stride) {
5973 // This code is optimized for the case when whole substring
5974 // is matched if its head is matched.
5975 bind(MATCH_SUBSTR_HEAD);
5976 pcmpestri(vec, Address(result, 0), mode);
5977 // Reload only string if does not match
5978 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5979
5980 Label CONT_SCAN_SUBSTR;
5981 // Compare the rest of substring (> 8 chars).
5982 bind(FOUND_SUBSTR);
5983 // First 8 chars are already matched.
5984 negptr(cnt2);
5985 addptr(cnt2, stride);
5986
5987 bind(SCAN_SUBSTR);
5988 subl(cnt1, stride);
5989 cmpl(cnt2, -stride); // Do not read beyond substring
5990 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5991 // Back-up strings to avoid reading beyond substring:
5992 // cnt1 = cnt1 - cnt2 + 8
5993 addl(cnt1, cnt2); // cnt2 is negative
5994 addl(cnt1, stride);
5995 movl(cnt2, stride); negptr(cnt2);
5996 bind(CONT_SCAN_SUBSTR);
5997 if (int_cnt2 < (int)G) {
5998 int tail_off1 = int_cnt2<<scale1;
5999 int tail_off2 = int_cnt2<<scale2;
6000 if (ae == StrIntrinsicNode::UL) {
6001 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6002 } else {
6003 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6004 }
6005 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6006 } else {
6007 // calculate index in register to avoid integer overflow (int_cnt2*2)
6008 movl(tmp, int_cnt2);
6009 addptr(tmp, cnt2);
6010 if (ae == StrIntrinsicNode::UL) {
6011 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6012 } else {
6013 movdqu(vec, Address(str2, tmp, scale2, 0));
6014 }
6015 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6016 }
6017 // Need to reload strings pointers if not matched whole vector
6018 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6019 addptr(cnt2, stride);
6020 jcc(Assembler::negative, SCAN_SUBSTR);
6021 // Fall through if found full substring
6022
6023 } // (int_cnt2 > 8)
6024
6025 bind(RET_FOUND);
6026 // Found result if we matched full small substring.
6027 // Compute substr offset
6028 subptr(result, str1);
6029 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6030 shrl(result, 1); // index
6031 }
6032 bind(EXIT);
6033
6034 } // string_indexofC8
6035
6036 // Small strings are loaded through stack if they cross page boundary.
6037 void MacroAssembler::string_indexof(Register str1, Register str2,
6038 Register cnt1, Register cnt2,
6039 int int_cnt2, Register result,
6040 XMMRegister vec, Register tmp,
6041 int ae) {
6042 ShortBranchVerifier sbv(this);
6043 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6044 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6045
6046 //
6047 // int_cnt2 is length of small (< 8 chars) constant substring
6048 // or (-1) for non constant substring in which case its length
6049 // is in cnt2 register.
6050 //
6051 // Note, inline_string_indexOf() generates checks:
6052 // if (substr.count > string.count) return -1;
6053 // if (substr.count == 0) return 0;
6054 //
6055 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6056 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6057 // This method uses the pcmpestri instruction with bound registers
6058 // inputs:
6059 // xmm - substring
6060 // rax - substring length (elements count)
6061 // mem - scanned string
6062 // rdx - string length (elements count)
6063 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6064 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6065 // outputs:
6066 // rcx - matched index in string
6067 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6068 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6069 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6070 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6071
6072 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6073 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6074 FOUND_CANDIDATE;
6075
6076 { //========================================================
6077 // We don't know where these strings are located
6078 // and we can't read beyond them. Load them through stack.
6079 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6080
6081 movptr(tmp, rsp); // save old SP
6082
6083 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6084 if (int_cnt2 == (1>>scale2)) { // One byte
6085 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6086 load_unsigned_byte(result, Address(str2, 0));
6087 movdl(vec, result); // move 32 bits
6088 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6089 // Not enough header space in 32-bit VM: 12+3 = 15.
6090 movl(result, Address(str2, -1));
6091 shrl(result, 8);
6092 movdl(vec, result); // move 32 bits
6093 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6094 load_unsigned_short(result, Address(str2, 0));
6095 movdl(vec, result); // move 32 bits
6096 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6097 movdl(vec, Address(str2, 0)); // move 32 bits
6098 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6099 movq(vec, Address(str2, 0)); // move 64 bits
6100 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6101 // Array header size is 12 bytes in 32-bit VM
6102 // + 6 bytes for 3 chars == 18 bytes,
6103 // enough space to load vec and shift.
6104 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6105 if (ae == StrIntrinsicNode::UL) {
6106 int tail_off = int_cnt2-8;
6107 pmovzxbw(vec, Address(str2, tail_off));
6108 psrldq(vec, -2*tail_off);
6109 }
6110 else {
6111 int tail_off = int_cnt2*(1<<scale2);
6112 movdqu(vec, Address(str2, tail_off-16));
6113 psrldq(vec, 16-tail_off);
6114 }
6115 }
6116 } else { // not constant substring
6117 cmpl(cnt2, stride);
6118 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6119
6120 // We can read beyond string if srt+16 does not cross page boundary
6121 // since heaps are aligned and mapped by pages.
6122 assert(os::vm_page_size() < (int)G, "default page should be small");
6123 movl(result, str2); // We need only low 32 bits
6124 andl(result, (os::vm_page_size()-1));
6125 cmpl(result, (os::vm_page_size()-16));
6126 jccb(Assembler::belowEqual, CHECK_STR);
6127
6128 // Move small strings to stack to allow load 16 bytes into vec.
6129 subptr(rsp, 16);
6130 int stk_offset = wordSize-(1<<scale2);
6131 push(cnt2);
6132
6133 bind(COPY_SUBSTR);
6134 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6135 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6136 movb(Address(rsp, cnt2, scale2, stk_offset), result);
6137 } else if (ae == StrIntrinsicNode::UU) {
6138 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
6139 movw(Address(rsp, cnt2, scale2, stk_offset), result);
6140 }
6141 decrement(cnt2);
6142 jccb(Assembler::notZero, COPY_SUBSTR);
6143
6144 pop(cnt2);
6145 movptr(str2, rsp); // New substring address
6146 } // non constant
6147
6148 bind(CHECK_STR);
6149 cmpl(cnt1, stride);
6150 jccb(Assembler::aboveEqual, BIG_STRINGS);
6151
6152 // Check cross page boundary.
6153 movl(result, str1); // We need only low 32 bits
6154 andl(result, (os::vm_page_size()-1));
6155 cmpl(result, (os::vm_page_size()-16));
6156 jccb(Assembler::belowEqual, BIG_STRINGS);
6157
6158 subptr(rsp, 16);
6159 int stk_offset = -(1<<scale1);
6160 if (int_cnt2 < 0) { // not constant
6161 push(cnt2);
6162 stk_offset += wordSize;
6163 }
6164 movl(cnt2, cnt1);
6165
6166 bind(COPY_STR);
6167 if (ae == StrIntrinsicNode::LL) {
6168 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
6169 movb(Address(rsp, cnt2, scale1, stk_offset), result);
6170 } else {
6171 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
6172 movw(Address(rsp, cnt2, scale1, stk_offset), result);
6173 }
6174 decrement(cnt2);
6175 jccb(Assembler::notZero, COPY_STR);
6176
6177 if (int_cnt2 < 0) { // not constant
6178 pop(cnt2);
6179 }
6180 movptr(str1, rsp); // New string address
6181
6182 bind(BIG_STRINGS);
6183 // Load substring.
6184 if (int_cnt2 < 0) { // -1
6185 if (ae == StrIntrinsicNode::UL) {
6186 pmovzxbw(vec, Address(str2, 0));
6187 } else {
6188 movdqu(vec, Address(str2, 0));
6189 }
6190 push(cnt2); // substr count
6191 push(str2); // substr addr
6192 push(str1); // string addr
6193 } else {
6194 // Small (< 8 chars) constant substrings are loaded already.
6195 movl(cnt2, int_cnt2);
6196 }
6197 push(tmp); // original SP
6198
6199 } // Finished loading
6200
6201 //========================================================
6202 // Start search
6203 //
6204
6205 movptr(result, str1); // string addr
6206
6207 if (int_cnt2 < 0) { // Only for non constant substring
6208 jmpb(SCAN_TO_SUBSTR);
6209
6210 // SP saved at sp+0
6211 // String saved at sp+1*wordSize
6212 // Substr saved at sp+2*wordSize
6213 // Substr count saved at sp+3*wordSize
6214
6215 // Reload substr for rescan, this code
6216 // is executed only for large substrings (> 8 chars)
6217 bind(RELOAD_SUBSTR);
6218 movptr(str2, Address(rsp, 2*wordSize));
6219 movl(cnt2, Address(rsp, 3*wordSize));
6220 if (ae == StrIntrinsicNode::UL) {
6221 pmovzxbw(vec, Address(str2, 0));
6222 } else {
6223 movdqu(vec, Address(str2, 0));
6224 }
6225 // We came here after the beginning of the substring was
6226 // matched but the rest of it was not so we need to search
6227 // again. Start from the next element after the previous match.
6228 subptr(str1, result); // Restore counter
6229 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6230 shrl(str1, 1);
6231 }
6232 addl(cnt1, str1);
6233 decrementl(cnt1); // Shift to next element
6234 cmpl(cnt1, cnt2);
6235 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6236
6237 addptr(result, (1<<scale1));
6238 } // non constant
6239
6240 // Scan string for start of substr in 16-byte vectors
6241 bind(SCAN_TO_SUBSTR);
6242 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6243 pcmpestri(vec, Address(result, 0), mode);
6244 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6245 subl(cnt1, stride);
6246 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6247 cmpl(cnt1, cnt2);
6248 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6249 addptr(result, 16);
6250
6251 bind(ADJUST_STR);
6252 cmpl(cnt1, stride); // Do not read beyond string
6253 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6254 // Back-up string to avoid reading beyond string.
6255 lea(result, Address(result, cnt1, scale1, -16));
6256 movl(cnt1, stride);
6257 jmpb(SCAN_TO_SUBSTR);
6258
6259 // Found a potential substr
6260 bind(FOUND_CANDIDATE);
6261 // After pcmpestri tmp(rcx) contains matched element index
6262
6263 // Make sure string is still long enough
6264 subl(cnt1, tmp);
6265 cmpl(cnt1, cnt2);
6266 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6267 // Left less then substring.
6268
6269 bind(RET_NOT_FOUND);
6270 movl(result, -1);
6271 jmp(CLEANUP);
6272
6273 bind(FOUND_SUBSTR);
6274 // Compute start addr of substr
6275 lea(result, Address(result, tmp, scale1));
6276 if (int_cnt2 > 0) { // Constant substring
6277 // Repeat search for small substring (< 8 chars)
6278 // from new point without reloading substring.
6279 // Have to check that we don't read beyond string.
6280 cmpl(tmp, stride-int_cnt2);
6281 jccb(Assembler::greater, ADJUST_STR);
6282 // Fall through if matched whole substring.
6283 } else { // non constant
6284 assert(int_cnt2 == -1, "should be != 0");
6285
6286 addl(tmp, cnt2);
6287 // Found result if we matched whole substring.
6288 cmpl(tmp, stride);
6289 jcc(Assembler::lessEqual, RET_FOUND);
6290
6291 // Repeat search for small substring (<= 8 chars)
6292 // from new point 'str1' without reloading substring.
6293 cmpl(cnt2, stride);
6294 // Have to check that we don't read beyond string.
6295 jccb(Assembler::lessEqual, ADJUST_STR);
6296
6297 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6298 // Compare the rest of substring (> 8 chars).
6299 movptr(str1, result);
6300
6301 cmpl(tmp, cnt2);
6302 // First 8 chars are already matched.
6303 jccb(Assembler::equal, CHECK_NEXT);
6304
6305 bind(SCAN_SUBSTR);
6306 pcmpestri(vec, Address(str1, 0), mode);
6307 // Need to reload strings pointers if not matched whole vector
6308 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6309
6310 bind(CHECK_NEXT);
6311 subl(cnt2, stride);
6312 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6313 addptr(str1, 16);
6314 if (ae == StrIntrinsicNode::UL) {
6315 addptr(str2, 8);
6316 } else {
6317 addptr(str2, 16);
6318 }
6319 subl(cnt1, stride);
6320 cmpl(cnt2, stride); // Do not read beyond substring
6321 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6322 // Back-up strings to avoid reading beyond substring.
6323
6324 if (ae == StrIntrinsicNode::UL) {
6325 lea(str2, Address(str2, cnt2, scale2, -8));
6326 lea(str1, Address(str1, cnt2, scale1, -16));
6327 } else {
6328 lea(str2, Address(str2, cnt2, scale2, -16));
6329 lea(str1, Address(str1, cnt2, scale1, -16));
6330 }
6331 subl(cnt1, cnt2);
6332 movl(cnt2, stride);
6333 addl(cnt1, stride);
6334 bind(CONT_SCAN_SUBSTR);
6335 if (ae == StrIntrinsicNode::UL) {
6336 pmovzxbw(vec, Address(str2, 0));
6337 } else {
6338 movdqu(vec, Address(str2, 0));
6339 }
6340 jmp(SCAN_SUBSTR);
6341
6342 bind(RET_FOUND_LONG);
6343 movptr(str1, Address(rsp, wordSize));
6344 } // non constant
6345
6346 bind(RET_FOUND);
6347 // Compute substr offset
6348 subptr(result, str1);
6349 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6350 shrl(result, 1); // index
6351 }
6352 bind(CLEANUP);
6353 pop(rsp); // restore SP
6354
6355 } // string_indexof
6356
6357 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6358 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6359 ShortBranchVerifier sbv(this);
6360 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6361
6362 int stride = 8;
6363
6364 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6365 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6366 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6367 FOUND_SEQ_CHAR, DONE_LABEL;
6368
6369 movptr(result, str1);
6370 if (UseAVX >= 2) {
6371 cmpl(cnt1, stride);
6372 jcc(Assembler::less, SCAN_TO_CHAR);
6373 cmpl(cnt1, 2*stride);
6374 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6375 movdl(vec1, ch);
6376 vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6377 vpxor(vec2, vec2);
6378 movl(tmp, cnt1);
6379 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
6380 andl(cnt1,0x0000000F); //tail count (in chars)
6381
6382 bind(SCAN_TO_16_CHAR_LOOP);
6383 vmovdqu(vec3, Address(result, 0));
6384 vpcmpeqw(vec3, vec3, vec1, 1);
6385 vptest(vec2, vec3);
6386 jcc(Assembler::carryClear, FOUND_CHAR);
6387 addptr(result, 32);
6388 subl(tmp, 2*stride);
6389 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6390 jmp(SCAN_TO_8_CHAR);
6391 bind(SCAN_TO_8_CHAR_INIT);
6392 movdl(vec1, ch);
6393 pshuflw(vec1, vec1, 0x00);
6394 pshufd(vec1, vec1, 0);
6395 pxor(vec2, vec2);
6396 }
6397 bind(SCAN_TO_8_CHAR);
6398 cmpl(cnt1, stride);
6399 jcc(Assembler::less, SCAN_TO_CHAR);
6400 if (UseAVX < 2) {
6401 movdl(vec1, ch);
6402 pshuflw(vec1, vec1, 0x00);
6403 pshufd(vec1, vec1, 0);
6404 pxor(vec2, vec2);
6405 }
6406 movl(tmp, cnt1);
6407 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
6408 andl(cnt1,0x00000007); //tail count (in chars)
6409
6410 bind(SCAN_TO_8_CHAR_LOOP);
6411 movdqu(vec3, Address(result, 0));
6412 pcmpeqw(vec3, vec1);
6413 ptest(vec2, vec3);
6414 jcc(Assembler::carryClear, FOUND_CHAR);
6415 addptr(result, 16);
6416 subl(tmp, stride);
6417 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6418 bind(SCAN_TO_CHAR);
6419 testl(cnt1, cnt1);
6420 jcc(Assembler::zero, RET_NOT_FOUND);
6421 bind(SCAN_TO_CHAR_LOOP);
6422 load_unsigned_short(tmp, Address(result, 0));
6423 cmpl(ch, tmp);
6424 jccb(Assembler::equal, FOUND_SEQ_CHAR);
6425 addptr(result, 2);
6426 subl(cnt1, 1);
6427 jccb(Assembler::zero, RET_NOT_FOUND);
6428 jmp(SCAN_TO_CHAR_LOOP);
6429
6430 bind(RET_NOT_FOUND);
6431 movl(result, -1);
6432 jmpb(DONE_LABEL);
6433
6434 bind(FOUND_CHAR);
6435 if (UseAVX >= 2) {
6436 vpmovmskb(tmp, vec3);
6437 } else {
6438 pmovmskb(tmp, vec3);
6439 }
6440 bsfl(ch, tmp);
6441 addl(result, ch);
6442
6443 bind(FOUND_SEQ_CHAR);
6444 subptr(result, str1);
6445 shrl(result, 1);
6446
6447 bind(DONE_LABEL);
6448 } // string_indexof_char
6449
6450 // helper function for string_compare
6451 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6452 Address::ScaleFactor scale, Address::ScaleFactor scale1,
6453 Address::ScaleFactor scale2, Register index, int ae) {
6454 if (ae == StrIntrinsicNode::LL) {
6455 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6456 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6457 } else if (ae == StrIntrinsicNode::UU) {
6458 load_unsigned_short(elem1, Address(str1, index, scale, 0));
6459 load_unsigned_short(elem2, Address(str2, index, scale, 0));
6460 } else {
6461 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6462 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6463 }
6464 }
6465
6466 // Compare strings, used for char[] and byte[].
6467 void MacroAssembler::string_compare(Register str1, Register str2,
6468 Register cnt1, Register cnt2, Register result,
6469 XMMRegister vec1, int ae) {
6470 ShortBranchVerifier sbv(this);
6471 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6472 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
6473 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6474 int stride2x2 = 0x40;
6475 Address::ScaleFactor scale = Address::no_scale;
6476 Address::ScaleFactor scale1 = Address::no_scale;
6477 Address::ScaleFactor scale2 = Address::no_scale;
6478
6479 if (ae != StrIntrinsicNode::LL) {
6480 stride2x2 = 0x20;
6481 }
6482
6483 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6484 shrl(cnt2, 1);
6485 }
6486 // Compute the minimum of the string lengths and the
6487 // difference of the string lengths (stack).
6488 // Do the conditional move stuff
6489 movl(result, cnt1);
6490 subl(cnt1, cnt2);
6491 push(cnt1);
6492 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
6493
6494 // Is the minimum length zero?
6495 testl(cnt2, cnt2);
6496 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6497 if (ae == StrIntrinsicNode::LL) {
6498 // Load first bytes
6499 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
6500 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
6501 } else if (ae == StrIntrinsicNode::UU) {
6502 // Load first characters
6503 load_unsigned_short(result, Address(str1, 0));
6504 load_unsigned_short(cnt1, Address(str2, 0));
6505 } else {
6506 load_unsigned_byte(result, Address(str1, 0));
6507 load_unsigned_short(cnt1, Address(str2, 0));
6508 }
6509 subl(result, cnt1);
6510 jcc(Assembler::notZero, POP_LABEL);
6511
6512 if (ae == StrIntrinsicNode::UU) {
6513 // Divide length by 2 to get number of chars
6514 shrl(cnt2, 1);
6515 }
6516 cmpl(cnt2, 1);
6517 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6518
6519 // Check if the strings start at the same location and setup scale and stride
6520 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6521 cmpptr(str1, str2);
6522 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6523 if (ae == StrIntrinsicNode::LL) {
6524 scale = Address::times_1;
6525 stride = 16;
6526 } else {
6527 scale = Address::times_2;
6528 stride = 8;
6529 }
6530 } else {
6531 scale1 = Address::times_1;
6532 scale2 = Address::times_2;
6533 // scale not used
6534 stride = 8;
6535 }
6536
6537 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6538 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6539 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6540 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6541 Label COMPARE_TAIL_LONG;
6542 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
6543
6544 int pcmpmask = 0x19;
6545 if (ae == StrIntrinsicNode::LL) {
6546 pcmpmask &= ~0x01;
6547 }
6548
6549 // Setup to compare 16-chars (32-bytes) vectors,
6550 // start from first character again because it has aligned address.
6551 if (ae == StrIntrinsicNode::LL) {
6552 stride2 = 32;
6553 } else {
6554 stride2 = 16;
6555 }
6556 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6557 adr_stride = stride << scale;
6558 } else {
6559 adr_stride1 = 8; //stride << scale1;
6560 adr_stride2 = 16; //stride << scale2;
6561 }
6562
6563 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6564 // rax and rdx are used by pcmpestri as elements counters
6565 movl(result, cnt2);
6566 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6567 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6568
6569 // fast path : compare first 2 8-char vectors.
6570 bind(COMPARE_16_CHARS);
6571 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6572 movdqu(vec1, Address(str1, 0));
6573 } else {
6574 pmovzxbw(vec1, Address(str1, 0));
6575 }
6576 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6577 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6578
6579 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6580 movdqu(vec1, Address(str1, adr_stride));
6581 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6582 } else {
6583 pmovzxbw(vec1, Address(str1, adr_stride1));
6584 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6585 }
6586 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6587 addl(cnt1, stride);
6588
6589 // Compare the characters at index in cnt1
6590 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6591 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6592 subl(result, cnt2);
6593 jmp(POP_LABEL);
6594
6595 // Setup the registers to start vector comparison loop
6596 bind(COMPARE_WIDE_VECTORS);
6597 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6598 lea(str1, Address(str1, result, scale));
6599 lea(str2, Address(str2, result, scale));
6600 } else {
6601 lea(str1, Address(str1, result, scale1));
6602 lea(str2, Address(str2, result, scale2));
6603 }
6604 subl(result, stride2);
6605 subl(cnt2, stride2);
6606 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6607 negptr(result);
6608
6609 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6610 bind(COMPARE_WIDE_VECTORS_LOOP);
6611
6612 #ifdef _LP64
6613 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6614 cmpl(cnt2, stride2x2);
6615 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6616 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
6617 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
6618
6619 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6620 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6621 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6622 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6623 } else {
6624 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6625 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6626 }
6627 kortestql(k7, k7);
6628 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
6629 addptr(result, stride2x2); // update since we already compared at this addr
6630 subl(cnt2, stride2x2); // and sub the size too
6631 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6632
6633 vpxor(vec1, vec1);
6634 jmpb(COMPARE_WIDE_TAIL);
6635 }//if (VM_Version::supports_avx512vlbw())
6636 #endif // _LP64
6637
6638
6639 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6640 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6641 vmovdqu(vec1, Address(str1, result, scale));
6642 vpxor(vec1, Address(str2, result, scale));
6643 } else {
6644 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6645 vpxor(vec1, Address(str2, result, scale2));
6646 }
6647 vptest(vec1, vec1);
6648 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6649 addptr(result, stride2);
6650 subl(cnt2, stride2);
6651 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6652 // clean upper bits of YMM registers
6653 vpxor(vec1, vec1);
6654
6655 // compare wide vectors tail
6656 bind(COMPARE_WIDE_TAIL);
6657 testptr(result, result);
6658 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6659
6660 movl(result, stride2);
6661 movl(cnt2, result);
6662 negptr(result);
6663 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6664
6665 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6666 bind(VECTOR_NOT_EQUAL);
6667 // clean upper bits of YMM registers
6668 vpxor(vec1, vec1);
6669 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6670 lea(str1, Address(str1, result, scale));
6671 lea(str2, Address(str2, result, scale));
6672 } else {
6673 lea(str1, Address(str1, result, scale1));
6674 lea(str2, Address(str2, result, scale2));
6675 }
6676 jmp(COMPARE_16_CHARS);
6677
6678 // Compare tail chars, length between 1 to 15 chars
6679 bind(COMPARE_TAIL_LONG);
6680 movl(cnt2, result);
6681 cmpl(cnt2, stride);
6682 jcc(Assembler::less, COMPARE_SMALL_STR);
6683
6684 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6685 movdqu(vec1, Address(str1, 0));
6686 } else {
6687 pmovzxbw(vec1, Address(str1, 0));
6688 }
6689 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6690 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6691 subptr(cnt2, stride);
6692 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6693 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6694 lea(str1, Address(str1, result, scale));
6695 lea(str2, Address(str2, result, scale));
6696 } else {
6697 lea(str1, Address(str1, result, scale1));
6698 lea(str2, Address(str2, result, scale2));
6699 }
6700 negptr(cnt2);
6701 jmpb(WHILE_HEAD_LABEL);
6702
6703 bind(COMPARE_SMALL_STR);
6704 } else if (UseSSE42Intrinsics) {
6705 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6706 int pcmpmask = 0x19;
6707 // Setup to compare 8-char (16-byte) vectors,
6708 // start from first character again because it has aligned address.
6709 movl(result, cnt2);
6710 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6711 if (ae == StrIntrinsicNode::LL) {
6712 pcmpmask &= ~0x01;
6713 }
6714 jcc(Assembler::zero, COMPARE_TAIL);
6715 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6716 lea(str1, Address(str1, result, scale));
6717 lea(str2, Address(str2, result, scale));
6718 } else {
6719 lea(str1, Address(str1, result, scale1));
6720 lea(str2, Address(str2, result, scale2));
6721 }
6722 negptr(result);
6723
6724 // pcmpestri
6725 // inputs:
6726 // vec1- substring
6727 // rax - negative string length (elements count)
6728 // mem - scanned string
6729 // rdx - string length (elements count)
6730 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6731 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6732 // outputs:
6733 // rcx - first mismatched element index
6734 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6735
6736 bind(COMPARE_WIDE_VECTORS);
6737 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6738 movdqu(vec1, Address(str1, result, scale));
6739 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6740 } else {
6741 pmovzxbw(vec1, Address(str1, result, scale1));
6742 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6743 }
6744 // After pcmpestri cnt1(rcx) contains mismatched element index
6745
6746 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6747 addptr(result, stride);
6748 subptr(cnt2, stride);
6749 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6750
6751 // compare wide vectors tail
6752 testptr(result, result);
6753 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6754
6755 movl(cnt2, stride);
6756 movl(result, stride);
6757 negptr(result);
6758 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6759 movdqu(vec1, Address(str1, result, scale));
6760 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6761 } else {
6762 pmovzxbw(vec1, Address(str1, result, scale1));
6763 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6764 }
6765 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6766
6767 // Mismatched characters in the vectors
6768 bind(VECTOR_NOT_EQUAL);
6769 addptr(cnt1, result);
6770 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6771 subl(result, cnt2);
6772 jmpb(POP_LABEL);
6773
6774 bind(COMPARE_TAIL); // limit is zero
6775 movl(cnt2, result);
6776 // Fallthru to tail compare
6777 }
6778 // Shift str2 and str1 to the end of the arrays, negate min
6779 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6780 lea(str1, Address(str1, cnt2, scale));
6781 lea(str2, Address(str2, cnt2, scale));
6782 } else {
6783 lea(str1, Address(str1, cnt2, scale1));
6784 lea(str2, Address(str2, cnt2, scale2));
6785 }
6786 decrementl(cnt2); // first character was compared already
6787 negptr(cnt2);
6788
6789 // Compare the rest of the elements
6790 bind(WHILE_HEAD_LABEL);
6791 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6792 subl(result, cnt1);
6793 jccb(Assembler::notZero, POP_LABEL);
6794 increment(cnt2);
6795 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6796
6797 // Strings are equal up to min length. Return the length difference.
6798 bind(LENGTH_DIFF_LABEL);
6799 pop(result);
6800 if (ae == StrIntrinsicNode::UU) {
6801 // Divide diff by 2 to get number of chars
6802 sarl(result, 1);
6803 }
6804 jmpb(DONE_LABEL);
6805
6806 #ifdef _LP64
6807 if (VM_Version::supports_avx512vlbw()) {
6808
6809 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6810
6811 kmovql(cnt1, k7);
6812 notq(cnt1);
6813 bsfq(cnt2, cnt1);
6814 if (ae != StrIntrinsicNode::LL) {
6815 // Divide diff by 2 to get number of chars
6816 sarl(cnt2, 1);
6817 }
6818 addq(result, cnt2);
6819 if (ae == StrIntrinsicNode::LL) {
6820 load_unsigned_byte(cnt1, Address(str2, result));
6821 load_unsigned_byte(result, Address(str1, result));
6822 } else if (ae == StrIntrinsicNode::UU) {
6823 load_unsigned_short(cnt1, Address(str2, result, scale));
6824 load_unsigned_short(result, Address(str1, result, scale));
6825 } else {
6826 load_unsigned_short(cnt1, Address(str2, result, scale2));
6827 load_unsigned_byte(result, Address(str1, result, scale1));
6828 }
6829 subl(result, cnt1);
6830 jmpb(POP_LABEL);
6831 }//if (VM_Version::supports_avx512vlbw())
6832 #endif // _LP64
6833
6834 // Discard the stored length difference
6835 bind(POP_LABEL);
6836 pop(cnt1);
6837
6838 // That's it
6839 bind(DONE_LABEL);
6840 if(ae == StrIntrinsicNode::UL) {
6841 negl(result);
6842 }
6843
6844 }
6845
6846 // Search for Non-ASCII character (Negative byte value) in a byte array,
6847 // return true if it has any and false otherwise.
6848 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6849 // @HotSpotIntrinsicCandidate
6850 // private static boolean hasNegatives(byte[] ba, int off, int len) {
6851 // for (int i = off; i < off + len; i++) {
6852 // if (ba[i] < 0) {
6853 // return true;
6854 // }
6855 // }
6856 // return false;
6857 // }
6858 void MacroAssembler::has_negatives(Register ary1, Register len,
6859 Register result, Register tmp1,
6860 XMMRegister vec1, XMMRegister vec2) {
6861 // rsi: byte array
6862 // rcx: len
6863 // rax: result
6864 ShortBranchVerifier sbv(this);
6865 assert_different_registers(ary1, len, result, tmp1);
6866 assert_different_registers(vec1, vec2);
6867 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6868
6869 // len == 0
6870 testl(len, len);
6871 jcc(Assembler::zero, FALSE_LABEL);
6872
6873 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
6874 VM_Version::supports_avx512vlbw() &&
6875 VM_Version::supports_bmi2()) {
6876
6877 Label test_64_loop, test_tail;
6878 Register tmp3_aliased = len;
6879
6880 movl(tmp1, len);
6881 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6882
6883 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
6884 andl(len, ~(64 - 1)); // vector count (in chars)
6885 jccb(Assembler::zero, test_tail);
6886
6887 lea(ary1, Address(ary1, len, Address::times_1));
6888 negptr(len);
6889
6890 bind(test_64_loop);
6891 // Check whether our 64 elements of size byte contain negatives
6892 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6893 kortestql(k2, k2);
6894 jcc(Assembler::notZero, TRUE_LABEL);
6895
6896 addptr(len, 64);
6897 jccb(Assembler::notZero, test_64_loop);
6898
6899
6900 bind(test_tail);
6901 // bail out when there is nothing to be done
6902 testl(tmp1, -1);
6903 jcc(Assembler::zero, FALSE_LABEL);
6904
6905 // ~(~0 << len) applied up to two times (for 32-bit scenario)
6906 #ifdef _LP64
6907 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6908 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6909 notq(tmp3_aliased);
6910 kmovql(k3, tmp3_aliased);
6911 #else
6912 Label k_init;
6913 jmp(k_init);
6914
6915 // We could not read 64-bits from a general purpose register thus we move
6916 // data required to compose 64 1's to the instruction stream
6917 // We emit 64 byte wide series of elements from 0..63 which later on would
6918 // be used as a compare targets with tail count contained in tmp1 register.
6919 // Result would be a k register having tmp1 consecutive number or 1
6920 // counting from least significant bit.
6921 address tmp = pc();
6922 emit_int64(0x0706050403020100);
6923 emit_int64(0x0F0E0D0C0B0A0908);
6924 emit_int64(0x1716151413121110);
6925 emit_int64(0x1F1E1D1C1B1A1918);
6926 emit_int64(0x2726252423222120);
6927 emit_int64(0x2F2E2D2C2B2A2928);
6928 emit_int64(0x3736353433323130);
6929 emit_int64(0x3F3E3D3C3B3A3938);
6930
6931 bind(k_init);
6932 lea(len, InternalAddress(tmp));
6933 // create mask to test for negative byte inside a vector
6934 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6935 evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
6936
6937 #endif
6938 evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6939 ktestq(k2, k3);
6940 jcc(Assembler::notZero, TRUE_LABEL);
6941
6942 jmp(FALSE_LABEL);
6943 } else {
6944 movl(result, len); // copy
6945
6946 if (UseAVX >= 2 && UseSSE >= 2) {
6947 // With AVX2, use 32-byte vector compare
6948 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6949
6950 // Compare 32-byte vectors
6951 andl(result, 0x0000001f); // tail count (in bytes)
6952 andl(len, 0xffffffe0); // vector count (in bytes)
6953 jccb(Assembler::zero, COMPARE_TAIL);
6954
6955 lea(ary1, Address(ary1, len, Address::times_1));
6956 negptr(len);
6957
6958 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
6959 movdl(vec2, tmp1);
6960 vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6961
6962 bind(COMPARE_WIDE_VECTORS);
6963 vmovdqu(vec1, Address(ary1, len, Address::times_1));
6964 vptest(vec1, vec2);
6965 jccb(Assembler::notZero, TRUE_LABEL);
6966 addptr(len, 32);
6967 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6968
6969 testl(result, result);
6970 jccb(Assembler::zero, FALSE_LABEL);
6971
6972 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6973 vptest(vec1, vec2);
6974 jccb(Assembler::notZero, TRUE_LABEL);
6975 jmpb(FALSE_LABEL);
6976
6977 bind(COMPARE_TAIL); // len is zero
6978 movl(len, result);
6979 // Fallthru to tail compare
6980 } else if (UseSSE42Intrinsics) {
6981 // With SSE4.2, use double quad vector compare
6982 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6983
6984 // Compare 16-byte vectors
6985 andl(result, 0x0000000f); // tail count (in bytes)
6986 andl(len, 0xfffffff0); // vector count (in bytes)
6987 jcc(Assembler::zero, COMPARE_TAIL);
6988
6989 lea(ary1, Address(ary1, len, Address::times_1));
6990 negptr(len);
6991
6992 movl(tmp1, 0x80808080);
6993 movdl(vec2, tmp1);
6994 pshufd(vec2, vec2, 0);
6995
6996 bind(COMPARE_WIDE_VECTORS);
6997 movdqu(vec1, Address(ary1, len, Address::times_1));
6998 ptest(vec1, vec2);
6999 jcc(Assembler::notZero, TRUE_LABEL);
7000 addptr(len, 16);
7001 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7002
7003 testl(result, result);
7004 jcc(Assembler::zero, FALSE_LABEL);
7005
7006 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7007 ptest(vec1, vec2);
7008 jccb(Assembler::notZero, TRUE_LABEL);
7009 jmpb(FALSE_LABEL);
7010
7011 bind(COMPARE_TAIL); // len is zero
7012 movl(len, result);
7013 // Fallthru to tail compare
7014 }
7015 }
7016 // Compare 4-byte vectors
7017 andl(len, 0xfffffffc); // vector count (in bytes)
7018 jccb(Assembler::zero, COMPARE_CHAR);
7019
7020 lea(ary1, Address(ary1, len, Address::times_1));
7021 negptr(len);
7022
7023 bind(COMPARE_VECTORS);
7024 movl(tmp1, Address(ary1, len, Address::times_1));
7025 andl(tmp1, 0x80808080);
7026 jccb(Assembler::notZero, TRUE_LABEL);
7027 addptr(len, 4);
7028 jcc(Assembler::notZero, COMPARE_VECTORS);
7029
7030 // Compare trailing char (final 2 bytes), if any
7031 bind(COMPARE_CHAR);
7032 testl(result, 0x2); // tail char
7033 jccb(Assembler::zero, COMPARE_BYTE);
7034 load_unsigned_short(tmp1, Address(ary1, 0));
7035 andl(tmp1, 0x00008080);
7036 jccb(Assembler::notZero, TRUE_LABEL);
7037 subptr(result, 2);
7038 lea(ary1, Address(ary1, 2));
7039
7040 bind(COMPARE_BYTE);
7041 testl(result, 0x1); // tail byte
7042 jccb(Assembler::zero, FALSE_LABEL);
7043 load_unsigned_byte(tmp1, Address(ary1, 0));
7044 andl(tmp1, 0x00000080);
7045 jccb(Assembler::notEqual, TRUE_LABEL);
7046 jmpb(FALSE_LABEL);
7047
7048 bind(TRUE_LABEL);
7049 movl(result, 1); // return true
7050 jmpb(DONE);
7051
7052 bind(FALSE_LABEL);
7053 xorl(result, result); // return false
7054
7055 // That's it
7056 bind(DONE);
7057 if (UseAVX >= 2 && UseSSE >= 2) {
7058 // clean upper bits of YMM registers
7059 vpxor(vec1, vec1);
7060 vpxor(vec2, vec2);
7061 }
7062 }
7063 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7064 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7065 Register limit, Register result, Register chr,
7066 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7067 ShortBranchVerifier sbv(this);
7068 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7069
7070 int length_offset = arrayOopDesc::length_offset_in_bytes();
7071 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7072
7073 if (is_array_equ) {
7074 // Check the input args
7075 cmpoop(ary1, ary2);
7076 jcc(Assembler::equal, TRUE_LABEL);
7077
7078 // Need additional checks for arrays_equals.
7079 testptr(ary1, ary1);
7080 jcc(Assembler::zero, FALSE_LABEL);
7081 testptr(ary2, ary2);
7082 jcc(Assembler::zero, FALSE_LABEL);
7083
7084 // Check the lengths
7085 movl(limit, Address(ary1, length_offset));
7086 cmpl(limit, Address(ary2, length_offset));
7087 jcc(Assembler::notEqual, FALSE_LABEL);
7088 }
7089
7090 // count == 0
7091 testl(limit, limit);
7092 jcc(Assembler::zero, TRUE_LABEL);
7093
7094 if (is_array_equ) {
7095 // Load array address
7096 lea(ary1, Address(ary1, base_offset));
7097 lea(ary2, Address(ary2, base_offset));
7098 }
7099
7100 if (is_array_equ && is_char) {
7101 // arrays_equals when used for char[].
7102 shll(limit, 1); // byte count != 0
7103 }
7104 movl(result, limit); // copy
7105
7106 if (UseAVX >= 2) {
7107 // With AVX2, use 32-byte vector compare
7108 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7109
7110 // Compare 32-byte vectors
7111 andl(result, 0x0000001f); // tail count (in bytes)
7112 andl(limit, 0xffffffe0); // vector count (in bytes)
7113 jcc(Assembler::zero, COMPARE_TAIL);
7114
7115 lea(ary1, Address(ary1, limit, Address::times_1));
7116 lea(ary2, Address(ary2, limit, Address::times_1));
7117 negptr(limit);
7118
7119 #ifdef _LP64
7120 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7121 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7122
7123 cmpl(limit, -64);
7124 jcc(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7125
7126 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7127
7128 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
7129 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
7130 kortestql(k7, k7);
7131 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7132 addptr(limit, 64); // update since we already compared at this addr
7133 cmpl(limit, -64);
7134 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7135
7136 // At this point we may still need to compare -limit+result bytes.
7137 // We could execute the next two instruction and just continue via non-wide path:
7138 // cmpl(limit, 0);
7139 // jcc(Assembler::equal, COMPARE_TAIL); // true
7140 // But since we stopped at the points ary{1,2}+limit which are
7141 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
7142 // (|limit| <= 32 and result < 32),
7143 // we may just compare the last 64 bytes.
7144 //
7145 addptr(result, -64); // it is safe, bc we just came from this area
7146 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
7147 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
7148 kortestql(k7, k7);
7149 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7150
7151 jmp(TRUE_LABEL);
7152
7153 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7154
7155 }//if (VM_Version::supports_avx512vlbw())
7156 #endif //_LP64
7157 bind(COMPARE_WIDE_VECTORS);
7158 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7159 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7160 vpxor(vec1, vec2);
7161
7162 vptest(vec1, vec1);
7163 jcc(Assembler::notZero, FALSE_LABEL);
7164 addptr(limit, 32);
7165 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7166
7167 testl(result, result);
7168 jcc(Assembler::zero, TRUE_LABEL);
7169
7170 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7171 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7172 vpxor(vec1, vec2);
7173
7174 vptest(vec1, vec1);
7175 jccb(Assembler::notZero, FALSE_LABEL);
7176 jmpb(TRUE_LABEL);
7177
7178 bind(COMPARE_TAIL); // limit is zero
7179 movl(limit, result);
7180 // Fallthru to tail compare
7181 } else if (UseSSE42Intrinsics) {
7182 // With SSE4.2, use double quad vector compare
7183 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7184
7185 // Compare 16-byte vectors
7186 andl(result, 0x0000000f); // tail count (in bytes)
7187 andl(limit, 0xfffffff0); // vector count (in bytes)
7188 jcc(Assembler::zero, COMPARE_TAIL);
7189
7190 lea(ary1, Address(ary1, limit, Address::times_1));
7191 lea(ary2, Address(ary2, limit, Address::times_1));
7192 negptr(limit);
7193
7194 bind(COMPARE_WIDE_VECTORS);
7195 movdqu(vec1, Address(ary1, limit, Address::times_1));
7196 movdqu(vec2, Address(ary2, limit, Address::times_1));
7197 pxor(vec1, vec2);
7198
7199 ptest(vec1, vec1);
7200 jcc(Assembler::notZero, FALSE_LABEL);
7201 addptr(limit, 16);
7202 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7203
7204 testl(result, result);
7205 jcc(Assembler::zero, TRUE_LABEL);
7206
7207 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7208 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7209 pxor(vec1, vec2);
7210
7211 ptest(vec1, vec1);
7212 jccb(Assembler::notZero, FALSE_LABEL);
7213 jmpb(TRUE_LABEL);
7214
7215 bind(COMPARE_TAIL); // limit is zero
7216 movl(limit, result);
7217 // Fallthru to tail compare
7218 }
7219
7220 // Compare 4-byte vectors
7221 andl(limit, 0xfffffffc); // vector count (in bytes)
7222 jccb(Assembler::zero, COMPARE_CHAR);
7223
7224 lea(ary1, Address(ary1, limit, Address::times_1));
7225 lea(ary2, Address(ary2, limit, Address::times_1));
7226 negptr(limit);
7227
7228 bind(COMPARE_VECTORS);
7229 movl(chr, Address(ary1, limit, Address::times_1));
7230 cmpl(chr, Address(ary2, limit, Address::times_1));
7231 jccb(Assembler::notEqual, FALSE_LABEL);
7232 addptr(limit, 4);
7233 jcc(Assembler::notZero, COMPARE_VECTORS);
7234
7235 // Compare trailing char (final 2 bytes), if any
7236 bind(COMPARE_CHAR);
7237 testl(result, 0x2); // tail char
7238 jccb(Assembler::zero, COMPARE_BYTE);
7239 load_unsigned_short(chr, Address(ary1, 0));
7240 load_unsigned_short(limit, Address(ary2, 0));
7241 cmpl(chr, limit);
7242 jccb(Assembler::notEqual, FALSE_LABEL);
7243
7244 if (is_array_equ && is_char) {
7245 bind(COMPARE_BYTE);
7246 } else {
7247 lea(ary1, Address(ary1, 2));
7248 lea(ary2, Address(ary2, 2));
7249
7250 bind(COMPARE_BYTE);
7251 testl(result, 0x1); // tail byte
7252 jccb(Assembler::zero, TRUE_LABEL);
7253 load_unsigned_byte(chr, Address(ary1, 0));
7254 load_unsigned_byte(limit, Address(ary2, 0));
7255 cmpl(chr, limit);
7256 jccb(Assembler::notEqual, FALSE_LABEL);
7257 }
7258 bind(TRUE_LABEL);
7259 movl(result, 1); // return true
7260 jmpb(DONE);
7261
7262 bind(FALSE_LABEL);
7263 xorl(result, result); // return false
7264
7265 // That's it
7266 bind(DONE);
7267 if (UseAVX >= 2) {
7268 // clean upper bits of YMM registers
7269 vpxor(vec1, vec1);
7270 vpxor(vec2, vec2);
7271 }
7272 }
7273
7274 #endif
7275
7276 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7277 Register to, Register value, Register count,
7278 Register rtmp, XMMRegister xtmp) {
7279 ShortBranchVerifier sbv(this);
7280 assert_different_registers(to, value, count, rtmp);
7281 Label L_exit;
7282 Label L_fill_2_bytes, L_fill_4_bytes;
7283
7284 int shift = -1;
7285 switch (t) {
7286 case T_BYTE:
7287 shift = 2;
7288 break;
7289 case T_SHORT:
7290 shift = 1;
7291 break;
7292 case T_INT:
7293 shift = 0;
7294 break;
7295 default: ShouldNotReachHere();
7296 }
7297
7298 if (t == T_BYTE) {
7299 andl(value, 0xff);
7300 movl(rtmp, value);
7301 shll(rtmp, 8);
7302 orl(value, rtmp);
7303 }
7304 if (t == T_SHORT) {
7305 andl(value, 0xffff);
7306 }
7307 if (t == T_BYTE || t == T_SHORT) {
7308 movl(rtmp, value);
7309 shll(rtmp, 16);
7310 orl(value, rtmp);
7311 }
7312
7313 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7314 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7315 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7316 Label L_skip_align2;
7317 // align source address at 4 bytes address boundary
7318 if (t == T_BYTE) {
7319 Label L_skip_align1;
7320 // One byte misalignment happens only for byte arrays
7321 testptr(to, 1);
7322 jccb(Assembler::zero, L_skip_align1);
7323 movb(Address(to, 0), value);
7324 increment(to);
7325 decrement(count);
7326 BIND(L_skip_align1);
7327 }
7328 // Two bytes misalignment happens only for byte and short (char) arrays
7329 testptr(to, 2);
7330 jccb(Assembler::zero, L_skip_align2);
7331 movw(Address(to, 0), value);
7332 addptr(to, 2);
7333 subl(count, 1<<(shift-1));
7334 BIND(L_skip_align2);
7335 }
7336 if (UseSSE < 2) {
7337 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7338 // Fill 32-byte chunks
7339 subl(count, 8 << shift);
7340 jcc(Assembler::less, L_check_fill_8_bytes);
7341 align(16);
7342
7343 BIND(L_fill_32_bytes_loop);
7344
7345 for (int i = 0; i < 32; i += 4) {
7346 movl(Address(to, i), value);
7347 }
7348
7349 addptr(to, 32);
7350 subl(count, 8 << shift);
7351 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7352 BIND(L_check_fill_8_bytes);
7353 addl(count, 8 << shift);
7354 jccb(Assembler::zero, L_exit);
7355 jmpb(L_fill_8_bytes);
7356
7357 //
7358 // length is too short, just fill qwords
7359 //
7360 BIND(L_fill_8_bytes_loop);
7361 movl(Address(to, 0), value);
7362 movl(Address(to, 4), value);
7363 addptr(to, 8);
7364 BIND(L_fill_8_bytes);
7365 subl(count, 1 << (shift + 1));
7366 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7367 // fall through to fill 4 bytes
7368 } else {
7369 Label L_fill_32_bytes;
7370 if (!UseUnalignedLoadStores) {
7371 // align to 8 bytes, we know we are 4 byte aligned to start
7372 testptr(to, 4);
7373 jccb(Assembler::zero, L_fill_32_bytes);
7374 movl(Address(to, 0), value);
7375 addptr(to, 4);
7376 subl(count, 1<<shift);
7377 }
7378 BIND(L_fill_32_bytes);
7379 {
7380 assert( UseSSE >= 2, "supported cpu only" );
7381 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7382 movdl(xtmp, value);
7383 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7384 Label L_check_fill_32_bytes;
7385 if (UseAVX > 2) {
7386 // Fill 64-byte chunks
7387 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
7388
7389 // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
7390 cmpl(count, AVX3Threshold);
7391 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
7392
7393 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7394
7395 subl(count, 16 << shift);
7396 jccb(Assembler::less, L_check_fill_32_bytes);
7397 align(16);
7398
7399 BIND(L_fill_64_bytes_loop_avx3);
7400 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7401 addptr(to, 64);
7402 subl(count, 16 << shift);
7403 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
7404 jmpb(L_check_fill_32_bytes);
7405
7406 BIND(L_check_fill_64_bytes_avx2);
7407 }
7408 // Fill 64-byte chunks
7409 Label L_fill_64_bytes_loop;
7410 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7411
7412 subl(count, 16 << shift);
7413 jcc(Assembler::less, L_check_fill_32_bytes);
7414 align(16);
7415
7416 BIND(L_fill_64_bytes_loop);
7417 vmovdqu(Address(to, 0), xtmp);
7418 vmovdqu(Address(to, 32), xtmp);
7419 addptr(to, 64);
7420 subl(count, 16 << shift);
7421 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7422
7423 BIND(L_check_fill_32_bytes);
7424 addl(count, 8 << shift);
7425 jccb(Assembler::less, L_check_fill_8_bytes);
7426 vmovdqu(Address(to, 0), xtmp);
7427 addptr(to, 32);
7428 subl(count, 8 << shift);
7429
7430 BIND(L_check_fill_8_bytes);
7431 // clean upper bits of YMM registers
7432 movdl(xtmp, value);
7433 pshufd(xtmp, xtmp, 0);
7434 } else {
7435 // Fill 32-byte chunks
7436 pshufd(xtmp, xtmp, 0);
7437
7438 subl(count, 8 << shift);
7439 jcc(Assembler::less, L_check_fill_8_bytes);
7440 align(16);
7441
7442 BIND(L_fill_32_bytes_loop);
7443
7444 if (UseUnalignedLoadStores) {
7445 movdqu(Address(to, 0), xtmp);
7446 movdqu(Address(to, 16), xtmp);
7447 } else {
7448 movq(Address(to, 0), xtmp);
7449 movq(Address(to, 8), xtmp);
7450 movq(Address(to, 16), xtmp);
7451 movq(Address(to, 24), xtmp);
7452 }
7453
7454 addptr(to, 32);
7455 subl(count, 8 << shift);
7456 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7457
7458 BIND(L_check_fill_8_bytes);
7459 }
7460 addl(count, 8 << shift);
7461 jccb(Assembler::zero, L_exit);
7462 jmpb(L_fill_8_bytes);
7463
7464 //
7465 // length is too short, just fill qwords
7466 //
7467 BIND(L_fill_8_bytes_loop);
7468 movq(Address(to, 0), xtmp);
7469 addptr(to, 8);
7470 BIND(L_fill_8_bytes);
7471 subl(count, 1 << (shift + 1));
7472 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7473 }
7474 }
7475 // fill trailing 4 bytes
7476 BIND(L_fill_4_bytes);
7477 testl(count, 1<<shift);
7478 jccb(Assembler::zero, L_fill_2_bytes);
7479 movl(Address(to, 0), value);
7480 if (t == T_BYTE || t == T_SHORT) {
7481 Label L_fill_byte;
7482 addptr(to, 4);
7483 BIND(L_fill_2_bytes);
7484 // fill trailing 2 bytes
7485 testl(count, 1<<(shift-1));
7486 jccb(Assembler::zero, L_fill_byte);
7487 movw(Address(to, 0), value);
7488 if (t == T_BYTE) {
7489 addptr(to, 2);
7490 BIND(L_fill_byte);
7491 // fill trailing byte
7492 testl(count, 1);
7493 jccb(Assembler::zero, L_exit);
7494 movb(Address(to, 0), value);
7495 } else {
7496 BIND(L_fill_byte);
7497 }
7498 } else {
7499 BIND(L_fill_2_bytes);
7500 }
7501 BIND(L_exit);
7502 }
7503
7504 // encode char[] to byte[] in ISO_8859_1
7505 //@HotSpotIntrinsicCandidate
7506 //private static int implEncodeISOArray(byte[] sa, int sp,
7507 //byte[] da, int dp, int len) {
7508 // int i = 0;
7509 // for (; i < len; i++) {
7510 // char c = StringUTF16.getChar(sa, sp++);
7511 // if (c > '\u00FF')
7512 // break;
7513 // da[dp++] = (byte)c;
7514 // }
7515 // return i;
7516 //}
7517 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7518 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7519 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7520 Register tmp5, Register result) {
7521
7522 // rsi: src
7523 // rdi: dst
7524 // rdx: len
7525 // rcx: tmp5
7526 // rax: result
7527 ShortBranchVerifier sbv(this);
7528 assert_different_registers(src, dst, len, tmp5, result);
7529 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7530
7531 // set result
7532 xorl(result, result);
7533 // check for zero length
7534 testl(len, len);
7535 jcc(Assembler::zero, L_done);
7536
7537 movl(result, len);
7538
7539 // Setup pointers
7540 lea(src, Address(src, len, Address::times_2)); // char[]
7541 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7542 negptr(len);
7543
7544 if (UseSSE42Intrinsics || UseAVX >= 2) {
7545 Label L_copy_8_chars, L_copy_8_chars_exit;
7546 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7547
7548 if (UseAVX >= 2) {
7549 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7550 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7551 movdl(tmp1Reg, tmp5);
7552 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7553 jmp(L_chars_32_check);
7554
7555 bind(L_copy_32_chars);
7556 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7557 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7558 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7559 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7560 jccb(Assembler::notZero, L_copy_32_chars_exit);
7561 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7562 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7563 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7564
7565 bind(L_chars_32_check);
7566 addptr(len, 32);
7567 jcc(Assembler::lessEqual, L_copy_32_chars);
7568
7569 bind(L_copy_32_chars_exit);
7570 subptr(len, 16);
7571 jccb(Assembler::greater, L_copy_16_chars_exit);
7572
7573 } else if (UseSSE42Intrinsics) {
7574 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7575 movdl(tmp1Reg, tmp5);
7576 pshufd(tmp1Reg, tmp1Reg, 0);
7577 jmpb(L_chars_16_check);
7578 }
7579
7580 bind(L_copy_16_chars);
7581 if (UseAVX >= 2) {
7582 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7583 vptest(tmp2Reg, tmp1Reg);
7584 jcc(Assembler::notZero, L_copy_16_chars_exit);
7585 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7586 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7587 } else {
7588 if (UseAVX > 0) {
7589 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7590 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7591 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7592 } else {
7593 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7594 por(tmp2Reg, tmp3Reg);
7595 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7596 por(tmp2Reg, tmp4Reg);
7597 }
7598 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7599 jccb(Assembler::notZero, L_copy_16_chars_exit);
7600 packuswb(tmp3Reg, tmp4Reg);
7601 }
7602 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7603
7604 bind(L_chars_16_check);
7605 addptr(len, 16);
7606 jcc(Assembler::lessEqual, L_copy_16_chars);
7607
7608 bind(L_copy_16_chars_exit);
7609 if (UseAVX >= 2) {
7610 // clean upper bits of YMM registers
7611 vpxor(tmp2Reg, tmp2Reg);
7612 vpxor(tmp3Reg, tmp3Reg);
7613 vpxor(tmp4Reg, tmp4Reg);
7614 movdl(tmp1Reg, tmp5);
7615 pshufd(tmp1Reg, tmp1Reg, 0);
7616 }
7617 subptr(len, 8);
7618 jccb(Assembler::greater, L_copy_8_chars_exit);
7619
7620 bind(L_copy_8_chars);
7621 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7622 ptest(tmp3Reg, tmp1Reg);
7623 jccb(Assembler::notZero, L_copy_8_chars_exit);
7624 packuswb(tmp3Reg, tmp1Reg);
7625 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7626 addptr(len, 8);
7627 jccb(Assembler::lessEqual, L_copy_8_chars);
7628
7629 bind(L_copy_8_chars_exit);
7630 subptr(len, 8);
7631 jccb(Assembler::zero, L_done);
7632 }
7633
7634 bind(L_copy_1_char);
7635 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7636 testl(tmp5, 0xff00); // check if Unicode char
7637 jccb(Assembler::notZero, L_copy_1_char_exit);
7638 movb(Address(dst, len, Address::times_1, 0), tmp5);
7639 addptr(len, 1);
7640 jccb(Assembler::less, L_copy_1_char);
7641
7642 bind(L_copy_1_char_exit);
7643 addptr(result, len); // len is negative count of not processed elements
7644
7645 bind(L_done);
7646 }
7647
7648 #ifdef _LP64
7649 /**
7650 * Helper for multiply_to_len().
7651 */
7652 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7653 addq(dest_lo, src1);
7654 adcq(dest_hi, 0);
7655 addq(dest_lo, src2);
7656 adcq(dest_hi, 0);
7657 }
7658
7659 /**
7660 * Multiply 64 bit by 64 bit first loop.
7661 */
7662 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7663 Register y, Register y_idx, Register z,
7664 Register carry, Register product,
7665 Register idx, Register kdx) {
7666 //
7667 // jlong carry, x[], y[], z[];
7668 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7669 // huge_128 product = y[idx] * x[xstart] + carry;
7670 // z[kdx] = (jlong)product;
7671 // carry = (jlong)(product >>> 64);
7672 // }
7673 // z[xstart] = carry;
7674 //
7675
7676 Label L_first_loop, L_first_loop_exit;
7677 Label L_one_x, L_one_y, L_multiply;
7678
7679 decrementl(xstart);
7680 jcc(Assembler::negative, L_one_x);
7681
7682 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7683 rorq(x_xstart, 32); // convert big-endian to little-endian
7684
7685 bind(L_first_loop);
7686 decrementl(idx);
7687 jcc(Assembler::negative, L_first_loop_exit);
7688 decrementl(idx);
7689 jcc(Assembler::negative, L_one_y);
7690 movq(y_idx, Address(y, idx, Address::times_4, 0));
7691 rorq(y_idx, 32); // convert big-endian to little-endian
7692 bind(L_multiply);
7693 movq(product, x_xstart);
7694 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7695 addq(product, carry);
7696 adcq(rdx, 0);
7697 subl(kdx, 2);
7698 movl(Address(z, kdx, Address::times_4, 4), product);
7699 shrq(product, 32);
7700 movl(Address(z, kdx, Address::times_4, 0), product);
7701 movq(carry, rdx);
7702 jmp(L_first_loop);
7703
7704 bind(L_one_y);
7705 movl(y_idx, Address(y, 0));
7706 jmp(L_multiply);
7707
7708 bind(L_one_x);
7709 movl(x_xstart, Address(x, 0));
7710 jmp(L_first_loop);
7711
7712 bind(L_first_loop_exit);
7713 }
7714
7715 /**
7716 * Multiply 64 bit by 64 bit and add 128 bit.
7717 */
7718 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7719 Register yz_idx, Register idx,
7720 Register carry, Register product, int offset) {
7721 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7722 // z[kdx] = (jlong)product;
7723
7724 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7725 rorq(yz_idx, 32); // convert big-endian to little-endian
7726 movq(product, x_xstart);
7727 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7728 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7729 rorq(yz_idx, 32); // convert big-endian to little-endian
7730
7731 add2_with_carry(rdx, product, carry, yz_idx);
7732
7733 movl(Address(z, idx, Address::times_4, offset+4), product);
7734 shrq(product, 32);
7735 movl(Address(z, idx, Address::times_4, offset), product);
7736
7737 }
7738
7739 /**
7740 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7741 */
7742 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7743 Register yz_idx, Register idx, Register jdx,
7744 Register carry, Register product,
7745 Register carry2) {
7746 // jlong carry, x[], y[], z[];
7747 // int kdx = ystart+1;
7748 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7749 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7750 // z[kdx+idx+1] = (jlong)product;
7751 // jlong carry2 = (jlong)(product >>> 64);
7752 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7753 // z[kdx+idx] = (jlong)product;
7754 // carry = (jlong)(product >>> 64);
7755 // }
7756 // idx += 2;
7757 // if (idx > 0) {
7758 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7759 // z[kdx+idx] = (jlong)product;
7760 // carry = (jlong)(product >>> 64);
7761 // }
7762 //
7763
7764 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7765
7766 movl(jdx, idx);
7767 andl(jdx, 0xFFFFFFFC);
7768 shrl(jdx, 2);
7769
7770 bind(L_third_loop);
7771 subl(jdx, 1);
7772 jcc(Assembler::negative, L_third_loop_exit);
7773 subl(idx, 4);
7774
7775 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7776 movq(carry2, rdx);
7777
7778 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7779 movq(carry, rdx);
7780 jmp(L_third_loop);
7781
7782 bind (L_third_loop_exit);
7783
7784 andl (idx, 0x3);
7785 jcc(Assembler::zero, L_post_third_loop_done);
7786
7787 Label L_check_1;
7788 subl(idx, 2);
7789 jcc(Assembler::negative, L_check_1);
7790
7791 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7792 movq(carry, rdx);
7793
7794 bind (L_check_1);
7795 addl (idx, 0x2);
7796 andl (idx, 0x1);
7797 subl(idx, 1);
7798 jcc(Assembler::negative, L_post_third_loop_done);
7799
7800 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7801 movq(product, x_xstart);
7802 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7803 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7804
7805 add2_with_carry(rdx, product, yz_idx, carry);
7806
7807 movl(Address(z, idx, Address::times_4, 0), product);
7808 shrq(product, 32);
7809
7810 shlq(rdx, 32);
7811 orq(product, rdx);
7812 movq(carry, product);
7813
7814 bind(L_post_third_loop_done);
7815 }
7816
7817 /**
7818 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7819 *
7820 */
7821 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7822 Register carry, Register carry2,
7823 Register idx, Register jdx,
7824 Register yz_idx1, Register yz_idx2,
7825 Register tmp, Register tmp3, Register tmp4) {
7826 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7827
7828 // jlong carry, x[], y[], z[];
7829 // int kdx = ystart+1;
7830 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7831 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7832 // jlong carry2 = (jlong)(tmp3 >>> 64);
7833 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7834 // carry = (jlong)(tmp4 >>> 64);
7835 // z[kdx+idx+1] = (jlong)tmp3;
7836 // z[kdx+idx] = (jlong)tmp4;
7837 // }
7838 // idx += 2;
7839 // if (idx > 0) {
7840 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7841 // z[kdx+idx] = (jlong)yz_idx1;
7842 // carry = (jlong)(yz_idx1 >>> 64);
7843 // }
7844 //
7845
7846 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7847
7848 movl(jdx, idx);
7849 andl(jdx, 0xFFFFFFFC);
7850 shrl(jdx, 2);
7851
7852 bind(L_third_loop);
7853 subl(jdx, 1);
7854 jcc(Assembler::negative, L_third_loop_exit);
7855 subl(idx, 4);
7856
7857 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7858 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7859 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7860 rorxq(yz_idx2, yz_idx2, 32);
7861
7862 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7863 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7864
7865 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7866 rorxq(yz_idx1, yz_idx1, 32);
7867 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7868 rorxq(yz_idx2, yz_idx2, 32);
7869
7870 if (VM_Version::supports_adx()) {
7871 adcxq(tmp3, carry);
7872 adoxq(tmp3, yz_idx1);
7873
7874 adcxq(tmp4, tmp);
7875 adoxq(tmp4, yz_idx2);
7876
7877 movl(carry, 0); // does not affect flags
7878 adcxq(carry2, carry);
7879 adoxq(carry2, carry);
7880 } else {
7881 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7882 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7883 }
7884 movq(carry, carry2);
7885
7886 movl(Address(z, idx, Address::times_4, 12), tmp3);
7887 shrq(tmp3, 32);
7888 movl(Address(z, idx, Address::times_4, 8), tmp3);
7889
7890 movl(Address(z, idx, Address::times_4, 4), tmp4);
7891 shrq(tmp4, 32);
7892 movl(Address(z, idx, Address::times_4, 0), tmp4);
7893
7894 jmp(L_third_loop);
7895
7896 bind (L_third_loop_exit);
7897
7898 andl (idx, 0x3);
7899 jcc(Assembler::zero, L_post_third_loop_done);
7900
7901 Label L_check_1;
7902 subl(idx, 2);
7903 jcc(Assembler::negative, L_check_1);
7904
7905 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7906 rorxq(yz_idx1, yz_idx1, 32);
7907 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7908 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7909 rorxq(yz_idx2, yz_idx2, 32);
7910
7911 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7912
7913 movl(Address(z, idx, Address::times_4, 4), tmp3);
7914 shrq(tmp3, 32);
7915 movl(Address(z, idx, Address::times_4, 0), tmp3);
7916 movq(carry, tmp4);
7917
7918 bind (L_check_1);
7919 addl (idx, 0x2);
7920 andl (idx, 0x1);
7921 subl(idx, 1);
7922 jcc(Assembler::negative, L_post_third_loop_done);
7923 movl(tmp4, Address(y, idx, Address::times_4, 0));
7924 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7925 movl(tmp4, Address(z, idx, Address::times_4, 0));
7926
7927 add2_with_carry(carry2, tmp3, tmp4, carry);
7928
7929 movl(Address(z, idx, Address::times_4, 0), tmp3);
7930 shrq(tmp3, 32);
7931
7932 shlq(carry2, 32);
7933 orq(tmp3, carry2);
7934 movq(carry, tmp3);
7935
7936 bind(L_post_third_loop_done);
7937 }
7938
7939 /**
7940 * Code for BigInteger::multiplyToLen() instrinsic.
7941 *
7942 * rdi: x
7943 * rax: xlen
7944 * rsi: y
7945 * rcx: ylen
7946 * r8: z
7947 * r11: zlen
7948 * r12: tmp1
7949 * r13: tmp2
7950 * r14: tmp3
7951 * r15: tmp4
7952 * rbx: tmp5
7953 *
7954 */
7955 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7956 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7957 ShortBranchVerifier sbv(this);
7958 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7959
7960 push(tmp1);
7961 push(tmp2);
7962 push(tmp3);
7963 push(tmp4);
7964 push(tmp5);
7965
7966 push(xlen);
7967 push(zlen);
7968
7969 const Register idx = tmp1;
7970 const Register kdx = tmp2;
7971 const Register xstart = tmp3;
7972
7973 const Register y_idx = tmp4;
7974 const Register carry = tmp5;
7975 const Register product = xlen;
7976 const Register x_xstart = zlen; // reuse register
7977
7978 // First Loop.
7979 //
7980 // final static long LONG_MASK = 0xffffffffL;
7981 // int xstart = xlen - 1;
7982 // int ystart = ylen - 1;
7983 // long carry = 0;
7984 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7985 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7986 // z[kdx] = (int)product;
7987 // carry = product >>> 32;
7988 // }
7989 // z[xstart] = (int)carry;
7990 //
7991
7992 movl(idx, ylen); // idx = ylen;
7993 movl(kdx, zlen); // kdx = xlen+ylen;
7994 xorq(carry, carry); // carry = 0;
7995
7996 Label L_done;
7997
7998 movl(xstart, xlen);
7999 decrementl(xstart);
8000 jcc(Assembler::negative, L_done);
8001
8002 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8003
8004 Label L_second_loop;
8005 testl(kdx, kdx);
8006 jcc(Assembler::zero, L_second_loop);
8007
8008 Label L_carry;
8009 subl(kdx, 1);
8010 jcc(Assembler::zero, L_carry);
8011
8012 movl(Address(z, kdx, Address::times_4, 0), carry);
8013 shrq(carry, 32);
8014 subl(kdx, 1);
8015
8016 bind(L_carry);
8017 movl(Address(z, kdx, Address::times_4, 0), carry);
8018
8019 // Second and third (nested) loops.
8020 //
8021 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8022 // carry = 0;
8023 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8024 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8025 // (z[k] & LONG_MASK) + carry;
8026 // z[k] = (int)product;
8027 // carry = product >>> 32;
8028 // }
8029 // z[i] = (int)carry;
8030 // }
8031 //
8032 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8033
8034 const Register jdx = tmp1;
8035
8036 bind(L_second_loop);
8037 xorl(carry, carry); // carry = 0;
8038 movl(jdx, ylen); // j = ystart+1
8039
8040 subl(xstart, 1); // i = xstart-1;
8041 jcc(Assembler::negative, L_done);
8042
8043 push (z);
8044
8045 Label L_last_x;
8046 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8047 subl(xstart, 1); // i = xstart-1;
8048 jcc(Assembler::negative, L_last_x);
8049
8050 if (UseBMI2Instructions) {
8051 movq(rdx, Address(x, xstart, Address::times_4, 0));
8052 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8053 } else {
8054 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8055 rorq(x_xstart, 32); // convert big-endian to little-endian
8056 }
8057
8058 Label L_third_loop_prologue;
8059 bind(L_third_loop_prologue);
8060
8061 push (x);
8062 push (xstart);
8063 push (ylen);
8064
8065
8066 if (UseBMI2Instructions) {
8067 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8068 } else { // !UseBMI2Instructions
8069 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8070 }
8071
8072 pop(ylen);
8073 pop(xlen);
8074 pop(x);
8075 pop(z);
8076
8077 movl(tmp3, xlen);
8078 addl(tmp3, 1);
8079 movl(Address(z, tmp3, Address::times_4, 0), carry);
8080 subl(tmp3, 1);
8081 jccb(Assembler::negative, L_done);
8082
8083 shrq(carry, 32);
8084 movl(Address(z, tmp3, Address::times_4, 0), carry);
8085 jmp(L_second_loop);
8086
8087 // Next infrequent code is moved outside loops.
8088 bind(L_last_x);
8089 if (UseBMI2Instructions) {
8090 movl(rdx, Address(x, 0));
8091 } else {
8092 movl(x_xstart, Address(x, 0));
8093 }
8094 jmp(L_third_loop_prologue);
8095
8096 bind(L_done);
8097
8098 pop(zlen);
8099 pop(xlen);
8100
8101 pop(tmp5);
8102 pop(tmp4);
8103 pop(tmp3);
8104 pop(tmp2);
8105 pop(tmp1);
8106 }
8107
8108 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8109 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8110 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8111 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8112 Label VECTOR8_TAIL, VECTOR4_TAIL;
8113 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8114 Label SAME_TILL_END, DONE;
8115 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8116
8117 //scale is in rcx in both Win64 and Unix
8118 ShortBranchVerifier sbv(this);
8119
8120 shlq(length);
8121 xorq(result, result);
8122
8123 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
8124 VM_Version::supports_avx512vlbw()) {
8125 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8126
8127 cmpq(length, 64);
8128 jcc(Assembler::less, VECTOR32_TAIL);
8129
8130 movq(tmp1, length);
8131 andq(tmp1, 0x3F); // tail count
8132 andq(length, ~(0x3F)); //vector count
8133
8134 bind(VECTOR64_LOOP);
8135 // AVX512 code to compare 64 byte vectors.
8136 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
8137 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
8138 kortestql(k7, k7);
8139 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
8140 addq(result, 64);
8141 subq(length, 64);
8142 jccb(Assembler::notZero, VECTOR64_LOOP);
8143
8144 //bind(VECTOR64_TAIL);
8145 testq(tmp1, tmp1);
8146 jcc(Assembler::zero, SAME_TILL_END);
8147
8148 //bind(VECTOR64_TAIL);
8149 // AVX512 code to compare upto 63 byte vectors.
8150 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
8151 shlxq(tmp2, tmp2, tmp1);
8152 notq(tmp2);
8153 kmovql(k3, tmp2);
8154
8155 evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
8156 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
8157
8158 ktestql(k7, k3);
8159 jcc(Assembler::below, SAME_TILL_END); // not mismatch
8160
8161 bind(VECTOR64_NOT_EQUAL);
8162 kmovql(tmp1, k7);
8163 notq(tmp1);
8164 tzcntq(tmp1, tmp1);
8165 addq(result, tmp1);
8166 shrq(result);
8167 jmp(DONE);
8168 bind(VECTOR32_TAIL);
8169 }
8170
8171 cmpq(length, 8);
8172 jcc(Assembler::equal, VECTOR8_LOOP);
8173 jcc(Assembler::less, VECTOR4_TAIL);
8174
8175 if (UseAVX >= 2) {
8176 Label VECTOR16_TAIL, VECTOR32_LOOP;
8177
8178 cmpq(length, 16);
8179 jcc(Assembler::equal, VECTOR16_LOOP);
8180 jcc(Assembler::less, VECTOR8_LOOP);
8181
8182 cmpq(length, 32);
8183 jccb(Assembler::less, VECTOR16_TAIL);
8184
8185 subq(length, 32);
8186 bind(VECTOR32_LOOP);
8187 vmovdqu(rymm0, Address(obja, result));
8188 vmovdqu(rymm1, Address(objb, result));
8189 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8190 vptest(rymm2, rymm2);
8191 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8192 addq(result, 32);
8193 subq(length, 32);
8194 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8195 addq(length, 32);
8196 jcc(Assembler::equal, SAME_TILL_END);
8197 //falling through if less than 32 bytes left //close the branch here.
8198
8199 bind(VECTOR16_TAIL);
8200 cmpq(length, 16);
8201 jccb(Assembler::less, VECTOR8_TAIL);
8202 bind(VECTOR16_LOOP);
8203 movdqu(rymm0, Address(obja, result));
8204 movdqu(rymm1, Address(objb, result));
8205 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8206 ptest(rymm2, rymm2);
8207 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8208 addq(result, 16);
8209 subq(length, 16);
8210 jcc(Assembler::equal, SAME_TILL_END);
8211 //falling through if less than 16 bytes left
8212 } else {//regular intrinsics
8213
8214 cmpq(length, 16);
8215 jccb(Assembler::less, VECTOR8_TAIL);
8216
8217 subq(length, 16);
8218 bind(VECTOR16_LOOP);
8219 movdqu(rymm0, Address(obja, result));
8220 movdqu(rymm1, Address(objb, result));
8221 pxor(rymm0, rymm1);
8222 ptest(rymm0, rymm0);
8223 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8224 addq(result, 16);
8225 subq(length, 16);
8226 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8227 addq(length, 16);
8228 jcc(Assembler::equal, SAME_TILL_END);
8229 //falling through if less than 16 bytes left
8230 }
8231
8232 bind(VECTOR8_TAIL);
8233 cmpq(length, 8);
8234 jccb(Assembler::less, VECTOR4_TAIL);
8235 bind(VECTOR8_LOOP);
8236 movq(tmp1, Address(obja, result));
8237 movq(tmp2, Address(objb, result));
8238 xorq(tmp1, tmp2);
8239 testq(tmp1, tmp1);
8240 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8241 addq(result, 8);
8242 subq(length, 8);
8243 jcc(Assembler::equal, SAME_TILL_END);
8244 //falling through if less than 8 bytes left
8245
8246 bind(VECTOR4_TAIL);
8247 cmpq(length, 4);
8248 jccb(Assembler::less, BYTES_TAIL);
8249 bind(VECTOR4_LOOP);
8250 movl(tmp1, Address(obja, result));
8251 xorl(tmp1, Address(objb, result));
8252 testl(tmp1, tmp1);
8253 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8254 addq(result, 4);
8255 subq(length, 4);
8256 jcc(Assembler::equal, SAME_TILL_END);
8257 //falling through if less than 4 bytes left
8258
8259 bind(BYTES_TAIL);
8260 bind(BYTES_LOOP);
8261 load_unsigned_byte(tmp1, Address(obja, result));
8262 load_unsigned_byte(tmp2, Address(objb, result));
8263 xorl(tmp1, tmp2);
8264 testl(tmp1, tmp1);
8265 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8266 decq(length);
8267 jcc(Assembler::zero, SAME_TILL_END);
8268 incq(result);
8269 load_unsigned_byte(tmp1, Address(obja, result));
8270 load_unsigned_byte(tmp2, Address(objb, result));
8271 xorl(tmp1, tmp2);
8272 testl(tmp1, tmp1);
8273 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8274 decq(length);
8275 jcc(Assembler::zero, SAME_TILL_END);
8276 incq(result);
8277 load_unsigned_byte(tmp1, Address(obja, result));
8278 load_unsigned_byte(tmp2, Address(objb, result));
8279 xorl(tmp1, tmp2);
8280 testl(tmp1, tmp1);
8281 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8282 jmp(SAME_TILL_END);
8283
8284 if (UseAVX >= 2) {
8285 bind(VECTOR32_NOT_EQUAL);
8286 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8287 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8288 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8289 vpmovmskb(tmp1, rymm0);
8290 bsfq(tmp1, tmp1);
8291 addq(result, tmp1);
8292 shrq(result);
8293 jmp(DONE);
8294 }
8295
8296 bind(VECTOR16_NOT_EQUAL);
8297 if (UseAVX >= 2) {
8298 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8299 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8300 pxor(rymm0, rymm2);
8301 } else {
8302 pcmpeqb(rymm2, rymm2);
8303 pxor(rymm0, rymm1);
8304 pcmpeqb(rymm0, rymm1);
8305 pxor(rymm0, rymm2);
8306 }
8307 pmovmskb(tmp1, rymm0);
8308 bsfq(tmp1, tmp1);
8309 addq(result, tmp1);
8310 shrq(result);
8311 jmpb(DONE);
8312
8313 bind(VECTOR8_NOT_EQUAL);
8314 bind(VECTOR4_NOT_EQUAL);
8315 bsfq(tmp1, tmp1);
8316 shrq(tmp1, 3);
8317 addq(result, tmp1);
8318 bind(BYTES_NOT_EQUAL);
8319 shrq(result);
8320 jmpb(DONE);
8321
8322 bind(SAME_TILL_END);
8323 mov64(result, -1);
8324
8325 bind(DONE);
8326 }
8327
8328 //Helper functions for square_to_len()
8329
8330 /**
8331 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8332 * Preserves x and z and modifies rest of the registers.
8333 */
8334 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8335 // Perform square and right shift by 1
8336 // Handle odd xlen case first, then for even xlen do the following
8337 // jlong carry = 0;
8338 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8339 // huge_128 product = x[j:j+1] * x[j:j+1];
8340 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8341 // z[i+2:i+3] = (jlong)(product >>> 1);
8342 // carry = (jlong)product;
8343 // }
8344
8345 xorq(tmp5, tmp5); // carry
8346 xorq(rdxReg, rdxReg);
8347 xorl(tmp1, tmp1); // index for x
8348 xorl(tmp4, tmp4); // index for z
8349
8350 Label L_first_loop, L_first_loop_exit;
8351
8352 testl(xlen, 1);
8353 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8354
8355 // Square and right shift by 1 the odd element using 32 bit multiply
8356 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8357 imulq(raxReg, raxReg);
8358 shrq(raxReg, 1);
8359 adcq(tmp5, 0);
8360 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8361 incrementl(tmp1);
8362 addl(tmp4, 2);
8363
8364 // Square and right shift by 1 the rest using 64 bit multiply
8365 bind(L_first_loop);
8366 cmpptr(tmp1, xlen);
8367 jccb(Assembler::equal, L_first_loop_exit);
8368
8369 // Square
8370 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8371 rorq(raxReg, 32); // convert big-endian to little-endian
8372 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8373
8374 // Right shift by 1 and save carry
8375 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8376 rcrq(rdxReg, 1);
8377 rcrq(raxReg, 1);
8378 adcq(tmp5, 0);
8379
8380 // Store result in z
8381 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8382 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8383
8384 // Update indices for x and z
8385 addl(tmp1, 2);
8386 addl(tmp4, 4);
8387 jmp(L_first_loop);
8388
8389 bind(L_first_loop_exit);
8390 }
8391
8392
8393 /**
8394 * Perform the following multiply add operation using BMI2 instructions
8395 * carry:sum = sum + op1*op2 + carry
8396 * op2 should be in rdx
8397 * op2 is preserved, all other registers are modified
8398 */
8399 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8400 // assert op2 is rdx
8401 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8402 addq(sum, carry);
8403 adcq(tmp2, 0);
8404 addq(sum, op1);
8405 adcq(tmp2, 0);
8406 movq(carry, tmp2);
8407 }
8408
8409 /**
8410 * Perform the following multiply add operation:
8411 * carry:sum = sum + op1*op2 + carry
8412 * Preserves op1, op2 and modifies rest of registers
8413 */
8414 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8415 // rdx:rax = op1 * op2
8416 movq(raxReg, op2);
8417 mulq(op1);
8418
8419 // rdx:rax = sum + carry + rdx:rax
8420 addq(sum, carry);
8421 adcq(rdxReg, 0);
8422 addq(sum, raxReg);
8423 adcq(rdxReg, 0);
8424
8425 // carry:sum = rdx:sum
8426 movq(carry, rdxReg);
8427 }
8428
8429 /**
8430 * Add 64 bit long carry into z[] with carry propogation.
8431 * Preserves z and carry register values and modifies rest of registers.
8432 *
8433 */
8434 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8435 Label L_fourth_loop, L_fourth_loop_exit;
8436
8437 movl(tmp1, 1);
8438 subl(zlen, 2);
8439 addq(Address(z, zlen, Address::times_4, 0), carry);
8440
8441 bind(L_fourth_loop);
8442 jccb(Assembler::carryClear, L_fourth_loop_exit);
8443 subl(zlen, 2);
8444 jccb(Assembler::negative, L_fourth_loop_exit);
8445 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8446 jmp(L_fourth_loop);
8447 bind(L_fourth_loop_exit);
8448 }
8449
8450 /**
8451 * Shift z[] left by 1 bit.
8452 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8453 *
8454 */
8455 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8456
8457 Label L_fifth_loop, L_fifth_loop_exit;
8458
8459 // Fifth loop
8460 // Perform primitiveLeftShift(z, zlen, 1)
8461
8462 const Register prev_carry = tmp1;
8463 const Register new_carry = tmp4;
8464 const Register value = tmp2;
8465 const Register zidx = tmp3;
8466
8467 // int zidx, carry;
8468 // long value;
8469 // carry = 0;
8470 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8471 // (carry:value) = (z[i] << 1) | carry ;
8472 // z[i] = value;
8473 // }
8474
8475 movl(zidx, zlen);
8476 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8477
8478 bind(L_fifth_loop);
8479 decl(zidx); // Use decl to preserve carry flag
8480 decl(zidx);
8481 jccb(Assembler::negative, L_fifth_loop_exit);
8482
8483 if (UseBMI2Instructions) {
8484 movq(value, Address(z, zidx, Address::times_4, 0));
8485 rclq(value, 1);
8486 rorxq(value, value, 32);
8487 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8488 }
8489 else {
8490 // clear new_carry
8491 xorl(new_carry, new_carry);
8492
8493 // Shift z[i] by 1, or in previous carry and save new carry
8494 movq(value, Address(z, zidx, Address::times_4, 0));
8495 shlq(value, 1);
8496 adcl(new_carry, 0);
8497
8498 orq(value, prev_carry);
8499 rorq(value, 0x20);
8500 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8501
8502 // Set previous carry = new carry
8503 movl(prev_carry, new_carry);
8504 }
8505 jmp(L_fifth_loop);
8506
8507 bind(L_fifth_loop_exit);
8508 }
8509
8510
8511 /**
8512 * Code for BigInteger::squareToLen() intrinsic
8513 *
8514 * rdi: x
8515 * rsi: len
8516 * r8: z
8517 * rcx: zlen
8518 * r12: tmp1
8519 * r13: tmp2
8520 * r14: tmp3
8521 * r15: tmp4
8522 * rbx: tmp5
8523 *
8524 */
8525 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8526
8527 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8528 push(tmp1);
8529 push(tmp2);
8530 push(tmp3);
8531 push(tmp4);
8532 push(tmp5);
8533
8534 // First loop
8535 // Store the squares, right shifted one bit (i.e., divided by 2).
8536 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8537
8538 // Add in off-diagonal sums.
8539 //
8540 // Second, third (nested) and fourth loops.
8541 // zlen +=2;
8542 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8543 // carry = 0;
8544 // long op2 = x[xidx:xidx+1];
8545 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8546 // k -= 2;
8547 // long op1 = x[j:j+1];
8548 // long sum = z[k:k+1];
8549 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8550 // z[k:k+1] = sum;
8551 // }
8552 // add_one_64(z, k, carry, tmp_regs);
8553 // }
8554
8555 const Register carry = tmp5;
8556 const Register sum = tmp3;
8557 const Register op1 = tmp4;
8558 Register op2 = tmp2;
8559
8560 push(zlen);
8561 push(len);
8562 addl(zlen,2);
8563 bind(L_second_loop);
8564 xorq(carry, carry);
8565 subl(zlen, 4);
8566 subl(len, 2);
8567 push(zlen);
8568 push(len);
8569 cmpl(len, 0);
8570 jccb(Assembler::lessEqual, L_second_loop_exit);
8571
8572 // Multiply an array by one 64 bit long.
8573 if (UseBMI2Instructions) {
8574 op2 = rdxReg;
8575 movq(op2, Address(x, len, Address::times_4, 0));
8576 rorxq(op2, op2, 32);
8577 }
8578 else {
8579 movq(op2, Address(x, len, Address::times_4, 0));
8580 rorq(op2, 32);
8581 }
8582
8583 bind(L_third_loop);
8584 decrementl(len);
8585 jccb(Assembler::negative, L_third_loop_exit);
8586 decrementl(len);
8587 jccb(Assembler::negative, L_last_x);
8588
8589 movq(op1, Address(x, len, Address::times_4, 0));
8590 rorq(op1, 32);
8591
8592 bind(L_multiply);
8593 subl(zlen, 2);
8594 movq(sum, Address(z, zlen, Address::times_4, 0));
8595
8596 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8597 if (UseBMI2Instructions) {
8598 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8599 }
8600 else {
8601 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8602 }
8603
8604 movq(Address(z, zlen, Address::times_4, 0), sum);
8605
8606 jmp(L_third_loop);
8607 bind(L_third_loop_exit);
8608
8609 // Fourth loop
8610 // Add 64 bit long carry into z with carry propogation.
8611 // Uses offsetted zlen.
8612 add_one_64(z, zlen, carry, tmp1);
8613
8614 pop(len);
8615 pop(zlen);
8616 jmp(L_second_loop);
8617
8618 // Next infrequent code is moved outside loops.
8619 bind(L_last_x);
8620 movl(op1, Address(x, 0));
8621 jmp(L_multiply);
8622
8623 bind(L_second_loop_exit);
8624 pop(len);
8625 pop(zlen);
8626 pop(len);
8627 pop(zlen);
8628
8629 // Fifth loop
8630 // Shift z left 1 bit.
8631 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8632
8633 // z[zlen-1] |= x[len-1] & 1;
8634 movl(tmp3, Address(x, len, Address::times_4, -4));
8635 andl(tmp3, 1);
8636 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8637
8638 pop(tmp5);
8639 pop(tmp4);
8640 pop(tmp3);
8641 pop(tmp2);
8642 pop(tmp1);
8643 }
8644
8645 /**
8646 * Helper function for mul_add()
8647 * Multiply the in[] by int k and add to out[] starting at offset offs using
8648 * 128 bit by 32 bit multiply and return the carry in tmp5.
8649 * Only quad int aligned length of in[] is operated on in this function.
8650 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8651 * This function preserves out, in and k registers.
8652 * len and offset point to the appropriate index in "in" & "out" correspondingly
8653 * tmp5 has the carry.
8654 * other registers are temporary and are modified.
8655 *
8656 */
8657 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8658 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8659 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8660
8661 Label L_first_loop, L_first_loop_exit;
8662
8663 movl(tmp1, len);
8664 shrl(tmp1, 2);
8665
8666 bind(L_first_loop);
8667 subl(tmp1, 1);
8668 jccb(Assembler::negative, L_first_loop_exit);
8669
8670 subl(len, 4);
8671 subl(offset, 4);
8672
8673 Register op2 = tmp2;
8674 const Register sum = tmp3;
8675 const Register op1 = tmp4;
8676 const Register carry = tmp5;
8677
8678 if (UseBMI2Instructions) {
8679 op2 = rdxReg;
8680 }
8681
8682 movq(op1, Address(in, len, Address::times_4, 8));
8683 rorq(op1, 32);
8684 movq(sum, Address(out, offset, Address::times_4, 8));
8685 rorq(sum, 32);
8686 if (UseBMI2Instructions) {
8687 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8688 }
8689 else {
8690 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8691 }
8692 // Store back in big endian from little endian
8693 rorq(sum, 0x20);
8694 movq(Address(out, offset, Address::times_4, 8), sum);
8695
8696 movq(op1, Address(in, len, Address::times_4, 0));
8697 rorq(op1, 32);
8698 movq(sum, Address(out, offset, Address::times_4, 0));
8699 rorq(sum, 32);
8700 if (UseBMI2Instructions) {
8701 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8702 }
8703 else {
8704 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8705 }
8706 // Store back in big endian from little endian
8707 rorq(sum, 0x20);
8708 movq(Address(out, offset, Address::times_4, 0), sum);
8709
8710 jmp(L_first_loop);
8711 bind(L_first_loop_exit);
8712 }
8713
8714 /**
8715 * Code for BigInteger::mulAdd() intrinsic
8716 *
8717 * rdi: out
8718 * rsi: in
8719 * r11: offs (out.length - offset)
8720 * rcx: len
8721 * r8: k
8722 * r12: tmp1
8723 * r13: tmp2
8724 * r14: tmp3
8725 * r15: tmp4
8726 * rbx: tmp5
8727 * Multiply the in[] by word k and add to out[], return the carry in rax
8728 */
8729 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8730 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8731 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8732
8733 Label L_carry, L_last_in, L_done;
8734
8735 // carry = 0;
8736 // for (int j=len-1; j >= 0; j--) {
8737 // long product = (in[j] & LONG_MASK) * kLong +
8738 // (out[offs] & LONG_MASK) + carry;
8739 // out[offs--] = (int)product;
8740 // carry = product >>> 32;
8741 // }
8742 //
8743 push(tmp1);
8744 push(tmp2);
8745 push(tmp3);
8746 push(tmp4);
8747 push(tmp5);
8748
8749 Register op2 = tmp2;
8750 const Register sum = tmp3;
8751 const Register op1 = tmp4;
8752 const Register carry = tmp5;
8753
8754 if (UseBMI2Instructions) {
8755 op2 = rdxReg;
8756 movl(op2, k);
8757 }
8758 else {
8759 movl(op2, k);
8760 }
8761
8762 xorq(carry, carry);
8763
8764 //First loop
8765
8766 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8767 //The carry is in tmp5
8768 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8769
8770 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8771 decrementl(len);
8772 jccb(Assembler::negative, L_carry);
8773 decrementl(len);
8774 jccb(Assembler::negative, L_last_in);
8775
8776 movq(op1, Address(in, len, Address::times_4, 0));
8777 rorq(op1, 32);
8778
8779 subl(offs, 2);
8780 movq(sum, Address(out, offs, Address::times_4, 0));
8781 rorq(sum, 32);
8782
8783 if (UseBMI2Instructions) {
8784 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8785 }
8786 else {
8787 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8788 }
8789
8790 // Store back in big endian from little endian
8791 rorq(sum, 0x20);
8792 movq(Address(out, offs, Address::times_4, 0), sum);
8793
8794 testl(len, len);
8795 jccb(Assembler::zero, L_carry);
8796
8797 //Multiply the last in[] entry, if any
8798 bind(L_last_in);
8799 movl(op1, Address(in, 0));
8800 movl(sum, Address(out, offs, Address::times_4, -4));
8801
8802 movl(raxReg, k);
8803 mull(op1); //tmp4 * eax -> edx:eax
8804 addl(sum, carry);
8805 adcl(rdxReg, 0);
8806 addl(sum, raxReg);
8807 adcl(rdxReg, 0);
8808 movl(carry, rdxReg);
8809
8810 movl(Address(out, offs, Address::times_4, -4), sum);
8811
8812 bind(L_carry);
8813 //return tmp5/carry as carry in rax
8814 movl(rax, carry);
8815
8816 bind(L_done);
8817 pop(tmp5);
8818 pop(tmp4);
8819 pop(tmp3);
8820 pop(tmp2);
8821 pop(tmp1);
8822 }
8823 #endif
8824
8825 /**
8826 * Emits code to update CRC-32 with a byte value according to constants in table
8827 *
8828 * @param [in,out]crc Register containing the crc.
8829 * @param [in]val Register containing the byte to fold into the CRC.
8830 * @param [in]table Register containing the table of crc constants.
8831 *
8832 * uint32_t crc;
8833 * val = crc_table[(val ^ crc) & 0xFF];
8834 * crc = val ^ (crc >> 8);
8835 *
8836 */
8837 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8838 xorl(val, crc);
8839 andl(val, 0xFF);
8840 shrl(crc, 8); // unsigned shift
8841 xorl(crc, Address(table, val, Address::times_4, 0));
8842 }
8843
8844 /**
8845 * Fold four 128-bit data chunks
8846 */
8847 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8848 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8849 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8850 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8851 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8852 }
8853
8854 /**
8855 * Fold 128-bit data chunk
8856 */
8857 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8858 if (UseAVX > 0) {
8859 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8860 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8861 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8862 pxor(xcrc, xtmp);
8863 } else {
8864 movdqa(xtmp, xcrc);
8865 pclmulhdq(xtmp, xK); // [123:64]
8866 pclmulldq(xcrc, xK); // [63:0]
8867 pxor(xcrc, xtmp);
8868 movdqu(xtmp, Address(buf, offset));
8869 pxor(xcrc, xtmp);
8870 }
8871 }
8872
8873 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8874 if (UseAVX > 0) {
8875 vpclmulhdq(xtmp, xK, xcrc);
8876 vpclmulldq(xcrc, xK, xcrc);
8877 pxor(xcrc, xbuf);
8878 pxor(xcrc, xtmp);
8879 } else {
8880 movdqa(xtmp, xcrc);
8881 pclmulhdq(xtmp, xK);
8882 pclmulldq(xcrc, xK);
8883 pxor(xcrc, xbuf);
8884 pxor(xcrc, xtmp);
8885 }
8886 }
8887
8888 /**
8889 * 8-bit folds to compute 32-bit CRC
8890 *
8891 * uint64_t xcrc;
8892 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8893 */
8894 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8895 movdl(tmp, xcrc);
8896 andl(tmp, 0xFF);
8897 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8898 psrldq(xcrc, 1); // unsigned shift one byte
8899 pxor(xcrc, xtmp);
8900 }
8901
8902 /**
8903 * uint32_t crc;
8904 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8905 */
8906 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8907 movl(tmp, crc);
8908 andl(tmp, 0xFF);
8909 shrl(crc, 8);
8910 xorl(crc, Address(table, tmp, Address::times_4, 0));
8911 }
8912
8913 /**
8914 * @param crc register containing existing CRC (32-bit)
8915 * @param buf register pointing to input byte buffer (byte*)
8916 * @param len register containing number of bytes
8917 * @param table register that will contain address of CRC table
8918 * @param tmp scratch register
8919 */
8920 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8921 assert_different_registers(crc, buf, len, table, tmp, rax);
8922
8923 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8924 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8925
8926 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8927 // context for the registers used, where all instructions below are using 128-bit mode
8928 // On EVEX without VL and BW, these instructions will all be AVX.
8929 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8930 notl(crc); // ~crc
8931 cmpl(len, 16);
8932 jcc(Assembler::less, L_tail);
8933
8934 // Align buffer to 16 bytes
8935 movl(tmp, buf);
8936 andl(tmp, 0xF);
8937 jccb(Assembler::zero, L_aligned);
8938 subl(tmp, 16);
8939 addl(len, tmp);
8940
8941 align(4);
8942 BIND(L_align_loop);
8943 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8944 update_byte_crc32(crc, rax, table);
8945 increment(buf);
8946 incrementl(tmp);
8947 jccb(Assembler::less, L_align_loop);
8948
8949 BIND(L_aligned);
8950 movl(tmp, len); // save
8951 shrl(len, 4);
8952 jcc(Assembler::zero, L_tail_restore);
8953
8954 // Fold crc into first bytes of vector
8955 movdqa(xmm1, Address(buf, 0));
8956 movdl(rax, xmm1);
8957 xorl(crc, rax);
8958 if (VM_Version::supports_sse4_1()) {
8959 pinsrd(xmm1, crc, 0);
8960 } else {
8961 pinsrw(xmm1, crc, 0);
8962 shrl(crc, 16);
8963 pinsrw(xmm1, crc, 1);
8964 }
8965 addptr(buf, 16);
8966 subl(len, 4); // len > 0
8967 jcc(Assembler::less, L_fold_tail);
8968
8969 movdqa(xmm2, Address(buf, 0));
8970 movdqa(xmm3, Address(buf, 16));
8971 movdqa(xmm4, Address(buf, 32));
8972 addptr(buf, 48);
8973 subl(len, 3);
8974 jcc(Assembler::lessEqual, L_fold_512b);
8975
8976 // Fold total 512 bits of polynomial on each iteration,
8977 // 128 bits per each of 4 parallel streams.
8978 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8979
8980 align(32);
8981 BIND(L_fold_512b_loop);
8982 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8983 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8984 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8985 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8986 addptr(buf, 64);
8987 subl(len, 4);
8988 jcc(Assembler::greater, L_fold_512b_loop);
8989
8990 // Fold 512 bits to 128 bits.
8991 BIND(L_fold_512b);
8992 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8993 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8994 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8995 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8996
8997 // Fold the rest of 128 bits data chunks
8998 BIND(L_fold_tail);
8999 addl(len, 3);
9000 jccb(Assembler::lessEqual, L_fold_128b);
9001 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9002
9003 BIND(L_fold_tail_loop);
9004 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9005 addptr(buf, 16);
9006 decrementl(len);
9007 jccb(Assembler::greater, L_fold_tail_loop);
9008
9009 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9010 BIND(L_fold_128b);
9011 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9012 if (UseAVX > 0) {
9013 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9014 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9015 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9016 } else {
9017 movdqa(xmm2, xmm0);
9018 pclmulqdq(xmm2, xmm1, 0x1);
9019 movdqa(xmm3, xmm0);
9020 pand(xmm3, xmm2);
9021 pclmulqdq(xmm0, xmm3, 0x1);
9022 }
9023 psrldq(xmm1, 8);
9024 psrldq(xmm2, 4);
9025 pxor(xmm0, xmm1);
9026 pxor(xmm0, xmm2);
9027
9028 // 8 8-bit folds to compute 32-bit CRC.
9029 for (int j = 0; j < 4; j++) {
9030 fold_8bit_crc32(xmm0, table, xmm1, rax);
9031 }
9032 movdl(crc, xmm0); // mov 32 bits to general register
9033 for (int j = 0; j < 4; j++) {
9034 fold_8bit_crc32(crc, table, rax);
9035 }
9036
9037 BIND(L_tail_restore);
9038 movl(len, tmp); // restore
9039 BIND(L_tail);
9040 andl(len, 0xf);
9041 jccb(Assembler::zero, L_exit);
9042
9043 // Fold the rest of bytes
9044 align(4);
9045 BIND(L_tail_loop);
9046 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9047 update_byte_crc32(crc, rax, table);
9048 increment(buf);
9049 decrementl(len);
9050 jccb(Assembler::greater, L_tail_loop);
9051
9052 BIND(L_exit);
9053 notl(crc); // ~c
9054 }
9055
9056 #ifdef _LP64
9057 // S. Gueron / Information Processing Letters 112 (2012) 184
9058 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9059 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9060 // Output: the 64-bit carry-less product of B * CONST
9061 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9062 Register tmp1, Register tmp2, Register tmp3) {
9063 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9064 if (n > 0) {
9065 addq(tmp3, n * 256 * 8);
9066 }
9067 // Q1 = TABLEExt[n][B & 0xFF];
9068 movl(tmp1, in);
9069 andl(tmp1, 0x000000FF);
9070 shll(tmp1, 3);
9071 addq(tmp1, tmp3);
9072 movq(tmp1, Address(tmp1, 0));
9073
9074 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9075 movl(tmp2, in);
9076 shrl(tmp2, 8);
9077 andl(tmp2, 0x000000FF);
9078 shll(tmp2, 3);
9079 addq(tmp2, tmp3);
9080 movq(tmp2, Address(tmp2, 0));
9081
9082 shlq(tmp2, 8);
9083 xorq(tmp1, tmp2);
9084
9085 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9086 movl(tmp2, in);
9087 shrl(tmp2, 16);
9088 andl(tmp2, 0x000000FF);
9089 shll(tmp2, 3);
9090 addq(tmp2, tmp3);
9091 movq(tmp2, Address(tmp2, 0));
9092
9093 shlq(tmp2, 16);
9094 xorq(tmp1, tmp2);
9095
9096 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9097 shrl(in, 24);
9098 andl(in, 0x000000FF);
9099 shll(in, 3);
9100 addq(in, tmp3);
9101 movq(in, Address(in, 0));
9102
9103 shlq(in, 24);
9104 xorq(in, tmp1);
9105 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9106 }
9107
9108 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9109 Register in_out,
9110 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9111 XMMRegister w_xtmp2,
9112 Register tmp1,
9113 Register n_tmp2, Register n_tmp3) {
9114 if (is_pclmulqdq_supported) {
9115 movdl(w_xtmp1, in_out); // modified blindly
9116
9117 movl(tmp1, const_or_pre_comp_const_index);
9118 movdl(w_xtmp2, tmp1);
9119 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9120
9121 movdq(in_out, w_xtmp1);
9122 } else {
9123 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9124 }
9125 }
9126
9127 // Recombination Alternative 2: No bit-reflections
9128 // T1 = (CRC_A * U1) << 1
9129 // T2 = (CRC_B * U2) << 1
9130 // C1 = T1 >> 32
9131 // C2 = T2 >> 32
9132 // T1 = T1 & 0xFFFFFFFF
9133 // T2 = T2 & 0xFFFFFFFF
9134 // T1 = CRC32(0, T1)
9135 // T2 = CRC32(0, T2)
9136 // C1 = C1 ^ T1
9137 // C2 = C2 ^ T2
9138 // CRC = C1 ^ C2 ^ CRC_C
9139 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9140 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9141 Register tmp1, Register tmp2,
9142 Register n_tmp3) {
9143 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9144 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9145 shlq(in_out, 1);
9146 movl(tmp1, in_out);
9147 shrq(in_out, 32);
9148 xorl(tmp2, tmp2);
9149 crc32(tmp2, tmp1, 4);
9150 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9151 shlq(in1, 1);
9152 movl(tmp1, in1);
9153 shrq(in1, 32);
9154 xorl(tmp2, tmp2);
9155 crc32(tmp2, tmp1, 4);
9156 xorl(in1, tmp2);
9157 xorl(in_out, in1);
9158 xorl(in_out, in2);
9159 }
9160
9161 // Set N to predefined value
9162 // Subtract from a lenght of a buffer
9163 // execute in a loop:
9164 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9165 // for i = 1 to N do
9166 // CRC_A = CRC32(CRC_A, A[i])
9167 // CRC_B = CRC32(CRC_B, B[i])
9168 // CRC_C = CRC32(CRC_C, C[i])
9169 // end for
9170 // Recombine
9171 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9172 Register in_out1, Register in_out2, Register in_out3,
9173 Register tmp1, Register tmp2, Register tmp3,
9174 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9175 Register tmp4, Register tmp5,
9176 Register n_tmp6) {
9177 Label L_processPartitions;
9178 Label L_processPartition;
9179 Label L_exit;
9180
9181 bind(L_processPartitions);
9182 cmpl(in_out1, 3 * size);
9183 jcc(Assembler::less, L_exit);
9184 xorl(tmp1, tmp1);
9185 xorl(tmp2, tmp2);
9186 movq(tmp3, in_out2);
9187 addq(tmp3, size);
9188
9189 bind(L_processPartition);
9190 crc32(in_out3, Address(in_out2, 0), 8);
9191 crc32(tmp1, Address(in_out2, size), 8);
9192 crc32(tmp2, Address(in_out2, size * 2), 8);
9193 addq(in_out2, 8);
9194 cmpq(in_out2, tmp3);
9195 jcc(Assembler::less, L_processPartition);
9196 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9197 w_xtmp1, w_xtmp2, w_xtmp3,
9198 tmp4, tmp5,
9199 n_tmp6);
9200 addq(in_out2, 2 * size);
9201 subl(in_out1, 3 * size);
9202 jmp(L_processPartitions);
9203
9204 bind(L_exit);
9205 }
9206 #else
9207 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9208 Register tmp1, Register tmp2, Register tmp3,
9209 XMMRegister xtmp1, XMMRegister xtmp2) {
9210 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9211 if (n > 0) {
9212 addl(tmp3, n * 256 * 8);
9213 }
9214 // Q1 = TABLEExt[n][B & 0xFF];
9215 movl(tmp1, in_out);
9216 andl(tmp1, 0x000000FF);
9217 shll(tmp1, 3);
9218 addl(tmp1, tmp3);
9219 movq(xtmp1, Address(tmp1, 0));
9220
9221 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9222 movl(tmp2, in_out);
9223 shrl(tmp2, 8);
9224 andl(tmp2, 0x000000FF);
9225 shll(tmp2, 3);
9226 addl(tmp2, tmp3);
9227 movq(xtmp2, Address(tmp2, 0));
9228
9229 psllq(xtmp2, 8);
9230 pxor(xtmp1, xtmp2);
9231
9232 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9233 movl(tmp2, in_out);
9234 shrl(tmp2, 16);
9235 andl(tmp2, 0x000000FF);
9236 shll(tmp2, 3);
9237 addl(tmp2, tmp3);
9238 movq(xtmp2, Address(tmp2, 0));
9239
9240 psllq(xtmp2, 16);
9241 pxor(xtmp1, xtmp2);
9242
9243 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9244 shrl(in_out, 24);
9245 andl(in_out, 0x000000FF);
9246 shll(in_out, 3);
9247 addl(in_out, tmp3);
9248 movq(xtmp2, Address(in_out, 0));
9249
9250 psllq(xtmp2, 24);
9251 pxor(xtmp1, xtmp2); // Result in CXMM
9252 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9253 }
9254
9255 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9256 Register in_out,
9257 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9258 XMMRegister w_xtmp2,
9259 Register tmp1,
9260 Register n_tmp2, Register n_tmp3) {
9261 if (is_pclmulqdq_supported) {
9262 movdl(w_xtmp1, in_out);
9263
9264 movl(tmp1, const_or_pre_comp_const_index);
9265 movdl(w_xtmp2, tmp1);
9266 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9267 // Keep result in XMM since GPR is 32 bit in length
9268 } else {
9269 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9270 }
9271 }
9272
9273 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9274 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9275 Register tmp1, Register tmp2,
9276 Register n_tmp3) {
9277 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9278 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9279
9280 psllq(w_xtmp1, 1);
9281 movdl(tmp1, w_xtmp1);
9282 psrlq(w_xtmp1, 32);
9283 movdl(in_out, w_xtmp1);
9284
9285 xorl(tmp2, tmp2);
9286 crc32(tmp2, tmp1, 4);
9287 xorl(in_out, tmp2);
9288
9289 psllq(w_xtmp2, 1);
9290 movdl(tmp1, w_xtmp2);
9291 psrlq(w_xtmp2, 32);
9292 movdl(in1, w_xtmp2);
9293
9294 xorl(tmp2, tmp2);
9295 crc32(tmp2, tmp1, 4);
9296 xorl(in1, tmp2);
9297 xorl(in_out, in1);
9298 xorl(in_out, in2);
9299 }
9300
9301 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9302 Register in_out1, Register in_out2, Register in_out3,
9303 Register tmp1, Register tmp2, Register tmp3,
9304 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9305 Register tmp4, Register tmp5,
9306 Register n_tmp6) {
9307 Label L_processPartitions;
9308 Label L_processPartition;
9309 Label L_exit;
9310
9311 bind(L_processPartitions);
9312 cmpl(in_out1, 3 * size);
9313 jcc(Assembler::less, L_exit);
9314 xorl(tmp1, tmp1);
9315 xorl(tmp2, tmp2);
9316 movl(tmp3, in_out2);
9317 addl(tmp3, size);
9318
9319 bind(L_processPartition);
9320 crc32(in_out3, Address(in_out2, 0), 4);
9321 crc32(tmp1, Address(in_out2, size), 4);
9322 crc32(tmp2, Address(in_out2, size*2), 4);
9323 crc32(in_out3, Address(in_out2, 0+4), 4);
9324 crc32(tmp1, Address(in_out2, size+4), 4);
9325 crc32(tmp2, Address(in_out2, size*2+4), 4);
9326 addl(in_out2, 8);
9327 cmpl(in_out2, tmp3);
9328 jcc(Assembler::less, L_processPartition);
9329
9330 push(tmp3);
9331 push(in_out1);
9332 push(in_out2);
9333 tmp4 = tmp3;
9334 tmp5 = in_out1;
9335 n_tmp6 = in_out2;
9336
9337 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9338 w_xtmp1, w_xtmp2, w_xtmp3,
9339 tmp4, tmp5,
9340 n_tmp6);
9341
9342 pop(in_out2);
9343 pop(in_out1);
9344 pop(tmp3);
9345
9346 addl(in_out2, 2 * size);
9347 subl(in_out1, 3 * size);
9348 jmp(L_processPartitions);
9349
9350 bind(L_exit);
9351 }
9352 #endif //LP64
9353
9354 #ifdef _LP64
9355 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9356 // Input: A buffer I of L bytes.
9357 // Output: the CRC32C value of the buffer.
9358 // Notations:
9359 // Write L = 24N + r, with N = floor (L/24).
9360 // r = L mod 24 (0 <= r < 24).
9361 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9362 // N quadwords, and R consists of r bytes.
9363 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9364 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9365 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9366 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9367 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9368 Register tmp1, Register tmp2, Register tmp3,
9369 Register tmp4, Register tmp5, Register tmp6,
9370 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9371 bool is_pclmulqdq_supported) {
9372 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9373 Label L_wordByWord;
9374 Label L_byteByByteProlog;
9375 Label L_byteByByte;
9376 Label L_exit;
9377
9378 if (is_pclmulqdq_supported ) {
9379 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9380 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9381
9382 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9383 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9384
9385 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9386 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9387 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9388 } else {
9389 const_or_pre_comp_const_index[0] = 1;
9390 const_or_pre_comp_const_index[1] = 0;
9391
9392 const_or_pre_comp_const_index[2] = 3;
9393 const_or_pre_comp_const_index[3] = 2;
9394
9395 const_or_pre_comp_const_index[4] = 5;
9396 const_or_pre_comp_const_index[5] = 4;
9397 }
9398 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9399 in2, in1, in_out,
9400 tmp1, tmp2, tmp3,
9401 w_xtmp1, w_xtmp2, w_xtmp3,
9402 tmp4, tmp5,
9403 tmp6);
9404 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9405 in2, in1, in_out,
9406 tmp1, tmp2, tmp3,
9407 w_xtmp1, w_xtmp2, w_xtmp3,
9408 tmp4, tmp5,
9409 tmp6);
9410 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9411 in2, in1, in_out,
9412 tmp1, tmp2, tmp3,
9413 w_xtmp1, w_xtmp2, w_xtmp3,
9414 tmp4, tmp5,
9415 tmp6);
9416 movl(tmp1, in2);
9417 andl(tmp1, 0x00000007);
9418 negl(tmp1);
9419 addl(tmp1, in2);
9420 addq(tmp1, in1);
9421
9422 BIND(L_wordByWord);
9423 cmpq(in1, tmp1);
9424 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9425 crc32(in_out, Address(in1, 0), 4);
9426 addq(in1, 4);
9427 jmp(L_wordByWord);
9428
9429 BIND(L_byteByByteProlog);
9430 andl(in2, 0x00000007);
9431 movl(tmp2, 1);
9432
9433 BIND(L_byteByByte);
9434 cmpl(tmp2, in2);
9435 jccb(Assembler::greater, L_exit);
9436 crc32(in_out, Address(in1, 0), 1);
9437 incq(in1);
9438 incl(tmp2);
9439 jmp(L_byteByByte);
9440
9441 BIND(L_exit);
9442 }
9443 #else
9444 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9445 Register tmp1, Register tmp2, Register tmp3,
9446 Register tmp4, Register tmp5, Register tmp6,
9447 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9448 bool is_pclmulqdq_supported) {
9449 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9450 Label L_wordByWord;
9451 Label L_byteByByteProlog;
9452 Label L_byteByByte;
9453 Label L_exit;
9454
9455 if (is_pclmulqdq_supported) {
9456 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9457 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9458
9459 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9460 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9461
9462 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9463 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9464 } else {
9465 const_or_pre_comp_const_index[0] = 1;
9466 const_or_pre_comp_const_index[1] = 0;
9467
9468 const_or_pre_comp_const_index[2] = 3;
9469 const_or_pre_comp_const_index[3] = 2;
9470
9471 const_or_pre_comp_const_index[4] = 5;
9472 const_or_pre_comp_const_index[5] = 4;
9473 }
9474 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9475 in2, in1, in_out,
9476 tmp1, tmp2, tmp3,
9477 w_xtmp1, w_xtmp2, w_xtmp3,
9478 tmp4, tmp5,
9479 tmp6);
9480 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9481 in2, in1, in_out,
9482 tmp1, tmp2, tmp3,
9483 w_xtmp1, w_xtmp2, w_xtmp3,
9484 tmp4, tmp5,
9485 tmp6);
9486 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9487 in2, in1, in_out,
9488 tmp1, tmp2, tmp3,
9489 w_xtmp1, w_xtmp2, w_xtmp3,
9490 tmp4, tmp5,
9491 tmp6);
9492 movl(tmp1, in2);
9493 andl(tmp1, 0x00000007);
9494 negl(tmp1);
9495 addl(tmp1, in2);
9496 addl(tmp1, in1);
9497
9498 BIND(L_wordByWord);
9499 cmpl(in1, tmp1);
9500 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9501 crc32(in_out, Address(in1,0), 4);
9502 addl(in1, 4);
9503 jmp(L_wordByWord);
9504
9505 BIND(L_byteByByteProlog);
9506 andl(in2, 0x00000007);
9507 movl(tmp2, 1);
9508
9509 BIND(L_byteByByte);
9510 cmpl(tmp2, in2);
9511 jccb(Assembler::greater, L_exit);
9512 movb(tmp1, Address(in1, 0));
9513 crc32(in_out, tmp1, 1);
9514 incl(in1);
9515 incl(tmp2);
9516 jmp(L_byteByByte);
9517
9518 BIND(L_exit);
9519 }
9520 #endif // LP64
9521 #undef BIND
9522 #undef BLOCK_COMMENT
9523
9524 // Compress char[] array to byte[].
9525 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9526 // @HotSpotIntrinsicCandidate
9527 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9528 // for (int i = 0; i < len; i++) {
9529 // int c = src[srcOff++];
9530 // if (c >>> 8 != 0) {
9531 // return 0;
9532 // }
9533 // dst[dstOff++] = (byte)c;
9534 // }
9535 // return len;
9536 // }
9537 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9538 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9539 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9540 Register tmp5, Register result) {
9541 Label copy_chars_loop, return_length, return_zero, done;
9542
9543 // rsi: src
9544 // rdi: dst
9545 // rdx: len
9546 // rcx: tmp5
9547 // rax: result
9548
9549 // rsi holds start addr of source char[] to be compressed
9550 // rdi holds start addr of destination byte[]
9551 // rdx holds length
9552
9553 assert(len != result, "");
9554
9555 // save length for return
9556 push(len);
9557
9558 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9559 VM_Version::supports_avx512vlbw() &&
9560 VM_Version::supports_bmi2()) {
9561
9562 Label copy_32_loop, copy_loop_tail, below_threshold;
9563
9564 // alignment
9565 Label post_alignment;
9566
9567 // if length of the string is less than 16, handle it in an old fashioned way
9568 testl(len, -32);
9569 jcc(Assembler::zero, below_threshold);
9570
9571 // First check whether a character is compressable ( <= 0xFF).
9572 // Create mask to test for Unicode chars inside zmm vector
9573 movl(result, 0x00FF);
9574 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9575
9576 testl(len, -64);
9577 jcc(Assembler::zero, post_alignment);
9578
9579 movl(tmp5, dst);
9580 andl(tmp5, (32 - 1));
9581 negl(tmp5);
9582 andl(tmp5, (32 - 1));
9583
9584 // bail out when there is nothing to be done
9585 testl(tmp5, 0xFFFFFFFF);
9586 jcc(Assembler::zero, post_alignment);
9587
9588 // ~(~0 << len), where len is the # of remaining elements to process
9589 movl(result, 0xFFFFFFFF);
9590 shlxl(result, result, tmp5);
9591 notl(result);
9592 kmovdl(k3, result);
9593
9594 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9595 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9596 ktestd(k2, k3);
9597 jcc(Assembler::carryClear, return_zero);
9598
9599 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9600
9601 addptr(src, tmp5);
9602 addptr(src, tmp5);
9603 addptr(dst, tmp5);
9604 subl(len, tmp5);
9605
9606 bind(post_alignment);
9607 // end of alignment
9608
9609 movl(tmp5, len);
9610 andl(tmp5, (32 - 1)); // tail count (in chars)
9611 andl(len, ~(32 - 1)); // vector count (in chars)
9612 jcc(Assembler::zero, copy_loop_tail);
9613
9614 lea(src, Address(src, len, Address::times_2));
9615 lea(dst, Address(dst, len, Address::times_1));
9616 negptr(len);
9617
9618 bind(copy_32_loop);
9619 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9620 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9621 kortestdl(k2, k2);
9622 jcc(Assembler::carryClear, return_zero);
9623
9624 // All elements in current processed chunk are valid candidates for
9625 // compression. Write a truncated byte elements to the memory.
9626 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9627 addptr(len, 32);
9628 jcc(Assembler::notZero, copy_32_loop);
9629
9630 bind(copy_loop_tail);
9631 // bail out when there is nothing to be done
9632 testl(tmp5, 0xFFFFFFFF);
9633 jcc(Assembler::zero, return_length);
9634
9635 movl(len, tmp5);
9636
9637 // ~(~0 << len), where len is the # of remaining elements to process
9638 movl(result, 0xFFFFFFFF);
9639 shlxl(result, result, len);
9640 notl(result);
9641
9642 kmovdl(k3, result);
9643
9644 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9645 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9646 ktestd(k2, k3);
9647 jcc(Assembler::carryClear, return_zero);
9648
9649 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9650 jmp(return_length);
9651
9652 bind(below_threshold);
9653 }
9654
9655 if (UseSSE42Intrinsics) {
9656 Label copy_32_loop, copy_16, copy_tail;
9657
9658 movl(result, len);
9659
9660 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9661
9662 // vectored compression
9663 andl(len, 0xfffffff0); // vector count (in chars)
9664 andl(result, 0x0000000f); // tail count (in chars)
9665 testl(len, len);
9666 jcc(Assembler::zero, copy_16);
9667
9668 // compress 16 chars per iter
9669 movdl(tmp1Reg, tmp5);
9670 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9671 pxor(tmp4Reg, tmp4Reg);
9672
9673 lea(src, Address(src, len, Address::times_2));
9674 lea(dst, Address(dst, len, Address::times_1));
9675 negptr(len);
9676
9677 bind(copy_32_loop);
9678 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9679 por(tmp4Reg, tmp2Reg);
9680 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9681 por(tmp4Reg, tmp3Reg);
9682 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9683 jcc(Assembler::notZero, return_zero);
9684 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9685 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9686 addptr(len, 16);
9687 jcc(Assembler::notZero, copy_32_loop);
9688
9689 // compress next vector of 8 chars (if any)
9690 bind(copy_16);
9691 movl(len, result);
9692 andl(len, 0xfffffff8); // vector count (in chars)
9693 andl(result, 0x00000007); // tail count (in chars)
9694 testl(len, len);
9695 jccb(Assembler::zero, copy_tail);
9696
9697 movdl(tmp1Reg, tmp5);
9698 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9699 pxor(tmp3Reg, tmp3Reg);
9700
9701 movdqu(tmp2Reg, Address(src, 0));
9702 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9703 jccb(Assembler::notZero, return_zero);
9704 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9705 movq(Address(dst, 0), tmp2Reg);
9706 addptr(src, 16);
9707 addptr(dst, 8);
9708
9709 bind(copy_tail);
9710 movl(len, result);
9711 }
9712 // compress 1 char per iter
9713 testl(len, len);
9714 jccb(Assembler::zero, return_length);
9715 lea(src, Address(src, len, Address::times_2));
9716 lea(dst, Address(dst, len, Address::times_1));
9717 negptr(len);
9718
9719 bind(copy_chars_loop);
9720 load_unsigned_short(result, Address(src, len, Address::times_2));
9721 testl(result, 0xff00); // check if Unicode char
9722 jccb(Assembler::notZero, return_zero);
9723 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
9724 increment(len);
9725 jcc(Assembler::notZero, copy_chars_loop);
9726
9727 // if compression succeeded, return length
9728 bind(return_length);
9729 pop(result);
9730 jmpb(done);
9731
9732 // if compression failed, return 0
9733 bind(return_zero);
9734 xorl(result, result);
9735 addptr(rsp, wordSize);
9736
9737 bind(done);
9738 }
9739
9740 // Inflate byte[] array to char[].
9741 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9742 // @HotSpotIntrinsicCandidate
9743 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9744 // for (int i = 0; i < len; i++) {
9745 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9746 // }
9747 // }
9748 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9749 XMMRegister tmp1, Register tmp2) {
9750 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9751 // rsi: src
9752 // rdi: dst
9753 // rdx: len
9754 // rcx: tmp2
9755
9756 // rsi holds start addr of source byte[] to be inflated
9757 // rdi holds start addr of destination char[]
9758 // rdx holds length
9759 assert_different_registers(src, dst, len, tmp2);
9760 movl(tmp2, len);
9761 if ((UseAVX > 2) && // AVX512
9762 VM_Version::supports_avx512vlbw() &&
9763 VM_Version::supports_bmi2()) {
9764
9765 Label copy_32_loop, copy_tail;
9766 Register tmp3_aliased = len;
9767
9768 // if length of the string is less than 16, handle it in an old fashioned way
9769 testl(len, -16);
9770 jcc(Assembler::zero, below_threshold);
9771
9772 testl(len, -1 * AVX3Threshold);
9773 jcc(Assembler::zero, avx3_threshold);
9774
9775 // In order to use only one arithmetic operation for the main loop we use
9776 // this pre-calculation
9777 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9778 andl(len, -32); // vector count
9779 jccb(Assembler::zero, copy_tail);
9780
9781 lea(src, Address(src, len, Address::times_1));
9782 lea(dst, Address(dst, len, Address::times_2));
9783 negptr(len);
9784
9785
9786 // inflate 32 chars per iter
9787 bind(copy_32_loop);
9788 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9789 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9790 addptr(len, 32);
9791 jcc(Assembler::notZero, copy_32_loop);
9792
9793 bind(copy_tail);
9794 // bail out when there is nothing to be done
9795 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9796 jcc(Assembler::zero, done);
9797
9798 // ~(~0 << length), where length is the # of remaining elements to process
9799 movl(tmp3_aliased, -1);
9800 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9801 notl(tmp3_aliased);
9802 kmovdl(k2, tmp3_aliased);
9803 evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9804 evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9805
9806 jmp(done);
9807 bind(avx3_threshold);
9808 }
9809 if (UseSSE42Intrinsics) {
9810 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9811
9812 if (UseAVX > 1) {
9813 andl(tmp2, (16 - 1));
9814 andl(len, -16);
9815 jccb(Assembler::zero, copy_new_tail);
9816 } else {
9817 andl(tmp2, 0x00000007); // tail count (in chars)
9818 andl(len, 0xfffffff8); // vector count (in chars)
9819 jccb(Assembler::zero, copy_tail);
9820 }
9821
9822 // vectored inflation
9823 lea(src, Address(src, len, Address::times_1));
9824 lea(dst, Address(dst, len, Address::times_2));
9825 negptr(len);
9826
9827 if (UseAVX > 1) {
9828 bind(copy_16_loop);
9829 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9830 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9831 addptr(len, 16);
9832 jcc(Assembler::notZero, copy_16_loop);
9833
9834 bind(below_threshold);
9835 bind(copy_new_tail);
9836 movl(len, tmp2);
9837 andl(tmp2, 0x00000007);
9838 andl(len, 0xFFFFFFF8);
9839 jccb(Assembler::zero, copy_tail);
9840
9841 pmovzxbw(tmp1, Address(src, 0));
9842 movdqu(Address(dst, 0), tmp1);
9843 addptr(src, 8);
9844 addptr(dst, 2 * 8);
9845
9846 jmp(copy_tail, true);
9847 }
9848
9849 // inflate 8 chars per iter
9850 bind(copy_8_loop);
9851 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9852 movdqu(Address(dst, len, Address::times_2), tmp1);
9853 addptr(len, 8);
9854 jcc(Assembler::notZero, copy_8_loop);
9855
9856 bind(copy_tail);
9857 movl(len, tmp2);
9858
9859 cmpl(len, 4);
9860 jccb(Assembler::less, copy_bytes);
9861
9862 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9863 pmovzxbw(tmp1, tmp1);
9864 movq(Address(dst, 0), tmp1);
9865 subptr(len, 4);
9866 addptr(src, 4);
9867 addptr(dst, 8);
9868
9869 bind(copy_bytes);
9870 } else {
9871 bind(below_threshold);
9872 }
9873
9874 testl(len, len);
9875 jccb(Assembler::zero, done);
9876 lea(src, Address(src, len, Address::times_1));
9877 lea(dst, Address(dst, len, Address::times_2));
9878 negptr(len);
9879
9880 // inflate 1 char per iter
9881 bind(copy_chars_loop);
9882 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9883 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9884 increment(len);
9885 jcc(Assembler::notZero, copy_chars_loop);
9886
9887 bind(done);
9888 }
9889
9890 #ifdef _LP64
9891 void MacroAssembler::cache_wb(Address line)
9892 {
9893 // 64 bit cpus always support clflush
9894 assert(VM_Version::supports_clflush(), "clflush should be available");
9895 bool optimized = VM_Version::supports_clflushopt();
9896 bool no_evict = VM_Version::supports_clwb();
9897
9898 // prefer clwb (writeback without evict) otherwise
9899 // prefer clflushopt (potentially parallel writeback with evict)
9900 // otherwise fallback on clflush (serial writeback with evict)
9901
9902 if (optimized) {
9903 if (no_evict) {
9904 clwb(line);
9905 } else {
9906 clflushopt(line);
9907 }
9908 } else {
9909 // no need for fence when using CLFLUSH
9910 clflush(line);
9911 }
9912 }
9913
9914 void MacroAssembler::cache_wbsync(bool is_pre)
9915 {
9916 assert(VM_Version::supports_clflush(), "clflush should be available");
9917 bool optimized = VM_Version::supports_clflushopt();
9918 bool no_evict = VM_Version::supports_clwb();
9919
9920 // pick the correct implementation
9921
9922 if (!is_pre && (optimized || no_evict)) {
9923 // need an sfence for post flush when using clflushopt or clwb
9924 // otherwise no no need for any synchroniaztion
9925
9926 sfence();
9927 }
9928 }
9929 #endif // _LP64
9930
9931 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9932 switch (cond) {
9933 // Note some conditions are synonyms for others
9934 case Assembler::zero: return Assembler::notZero;
9935 case Assembler::notZero: return Assembler::zero;
9936 case Assembler::less: return Assembler::greaterEqual;
9937 case Assembler::lessEqual: return Assembler::greater;
9938 case Assembler::greater: return Assembler::lessEqual;
9939 case Assembler::greaterEqual: return Assembler::less;
9940 case Assembler::below: return Assembler::aboveEqual;
9941 case Assembler::belowEqual: return Assembler::above;
9942 case Assembler::above: return Assembler::belowEqual;
9943 case Assembler::aboveEqual: return Assembler::below;
9944 case Assembler::overflow: return Assembler::noOverflow;
9945 case Assembler::noOverflow: return Assembler::overflow;
9946 case Assembler::negative: return Assembler::positive;
9947 case Assembler::positive: return Assembler::negative;
9948 case Assembler::parity: return Assembler::noParity;
9949 case Assembler::noParity: return Assembler::parity;
9950 }
9951 ShouldNotReachHere(); return Assembler::overflow;
9952 }
9953
9954 SkipIfEqual::SkipIfEqual(
9955 MacroAssembler* masm, const bool* flag_addr, bool value) {
9956 _masm = masm;
9957 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9958 _masm->jcc(Assembler::equal, _label);
9959 }
9960
9961 SkipIfEqual::~SkipIfEqual() {
9962 _masm->bind(_label);
9963 }
9964
9965 // 32-bit Windows has its own fast-path implementation
9966 // of get_thread
9967 #if !defined(WIN32) || defined(_LP64)
9968
9969 // This is simply a call to Thread::current()
9970 void MacroAssembler::get_thread(Register thread) {
9971 if (thread != rax) {
9972 push(rax);
9973 }
9974 LP64_ONLY(push(rdi);)
9975 LP64_ONLY(push(rsi);)
9976 push(rdx);
9977 push(rcx);
9978 #ifdef _LP64
9979 push(r8);
9980 push(r9);
9981 push(r10);
9982 push(r11);
9983 #endif
9984
9985 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9986
9987 #ifdef _LP64
9988 pop(r11);
9989 pop(r10);
9990 pop(r9);
9991 pop(r8);
9992 #endif
9993 pop(rcx);
9994 pop(rdx);
9995 LP64_ONLY(pop(rsi);)
9996 LP64_ONLY(pop(rdi);)
9997 if (thread != rax) {
9998 mov(thread, rax);
9999 pop(rax);
10000 }
10001 }
10002
10003 #endif