407 }
408
409 //-------------------visits--------------------------
410
411 // complete rework of LIR instruction visitor.
412 // The virtual call for each instruction type is replaced by a big
413 // switch that adds the operands for each instruction
414
415 void LIR_OpVisitState::visit(LIR_Op* op) {
416 // copy information from the LIR_Op
417 reset();
418 set_op(op);
419
420 switch (op->code()) {
421
422 // LIR_Op0
423 case lir_word_align: // result and info always invalid
424 case lir_backwardbranch_target: // result and info always invalid
425 case lir_build_frame: // result and info always invalid
426 case lir_fpop_raw: // result and info always invalid
427 case lir_24bit_FPU: // result and info always invalid
428 case lir_reset_FPU: // result and info always invalid
429 case lir_breakpoint: // result and info always invalid
430 case lir_membar: // result and info always invalid
431 case lir_membar_acquire: // result and info always invalid
432 case lir_membar_release: // result and info always invalid
433 case lir_membar_loadload: // result and info always invalid
434 case lir_membar_storestore: // result and info always invalid
435 case lir_membar_loadstore: // result and info always invalid
436 case lir_membar_storeload: // result and info always invalid
437 case lir_on_spin_wait:
438 {
439 assert(op->as_Op0() != NULL, "must be");
440 assert(op->_info == NULL, "info not used by this instruction");
441 assert(op->_result->is_illegal(), "not used");
442 break;
443 }
444
445 case lir_nop: // may have info, result always invalid
446 case lir_std_entry: // may have result, info always invalid
447 case lir_osr_entry: // may have result, info always invalid
448 case lir_get_thread: // may have result, info always invalid
450 assert(op->as_Op0() != NULL, "must be");
451 if (op->_info != NULL) do_info(op->_info);
452 if (op->_result->is_valid()) do_output(op->_result);
453 break;
454 }
455
456
457 // LIR_OpLabel
458 case lir_label: // result and info always invalid
459 {
460 assert(op->as_OpLabel() != NULL, "must be");
461 assert(op->_info == NULL, "info not used by this instruction");
462 assert(op->_result->is_illegal(), "not used");
463 break;
464 }
465
466
467 // LIR_Op1
468 case lir_fxch: // input always valid, result and info always invalid
469 case lir_fld: // input always valid, result and info always invalid
470 case lir_ffree: // input always valid, result and info always invalid
471 case lir_push: // input always valid, result and info always invalid
472 case lir_pop: // input always valid, result and info always invalid
473 case lir_return: // input always valid, result and info always invalid
474 case lir_leal: // input and result always valid, info always invalid
475 case lir_monaddr: // input and result always valid, info always invalid
476 case lir_null_check: // input and info always valid, result always invalid
477 case lir_move: // input and result always valid, may have info
478 case lir_pack64: // input and result always valid
479 case lir_unpack64: // input and result always valid
480 {
481 assert(op->as_Op1() != NULL, "must be");
482 LIR_Op1* op1 = (LIR_Op1*)op;
483
484 if (op1->_info) do_info(op1->_info);
485 if (op1->_opr->is_valid()) do_input(op1->_opr);
486 if (op1->_result->is_valid()) do_output(op1->_result);
487
488 break;
489 }
490
1632 const char * LIR_Op::name() const {
1633 const char* s = NULL;
1634 switch(code()) {
1635 // LIR_Op0
1636 case lir_membar: s = "membar"; break;
1637 case lir_membar_acquire: s = "membar_acquire"; break;
1638 case lir_membar_release: s = "membar_release"; break;
1639 case lir_membar_loadload: s = "membar_loadload"; break;
1640 case lir_membar_storestore: s = "membar_storestore"; break;
1641 case lir_membar_loadstore: s = "membar_loadstore"; break;
1642 case lir_membar_storeload: s = "membar_storeload"; break;
1643 case lir_word_align: s = "word_align"; break;
1644 case lir_label: s = "label"; break;
1645 case lir_nop: s = "nop"; break;
1646 case lir_on_spin_wait: s = "on_spin_wait"; break;
1647 case lir_backwardbranch_target: s = "backbranch"; break;
1648 case lir_std_entry: s = "std_entry"; break;
1649 case lir_osr_entry: s = "osr_entry"; break;
1650 case lir_build_frame: s = "build_frm"; break;
1651 case lir_fpop_raw: s = "fpop_raw"; break;
1652 case lir_24bit_FPU: s = "24bit_FPU"; break;
1653 case lir_reset_FPU: s = "reset_FPU"; break;
1654 case lir_breakpoint: s = "breakpoint"; break;
1655 case lir_get_thread: s = "get_thread"; break;
1656 // LIR_Op1
1657 case lir_fxch: s = "fxch"; break;
1658 case lir_fld: s = "fld"; break;
1659 case lir_ffree: s = "ffree"; break;
1660 case lir_push: s = "push"; break;
1661 case lir_pop: s = "pop"; break;
1662 case lir_null_check: s = "null_check"; break;
1663 case lir_return: s = "return"; break;
1664 case lir_safepoint: s = "safepoint"; break;
1665 case lir_leal: s = "leal"; break;
1666 case lir_branch: s = "branch"; break;
1667 case lir_cond_float_branch: s = "flt_cond_br"; break;
1668 case lir_move: s = "move"; break;
1669 case lir_roundfp: s = "roundfp"; break;
1670 case lir_rtcall: s = "rtcall"; break;
1671 case lir_throw: s = "throw"; break;
1672 case lir_unwind: s = "unwind"; break;
1673 case lir_convert: s = "convert"; break;
1674 case lir_alloc_object: s = "alloc_obj"; break;
1675 case lir_monaddr: s = "mon_addr"; break;
1676 case lir_pack64: s = "pack64"; break;
1677 case lir_unpack64: s = "unpack64"; break;
1678 // LIR_Op2
1679 case lir_cmp: s = "cmp"; break;
|
407 }
408
409 //-------------------visits--------------------------
410
411 // complete rework of LIR instruction visitor.
412 // The virtual call for each instruction type is replaced by a big
413 // switch that adds the operands for each instruction
414
415 void LIR_OpVisitState::visit(LIR_Op* op) {
416 // copy information from the LIR_Op
417 reset();
418 set_op(op);
419
420 switch (op->code()) {
421
422 // LIR_Op0
423 case lir_word_align: // result and info always invalid
424 case lir_backwardbranch_target: // result and info always invalid
425 case lir_build_frame: // result and info always invalid
426 case lir_fpop_raw: // result and info always invalid
427 case lir_breakpoint: // result and info always invalid
428 case lir_membar: // result and info always invalid
429 case lir_membar_acquire: // result and info always invalid
430 case lir_membar_release: // result and info always invalid
431 case lir_membar_loadload: // result and info always invalid
432 case lir_membar_storestore: // result and info always invalid
433 case lir_membar_loadstore: // result and info always invalid
434 case lir_membar_storeload: // result and info always invalid
435 case lir_on_spin_wait:
436 {
437 assert(op->as_Op0() != NULL, "must be");
438 assert(op->_info == NULL, "info not used by this instruction");
439 assert(op->_result->is_illegal(), "not used");
440 break;
441 }
442
443 case lir_nop: // may have info, result always invalid
444 case lir_std_entry: // may have result, info always invalid
445 case lir_osr_entry: // may have result, info always invalid
446 case lir_get_thread: // may have result, info always invalid
448 assert(op->as_Op0() != NULL, "must be");
449 if (op->_info != NULL) do_info(op->_info);
450 if (op->_result->is_valid()) do_output(op->_result);
451 break;
452 }
453
454
455 // LIR_OpLabel
456 case lir_label: // result and info always invalid
457 {
458 assert(op->as_OpLabel() != NULL, "must be");
459 assert(op->_info == NULL, "info not used by this instruction");
460 assert(op->_result->is_illegal(), "not used");
461 break;
462 }
463
464
465 // LIR_Op1
466 case lir_fxch: // input always valid, result and info always invalid
467 case lir_fld: // input always valid, result and info always invalid
468 case lir_push: // input always valid, result and info always invalid
469 case lir_pop: // input always valid, result and info always invalid
470 case lir_return: // input always valid, result and info always invalid
471 case lir_leal: // input and result always valid, info always invalid
472 case lir_monaddr: // input and result always valid, info always invalid
473 case lir_null_check: // input and info always valid, result always invalid
474 case lir_move: // input and result always valid, may have info
475 case lir_pack64: // input and result always valid
476 case lir_unpack64: // input and result always valid
477 {
478 assert(op->as_Op1() != NULL, "must be");
479 LIR_Op1* op1 = (LIR_Op1*)op;
480
481 if (op1->_info) do_info(op1->_info);
482 if (op1->_opr->is_valid()) do_input(op1->_opr);
483 if (op1->_result->is_valid()) do_output(op1->_result);
484
485 break;
486 }
487
1629 const char * LIR_Op::name() const {
1630 const char* s = NULL;
1631 switch(code()) {
1632 // LIR_Op0
1633 case lir_membar: s = "membar"; break;
1634 case lir_membar_acquire: s = "membar_acquire"; break;
1635 case lir_membar_release: s = "membar_release"; break;
1636 case lir_membar_loadload: s = "membar_loadload"; break;
1637 case lir_membar_storestore: s = "membar_storestore"; break;
1638 case lir_membar_loadstore: s = "membar_loadstore"; break;
1639 case lir_membar_storeload: s = "membar_storeload"; break;
1640 case lir_word_align: s = "word_align"; break;
1641 case lir_label: s = "label"; break;
1642 case lir_nop: s = "nop"; break;
1643 case lir_on_spin_wait: s = "on_spin_wait"; break;
1644 case lir_backwardbranch_target: s = "backbranch"; break;
1645 case lir_std_entry: s = "std_entry"; break;
1646 case lir_osr_entry: s = "osr_entry"; break;
1647 case lir_build_frame: s = "build_frm"; break;
1648 case lir_fpop_raw: s = "fpop_raw"; break;
1649 case lir_breakpoint: s = "breakpoint"; break;
1650 case lir_get_thread: s = "get_thread"; break;
1651 // LIR_Op1
1652 case lir_fxch: s = "fxch"; break;
1653 case lir_fld: s = "fld"; break;
1654 case lir_push: s = "push"; break;
1655 case lir_pop: s = "pop"; break;
1656 case lir_null_check: s = "null_check"; break;
1657 case lir_return: s = "return"; break;
1658 case lir_safepoint: s = "safepoint"; break;
1659 case lir_leal: s = "leal"; break;
1660 case lir_branch: s = "branch"; break;
1661 case lir_cond_float_branch: s = "flt_cond_br"; break;
1662 case lir_move: s = "move"; break;
1663 case lir_roundfp: s = "roundfp"; break;
1664 case lir_rtcall: s = "rtcall"; break;
1665 case lir_throw: s = "throw"; break;
1666 case lir_unwind: s = "unwind"; break;
1667 case lir_convert: s = "convert"; break;
1668 case lir_alloc_object: s = "alloc_obj"; break;
1669 case lir_monaddr: s = "mon_addr"; break;
1670 case lir_pack64: s = "pack64"; break;
1671 case lir_unpack64: s = "unpack64"; break;
1672 // LIR_Op2
1673 case lir_cmp: s = "cmp"; break;
|