1 /*
   2  * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "runtime/timerTrace.hpp"
  36 #include "utilities/bitMap.inline.hpp"
  37 
  38 #ifndef PRODUCT
  39 
  40   static LinearScanStatistic _stat_before_alloc;
  41   static LinearScanStatistic _stat_after_asign;
  42   static LinearScanStatistic _stat_final;
  43 
  44   static LinearScanTimers _total_timer;
  45 
  46   // helper macro for short definition of timer
  47   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  48 
  49   // helper macro for short definition of trace-output inside code
  50   #define TRACE_LINEAR_SCAN(level, code)       \
  51     if (TraceLinearScanLevel >= level) {       \
  52       code;                                    \
  53     }
  54 
  55 #else
  56 
  57   #define TIME_LINEAR_SCAN(timer_name)
  58   #define TRACE_LINEAR_SCAN(level, code)
  59 
  60 #endif
  61 
  62 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  63 #ifdef _LP64
  64 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  65 #else
  66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  67 #endif
  68 
  69 
  70 // Implementation of LinearScan
  71 
  72 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  73  : _compilation(ir->compilation())
  74  , _ir(ir)
  75  , _gen(gen)
  76  , _frame_map(frame_map)
  77  , _cached_blocks(*ir->linear_scan_order())
  78  , _num_virtual_regs(gen->max_virtual_register_number())
  79  , _has_fpu_registers(false)
  80  , _num_calls(-1)
  81  , _max_spills(0)
  82  , _unused_spill_slot(-1)
  83  , _intervals(0)   // initialized later with correct length
  84  , _new_intervals_from_allocation(NULL)
  85  , _sorted_intervals(NULL)
  86  , _needs_full_resort(false)
  87  , _lir_ops(0)     // initialized later with correct length
  88  , _block_of_op(0) // initialized later with correct length
  89  , _has_info(0)
  90  , _has_call(0)
  91  , _interval_in_loop(0)  // initialized later with correct length
  92  , _scope_value_cache(0) // initialized later with correct length
  93 #ifdef IA32
  94  , _fpu_stack_allocator(NULL)
  95 #endif
  96 {
  97   assert(this->ir() != NULL,          "check if valid");
  98   assert(this->compilation() != NULL, "check if valid");
  99   assert(this->gen() != NULL,         "check if valid");
 100   assert(this->frame_map() != NULL,   "check if valid");
 101 }
 102 
 103 
 104 // ********** functions for converting LIR-Operands to register numbers
 105 //
 106 // Emulate a flat register file comprising physical integer registers,
 107 // physical floating-point registers and virtual registers, in that order.
 108 // Virtual registers already have appropriate numbers, since V0 is
 109 // the number of physical registers.
 110 // Returns -1 for hi word if opr is a single word operand.
 111 //
 112 // Note: the inverse operation (calculating an operand for register numbers)
 113 //       is done in calc_operand_for_interval()
 114 
 115 int LinearScan::reg_num(LIR_Opr opr) {
 116   assert(opr->is_register(), "should not call this otherwise");
 117 
 118   if (opr->is_virtual_register()) {
 119     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 120     return opr->vreg_number();
 121   } else if (opr->is_single_cpu()) {
 122     return opr->cpu_regnr();
 123   } else if (opr->is_double_cpu()) {
 124     return opr->cpu_regnrLo();
 125 #ifdef X86
 126   } else if (opr->is_single_xmm()) {
 127     return opr->fpu_regnr() + pd_first_xmm_reg;
 128   } else if (opr->is_double_xmm()) {
 129     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 130 #endif
 131   } else if (opr->is_single_fpu()) {
 132     return opr->fpu_regnr() + pd_first_fpu_reg;
 133   } else if (opr->is_double_fpu()) {
 134     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 135   } else {
 136     ShouldNotReachHere();
 137     return -1;
 138   }
 139 }
 140 
 141 int LinearScan::reg_numHi(LIR_Opr opr) {
 142   assert(opr->is_register(), "should not call this otherwise");
 143 
 144   if (opr->is_virtual_register()) {
 145     return -1;
 146   } else if (opr->is_single_cpu()) {
 147     return -1;
 148   } else if (opr->is_double_cpu()) {
 149     return opr->cpu_regnrHi();
 150 #ifdef X86
 151   } else if (opr->is_single_xmm()) {
 152     return -1;
 153   } else if (opr->is_double_xmm()) {
 154     return -1;
 155 #endif
 156   } else if (opr->is_single_fpu()) {
 157     return -1;
 158   } else if (opr->is_double_fpu()) {
 159     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 160   } else {
 161     ShouldNotReachHere();
 162     return -1;
 163   }
 164 }
 165 
 166 
 167 // ********** functions for classification of intervals
 168 
 169 bool LinearScan::is_precolored_interval(const Interval* i) {
 170   return i->reg_num() < LinearScan::nof_regs;
 171 }
 172 
 173 bool LinearScan::is_virtual_interval(const Interval* i) {
 174   return i->reg_num() >= LIR_OprDesc::vreg_base;
 175 }
 176 
 177 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 178   return i->reg_num() < LinearScan::nof_cpu_regs;
 179 }
 180 
 181 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 182 #if defined(__SOFTFP__) || defined(E500V2)
 183   return i->reg_num() >= LIR_OprDesc::vreg_base;
 184 #else
 185   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 186 #endif // __SOFTFP__ or E500V2
 187 }
 188 
 189 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 190   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 191 }
 192 
 193 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 194 #if defined(__SOFTFP__) || defined(E500V2)
 195   return false;
 196 #else
 197   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 198 #endif // __SOFTFP__ or E500V2
 199 }
 200 
 201 bool LinearScan::is_in_fpu_register(const Interval* i) {
 202   // fixed intervals not needed for FPU stack allocation
 203   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 204 }
 205 
 206 bool LinearScan::is_oop_interval(const Interval* i) {
 207   // fixed intervals never contain oops
 208   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 209 }
 210 
 211 
 212 // ********** General helper functions
 213 
 214 // compute next unused stack index that can be used for spilling
 215 int LinearScan::allocate_spill_slot(bool double_word) {
 216   int spill_slot;
 217   if (double_word) {
 218     if ((_max_spills & 1) == 1) {
 219       // alignment of double-word values
 220       // the hole because of the alignment is filled with the next single-word value
 221       assert(_unused_spill_slot == -1, "wasting a spill slot");
 222       _unused_spill_slot = _max_spills;
 223       _max_spills++;
 224     }
 225     spill_slot = _max_spills;
 226     _max_spills += 2;
 227 
 228   } else if (_unused_spill_slot != -1) {
 229     // re-use hole that was the result of a previous double-word alignment
 230     spill_slot = _unused_spill_slot;
 231     _unused_spill_slot = -1;
 232 
 233   } else {
 234     spill_slot = _max_spills;
 235     _max_spills++;
 236   }
 237 
 238   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 239 
 240   // the class OopMapValue uses only 11 bits for storing the name of the
 241   // oop location. So a stack slot bigger than 2^11 leads to an overflow
 242   // that is not reported in product builds. Prevent this by checking the
 243   // spill slot here (altough this value and the later used location name
 244   // are slightly different)
 245   if (result > 2000) {
 246     bailout("too many stack slots used");
 247   }
 248 
 249   return result;
 250 }
 251 
 252 void LinearScan::assign_spill_slot(Interval* it) {
 253   // assign the canonical spill slot of the parent (if a part of the interval
 254   // is already spilled) or allocate a new spill slot
 255   if (it->canonical_spill_slot() >= 0) {
 256     it->assign_reg(it->canonical_spill_slot());
 257   } else {
 258     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 259     it->set_canonical_spill_slot(spill);
 260     it->assign_reg(spill);
 261   }
 262 }
 263 
 264 void LinearScan::propagate_spill_slots() {
 265   if (!frame_map()->finalize_frame(max_spills())) {
 266     bailout("frame too large");
 267   }
 268 }
 269 
 270 // create a new interval with a predefined reg_num
 271 // (only used for parent intervals that are created during the building phase)
 272 Interval* LinearScan::create_interval(int reg_num) {
 273   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 274 
 275   Interval* interval = new Interval(reg_num);
 276   _intervals.at_put(reg_num, interval);
 277 
 278   // assign register number for precolored intervals
 279   if (reg_num < LIR_OprDesc::vreg_base) {
 280     interval->assign_reg(reg_num);
 281   }
 282   return interval;
 283 }
 284 
 285 // assign a new reg_num to the interval and append it to the list of intervals
 286 // (only used for child intervals that are created during register allocation)
 287 void LinearScan::append_interval(Interval* it) {
 288   it->set_reg_num(_intervals.length());
 289   _intervals.append(it);
 290   IntervalList* new_intervals = _new_intervals_from_allocation;
 291   if (new_intervals == NULL) {
 292     new_intervals = _new_intervals_from_allocation = new IntervalList();
 293   }
 294   new_intervals->append(it);
 295 }
 296 
 297 // copy the vreg-flags if an interval is split
 298 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 299   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 300     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 301   }
 302   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 303     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 304   }
 305 
 306   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 307   //       intervals (only the very beginning of the interval must be in memory)
 308 }
 309 
 310 
 311 // ********** spill move optimization
 312 // eliminate moves from register to stack if stack slot is known to be correct
 313 
 314 // called during building of intervals
 315 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 316   assert(interval->is_split_parent(), "can only be called for split parents");
 317 
 318   switch (interval->spill_state()) {
 319     case noDefinitionFound:
 320       assert(interval->spill_definition_pos() == -1, "must no be set before");
 321       interval->set_spill_definition_pos(def_pos);
 322       interval->set_spill_state(oneDefinitionFound);
 323       break;
 324 
 325     case oneDefinitionFound:
 326       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 327       if (def_pos < interval->spill_definition_pos() - 2) {
 328         // second definition found, so no spill optimization possible for this interval
 329         interval->set_spill_state(noOptimization);
 330       } else {
 331         // two consecutive definitions (because of two-operand LIR form)
 332         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 333       }
 334       break;
 335 
 336     case noOptimization:
 337       // nothing to do
 338       break;
 339 
 340     default:
 341       assert(false, "other states not allowed at this time");
 342   }
 343 }
 344 
 345 // called during register allocation
 346 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 347   switch (interval->spill_state()) {
 348     case oneDefinitionFound: {
 349       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 350       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 351 
 352       if (def_loop_depth < spill_loop_depth) {
 353         // the loop depth of the spilling position is higher then the loop depth
 354         // at the definition of the interval -> move write to memory out of loop
 355         // by storing at definitin of the interval
 356         interval->set_spill_state(storeAtDefinition);
 357       } else {
 358         // the interval is currently spilled only once, so for now there is no
 359         // reason to store the interval at the definition
 360         interval->set_spill_state(oneMoveInserted);
 361       }
 362       break;
 363     }
 364 
 365     case oneMoveInserted: {
 366       // the interval is spilled more then once, so it is better to store it to
 367       // memory at the definition
 368       interval->set_spill_state(storeAtDefinition);
 369       break;
 370     }
 371 
 372     case storeAtDefinition:
 373     case startInMemory:
 374     case noOptimization:
 375     case noDefinitionFound:
 376       // nothing to do
 377       break;
 378 
 379     default:
 380       assert(false, "other states not allowed at this time");
 381   }
 382 }
 383 
 384 
 385 bool LinearScan::must_store_at_definition(const Interval* i) {
 386   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 387 }
 388 
 389 // called once before asignment of register numbers
 390 void LinearScan::eliminate_spill_moves() {
 391   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 392   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 393 
 394   // collect all intervals that must be stored after their definion.
 395   // the list is sorted by Interval::spill_definition_pos
 396   Interval* interval;
 397   Interval* temp_list;
 398   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 399 
 400 #ifdef ASSERT
 401   Interval* prev = NULL;
 402   Interval* temp = interval;
 403   while (temp != Interval::end()) {
 404     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 405     if (prev != NULL) {
 406       assert(temp->from() >= prev->from(), "intervals not sorted");
 407       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 408     }
 409 
 410     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 411     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 412     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 413 
 414     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 415 
 416     temp = temp->next();
 417   }
 418 #endif
 419 
 420   LIR_InsertionBuffer insertion_buffer;
 421   int num_blocks = block_count();
 422   for (int i = 0; i < num_blocks; i++) {
 423     BlockBegin* block = block_at(i);
 424     LIR_OpList* instructions = block->lir()->instructions_list();
 425     int         num_inst = instructions->length();
 426     bool        has_new = false;
 427 
 428     // iterate all instructions of the block. skip the first because it is always a label
 429     for (int j = 1; j < num_inst; j++) {
 430       LIR_Op* op = instructions->at(j);
 431       int op_id = op->id();
 432 
 433       if (op_id == -1) {
 434         // remove move from register to stack if the stack slot is guaranteed to be correct.
 435         // only moves that have been inserted by LinearScan can be removed.
 436         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 437         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 438         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 439 
 440         LIR_Op1* op1 = (LIR_Op1*)op;
 441         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 442 
 443         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 444           // move target is a stack slot that is always correct, so eliminate instruction
 445           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 446           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 447         }
 448 
 449       } else {
 450         // insert move from register to stack just after the beginning of the interval
 451         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 452         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 453 
 454         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 455           if (!has_new) {
 456             // prepare insertion buffer (appended when all instructions of the block are processed)
 457             insertion_buffer.init(block->lir());
 458             has_new = true;
 459           }
 460 
 461           LIR_Opr from_opr = operand_for_interval(interval);
 462           LIR_Opr to_opr = canonical_spill_opr(interval);
 463           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 464           assert(to_opr->is_stack(), "to operand must be a stack slot");
 465 
 466           insertion_buffer.move(j, from_opr, to_opr);
 467           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 468 
 469           interval = interval->next();
 470         }
 471       }
 472     } // end of instruction iteration
 473 
 474     if (has_new) {
 475       block->lir()->append(&insertion_buffer);
 476     }
 477   } // end of block iteration
 478 
 479   assert(interval == Interval::end(), "missed an interval");
 480 }
 481 
 482 
 483 // ********** Phase 1: number all instructions in all blocks
 484 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 485 
 486 void LinearScan::number_instructions() {
 487   {
 488     // dummy-timer to measure the cost of the timer itself
 489     // (this time is then subtracted from all other timers to get the real value)
 490     TIME_LINEAR_SCAN(timer_do_nothing);
 491   }
 492   TIME_LINEAR_SCAN(timer_number_instructions);
 493 
 494   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 495   int num_blocks = block_count();
 496   int num_instructions = 0;
 497   int i;
 498   for (i = 0; i < num_blocks; i++) {
 499     num_instructions += block_at(i)->lir()->instructions_list()->length();
 500   }
 501 
 502   // initialize with correct length
 503   _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
 504   _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
 505 
 506   int op_id = 0;
 507   int idx = 0;
 508 
 509   for (i = 0; i < num_blocks; i++) {
 510     BlockBegin* block = block_at(i);
 511     block->set_first_lir_instruction_id(op_id);
 512     LIR_OpList* instructions = block->lir()->instructions_list();
 513 
 514     int num_inst = instructions->length();
 515     for (int j = 0; j < num_inst; j++) {
 516       LIR_Op* op = instructions->at(j);
 517       op->set_id(op_id);
 518 
 519       _lir_ops.at_put(idx, op);
 520       _block_of_op.at_put(idx, block);
 521       assert(lir_op_with_id(op_id) == op, "must match");
 522 
 523       idx++;
 524       op_id += 2; // numbering of lir_ops by two
 525     }
 526     block->set_last_lir_instruction_id(op_id - 2);
 527   }
 528   assert(idx == num_instructions, "must match");
 529   assert(idx * 2 == op_id, "must match");
 530 
 531   _has_call.initialize(num_instructions);
 532   _has_info.initialize(num_instructions);
 533 }
 534 
 535 
 536 // ********** Phase 2: compute local live sets separately for each block
 537 // (sets live_gen and live_kill for each block)
 538 
 539 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 540   LIR_Opr opr = value->operand();
 541   Constant* con = value->as_Constant();
 542 
 543   // check some asumptions about debug information
 544   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 545   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 546   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 547 
 548   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 549     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 550     int reg = opr->vreg_number();
 551     if (!live_kill.at(reg)) {
 552       live_gen.set_bit(reg);
 553       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 554     }
 555   }
 556 }
 557 
 558 
 559 void LinearScan::compute_local_live_sets() {
 560   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 561 
 562   int  num_blocks = block_count();
 563   int  live_size = live_set_size();
 564   bool local_has_fpu_registers = false;
 565   int  local_num_calls = 0;
 566   LIR_OpVisitState visitor;
 567 
 568   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 569 
 570   // iterate all blocks
 571   for (int i = 0; i < num_blocks; i++) {
 572     BlockBegin* block = block_at(i);
 573 
 574     ResourceBitMap live_gen(live_size);
 575     ResourceBitMap live_kill(live_size);
 576 
 577     if (block->is_set(BlockBegin::exception_entry_flag)) {
 578       // Phi functions at the begin of an exception handler are
 579       // implicitly defined (= killed) at the beginning of the block.
 580       for_each_phi_fun(block, phi,
 581         if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
 582       );
 583     }
 584 
 585     LIR_OpList* instructions = block->lir()->instructions_list();
 586     int num_inst = instructions->length();
 587 
 588     // iterate all instructions of the block. skip the first because it is always a label
 589     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 590     for (int j = 1; j < num_inst; j++) {
 591       LIR_Op* op = instructions->at(j);
 592 
 593       // visit operation to collect all operands
 594       visitor.visit(op);
 595 
 596       if (visitor.has_call()) {
 597         _has_call.set_bit(op->id() >> 1);
 598         local_num_calls++;
 599       }
 600       if (visitor.info_count() > 0) {
 601         _has_info.set_bit(op->id() >> 1);
 602       }
 603 
 604       // iterate input operands of instruction
 605       int k, n, reg;
 606       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 607       for (k = 0; k < n; k++) {
 608         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 609         assert(opr->is_register(), "visitor should only return register operands");
 610 
 611         if (opr->is_virtual_register()) {
 612           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 613           reg = opr->vreg_number();
 614           if (!live_kill.at(reg)) {
 615             live_gen.set_bit(reg);
 616             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 617           }
 618           if (block->loop_index() >= 0) {
 619             local_interval_in_loop.set_bit(reg, block->loop_index());
 620           }
 621           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 622         }
 623 
 624 #ifdef ASSERT
 625         // fixed intervals are never live at block boundaries, so
 626         // they need not be processed in live sets.
 627         // this is checked by these assertions to be sure about it.
 628         // the entry block may have incoming values in registers, which is ok.
 629         if (!opr->is_virtual_register() && block != ir()->start()) {
 630           reg = reg_num(opr);
 631           if (is_processed_reg_num(reg)) {
 632             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 633           }
 634           reg = reg_numHi(opr);
 635           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 636             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 637           }
 638         }
 639 #endif
 640       }
 641 
 642       // Add uses of live locals from interpreter's point of view for proper debug information generation
 643       n = visitor.info_count();
 644       for (k = 0; k < n; k++) {
 645         CodeEmitInfo* info = visitor.info_at(k);
 646         ValueStack* stack = info->stack();
 647         for_each_state_value(stack, value,
 648           set_live_gen_kill(value, op, live_gen, live_kill)
 649         );
 650       }
 651 
 652       // iterate temp operands of instruction
 653       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 654       for (k = 0; k < n; k++) {
 655         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 656         assert(opr->is_register(), "visitor should only return register operands");
 657 
 658         if (opr->is_virtual_register()) {
 659           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 660           reg = opr->vreg_number();
 661           live_kill.set_bit(reg);
 662           if (block->loop_index() >= 0) {
 663             local_interval_in_loop.set_bit(reg, block->loop_index());
 664           }
 665           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 666         }
 667 
 668 #ifdef ASSERT
 669         // fixed intervals are never live at block boundaries, so
 670         // they need not be processed in live sets
 671         // process them only in debug mode so that this can be checked
 672         if (!opr->is_virtual_register()) {
 673           reg = reg_num(opr);
 674           if (is_processed_reg_num(reg)) {
 675             live_kill.set_bit(reg_num(opr));
 676           }
 677           reg = reg_numHi(opr);
 678           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 679             live_kill.set_bit(reg);
 680           }
 681         }
 682 #endif
 683       }
 684 
 685       // iterate output operands of instruction
 686       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 687       for (k = 0; k < n; k++) {
 688         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 689         assert(opr->is_register(), "visitor should only return register operands");
 690 
 691         if (opr->is_virtual_register()) {
 692           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 693           reg = opr->vreg_number();
 694           live_kill.set_bit(reg);
 695           if (block->loop_index() >= 0) {
 696             local_interval_in_loop.set_bit(reg, block->loop_index());
 697           }
 698           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 699         }
 700 
 701 #ifdef ASSERT
 702         // fixed intervals are never live at block boundaries, so
 703         // they need not be processed in live sets
 704         // process them only in debug mode so that this can be checked
 705         if (!opr->is_virtual_register()) {
 706           reg = reg_num(opr);
 707           if (is_processed_reg_num(reg)) {
 708             live_kill.set_bit(reg_num(opr));
 709           }
 710           reg = reg_numHi(opr);
 711           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 712             live_kill.set_bit(reg);
 713           }
 714         }
 715 #endif
 716       }
 717     } // end of instruction iteration
 718 
 719     block->set_live_gen (live_gen);
 720     block->set_live_kill(live_kill);
 721     block->set_live_in  (ResourceBitMap(live_size));
 722     block->set_live_out (ResourceBitMap(live_size));
 723 
 724     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 725     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 726   } // end of block iteration
 727 
 728   // propagate local calculated information into LinearScan object
 729   _has_fpu_registers = local_has_fpu_registers;
 730   compilation()->set_has_fpu_code(local_has_fpu_registers);
 731 
 732   _num_calls = local_num_calls;
 733   _interval_in_loop = local_interval_in_loop;
 734 }
 735 
 736 
 737 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 738 // (sets live_in and live_out for each block)
 739 
 740 void LinearScan::compute_global_live_sets() {
 741   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 742 
 743   int  num_blocks = block_count();
 744   bool change_occurred;
 745   bool change_occurred_in_block;
 746   int  iteration_count = 0;
 747   ResourceBitMap live_out(live_set_size()); // scratch set for calculations
 748 
 749   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 750   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 751   // Exception handlers must be processed because not all live values are
 752   // present in the state array, e.g. because of global value numbering
 753   do {
 754     change_occurred = false;
 755 
 756     // iterate all blocks in reverse order
 757     for (int i = num_blocks - 1; i >= 0; i--) {
 758       BlockBegin* block = block_at(i);
 759 
 760       change_occurred_in_block = false;
 761 
 762       // live_out(block) is the union of live_in(sux), for successors sux of block
 763       int n = block->number_of_sux();
 764       int e = block->number_of_exception_handlers();
 765       if (n + e > 0) {
 766         // block has successors
 767         if (n > 0) {
 768           live_out.set_from(block->sux_at(0)->live_in());
 769           for (int j = 1; j < n; j++) {
 770             live_out.set_union(block->sux_at(j)->live_in());
 771           }
 772         } else {
 773           live_out.clear();
 774         }
 775         for (int j = 0; j < e; j++) {
 776           live_out.set_union(block->exception_handler_at(j)->live_in());
 777         }
 778 
 779         if (!block->live_out().is_same(live_out)) {
 780           // A change occurred.  Swap the old and new live out sets to avoid copying.
 781           ResourceBitMap temp = block->live_out();
 782           block->set_live_out(live_out);
 783           live_out = temp;
 784 
 785           change_occurred = true;
 786           change_occurred_in_block = true;
 787         }
 788       }
 789 
 790       if (iteration_count == 0 || change_occurred_in_block) {
 791         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 792         // note: live_in has to be computed only in first iteration or if live_out has changed!
 793         ResourceBitMap live_in = block->live_in();
 794         live_in.set_from(block->live_out());
 795         live_in.set_difference(block->live_kill());
 796         live_in.set_union(block->live_gen());
 797       }
 798 
 799 #ifndef PRODUCT
 800       if (TraceLinearScanLevel >= 4) {
 801         char c = ' ';
 802         if (iteration_count == 0 || change_occurred_in_block) {
 803           c = '*';
 804         }
 805         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 806         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 807       }
 808 #endif
 809     }
 810     iteration_count++;
 811 
 812     if (change_occurred && iteration_count > 50) {
 813       BAILOUT("too many iterations in compute_global_live_sets");
 814     }
 815   } while (change_occurred);
 816 
 817 
 818 #ifdef ASSERT
 819   // check that fixed intervals are not live at block boundaries
 820   // (live set must be empty at fixed intervals)
 821   for (int i = 0; i < num_blocks; i++) {
 822     BlockBegin* block = block_at(i);
 823     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 824       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 825       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 826       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 827     }
 828   }
 829 #endif
 830 
 831   // check that the live_in set of the first block is empty
 832   ResourceBitMap live_in_args(ir()->start()->live_in().size());
 833   if (!ir()->start()->live_in().is_same(live_in_args)) {
 834 #ifdef ASSERT
 835     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 836     tty->print_cr("affected registers:");
 837     print_bitmap(ir()->start()->live_in());
 838 
 839     // print some additional information to simplify debugging
 840     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 841       if (ir()->start()->live_in().at(i)) {
 842         Instruction* instr = gen()->instruction_for_vreg(i);
 843         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 844 
 845         for (int j = 0; j < num_blocks; j++) {
 846           BlockBegin* block = block_at(j);
 847           if (block->live_gen().at(i)) {
 848             tty->print_cr("  used in block B%d", block->block_id());
 849           }
 850           if (block->live_kill().at(i)) {
 851             tty->print_cr("  defined in block B%d", block->block_id());
 852           }
 853         }
 854       }
 855     }
 856 
 857 #endif
 858     // when this fails, virtual registers are used before they are defined.
 859     assert(false, "live_in set of first block must be empty");
 860     // bailout of if this occurs in product mode.
 861     bailout("live_in set of first block not empty");
 862   }
 863 }
 864 
 865 
 866 // ********** Phase 4: build intervals
 867 // (fills the list _intervals)
 868 
 869 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 870   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 871   LIR_Opr opr = value->operand();
 872   Constant* con = value->as_Constant();
 873 
 874   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 875     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 876     add_use(opr, from, to, use_kind);
 877   }
 878 }
 879 
 880 
 881 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 882   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 883   assert(opr->is_register(), "should not be called otherwise");
 884 
 885   if (opr->is_virtual_register()) {
 886     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 887     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 888 
 889   } else {
 890     int reg = reg_num(opr);
 891     if (is_processed_reg_num(reg)) {
 892       add_def(reg, def_pos, use_kind, opr->type_register());
 893     }
 894     reg = reg_numHi(opr);
 895     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 896       add_def(reg, def_pos, use_kind, opr->type_register());
 897     }
 898   }
 899 }
 900 
 901 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 902   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 903   assert(opr->is_register(), "should not be called otherwise");
 904 
 905   if (opr->is_virtual_register()) {
 906     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 907     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 908 
 909   } else {
 910     int reg = reg_num(opr);
 911     if (is_processed_reg_num(reg)) {
 912       add_use(reg, from, to, use_kind, opr->type_register());
 913     }
 914     reg = reg_numHi(opr);
 915     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 916       add_use(reg, from, to, use_kind, opr->type_register());
 917     }
 918   }
 919 }
 920 
 921 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 922   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 923   assert(opr->is_register(), "should not be called otherwise");
 924 
 925   if (opr->is_virtual_register()) {
 926     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 927     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 928 
 929   } else {
 930     int reg = reg_num(opr);
 931     if (is_processed_reg_num(reg)) {
 932       add_temp(reg, temp_pos, use_kind, opr->type_register());
 933     }
 934     reg = reg_numHi(opr);
 935     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 936       add_temp(reg, temp_pos, use_kind, opr->type_register());
 937     }
 938   }
 939 }
 940 
 941 
 942 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 943   Interval* interval = interval_at(reg_num);
 944   if (interval != NULL) {
 945     assert(interval->reg_num() == reg_num, "wrong interval");
 946 
 947     if (type != T_ILLEGAL) {
 948       interval->set_type(type);
 949     }
 950 
 951     Range* r = interval->first();
 952     if (r->from() <= def_pos) {
 953       // Update the starting point (when a range is first created for a use, its
 954       // start is the beginning of the current block until a def is encountered.)
 955       r->set_from(def_pos);
 956       interval->add_use_pos(def_pos, use_kind);
 957 
 958     } else {
 959       // Dead value - make vacuous interval
 960       // also add use_kind for dead intervals
 961       interval->add_range(def_pos, def_pos + 1);
 962       interval->add_use_pos(def_pos, use_kind);
 963       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 964     }
 965 
 966   } else {
 967     // Dead value - make vacuous interval
 968     // also add use_kind for dead intervals
 969     interval = create_interval(reg_num);
 970     if (type != T_ILLEGAL) {
 971       interval->set_type(type);
 972     }
 973 
 974     interval->add_range(def_pos, def_pos + 1);
 975     interval->add_use_pos(def_pos, use_kind);
 976     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 977   }
 978 
 979   change_spill_definition_pos(interval, def_pos);
 980   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 981         // detection of method-parameters and roundfp-results
 982         // TODO: move this directly to position where use-kind is computed
 983     interval->set_spill_state(startInMemory);
 984   }
 985 }
 986 
 987 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 988   Interval* interval = interval_at(reg_num);
 989   if (interval == NULL) {
 990     interval = create_interval(reg_num);
 991   }
 992   assert(interval->reg_num() == reg_num, "wrong interval");
 993 
 994   if (type != T_ILLEGAL) {
 995     interval->set_type(type);
 996   }
 997 
 998   interval->add_range(from, to);
 999   interval->add_use_pos(to, use_kind);
1000 }
1001 
1002 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1003   Interval* interval = interval_at(reg_num);
1004   if (interval == NULL) {
1005     interval = create_interval(reg_num);
1006   }
1007   assert(interval->reg_num() == reg_num, "wrong interval");
1008 
1009   if (type != T_ILLEGAL) {
1010     interval->set_type(type);
1011   }
1012 
1013   interval->add_range(temp_pos, temp_pos + 1);
1014   interval->add_use_pos(temp_pos, use_kind);
1015 }
1016 
1017 
1018 // the results of this functions are used for optimizing spilling and reloading
1019 // if the functions return shouldHaveRegister and the interval is spilled,
1020 // it is not reloaded to a register.
1021 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1022   if (op->code() == lir_move) {
1023     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1024     LIR_Op1* move = (LIR_Op1*)op;
1025     LIR_Opr res = move->result_opr();
1026     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1027 
1028     if (result_in_memory) {
1029       // Begin of an interval with must_start_in_memory set.
1030       // This interval will always get a stack slot first, so return noUse.
1031       return noUse;
1032 
1033     } else if (move->in_opr()->is_stack()) {
1034       // method argument (condition must be equal to handle_method_arguments)
1035       return noUse;
1036 
1037     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1038       // Move from register to register
1039       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1040         // special handling of phi-function moves inside osr-entry blocks
1041         // input operand must have a register instead of output operand (leads to better register allocation)
1042         return shouldHaveRegister;
1043       }
1044     }
1045   }
1046 
1047   if (opr->is_virtual() &&
1048       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1049     // result is a stack-slot, so prevent immediate reloading
1050     return noUse;
1051   }
1052 
1053   // all other operands require a register
1054   return mustHaveRegister;
1055 }
1056 
1057 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1058   if (op->code() == lir_move) {
1059     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1060     LIR_Op1* move = (LIR_Op1*)op;
1061     LIR_Opr res = move->result_opr();
1062     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1063 
1064     if (result_in_memory) {
1065       // Move to an interval with must_start_in_memory set.
1066       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1067       return mustHaveRegister;
1068 
1069     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1070       // Move from register to register
1071       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1072         // special handling of phi-function moves inside osr-entry blocks
1073         // input operand must have a register instead of output operand (leads to better register allocation)
1074         return mustHaveRegister;
1075       }
1076 
1077       // The input operand is not forced to a register (moves from stack to register are allowed),
1078       // but it is faster if the input operand is in a register
1079       return shouldHaveRegister;
1080     }
1081   }
1082 
1083 
1084 #if defined(X86) || defined(S390)
1085   if (op->code() == lir_cmove) {
1086     // conditional moves can handle stack operands
1087     assert(op->result_opr()->is_register(), "result must always be in a register");
1088     return shouldHaveRegister;
1089   }
1090 
1091   // optimizations for second input operand of arithmehtic operations on Intel
1092   // this operand is allowed to be on the stack in some cases
1093   BasicType opr_type = opr->type_register();
1094   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1095     if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1096       // SSE float instruction (T_DOUBLE only supported with SSE2)
1097       switch (op->code()) {
1098         case lir_cmp:
1099         case lir_add:
1100         case lir_sub:
1101         case lir_mul:
1102         case lir_div:
1103         {
1104           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1105           LIR_Op2* op2 = (LIR_Op2*)op;
1106           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1107             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1108             return shouldHaveRegister;
1109           }
1110         }
1111         default:
1112           break;
1113       }
1114     } else {
1115       // FPU stack float instruction
1116       switch (op->code()) {
1117         case lir_add:
1118         case lir_sub:
1119         case lir_mul:
1120         case lir_div:
1121         {
1122           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1123           LIR_Op2* op2 = (LIR_Op2*)op;
1124           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1125             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1126             return shouldHaveRegister;
1127           }
1128         }
1129         default:
1130           break;
1131       }
1132     }
1133     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1134     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1135     // T_OBJECT doesn't get spilled along with T_LONG.
1136   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1137     // integer instruction (note: long operands must always be in register)
1138     switch (op->code()) {
1139       case lir_cmp:
1140       case lir_add:
1141       case lir_sub:
1142       case lir_logic_and:
1143       case lir_logic_or:
1144       case lir_logic_xor:
1145       {
1146         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1147         LIR_Op2* op2 = (LIR_Op2*)op;
1148         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1149           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1150           return shouldHaveRegister;
1151         }
1152       }
1153       default:
1154         break;
1155     }
1156   }
1157 #endif // X86 || S390
1158 
1159   // all other operands require a register
1160   return mustHaveRegister;
1161 }
1162 
1163 
1164 void LinearScan::handle_method_arguments(LIR_Op* op) {
1165   // special handling for method arguments (moves from stack to virtual register):
1166   // the interval gets no register assigned, but the stack slot.
1167   // it is split before the first use by the register allocator.
1168 
1169   if (op->code() == lir_move) {
1170     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1171     LIR_Op1* move = (LIR_Op1*)op;
1172 
1173     if (move->in_opr()->is_stack()) {
1174 #ifdef ASSERT
1175       int arg_size = compilation()->method()->arg_size();
1176       LIR_Opr o = move->in_opr();
1177       if (o->is_single_stack()) {
1178         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1179       } else if (o->is_double_stack()) {
1180         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1181       } else {
1182         ShouldNotReachHere();
1183       }
1184 
1185       assert(move->id() > 0, "invalid id");
1186       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1187       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1188 
1189       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1190 #endif
1191 
1192       Interval* interval = interval_at(reg_num(move->result_opr()));
1193 
1194       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1195       interval->set_canonical_spill_slot(stack_slot);
1196       interval->assign_reg(stack_slot);
1197     }
1198   }
1199 }
1200 
1201 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1202   // special handling for doubleword move from memory to register:
1203   // in this case the registers of the input address and the result
1204   // registers must not overlap -> add a temp range for the input registers
1205   if (op->code() == lir_move) {
1206     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1207     LIR_Op1* move = (LIR_Op1*)op;
1208 
1209     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1210       LIR_Address* address = move->in_opr()->as_address_ptr();
1211       if (address != NULL) {
1212         if (address->base()->is_valid()) {
1213           add_temp(address->base(), op->id(), noUse);
1214         }
1215         if (address->index()->is_valid()) {
1216           add_temp(address->index(), op->id(), noUse);
1217         }
1218       }
1219     }
1220   }
1221 }
1222 
1223 void LinearScan::add_register_hints(LIR_Op* op) {
1224   switch (op->code()) {
1225     case lir_move:      // fall through
1226     case lir_convert: {
1227       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1228       LIR_Op1* move = (LIR_Op1*)op;
1229 
1230       LIR_Opr move_from = move->in_opr();
1231       LIR_Opr move_to = move->result_opr();
1232 
1233       if (move_to->is_register() && move_from->is_register()) {
1234         Interval* from = interval_at(reg_num(move_from));
1235         Interval* to = interval_at(reg_num(move_to));
1236         if (from != NULL && to != NULL) {
1237           to->set_register_hint(from);
1238           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1239         }
1240       }
1241       break;
1242     }
1243     case lir_cmove: {
1244       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1245       LIR_Op2* cmove = (LIR_Op2*)op;
1246 
1247       LIR_Opr move_from = cmove->in_opr1();
1248       LIR_Opr move_to = cmove->result_opr();
1249 
1250       if (move_to->is_register() && move_from->is_register()) {
1251         Interval* from = interval_at(reg_num(move_from));
1252         Interval* to = interval_at(reg_num(move_to));
1253         if (from != NULL && to != NULL) {
1254           to->set_register_hint(from);
1255           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1256         }
1257       }
1258       break;
1259     }
1260     default:
1261       break;
1262   }
1263 }
1264 
1265 
1266 void LinearScan::build_intervals() {
1267   TIME_LINEAR_SCAN(timer_build_intervals);
1268 
1269   // initialize interval list with expected number of intervals
1270   // (32 is added to have some space for split children without having to resize the list)
1271   _intervals = IntervalList(num_virtual_regs() + 32);
1272   // initialize all slots that are used by build_intervals
1273   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1274 
1275   // create a list with all caller-save registers (cpu, fpu, xmm)
1276   // when an instruction is a call, a temp range is created for all these registers
1277   int num_caller_save_registers = 0;
1278   int caller_save_registers[LinearScan::nof_regs];
1279 
1280   int i;
1281   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1282     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1283     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1284     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1285     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1286   }
1287 
1288   // temp ranges for fpu registers are only created when the method has
1289   // virtual fpu operands. Otherwise no allocation for fpu registers is
1290   // performed and so the temp ranges would be useless
1291   if (has_fpu_registers()) {
1292 #ifdef IA32
1293     if (UseSSE < 2) {
1294 #endif // IA32
1295       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1296         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1297         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1298         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1299         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1300       }
1301 #ifdef IA32
1302     }
1303 #endif// IA32
1304 
1305 #ifdef X86
1306     if (UseSSE > 0) {
1307       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1308       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1309         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1310         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1311         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1312         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1313       }
1314     }
1315 #endif // X86
1316   }
1317   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1318 
1319 
1320   LIR_OpVisitState visitor;
1321 
1322   // iterate all blocks in reverse order
1323   for (i = block_count() - 1; i >= 0; i--) {
1324     BlockBegin* block = block_at(i);
1325     LIR_OpList* instructions = block->lir()->instructions_list();
1326     int         block_from =   block->first_lir_instruction_id();
1327     int         block_to =     block->last_lir_instruction_id();
1328 
1329     assert(block_from == instructions->at(0)->id(), "must be");
1330     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1331 
1332     // Update intervals for registers live at the end of this block;
1333     ResourceBitMap live = block->live_out();
1334     int size = (int)live.size();
1335     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1336       assert(live.at(number), "should not stop here otherwise");
1337       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1338       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1339 
1340       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1341 
1342       // add special use positions for loop-end blocks when the
1343       // interval is used anywhere inside this loop.  It's possible
1344       // that the block was part of a non-natural loop, so it might
1345       // have an invalid loop index.
1346       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1347           block->loop_index() != -1 &&
1348           is_interval_in_loop(number, block->loop_index())) {
1349         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1350       }
1351     }
1352 
1353     // iterate all instructions of the block in reverse order.
1354     // skip the first instruction because it is always a label
1355     // definitions of intervals are processed before uses
1356     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1357     for (int j = instructions->length() - 1; j >= 1; j--) {
1358       LIR_Op* op = instructions->at(j);
1359       int op_id = op->id();
1360 
1361       // visit operation to collect all operands
1362       visitor.visit(op);
1363 
1364       // add a temp range for each register if operation destroys caller-save registers
1365       if (visitor.has_call()) {
1366         for (int k = 0; k < num_caller_save_registers; k++) {
1367           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1368         }
1369         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1370       }
1371 
1372       // Add any platform dependent temps
1373       pd_add_temps(op);
1374 
1375       // visit definitions (output and temp operands)
1376       int k, n;
1377       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1378       for (k = 0; k < n; k++) {
1379         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1380         assert(opr->is_register(), "visitor should only return register operands");
1381         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1382       }
1383 
1384       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1385       for (k = 0; k < n; k++) {
1386         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1387         assert(opr->is_register(), "visitor should only return register operands");
1388         add_temp(opr, op_id, mustHaveRegister);
1389       }
1390 
1391       // visit uses (input operands)
1392       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1393       for (k = 0; k < n; k++) {
1394         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1395         assert(opr->is_register(), "visitor should only return register operands");
1396         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1397       }
1398 
1399       // Add uses of live locals from interpreter's point of view for proper
1400       // debug information generation
1401       // Treat these operands as temp values (if the life range is extended
1402       // to a call site, the value would be in a register at the call otherwise)
1403       n = visitor.info_count();
1404       for (k = 0; k < n; k++) {
1405         CodeEmitInfo* info = visitor.info_at(k);
1406         ValueStack* stack = info->stack();
1407         for_each_state_value(stack, value,
1408           add_use(value, block_from, op_id + 1, noUse);
1409         );
1410       }
1411 
1412       // special steps for some instructions (especially moves)
1413       handle_method_arguments(op);
1414       handle_doubleword_moves(op);
1415       add_register_hints(op);
1416 
1417     } // end of instruction iteration
1418   } // end of block iteration
1419 
1420 
1421   // add the range [0, 1[ to all fixed intervals
1422   // -> the register allocator need not handle unhandled fixed intervals
1423   for (int n = 0; n < LinearScan::nof_regs; n++) {
1424     Interval* interval = interval_at(n);
1425     if (interval != NULL) {
1426       interval->add_range(0, 1);
1427     }
1428   }
1429 }
1430 
1431 
1432 // ********** Phase 5: actual register allocation
1433 
1434 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1435   if (*a != NULL) {
1436     if (*b != NULL) {
1437       return (*a)->from() - (*b)->from();
1438     } else {
1439       return -1;
1440     }
1441   } else {
1442     if (*b != NULL) {
1443       return 1;
1444     } else {
1445       return 0;
1446     }
1447   }
1448 }
1449 
1450 #ifndef PRODUCT
1451 int interval_cmp(Interval* const& l, Interval* const& r) {
1452   return l->from() - r->from();
1453 }
1454 
1455 bool find_interval(Interval* interval, IntervalArray* intervals) {
1456   bool found;
1457   int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1458 
1459   if (!found) {
1460     return false;
1461   }
1462 
1463   int from = interval->from();
1464 
1465   // The index we've found using binary search is pointing to an interval
1466   // that is defined in the same place as the interval we were looking for.
1467   // So now we have to look around that index and find exact interval.
1468   for (int i = idx; i >= 0; i--) {
1469     if (intervals->at(i) == interval) {
1470       return true;
1471     }
1472     if (intervals->at(i)->from() != from) {
1473       break;
1474     }
1475   }
1476 
1477   for (int i = idx + 1; i < intervals->length(); i++) {
1478     if (intervals->at(i) == interval) {
1479       return true;
1480     }
1481     if (intervals->at(i)->from() != from) {
1482       break;
1483     }
1484   }
1485 
1486   return false;
1487 }
1488 
1489 bool LinearScan::is_sorted(IntervalArray* intervals) {
1490   int from = -1;
1491   int null_count = 0;
1492 
1493   for (int i = 0; i < intervals->length(); i++) {
1494     Interval* it = intervals->at(i);
1495     if (it != NULL) {
1496       assert(from <= it->from(), "Intervals are unordered");
1497       from = it->from();
1498     } else {
1499       null_count++;
1500     }
1501   }
1502 
1503   assert(null_count == 0, "Sorted intervals should not contain nulls");
1504 
1505   null_count = 0;
1506 
1507   for (int i = 0; i < interval_count(); i++) {
1508     Interval* interval = interval_at(i);
1509     if (interval != NULL) {
1510       assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1511     } else {
1512       null_count++;
1513     }
1514   }
1515 
1516   assert(interval_count() - null_count == intervals->length(),
1517       "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1518 
1519   return true;
1520 }
1521 #endif
1522 
1523 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1524   if (*prev != NULL) {
1525     (*prev)->set_next(interval);
1526   } else {
1527     *first = interval;
1528   }
1529   *prev = interval;
1530 }
1531 
1532 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1533   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1534 
1535   *list1 = *list2 = Interval::end();
1536 
1537   Interval* list1_prev = NULL;
1538   Interval* list2_prev = NULL;
1539   Interval* v;
1540 
1541   const int n = _sorted_intervals->length();
1542   for (int i = 0; i < n; i++) {
1543     v = _sorted_intervals->at(i);
1544     if (v == NULL) continue;
1545 
1546     if (is_list1(v)) {
1547       add_to_list(list1, &list1_prev, v);
1548     } else if (is_list2 == NULL || is_list2(v)) {
1549       add_to_list(list2, &list2_prev, v);
1550     }
1551   }
1552 
1553   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1554   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1555 
1556   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1557   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1558 }
1559 
1560 
1561 void LinearScan::sort_intervals_before_allocation() {
1562   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1563 
1564   if (_needs_full_resort) {
1565     // There is no known reason why this should occur but just in case...
1566     assert(false, "should never occur");
1567     // Re-sort existing interval list because an Interval::from() has changed
1568     _sorted_intervals->sort(interval_cmp);
1569     _needs_full_resort = false;
1570   }
1571 
1572   IntervalList* unsorted_list = &_intervals;
1573   int unsorted_len = unsorted_list->length();
1574   int sorted_len = 0;
1575   int unsorted_idx;
1576   int sorted_idx = 0;
1577   int sorted_from_max = -1;
1578 
1579   // calc number of items for sorted list (sorted list must not contain NULL values)
1580   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1581     if (unsorted_list->at(unsorted_idx) != NULL) {
1582       sorted_len++;
1583     }
1584   }
1585   IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1586 
1587   // special sorting algorithm: the original interval-list is almost sorted,
1588   // only some intervals are swapped. So this is much faster than a complete QuickSort
1589   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1590     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1591 
1592     if (cur_interval != NULL) {
1593       int cur_from = cur_interval->from();
1594 
1595       if (sorted_from_max <= cur_from) {
1596         sorted_list->at_put(sorted_idx++, cur_interval);
1597         sorted_from_max = cur_interval->from();
1598       } else {
1599         // the asumption that the intervals are already sorted failed,
1600         // so this interval must be sorted in manually
1601         int j;
1602         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1603           sorted_list->at_put(j + 1, sorted_list->at(j));
1604         }
1605         sorted_list->at_put(j + 1, cur_interval);
1606         sorted_idx++;
1607       }
1608     }
1609   }
1610   _sorted_intervals = sorted_list;
1611   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1612 }
1613 
1614 void LinearScan::sort_intervals_after_allocation() {
1615   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1616 
1617   if (_needs_full_resort) {
1618     // Re-sort existing interval list because an Interval::from() has changed
1619     _sorted_intervals->sort(interval_cmp);
1620     _needs_full_resort = false;
1621   }
1622 
1623   IntervalArray* old_list = _sorted_intervals;
1624   IntervalList* new_list = _new_intervals_from_allocation;
1625   int old_len = old_list->length();
1626   int new_len = new_list == NULL ? 0 : new_list->length();
1627 
1628   if (new_len == 0) {
1629     // no intervals have been added during allocation, so sorted list is already up to date
1630     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1631     return;
1632   }
1633 
1634   // conventional sort-algorithm for new intervals
1635   new_list->sort(interval_cmp);
1636 
1637   // merge old and new list (both already sorted) into one combined list
1638   int combined_list_len = old_len + new_len;
1639   IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1640   int old_idx = 0;
1641   int new_idx = 0;
1642 
1643   while (old_idx + new_idx < old_len + new_len) {
1644     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1645       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1646       old_idx++;
1647     } else {
1648       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1649       new_idx++;
1650     }
1651   }
1652 
1653   _sorted_intervals = combined_list;
1654   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1655 }
1656 
1657 
1658 void LinearScan::allocate_registers() {
1659   TIME_LINEAR_SCAN(timer_allocate_registers);
1660 
1661   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1662   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1663 
1664   // allocate cpu registers
1665   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1666                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1667 
1668   // allocate fpu registers
1669   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1670                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1671 
1672   // the fpu interval allocation cannot be moved down below with the fpu section as
1673   // the cpu_lsw.walk() changes interval positions.
1674 
1675   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1676   cpu_lsw.walk();
1677   cpu_lsw.finish_allocation();
1678 
1679   if (has_fpu_registers()) {
1680     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1681     fpu_lsw.walk();
1682     fpu_lsw.finish_allocation();
1683   }
1684 }
1685 
1686 
1687 // ********** Phase 6: resolve data flow
1688 // (insert moves at edges between blocks if intervals have been split)
1689 
1690 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1691 // instead of returning NULL
1692 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1693   Interval* result = interval->split_child_at_op_id(op_id, mode);
1694   if (result != NULL) {
1695     return result;
1696   }
1697 
1698   assert(false, "must find an interval, but do a clean bailout in product mode");
1699   result = new Interval(LIR_OprDesc::vreg_base);
1700   result->assign_reg(0);
1701   result->set_type(T_INT);
1702   BAILOUT_("LinearScan: interval is NULL", result);
1703 }
1704 
1705 
1706 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1707   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1708   assert(interval_at(reg_num) != NULL, "no interval found");
1709 
1710   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1711 }
1712 
1713 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1714   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1715   assert(interval_at(reg_num) != NULL, "no interval found");
1716 
1717   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1718 }
1719 
1720 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1721   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1722   assert(interval_at(reg_num) != NULL, "no interval found");
1723 
1724   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1725 }
1726 
1727 
1728 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1729   DEBUG_ONLY(move_resolver.check_empty());
1730 
1731   const int size = live_set_size();
1732   const ResourceBitMap live_at_edge = to_block->live_in();
1733 
1734   // visit all registers where the live_at_edge bit is set
1735   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1736     assert(r < num_virtual_regs(), "live information set for not exisiting interval");
1737     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1738 
1739     Interval* from_interval = interval_at_block_end(from_block, r);
1740     Interval* to_interval = interval_at_block_begin(to_block, r);
1741 
1742     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1743       // need to insert move instruction
1744       move_resolver.add_mapping(from_interval, to_interval);
1745     }
1746   }
1747 }
1748 
1749 
1750 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1751   if (from_block->number_of_sux() <= 1) {
1752     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1753 
1754     LIR_OpList* instructions = from_block->lir()->instructions_list();
1755     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1756     if (branch != NULL) {
1757       // insert moves before branch
1758       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1759       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1760     } else {
1761       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1762     }
1763 
1764   } else {
1765     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1766 #ifdef ASSERT
1767     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1768 
1769     // because the number of predecessor edges matches the number of
1770     // successor edges, blocks which are reached by switch statements
1771     // may have be more than one predecessor but it will be guaranteed
1772     // that all predecessors will be the same.
1773     for (int i = 0; i < to_block->number_of_preds(); i++) {
1774       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1775     }
1776 #endif
1777 
1778     move_resolver.set_insert_position(to_block->lir(), 0);
1779   }
1780 }
1781 
1782 
1783 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1784 void LinearScan::resolve_data_flow() {
1785   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1786 
1787   int num_blocks = block_count();
1788   MoveResolver move_resolver(this);
1789   ResourceBitMap block_completed(num_blocks);
1790   ResourceBitMap already_resolved(num_blocks);
1791 
1792   int i;
1793   for (i = 0; i < num_blocks; i++) {
1794     BlockBegin* block = block_at(i);
1795 
1796     // check if block has only one predecessor and only one successor
1797     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1798       LIR_OpList* instructions = block->lir()->instructions_list();
1799       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1800       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1801       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1802 
1803       // check if block is empty (only label and branch)
1804       if (instructions->length() == 2) {
1805         BlockBegin* pred = block->pred_at(0);
1806         BlockBegin* sux = block->sux_at(0);
1807 
1808         // prevent optimization of two consecutive blocks
1809         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1810           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1811           block_completed.set_bit(block->linear_scan_number());
1812 
1813           // directly resolve between pred and sux (without looking at the empty block between)
1814           resolve_collect_mappings(pred, sux, move_resolver);
1815           if (move_resolver.has_mappings()) {
1816             move_resolver.set_insert_position(block->lir(), 0);
1817             move_resolver.resolve_and_append_moves();
1818           }
1819         }
1820       }
1821     }
1822   }
1823 
1824 
1825   for (i = 0; i < num_blocks; i++) {
1826     if (!block_completed.at(i)) {
1827       BlockBegin* from_block = block_at(i);
1828       already_resolved.set_from(block_completed);
1829 
1830       int num_sux = from_block->number_of_sux();
1831       for (int s = 0; s < num_sux; s++) {
1832         BlockBegin* to_block = from_block->sux_at(s);
1833 
1834         // check for duplicate edges between the same blocks (can happen with switch blocks)
1835         if (!already_resolved.at(to_block->linear_scan_number())) {
1836           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1837           already_resolved.set_bit(to_block->linear_scan_number());
1838 
1839           // collect all intervals that have been split between from_block and to_block
1840           resolve_collect_mappings(from_block, to_block, move_resolver);
1841           if (move_resolver.has_mappings()) {
1842             resolve_find_insert_pos(from_block, to_block, move_resolver);
1843             move_resolver.resolve_and_append_moves();
1844           }
1845         }
1846       }
1847     }
1848   }
1849 }
1850 
1851 
1852 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1853   if (interval_at(reg_num) == NULL) {
1854     // if a phi function is never used, no interval is created -> ignore this
1855     return;
1856   }
1857 
1858   Interval* interval = interval_at_block_begin(block, reg_num);
1859   int reg = interval->assigned_reg();
1860   int regHi = interval->assigned_regHi();
1861 
1862   if ((reg < nof_regs && interval->always_in_memory()) ||
1863       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1864     // the interval is split to get a short range that is located on the stack
1865     // in the following two cases:
1866     // * the interval started in memory (e.g. method parameter), but is currently in a register
1867     //   this is an optimization for exception handling that reduces the number of moves that
1868     //   are necessary for resolving the states when an exception uses this exception handler
1869     // * the interval would be on the fpu stack at the begin of the exception handler
1870     //   this is not allowed because of the complicated fpu stack handling on Intel
1871 
1872     // range that will be spilled to memory
1873     int from_op_id = block->first_lir_instruction_id();
1874     int to_op_id = from_op_id + 1;  // short live range of length 1
1875     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1876            "no split allowed between exception entry and first instruction");
1877 
1878     if (interval->from() != from_op_id) {
1879       // the part before from_op_id is unchanged
1880       interval = interval->split(from_op_id);
1881       interval->assign_reg(reg, regHi);
1882       append_interval(interval);
1883     } else {
1884       _needs_full_resort = true;
1885     }
1886     assert(interval->from() == from_op_id, "must be true now");
1887 
1888     Interval* spilled_part = interval;
1889     if (interval->to() != to_op_id) {
1890       // the part after to_op_id is unchanged
1891       spilled_part = interval->split_from_start(to_op_id);
1892       append_interval(spilled_part);
1893       move_resolver.add_mapping(spilled_part, interval);
1894     }
1895     assign_spill_slot(spilled_part);
1896 
1897     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1898   }
1899 }
1900 
1901 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1902   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1903   DEBUG_ONLY(move_resolver.check_empty());
1904 
1905   // visit all registers where the live_in bit is set
1906   int size = live_set_size();
1907   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1908     resolve_exception_entry(block, r, move_resolver);
1909   }
1910 
1911   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1912   for_each_phi_fun(block, phi,
1913     if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1914   );
1915 
1916   if (move_resolver.has_mappings()) {
1917     // insert moves after first instruction
1918     move_resolver.set_insert_position(block->lir(), 0);
1919     move_resolver.resolve_and_append_moves();
1920   }
1921 }
1922 
1923 
1924 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1925   if (interval_at(reg_num) == NULL) {
1926     // if a phi function is never used, no interval is created -> ignore this
1927     return;
1928   }
1929 
1930   // the computation of to_interval is equal to resolve_collect_mappings,
1931   // but from_interval is more complicated because of phi functions
1932   BlockBegin* to_block = handler->entry_block();
1933   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1934 
1935   if (phi != NULL) {
1936     // phi function of the exception entry block
1937     // no moves are created for this phi function in the LIR_Generator, so the
1938     // interval at the throwing instruction must be searched using the operands
1939     // of the phi function
1940     Value from_value = phi->operand_at(handler->phi_operand());
1941 
1942     // with phi functions it can happen that the same from_value is used in
1943     // multiple mappings, so notify move-resolver that this is allowed
1944     move_resolver.set_multiple_reads_allowed();
1945 
1946     Constant* con = from_value->as_Constant();
1947     if (con != NULL && !con->is_pinned()) {
1948       // unpinned constants may have no register, so add mapping from constant to interval
1949       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1950     } else {
1951       // search split child at the throwing op_id
1952       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1953       move_resolver.add_mapping(from_interval, to_interval);
1954     }
1955 
1956   } else {
1957     // no phi function, so use reg_num also for from_interval
1958     // search split child at the throwing op_id
1959     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1960     if (from_interval != to_interval) {
1961       // optimization to reduce number of moves: when to_interval is on stack and
1962       // the stack slot is known to be always correct, then no move is necessary
1963       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1964         move_resolver.add_mapping(from_interval, to_interval);
1965       }
1966     }
1967   }
1968 }
1969 
1970 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1971   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1972 
1973   DEBUG_ONLY(move_resolver.check_empty());
1974   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1975   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1976   assert(handler->entry_code() == NULL, "code already present");
1977 
1978   // visit all registers where the live_in bit is set
1979   BlockBegin* block = handler->entry_block();
1980   int size = live_set_size();
1981   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1982     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1983   }
1984 
1985   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1986   for_each_phi_fun(block, phi,
1987     if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
1988   );
1989 
1990   if (move_resolver.has_mappings()) {
1991     LIR_List* entry_code = new LIR_List(compilation());
1992     move_resolver.set_insert_position(entry_code, 0);
1993     move_resolver.resolve_and_append_moves();
1994 
1995     entry_code->jump(handler->entry_block());
1996     handler->set_entry_code(entry_code);
1997   }
1998 }
1999 
2000 
2001 void LinearScan::resolve_exception_handlers() {
2002   MoveResolver move_resolver(this);
2003   LIR_OpVisitState visitor;
2004   int num_blocks = block_count();
2005 
2006   int i;
2007   for (i = 0; i < num_blocks; i++) {
2008     BlockBegin* block = block_at(i);
2009     if (block->is_set(BlockBegin::exception_entry_flag)) {
2010       resolve_exception_entry(block, move_resolver);
2011     }
2012   }
2013 
2014   for (i = 0; i < num_blocks; i++) {
2015     BlockBegin* block = block_at(i);
2016     LIR_List* ops = block->lir();
2017     int num_ops = ops->length();
2018 
2019     // iterate all instructions of the block. skip the first because it is always a label
2020     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2021     for (int j = 1; j < num_ops; j++) {
2022       LIR_Op* op = ops->at(j);
2023       int op_id = op->id();
2024 
2025       if (op_id != -1 && has_info(op_id)) {
2026         // visit operation to collect all operands
2027         visitor.visit(op);
2028         assert(visitor.info_count() > 0, "should not visit otherwise");
2029 
2030         XHandlers* xhandlers = visitor.all_xhandler();
2031         int n = xhandlers->length();
2032         for (int k = 0; k < n; k++) {
2033           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2034         }
2035 
2036 #ifdef ASSERT
2037       } else {
2038         visitor.visit(op);
2039         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2040 #endif
2041       }
2042     }
2043   }
2044 }
2045 
2046 
2047 // ********** Phase 7: assign register numbers back to LIR
2048 // (includes computation of debug information and oop maps)
2049 
2050 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2051   VMReg reg = interval->cached_vm_reg();
2052   if (!reg->is_valid() ) {
2053     reg = vm_reg_for_operand(operand_for_interval(interval));
2054     interval->set_cached_vm_reg(reg);
2055   }
2056   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2057   return reg;
2058 }
2059 
2060 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2061   assert(opr->is_oop(), "currently only implemented for oop operands");
2062   return frame_map()->regname(opr);
2063 }
2064 
2065 
2066 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2067   LIR_Opr opr = interval->cached_opr();
2068   if (opr->is_illegal()) {
2069     opr = calc_operand_for_interval(interval);
2070     interval->set_cached_opr(opr);
2071   }
2072 
2073   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2074   return opr;
2075 }
2076 
2077 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2078   int assigned_reg = interval->assigned_reg();
2079   BasicType type = interval->type();
2080 
2081   if (assigned_reg >= nof_regs) {
2082     // stack slot
2083     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2084     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2085 
2086   } else {
2087     // register
2088     switch (type) {
2089       case T_OBJECT: {
2090         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2091         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2092         return LIR_OprFact::single_cpu_oop(assigned_reg);
2093       }
2094 
2095       case T_ADDRESS: {
2096         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2097         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2098         return LIR_OprFact::single_cpu_address(assigned_reg);
2099       }
2100 
2101       case T_METADATA: {
2102         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2103         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2104         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2105       }
2106 
2107 #ifdef __SOFTFP__
2108       case T_FLOAT:  // fall through
2109 #endif // __SOFTFP__
2110       case T_INT: {
2111         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2112         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2113         return LIR_OprFact::single_cpu(assigned_reg);
2114       }
2115 
2116 #ifdef __SOFTFP__
2117       case T_DOUBLE:  // fall through
2118 #endif // __SOFTFP__
2119       case T_LONG: {
2120         int assigned_regHi = interval->assigned_regHi();
2121         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2122         assert(num_physical_regs(T_LONG) == 1 ||
2123                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2124 
2125         assert(assigned_reg != assigned_regHi, "invalid allocation");
2126         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2127                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2128         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2129         if (requires_adjacent_regs(T_LONG)) {
2130           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2131         }
2132 
2133 #ifdef _LP64
2134         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2135 #else
2136 #if defined(SPARC) || defined(PPC32)
2137         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2138 #else
2139         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2140 #endif // SPARC
2141 #endif // LP64
2142       }
2143 
2144 #ifndef __SOFTFP__
2145       case T_FLOAT: {
2146 #ifdef X86
2147         if (UseSSE >= 1) {
2148           int last_xmm_reg = pd_last_xmm_reg;
2149 #ifdef _LP64
2150           if (UseAVX < 3) {
2151             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2152           }
2153 #endif
2154           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2155           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2156           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2157         }
2158 #endif
2159 
2160         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2161         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2162         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2163       }
2164 
2165       case T_DOUBLE: {
2166 #ifdef X86
2167         if (UseSSE >= 2) {
2168           int last_xmm_reg = pd_last_xmm_reg;
2169 #ifdef _LP64
2170           if (UseAVX < 3) {
2171             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2172           }
2173 #endif
2174           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2175           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2176           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2177         }
2178 #endif
2179 
2180 #ifdef SPARC
2181         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2182         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2183         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2184         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2185 #elif defined(ARM32)
2186         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2187         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2188         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2189         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2190 #else
2191         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2192         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2193         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2194 #endif
2195         return result;
2196       }
2197 #endif // __SOFTFP__
2198 
2199       default: {
2200         ShouldNotReachHere();
2201         return LIR_OprFact::illegalOpr;
2202       }
2203     }
2204   }
2205 }
2206 
2207 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2208   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2209   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2210 }
2211 
2212 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2213   assert(opr->is_virtual(), "should not call this otherwise");
2214 
2215   Interval* interval = interval_at(opr->vreg_number());
2216   assert(interval != NULL, "interval must exist");
2217 
2218   if (op_id != -1) {
2219 #ifdef ASSERT
2220     BlockBegin* block = block_of_op_with_id(op_id);
2221     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2222       // check if spill moves could have been appended at the end of this block, but
2223       // before the branch instruction. So the split child information for this branch would
2224       // be incorrect.
2225       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2226       if (branch != NULL) {
2227         if (block->live_out().at(opr->vreg_number())) {
2228           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2229           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2230         }
2231       }
2232     }
2233 #endif
2234 
2235     // operands are not changed when an interval is split during allocation,
2236     // so search the right interval here
2237     interval = split_child_at_op_id(interval, op_id, mode);
2238   }
2239 
2240   LIR_Opr res = operand_for_interval(interval);
2241 
2242 #ifdef X86
2243   // new semantic for is_last_use: not only set on definite end of interval,
2244   // but also before hole
2245   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2246   // last use information is completely correct
2247   // information is only needed for fpu stack allocation
2248   if (res->is_fpu_register()) {
2249     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2250       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2251       res = res->make_last_use();
2252     }
2253   }
2254 #endif
2255 
2256   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2257 
2258   return res;
2259 }
2260 
2261 
2262 #ifdef ASSERT
2263 // some methods used to check correctness of debug information
2264 
2265 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2266   if (values == NULL) {
2267     return;
2268   }
2269 
2270   for (int i = 0; i < values->length(); i++) {
2271     ScopeValue* value = values->at(i);
2272 
2273     if (value->is_location()) {
2274       Location location = ((LocationValue*)value)->location();
2275       assert(location.where() == Location::on_stack, "value is in register");
2276     }
2277   }
2278 }
2279 
2280 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2281   if (values == NULL) {
2282     return;
2283   }
2284 
2285   for (int i = 0; i < values->length(); i++) {
2286     MonitorValue* value = values->at(i);
2287 
2288     if (value->owner()->is_location()) {
2289       Location location = ((LocationValue*)value->owner())->location();
2290       assert(location.where() == Location::on_stack, "owner is in register");
2291     }
2292     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2293   }
2294 }
2295 
2296 void assert_equal(Location l1, Location l2) {
2297   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2298 }
2299 
2300 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2301   if (v1->is_location()) {
2302     assert(v2->is_location(), "");
2303     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2304   } else if (v1->is_constant_int()) {
2305     assert(v2->is_constant_int(), "");
2306     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2307   } else if (v1->is_constant_double()) {
2308     assert(v2->is_constant_double(), "");
2309     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2310   } else if (v1->is_constant_long()) {
2311     assert(v2->is_constant_long(), "");
2312     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2313   } else if (v1->is_constant_oop()) {
2314     assert(v2->is_constant_oop(), "");
2315     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2316   } else {
2317     ShouldNotReachHere();
2318   }
2319 }
2320 
2321 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2322   assert_equal(m1->owner(), m2->owner());
2323   assert_equal(m1->basic_lock(), m2->basic_lock());
2324 }
2325 
2326 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2327   assert(d1->scope() == d2->scope(), "not equal");
2328   assert(d1->bci() == d2->bci(), "not equal");
2329 
2330   if (d1->locals() != NULL) {
2331     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2332     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2333     for (int i = 0; i < d1->locals()->length(); i++) {
2334       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2335     }
2336   } else {
2337     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2338   }
2339 
2340   if (d1->expressions() != NULL) {
2341     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2342     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2343     for (int i = 0; i < d1->expressions()->length(); i++) {
2344       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2345     }
2346   } else {
2347     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2348   }
2349 
2350   if (d1->monitors() != NULL) {
2351     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2352     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2353     for (int i = 0; i < d1->monitors()->length(); i++) {
2354       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2355     }
2356   } else {
2357     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2358   }
2359 
2360   if (d1->caller() != NULL) {
2361     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2362     assert_equal(d1->caller(), d2->caller());
2363   } else {
2364     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2365   }
2366 }
2367 
2368 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2369   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2370     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2371     switch (code) {
2372       case Bytecodes::_ifnull    : // fall through
2373       case Bytecodes::_ifnonnull : // fall through
2374       case Bytecodes::_ifeq      : // fall through
2375       case Bytecodes::_ifne      : // fall through
2376       case Bytecodes::_iflt      : // fall through
2377       case Bytecodes::_ifge      : // fall through
2378       case Bytecodes::_ifgt      : // fall through
2379       case Bytecodes::_ifle      : // fall through
2380       case Bytecodes::_if_icmpeq : // fall through
2381       case Bytecodes::_if_icmpne : // fall through
2382       case Bytecodes::_if_icmplt : // fall through
2383       case Bytecodes::_if_icmpge : // fall through
2384       case Bytecodes::_if_icmpgt : // fall through
2385       case Bytecodes::_if_icmple : // fall through
2386       case Bytecodes::_if_acmpeq : // fall through
2387       case Bytecodes::_if_acmpne :
2388         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2389         break;
2390       default:
2391         break;
2392     }
2393   }
2394 }
2395 
2396 #endif // ASSERT
2397 
2398 
2399 IntervalWalker* LinearScan::init_compute_oop_maps() {
2400   // setup lists of potential oops for walking
2401   Interval* oop_intervals;
2402   Interval* non_oop_intervals;
2403 
2404   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2405 
2406   // intervals that have no oops inside need not to be processed
2407   // to ensure a walking until the last instruction id, add a dummy interval
2408   // with a high operation id
2409   non_oop_intervals = new Interval(any_reg);
2410   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2411 
2412   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2413 }
2414 
2415 
2416 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2417   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2418 
2419   // walk before the current operation -> intervals that start at
2420   // the operation (= output operands of the operation) are not
2421   // included in the oop map
2422   iw->walk_before(op->id());
2423 
2424   int frame_size = frame_map()->framesize();
2425   int arg_count = frame_map()->oop_map_arg_count();
2426   OopMap* map = new OopMap(frame_size, arg_count);
2427 
2428   // Iterate through active intervals
2429   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2430     int assigned_reg = interval->assigned_reg();
2431 
2432     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2433     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2434     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2435 
2436     // Check if this range covers the instruction. Intervals that
2437     // start or end at the current operation are not included in the
2438     // oop map, except in the case of patching moves.  For patching
2439     // moves, any intervals which end at this instruction are included
2440     // in the oop map since we may safepoint while doing the patch
2441     // before we've consumed the inputs.
2442     if (op->is_patching() || op->id() < interval->current_to()) {
2443 
2444       // caller-save registers must not be included into oop-maps at calls
2445       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2446 
2447       VMReg name = vm_reg_for_interval(interval);
2448       set_oop(map, name);
2449 
2450       // Spill optimization: when the stack value is guaranteed to be always correct,
2451       // then it must be added to the oop map even if the interval is currently in a register
2452       if (interval->always_in_memory() &&
2453           op->id() > interval->spill_definition_pos() &&
2454           interval->assigned_reg() != interval->canonical_spill_slot()) {
2455         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2456         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2457         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2458 
2459         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2460       }
2461     }
2462   }
2463 
2464   // add oops from lock stack
2465   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2466   int locks_count = info->stack()->total_locks_size();
2467   for (int i = 0; i < locks_count; i++) {
2468     set_oop(map, frame_map()->monitor_object_regname(i));
2469   }
2470 
2471   return map;
2472 }
2473 
2474 
2475 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2476   assert(visitor.info_count() > 0, "no oop map needed");
2477 
2478   // compute oop_map only for first CodeEmitInfo
2479   // because it is (in most cases) equal for all other infos of the same operation
2480   CodeEmitInfo* first_info = visitor.info_at(0);
2481   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2482 
2483   for (int i = 0; i < visitor.info_count(); i++) {
2484     CodeEmitInfo* info = visitor.info_at(i);
2485     OopMap* oop_map = first_oop_map;
2486 
2487     // compute worst case interpreter size in case of a deoptimization
2488     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2489 
2490     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2491       // this info has a different number of locks then the precomputed oop map
2492       // (possible for lock and unlock instructions) -> compute oop map with
2493       // correct lock information
2494       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2495     }
2496 
2497     if (info->_oop_map == NULL) {
2498       info->_oop_map = oop_map;
2499     } else {
2500       // a CodeEmitInfo can not be shared between different LIR-instructions
2501       // because interval splitting can occur anywhere between two instructions
2502       // and so the oop maps must be different
2503       // -> check if the already set oop_map is exactly the one calculated for this operation
2504       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2505     }
2506   }
2507 }
2508 
2509 
2510 // frequently used constants
2511 // Allocate them with new so they are never destroyed (otherwise, a
2512 // forced exit could destroy these objects while they are still in
2513 // use).
2514 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2515 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2516 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue((jint)0);
2517 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2518 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2519 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2520 
2521 void LinearScan::init_compute_debug_info() {
2522   // cache for frequently used scope values
2523   // (cpu registers and stack slots)
2524   int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2525   _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2526 }
2527 
2528 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2529   Location loc;
2530   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2531     bailout("too large frame");
2532   }
2533   ScopeValue* object_scope_value = new LocationValue(loc);
2534 
2535   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2536     bailout("too large frame");
2537   }
2538   return new MonitorValue(object_scope_value, loc);
2539 }
2540 
2541 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2542   Location loc;
2543   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2544     bailout("too large frame");
2545   }
2546   return new LocationValue(loc);
2547 }
2548 
2549 
2550 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2551   assert(opr->is_constant(), "should not be called otherwise");
2552 
2553   LIR_Const* c = opr->as_constant_ptr();
2554   BasicType t = c->type();
2555   switch (t) {
2556     case T_OBJECT: {
2557       jobject value = c->as_jobject();
2558       if (value == NULL) {
2559         scope_values->append(_oop_null_scope_value);
2560       } else {
2561         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2562       }
2563       return 1;
2564     }
2565 
2566     case T_INT: // fall through
2567     case T_FLOAT: {
2568       int value = c->as_jint_bits();
2569       switch (value) {
2570         case -1: scope_values->append(_int_m1_scope_value); break;
2571         case 0:  scope_values->append(_int_0_scope_value); break;
2572         case 1:  scope_values->append(_int_1_scope_value); break;
2573         case 2:  scope_values->append(_int_2_scope_value); break;
2574         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2575       }
2576       return 1;
2577     }
2578 
2579     case T_LONG: // fall through
2580     case T_DOUBLE: {
2581 #ifdef _LP64
2582       scope_values->append(_int_0_scope_value);
2583       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2584 #else
2585       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2586         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2587         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2588       } else {
2589         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2590         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2591       }
2592 #endif
2593       return 2;
2594     }
2595 
2596     case T_ADDRESS: {
2597 #ifdef _LP64
2598       scope_values->append(new ConstantLongValue(c->as_jint()));
2599 #else
2600       scope_values->append(new ConstantIntValue(c->as_jint()));
2601 #endif
2602       return 1;
2603     }
2604 
2605     default:
2606       ShouldNotReachHere();
2607       return -1;
2608   }
2609 }
2610 
2611 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2612   if (opr->is_single_stack()) {
2613     int stack_idx = opr->single_stack_ix();
2614     bool is_oop = opr->is_oop_register();
2615     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2616 
2617     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2618     if (sv == NULL) {
2619       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2620       sv = location_for_name(stack_idx, loc_type);
2621       _scope_value_cache.at_put(cache_idx, sv);
2622     }
2623 
2624     // check if cached value is correct
2625     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2626 
2627     scope_values->append(sv);
2628     return 1;
2629 
2630   } else if (opr->is_single_cpu()) {
2631     bool is_oop = opr->is_oop_register();
2632     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2633     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2634 
2635     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2636     if (sv == NULL) {
2637       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2638       VMReg rname = frame_map()->regname(opr);
2639       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2640       _scope_value_cache.at_put(cache_idx, sv);
2641     }
2642 
2643     // check if cached value is correct
2644     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2645 
2646     scope_values->append(sv);
2647     return 1;
2648 
2649 #ifdef X86
2650   } else if (opr->is_single_xmm()) {
2651     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2652     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2653 
2654     scope_values->append(sv);
2655     return 1;
2656 #endif
2657 
2658   } else if (opr->is_single_fpu()) {
2659 #ifdef IA32
2660     // the exact location of fpu stack values is only known
2661     // during fpu stack allocation, so the stack allocator object
2662     // must be present
2663     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2664     assert(_fpu_stack_allocator != NULL, "must be present");
2665     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2666 #elif defined(AMD64)
2667     assert(false, "FPU not used on x86-64");
2668 #endif
2669 
2670     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2671     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2672 #ifndef __SOFTFP__
2673 #ifndef VM_LITTLE_ENDIAN
2674     // On S390 a (single precision) float value occupies only the high
2675     // word of the full double register. So when the double register is
2676     // stored to memory (e.g. by the RegisterSaver), then the float value
2677     // is found at offset 0. I.e. the code below is not needed on S390.
2678 #ifndef S390
2679     if (! float_saved_as_double) {
2680       // On big endian system, we may have an issue if float registers use only
2681       // the low half of the (same) double registers.
2682       // Both the float and the double could have the same regnr but would correspond
2683       // to two different addresses once saved.
2684 
2685       // get next safely (no assertion checks)
2686       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2687       if (next->is_reg() &&
2688           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2689         // the back-end does use the same numbering for the double and the float
2690         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2691       }
2692     }
2693 #endif // !S390
2694 #endif
2695 #endif
2696     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2697 
2698     scope_values->append(sv);
2699     return 1;
2700 
2701   } else {
2702     // double-size operands
2703 
2704     ScopeValue* first;
2705     ScopeValue* second;
2706 
2707     if (opr->is_double_stack()) {
2708 #ifdef _LP64
2709       Location loc1;
2710       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2711       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2712         bailout("too large frame");
2713       }
2714       // Does this reverse on x86 vs. sparc?
2715       first =  new LocationValue(loc1);
2716       second = _int_0_scope_value;
2717 #else
2718       Location loc1, loc2;
2719       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2720         bailout("too large frame");
2721       }
2722       first =  new LocationValue(loc1);
2723       second = new LocationValue(loc2);
2724 #endif // _LP64
2725 
2726     } else if (opr->is_double_cpu()) {
2727 #ifdef _LP64
2728       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2729       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2730       second = _int_0_scope_value;
2731 #else
2732       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2733       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2734 
2735       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2736         // lo/hi and swapped relative to first and second, so swap them
2737         VMReg tmp = rname_first;
2738         rname_first = rname_second;
2739         rname_second = tmp;
2740       }
2741 
2742       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2743       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2744 #endif //_LP64
2745 
2746 
2747 #ifdef X86
2748     } else if (opr->is_double_xmm()) {
2749       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2750       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2751 #  ifdef _LP64
2752       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2753       second = _int_0_scope_value;
2754 #  else
2755       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2756       // %%% This is probably a waste but we'll keep things as they were for now
2757       if (true) {
2758         VMReg rname_second = rname_first->next();
2759         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2760       }
2761 #  endif
2762 #endif
2763 
2764     } else if (opr->is_double_fpu()) {
2765       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2766       // the double as float registers in the native ordering. On X86,
2767       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2768       // the low-order word of the double and fpu_regnrLo + 1 is the
2769       // name for the other half.  *first and *second must represent the
2770       // least and most significant words, respectively.
2771 
2772 #ifdef IA32
2773       // the exact location of fpu stack values is only known
2774       // during fpu stack allocation, so the stack allocator object
2775       // must be present
2776       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2777       assert(_fpu_stack_allocator != NULL, "must be present");
2778       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2779 
2780       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2781 #endif
2782 #ifdef AMD64
2783       assert(false, "FPU not used on x86-64");
2784 #endif
2785 #ifdef SPARC
2786       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2787 #endif
2788 #ifdef ARM32
2789       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2790 #endif
2791 #ifdef PPC32
2792       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2793 #endif
2794 
2795 #ifdef VM_LITTLE_ENDIAN
2796       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2797 #else
2798       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2799 #endif
2800 
2801 #ifdef _LP64
2802       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2803       second = _int_0_scope_value;
2804 #else
2805       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2806       // %%% This is probably a waste but we'll keep things as they were for now
2807       if (true) {
2808         VMReg rname_second = rname_first->next();
2809         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2810       }
2811 #endif
2812 
2813     } else {
2814       ShouldNotReachHere();
2815       first = NULL;
2816       second = NULL;
2817     }
2818 
2819     assert(first != NULL && second != NULL, "must be set");
2820     // The convention the interpreter uses is that the second local
2821     // holds the first raw word of the native double representation.
2822     // This is actually reasonable, since locals and stack arrays
2823     // grow downwards in all implementations.
2824     // (If, on some machine, the interpreter's Java locals or stack
2825     // were to grow upwards, the embedded doubles would be word-swapped.)
2826     scope_values->append(second);
2827     scope_values->append(first);
2828     return 2;
2829   }
2830 }
2831 
2832 
2833 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2834   if (value != NULL) {
2835     LIR_Opr opr = value->operand();
2836     Constant* con = value->as_Constant();
2837 
2838     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2839     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2840 
2841     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2842       // Unpinned constants may have a virtual operand for a part of the lifetime
2843       // or may be illegal when it was optimized away,
2844       // so always use a constant operand
2845       opr = LIR_OprFact::value_type(con->type());
2846     }
2847     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2848 
2849     if (opr->is_virtual()) {
2850       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2851 
2852       BlockBegin* block = block_of_op_with_id(op_id);
2853       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2854         // generating debug information for the last instruction of a block.
2855         // if this instruction is a branch, spill moves are inserted before this branch
2856         // and so the wrong operand would be returned (spill moves at block boundaries are not
2857         // considered in the live ranges of intervals)
2858         // Solution: use the first op_id of the branch target block instead.
2859         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2860           if (block->live_out().at(opr->vreg_number())) {
2861             op_id = block->sux_at(0)->first_lir_instruction_id();
2862             mode = LIR_OpVisitState::outputMode;
2863           }
2864         }
2865       }
2866 
2867       // Get current location of operand
2868       // The operand must be live because debug information is considered when building the intervals
2869       // if the interval is not live, color_lir_opr will cause an assertion failure
2870       opr = color_lir_opr(opr, op_id, mode);
2871       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2872 
2873       // Append to ScopeValue array
2874       return append_scope_value_for_operand(opr, scope_values);
2875 
2876     } else {
2877       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2878       assert(opr->is_constant(), "operand must be constant");
2879 
2880       return append_scope_value_for_constant(opr, scope_values);
2881     }
2882   } else {
2883     // append a dummy value because real value not needed
2884     scope_values->append(_illegal_value);
2885     return 1;
2886   }
2887 }
2888 
2889 
2890 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2891   IRScopeDebugInfo* caller_debug_info = NULL;
2892 
2893   ValueStack* caller_state = cur_state->caller_state();
2894   if (caller_state != NULL) {
2895     // process recursively to compute outermost scope first
2896     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2897   }
2898 
2899   // initialize these to null.
2900   // If we don't need deopt info or there are no locals, expressions or monitors,
2901   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2902   GrowableArray<ScopeValue*>*   locals      = NULL;
2903   GrowableArray<ScopeValue*>*   expressions = NULL;
2904   GrowableArray<MonitorValue*>* monitors    = NULL;
2905 
2906   // describe local variable values
2907   int nof_locals = cur_state->locals_size();
2908   if (nof_locals > 0) {
2909     locals = new GrowableArray<ScopeValue*>(nof_locals);
2910 
2911     int pos = 0;
2912     while (pos < nof_locals) {
2913       assert(pos < cur_state->locals_size(), "why not?");
2914 
2915       Value local = cur_state->local_at(pos);
2916       pos += append_scope_value(op_id, local, locals);
2917 
2918       assert(locals->length() == pos, "must match");
2919     }
2920     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2921     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2922   } else if (cur_scope->method()->max_locals() > 0) {
2923     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2924     nof_locals = cur_scope->method()->max_locals();
2925     locals = new GrowableArray<ScopeValue*>(nof_locals);
2926     for(int i = 0; i < nof_locals; i++) {
2927       locals->append(_illegal_value);
2928     }
2929   }
2930 
2931   // describe expression stack
2932   int nof_stack = cur_state->stack_size();
2933   if (nof_stack > 0) {
2934     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2935 
2936     int pos = 0;
2937     while (pos < nof_stack) {
2938       Value expression = cur_state->stack_at_inc(pos);
2939       append_scope_value(op_id, expression, expressions);
2940 
2941       assert(expressions->length() == pos, "must match");
2942     }
2943     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2944   }
2945 
2946   // describe monitors
2947   int nof_locks = cur_state->locks_size();
2948   if (nof_locks > 0) {
2949     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2950     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2951     for (int i = 0; i < nof_locks; i++) {
2952       monitors->append(location_for_monitor_index(lock_offset + i));
2953     }
2954   }
2955 
2956   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2957 }
2958 
2959 
2960 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2961   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2962 
2963   IRScope* innermost_scope = info->scope();
2964   ValueStack* innermost_state = info->stack();
2965 
2966   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2967 
2968   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2969 
2970   if (info->_scope_debug_info == NULL) {
2971     // compute debug information
2972     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2973   } else {
2974     // debug information already set. Check that it is correct from the current point of view
2975     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2976   }
2977 }
2978 
2979 
2980 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2981   LIR_OpVisitState visitor;
2982   int num_inst = instructions->length();
2983   bool has_dead = false;
2984 
2985   for (int j = 0; j < num_inst; j++) {
2986     LIR_Op* op = instructions->at(j);
2987     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2988       has_dead = true;
2989       continue;
2990     }
2991     int op_id = op->id();
2992 
2993     // visit instruction to get list of operands
2994     visitor.visit(op);
2995 
2996     // iterate all modes of the visitor and process all virtual operands
2997     for_each_visitor_mode(mode) {
2998       int n = visitor.opr_count(mode);
2999       for (int k = 0; k < n; k++) {
3000         LIR_Opr opr = visitor.opr_at(mode, k);
3001         if (opr->is_virtual_register()) {
3002           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
3003         }
3004       }
3005     }
3006 
3007     if (visitor.info_count() > 0) {
3008       // exception handling
3009       if (compilation()->has_exception_handlers()) {
3010         XHandlers* xhandlers = visitor.all_xhandler();
3011         int n = xhandlers->length();
3012         for (int k = 0; k < n; k++) {
3013           XHandler* handler = xhandlers->handler_at(k);
3014           if (handler->entry_code() != NULL) {
3015             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3016           }
3017         }
3018       } else {
3019         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3020       }
3021 
3022       // compute oop map
3023       assert(iw != NULL, "needed for compute_oop_map");
3024       compute_oop_map(iw, visitor, op);
3025 
3026       // compute debug information
3027       if (!use_fpu_stack_allocation()) {
3028         // compute debug information if fpu stack allocation is not needed.
3029         // when fpu stack allocation is needed, the debug information can not
3030         // be computed here because the exact location of fpu operands is not known
3031         // -> debug information is created inside the fpu stack allocator
3032         int n = visitor.info_count();
3033         for (int k = 0; k < n; k++) {
3034           compute_debug_info(visitor.info_at(k), op_id);
3035         }
3036       }
3037     }
3038 
3039 #ifdef ASSERT
3040     // make sure we haven't made the op invalid.
3041     op->verify();
3042 #endif
3043 
3044     // remove useless moves
3045     if (op->code() == lir_move) {
3046       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3047       LIR_Op1* move = (LIR_Op1*)op;
3048       LIR_Opr src = move->in_opr();
3049       LIR_Opr dst = move->result_opr();
3050       if (dst == src ||
3051           (!dst->is_pointer() && !src->is_pointer() &&
3052            src->is_same_register(dst))) {
3053         instructions->at_put(j, NULL);
3054         has_dead = true;
3055       }
3056     }
3057   }
3058 
3059   if (has_dead) {
3060     // iterate all instructions of the block and remove all null-values.
3061     int insert_point = 0;
3062     for (int j = 0; j < num_inst; j++) {
3063       LIR_Op* op = instructions->at(j);
3064       if (op != NULL) {
3065         if (insert_point != j) {
3066           instructions->at_put(insert_point, op);
3067         }
3068         insert_point++;
3069       }
3070     }
3071     instructions->trunc_to(insert_point);
3072   }
3073 }
3074 
3075 void LinearScan::assign_reg_num() {
3076   TIME_LINEAR_SCAN(timer_assign_reg_num);
3077 
3078   init_compute_debug_info();
3079   IntervalWalker* iw = init_compute_oop_maps();
3080 
3081   int num_blocks = block_count();
3082   for (int i = 0; i < num_blocks; i++) {
3083     BlockBegin* block = block_at(i);
3084     assign_reg_num(block->lir()->instructions_list(), iw);
3085   }
3086 }
3087 
3088 
3089 void LinearScan::do_linear_scan() {
3090   NOT_PRODUCT(_total_timer.begin_method());
3091 
3092   number_instructions();
3093 
3094   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3095 
3096   compute_local_live_sets();
3097   compute_global_live_sets();
3098   CHECK_BAILOUT();
3099 
3100   build_intervals();
3101   CHECK_BAILOUT();
3102   sort_intervals_before_allocation();
3103 
3104   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3105   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3106 
3107   allocate_registers();
3108   CHECK_BAILOUT();
3109 
3110   resolve_data_flow();
3111   if (compilation()->has_exception_handlers()) {
3112     resolve_exception_handlers();
3113   }
3114   // fill in number of spill slots into frame_map
3115   propagate_spill_slots();
3116   CHECK_BAILOUT();
3117 
3118   NOT_PRODUCT(print_intervals("After Register Allocation"));
3119   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3120 
3121   sort_intervals_after_allocation();
3122 
3123   DEBUG_ONLY(verify());
3124 
3125   eliminate_spill_moves();
3126   assign_reg_num();
3127   CHECK_BAILOUT();
3128 
3129   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3130   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3131 
3132   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3133 
3134     if (use_fpu_stack_allocation()) {
3135       allocate_fpu_stack(); // Only has effect on Intel
3136       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3137     }
3138   }
3139 
3140   { TIME_LINEAR_SCAN(timer_optimize_lir);
3141 
3142     EdgeMoveOptimizer::optimize(ir()->code());
3143     ControlFlowOptimizer::optimize(ir()->code());
3144     // check that cfg is still correct after optimizations
3145     ir()->verify();
3146   }
3147 
3148   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3149   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3150   NOT_PRODUCT(_total_timer.end_method(this));
3151 }
3152 
3153 
3154 // ********** Printing functions
3155 
3156 #ifndef PRODUCT
3157 
3158 void LinearScan::print_timers(double total) {
3159   _total_timer.print(total);
3160 }
3161 
3162 void LinearScan::print_statistics() {
3163   _stat_before_alloc.print("before allocation");
3164   _stat_after_asign.print("after assignment of register");
3165   _stat_final.print("after optimization");
3166 }
3167 
3168 void LinearScan::print_bitmap(BitMap& b) {
3169   for (unsigned int i = 0; i < b.size(); i++) {
3170     if (b.at(i)) tty->print("%d ", i);
3171   }
3172   tty->cr();
3173 }
3174 
3175 void LinearScan::print_intervals(const char* label) {
3176   if (TraceLinearScanLevel >= 1) {
3177     int i;
3178     tty->cr();
3179     tty->print_cr("%s", label);
3180 
3181     for (i = 0; i < interval_count(); i++) {
3182       Interval* interval = interval_at(i);
3183       if (interval != NULL) {
3184         interval->print();
3185       }
3186     }
3187 
3188     tty->cr();
3189     tty->print_cr("--- Basic Blocks ---");
3190     for (i = 0; i < block_count(); i++) {
3191       BlockBegin* block = block_at(i);
3192       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3193     }
3194     tty->cr();
3195     tty->cr();
3196   }
3197 
3198   if (PrintCFGToFile) {
3199     CFGPrinter::print_intervals(&_intervals, label);
3200   }
3201 }
3202 
3203 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3204   if (TraceLinearScanLevel >= level) {
3205     tty->cr();
3206     tty->print_cr("%s", label);
3207     print_LIR(ir()->linear_scan_order());
3208     tty->cr();
3209   }
3210 
3211   if (level == 1 && PrintCFGToFile) {
3212     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3213   }
3214 }
3215 
3216 #endif //PRODUCT
3217 
3218 
3219 // ********** verification functions for allocation
3220 // (check that all intervals have a correct register and that no registers are overwritten)
3221 #ifdef ASSERT
3222 
3223 void LinearScan::verify() {
3224   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3225   verify_intervals();
3226 
3227   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3228   verify_no_oops_in_fixed_intervals();
3229 
3230   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3231   verify_constants();
3232 
3233   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3234   verify_registers();
3235 
3236   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3237 }
3238 
3239 void LinearScan::verify_intervals() {
3240   int len = interval_count();
3241   bool has_error = false;
3242 
3243   for (int i = 0; i < len; i++) {
3244     Interval* i1 = interval_at(i);
3245     if (i1 == NULL) continue;
3246 
3247     i1->check_split_children();
3248 
3249     if (i1->reg_num() != i) {
3250       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3251       has_error = true;
3252     }
3253 
3254     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3255       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3256       has_error = true;
3257     }
3258 
3259     if (i1->assigned_reg() == any_reg) {
3260       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3261       has_error = true;
3262     }
3263 
3264     if (i1->assigned_reg() == i1->assigned_regHi()) {
3265       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3266       has_error = true;
3267     }
3268 
3269     if (!is_processed_reg_num(i1->assigned_reg())) {
3270       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3271       has_error = true;
3272     }
3273 
3274     // special intervals that are created in MoveResolver
3275     // -> ignore them because the range information has no meaning there
3276     if (i1->from() == 1 && i1->to() == 2) continue;
3277 
3278     if (i1->first() == Range::end()) {
3279       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3280       has_error = true;
3281     }
3282 
3283     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3284       if (r->from() >= r->to()) {
3285         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3286         has_error = true;
3287       }
3288     }
3289 
3290     for (int j = i + 1; j < len; j++) {
3291       Interval* i2 = interval_at(j);
3292       if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3293 
3294       int r1 = i1->assigned_reg();
3295       int r1Hi = i1->assigned_regHi();
3296       int r2 = i2->assigned_reg();
3297       int r2Hi = i2->assigned_regHi();
3298       if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3299         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3300         i1->print(); tty->cr();
3301         i2->print(); tty->cr();
3302         has_error = true;
3303       }
3304     }
3305   }
3306 
3307   assert(has_error == false, "register allocation invalid");
3308 }
3309 
3310 
3311 void LinearScan::verify_no_oops_in_fixed_intervals() {
3312   Interval* fixed_intervals;
3313   Interval* other_intervals;
3314   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3315 
3316   // to ensure a walking until the last instruction id, add a dummy interval
3317   // with a high operation id
3318   other_intervals = new Interval(any_reg);
3319   other_intervals->add_range(max_jint - 2, max_jint - 1);
3320   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3321 
3322   LIR_OpVisitState visitor;
3323   for (int i = 0; i < block_count(); i++) {
3324     BlockBegin* block = block_at(i);
3325 
3326     LIR_OpList* instructions = block->lir()->instructions_list();
3327 
3328     for (int j = 0; j < instructions->length(); j++) {
3329       LIR_Op* op = instructions->at(j);
3330       int op_id = op->id();
3331 
3332       visitor.visit(op);
3333 
3334       if (visitor.info_count() > 0) {
3335         iw->walk_before(op->id());
3336         bool check_live = true;
3337         if (op->code() == lir_move) {
3338           LIR_Op1* move = (LIR_Op1*)op;
3339           check_live = (move->patch_code() == lir_patch_none);
3340         }
3341         LIR_OpBranch* branch = op->as_OpBranch();
3342         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3343           // Don't bother checking the stub in this case since the
3344           // exception stub will never return to normal control flow.
3345           check_live = false;
3346         }
3347 
3348         // Make sure none of the fixed registers is live across an
3349         // oopmap since we can't handle that correctly.
3350         if (check_live) {
3351           for (Interval* interval = iw->active_first(fixedKind);
3352                interval != Interval::end();
3353                interval = interval->next()) {
3354             if (interval->current_to() > op->id() + 1) {
3355               // This interval is live out of this op so make sure
3356               // that this interval represents some value that's
3357               // referenced by this op either as an input or output.
3358               bool ok = false;
3359               for_each_visitor_mode(mode) {
3360                 int n = visitor.opr_count(mode);
3361                 for (int k = 0; k < n; k++) {
3362                   LIR_Opr opr = visitor.opr_at(mode, k);
3363                   if (opr->is_fixed_cpu()) {
3364                     if (interval_at(reg_num(opr)) == interval) {
3365                       ok = true;
3366                       break;
3367                     }
3368                     int hi = reg_numHi(opr);
3369                     if (hi != -1 && interval_at(hi) == interval) {
3370                       ok = true;
3371                       break;
3372                     }
3373                   }
3374                 }
3375               }
3376               assert(ok, "fixed intervals should never be live across an oopmap point");
3377             }
3378           }
3379         }
3380       }
3381 
3382       // oop-maps at calls do not contain registers, so check is not needed
3383       if (!visitor.has_call()) {
3384 
3385         for_each_visitor_mode(mode) {
3386           int n = visitor.opr_count(mode);
3387           for (int k = 0; k < n; k++) {
3388             LIR_Opr opr = visitor.opr_at(mode, k);
3389 
3390             if (opr->is_fixed_cpu() && opr->is_oop()) {
3391               // operand is a non-virtual cpu register and contains an oop
3392               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3393 
3394               Interval* interval = interval_at(reg_num(opr));
3395               assert(interval != NULL, "no interval");
3396 
3397               if (mode == LIR_OpVisitState::inputMode) {
3398                 if (interval->to() >= op_id + 1) {
3399                   assert(interval->to() < op_id + 2 ||
3400                          interval->has_hole_between(op_id, op_id + 2),
3401                          "oop input operand live after instruction");
3402                 }
3403               } else if (mode == LIR_OpVisitState::outputMode) {
3404                 if (interval->from() <= op_id - 1) {
3405                   assert(interval->has_hole_between(op_id - 1, op_id),
3406                          "oop input operand live after instruction");
3407                 }
3408               }
3409             }
3410           }
3411         }
3412       }
3413     }
3414   }
3415 }
3416 
3417 
3418 void LinearScan::verify_constants() {
3419   int num_regs = num_virtual_regs();
3420   int size = live_set_size();
3421   int num_blocks = block_count();
3422 
3423   for (int i = 0; i < num_blocks; i++) {
3424     BlockBegin* block = block_at(i);
3425     ResourceBitMap live_at_edge = block->live_in();
3426 
3427     // visit all registers where the live_at_edge bit is set
3428     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3429       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3430 
3431       Value value = gen()->instruction_for_vreg(r);
3432 
3433       assert(value != NULL, "all intervals live across block boundaries must have Value");
3434       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3435       assert(value->operand()->vreg_number() == r, "register number must match");
3436       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3437     }
3438   }
3439 }
3440 
3441 
3442 class RegisterVerifier: public StackObj {
3443  private:
3444   LinearScan*   _allocator;
3445   BlockList     _work_list;      // all blocks that must be processed
3446   IntervalsList _saved_states;   // saved information of previous check
3447 
3448   // simplified access to methods of LinearScan
3449   Compilation*  compilation() const              { return _allocator->compilation(); }
3450   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3451   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3452 
3453   // currently, only registers are processed
3454   int           state_size()                     { return LinearScan::nof_regs; }
3455 
3456   // accessors
3457   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3458   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3459   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3460 
3461   // helper functions
3462   IntervalList* copy(IntervalList* input_state);
3463   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3464   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3465 
3466   void process_block(BlockBegin* block);
3467   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3468   void process_successor(BlockBegin* block, IntervalList* input_state);
3469   void process_operations(LIR_List* ops, IntervalList* input_state);
3470 
3471  public:
3472   RegisterVerifier(LinearScan* allocator)
3473     : _allocator(allocator)
3474     , _work_list(16)
3475     , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3476   { }
3477 
3478   void verify(BlockBegin* start);
3479 };
3480 
3481 
3482 // entry function from LinearScan that starts the verification
3483 void LinearScan::verify_registers() {
3484   RegisterVerifier verifier(this);
3485   verifier.verify(block_at(0));
3486 }
3487 
3488 
3489 void RegisterVerifier::verify(BlockBegin* start) {
3490   // setup input registers (method arguments) for first block
3491   int input_state_len = state_size();
3492   IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3493   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3494   for (int n = 0; n < args->length(); n++) {
3495     LIR_Opr opr = args->at(n);
3496     if (opr->is_register()) {
3497       Interval* interval = interval_at(reg_num(opr));
3498 
3499       if (interval->assigned_reg() < state_size()) {
3500         input_state->at_put(interval->assigned_reg(), interval);
3501       }
3502       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3503         input_state->at_put(interval->assigned_regHi(), interval);
3504       }
3505     }
3506   }
3507 
3508   set_state_for_block(start, input_state);
3509   add_to_work_list(start);
3510 
3511   // main loop for verification
3512   do {
3513     BlockBegin* block = _work_list.at(0);
3514     _work_list.remove_at(0);
3515 
3516     process_block(block);
3517   } while (!_work_list.is_empty());
3518 }
3519 
3520 void RegisterVerifier::process_block(BlockBegin* block) {
3521   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3522 
3523   // must copy state because it is modified
3524   IntervalList* input_state = copy(state_for_block(block));
3525 
3526   if (TraceLinearScanLevel >= 4) {
3527     tty->print_cr("Input-State of intervals:");
3528     tty->print("    ");
3529     for (int i = 0; i < state_size(); i++) {
3530       if (input_state->at(i) != NULL) {
3531         tty->print(" %4d", input_state->at(i)->reg_num());
3532       } else {
3533         tty->print("   __");
3534       }
3535     }
3536     tty->cr();
3537     tty->cr();
3538   }
3539 
3540   // process all operations of the block
3541   process_operations(block->lir(), input_state);
3542 
3543   // iterate all successors
3544   for (int i = 0; i < block->number_of_sux(); i++) {
3545     process_successor(block->sux_at(i), input_state);
3546   }
3547 }
3548 
3549 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3550   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3551 
3552   // must copy state because it is modified
3553   input_state = copy(input_state);
3554 
3555   if (xhandler->entry_code() != NULL) {
3556     process_operations(xhandler->entry_code(), input_state);
3557   }
3558   process_successor(xhandler->entry_block(), input_state);
3559 }
3560 
3561 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3562   IntervalList* saved_state = state_for_block(block);
3563 
3564   if (saved_state != NULL) {
3565     // this block was already processed before.
3566     // check if new input_state is consistent with saved_state
3567 
3568     bool saved_state_correct = true;
3569     for (int i = 0; i < state_size(); i++) {
3570       if (input_state->at(i) != saved_state->at(i)) {
3571         // current input_state and previous saved_state assume a different
3572         // interval in this register -> assume that this register is invalid
3573         if (saved_state->at(i) != NULL) {
3574           // invalidate old calculation only if it assumed that
3575           // register was valid. when the register was already invalid,
3576           // then the old calculation was correct.
3577           saved_state_correct = false;
3578           saved_state->at_put(i, NULL);
3579 
3580           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3581         }
3582       }
3583     }
3584 
3585     if (saved_state_correct) {
3586       // already processed block with correct input_state
3587       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3588     } else {
3589       // must re-visit this block
3590       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3591       add_to_work_list(block);
3592     }
3593 
3594   } else {
3595     // block was not processed before, so set initial input_state
3596     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3597 
3598     set_state_for_block(block, copy(input_state));
3599     add_to_work_list(block);
3600   }
3601 }
3602 
3603 
3604 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3605   IntervalList* copy_state = new IntervalList(input_state->length());
3606   copy_state->appendAll(input_state);
3607   return copy_state;
3608 }
3609 
3610 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3611   if (reg != LinearScan::any_reg && reg < state_size()) {
3612     if (interval != NULL) {
3613       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3614     } else if (input_state->at(reg) != NULL) {
3615       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3616     }
3617 
3618     input_state->at_put(reg, interval);
3619   }
3620 }
3621 
3622 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3623   if (reg != LinearScan::any_reg && reg < state_size()) {
3624     if (input_state->at(reg) != interval) {
3625       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3626       return true;
3627     }
3628   }
3629   return false;
3630 }
3631 
3632 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3633   // visit all instructions of the block
3634   LIR_OpVisitState visitor;
3635   bool has_error = false;
3636 
3637   for (int i = 0; i < ops->length(); i++) {
3638     LIR_Op* op = ops->at(i);
3639     visitor.visit(op);
3640 
3641     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3642 
3643     // check if input operands are correct
3644     int j;
3645     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3646     for (j = 0; j < n; j++) {
3647       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3648       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3649         Interval* interval = interval_at(reg_num(opr));
3650         if (op->id() != -1) {
3651           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3652         }
3653 
3654         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3655         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3656 
3657         // When an operand is marked with is_last_use, then the fpu stack allocator
3658         // removes the register from the fpu stack -> the register contains no value
3659         if (opr->is_last_use()) {
3660           state_put(input_state, interval->assigned_reg(),   NULL);
3661           state_put(input_state, interval->assigned_regHi(), NULL);
3662         }
3663       }
3664     }
3665 
3666     // invalidate all caller save registers at calls
3667     if (visitor.has_call()) {
3668       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3669         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3670       }
3671       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3672         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3673       }
3674 
3675 #ifdef X86
3676       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3677       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3678         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3679       }
3680 #endif
3681     }
3682 
3683     // process xhandler before output and temp operands
3684     XHandlers* xhandlers = visitor.all_xhandler();
3685     n = xhandlers->length();
3686     for (int k = 0; k < n; k++) {
3687       process_xhandler(xhandlers->handler_at(k), input_state);
3688     }
3689 
3690     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3691     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3692     for (j = 0; j < n; j++) {
3693       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3694       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3695         Interval* interval = interval_at(reg_num(opr));
3696         if (op->id() != -1) {
3697           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3698         }
3699 
3700         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3701         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3702       }
3703     }
3704 
3705     // set output operands
3706     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3707     for (j = 0; j < n; j++) {
3708       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3709       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3710         Interval* interval = interval_at(reg_num(opr));
3711         if (op->id() != -1) {
3712           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3713         }
3714 
3715         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3716         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3717       }
3718     }
3719   }
3720   assert(has_error == false, "Error in register allocation");
3721 }
3722 
3723 #endif // ASSERT
3724 
3725 
3726 
3727 // **** Implementation of MoveResolver ******************************
3728 
3729 MoveResolver::MoveResolver(LinearScan* allocator) :
3730   _allocator(allocator),
3731   _insert_list(NULL),
3732   _insert_idx(-1),
3733   _insertion_buffer(),
3734   _mapping_from(8),
3735   _mapping_from_opr(8),
3736   _mapping_to(8),
3737   _multiple_reads_allowed(false)
3738 {
3739   for (int i = 0; i < LinearScan::nof_regs; i++) {
3740     _register_blocked[i] = 0;
3741   }
3742   DEBUG_ONLY(check_empty());
3743 }
3744 
3745 
3746 #ifdef ASSERT
3747 
3748 void MoveResolver::check_empty() {
3749   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3750   for (int i = 0; i < LinearScan::nof_regs; i++) {
3751     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3752   }
3753   assert(_multiple_reads_allowed == false, "must have default value");
3754 }
3755 
3756 void MoveResolver::verify_before_resolve() {
3757   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3758   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3759   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3760 
3761   int i, j;
3762   if (!_multiple_reads_allowed) {
3763     for (i = 0; i < _mapping_from.length(); i++) {
3764       for (j = i + 1; j < _mapping_from.length(); j++) {
3765         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3766       }
3767     }
3768   }
3769 
3770   for (i = 0; i < _mapping_to.length(); i++) {
3771     for (j = i + 1; j < _mapping_to.length(); j++) {
3772       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3773     }
3774   }
3775 
3776 
3777   ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3778   if (!_multiple_reads_allowed) {
3779     for (i = 0; i < _mapping_from.length(); i++) {
3780       Interval* it = _mapping_from.at(i);
3781       if (it != NULL) {
3782         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3783         used_regs.set_bit(it->assigned_reg());
3784 
3785         if (it->assigned_regHi() != LinearScan::any_reg) {
3786           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3787           used_regs.set_bit(it->assigned_regHi());
3788         }
3789       }
3790     }
3791   }
3792 
3793   used_regs.clear();
3794   for (i = 0; i < _mapping_to.length(); i++) {
3795     Interval* it = _mapping_to.at(i);
3796     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3797     used_regs.set_bit(it->assigned_reg());
3798 
3799     if (it->assigned_regHi() != LinearScan::any_reg) {
3800       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3801       used_regs.set_bit(it->assigned_regHi());
3802     }
3803   }
3804 
3805   used_regs.clear();
3806   for (i = 0; i < _mapping_from.length(); i++) {
3807     Interval* it = _mapping_from.at(i);
3808     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3809       used_regs.set_bit(it->assigned_reg());
3810     }
3811   }
3812   for (i = 0; i < _mapping_to.length(); i++) {
3813     Interval* it = _mapping_to.at(i);
3814     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3815   }
3816 }
3817 
3818 #endif // ASSERT
3819 
3820 
3821 // mark assigned_reg and assigned_regHi of the interval as blocked
3822 void MoveResolver::block_registers(Interval* it) {
3823   int reg = it->assigned_reg();
3824   if (reg < LinearScan::nof_regs) {
3825     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3826     set_register_blocked(reg, 1);
3827   }
3828   reg = it->assigned_regHi();
3829   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3830     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3831     set_register_blocked(reg, 1);
3832   }
3833 }
3834 
3835 // mark assigned_reg and assigned_regHi of the interval as unblocked
3836 void MoveResolver::unblock_registers(Interval* it) {
3837   int reg = it->assigned_reg();
3838   if (reg < LinearScan::nof_regs) {
3839     assert(register_blocked(reg) > 0, "register already marked as unused");
3840     set_register_blocked(reg, -1);
3841   }
3842   reg = it->assigned_regHi();
3843   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3844     assert(register_blocked(reg) > 0, "register already marked as unused");
3845     set_register_blocked(reg, -1);
3846   }
3847 }
3848 
3849 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3850 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3851   int from_reg = -1;
3852   int from_regHi = -1;
3853   if (from != NULL) {
3854     from_reg = from->assigned_reg();
3855     from_regHi = from->assigned_regHi();
3856   }
3857 
3858   int reg = to->assigned_reg();
3859   if (reg < LinearScan::nof_regs) {
3860     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3861       return false;
3862     }
3863   }
3864   reg = to->assigned_regHi();
3865   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3866     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3867       return false;
3868     }
3869   }
3870 
3871   return true;
3872 }
3873 
3874 
3875 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3876   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3877   _insertion_buffer.init(list);
3878 }
3879 
3880 void MoveResolver::append_insertion_buffer() {
3881   if (_insertion_buffer.initialized()) {
3882     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3883   }
3884   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3885 
3886   _insert_list = NULL;
3887   _insert_idx = -1;
3888 }
3889 
3890 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3891   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3892   assert(from_interval->type() == to_interval->type(), "move between different types");
3893   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3894   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3895 
3896   LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3897   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3898 
3899   if (!_multiple_reads_allowed) {
3900     // the last_use flag is an optimization for FPU stack allocation. When the same
3901     // input interval is used in more than one move, then it is too difficult to determine
3902     // if this move is really the last use.
3903     from_opr = from_opr->make_last_use();
3904   }
3905   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3906 
3907   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3908 }
3909 
3910 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3911   assert(from_opr->type() == to_interval->type(), "move between different types");
3912   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3913   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3914 
3915   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3916   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3917 
3918   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3919 }
3920 
3921 
3922 void MoveResolver::resolve_mappings() {
3923   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3924   DEBUG_ONLY(verify_before_resolve());
3925 
3926   // Block all registers that are used as input operands of a move.
3927   // When a register is blocked, no move to this register is emitted.
3928   // This is necessary for detecting cycles in moves.
3929   int i;
3930   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3931     Interval* from_interval = _mapping_from.at(i);
3932     if (from_interval != NULL) {
3933       block_registers(from_interval);
3934     }
3935   }
3936 
3937   int spill_candidate = -1;
3938   while (_mapping_from.length() > 0) {
3939     bool processed_interval = false;
3940 
3941     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3942       Interval* from_interval = _mapping_from.at(i);
3943       Interval* to_interval = _mapping_to.at(i);
3944 
3945       if (save_to_process_move(from_interval, to_interval)) {
3946         // this inverval can be processed because target is free
3947         if (from_interval != NULL) {
3948           insert_move(from_interval, to_interval);
3949           unblock_registers(from_interval);
3950         } else {
3951           insert_move(_mapping_from_opr.at(i), to_interval);
3952         }
3953         _mapping_from.remove_at(i);
3954         _mapping_from_opr.remove_at(i);
3955         _mapping_to.remove_at(i);
3956 
3957         processed_interval = true;
3958       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3959         // this interval cannot be processed now because target is not free
3960         // it starts in a register, so it is a possible candidate for spilling
3961         spill_candidate = i;
3962       }
3963     }
3964 
3965     if (!processed_interval) {
3966       // no move could be processed because there is a cycle in the move list
3967       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3968       guarantee(spill_candidate != -1, "no interval in register for spilling found");
3969 
3970       // create a new spill interval and assign a stack slot to it
3971       Interval* from_interval = _mapping_from.at(spill_candidate);
3972       Interval* spill_interval = new Interval(-1);
3973       spill_interval->set_type(from_interval->type());
3974 
3975       // add a dummy range because real position is difficult to calculate
3976       // Note: this range is a special case when the integrity of the allocation is checked
3977       spill_interval->add_range(1, 2);
3978 
3979       //       do not allocate a new spill slot for temporary interval, but
3980       //       use spill slot assigned to from_interval. Otherwise moves from
3981       //       one stack slot to another can happen (not allowed by LIR_Assembler
3982       int spill_slot = from_interval->canonical_spill_slot();
3983       if (spill_slot < 0) {
3984         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3985         from_interval->set_canonical_spill_slot(spill_slot);
3986       }
3987       spill_interval->assign_reg(spill_slot);
3988       allocator()->append_interval(spill_interval);
3989 
3990       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3991 
3992       // insert a move from register to stack and update the mapping
3993       insert_move(from_interval, spill_interval);
3994       _mapping_from.at_put(spill_candidate, spill_interval);
3995       unblock_registers(from_interval);
3996     }
3997   }
3998 
3999   // reset to default value
4000   _multiple_reads_allowed = false;
4001 
4002   // check that all intervals have been processed
4003   DEBUG_ONLY(check_empty());
4004 }
4005 
4006 
4007 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4008   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4009   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4010 
4011   create_insertion_buffer(insert_list);
4012   _insert_list = insert_list;
4013   _insert_idx = insert_idx;
4014 }
4015 
4016 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4017   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4018 
4019   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4020     // insert position changed -> resolve current mappings
4021     resolve_mappings();
4022   }
4023 
4024   if (insert_list != _insert_list) {
4025     // block changed -> append insertion_buffer because it is
4026     // bound to a specific block and create a new insertion_buffer
4027     append_insertion_buffer();
4028     create_insertion_buffer(insert_list);
4029   }
4030 
4031   _insert_list = insert_list;
4032   _insert_idx = insert_idx;
4033 }
4034 
4035 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4036   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4037 
4038   _mapping_from.append(from_interval);
4039   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4040   _mapping_to.append(to_interval);
4041 }
4042 
4043 
4044 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4045   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4046   assert(from_opr->is_constant(), "only for constants");
4047 
4048   _mapping_from.append(NULL);
4049   _mapping_from_opr.append(from_opr);
4050   _mapping_to.append(to_interval);
4051 }
4052 
4053 void MoveResolver::resolve_and_append_moves() {
4054   if (has_mappings()) {
4055     resolve_mappings();
4056   }
4057   append_insertion_buffer();
4058 }
4059 
4060 
4061 
4062 // **** Implementation of Range *************************************
4063 
4064 Range::Range(int from, int to, Range* next) :
4065   _from(from),
4066   _to(to),
4067   _next(next)
4068 {
4069 }
4070 
4071 // initialize sentinel
4072 Range* Range::_end = NULL;
4073 void Range::initialize(Arena* arena) {
4074   _end = new (arena) Range(max_jint, max_jint, NULL);
4075 }
4076 
4077 int Range::intersects_at(Range* r2) const {
4078   const Range* r1 = this;
4079 
4080   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4081   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4082 
4083   do {
4084     if (r1->from() < r2->from()) {
4085       if (r1->to() <= r2->from()) {
4086         r1 = r1->next(); if (r1 == _end) return -1;
4087       } else {
4088         return r2->from();
4089       }
4090     } else if (r2->from() < r1->from()) {
4091       if (r2->to() <= r1->from()) {
4092         r2 = r2->next(); if (r2 == _end) return -1;
4093       } else {
4094         return r1->from();
4095       }
4096     } else { // r1->from() == r2->from()
4097       if (r1->from() == r1->to()) {
4098         r1 = r1->next(); if (r1 == _end) return -1;
4099       } else if (r2->from() == r2->to()) {
4100         r2 = r2->next(); if (r2 == _end) return -1;
4101       } else {
4102         return r1->from();
4103       }
4104     }
4105   } while (true);
4106 }
4107 
4108 #ifndef PRODUCT
4109 void Range::print(outputStream* out) const {
4110   out->print("[%d, %d[ ", _from, _to);
4111 }
4112 #endif
4113 
4114 
4115 
4116 // **** Implementation of Interval **********************************
4117 
4118 // initialize sentinel
4119 Interval* Interval::_end = NULL;
4120 void Interval::initialize(Arena* arena) {
4121   Range::initialize(arena);
4122   _end = new (arena) Interval(-1);
4123 }
4124 
4125 Interval::Interval(int reg_num) :
4126   _reg_num(reg_num),
4127   _type(T_ILLEGAL),
4128   _first(Range::end()),
4129   _use_pos_and_kinds(12),
4130   _current(Range::end()),
4131   _next(_end),
4132   _state(invalidState),
4133   _assigned_reg(LinearScan::any_reg),
4134   _assigned_regHi(LinearScan::any_reg),
4135   _cached_to(-1),
4136   _cached_opr(LIR_OprFact::illegalOpr),
4137   _cached_vm_reg(VMRegImpl::Bad()),
4138   _split_children(NULL),
4139   _canonical_spill_slot(-1),
4140   _insert_move_when_activated(false),
4141   _spill_state(noDefinitionFound),
4142   _spill_definition_pos(-1),
4143   _register_hint(NULL)
4144 {
4145   _split_parent = this;
4146   _current_split_child = this;
4147 }
4148 
4149 int Interval::calc_to() {
4150   assert(_first != Range::end(), "interval has no range");
4151 
4152   Range* r = _first;
4153   while (r->next() != Range::end()) {
4154     r = r->next();
4155   }
4156   return r->to();
4157 }
4158 
4159 
4160 #ifdef ASSERT
4161 // consistency check of split-children
4162 void Interval::check_split_children() {
4163   if (_split_children != NULL && _split_children->length() > 0) {
4164     assert(is_split_parent(), "only split parents can have children");
4165 
4166     for (int i = 0; i < _split_children->length(); i++) {
4167       Interval* i1 = _split_children->at(i);
4168 
4169       assert(i1->split_parent() == this, "not a split child of this interval");
4170       assert(i1->type() == type(), "must be equal for all split children");
4171       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4172 
4173       for (int j = i + 1; j < _split_children->length(); j++) {
4174         Interval* i2 = _split_children->at(j);
4175 
4176         assert(i1->reg_num() != i2->reg_num(), "same register number");
4177 
4178         if (i1->from() < i2->from()) {
4179           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4180         } else {
4181           assert(i2->from() < i1->from(), "intervals start at same op_id");
4182           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4183         }
4184       }
4185     }
4186   }
4187 }
4188 #endif // ASSERT
4189 
4190 Interval* Interval::register_hint(bool search_split_child) const {
4191   if (!search_split_child) {
4192     return _register_hint;
4193   }
4194 
4195   if (_register_hint != NULL) {
4196     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4197 
4198     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4199       return _register_hint;
4200 
4201     } else if (_register_hint->_split_children != NULL && _register_hint->_split_children->length() > 0) {
4202       // search the first split child that has a register assigned
4203       int len = _register_hint->_split_children->length();
4204       for (int i = 0; i < len; i++) {
4205         Interval* cur = _register_hint->_split_children->at(i);
4206 
4207         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4208           return cur;
4209         }
4210       }
4211     }
4212   }
4213 
4214   // no hint interval found that has a register assigned
4215   return NULL;
4216 }
4217 
4218 
4219 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4220   assert(is_split_parent(), "can only be called for split parents");
4221   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4222 
4223   Interval* result;
4224   if (_split_children == NULL || _split_children->length() == 0) {
4225     result = this;
4226   } else {
4227     result = NULL;
4228     int len = _split_children->length();
4229 
4230     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4231     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4232 
4233     int i;
4234     for (i = 0; i < len; i++) {
4235       Interval* cur = _split_children->at(i);
4236       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4237         if (i > 0) {
4238           // exchange current split child to start of list (faster access for next call)
4239           _split_children->at_put(i, _split_children->at(0));
4240           _split_children->at_put(0, cur);
4241         }
4242 
4243         // interval found
4244         result = cur;
4245         break;
4246       }
4247     }
4248 
4249 #ifdef ASSERT
4250     for (i = 0; i < len; i++) {
4251       Interval* tmp = _split_children->at(i);
4252       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4253         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4254         result->print();
4255         tmp->print();
4256         assert(false, "two valid result intervals found");
4257       }
4258     }
4259 #endif
4260   }
4261 
4262   assert(result != NULL, "no matching interval found");
4263   assert(result->covers(op_id, mode), "op_id not covered by interval");
4264 
4265   return result;
4266 }
4267 
4268 
4269 // returns the last split child that ends before the given op_id
4270 Interval* Interval::split_child_before_op_id(int op_id) {
4271   assert(op_id >= 0, "invalid op_id");
4272 
4273   Interval* parent = split_parent();
4274   Interval* result = NULL;
4275 
4276   assert(parent->_split_children != NULL, "no split children available");
4277   int len = parent->_split_children->length();
4278   assert(len > 0, "no split children available");
4279 
4280   for (int i = len - 1; i >= 0; i--) {
4281     Interval* cur = parent->_split_children->at(i);
4282     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4283       result = cur;
4284     }
4285   }
4286 
4287   assert(result != NULL, "no split child found");
4288   return result;
4289 }
4290 
4291 
4292 // Note: use positions are sorted descending -> first use has highest index
4293 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4294   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4295 
4296   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4297     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4298       return _use_pos_and_kinds.at(i);
4299     }
4300   }
4301   return max_jint;
4302 }
4303 
4304 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4305   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4306 
4307   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4308     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4309       return _use_pos_and_kinds.at(i);
4310     }
4311   }
4312   return max_jint;
4313 }
4314 
4315 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4316   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4317 
4318   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4319     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4320       return _use_pos_and_kinds.at(i);
4321     }
4322   }
4323   return max_jint;
4324 }
4325 
4326 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4327   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4328 
4329   int prev = 0;
4330   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4331     if (_use_pos_and_kinds.at(i) > from) {
4332       return prev;
4333     }
4334     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4335       prev = _use_pos_and_kinds.at(i);
4336     }
4337   }
4338   return prev;
4339 }
4340 
4341 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4342   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4343 
4344   // do not add use positions for precolored intervals because
4345   // they are never used
4346   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4347 #ifdef ASSERT
4348     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4349     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4350       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4351       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4352       if (i > 0) {
4353         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4354       }
4355     }
4356 #endif
4357 
4358     // Note: add_use is called in descending order, so list gets sorted
4359     //       automatically by just appending new use positions
4360     int len = _use_pos_and_kinds.length();
4361     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4362       _use_pos_and_kinds.append(pos);
4363       _use_pos_and_kinds.append(use_kind);
4364     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4365       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4366       _use_pos_and_kinds.at_put(len - 1, use_kind);
4367     }
4368   }
4369 }
4370 
4371 void Interval::add_range(int from, int to) {
4372   assert(from < to, "invalid range");
4373   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4374   assert(from <= first()->to(), "not inserting at begin of interval");
4375 
4376   if (first()->from() <= to) {
4377     // join intersecting ranges
4378     first()->set_from(MIN2(from, first()->from()));
4379     first()->set_to  (MAX2(to,   first()->to()));
4380   } else {
4381     // insert new range
4382     _first = new Range(from, to, first());
4383   }
4384 }
4385 
4386 Interval* Interval::new_split_child() {
4387   // allocate new interval
4388   Interval* result = new Interval(-1);
4389   result->set_type(type());
4390 
4391   Interval* parent = split_parent();
4392   result->_split_parent = parent;
4393   result->set_register_hint(parent);
4394 
4395   // insert new interval in children-list of parent
4396   if (parent->_split_children == NULL) {
4397     assert(is_split_parent(), "list must be initialized at first split");
4398 
4399     parent->_split_children = new IntervalList(4);
4400     parent->_split_children->append(this);
4401   }
4402   parent->_split_children->append(result);
4403 
4404   return result;
4405 }
4406 
4407 // split this interval at the specified position and return
4408 // the remainder as a new interval.
4409 //
4410 // when an interval is split, a bi-directional link is established between the original interval
4411 // (the split parent) and the intervals that are split off this interval (the split children)
4412 // When a split child is split again, the new created interval is also a direct child
4413 // of the original parent (there is no tree of split children stored, but a flat list)
4414 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4415 //
4416 // Note: The new interval has no valid reg_num
4417 Interval* Interval::split(int split_pos) {
4418   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4419 
4420   // allocate new interval
4421   Interval* result = new_split_child();
4422 
4423   // split the ranges
4424   Range* prev = NULL;
4425   Range* cur = _first;
4426   while (cur != Range::end() && cur->to() <= split_pos) {
4427     prev = cur;
4428     cur = cur->next();
4429   }
4430   assert(cur != Range::end(), "split interval after end of last range");
4431 
4432   if (cur->from() < split_pos) {
4433     result->_first = new Range(split_pos, cur->to(), cur->next());
4434     cur->set_to(split_pos);
4435     cur->set_next(Range::end());
4436 
4437   } else {
4438     assert(prev != NULL, "split before start of first range");
4439     result->_first = cur;
4440     prev->set_next(Range::end());
4441   }
4442   result->_current = result->_first;
4443   _cached_to = -1; // clear cached value
4444 
4445   // split list of use positions
4446   int total_len = _use_pos_and_kinds.length();
4447   int start_idx = total_len - 2;
4448   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4449     start_idx -= 2;
4450   }
4451 
4452   intStack new_use_pos_and_kinds(total_len - start_idx);
4453   int i;
4454   for (i = start_idx + 2; i < total_len; i++) {
4455     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4456   }
4457 
4458   _use_pos_and_kinds.trunc_to(start_idx + 2);
4459   result->_use_pos_and_kinds = _use_pos_and_kinds;
4460   _use_pos_and_kinds = new_use_pos_and_kinds;
4461 
4462 #ifdef ASSERT
4463   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4464   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4465   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4466 
4467   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4468     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4469     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4470   }
4471   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4472     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4473     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4474   }
4475 #endif
4476 
4477   return result;
4478 }
4479 
4480 // split this interval at the specified position and return
4481 // the head as a new interval (the original interval is the tail)
4482 //
4483 // Currently, only the first range can be split, and the new interval
4484 // must not have split positions
4485 Interval* Interval::split_from_start(int split_pos) {
4486   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4487   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4488   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4489   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4490 
4491   // allocate new interval
4492   Interval* result = new_split_child();
4493 
4494   // the new created interval has only one range (checked by assertion above),
4495   // so the splitting of the ranges is very simple
4496   result->add_range(_first->from(), split_pos);
4497 
4498   if (split_pos == _first->to()) {
4499     assert(_first->next() != Range::end(), "must not be at end");
4500     _first = _first->next();
4501   } else {
4502     _first->set_from(split_pos);
4503   }
4504 
4505   return result;
4506 }
4507 
4508 
4509 // returns true if the op_id is inside the interval
4510 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4511   Range* cur  = _first;
4512 
4513   while (cur != Range::end() && cur->to() < op_id) {
4514     cur = cur->next();
4515   }
4516   if (cur != Range::end()) {
4517     assert(cur->to() != cur->next()->from(), "ranges not separated");
4518 
4519     if (mode == LIR_OpVisitState::outputMode) {
4520       return cur->from() <= op_id && op_id < cur->to();
4521     } else {
4522       return cur->from() <= op_id && op_id <= cur->to();
4523     }
4524   }
4525   return false;
4526 }
4527 
4528 // returns true if the interval has any hole between hole_from and hole_to
4529 // (even if the hole has only the length 1)
4530 bool Interval::has_hole_between(int hole_from, int hole_to) {
4531   assert(hole_from < hole_to, "check");
4532   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4533 
4534   Range* cur  = _first;
4535   while (cur != Range::end()) {
4536     assert(cur->to() < cur->next()->from(), "no space between ranges");
4537 
4538     // hole-range starts before this range -> hole
4539     if (hole_from < cur->from()) {
4540       return true;
4541 
4542     // hole-range completely inside this range -> no hole
4543     } else if (hole_to <= cur->to()) {
4544       return false;
4545 
4546     // overlapping of hole-range with this range -> hole
4547     } else if (hole_from <= cur->to()) {
4548       return true;
4549     }
4550 
4551     cur = cur->next();
4552   }
4553 
4554   return false;
4555 }
4556 
4557 
4558 #ifndef PRODUCT
4559 void Interval::print(outputStream* out) const {
4560   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4561   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4562 
4563   const char* type_name;
4564   LIR_Opr opr = LIR_OprFact::illegal();
4565   if (reg_num() < LIR_OprDesc::vreg_base) {
4566     type_name = "fixed";
4567     // need a temporary operand for fixed intervals because type() cannot be called
4568 #ifdef X86
4569     int last_xmm_reg = pd_last_xmm_reg;
4570 #ifdef _LP64
4571     if (UseAVX < 3) {
4572       last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
4573     }
4574 #endif
4575 #endif
4576     if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4577       opr = LIR_OprFact::single_cpu(assigned_reg());
4578     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4579       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4580 #ifdef X86
4581     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) {
4582       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4583 #endif
4584     } else {
4585       ShouldNotReachHere();
4586     }
4587   } else {
4588     type_name = type2name(type());
4589     if (assigned_reg() != -1 &&
4590         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4591       opr = LinearScan::calc_operand_for_interval(this);
4592     }
4593   }
4594 
4595   out->print("%d %s ", reg_num(), type_name);
4596   if (opr->is_valid()) {
4597     out->print("\"");
4598     opr->print(out);
4599     out->print("\" ");
4600   }
4601   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4602 
4603   // print ranges
4604   Range* cur = _first;
4605   while (cur != Range::end()) {
4606     cur->print(out);
4607     cur = cur->next();
4608     assert(cur != NULL, "range list not closed with range sentinel");
4609   }
4610 
4611   // print use positions
4612   int prev = 0;
4613   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4614   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4615     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4616     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4617 
4618     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4619     prev = _use_pos_and_kinds.at(i);
4620   }
4621 
4622   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4623   out->cr();
4624 }
4625 #endif
4626 
4627 
4628 
4629 // **** Implementation of IntervalWalker ****************************
4630 
4631 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4632  : _compilation(allocator->compilation())
4633  , _allocator(allocator)
4634 {
4635   _unhandled_first[fixedKind] = unhandled_fixed_first;
4636   _unhandled_first[anyKind]   = unhandled_any_first;
4637   _active_first[fixedKind]    = Interval::end();
4638   _inactive_first[fixedKind]  = Interval::end();
4639   _active_first[anyKind]      = Interval::end();
4640   _inactive_first[anyKind]    = Interval::end();
4641   _current_position = -1;
4642   _current = NULL;
4643   next_interval();
4644 }
4645 
4646 
4647 // append interval in order of current range from()
4648 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4649   Interval* prev = NULL;
4650   Interval* cur  = *list;
4651   while (cur->current_from() < interval->current_from()) {
4652     prev = cur; cur = cur->next();
4653   }
4654   if (prev == NULL) {
4655     *list = interval;
4656   } else {
4657     prev->set_next(interval);
4658   }
4659   interval->set_next(cur);
4660 }
4661 
4662 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4663   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4664 
4665   Interval* prev = NULL;
4666   Interval* cur  = *list;
4667   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4668     prev = cur; cur = cur->next();
4669   }
4670   if (prev == NULL) {
4671     *list = interval;
4672   } else {
4673     prev->set_next(interval);
4674   }
4675   interval->set_next(cur);
4676 }
4677 
4678 
4679 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4680   while (*list != Interval::end() && *list != i) {
4681     list = (*list)->next_addr();
4682   }
4683   if (*list != Interval::end()) {
4684     assert(*list == i, "check");
4685     *list = (*list)->next();
4686     return true;
4687   } else {
4688     return false;
4689   }
4690 }
4691 
4692 void IntervalWalker::remove_from_list(Interval* i) {
4693   bool deleted;
4694 
4695   if (i->state() == activeState) {
4696     deleted = remove_from_list(active_first_addr(anyKind), i);
4697   } else {
4698     assert(i->state() == inactiveState, "invalid state");
4699     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4700   }
4701 
4702   assert(deleted, "interval has not been found in list");
4703 }
4704 
4705 
4706 void IntervalWalker::walk_to(IntervalState state, int from) {
4707   assert (state == activeState || state == inactiveState, "wrong state");
4708   for_each_interval_kind(kind) {
4709     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4710     Interval* next   = *prev;
4711     while (next->current_from() <= from) {
4712       Interval* cur = next;
4713       next = cur->next();
4714 
4715       bool range_has_changed = false;
4716       while (cur->current_to() <= from) {
4717         cur->next_range();
4718         range_has_changed = true;
4719       }
4720 
4721       // also handle move from inactive list to active list
4722       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4723 
4724       if (range_has_changed) {
4725         // remove cur from list
4726         *prev = next;
4727         if (cur->current_at_end()) {
4728           // move to handled state (not maintained as a list)
4729           cur->set_state(handledState);
4730           interval_moved(cur, kind, state, handledState);
4731         } else if (cur->current_from() <= from){
4732           // sort into active list
4733           append_sorted(active_first_addr(kind), cur);
4734           cur->set_state(activeState);
4735           if (*prev == cur) {
4736             assert(state == activeState, "check");
4737             prev = cur->next_addr();
4738           }
4739           interval_moved(cur, kind, state, activeState);
4740         } else {
4741           // sort into inactive list
4742           append_sorted(inactive_first_addr(kind), cur);
4743           cur->set_state(inactiveState);
4744           if (*prev == cur) {
4745             assert(state == inactiveState, "check");
4746             prev = cur->next_addr();
4747           }
4748           interval_moved(cur, kind, state, inactiveState);
4749         }
4750       } else {
4751         prev = cur->next_addr();
4752         continue;
4753       }
4754     }
4755   }
4756 }
4757 
4758 
4759 void IntervalWalker::next_interval() {
4760   IntervalKind kind;
4761   Interval* any   = _unhandled_first[anyKind];
4762   Interval* fixed = _unhandled_first[fixedKind];
4763 
4764   if (any != Interval::end()) {
4765     // intervals may start at same position -> prefer fixed interval
4766     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4767 
4768     assert (kind == fixedKind && fixed->from() <= any->from() ||
4769             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4770     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4771 
4772   } else if (fixed != Interval::end()) {
4773     kind = fixedKind;
4774   } else {
4775     _current = NULL; return;
4776   }
4777   _current_kind = kind;
4778   _current = _unhandled_first[kind];
4779   _unhandled_first[kind] = _current->next();
4780   _current->set_next(Interval::end());
4781   _current->rewind_range();
4782 }
4783 
4784 
4785 void IntervalWalker::walk_to(int lir_op_id) {
4786   assert(_current_position <= lir_op_id, "can not walk backwards");
4787   while (current() != NULL) {
4788     bool is_active = current()->from() <= lir_op_id;
4789     int id = is_active ? current()->from() : lir_op_id;
4790 
4791     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4792 
4793     // set _current_position prior to call of walk_to
4794     _current_position = id;
4795 
4796     // call walk_to even if _current_position == id
4797     walk_to(activeState, id);
4798     walk_to(inactiveState, id);
4799 
4800     if (is_active) {
4801       current()->set_state(activeState);
4802       if (activate_current()) {
4803         append_sorted(active_first_addr(current_kind()), current());
4804         interval_moved(current(), current_kind(), unhandledState, activeState);
4805       }
4806 
4807       next_interval();
4808     } else {
4809       return;
4810     }
4811   }
4812 }
4813 
4814 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4815 #ifndef PRODUCT
4816   if (TraceLinearScanLevel >= 4) {
4817     #define print_state(state) \
4818     switch(state) {\
4819       case unhandledState: tty->print("unhandled"); break;\
4820       case activeState: tty->print("active"); break;\
4821       case inactiveState: tty->print("inactive"); break;\
4822       case handledState: tty->print("handled"); break;\
4823       default: ShouldNotReachHere(); \
4824     }
4825 
4826     print_state(from); tty->print(" to "); print_state(to);
4827     tty->fill_to(23);
4828     interval->print();
4829 
4830     #undef print_state
4831   }
4832 #endif
4833 }
4834 
4835 
4836 
4837 // **** Implementation of LinearScanWalker **************************
4838 
4839 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4840   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4841   , _move_resolver(allocator)
4842 {
4843   for (int i = 0; i < LinearScan::nof_regs; i++) {
4844     _spill_intervals[i] = new IntervalList(2);
4845   }
4846 }
4847 
4848 
4849 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4850   for (int i = _first_reg; i <= _last_reg; i++) {
4851     _use_pos[i] = max_jint;
4852 
4853     if (!only_process_use_pos) {
4854       _block_pos[i] = max_jint;
4855       _spill_intervals[i]->clear();
4856     }
4857   }
4858 }
4859 
4860 inline void LinearScanWalker::exclude_from_use(int reg) {
4861   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4862   if (reg >= _first_reg && reg <= _last_reg) {
4863     _use_pos[reg] = 0;
4864   }
4865 }
4866 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4867   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4868 
4869   exclude_from_use(i->assigned_reg());
4870   exclude_from_use(i->assigned_regHi());
4871 }
4872 
4873 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4874   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4875 
4876   if (reg >= _first_reg && reg <= _last_reg) {
4877     if (_use_pos[reg] > use_pos) {
4878       _use_pos[reg] = use_pos;
4879     }
4880     if (!only_process_use_pos) {
4881       _spill_intervals[reg]->append(i);
4882     }
4883   }
4884 }
4885 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4886   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4887   if (use_pos != -1) {
4888     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4889     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4890   }
4891 }
4892 
4893 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4894   if (reg >= _first_reg && reg <= _last_reg) {
4895     if (_block_pos[reg] > block_pos) {
4896       _block_pos[reg] = block_pos;
4897     }
4898     if (_use_pos[reg] > block_pos) {
4899       _use_pos[reg] = block_pos;
4900     }
4901   }
4902 }
4903 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4904   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4905   if (block_pos != -1) {
4906     set_block_pos(i->assigned_reg(), i, block_pos);
4907     set_block_pos(i->assigned_regHi(), i, block_pos);
4908   }
4909 }
4910 
4911 
4912 void LinearScanWalker::free_exclude_active_fixed() {
4913   Interval* list = active_first(fixedKind);
4914   while (list != Interval::end()) {
4915     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4916     exclude_from_use(list);
4917     list = list->next();
4918   }
4919 }
4920 
4921 void LinearScanWalker::free_exclude_active_any() {
4922   Interval* list = active_first(anyKind);
4923   while (list != Interval::end()) {
4924     exclude_from_use(list);
4925     list = list->next();
4926   }
4927 }
4928 
4929 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4930   Interval* list = inactive_first(fixedKind);
4931   while (list != Interval::end()) {
4932     if (cur->to() <= list->current_from()) {
4933       assert(list->current_intersects_at(cur) == -1, "must not intersect");
4934       set_use_pos(list, list->current_from(), true);
4935     } else {
4936       set_use_pos(list, list->current_intersects_at(cur), true);
4937     }
4938     list = list->next();
4939   }
4940 }
4941 
4942 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4943   Interval* list = inactive_first(anyKind);
4944   while (list != Interval::end()) {
4945     set_use_pos(list, list->current_intersects_at(cur), true);
4946     list = list->next();
4947   }
4948 }
4949 
4950 void LinearScanWalker::spill_exclude_active_fixed() {
4951   Interval* list = active_first(fixedKind);
4952   while (list != Interval::end()) {
4953     exclude_from_use(list);
4954     list = list->next();
4955   }
4956 }
4957 
4958 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4959   Interval* list = inactive_first(fixedKind);
4960   while (list != Interval::end()) {
4961     if (cur->to() > list->current_from()) {
4962       set_block_pos(list, list->current_intersects_at(cur));
4963     } else {
4964       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4965     }
4966 
4967     list = list->next();
4968   }
4969 }
4970 
4971 void LinearScanWalker::spill_collect_active_any() {
4972   Interval* list = active_first(anyKind);
4973   while (list != Interval::end()) {
4974     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4975     list = list->next();
4976   }
4977 }
4978 
4979 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4980   Interval* list = inactive_first(anyKind);
4981   while (list != Interval::end()) {
4982     if (list->current_intersects(cur)) {
4983       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4984     }
4985     list = list->next();
4986   }
4987 }
4988 
4989 
4990 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4991   // output all moves here. When source and target are equal, the move is
4992   // optimized away later in assign_reg_nums
4993 
4994   op_id = (op_id + 1) & ~1;
4995   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4996   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4997 
4998   // calculate index of instruction inside instruction list of current block
4999   // the minimal index (for a block with no spill moves) can be calculated because the
5000   // numbering of instructions is known.
5001   // When the block already contains spill moves, the index must be increased until the
5002   // correct index is reached.
5003   LIR_OpList* list = op_block->lir()->instructions_list();
5004   int index = (op_id - list->at(0)->id()) / 2;
5005   assert(list->at(index)->id() <= op_id, "error in calculation");
5006 
5007   while (list->at(index)->id() != op_id) {
5008     index++;
5009     assert(0 <= index && index < list->length(), "index out of bounds");
5010   }
5011   assert(1 <= index && index < list->length(), "index out of bounds");
5012   assert(list->at(index)->id() == op_id, "error in calculation");
5013 
5014   // insert new instruction before instruction at position index
5015   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5016   _move_resolver.add_mapping(src_it, dst_it);
5017 }
5018 
5019 
5020 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5021   int from_block_nr = min_block->linear_scan_number();
5022   int to_block_nr = max_block->linear_scan_number();
5023 
5024   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5025   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5026   assert(from_block_nr < to_block_nr, "must cross block boundary");
5027 
5028   // Try to split at end of max_block. If this would be after
5029   // max_split_pos, then use the begin of max_block
5030   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5031   if (optimal_split_pos > max_split_pos) {
5032     optimal_split_pos = max_block->first_lir_instruction_id();
5033   }
5034 
5035   int min_loop_depth = max_block->loop_depth();
5036   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5037     BlockBegin* cur = block_at(i);
5038 
5039     if (cur->loop_depth() < min_loop_depth) {
5040       // block with lower loop-depth found -> split at the end of this block
5041       min_loop_depth = cur->loop_depth();
5042       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5043     }
5044   }
5045   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5046 
5047   return optimal_split_pos;
5048 }
5049 
5050 
5051 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5052   int optimal_split_pos = -1;
5053   if (min_split_pos == max_split_pos) {
5054     // trivial case, no optimization of split position possible
5055     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5056     optimal_split_pos = min_split_pos;
5057 
5058   } else {
5059     assert(min_split_pos < max_split_pos, "must be true then");
5060     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5061 
5062     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5063     // beginning of a block, then min_split_pos is also a possible split position.
5064     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5065     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5066 
5067     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5068     // when an interval ends at the end of the last block of the method
5069     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5070     // block at this op_id)
5071     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5072 
5073     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5074     if (min_block == max_block) {
5075       // split position cannot be moved to block boundary, so split as late as possible
5076       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5077       optimal_split_pos = max_split_pos;
5078 
5079     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5080       // Do not move split position if the interval has a hole before max_split_pos.
5081       // Intervals resulting from Phi-Functions have more than one definition (marked
5082       // as mustHaveRegister) with a hole before each definition. When the register is needed
5083       // for the second definition, an earlier reloading is unnecessary.
5084       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5085       optimal_split_pos = max_split_pos;
5086 
5087     } else {
5088       // seach optimal block boundary between min_split_pos and max_split_pos
5089       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5090 
5091       if (do_loop_optimization) {
5092         // Loop optimization: if a loop-end marker is found between min- and max-position,
5093         // then split before this loop
5094         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5095         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5096 
5097         assert(loop_end_pos > min_split_pos, "invalid order");
5098         if (loop_end_pos < max_split_pos) {
5099           // loop-end marker found between min- and max-position
5100           // if it is not the end marker for the same loop as the min-position, then move
5101           // the max-position to this loop block.
5102           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5103           // of the interval (normally, only mustHaveRegister causes a reloading)
5104           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5105 
5106           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5107           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5108 
5109           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5110           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5111             optimal_split_pos = -1;
5112             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5113           } else {
5114             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5115           }
5116         }
5117       }
5118 
5119       if (optimal_split_pos == -1) {
5120         // not calculated by loop optimization
5121         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5122       }
5123     }
5124   }
5125   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5126 
5127   return optimal_split_pos;
5128 }
5129 
5130 
5131 /*
5132   split an interval at the optimal position between min_split_pos and
5133   max_split_pos in two parts:
5134   1) the left part has already a location assigned
5135   2) the right part is sorted into to the unhandled-list
5136 */
5137 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5138   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5139   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5140 
5141   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5142   assert(current_position() < min_split_pos, "cannot split before current position");
5143   assert(min_split_pos <= max_split_pos,     "invalid order");
5144   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5145 
5146   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5147 
5148   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5149   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5150   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5151 
5152   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5153     // the split position would be just before the end of the interval
5154     // -> no split at all necessary
5155     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5156     return;
5157   }
5158 
5159   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5160   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5161 
5162   if (!allocator()->is_block_begin(optimal_split_pos)) {
5163     // move position before actual instruction (odd op_id)
5164     optimal_split_pos = (optimal_split_pos - 1) | 1;
5165   }
5166 
5167   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5168   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5169   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5170 
5171   Interval* split_part = it->split(optimal_split_pos);
5172 
5173   allocator()->append_interval(split_part);
5174   allocator()->copy_register_flags(it, split_part);
5175   split_part->set_insert_move_when_activated(move_necessary);
5176   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5177 
5178   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5179   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5180   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5181 }
5182 
5183 /*
5184   split an interval at the optimal position between min_split_pos and
5185   max_split_pos in two parts:
5186   1) the left part has already a location assigned
5187   2) the right part is always on the stack and therefore ignored in further processing
5188 */
5189 void LinearScanWalker::split_for_spilling(Interval* it) {
5190   // calculate allowed range of splitting position
5191   int max_split_pos = current_position();
5192   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5193 
5194   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5195   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5196 
5197   assert(it->state() == activeState,     "why spill interval that is not active?");
5198   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5199   assert(min_split_pos <= max_split_pos, "invalid order");
5200   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5201   assert(current_position() < it->to(),  "interval must not end before current position");
5202 
5203   if (min_split_pos == it->from()) {
5204     // the whole interval is never used, so spill it entirely to memory
5205     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5206     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5207 
5208     allocator()->assign_spill_slot(it);
5209     allocator()->change_spill_state(it, min_split_pos);
5210 
5211     // Also kick parent intervals out of register to memory when they have no use
5212     // position. This avoids short interval in register surrounded by intervals in
5213     // memory -> avoid useless moves from memory to register and back
5214     Interval* parent = it;
5215     while (parent != NULL && parent->is_split_child()) {
5216       parent = parent->split_child_before_op_id(parent->from());
5217 
5218       if (parent->assigned_reg() < LinearScan::nof_regs) {
5219         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5220           // parent is never used, so kick it out of its assigned register
5221           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5222           allocator()->assign_spill_slot(parent);
5223         } else {
5224           // do not go further back because the register is actually used by the interval
5225           parent = NULL;
5226         }
5227       }
5228     }
5229 
5230   } else {
5231     // search optimal split pos, split interval and spill only the right hand part
5232     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5233 
5234     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5235     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5236     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5237 
5238     if (!allocator()->is_block_begin(optimal_split_pos)) {
5239       // move position before actual instruction (odd op_id)
5240       optimal_split_pos = (optimal_split_pos - 1) | 1;
5241     }
5242 
5243     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5244     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5245     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5246 
5247     Interval* spilled_part = it->split(optimal_split_pos);
5248     allocator()->append_interval(spilled_part);
5249     allocator()->assign_spill_slot(spilled_part);
5250     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5251 
5252     if (!allocator()->is_block_begin(optimal_split_pos)) {
5253       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5254       insert_move(optimal_split_pos, it, spilled_part);
5255     }
5256 
5257     // the current_split_child is needed later when moves are inserted for reloading
5258     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5259     spilled_part->make_current_split_child();
5260 
5261     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5262     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5263     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5264   }
5265 }
5266 
5267 
5268 void LinearScanWalker::split_stack_interval(Interval* it) {
5269   int min_split_pos = current_position() + 1;
5270   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5271 
5272   split_before_usage(it, min_split_pos, max_split_pos);
5273 }
5274 
5275 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5276   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5277   int max_split_pos = register_available_until;
5278 
5279   split_before_usage(it, min_split_pos, max_split_pos);
5280 }
5281 
5282 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5283   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5284 
5285   int current_pos = current_position();
5286   if (it->state() == inactiveState) {
5287     // the interval is currently inactive, so no spill slot is needed for now.
5288     // when the split part is activated, the interval has a new chance to get a register,
5289     // so in the best case no stack slot is necessary
5290     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5291     split_before_usage(it, current_pos + 1, current_pos + 1);
5292 
5293   } else {
5294     // search the position where the interval must have a register and split
5295     // at the optimal position before.
5296     // The new created part is added to the unhandled list and will get a register
5297     // when it is activated
5298     int min_split_pos = current_pos + 1;
5299     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5300 
5301     split_before_usage(it, min_split_pos, max_split_pos);
5302 
5303     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5304     split_for_spilling(it);
5305   }
5306 }
5307 
5308 
5309 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5310   int min_full_reg = any_reg;
5311   int max_partial_reg = any_reg;
5312 
5313   for (int i = _first_reg; i <= _last_reg; i++) {
5314     if (i == ignore_reg) {
5315       // this register must be ignored
5316 
5317     } else if (_use_pos[i] >= interval_to) {
5318       // this register is free for the full interval
5319       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5320         min_full_reg = i;
5321       }
5322     } else if (_use_pos[i] > reg_needed_until) {
5323       // this register is at least free until reg_needed_until
5324       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5325         max_partial_reg = i;
5326       }
5327     }
5328   }
5329 
5330   if (min_full_reg != any_reg) {
5331     return min_full_reg;
5332   } else if (max_partial_reg != any_reg) {
5333     *need_split = true;
5334     return max_partial_reg;
5335   } else {
5336     return any_reg;
5337   }
5338 }
5339 
5340 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5341   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5342 
5343   int min_full_reg = any_reg;
5344   int max_partial_reg = any_reg;
5345 
5346   for (int i = _first_reg; i < _last_reg; i+=2) {
5347     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5348       // this register is free for the full interval
5349       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5350         min_full_reg = i;
5351       }
5352     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5353       // this register is at least free until reg_needed_until
5354       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5355         max_partial_reg = i;
5356       }
5357     }
5358   }
5359 
5360   if (min_full_reg != any_reg) {
5361     return min_full_reg;
5362   } else if (max_partial_reg != any_reg) {
5363     *need_split = true;
5364     return max_partial_reg;
5365   } else {
5366     return any_reg;
5367   }
5368 }
5369 
5370 
5371 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5372   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5373 
5374   init_use_lists(true);
5375   free_exclude_active_fixed();
5376   free_exclude_active_any();
5377   free_collect_inactive_fixed(cur);
5378   free_collect_inactive_any(cur);
5379   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5380 
5381   // _use_pos contains the start of the next interval that has this register assigned
5382   // (either as a fixed register or a normal allocated register in the past)
5383   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5384   TRACE_LINEAR_SCAN(4, tty->print_cr("      state of registers:"));
5385   TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr("      reg %d: use_pos: %d", i, _use_pos[i]));
5386 
5387   int hint_reg, hint_regHi;
5388   Interval* register_hint = cur->register_hint();
5389   if (register_hint != NULL) {
5390     hint_reg = register_hint->assigned_reg();
5391     hint_regHi = register_hint->assigned_regHi();
5392 
5393     if (allocator()->is_precolored_cpu_interval(register_hint)) {
5394       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5395       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5396     }
5397     TRACE_LINEAR_SCAN(4, tty->print("      hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5398 
5399   } else {
5400     hint_reg = any_reg;
5401     hint_regHi = any_reg;
5402   }
5403   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5404   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5405 
5406   // the register must be free at least until this position
5407   int reg_needed_until = cur->from() + 1;
5408   int interval_to = cur->to();
5409 
5410   bool need_split = false;
5411   int split_pos;
5412   int reg;
5413   int regHi = any_reg;
5414 
5415   if (_adjacent_regs) {
5416     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5417     regHi = reg + 1;
5418     if (reg == any_reg) {
5419       return false;
5420     }
5421     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5422 
5423   } else {
5424     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5425     if (reg == any_reg) {
5426       return false;
5427     }
5428     split_pos = _use_pos[reg];
5429 
5430     if (_num_phys_regs == 2) {
5431       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5432 
5433       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5434         // do not split interval if only one register can be assigned until the split pos
5435         // (when one register is found for the whole interval, split&spill is only
5436         // performed for the hi register)
5437         return false;
5438 
5439       } else if (regHi != any_reg) {
5440         split_pos = MIN2(split_pos, _use_pos[regHi]);
5441 
5442         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5443         if (reg > regHi) {
5444           int temp = reg;
5445           reg = regHi;
5446           regHi = temp;
5447         }
5448       }
5449     }
5450   }
5451 
5452   cur->assign_reg(reg, regHi);
5453   TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5454 
5455   assert(split_pos > 0, "invalid split_pos");
5456   if (need_split) {
5457     // register not available for full interval, so split it
5458     split_when_partial_register_available(cur, split_pos);
5459   }
5460 
5461   // only return true if interval is completely assigned
5462   return _num_phys_regs == 1 || regHi != any_reg;
5463 }
5464 
5465 
5466 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5467   int max_reg = any_reg;
5468 
5469   for (int i = _first_reg; i <= _last_reg; i++) {
5470     if (i == ignore_reg) {
5471       // this register must be ignored
5472 
5473     } else if (_use_pos[i] > reg_needed_until) {
5474       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5475         max_reg = i;
5476       }
5477     }
5478   }
5479 
5480   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5481     *need_split = true;
5482   }
5483 
5484   return max_reg;
5485 }
5486 
5487 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5488   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5489 
5490   int max_reg = any_reg;
5491 
5492   for (int i = _first_reg; i < _last_reg; i+=2) {
5493     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5494       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5495         max_reg = i;
5496       }
5497     }
5498   }
5499 
5500   if (max_reg != any_reg &&
5501       (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5502     *need_split = true;
5503   }
5504 
5505   return max_reg;
5506 }
5507 
5508 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5509   assert(reg != any_reg, "no register assigned");
5510 
5511   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5512     Interval* it = _spill_intervals[reg]->at(i);
5513     remove_from_list(it);
5514     split_and_spill_interval(it);
5515   }
5516 
5517   if (regHi != any_reg) {
5518     IntervalList* processed = _spill_intervals[reg];
5519     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5520       Interval* it = _spill_intervals[regHi]->at(i);
5521       if (processed->find(it) == -1) {
5522         remove_from_list(it);
5523         split_and_spill_interval(it);
5524       }
5525     }
5526   }
5527 }
5528 
5529 
5530 // Split an Interval and spill it to memory so that cur can be placed in a register
5531 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5532   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5533 
5534   // collect current usage of registers
5535   init_use_lists(false);
5536   spill_exclude_active_fixed();
5537   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5538   spill_block_inactive_fixed(cur);
5539   spill_collect_active_any();
5540   spill_collect_inactive_any(cur);
5541 
5542 #ifndef PRODUCT
5543   if (TraceLinearScanLevel >= 4) {
5544     tty->print_cr("      state of registers:");
5545     for (int i = _first_reg; i <= _last_reg; i++) {
5546       tty->print("      reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5547       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5548         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5549       }
5550       tty->cr();
5551     }
5552   }
5553 #endif
5554 
5555   // the register must be free at least until this position
5556   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5557   int interval_to = cur->to();
5558   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5559 
5560   int split_pos = 0;
5561   int use_pos = 0;
5562   bool need_split = false;
5563   int reg, regHi;
5564 
5565   if (_adjacent_regs) {
5566     reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5567     regHi = reg + 1;
5568 
5569     if (reg != any_reg) {
5570       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5571       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5572     }
5573   } else {
5574     reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5575     regHi = any_reg;
5576 
5577     if (reg != any_reg) {
5578       use_pos = _use_pos[reg];
5579       split_pos = _block_pos[reg];
5580 
5581       if (_num_phys_regs == 2) {
5582         if (cur->assigned_reg() != any_reg) {
5583           regHi = reg;
5584           reg = cur->assigned_reg();
5585         } else {
5586           regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5587           if (regHi != any_reg) {
5588             use_pos = MIN2(use_pos, _use_pos[regHi]);
5589             split_pos = MIN2(split_pos, _block_pos[regHi]);
5590           }
5591         }
5592 
5593         if (regHi != any_reg && reg > regHi) {
5594           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5595           int temp = reg;
5596           reg = regHi;
5597           regHi = temp;
5598         }
5599       }
5600     }
5601   }
5602 
5603   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5604     // the first use of cur is later than the spilling position -> spill cur
5605     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5606 
5607     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5608       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5609       // assign a reasonable register and do a bailout in product mode to avoid errors
5610       allocator()->assign_spill_slot(cur);
5611       BAILOUT("LinearScan: no register found");
5612     }
5613 
5614     split_and_spill_interval(cur);
5615   } else {
5616     TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5617     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5618     assert(split_pos > 0, "invalid split_pos");
5619     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5620 
5621     cur->assign_reg(reg, regHi);
5622     if (need_split) {
5623       // register not available for full interval, so split it
5624       split_when_partial_register_available(cur, split_pos);
5625     }
5626 
5627     // perform splitting and spilling for all affected intervalls
5628     split_and_spill_intersecting_intervals(reg, regHi);
5629   }
5630 }
5631 
5632 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5633 #ifdef X86
5634   // fast calculation of intervals that can never get a register because the
5635   // the next instruction is a call that blocks all registers
5636   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5637 
5638   // check if this interval is the result of a split operation
5639   // (an interval got a register until this position)
5640   int pos = cur->from();
5641   if ((pos & 1) == 1) {
5642     // the current instruction is a call that blocks all registers
5643     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5644       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5645 
5646       // safety check that there is really no register available
5647       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5648       return true;
5649     }
5650 
5651   }
5652 #endif
5653   return false;
5654 }
5655 
5656 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5657   BasicType type = cur->type();
5658   _num_phys_regs = LinearScan::num_physical_regs(type);
5659   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5660 
5661   if (pd_init_regs_for_alloc(cur)) {
5662     // the appropriate register range was selected.
5663   } else if (type == T_FLOAT || type == T_DOUBLE) {
5664     _first_reg = pd_first_fpu_reg;
5665     _last_reg = pd_last_fpu_reg;
5666   } else {
5667     _first_reg = pd_first_cpu_reg;
5668     _last_reg = FrameMap::last_cpu_reg();
5669   }
5670 
5671   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5672   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5673 }
5674 
5675 
5676 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5677   if (op->code() != lir_move) {
5678     return false;
5679   }
5680   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5681 
5682   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5683   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5684   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5685 }
5686 
5687 // optimization (especially for phi functions of nested loops):
5688 // assign same spill slot to non-intersecting intervals
5689 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5690   if (cur->is_split_child()) {
5691     // optimization is only suitable for split parents
5692     return;
5693   }
5694 
5695   Interval* register_hint = cur->register_hint(false);
5696   if (register_hint == NULL) {
5697     // cur is not the target of a move, otherwise register_hint would be set
5698     return;
5699   }
5700   assert(register_hint->is_split_parent(), "register hint must be split parent");
5701 
5702   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5703     // combining the stack slots for intervals where spill move optimization is applied
5704     // is not benefitial and would cause problems
5705     return;
5706   }
5707 
5708   int begin_pos = cur->from();
5709   int end_pos = cur->to();
5710   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5711     // safety check that lir_op_with_id is allowed
5712     return;
5713   }
5714 
5715   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5716     // cur and register_hint are not connected with two moves
5717     return;
5718   }
5719 
5720   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5721   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5722   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5723     // register_hint must be split, otherwise the re-writing of use positions does not work
5724     return;
5725   }
5726 
5727   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5728   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5729   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5730   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5731 
5732   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5733     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5734     return;
5735   }
5736   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5737 
5738   // modify intervals such that cur gets the same stack slot as register_hint
5739   // delete use positions to prevent the intervals to get a register at beginning
5740   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5741   cur->remove_first_use_pos();
5742   end_hint->remove_first_use_pos();
5743 }
5744 
5745 
5746 // allocate a physical register or memory location to an interval
5747 bool LinearScanWalker::activate_current() {
5748   Interval* cur = current();
5749   bool result = true;
5750 
5751   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5752   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5753 
5754   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5755     // activating an interval that has a stack slot assigned -> split it at first use position
5756     // used for method parameters
5757     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5758 
5759     split_stack_interval(cur);
5760     result = false;
5761 
5762   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5763     // activating an interval that must start in a stack slot, but may get a register later
5764     // used for lir_roundfp: rounding is done by store to stack and reload later
5765     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5766     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5767 
5768     allocator()->assign_spill_slot(cur);
5769     split_stack_interval(cur);
5770     result = false;
5771 
5772   } else if (cur->assigned_reg() == any_reg) {
5773     // interval has not assigned register -> normal allocation
5774     // (this is the normal case for most intervals)
5775     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5776 
5777     // assign same spill slot to non-intersecting intervals
5778     combine_spilled_intervals(cur);
5779 
5780     init_vars_for_alloc(cur);
5781     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5782       // no empty register available.
5783       // split and spill another interval so that this interval gets a register
5784       alloc_locked_reg(cur);
5785     }
5786 
5787     // spilled intervals need not be move to active-list
5788     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5789       result = false;
5790     }
5791   }
5792 
5793   // load spilled values that become active from stack slot to register
5794   if (cur->insert_move_when_activated()) {
5795     assert(cur->is_split_child(), "must be");
5796     assert(cur->current_split_child() != NULL, "must be");
5797     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5798     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5799 
5800     insert_move(cur->from(), cur->current_split_child(), cur);
5801   }
5802   cur->make_current_split_child();
5803 
5804   return result; // true = interval is moved to active list
5805 }
5806 
5807 
5808 // Implementation of EdgeMoveOptimizer
5809 
5810 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5811   _edge_instructions(4),
5812   _edge_instructions_idx(4)
5813 {
5814 }
5815 
5816 void EdgeMoveOptimizer::optimize(BlockList* code) {
5817   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5818 
5819   // ignore the first block in the list (index 0 is not processed)
5820   for (int i = code->length() - 1; i >= 1; i--) {
5821     BlockBegin* block = code->at(i);
5822 
5823     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5824       optimizer.optimize_moves_at_block_end(block);
5825     }
5826     if (block->number_of_sux() == 2) {
5827       optimizer.optimize_moves_at_block_begin(block);
5828     }
5829   }
5830 }
5831 
5832 
5833 // clear all internal data structures
5834 void EdgeMoveOptimizer::init_instructions() {
5835   _edge_instructions.clear();
5836   _edge_instructions_idx.clear();
5837 }
5838 
5839 // append a lir-instruction-list and the index of the current operation in to the list
5840 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5841   _edge_instructions.append(instructions);
5842   _edge_instructions_idx.append(instructions_idx);
5843 }
5844 
5845 // return the current operation of the given edge (predecessor or successor)
5846 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5847   LIR_OpList* instructions = _edge_instructions.at(edge);
5848   int idx = _edge_instructions_idx.at(edge);
5849 
5850   if (idx < instructions->length()) {
5851     return instructions->at(idx);
5852   } else {
5853     return NULL;
5854   }
5855 }
5856 
5857 // removes the current operation of the given edge (predecessor or successor)
5858 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5859   LIR_OpList* instructions = _edge_instructions.at(edge);
5860   int idx = _edge_instructions_idx.at(edge);
5861   instructions->remove_at(idx);
5862 
5863   if (decrement_index) {
5864     _edge_instructions_idx.at_put(edge, idx - 1);
5865   }
5866 }
5867 
5868 
5869 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5870   if (op1 == NULL || op2 == NULL) {
5871     // at least one block is already empty -> no optimization possible
5872     return true;
5873   }
5874 
5875   if (op1->code() == lir_move && op2->code() == lir_move) {
5876     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5877     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5878     LIR_Op1* move1 = (LIR_Op1*)op1;
5879     LIR_Op1* move2 = (LIR_Op1*)op2;
5880     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5881       // these moves are exactly equal and can be optimized
5882       return false;
5883     }
5884 
5885   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5886     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5887     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5888     LIR_Op1* fxch1 = (LIR_Op1*)op1;
5889     LIR_Op1* fxch2 = (LIR_Op1*)op2;
5890     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5891       // equal FPU stack operations can be optimized
5892       return false;
5893     }
5894 
5895   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5896     // equal FPU stack operations can be optimized
5897     return false;
5898   }
5899 
5900   // no optimization possible
5901   return true;
5902 }
5903 
5904 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5905   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5906 
5907   if (block->is_predecessor(block)) {
5908     // currently we can't handle this correctly.
5909     return;
5910   }
5911 
5912   init_instructions();
5913   int num_preds = block->number_of_preds();
5914   assert(num_preds > 1, "do not call otherwise");
5915   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5916 
5917   // setup a list with the lir-instructions of all predecessors
5918   int i;
5919   for (i = 0; i < num_preds; i++) {
5920     BlockBegin* pred = block->pred_at(i);
5921     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5922 
5923     if (pred->number_of_sux() != 1) {
5924       // this can happen with switch-statements where multiple edges are between
5925       // the same blocks.
5926       return;
5927     }
5928 
5929     assert(pred->number_of_sux() == 1, "can handle only one successor");
5930     assert(pred->sux_at(0) == block, "invalid control flow");
5931     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5932     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5933     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5934 
5935     if (pred_instructions->last()->info() != NULL) {
5936       // can not optimize instructions when debug info is needed
5937       return;
5938     }
5939 
5940     // ignore the unconditional branch at the end of the block
5941     append_instructions(pred_instructions, pred_instructions->length() - 2);
5942   }
5943 
5944 
5945   // process lir-instructions while all predecessors end with the same instruction
5946   while (true) {
5947     LIR_Op* op = instruction_at(0);
5948     for (i = 1; i < num_preds; i++) {
5949       if (operations_different(op, instruction_at(i))) {
5950         // these instructions are different and cannot be optimized ->
5951         // no further optimization possible
5952         return;
5953       }
5954     }
5955 
5956     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5957 
5958     // insert the instruction at the beginning of the current block
5959     block->lir()->insert_before(1, op);
5960 
5961     // delete the instruction at the end of all predecessors
5962     for (i = 0; i < num_preds; i++) {
5963       remove_cur_instruction(i, true);
5964     }
5965   }
5966 }
5967 
5968 
5969 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5970   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5971 
5972   init_instructions();
5973   int num_sux = block->number_of_sux();
5974 
5975   LIR_OpList* cur_instructions = block->lir()->instructions_list();
5976 
5977   assert(num_sux == 2, "method should not be called otherwise");
5978   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5979   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5980   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5981 
5982   if (cur_instructions->last()->info() != NULL) {
5983     // can no optimize instructions when debug info is needed
5984     return;
5985   }
5986 
5987   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5988   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5989     // not a valid case for optimization
5990     // currently, only blocks that end with two branches (conditional branch followed
5991     // by unconditional branch) are optimized
5992     return;
5993   }
5994 
5995   // now it is guaranteed that the block ends with two branch instructions.
5996   // the instructions are inserted at the end of the block before these two branches
5997   int insert_idx = cur_instructions->length() - 2;
5998 
5999   int i;
6000 #ifdef ASSERT
6001   for (i = insert_idx - 1; i >= 0; i--) {
6002     LIR_Op* op = cur_instructions->at(i);
6003     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6004       assert(false, "block with two successors can have only two branch instructions");
6005     }
6006   }
6007 #endif
6008 
6009   // setup a list with the lir-instructions of all successors
6010   for (i = 0; i < num_sux; i++) {
6011     BlockBegin* sux = block->sux_at(i);
6012     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6013 
6014     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6015 
6016     if (sux->number_of_preds() != 1) {
6017       // this can happen with switch-statements where multiple edges are between
6018       // the same blocks.
6019       return;
6020     }
6021     assert(sux->pred_at(0) == block, "invalid control flow");
6022     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6023 
6024     // ignore the label at the beginning of the block
6025     append_instructions(sux_instructions, 1);
6026   }
6027 
6028   // process lir-instructions while all successors begin with the same instruction
6029   while (true) {
6030     LIR_Op* op = instruction_at(0);
6031     for (i = 1; i < num_sux; i++) {
6032       if (operations_different(op, instruction_at(i))) {
6033         // these instructions are different and cannot be optimized ->
6034         // no further optimization possible
6035         return;
6036       }
6037     }
6038 
6039     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6040 
6041     // insert instruction at end of current block
6042     block->lir()->insert_before(insert_idx, op);
6043     insert_idx++;
6044 
6045     // delete the instructions at the beginning of all successors
6046     for (i = 0; i < num_sux; i++) {
6047       remove_cur_instruction(i, false);
6048     }
6049   }
6050 }
6051 
6052 
6053 // Implementation of ControlFlowOptimizer
6054 
6055 ControlFlowOptimizer::ControlFlowOptimizer() :
6056   _original_preds(4)
6057 {
6058 }
6059 
6060 void ControlFlowOptimizer::optimize(BlockList* code) {
6061   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6062 
6063   // push the OSR entry block to the end so that we're not jumping over it.
6064   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6065   if (osr_entry) {
6066     int index = osr_entry->linear_scan_number();
6067     assert(code->at(index) == osr_entry, "wrong index");
6068     code->remove_at(index);
6069     code->append(osr_entry);
6070   }
6071 
6072   optimizer.reorder_short_loops(code);
6073   optimizer.delete_empty_blocks(code);
6074   optimizer.delete_unnecessary_jumps(code);
6075   optimizer.delete_jumps_to_return(code);
6076 }
6077 
6078 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6079   int i = header_idx + 1;
6080   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6081   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6082     i++;
6083   }
6084 
6085   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6086     int end_idx = i - 1;
6087     BlockBegin* end_block = code->at(end_idx);
6088 
6089     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6090       // short loop from header_idx to end_idx found -> reorder blocks such that
6091       // the header_block is the last block instead of the first block of the loop
6092       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6093                                          end_idx - header_idx + 1,
6094                                          header_block->block_id(), end_block->block_id()));
6095 
6096       for (int j = header_idx; j < end_idx; j++) {
6097         code->at_put(j, code->at(j + 1));
6098       }
6099       code->at_put(end_idx, header_block);
6100 
6101       // correct the flags so that any loop alignment occurs in the right place.
6102       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6103       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6104       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6105     }
6106   }
6107 }
6108 
6109 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6110   for (int i = code->length() - 1; i >= 0; i--) {
6111     BlockBegin* block = code->at(i);
6112 
6113     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6114       reorder_short_loop(code, block, i);
6115     }
6116   }
6117 
6118   DEBUG_ONLY(verify(code));
6119 }
6120 
6121 // only blocks with exactly one successor can be deleted. Such blocks
6122 // must always end with an unconditional branch to this successor
6123 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6124   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6125     return false;
6126   }
6127 
6128   LIR_OpList* instructions = block->lir()->instructions_list();
6129 
6130   assert(instructions->length() >= 2, "block must have label and branch");
6131   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6132   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6133   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6134   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6135 
6136   // block must have exactly one successor
6137 
6138   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6139     return true;
6140   }
6141   return false;
6142 }
6143 
6144 // substitute branch targets in all branch-instructions of this blocks
6145 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6146   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6147 
6148   LIR_OpList* instructions = block->lir()->instructions_list();
6149 
6150   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6151   for (int i = instructions->length() - 1; i >= 1; i--) {
6152     LIR_Op* op = instructions->at(i);
6153 
6154     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6155       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6156       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6157 
6158       if (branch->block() == target_from) {
6159         branch->change_block(target_to);
6160       }
6161       if (branch->ublock() == target_from) {
6162         branch->change_ublock(target_to);
6163       }
6164     }
6165   }
6166 }
6167 
6168 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6169   int old_pos = 0;
6170   int new_pos = 0;
6171   int num_blocks = code->length();
6172 
6173   while (old_pos < num_blocks) {
6174     BlockBegin* block = code->at(old_pos);
6175 
6176     if (can_delete_block(block)) {
6177       BlockBegin* new_target = block->sux_at(0);
6178 
6179       // propagate backward branch target flag for correct code alignment
6180       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6181         new_target->set(BlockBegin::backward_branch_target_flag);
6182       }
6183 
6184       // collect a list with all predecessors that contains each predecessor only once
6185       // the predecessors of cur are changed during the substitution, so a copy of the
6186       // predecessor list is necessary
6187       int j;
6188       _original_preds.clear();
6189       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6190         BlockBegin* pred = block->pred_at(j);
6191         if (_original_preds.find(pred) == -1) {
6192           _original_preds.append(pred);
6193         }
6194       }
6195 
6196       for (j = _original_preds.length() - 1; j >= 0; j--) {
6197         BlockBegin* pred = _original_preds.at(j);
6198         substitute_branch_target(pred, block, new_target);
6199         pred->substitute_sux(block, new_target);
6200       }
6201     } else {
6202       // adjust position of this block in the block list if blocks before
6203       // have been deleted
6204       if (new_pos != old_pos) {
6205         code->at_put(new_pos, code->at(old_pos));
6206       }
6207       new_pos++;
6208     }
6209     old_pos++;
6210   }
6211   code->trunc_to(new_pos);
6212 
6213   DEBUG_ONLY(verify(code));
6214 }
6215 
6216 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6217   // skip the last block because there a branch is always necessary
6218   for (int i = code->length() - 2; i >= 0; i--) {
6219     BlockBegin* block = code->at(i);
6220     LIR_OpList* instructions = block->lir()->instructions_list();
6221 
6222     LIR_Op* last_op = instructions->last();
6223     if (last_op->code() == lir_branch) {
6224       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6225       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6226 
6227       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6228       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6229 
6230       if (last_branch->info() == NULL) {
6231         if (last_branch->block() == code->at(i + 1)) {
6232 
6233           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6234 
6235           // delete last branch instruction
6236           instructions->trunc_to(instructions->length() - 1);
6237 
6238         } else {
6239           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6240           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6241             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6242             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6243 
6244             if (prev_branch->stub() == NULL) {
6245 
6246               LIR_Op2* prev_cmp = NULL;
6247               // There might be a cmove inserted for profiling which depends on the same
6248               // compare. If we change the condition of the respective compare, we have
6249               // to take care of this cmove as well.
6250               LIR_Op2* prev_cmove = NULL;
6251 
6252               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6253                 prev_op = instructions->at(j);
6254                 // check for the cmove
6255                 if (prev_op->code() == lir_cmove) {
6256                   assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6257                   prev_cmove = (LIR_Op2*)prev_op;
6258                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6259                 }
6260                 if (prev_op->code() == lir_cmp) {
6261                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6262                   prev_cmp = (LIR_Op2*)prev_op;
6263                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6264                 }
6265               }
6266               // Guarantee because it is dereferenced below.
6267               guarantee(prev_cmp != NULL, "should have found comp instruction for branch");
6268               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6269 
6270                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6271 
6272                 // eliminate a conditional branch to the immediate successor
6273                 prev_branch->change_block(last_branch->block());
6274                 prev_branch->negate_cond();
6275                 prev_cmp->set_condition(prev_branch->cond());
6276                 instructions->trunc_to(instructions->length() - 1);
6277                 // if we do change the condition, we have to change the cmove as well
6278                 if (prev_cmove != NULL) {
6279                   prev_cmove->set_condition(prev_branch->cond());
6280                   LIR_Opr t = prev_cmove->in_opr1();
6281                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6282                   prev_cmove->set_in_opr2(t);
6283                 }
6284               }
6285             }
6286           }
6287         }
6288       }
6289     }
6290   }
6291 
6292   DEBUG_ONLY(verify(code));
6293 }
6294 
6295 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6296 #ifdef ASSERT
6297   ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6298 #endif
6299 
6300   for (int i = code->length() - 1; i >= 0; i--) {
6301     BlockBegin* block = code->at(i);
6302     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6303     LIR_Op*     cur_last_op = cur_instructions->last();
6304 
6305     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6306     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6307       // the block contains only a label and a return
6308       // if a predecessor ends with an unconditional jump to this block, then the jump
6309       // can be replaced with a return instruction
6310       //
6311       // Note: the original block with only a return statement cannot be deleted completely
6312       //       because the predecessors might have other (conditional) jumps to this block
6313       //       -> this may lead to unnecesary return instructions in the final code
6314 
6315       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6316       assert(block->number_of_sux() == 0 ||
6317              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6318              "blocks that end with return must not have successors");
6319 
6320       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6321       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6322 
6323       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6324         BlockBegin* pred = block->pred_at(j);
6325         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6326         LIR_Op*     pred_last_op = pred_instructions->last();
6327 
6328         if (pred_last_op->code() == lir_branch) {
6329           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6330           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6331 
6332           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6333             // replace the jump to a return with a direct return
6334             // Note: currently the edge between the blocks is not deleted
6335             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6336 #ifdef ASSERT
6337             return_converted.set_bit(pred->block_id());
6338 #endif
6339           }
6340         }
6341       }
6342     }
6343   }
6344 }
6345 
6346 
6347 #ifdef ASSERT
6348 void ControlFlowOptimizer::verify(BlockList* code) {
6349   for (int i = 0; i < code->length(); i++) {
6350     BlockBegin* block = code->at(i);
6351     LIR_OpList* instructions = block->lir()->instructions_list();
6352 
6353     int j;
6354     for (j = 0; j < instructions->length(); j++) {
6355       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6356 
6357       if (op_branch != NULL) {
6358         assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6359         assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6360       }
6361     }
6362 
6363     for (j = 0; j < block->number_of_sux() - 1; j++) {
6364       BlockBegin* sux = block->sux_at(j);
6365       assert(code->find(sux) != -1, "successor not valid");
6366     }
6367 
6368     for (j = 0; j < block->number_of_preds() - 1; j++) {
6369       BlockBegin* pred = block->pred_at(j);
6370       assert(code->find(pred) != -1, "successor not valid");
6371     }
6372   }
6373 }
6374 #endif
6375 
6376 
6377 #ifndef PRODUCT
6378 
6379 // Implementation of LinearStatistic
6380 
6381 const char* LinearScanStatistic::counter_name(int counter_idx) {
6382   switch (counter_idx) {
6383     case counter_method:          return "compiled methods";
6384     case counter_fpu_method:      return "methods using fpu";
6385     case counter_loop_method:     return "methods with loops";
6386     case counter_exception_method:return "methods with xhandler";
6387 
6388     case counter_loop:            return "loops";
6389     case counter_block:           return "blocks";
6390     case counter_loop_block:      return "blocks inside loop";
6391     case counter_exception_block: return "exception handler entries";
6392     case counter_interval:        return "intervals";
6393     case counter_fixed_interval:  return "fixed intervals";
6394     case counter_range:           return "ranges";
6395     case counter_fixed_range:     return "fixed ranges";
6396     case counter_use_pos:         return "use positions";
6397     case counter_fixed_use_pos:   return "fixed use positions";
6398     case counter_spill_slots:     return "spill slots";
6399 
6400     // counter for classes of lir instructions
6401     case counter_instruction:     return "total instructions";
6402     case counter_label:           return "labels";
6403     case counter_entry:           return "method entries";
6404     case counter_return:          return "method returns";
6405     case counter_call:            return "method calls";
6406     case counter_move:            return "moves";
6407     case counter_cmp:             return "compare";
6408     case counter_cond_branch:     return "conditional branches";
6409     case counter_uncond_branch:   return "unconditional branches";
6410     case counter_stub_branch:     return "branches to stub";
6411     case counter_alu:             return "artithmetic + logic";
6412     case counter_alloc:           return "allocations";
6413     case counter_sync:            return "synchronisation";
6414     case counter_throw:           return "throw";
6415     case counter_unwind:          return "unwind";
6416     case counter_typecheck:       return "type+null-checks";
6417     case counter_fpu_stack:       return "fpu-stack";
6418     case counter_misc_inst:       return "other instructions";
6419     case counter_other_inst:      return "misc. instructions";
6420 
6421     // counter for different types of moves
6422     case counter_move_total:      return "total moves";
6423     case counter_move_reg_reg:    return "register->register";
6424     case counter_move_reg_stack:  return "register->stack";
6425     case counter_move_stack_reg:  return "stack->register";
6426     case counter_move_stack_stack:return "stack->stack";
6427     case counter_move_reg_mem:    return "register->memory";
6428     case counter_move_mem_reg:    return "memory->register";
6429     case counter_move_const_any:  return "constant->any";
6430 
6431     case blank_line_1:            return "";
6432     case blank_line_2:            return "";
6433 
6434     default: ShouldNotReachHere(); return "";
6435   }
6436 }
6437 
6438 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6439   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6440     return counter_method;
6441   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6442     return counter_block;
6443   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6444     return counter_instruction;
6445   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6446     return counter_move_total;
6447   }
6448   return invalid_counter;
6449 }
6450 
6451 LinearScanStatistic::LinearScanStatistic() {
6452   for (int i = 0; i < number_of_counters; i++) {
6453     _counters_sum[i] = 0;
6454     _counters_max[i] = -1;
6455   }
6456 
6457 }
6458 
6459 // add the method-local numbers to the total sum
6460 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6461   for (int i = 0; i < number_of_counters; i++) {
6462     _counters_sum[i] += method_statistic._counters_sum[i];
6463     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6464   }
6465 }
6466 
6467 void LinearScanStatistic::print(const char* title) {
6468   if (CountLinearScan || TraceLinearScanLevel > 0) {
6469     tty->cr();
6470     tty->print_cr("***** LinearScan statistic - %s *****", title);
6471 
6472     for (int i = 0; i < number_of_counters; i++) {
6473       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6474         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6475 
6476         LinearScanStatistic::Counter cntr = base_counter(i);
6477         if (cntr != invalid_counter) {
6478           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6479         } else {
6480           tty->print("           ");
6481         }
6482 
6483         if (_counters_max[i] >= 0) {
6484           tty->print("%8d", _counters_max[i]);
6485         }
6486       }
6487       tty->cr();
6488     }
6489   }
6490 }
6491 
6492 void LinearScanStatistic::collect(LinearScan* allocator) {
6493   inc_counter(counter_method);
6494   if (allocator->has_fpu_registers()) {
6495     inc_counter(counter_fpu_method);
6496   }
6497   if (allocator->num_loops() > 0) {
6498     inc_counter(counter_loop_method);
6499   }
6500   inc_counter(counter_loop, allocator->num_loops());
6501   inc_counter(counter_spill_slots, allocator->max_spills());
6502 
6503   int i;
6504   for (i = 0; i < allocator->interval_count(); i++) {
6505     Interval* cur = allocator->interval_at(i);
6506 
6507     if (cur != NULL) {
6508       inc_counter(counter_interval);
6509       inc_counter(counter_use_pos, cur->num_use_positions());
6510       if (LinearScan::is_precolored_interval(cur)) {
6511         inc_counter(counter_fixed_interval);
6512         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6513       }
6514 
6515       Range* range = cur->first();
6516       while (range != Range::end()) {
6517         inc_counter(counter_range);
6518         if (LinearScan::is_precolored_interval(cur)) {
6519           inc_counter(counter_fixed_range);
6520         }
6521         range = range->next();
6522       }
6523     }
6524   }
6525 
6526   bool has_xhandlers = false;
6527   // Note: only count blocks that are in code-emit order
6528   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6529     BlockBegin* cur = allocator->ir()->code()->at(i);
6530 
6531     inc_counter(counter_block);
6532     if (cur->loop_depth() > 0) {
6533       inc_counter(counter_loop_block);
6534     }
6535     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6536       inc_counter(counter_exception_block);
6537       has_xhandlers = true;
6538     }
6539 
6540     LIR_OpList* instructions = cur->lir()->instructions_list();
6541     for (int j = 0; j < instructions->length(); j++) {
6542       LIR_Op* op = instructions->at(j);
6543 
6544       inc_counter(counter_instruction);
6545 
6546       switch (op->code()) {
6547         case lir_label:           inc_counter(counter_label); break;
6548         case lir_std_entry:
6549         case lir_osr_entry:       inc_counter(counter_entry); break;
6550         case lir_return:          inc_counter(counter_return); break;
6551 
6552         case lir_rtcall:
6553         case lir_static_call:
6554         case lir_optvirtual_call:
6555         case lir_virtual_call:    inc_counter(counter_call); break;
6556 
6557         case lir_move: {
6558           inc_counter(counter_move);
6559           inc_counter(counter_move_total);
6560 
6561           LIR_Opr in = op->as_Op1()->in_opr();
6562           LIR_Opr res = op->as_Op1()->result_opr();
6563           if (in->is_register()) {
6564             if (res->is_register()) {
6565               inc_counter(counter_move_reg_reg);
6566             } else if (res->is_stack()) {
6567               inc_counter(counter_move_reg_stack);
6568             } else if (res->is_address()) {
6569               inc_counter(counter_move_reg_mem);
6570             } else {
6571               ShouldNotReachHere();
6572             }
6573           } else if (in->is_stack()) {
6574             if (res->is_register()) {
6575               inc_counter(counter_move_stack_reg);
6576             } else {
6577               inc_counter(counter_move_stack_stack);
6578             }
6579           } else if (in->is_address()) {
6580             assert(res->is_register(), "must be");
6581             inc_counter(counter_move_mem_reg);
6582           } else if (in->is_constant()) {
6583             inc_counter(counter_move_const_any);
6584           } else {
6585             ShouldNotReachHere();
6586           }
6587           break;
6588         }
6589 
6590         case lir_cmp:             inc_counter(counter_cmp); break;
6591 
6592         case lir_branch:
6593         case lir_cond_float_branch: {
6594           LIR_OpBranch* branch = op->as_OpBranch();
6595           if (branch->block() == NULL) {
6596             inc_counter(counter_stub_branch);
6597           } else if (branch->cond() == lir_cond_always) {
6598             inc_counter(counter_uncond_branch);
6599           } else {
6600             inc_counter(counter_cond_branch);
6601           }
6602           break;
6603         }
6604 
6605         case lir_neg:
6606         case lir_add:
6607         case lir_sub:
6608         case lir_mul:
6609         case lir_mul_strictfp:
6610         case lir_div:
6611         case lir_div_strictfp:
6612         case lir_rem:
6613         case lir_sqrt:
6614         case lir_abs:
6615         case lir_log10:
6616         case lir_logic_and:
6617         case lir_logic_or:
6618         case lir_logic_xor:
6619         case lir_shl:
6620         case lir_shr:
6621         case lir_ushr:            inc_counter(counter_alu); break;
6622 
6623         case lir_alloc_object:
6624         case lir_alloc_array:     inc_counter(counter_alloc); break;
6625 
6626         case lir_monaddr:
6627         case lir_lock:
6628         case lir_unlock:          inc_counter(counter_sync); break;
6629 
6630         case lir_throw:           inc_counter(counter_throw); break;
6631 
6632         case lir_unwind:          inc_counter(counter_unwind); break;
6633 
6634         case lir_null_check:
6635         case lir_leal:
6636         case lir_instanceof:
6637         case lir_checkcast:
6638         case lir_store_check:     inc_counter(counter_typecheck); break;
6639 
6640         case lir_fpop_raw:
6641         case lir_fxch:
6642         case lir_fld:             inc_counter(counter_fpu_stack); break;
6643 
6644         case lir_nop:
6645         case lir_push:
6646         case lir_pop:
6647         case lir_convert:
6648         case lir_roundfp:
6649         case lir_cmove:           inc_counter(counter_misc_inst); break;
6650 
6651         default:                  inc_counter(counter_other_inst); break;
6652       }
6653     }
6654   }
6655 
6656   if (has_xhandlers) {
6657     inc_counter(counter_exception_method);
6658   }
6659 }
6660 
6661 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6662   if (CountLinearScan || TraceLinearScanLevel > 0) {
6663 
6664     LinearScanStatistic local_statistic = LinearScanStatistic();
6665 
6666     local_statistic.collect(allocator);
6667     global_statistic.sum_up(local_statistic);
6668 
6669     if (TraceLinearScanLevel > 2) {
6670       local_statistic.print("current local statistic");
6671     }
6672   }
6673 }
6674 
6675 
6676 // Implementation of LinearTimers
6677 
6678 LinearScanTimers::LinearScanTimers() {
6679   for (int i = 0; i < number_of_timers; i++) {
6680     timer(i)->reset();
6681   }
6682 }
6683 
6684 const char* LinearScanTimers::timer_name(int idx) {
6685   switch (idx) {
6686     case timer_do_nothing:               return "Nothing (Time Check)";
6687     case timer_number_instructions:      return "Number Instructions";
6688     case timer_compute_local_live_sets:  return "Local Live Sets";
6689     case timer_compute_global_live_sets: return "Global Live Sets";
6690     case timer_build_intervals:          return "Build Intervals";
6691     case timer_sort_intervals_before:    return "Sort Intervals Before";
6692     case timer_allocate_registers:       return "Allocate Registers";
6693     case timer_resolve_data_flow:        return "Resolve Data Flow";
6694     case timer_sort_intervals_after:     return "Sort Intervals After";
6695     case timer_eliminate_spill_moves:    return "Spill optimization";
6696     case timer_assign_reg_num:           return "Assign Reg Num";
6697     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6698     case timer_optimize_lir:             return "Optimize LIR";
6699     default: ShouldNotReachHere();       return "";
6700   }
6701 }
6702 
6703 void LinearScanTimers::begin_method() {
6704   if (TimeEachLinearScan) {
6705     // reset all timers to measure only current method
6706     for (int i = 0; i < number_of_timers; i++) {
6707       timer(i)->reset();
6708     }
6709   }
6710 }
6711 
6712 void LinearScanTimers::end_method(LinearScan* allocator) {
6713   if (TimeEachLinearScan) {
6714 
6715     double c = timer(timer_do_nothing)->seconds();
6716     double total = 0;
6717     for (int i = 1; i < number_of_timers; i++) {
6718       total += timer(i)->seconds() - c;
6719     }
6720 
6721     if (total >= 0.0005) {
6722       // print all information in one line for automatic processing
6723       tty->print("@"); allocator->compilation()->method()->print_name();
6724 
6725       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6726       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6727       tty->print("@ %d ", allocator->block_count());
6728       tty->print("@ %d ", allocator->num_virtual_regs());
6729       tty->print("@ %d ", allocator->interval_count());
6730       tty->print("@ %d ", allocator->_num_calls);
6731       tty->print("@ %d ", allocator->num_loops());
6732 
6733       tty->print("@ %6.6f ", total);
6734       for (int i = 1; i < number_of_timers; i++) {
6735         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6736       }
6737       tty->cr();
6738     }
6739   }
6740 }
6741 
6742 void LinearScanTimers::print(double total_time) {
6743   if (TimeLinearScan) {
6744     // correction value: sum of dummy-timer that only measures the time that
6745     // is necesary to start and stop itself
6746     double c = timer(timer_do_nothing)->seconds();
6747 
6748     for (int i = 0; i < number_of_timers; i++) {
6749       double t = timer(i)->seconds();
6750       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6751     }
6752   }
6753 }
6754 
6755 #endif // #ifndef PRODUCT
--- EOF ---