466 }
467
468 //------------------------------Ideal------------------------------------------
469 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
470 // Special case constant AND mask
471 const TypeInt *t2 = phase->type( in(2) )->isa_int();
472 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
473 const int mask = t2->get_con();
474 Node *load = in(1);
475 uint lop = load->Opcode();
476
477 // Masking bits off of a Character? Hi bits are already zero.
478 if( lop == Op_LoadUS &&
479 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
480 return new AndINode(load,phase->intcon(mask&0xFFFF));
481
482 // Masking bits off of a Short? Loading a Character does some masking
483 if (can_reshape &&
484 load->outcnt() == 1 && load->unique_out() == this) {
485 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
486 Node *ldus = new LoadUSNode(load->in(MemNode::Control),
487 load->in(MemNode::Memory),
488 load->in(MemNode::Address),
489 load->adr_type(),
490 TypeInt::CHAR, MemNode::unordered);
491 ldus = phase->transform(ldus);
492 return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
493 }
494
495 // Masking sign bits off of a Byte? Do an unsigned byte load plus
496 // an and.
497 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
498 Node* ldub = new LoadUBNode(load->in(MemNode::Control),
499 load->in(MemNode::Memory),
500 load->in(MemNode::Address),
501 load->adr_type(),
502 TypeInt::UBYTE, MemNode::unordered);
503 ldub = phase->transform(ldub);
504 return new AndINode(ldub, phase->intcon(mask));
505 }
506 }
507
508 // Masking off sign bits? Dont make them!
509 if( lop == Op_RShiftI ) {
510 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
511 if( t12 && t12->is_con() ) { // Shift is by a constant
512 int shift = t12->get_con();
513 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
514 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
515 // If the AND'ing of the 2 masks has no bits, then only original shifted
516 // bits survive. NO sign-extension bits survive the maskings.
517 if( (sign_bits_mask & mask) == 0 ) {
518 // Use zero-fill shift instead
519 Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
520 return new AndINode( zshift, in(2) );
521 }
522 }
917 if( shl->Opcode() != Op_LShiftI ) return NULL;
918
919 if( shift == 16 &&
920 (t3 = phase->type(shl->in(2))->isa_int()) &&
921 t3->is_con(16) ) {
922 Node *ld = shl->in(1);
923 if( ld->Opcode() == Op_LoadS ) {
924 // Sign extension is just useless here. Return a RShiftI of zero instead
925 // returning 'ld' directly. We cannot return an old Node directly as
926 // that is the job of 'Identity' calls and Identity calls only work on
927 // direct inputs ('ld' is an extra Node removed from 'this'). The
928 // combined optimization requires Identity only return direct inputs.
929 set_req(1, ld);
930 set_req(2, phase->intcon(0));
931 return this;
932 }
933 else if( can_reshape &&
934 ld->Opcode() == Op_LoadUS &&
935 ld->outcnt() == 1 && ld->unique_out() == shl)
936 // Replace zero-extension-load with sign-extension-load
937 return new LoadSNode( ld->in(MemNode::Control),
938 ld->in(MemNode::Memory),
939 ld->in(MemNode::Address),
940 ld->adr_type(), TypeInt::SHORT,
941 MemNode::unordered);
942 }
943
944 // Check for "(byte[i] <<24)>>24" which simply sign-extends
945 if( shift == 24 &&
946 (t3 = phase->type(shl->in(2))->isa_int()) &&
947 t3->is_con(24) ) {
948 Node *ld = shl->in(1);
949 if( ld->Opcode() == Op_LoadB ) {
950 // Sign extension is just useless here
951 set_req(1, ld);
952 set_req(2, phase->intcon(0));
953 return this;
954 }
955 }
956
957 return NULL;
958 }
959
960 //------------------------------Value------------------------------------------
961 // A RShiftINode shifts its input2 right by input1 amount.
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466 }
467
468 //------------------------------Ideal------------------------------------------
469 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
470 // Special case constant AND mask
471 const TypeInt *t2 = phase->type( in(2) )->isa_int();
472 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
473 const int mask = t2->get_con();
474 Node *load = in(1);
475 uint lop = load->Opcode();
476
477 // Masking bits off of a Character? Hi bits are already zero.
478 if( lop == Op_LoadUS &&
479 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
480 return new AndINode(load,phase->intcon(mask&0xFFFF));
481
482 // Masking bits off of a Short? Loading a Character does some masking
483 if (can_reshape &&
484 load->outcnt() == 1 && load->unique_out() == this) {
485 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
486 Node* ldus = load->as_Load()->convert_to_unsigned_load(*phase);
487 ldus = phase->transform(ldus);
488 return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
489 }
490
491 // Masking sign bits off of a Byte? Do an unsigned byte load plus
492 // an and.
493 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
494 Node* ldub = load->as_Load()->convert_to_unsigned_load(*phase);
495 ldub = phase->transform(ldub);
496 return new AndINode(ldub, phase->intcon(mask));
497 }
498 }
499
500 // Masking off sign bits? Dont make them!
501 if( lop == Op_RShiftI ) {
502 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
503 if( t12 && t12->is_con() ) { // Shift is by a constant
504 int shift = t12->get_con();
505 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
506 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
507 // If the AND'ing of the 2 masks has no bits, then only original shifted
508 // bits survive. NO sign-extension bits survive the maskings.
509 if( (sign_bits_mask & mask) == 0 ) {
510 // Use zero-fill shift instead
511 Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
512 return new AndINode( zshift, in(2) );
513 }
514 }
909 if( shl->Opcode() != Op_LShiftI ) return NULL;
910
911 if( shift == 16 &&
912 (t3 = phase->type(shl->in(2))->isa_int()) &&
913 t3->is_con(16) ) {
914 Node *ld = shl->in(1);
915 if( ld->Opcode() == Op_LoadS ) {
916 // Sign extension is just useless here. Return a RShiftI of zero instead
917 // returning 'ld' directly. We cannot return an old Node directly as
918 // that is the job of 'Identity' calls and Identity calls only work on
919 // direct inputs ('ld' is an extra Node removed from 'this'). The
920 // combined optimization requires Identity only return direct inputs.
921 set_req(1, ld);
922 set_req(2, phase->intcon(0));
923 return this;
924 }
925 else if( can_reshape &&
926 ld->Opcode() == Op_LoadUS &&
927 ld->outcnt() == 1 && ld->unique_out() == shl)
928 // Replace zero-extension-load with sign-extension-load
929 return ld->as_Load()->convert_to_signed_load(*phase);
930 }
931
932 // Check for "(byte[i] <<24)>>24" which simply sign-extends
933 if( shift == 24 &&
934 (t3 = phase->type(shl->in(2))->isa_int()) &&
935 t3->is_con(24) ) {
936 Node *ld = shl->in(1);
937 if( ld->Opcode() == Op_LoadB ) {
938 // Sign extension is just useless here
939 set_req(1, ld);
940 set_req(2, phase->intcon(0));
941 return this;
942 }
943 }
944
945 return NULL;
946 }
947
948 //------------------------------Value------------------------------------------
949 // A RShiftINode shifts its input2 right by input1 amount.
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