1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "vmreg_x86.inline.hpp"
44
45
46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
47 // instructions, to allow sign-masking or sign-bit flipping. They allow
48 // fast versions of NegF/NegD and AbsF/AbsD.
49
50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
53 // of 128-bits operands for SSE instructions.
54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
55 // Store the value to a 128-bits operand.
56 operand[0] = lo;
57 operand[1] = hi;
58 return operand;
59 }
60
61 // Buffer for 128-bits masks used by SSE instructions.
62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
63
64 // Static initialization during VM startup.
65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
69
70
71 NEEDS_CLEANUP // remove this definitions ?
72 const Register IC_Klass = rax; // where the IC klass is cached
73 const Register SYNC_header = rax; // synchronization header
74 const Register SHIFT_count = rcx; // where count for shift operations must be
75
76 #define __ _masm->
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp2 = extra;
89 }
90 assert_different_registers(preserve, tmp1, tmp2);
91 }
92
93
94
95 static void select_different_registers(Register preserve,
96 Register extra,
97 Register &tmp1,
98 Register &tmp2,
99 Register &tmp3) {
100 if (tmp1 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp1 = extra;
103 } else if (tmp2 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp2 = extra;
106 } else if (tmp3 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp3 = extra;
109 }
110 assert_different_registers(preserve, tmp1, tmp2, tmp3);
111 }
112
113
114
115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
116 if (opr->is_constant()) {
117 LIR_Const* constant = opr->as_constant_ptr();
118 switch (constant->type()) {
119 case T_INT: {
120 return true;
121 }
122
123 default:
124 return false;
125 }
126 }
127 return false;
128 }
129
130
131 LIR_Opr LIR_Assembler::receiverOpr() {
132 return FrameMap::receiver_opr;
133 }
134
135 LIR_Opr LIR_Assembler::osrBufferPointer() {
136 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
137 }
138
139 //--------------fpu register translations-----------------------
140
141
142 address LIR_Assembler::float_constant(float f) {
143 address const_addr = __ float_constant(f);
144 if (const_addr == NULL) {
145 bailout("const section overflow");
146 return __ code()->consts()->start();
147 } else {
148 return const_addr;
149 }
150 }
151
152
153 address LIR_Assembler::double_constant(double d) {
154 address const_addr = __ double_constant(d);
155 if (const_addr == NULL) {
156 bailout("const section overflow");
157 return __ code()->consts()->start();
158 } else {
159 return const_addr;
160 }
161 }
162
163
164 void LIR_Assembler::set_24bit_FPU() {
165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
166 }
167
168 void LIR_Assembler::reset_FPU() {
169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
170 }
171
172 void LIR_Assembler::fpop() {
173 __ fpop();
174 }
175
176 void LIR_Assembler::fxch(int i) {
177 __ fxch(i);
178 }
179
180 void LIR_Assembler::fld(int i) {
181 __ fld_s(i);
182 }
183
184 void LIR_Assembler::ffree(int i) {
185 __ ffree(i);
186 }
187
188 void LIR_Assembler::breakpoint() {
189 __ int3();
190 }
191
192 void LIR_Assembler::push(LIR_Opr opr) {
193 if (opr->is_single_cpu()) {
194 __ push_reg(opr->as_register());
195 } else if (opr->is_double_cpu()) {
196 NOT_LP64(__ push_reg(opr->as_register_hi()));
197 __ push_reg(opr->as_register_lo());
198 } else if (opr->is_stack()) {
199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
200 } else if (opr->is_constant()) {
201 LIR_Const* const_opr = opr->as_constant_ptr();
202 if (const_opr->type() == T_OBJECT) {
203 __ push_oop(const_opr->as_jobject());
204 } else if (const_opr->type() == T_INT) {
205 __ push_jint(const_opr->as_jint());
206 } else {
207 ShouldNotReachHere();
208 }
209
210 } else {
211 ShouldNotReachHere();
212 }
213 }
214
215 void LIR_Assembler::pop(LIR_Opr opr) {
216 if (opr->is_single_cpu()) {
217 __ pop_reg(opr->as_register());
218 } else {
219 ShouldNotReachHere();
220 }
221 }
222
223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
224 return addr->base()->is_illegal() && addr->index()->is_illegal();
225 }
226
227 //-------------------------------------------
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr) {
230 return as_Address(addr, rscratch1);
231 }
232
233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
234 if (addr->base()->is_illegal()) {
235 assert(addr->index()->is_illegal(), "must be illegal too");
236 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
237 if (! __ reachable(laddr)) {
238 __ movptr(tmp, laddr.addr());
239 Address res(tmp, 0);
240 return res;
241 } else {
242 return __ as_Address(laddr);
243 }
244 }
245
246 Register base = addr->base()->as_pointer_register();
247
248 if (addr->index()->is_illegal()) {
249 return Address( base, addr->disp());
250 } else if (addr->index()->is_cpu_register()) {
251 Register index = addr->index()->as_pointer_register();
252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
253 } else if (addr->index()->is_constant()) {
254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
255 assert(Assembler::is_simm32(addr_offset), "must be");
256
257 return Address(base, addr_offset);
258 } else {
259 Unimplemented();
260 return Address();
261 }
262 }
263
264
265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
266 Address base = as_Address(addr);
267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
268 }
269
270
271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
272 return as_Address(addr);
273 }
274
275
276 void LIR_Assembler::osr_entry() {
277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
278 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
279 ValueStack* entry_state = osr_entry->state();
280 int number_of_locks = entry_state->locks_size();
281
282 // we jump here if osr happens with the interpreter
283 // state set up to continue at the beginning of the
284 // loop that triggered osr - in particular, we have
285 // the following registers setup:
286 //
287 // rcx: osr buffer
288 //
289
290 // build frame
291 ciMethod* m = compilation()->method();
292 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
293
294 // OSR buffer is
295 //
296 // locals[nlocals-1..0]
297 // monitors[0..number_of_locks]
298 //
299 // locals is a direct copy of the interpreter frame so in the osr buffer
300 // so first slot in the local array is the last local from the interpreter
301 // and last slot is local[0] (receiver) from the interpreter
302 //
303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
305 // in the interpreter frame (the method lock if a sync method)
306
307 // Initialize monitors in the compiled activation.
308 // rcx: pointer to osr buffer
309 //
310 // All other registers are dead at this point and the locals will be
311 // copied into place by code emitted in the IR.
312
313 Register OSR_buf = osrBufferPointer()->as_pointer_register();
314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
315 int monitor_offset = BytesPerWord * method()->max_locals() +
316 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
318 // the OSR buffer using 2 word entries: first the lock and then
319 // the oop.
320 for (int i = 0; i < number_of_locks; i++) {
321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
322 #ifdef ASSERT
323 // verify the interpreter's monitor has a non-null object
324 {
325 Label L;
326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
327 __ jcc(Assembler::notZero, L);
328 __ stop("locked object is NULL");
329 __ bind(L);
330 }
331 #endif
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
335 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
336 }
337 }
338 }
339
340
341 // inline cache check; done before the frame is built.
342 int LIR_Assembler::check_icache() {
343 Register receiver = FrameMap::receiver_opr->as_register();
344 Register ic_klass = IC_Klass;
345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
346 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
347 if (!do_post_padding) {
348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
349 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
350 }
351 int offset = __ offset();
352 __ inline_cache_check(receiver, IC_Klass);
353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
354 if (do_post_padding) {
355 // force alignment after the cache check.
356 // It's been verified to be aligned if !VerifyOops
357 __ align(CodeEntryAlignment);
358 }
359 return offset;
360 }
361
362 void LIR_Assembler::clinit_barrier(ciMethod* method) {
363 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
364 assert(method->holder()->is_being_initialized() || method->holder()->is_initialized(),
365 "initialization should have been started");
366
367 Label L_skip_barrier;
368 Register klass = rscratch1;
369 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
370 assert(thread != noreg, "x86_32 not implemented");
371
372 __ mov_metadata(klass, method->holder()->constant_encoding());
373 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
374
375 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
376
377 __ bind(L_skip_barrier);
378 }
379
380 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
381 jobject o = NULL;
382 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
383 __ movoop(reg, o);
384 patching_epilog(patch, lir_patch_normal, reg, info);
385 }
386
387 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
388 Metadata* o = NULL;
389 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
390 __ mov_metadata(reg, o);
391 patching_epilog(patch, lir_patch_normal, reg, info);
392 }
393
394 // This specifies the rsp decrement needed to build the frame
395 int LIR_Assembler::initial_frame_size_in_bytes() const {
396 // if rounding, must let FrameMap know!
397
398 // The frame_map records size in slots (32bit word)
399
400 // subtract two words to account for return address and link
401 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
402 }
403
404
405 int LIR_Assembler::emit_exception_handler() {
406 // if the last instruction is a call (typically to do a throw which
407 // is coming at the end after block reordering) the return address
408 // must still point into the code area in order to avoid assertion
409 // failures when searching for the corresponding bci => add a nop
410 // (was bug 5/14/1999 - gri)
411 __ nop();
412
413 // generate code for exception handler
414 address handler_base = __ start_a_stub(exception_handler_size());
415 if (handler_base == NULL) {
416 // not enough space left for the handler
417 bailout("exception handler overflow");
418 return -1;
419 }
420
421 int offset = code_offset();
422
423 // the exception oop and pc are in rax, and rdx
424 // no other registers need to be preserved, so invalidate them
425 __ invalidate_registers(false, true, true, false, true, true);
426
427 // check that there is really an exception
428 __ verify_not_null_oop(rax);
429
430 // search an exception handler (rax: exception oop, rdx: throwing pc)
431 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
432 __ should_not_reach_here();
433 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
434 __ end_a_stub();
435
436 return offset;
437 }
438
439
440 // Emit the code to remove the frame from the stack in the exception
441 // unwind path.
442 int LIR_Assembler::emit_unwind_handler() {
443 #ifndef PRODUCT
444 if (CommentedAssembly) {
445 _masm->block_comment("Unwind handler");
446 }
447 #endif
448
449 int offset = code_offset();
450
451 // Fetch the exception from TLS and clear out exception related thread state
452 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
453 NOT_LP64(__ get_thread(rsi));
454 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
455 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
456 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
457
458 __ bind(_unwind_handler_entry);
459 __ verify_not_null_oop(rax);
460 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
461 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
462 }
463
464 // Preform needed unlocking
465 MonitorExitStub* stub = NULL;
466 if (method()->is_synchronized()) {
467 monitor_address(0, FrameMap::rax_opr);
468 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
469 __ unlock_object(rdi, rsi, rax, *stub->entry());
470 __ bind(*stub->continuation());
471 }
472
473 if (compilation()->env()->dtrace_method_probes()) {
474 #ifdef _LP64
475 __ mov(rdi, r15_thread);
476 __ mov_metadata(rsi, method()->constant_encoding());
477 #else
478 __ get_thread(rax);
479 __ movptr(Address(rsp, 0), rax);
480 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
481 #endif
482 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
483 }
484
485 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
486 __ mov(rax, rbx); // Restore the exception
487 }
488
489 // remove the activation and dispatch to the unwind handler
490 __ remove_frame(initial_frame_size_in_bytes());
491 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
492
493 // Emit the slow path assembly
494 if (stub != NULL) {
495 stub->emit_code(this);
496 }
497
498 return offset;
499 }
500
501
502 int LIR_Assembler::emit_deopt_handler() {
503 // if the last instruction is a call (typically to do a throw which
504 // is coming at the end after block reordering) the return address
505 // must still point into the code area in order to avoid assertion
506 // failures when searching for the corresponding bci => add a nop
507 // (was bug 5/14/1999 - gri)
508 __ nop();
509
510 // generate code for exception handler
511 address handler_base = __ start_a_stub(deopt_handler_size());
512 if (handler_base == NULL) {
513 // not enough space left for the handler
514 bailout("deopt handler overflow");
515 return -1;
516 }
517
518 int offset = code_offset();
519 InternalAddress here(__ pc());
520
521 __ pushptr(here.addr());
522 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
523 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
524 __ end_a_stub();
525
526 return offset;
527 }
528
529
530 void LIR_Assembler::return_op(LIR_Opr result) {
531 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
532 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
533 assert(result->fpu() == 0, "result must already be on TOS");
534 }
535
536 // Pop the stack before the safepoint code
537 __ remove_frame(initial_frame_size_in_bytes());
538
539 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
540 __ reserved_stack_check();
541 }
542
543 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
544
545 // Note: we do not need to round double result; float result has the right precision
546 // the poll sets the condition code, but no data registers
547
548 if (SafepointMechanism::uses_thread_local_poll()) {
549 #ifdef _LP64
550 const Register poll_addr = rscratch1;
551 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
552 #else
553 const Register poll_addr = rbx;
554 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
555 __ get_thread(poll_addr);
556 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
557 #endif
558 __ relocate(relocInfo::poll_return_type);
559 __ testl(rax, Address(poll_addr, 0));
560 } else {
561 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
562
563 if (Assembler::is_polling_page_far()) {
564 __ lea(rscratch1, polling_page);
565 __ relocate(relocInfo::poll_return_type);
566 __ testl(rax, Address(rscratch1, 0));
567 } else {
568 __ testl(rax, polling_page);
569 }
570 }
571 __ ret(0);
572 }
573
574
575 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
576 guarantee(info != NULL, "Shouldn't be NULL");
577 int offset = __ offset();
578 if (SafepointMechanism::uses_thread_local_poll()) {
579 #ifdef _LP64
580 const Register poll_addr = rscratch1;
581 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
582 #else
583 assert(tmp->is_cpu_register(), "needed");
584 const Register poll_addr = tmp->as_register();
585 __ get_thread(poll_addr);
586 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
587 #endif
588 add_debug_info_for_branch(info);
589 __ relocate(relocInfo::poll_type);
590 address pre_pc = __ pc();
591 __ testl(rax, Address(poll_addr, 0));
592 address post_pc = __ pc();
593 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
594 } else {
595 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
596 if (Assembler::is_polling_page_far()) {
597 __ lea(rscratch1, polling_page);
598 offset = __ offset();
599 add_debug_info_for_branch(info);
600 __ relocate(relocInfo::poll_type);
601 __ testl(rax, Address(rscratch1, 0));
602 } else {
603 add_debug_info_for_branch(info);
604 __ testl(rax, polling_page);
605 }
606 }
607 return offset;
608 }
609
610
611 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
612 if (from_reg != to_reg) __ mov(to_reg, from_reg);
613 }
614
615 void LIR_Assembler::swap_reg(Register a, Register b) {
616 __ xchgptr(a, b);
617 }
618
619
620 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
621 assert(src->is_constant(), "should not call otherwise");
622 assert(dest->is_register(), "should not call otherwise");
623 LIR_Const* c = src->as_constant_ptr();
624
625 switch (c->type()) {
626 case T_INT: {
627 assert(patch_code == lir_patch_none, "no patching handled here");
628 __ movl(dest->as_register(), c->as_jint());
629 break;
630 }
631
632 case T_ADDRESS: {
633 assert(patch_code == lir_patch_none, "no patching handled here");
634 __ movptr(dest->as_register(), c->as_jint());
635 break;
636 }
637
638 case T_LONG: {
639 assert(patch_code == lir_patch_none, "no patching handled here");
640 #ifdef _LP64
641 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
642 #else
643 __ movptr(dest->as_register_lo(), c->as_jint_lo());
644 __ movptr(dest->as_register_hi(), c->as_jint_hi());
645 #endif // _LP64
646 break;
647 }
648
649 case T_OBJECT: {
650 if (patch_code != lir_patch_none) {
651 jobject2reg_with_patching(dest->as_register(), info);
652 } else {
653 __ movoop(dest->as_register(), c->as_jobject());
654 }
655 break;
656 }
657
658 case T_METADATA: {
659 if (patch_code != lir_patch_none) {
660 klass2reg_with_patching(dest->as_register(), info);
661 } else {
662 __ mov_metadata(dest->as_register(), c->as_metadata());
663 }
664 break;
665 }
666
667 case T_FLOAT: {
668 if (dest->is_single_xmm()) {
669 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
670 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
671 } else {
672 __ movflt(dest->as_xmm_float_reg(),
673 InternalAddress(float_constant(c->as_jfloat())));
674 }
675 } else {
676 assert(dest->is_single_fpu(), "must be");
677 assert(dest->fpu_regnr() == 0, "dest must be TOS");
678 if (c->is_zero_float()) {
679 __ fldz();
680 } else if (c->is_one_float()) {
681 __ fld1();
682 } else {
683 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
684 }
685 }
686 break;
687 }
688
689 case T_DOUBLE: {
690 if (dest->is_double_xmm()) {
691 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
692 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
693 } else {
694 __ movdbl(dest->as_xmm_double_reg(),
695 InternalAddress(double_constant(c->as_jdouble())));
696 }
697 } else {
698 assert(dest->is_double_fpu(), "must be");
699 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
700 if (c->is_zero_double()) {
701 __ fldz();
702 } else if (c->is_one_double()) {
703 __ fld1();
704 } else {
705 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
706 }
707 }
708 break;
709 }
710
711 default:
712 ShouldNotReachHere();
713 }
714 }
715
716 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
717 assert(src->is_constant(), "should not call otherwise");
718 assert(dest->is_stack(), "should not call otherwise");
719 LIR_Const* c = src->as_constant_ptr();
720
721 switch (c->type()) {
722 case T_INT: // fall through
723 case T_FLOAT:
724 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
725 break;
726
727 case T_ADDRESS:
728 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
729 break;
730
731 case T_OBJECT:
732 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
733 break;
734
735 case T_LONG: // fall through
736 case T_DOUBLE:
737 #ifdef _LP64
738 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
739 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
740 #else
741 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
742 lo_word_offset_in_bytes), c->as_jint_lo_bits());
743 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
744 hi_word_offset_in_bytes), c->as_jint_hi_bits());
745 #endif // _LP64
746 break;
747
748 default:
749 ShouldNotReachHere();
750 }
751 }
752
753 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
754 assert(src->is_constant(), "should not call otherwise");
755 assert(dest->is_address(), "should not call otherwise");
756 LIR_Const* c = src->as_constant_ptr();
757 LIR_Address* addr = dest->as_address_ptr();
758
759 int null_check_here = code_offset();
760 switch (type) {
761 case T_INT: // fall through
762 case T_FLOAT:
763 __ movl(as_Address(addr), c->as_jint_bits());
764 break;
765
766 case T_ADDRESS:
767 __ movptr(as_Address(addr), c->as_jint_bits());
768 break;
769
770 case T_OBJECT: // fall through
771 case T_ARRAY:
772 if (c->as_jobject() == NULL) {
773 if (UseCompressedOops && !wide) {
774 __ movl(as_Address(addr), (int32_t)NULL_WORD);
775 } else {
776 #ifdef _LP64
777 __ xorptr(rscratch1, rscratch1);
778 null_check_here = code_offset();
779 __ movptr(as_Address(addr), rscratch1);
780 #else
781 __ movptr(as_Address(addr), NULL_WORD);
782 #endif
783 }
784 } else {
785 if (is_literal_address(addr)) {
786 ShouldNotReachHere();
787 __ movoop(as_Address(addr, noreg), c->as_jobject());
788 } else {
789 #ifdef _LP64
790 __ movoop(rscratch1, c->as_jobject());
791 if (UseCompressedOops && !wide) {
792 __ encode_heap_oop(rscratch1);
793 null_check_here = code_offset();
794 __ movl(as_Address_lo(addr), rscratch1);
795 } else {
796 null_check_here = code_offset();
797 __ movptr(as_Address_lo(addr), rscratch1);
798 }
799 #else
800 __ movoop(as_Address(addr), c->as_jobject());
801 #endif
802 }
803 }
804 break;
805
806 case T_LONG: // fall through
807 case T_DOUBLE:
808 #ifdef _LP64
809 if (is_literal_address(addr)) {
810 ShouldNotReachHere();
811 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
812 } else {
813 __ movptr(r10, (intptr_t)c->as_jlong_bits());
814 null_check_here = code_offset();
815 __ movptr(as_Address_lo(addr), r10);
816 }
817 #else
818 // Always reachable in 32bit so this doesn't produce useless move literal
819 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
820 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
821 #endif // _LP64
822 break;
823
824 case T_BOOLEAN: // fall through
825 case T_BYTE:
826 __ movb(as_Address(addr), c->as_jint() & 0xFF);
827 break;
828
829 case T_CHAR: // fall through
830 case T_SHORT:
831 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
832 break;
833
834 default:
835 ShouldNotReachHere();
836 };
837
838 if (info != NULL) {
839 add_debug_info_for_null_check(null_check_here, info);
840 }
841 }
842
843
844 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
845 assert(src->is_register(), "should not call otherwise");
846 assert(dest->is_register(), "should not call otherwise");
847
848 // move between cpu-registers
849 if (dest->is_single_cpu()) {
850 #ifdef _LP64
851 if (src->type() == T_LONG) {
852 // Can do LONG -> OBJECT
853 move_regs(src->as_register_lo(), dest->as_register());
854 return;
855 }
856 #endif
857 assert(src->is_single_cpu(), "must match");
858 if (src->type() == T_OBJECT) {
859 __ verify_oop(src->as_register());
860 }
861 move_regs(src->as_register(), dest->as_register());
862
863 } else if (dest->is_double_cpu()) {
864 #ifdef _LP64
865 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
866 // Surprising to me but we can see move of a long to t_object
867 __ verify_oop(src->as_register());
868 move_regs(src->as_register(), dest->as_register_lo());
869 return;
870 }
871 #endif
872 assert(src->is_double_cpu(), "must match");
873 Register f_lo = src->as_register_lo();
874 Register f_hi = src->as_register_hi();
875 Register t_lo = dest->as_register_lo();
876 Register t_hi = dest->as_register_hi();
877 #ifdef _LP64
878 assert(f_hi == f_lo, "must be same");
879 assert(t_hi == t_lo, "must be same");
880 move_regs(f_lo, t_lo);
881 #else
882 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
883
884
885 if (f_lo == t_hi && f_hi == t_lo) {
886 swap_reg(f_lo, f_hi);
887 } else if (f_hi == t_lo) {
888 assert(f_lo != t_hi, "overwriting register");
889 move_regs(f_hi, t_hi);
890 move_regs(f_lo, t_lo);
891 } else {
892 assert(f_hi != t_lo, "overwriting register");
893 move_regs(f_lo, t_lo);
894 move_regs(f_hi, t_hi);
895 }
896 #endif // LP64
897
898 // special moves from fpu-register to xmm-register
899 // necessary for method results
900 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
901 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
902 __ fld_s(Address(rsp, 0));
903 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
904 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
905 __ fld_d(Address(rsp, 0));
906 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
907 __ fstp_s(Address(rsp, 0));
908 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
909 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
910 __ fstp_d(Address(rsp, 0));
911 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
912
913 // move between xmm-registers
914 } else if (dest->is_single_xmm()) {
915 assert(src->is_single_xmm(), "must match");
916 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
917 } else if (dest->is_double_xmm()) {
918 assert(src->is_double_xmm(), "must match");
919 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
920
921 // move between fpu-registers (no instruction necessary because of fpu-stack)
922 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
923 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
924 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
925 } else {
926 ShouldNotReachHere();
927 }
928 }
929
930 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
931 assert(src->is_register(), "should not call otherwise");
932 assert(dest->is_stack(), "should not call otherwise");
933
934 if (src->is_single_cpu()) {
935 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
936 if (type == T_OBJECT || type == T_ARRAY) {
937 __ verify_oop(src->as_register());
938 __ movptr (dst, src->as_register());
939 } else if (type == T_METADATA) {
940 __ movptr (dst, src->as_register());
941 } else {
942 __ movl (dst, src->as_register());
943 }
944
945 } else if (src->is_double_cpu()) {
946 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
947 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
948 __ movptr (dstLO, src->as_register_lo());
949 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
950
951 } else if (src->is_single_xmm()) {
952 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
953 __ movflt(dst_addr, src->as_xmm_float_reg());
954
955 } else if (src->is_double_xmm()) {
956 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
957 __ movdbl(dst_addr, src->as_xmm_double_reg());
958
959 } else if (src->is_single_fpu()) {
960 assert(src->fpu_regnr() == 0, "argument must be on TOS");
961 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
962 if (pop_fpu_stack) __ fstp_s (dst_addr);
963 else __ fst_s (dst_addr);
964
965 } else if (src->is_double_fpu()) {
966 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
967 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
968 if (pop_fpu_stack) __ fstp_d (dst_addr);
969 else __ fst_d (dst_addr);
970
971 } else {
972 ShouldNotReachHere();
973 }
974 }
975
976
977 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
978 LIR_Address* to_addr = dest->as_address_ptr();
979 PatchingStub* patch = NULL;
980 Register compressed_src = rscratch1;
981
982 if (type == T_ARRAY || type == T_OBJECT) {
983 __ verify_oop(src->as_register());
984 #ifdef _LP64
985 if (UseCompressedOops && !wide) {
986 __ movptr(compressed_src, src->as_register());
987 __ encode_heap_oop(compressed_src);
988 if (patch_code != lir_patch_none) {
989 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
990 }
991 }
992 #endif
993 }
994
995 if (patch_code != lir_patch_none) {
996 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
997 Address toa = as_Address(to_addr);
998 assert(toa.disp() != 0, "must have");
999 }
1000
1001 int null_check_here = code_offset();
1002 switch (type) {
1003 case T_FLOAT: {
1004 if (src->is_single_xmm()) {
1005 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1006 } else {
1007 assert(src->is_single_fpu(), "must be");
1008 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1009 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1010 else __ fst_s (as_Address(to_addr));
1011 }
1012 break;
1013 }
1014
1015 case T_DOUBLE: {
1016 if (src->is_double_xmm()) {
1017 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1018 } else {
1019 assert(src->is_double_fpu(), "must be");
1020 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1021 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1022 else __ fst_d (as_Address(to_addr));
1023 }
1024 break;
1025 }
1026
1027 case T_ARRAY: // fall through
1028 case T_OBJECT: // fall through
1029 if (UseCompressedOops && !wide) {
1030 __ movl(as_Address(to_addr), compressed_src);
1031 } else {
1032 __ movptr(as_Address(to_addr), src->as_register());
1033 }
1034 break;
1035 case T_METADATA:
1036 // We get here to store a method pointer to the stack to pass to
1037 // a dtrace runtime call. This can't work on 64 bit with
1038 // compressed klass ptrs: T_METADATA can be a compressed klass
1039 // ptr or a 64 bit method pointer.
1040 LP64_ONLY(ShouldNotReachHere());
1041 __ movptr(as_Address(to_addr), src->as_register());
1042 break;
1043 case T_ADDRESS:
1044 __ movptr(as_Address(to_addr), src->as_register());
1045 break;
1046 case T_INT:
1047 __ movl(as_Address(to_addr), src->as_register());
1048 break;
1049
1050 case T_LONG: {
1051 Register from_lo = src->as_register_lo();
1052 Register from_hi = src->as_register_hi();
1053 #ifdef _LP64
1054 __ movptr(as_Address_lo(to_addr), from_lo);
1055 #else
1056 Register base = to_addr->base()->as_register();
1057 Register index = noreg;
1058 if (to_addr->index()->is_register()) {
1059 index = to_addr->index()->as_register();
1060 }
1061 if (base == from_lo || index == from_lo) {
1062 assert(base != from_hi, "can't be");
1063 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1064 __ movl(as_Address_hi(to_addr), from_hi);
1065 if (patch != NULL) {
1066 patching_epilog(patch, lir_patch_high, base, info);
1067 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1068 patch_code = lir_patch_low;
1069 }
1070 __ movl(as_Address_lo(to_addr), from_lo);
1071 } else {
1072 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1073 __ movl(as_Address_lo(to_addr), from_lo);
1074 if (patch != NULL) {
1075 patching_epilog(patch, lir_patch_low, base, info);
1076 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1077 patch_code = lir_patch_high;
1078 }
1079 __ movl(as_Address_hi(to_addr), from_hi);
1080 }
1081 #endif // _LP64
1082 break;
1083 }
1084
1085 case T_BYTE: // fall through
1086 case T_BOOLEAN: {
1087 Register src_reg = src->as_register();
1088 Address dst_addr = as_Address(to_addr);
1089 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1090 __ movb(dst_addr, src_reg);
1091 break;
1092 }
1093
1094 case T_CHAR: // fall through
1095 case T_SHORT:
1096 __ movw(as_Address(to_addr), src->as_register());
1097 break;
1098
1099 default:
1100 ShouldNotReachHere();
1101 }
1102 if (info != NULL) {
1103 add_debug_info_for_null_check(null_check_here, info);
1104 }
1105
1106 if (patch_code != lir_patch_none) {
1107 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1108 }
1109 }
1110
1111
1112 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1113 assert(src->is_stack(), "should not call otherwise");
1114 assert(dest->is_register(), "should not call otherwise");
1115
1116 if (dest->is_single_cpu()) {
1117 if (type == T_ARRAY || type == T_OBJECT) {
1118 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1119 __ verify_oop(dest->as_register());
1120 } else if (type == T_METADATA) {
1121 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1122 } else {
1123 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1124 }
1125
1126 } else if (dest->is_double_cpu()) {
1127 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1128 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1129 __ movptr(dest->as_register_lo(), src_addr_LO);
1130 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1131
1132 } else if (dest->is_single_xmm()) {
1133 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1134 __ movflt(dest->as_xmm_float_reg(), src_addr);
1135
1136 } else if (dest->is_double_xmm()) {
1137 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1138 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1139
1140 } else if (dest->is_single_fpu()) {
1141 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1142 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1143 __ fld_s(src_addr);
1144
1145 } else if (dest->is_double_fpu()) {
1146 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1147 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1148 __ fld_d(src_addr);
1149
1150 } else {
1151 ShouldNotReachHere();
1152 }
1153 }
1154
1155
1156 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1157 if (src->is_single_stack()) {
1158 if (type == T_OBJECT || type == T_ARRAY) {
1159 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1160 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1161 } else {
1162 #ifndef _LP64
1163 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1164 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1165 #else
1166 //no pushl on 64bits
1167 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1168 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1169 #endif
1170 }
1171
1172 } else if (src->is_double_stack()) {
1173 #ifdef _LP64
1174 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1175 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1176 #else
1177 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1178 // push and pop the part at src + wordSize, adding wordSize for the previous push
1179 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1180 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1181 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1182 #endif // _LP64
1183
1184 } else {
1185 ShouldNotReachHere();
1186 }
1187 }
1188
1189
1190 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1191 assert(src->is_address(), "should not call otherwise");
1192 assert(dest->is_register(), "should not call otherwise");
1193
1194 LIR_Address* addr = src->as_address_ptr();
1195 Address from_addr = as_Address(addr);
1196
1197 if (addr->base()->type() == T_OBJECT) {
1198 __ verify_oop(addr->base()->as_pointer_register());
1199 }
1200
1201 switch (type) {
1202 case T_BOOLEAN: // fall through
1203 case T_BYTE: // fall through
1204 case T_CHAR: // fall through
1205 case T_SHORT:
1206 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1207 // on pre P6 processors we may get partial register stalls
1208 // so blow away the value of to_rinfo before loading a
1209 // partial word into it. Do it here so that it precedes
1210 // the potential patch point below.
1211 __ xorptr(dest->as_register(), dest->as_register());
1212 }
1213 break;
1214 default:
1215 break;
1216 }
1217
1218 PatchingStub* patch = NULL;
1219 if (patch_code != lir_patch_none) {
1220 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1221 assert(from_addr.disp() != 0, "must have");
1222 }
1223 if (info != NULL) {
1224 add_debug_info_for_null_check_here(info);
1225 }
1226
1227 switch (type) {
1228 case T_FLOAT: {
1229 if (dest->is_single_xmm()) {
1230 __ movflt(dest->as_xmm_float_reg(), from_addr);
1231 } else {
1232 assert(dest->is_single_fpu(), "must be");
1233 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1234 __ fld_s(from_addr);
1235 }
1236 break;
1237 }
1238
1239 case T_DOUBLE: {
1240 if (dest->is_double_xmm()) {
1241 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1242 } else {
1243 assert(dest->is_double_fpu(), "must be");
1244 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1245 __ fld_d(from_addr);
1246 }
1247 break;
1248 }
1249
1250 case T_OBJECT: // fall through
1251 case T_ARRAY: // fall through
1252 if (UseCompressedOops && !wide) {
1253 __ movl(dest->as_register(), from_addr);
1254 } else {
1255 __ movptr(dest->as_register(), from_addr);
1256 }
1257 break;
1258
1259 case T_ADDRESS:
1260 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1261 __ movl(dest->as_register(), from_addr);
1262 } else {
1263 __ movptr(dest->as_register(), from_addr);
1264 }
1265 break;
1266 case T_INT:
1267 __ movl(dest->as_register(), from_addr);
1268 break;
1269
1270 case T_LONG: {
1271 Register to_lo = dest->as_register_lo();
1272 Register to_hi = dest->as_register_hi();
1273 #ifdef _LP64
1274 __ movptr(to_lo, as_Address_lo(addr));
1275 #else
1276 Register base = addr->base()->as_register();
1277 Register index = noreg;
1278 if (addr->index()->is_register()) {
1279 index = addr->index()->as_register();
1280 }
1281 if ((base == to_lo && index == to_hi) ||
1282 (base == to_hi && index == to_lo)) {
1283 // addresses with 2 registers are only formed as a result of
1284 // array access so this code will never have to deal with
1285 // patches or null checks.
1286 assert(info == NULL && patch == NULL, "must be");
1287 __ lea(to_hi, as_Address(addr));
1288 __ movl(to_lo, Address(to_hi, 0));
1289 __ movl(to_hi, Address(to_hi, BytesPerWord));
1290 } else if (base == to_lo || index == to_lo) {
1291 assert(base != to_hi, "can't be");
1292 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1293 __ movl(to_hi, as_Address_hi(addr));
1294 if (patch != NULL) {
1295 patching_epilog(patch, lir_patch_high, base, info);
1296 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1297 patch_code = lir_patch_low;
1298 }
1299 __ movl(to_lo, as_Address_lo(addr));
1300 } else {
1301 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1302 __ movl(to_lo, as_Address_lo(addr));
1303 if (patch != NULL) {
1304 patching_epilog(patch, lir_patch_low, base, info);
1305 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1306 patch_code = lir_patch_high;
1307 }
1308 __ movl(to_hi, as_Address_hi(addr));
1309 }
1310 #endif // _LP64
1311 break;
1312 }
1313
1314 case T_BOOLEAN: // fall through
1315 case T_BYTE: {
1316 Register dest_reg = dest->as_register();
1317 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1318 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1319 __ movsbl(dest_reg, from_addr);
1320 } else {
1321 __ movb(dest_reg, from_addr);
1322 __ shll(dest_reg, 24);
1323 __ sarl(dest_reg, 24);
1324 }
1325 break;
1326 }
1327
1328 case T_CHAR: {
1329 Register dest_reg = dest->as_register();
1330 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1331 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1332 __ movzwl(dest_reg, from_addr);
1333 } else {
1334 __ movw(dest_reg, from_addr);
1335 }
1336 break;
1337 }
1338
1339 case T_SHORT: {
1340 Register dest_reg = dest->as_register();
1341 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1342 __ movswl(dest_reg, from_addr);
1343 } else {
1344 __ movw(dest_reg, from_addr);
1345 __ shll(dest_reg, 16);
1346 __ sarl(dest_reg, 16);
1347 }
1348 break;
1349 }
1350
1351 default:
1352 ShouldNotReachHere();
1353 }
1354
1355 if (patch != NULL) {
1356 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1357 }
1358
1359 if (type == T_ARRAY || type == T_OBJECT) {
1360 #ifdef _LP64
1361 if (UseCompressedOops && !wide) {
1362 __ decode_heap_oop(dest->as_register());
1363 }
1364 #endif
1365
1366 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1367 if (!UseZGC) {
1368 __ verify_oop(dest->as_register());
1369 }
1370 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1371 #ifdef _LP64
1372 if (UseCompressedClassPointers) {
1373 __ decode_klass_not_null(dest->as_register());
1374 }
1375 #endif
1376 }
1377 }
1378
1379
1380 NEEDS_CLEANUP; // This could be static?
1381 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1382 int elem_size = type2aelembytes(type);
1383 switch (elem_size) {
1384 case 1: return Address::times_1;
1385 case 2: return Address::times_2;
1386 case 4: return Address::times_4;
1387 case 8: return Address::times_8;
1388 }
1389 ShouldNotReachHere();
1390 return Address::no_scale;
1391 }
1392
1393
1394 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1395 switch (op->code()) {
1396 case lir_idiv:
1397 case lir_irem:
1398 arithmetic_idiv(op->code(),
1399 op->in_opr1(),
1400 op->in_opr2(),
1401 op->in_opr3(),
1402 op->result_opr(),
1403 op->info());
1404 break;
1405 case lir_fmad:
1406 __ fmad(op->result_opr()->as_xmm_double_reg(),
1407 op->in_opr1()->as_xmm_double_reg(),
1408 op->in_opr2()->as_xmm_double_reg(),
1409 op->in_opr3()->as_xmm_double_reg());
1410 break;
1411 case lir_fmaf:
1412 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1413 op->in_opr1()->as_xmm_float_reg(),
1414 op->in_opr2()->as_xmm_float_reg(),
1415 op->in_opr3()->as_xmm_float_reg());
1416 break;
1417 default: ShouldNotReachHere(); break;
1418 }
1419 }
1420
1421 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1422 #ifdef ASSERT
1423 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1424 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1425 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1426 #endif
1427
1428 if (op->cond() == lir_cond_always) {
1429 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1430 __ jmp (*(op->label()));
1431 } else {
1432 Assembler::Condition acond = Assembler::zero;
1433 if (op->code() == lir_cond_float_branch) {
1434 assert(op->ublock() != NULL, "must have unordered successor");
1435 __ jcc(Assembler::parity, *(op->ublock()->label()));
1436 switch(op->cond()) {
1437 case lir_cond_equal: acond = Assembler::equal; break;
1438 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1439 case lir_cond_less: acond = Assembler::below; break;
1440 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1441 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1442 case lir_cond_greater: acond = Assembler::above; break;
1443 default: ShouldNotReachHere();
1444 }
1445 } else {
1446 switch (op->cond()) {
1447 case lir_cond_equal: acond = Assembler::equal; break;
1448 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1449 case lir_cond_less: acond = Assembler::less; break;
1450 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1451 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1452 case lir_cond_greater: acond = Assembler::greater; break;
1453 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1454 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1455 default: ShouldNotReachHere();
1456 }
1457 }
1458 __ jcc(acond,*(op->label()));
1459 }
1460 }
1461
1462 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1463 LIR_Opr src = op->in_opr();
1464 LIR_Opr dest = op->result_opr();
1465
1466 switch (op->bytecode()) {
1467 case Bytecodes::_i2l:
1468 #ifdef _LP64
1469 __ movl2ptr(dest->as_register_lo(), src->as_register());
1470 #else
1471 move_regs(src->as_register(), dest->as_register_lo());
1472 move_regs(src->as_register(), dest->as_register_hi());
1473 __ sarl(dest->as_register_hi(), 31);
1474 #endif // LP64
1475 break;
1476
1477 case Bytecodes::_l2i:
1478 #ifdef _LP64
1479 __ movl(dest->as_register(), src->as_register_lo());
1480 #else
1481 move_regs(src->as_register_lo(), dest->as_register());
1482 #endif
1483 break;
1484
1485 case Bytecodes::_i2b:
1486 move_regs(src->as_register(), dest->as_register());
1487 __ sign_extend_byte(dest->as_register());
1488 break;
1489
1490 case Bytecodes::_i2c:
1491 move_regs(src->as_register(), dest->as_register());
1492 __ andl(dest->as_register(), 0xFFFF);
1493 break;
1494
1495 case Bytecodes::_i2s:
1496 move_regs(src->as_register(), dest->as_register());
1497 __ sign_extend_short(dest->as_register());
1498 break;
1499
1500
1501 case Bytecodes::_f2d:
1502 case Bytecodes::_d2f:
1503 if (dest->is_single_xmm()) {
1504 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1505 } else if (dest->is_double_xmm()) {
1506 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1507 } else {
1508 assert(src->fpu() == dest->fpu(), "register must be equal");
1509 // do nothing (float result is rounded later through spilling)
1510 }
1511 break;
1512
1513 case Bytecodes::_i2f:
1514 case Bytecodes::_i2d:
1515 if (dest->is_single_xmm()) {
1516 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1517 } else if (dest->is_double_xmm()) {
1518 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1519 } else {
1520 assert(dest->fpu() == 0, "result must be on TOS");
1521 __ movl(Address(rsp, 0), src->as_register());
1522 __ fild_s(Address(rsp, 0));
1523 }
1524 break;
1525
1526 case Bytecodes::_f2i:
1527 case Bytecodes::_d2i:
1528 if (src->is_single_xmm()) {
1529 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1530 } else if (src->is_double_xmm()) {
1531 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1532 } else {
1533 assert(src->fpu() == 0, "input must be on TOS");
1534 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1535 __ fist_s(Address(rsp, 0));
1536 __ movl(dest->as_register(), Address(rsp, 0));
1537 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1538 }
1539
1540 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1541 assert(op->stub() != NULL, "stub required");
1542 __ cmpl(dest->as_register(), 0x80000000);
1543 __ jcc(Assembler::equal, *op->stub()->entry());
1544 __ bind(*op->stub()->continuation());
1545 break;
1546
1547 case Bytecodes::_l2f:
1548 case Bytecodes::_l2d:
1549 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1550 assert(dest->fpu() == 0, "result must be on TOS");
1551
1552 __ movptr(Address(rsp, 0), src->as_register_lo());
1553 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1554 __ fild_d(Address(rsp, 0));
1555 // float result is rounded later through spilling
1556 break;
1557
1558 case Bytecodes::_f2l:
1559 case Bytecodes::_d2l:
1560 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1561 assert(src->fpu() == 0, "input must be on TOS");
1562 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1563
1564 // instruction sequence too long to inline it here
1565 {
1566 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1567 }
1568 break;
1569
1570 default: ShouldNotReachHere();
1571 }
1572 }
1573
1574 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1575 if (op->init_check()) {
1576 add_debug_info_for_null_check_here(op->stub()->info());
1577 __ cmpb(Address(op->klass()->as_register(),
1578 InstanceKlass::init_state_offset()),
1579 InstanceKlass::fully_initialized);
1580 __ jcc(Assembler::notEqual, *op->stub()->entry());
1581 }
1582 __ allocate_object(op->obj()->as_register(),
1583 op->tmp1()->as_register(),
1584 op->tmp2()->as_register(),
1585 op->header_size(),
1586 op->object_size(),
1587 op->klass()->as_register(),
1588 *op->stub()->entry());
1589 __ bind(*op->stub()->continuation());
1590 }
1591
1592 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1593 Register len = op->len()->as_register();
1594 LP64_ONLY( __ movslq(len, len); )
1595
1596 if (UseSlowPath ||
1597 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1598 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1599 __ jmp(*op->stub()->entry());
1600 } else {
1601 Register tmp1 = op->tmp1()->as_register();
1602 Register tmp2 = op->tmp2()->as_register();
1603 Register tmp3 = op->tmp3()->as_register();
1604 if (len == tmp1) {
1605 tmp1 = tmp3;
1606 } else if (len == tmp2) {
1607 tmp2 = tmp3;
1608 } else if (len == tmp3) {
1609 // everything is ok
1610 } else {
1611 __ mov(tmp3, len);
1612 }
1613 __ allocate_array(op->obj()->as_register(),
1614 len,
1615 tmp1,
1616 tmp2,
1617 arrayOopDesc::header_size(op->type()),
1618 array_element_size(op->type()),
1619 op->klass()->as_register(),
1620 *op->stub()->entry());
1621 }
1622 __ bind(*op->stub()->continuation());
1623 }
1624
1625 void LIR_Assembler::type_profile_helper(Register mdo,
1626 ciMethodData *md, ciProfileData *data,
1627 Register recv, Label* update_done) {
1628 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1629 Label next_test;
1630 // See if the receiver is receiver[n].
1631 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1632 __ jccb(Assembler::notEqual, next_test);
1633 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1634 __ addptr(data_addr, DataLayout::counter_increment);
1635 __ jmp(*update_done);
1636 __ bind(next_test);
1637 }
1638
1639 // Didn't find receiver; find next empty slot and fill it in
1640 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1641 Label next_test;
1642 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1643 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1644 __ jccb(Assembler::notEqual, next_test);
1645 __ movptr(recv_addr, recv);
1646 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1647 __ jmp(*update_done);
1648 __ bind(next_test);
1649 }
1650 }
1651
1652 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1653 // we always need a stub for the failure case.
1654 CodeStub* stub = op->stub();
1655 Register obj = op->object()->as_register();
1656 Register k_RInfo = op->tmp1()->as_register();
1657 Register klass_RInfo = op->tmp2()->as_register();
1658 Register dst = op->result_opr()->as_register();
1659 ciKlass* k = op->klass();
1660 Register Rtmp1 = noreg;
1661
1662 // check if it needs to be profiled
1663 ciMethodData* md = NULL;
1664 ciProfileData* data = NULL;
1665
1666 if (op->should_profile()) {
1667 ciMethod* method = op->profiled_method();
1668 assert(method != NULL, "Should have method");
1669 int bci = op->profiled_bci();
1670 md = method->method_data_or_null();
1671 assert(md != NULL, "Sanity");
1672 data = md->bci_to_data(bci);
1673 assert(data != NULL, "need data for type check");
1674 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1675 }
1676 Label profile_cast_success, profile_cast_failure;
1677 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1678 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1679
1680 if (obj == k_RInfo) {
1681 k_RInfo = dst;
1682 } else if (obj == klass_RInfo) {
1683 klass_RInfo = dst;
1684 }
1685 if (k->is_loaded() && !UseCompressedClassPointers) {
1686 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1687 } else {
1688 Rtmp1 = op->tmp3()->as_register();
1689 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1690 }
1691
1692 assert_different_registers(obj, k_RInfo, klass_RInfo);
1693
1694 __ cmpptr(obj, (int32_t)NULL_WORD);
1695 if (op->should_profile()) {
1696 Label not_null;
1697 __ jccb(Assembler::notEqual, not_null);
1698 // Object is null; update MDO and exit
1699 Register mdo = klass_RInfo;
1700 __ mov_metadata(mdo, md->constant_encoding());
1701 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1702 int header_bits = BitData::null_seen_byte_constant();
1703 __ orb(data_addr, header_bits);
1704 __ jmp(*obj_is_null);
1705 __ bind(not_null);
1706 } else {
1707 __ jcc(Assembler::equal, *obj_is_null);
1708 }
1709
1710 if (!k->is_loaded()) {
1711 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1712 } else {
1713 #ifdef _LP64
1714 __ mov_metadata(k_RInfo, k->constant_encoding());
1715 #endif // _LP64
1716 }
1717 __ verify_oop(obj);
1718
1719 if (op->fast_check()) {
1720 // get object class
1721 // not a safepoint as obj null check happens earlier
1722 #ifdef _LP64
1723 if (UseCompressedClassPointers) {
1724 __ load_klass(Rtmp1, obj);
1725 __ cmpptr(k_RInfo, Rtmp1);
1726 } else {
1727 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1728 }
1729 #else
1730 if (k->is_loaded()) {
1731 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1732 } else {
1733 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1734 }
1735 #endif
1736 __ jcc(Assembler::notEqual, *failure_target);
1737 // successful cast, fall through to profile or jump
1738 } else {
1739 // get object class
1740 // not a safepoint as obj null check happens earlier
1741 __ load_klass(klass_RInfo, obj);
1742 if (k->is_loaded()) {
1743 // See if we get an immediate positive hit
1744 #ifdef _LP64
1745 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1746 #else
1747 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1748 #endif // _LP64
1749 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1750 __ jcc(Assembler::notEqual, *failure_target);
1751 // successful cast, fall through to profile or jump
1752 } else {
1753 // See if we get an immediate positive hit
1754 __ jcc(Assembler::equal, *success_target);
1755 // check for self
1756 #ifdef _LP64
1757 __ cmpptr(klass_RInfo, k_RInfo);
1758 #else
1759 __ cmpklass(klass_RInfo, k->constant_encoding());
1760 #endif // _LP64
1761 __ jcc(Assembler::equal, *success_target);
1762
1763 __ push(klass_RInfo);
1764 #ifdef _LP64
1765 __ push(k_RInfo);
1766 #else
1767 __ pushklass(k->constant_encoding());
1768 #endif // _LP64
1769 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1770 __ pop(klass_RInfo);
1771 __ pop(klass_RInfo);
1772 // result is a boolean
1773 __ cmpl(klass_RInfo, 0);
1774 __ jcc(Assembler::equal, *failure_target);
1775 // successful cast, fall through to profile or jump
1776 }
1777 } else {
1778 // perform the fast part of the checking logic
1779 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1780 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1781 __ push(klass_RInfo);
1782 __ push(k_RInfo);
1783 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1784 __ pop(klass_RInfo);
1785 __ pop(k_RInfo);
1786 // result is a boolean
1787 __ cmpl(k_RInfo, 0);
1788 __ jcc(Assembler::equal, *failure_target);
1789 // successful cast, fall through to profile or jump
1790 }
1791 }
1792 if (op->should_profile()) {
1793 Register mdo = klass_RInfo, recv = k_RInfo;
1794 __ bind(profile_cast_success);
1795 __ mov_metadata(mdo, md->constant_encoding());
1796 __ load_klass(recv, obj);
1797 type_profile_helper(mdo, md, data, recv, success);
1798 __ jmp(*success);
1799
1800 __ bind(profile_cast_failure);
1801 __ mov_metadata(mdo, md->constant_encoding());
1802 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1803 __ subptr(counter_addr, DataLayout::counter_increment);
1804 __ jmp(*failure);
1805 }
1806 __ jmp(*success);
1807 }
1808
1809
1810 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1811 LIR_Code code = op->code();
1812 if (code == lir_store_check) {
1813 Register value = op->object()->as_register();
1814 Register array = op->array()->as_register();
1815 Register k_RInfo = op->tmp1()->as_register();
1816 Register klass_RInfo = op->tmp2()->as_register();
1817 Register Rtmp1 = op->tmp3()->as_register();
1818
1819 CodeStub* stub = op->stub();
1820
1821 // check if it needs to be profiled
1822 ciMethodData* md = NULL;
1823 ciProfileData* data = NULL;
1824
1825 if (op->should_profile()) {
1826 ciMethod* method = op->profiled_method();
1827 assert(method != NULL, "Should have method");
1828 int bci = op->profiled_bci();
1829 md = method->method_data_or_null();
1830 assert(md != NULL, "Sanity");
1831 data = md->bci_to_data(bci);
1832 assert(data != NULL, "need data for type check");
1833 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1834 }
1835 Label profile_cast_success, profile_cast_failure, done;
1836 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1837 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1838
1839 __ cmpptr(value, (int32_t)NULL_WORD);
1840 if (op->should_profile()) {
1841 Label not_null;
1842 __ jccb(Assembler::notEqual, not_null);
1843 // Object is null; update MDO and exit
1844 Register mdo = klass_RInfo;
1845 __ mov_metadata(mdo, md->constant_encoding());
1846 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1847 int header_bits = BitData::null_seen_byte_constant();
1848 __ orb(data_addr, header_bits);
1849 __ jmp(done);
1850 __ bind(not_null);
1851 } else {
1852 __ jcc(Assembler::equal, done);
1853 }
1854
1855 add_debug_info_for_null_check_here(op->info_for_exception());
1856 __ load_klass(k_RInfo, array);
1857 __ load_klass(klass_RInfo, value);
1858
1859 // get instance klass (it's already uncompressed)
1860 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1861 // perform the fast part of the checking logic
1862 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1863 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1864 __ push(klass_RInfo);
1865 __ push(k_RInfo);
1866 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1867 __ pop(klass_RInfo);
1868 __ pop(k_RInfo);
1869 // result is a boolean
1870 __ cmpl(k_RInfo, 0);
1871 __ jcc(Assembler::equal, *failure_target);
1872 // fall through to the success case
1873
1874 if (op->should_profile()) {
1875 Register mdo = klass_RInfo, recv = k_RInfo;
1876 __ bind(profile_cast_success);
1877 __ mov_metadata(mdo, md->constant_encoding());
1878 __ load_klass(recv, value);
1879 type_profile_helper(mdo, md, data, recv, &done);
1880 __ jmpb(done);
1881
1882 __ bind(profile_cast_failure);
1883 __ mov_metadata(mdo, md->constant_encoding());
1884 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1885 __ subptr(counter_addr, DataLayout::counter_increment);
1886 __ jmp(*stub->entry());
1887 }
1888
1889 __ bind(done);
1890 } else
1891 if (code == lir_checkcast) {
1892 Register obj = op->object()->as_register();
1893 Register dst = op->result_opr()->as_register();
1894 Label success;
1895 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1896 __ bind(success);
1897 if (dst != obj) {
1898 __ mov(dst, obj);
1899 }
1900 } else
1901 if (code == lir_instanceof) {
1902 Register obj = op->object()->as_register();
1903 Register dst = op->result_opr()->as_register();
1904 Label success, failure, done;
1905 emit_typecheck_helper(op, &success, &failure, &failure);
1906 __ bind(failure);
1907 __ xorptr(dst, dst);
1908 __ jmpb(done);
1909 __ bind(success);
1910 __ movptr(dst, 1);
1911 __ bind(done);
1912 } else {
1913 ShouldNotReachHere();
1914 }
1915
1916 }
1917
1918
1919 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1920 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1921 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1922 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1923 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1924 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1925 Register addr = op->addr()->as_register();
1926 __ lock();
1927 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1928
1929 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1930 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1931 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1932 Register newval = op->new_value()->as_register();
1933 Register cmpval = op->cmp_value()->as_register();
1934 assert(cmpval == rax, "wrong register");
1935 assert(newval != NULL, "new val must be register");
1936 assert(cmpval != newval, "cmp and new values must be in different registers");
1937 assert(cmpval != addr, "cmp and addr must be in different registers");
1938 assert(newval != addr, "new value and addr must be in different registers");
1939
1940 if ( op->code() == lir_cas_obj) {
1941 #ifdef _LP64
1942 if (UseCompressedOops) {
1943 __ encode_heap_oop(cmpval);
1944 __ mov(rscratch1, newval);
1945 __ encode_heap_oop(rscratch1);
1946 __ lock();
1947 // cmpval (rax) is implicitly used by this instruction
1948 __ cmpxchgl(rscratch1, Address(addr, 0));
1949 } else
1950 #endif
1951 {
1952 __ lock();
1953 __ cmpxchgptr(newval, Address(addr, 0));
1954 }
1955 } else {
1956 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1957 __ lock();
1958 __ cmpxchgl(newval, Address(addr, 0));
1959 }
1960 #ifdef _LP64
1961 } else if (op->code() == lir_cas_long) {
1962 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1963 Register newval = op->new_value()->as_register_lo();
1964 Register cmpval = op->cmp_value()->as_register_lo();
1965 assert(cmpval == rax, "wrong register");
1966 assert(newval != NULL, "new val must be register");
1967 assert(cmpval != newval, "cmp and new values must be in different registers");
1968 assert(cmpval != addr, "cmp and addr must be in different registers");
1969 assert(newval != addr, "new value and addr must be in different registers");
1970 __ lock();
1971 __ cmpxchgq(newval, Address(addr, 0));
1972 #endif // _LP64
1973 } else {
1974 Unimplemented();
1975 }
1976 }
1977
1978 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1979 Assembler::Condition acond, ncond;
1980 switch (condition) {
1981 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1982 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1983 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1984 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1985 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1986 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1987 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1988 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1989 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1990 ShouldNotReachHere();
1991 }
1992
1993 if (opr1->is_cpu_register()) {
1994 reg2reg(opr1, result);
1995 } else if (opr1->is_stack()) {
1996 stack2reg(opr1, result, result->type());
1997 } else if (opr1->is_constant()) {
1998 const2reg(opr1, result, lir_patch_none, NULL);
1999 } else {
2000 ShouldNotReachHere();
2001 }
2002
2003 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2004 // optimized version that does not require a branch
2005 if (opr2->is_single_cpu()) {
2006 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2007 __ cmov(ncond, result->as_register(), opr2->as_register());
2008 } else if (opr2->is_double_cpu()) {
2009 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2010 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2011 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2012 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2013 } else if (opr2->is_single_stack()) {
2014 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2015 } else if (opr2->is_double_stack()) {
2016 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2017 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2018 } else {
2019 ShouldNotReachHere();
2020 }
2021
2022 } else {
2023 Label skip;
2024 __ jcc (acond, skip);
2025 if (opr2->is_cpu_register()) {
2026 reg2reg(opr2, result);
2027 } else if (opr2->is_stack()) {
2028 stack2reg(opr2, result, result->type());
2029 } else if (opr2->is_constant()) {
2030 const2reg(opr2, result, lir_patch_none, NULL);
2031 } else {
2032 ShouldNotReachHere();
2033 }
2034 __ bind(skip);
2035 }
2036 }
2037
2038
2039 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2040 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2041
2042 if (left->is_single_cpu()) {
2043 assert(left == dest, "left and dest must be equal");
2044 Register lreg = left->as_register();
2045
2046 if (right->is_single_cpu()) {
2047 // cpu register - cpu register
2048 Register rreg = right->as_register();
2049 switch (code) {
2050 case lir_add: __ addl (lreg, rreg); break;
2051 case lir_sub: __ subl (lreg, rreg); break;
2052 case lir_mul: __ imull(lreg, rreg); break;
2053 default: ShouldNotReachHere();
2054 }
2055
2056 } else if (right->is_stack()) {
2057 // cpu register - stack
2058 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2059 switch (code) {
2060 case lir_add: __ addl(lreg, raddr); break;
2061 case lir_sub: __ subl(lreg, raddr); break;
2062 default: ShouldNotReachHere();
2063 }
2064
2065 } else if (right->is_constant()) {
2066 // cpu register - constant
2067 jint c = right->as_constant_ptr()->as_jint();
2068 switch (code) {
2069 case lir_add: {
2070 __ incrementl(lreg, c);
2071 break;
2072 }
2073 case lir_sub: {
2074 __ decrementl(lreg, c);
2075 break;
2076 }
2077 default: ShouldNotReachHere();
2078 }
2079
2080 } else {
2081 ShouldNotReachHere();
2082 }
2083
2084 } else if (left->is_double_cpu()) {
2085 assert(left == dest, "left and dest must be equal");
2086 Register lreg_lo = left->as_register_lo();
2087 Register lreg_hi = left->as_register_hi();
2088
2089 if (right->is_double_cpu()) {
2090 // cpu register - cpu register
2091 Register rreg_lo = right->as_register_lo();
2092 Register rreg_hi = right->as_register_hi();
2093 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2094 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2095 switch (code) {
2096 case lir_add:
2097 __ addptr(lreg_lo, rreg_lo);
2098 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2099 break;
2100 case lir_sub:
2101 __ subptr(lreg_lo, rreg_lo);
2102 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2103 break;
2104 case lir_mul:
2105 #ifdef _LP64
2106 __ imulq(lreg_lo, rreg_lo);
2107 #else
2108 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2109 __ imull(lreg_hi, rreg_lo);
2110 __ imull(rreg_hi, lreg_lo);
2111 __ addl (rreg_hi, lreg_hi);
2112 __ mull (rreg_lo);
2113 __ addl (lreg_hi, rreg_hi);
2114 #endif // _LP64
2115 break;
2116 default:
2117 ShouldNotReachHere();
2118 }
2119
2120 } else if (right->is_constant()) {
2121 // cpu register - constant
2122 #ifdef _LP64
2123 jlong c = right->as_constant_ptr()->as_jlong_bits();
2124 __ movptr(r10, (intptr_t) c);
2125 switch (code) {
2126 case lir_add:
2127 __ addptr(lreg_lo, r10);
2128 break;
2129 case lir_sub:
2130 __ subptr(lreg_lo, r10);
2131 break;
2132 default:
2133 ShouldNotReachHere();
2134 }
2135 #else
2136 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2137 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2138 switch (code) {
2139 case lir_add:
2140 __ addptr(lreg_lo, c_lo);
2141 __ adcl(lreg_hi, c_hi);
2142 break;
2143 case lir_sub:
2144 __ subptr(lreg_lo, c_lo);
2145 __ sbbl(lreg_hi, c_hi);
2146 break;
2147 default:
2148 ShouldNotReachHere();
2149 }
2150 #endif // _LP64
2151
2152 } else {
2153 ShouldNotReachHere();
2154 }
2155
2156 } else if (left->is_single_xmm()) {
2157 assert(left == dest, "left and dest must be equal");
2158 XMMRegister lreg = left->as_xmm_float_reg();
2159
2160 if (right->is_single_xmm()) {
2161 XMMRegister rreg = right->as_xmm_float_reg();
2162 switch (code) {
2163 case lir_add: __ addss(lreg, rreg); break;
2164 case lir_sub: __ subss(lreg, rreg); break;
2165 case lir_mul_strictfp: // fall through
2166 case lir_mul: __ mulss(lreg, rreg); break;
2167 case lir_div_strictfp: // fall through
2168 case lir_div: __ divss(lreg, rreg); break;
2169 default: ShouldNotReachHere();
2170 }
2171 } else {
2172 Address raddr;
2173 if (right->is_single_stack()) {
2174 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2175 } else if (right->is_constant()) {
2176 // hack for now
2177 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2178 } else {
2179 ShouldNotReachHere();
2180 }
2181 switch (code) {
2182 case lir_add: __ addss(lreg, raddr); break;
2183 case lir_sub: __ subss(lreg, raddr); break;
2184 case lir_mul_strictfp: // fall through
2185 case lir_mul: __ mulss(lreg, raddr); break;
2186 case lir_div_strictfp: // fall through
2187 case lir_div: __ divss(lreg, raddr); break;
2188 default: ShouldNotReachHere();
2189 }
2190 }
2191
2192 } else if (left->is_double_xmm()) {
2193 assert(left == dest, "left and dest must be equal");
2194
2195 XMMRegister lreg = left->as_xmm_double_reg();
2196 if (right->is_double_xmm()) {
2197 XMMRegister rreg = right->as_xmm_double_reg();
2198 switch (code) {
2199 case lir_add: __ addsd(lreg, rreg); break;
2200 case lir_sub: __ subsd(lreg, rreg); break;
2201 case lir_mul_strictfp: // fall through
2202 case lir_mul: __ mulsd(lreg, rreg); break;
2203 case lir_div_strictfp: // fall through
2204 case lir_div: __ divsd(lreg, rreg); break;
2205 default: ShouldNotReachHere();
2206 }
2207 } else {
2208 Address raddr;
2209 if (right->is_double_stack()) {
2210 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2211 } else if (right->is_constant()) {
2212 // hack for now
2213 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2214 } else {
2215 ShouldNotReachHere();
2216 }
2217 switch (code) {
2218 case lir_add: __ addsd(lreg, raddr); break;
2219 case lir_sub: __ subsd(lreg, raddr); break;
2220 case lir_mul_strictfp: // fall through
2221 case lir_mul: __ mulsd(lreg, raddr); break;
2222 case lir_div_strictfp: // fall through
2223 case lir_div: __ divsd(lreg, raddr); break;
2224 default: ShouldNotReachHere();
2225 }
2226 }
2227
2228 } else if (left->is_single_fpu()) {
2229 assert(dest->is_single_fpu(), "fpu stack allocation required");
2230
2231 if (right->is_single_fpu()) {
2232 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2233
2234 } else {
2235 assert(left->fpu_regnr() == 0, "left must be on TOS");
2236 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2237
2238 Address raddr;
2239 if (right->is_single_stack()) {
2240 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2241 } else if (right->is_constant()) {
2242 address const_addr = float_constant(right->as_jfloat());
2243 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2244 // hack for now
2245 raddr = __ as_Address(InternalAddress(const_addr));
2246 } else {
2247 ShouldNotReachHere();
2248 }
2249
2250 switch (code) {
2251 case lir_add: __ fadd_s(raddr); break;
2252 case lir_sub: __ fsub_s(raddr); break;
2253 case lir_mul_strictfp: // fall through
2254 case lir_mul: __ fmul_s(raddr); break;
2255 case lir_div_strictfp: // fall through
2256 case lir_div: __ fdiv_s(raddr); break;
2257 default: ShouldNotReachHere();
2258 }
2259 }
2260
2261 } else if (left->is_double_fpu()) {
2262 assert(dest->is_double_fpu(), "fpu stack allocation required");
2263
2264 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2265 // Double values require special handling for strictfp mul/div on x86
2266 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2267 __ fmulp(left->fpu_regnrLo() + 1);
2268 }
2269
2270 if (right->is_double_fpu()) {
2271 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2272
2273 } else {
2274 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2275 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2276
2277 Address raddr;
2278 if (right->is_double_stack()) {
2279 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2280 } else if (right->is_constant()) {
2281 // hack for now
2282 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2283 } else {
2284 ShouldNotReachHere();
2285 }
2286
2287 switch (code) {
2288 case lir_add: __ fadd_d(raddr); break;
2289 case lir_sub: __ fsub_d(raddr); break;
2290 case lir_mul_strictfp: // fall through
2291 case lir_mul: __ fmul_d(raddr); break;
2292 case lir_div_strictfp: // fall through
2293 case lir_div: __ fdiv_d(raddr); break;
2294 default: ShouldNotReachHere();
2295 }
2296 }
2297
2298 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2299 // Double values require special handling for strictfp mul/div on x86
2300 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2301 __ fmulp(dest->fpu_regnrLo() + 1);
2302 }
2303
2304 } else if (left->is_single_stack() || left->is_address()) {
2305 assert(left == dest, "left and dest must be equal");
2306
2307 Address laddr;
2308 if (left->is_single_stack()) {
2309 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2310 } else if (left->is_address()) {
2311 laddr = as_Address(left->as_address_ptr());
2312 } else {
2313 ShouldNotReachHere();
2314 }
2315
2316 if (right->is_single_cpu()) {
2317 Register rreg = right->as_register();
2318 switch (code) {
2319 case lir_add: __ addl(laddr, rreg); break;
2320 case lir_sub: __ subl(laddr, rreg); break;
2321 default: ShouldNotReachHere();
2322 }
2323 } else if (right->is_constant()) {
2324 jint c = right->as_constant_ptr()->as_jint();
2325 switch (code) {
2326 case lir_add: {
2327 __ incrementl(laddr, c);
2328 break;
2329 }
2330 case lir_sub: {
2331 __ decrementl(laddr, c);
2332 break;
2333 }
2334 default: ShouldNotReachHere();
2335 }
2336 } else {
2337 ShouldNotReachHere();
2338 }
2339
2340 } else {
2341 ShouldNotReachHere();
2342 }
2343 }
2344
2345 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2346 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2347 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2348 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2349
2350 bool left_is_tos = (left_index == 0);
2351 bool dest_is_tos = (dest_index == 0);
2352 int non_tos_index = (left_is_tos ? right_index : left_index);
2353
2354 switch (code) {
2355 case lir_add:
2356 if (pop_fpu_stack) __ faddp(non_tos_index);
2357 else if (dest_is_tos) __ fadd (non_tos_index);
2358 else __ fadda(non_tos_index);
2359 break;
2360
2361 case lir_sub:
2362 if (left_is_tos) {
2363 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2364 else if (dest_is_tos) __ fsub (non_tos_index);
2365 else __ fsubra(non_tos_index);
2366 } else {
2367 if (pop_fpu_stack) __ fsubp (non_tos_index);
2368 else if (dest_is_tos) __ fsubr (non_tos_index);
2369 else __ fsuba (non_tos_index);
2370 }
2371 break;
2372
2373 case lir_mul_strictfp: // fall through
2374 case lir_mul:
2375 if (pop_fpu_stack) __ fmulp(non_tos_index);
2376 else if (dest_is_tos) __ fmul (non_tos_index);
2377 else __ fmula(non_tos_index);
2378 break;
2379
2380 case lir_div_strictfp: // fall through
2381 case lir_div:
2382 if (left_is_tos) {
2383 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2384 else if (dest_is_tos) __ fdiv (non_tos_index);
2385 else __ fdivra(non_tos_index);
2386 } else {
2387 if (pop_fpu_stack) __ fdivp (non_tos_index);
2388 else if (dest_is_tos) __ fdivr (non_tos_index);
2389 else __ fdiva (non_tos_index);
2390 }
2391 break;
2392
2393 case lir_rem:
2394 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2395 __ fremr(noreg);
2396 break;
2397
2398 default:
2399 ShouldNotReachHere();
2400 }
2401 }
2402
2403
2404 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2405 if (value->is_double_xmm()) {
2406 switch(code) {
2407 case lir_abs :
2408 {
2409 #ifdef _LP64
2410 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2411 assert(tmp->is_valid(), "need temporary");
2412 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2413 } else
2414 #endif
2415 {
2416 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2417 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2418 }
2419 assert(!tmp->is_valid(), "do not need temporary");
2420 __ andpd(dest->as_xmm_double_reg(),
2421 ExternalAddress((address)double_signmask_pool));
2422 }
2423 }
2424 break;
2425
2426 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2427 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2428 default : ShouldNotReachHere();
2429 }
2430
2431 } else if (value->is_double_fpu()) {
2432 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2433 switch(code) {
2434 case lir_abs : __ fabs() ; break;
2435 case lir_sqrt : __ fsqrt(); break;
2436 default : ShouldNotReachHere();
2437 }
2438 } else {
2439 Unimplemented();
2440 }
2441 }
2442
2443 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2444 // assert(left->destroys_register(), "check");
2445 if (left->is_single_cpu()) {
2446 Register reg = left->as_register();
2447 if (right->is_constant()) {
2448 int val = right->as_constant_ptr()->as_jint();
2449 switch (code) {
2450 case lir_logic_and: __ andl (reg, val); break;
2451 case lir_logic_or: __ orl (reg, val); break;
2452 case lir_logic_xor: __ xorl (reg, val); break;
2453 default: ShouldNotReachHere();
2454 }
2455 } else if (right->is_stack()) {
2456 // added support for stack operands
2457 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2458 switch (code) {
2459 case lir_logic_and: __ andl (reg, raddr); break;
2460 case lir_logic_or: __ orl (reg, raddr); break;
2461 case lir_logic_xor: __ xorl (reg, raddr); break;
2462 default: ShouldNotReachHere();
2463 }
2464 } else {
2465 Register rright = right->as_register();
2466 switch (code) {
2467 case lir_logic_and: __ andptr (reg, rright); break;
2468 case lir_logic_or : __ orptr (reg, rright); break;
2469 case lir_logic_xor: __ xorptr (reg, rright); break;
2470 default: ShouldNotReachHere();
2471 }
2472 }
2473 move_regs(reg, dst->as_register());
2474 } else {
2475 Register l_lo = left->as_register_lo();
2476 Register l_hi = left->as_register_hi();
2477 if (right->is_constant()) {
2478 #ifdef _LP64
2479 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2480 switch (code) {
2481 case lir_logic_and:
2482 __ andq(l_lo, rscratch1);
2483 break;
2484 case lir_logic_or:
2485 __ orq(l_lo, rscratch1);
2486 break;
2487 case lir_logic_xor:
2488 __ xorq(l_lo, rscratch1);
2489 break;
2490 default: ShouldNotReachHere();
2491 }
2492 #else
2493 int r_lo = right->as_constant_ptr()->as_jint_lo();
2494 int r_hi = right->as_constant_ptr()->as_jint_hi();
2495 switch (code) {
2496 case lir_logic_and:
2497 __ andl(l_lo, r_lo);
2498 __ andl(l_hi, r_hi);
2499 break;
2500 case lir_logic_or:
2501 __ orl(l_lo, r_lo);
2502 __ orl(l_hi, r_hi);
2503 break;
2504 case lir_logic_xor:
2505 __ xorl(l_lo, r_lo);
2506 __ xorl(l_hi, r_hi);
2507 break;
2508 default: ShouldNotReachHere();
2509 }
2510 #endif // _LP64
2511 } else {
2512 #ifdef _LP64
2513 Register r_lo;
2514 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2515 r_lo = right->as_register();
2516 } else {
2517 r_lo = right->as_register_lo();
2518 }
2519 #else
2520 Register r_lo = right->as_register_lo();
2521 Register r_hi = right->as_register_hi();
2522 assert(l_lo != r_hi, "overwriting registers");
2523 #endif
2524 switch (code) {
2525 case lir_logic_and:
2526 __ andptr(l_lo, r_lo);
2527 NOT_LP64(__ andptr(l_hi, r_hi);)
2528 break;
2529 case lir_logic_or:
2530 __ orptr(l_lo, r_lo);
2531 NOT_LP64(__ orptr(l_hi, r_hi);)
2532 break;
2533 case lir_logic_xor:
2534 __ xorptr(l_lo, r_lo);
2535 NOT_LP64(__ xorptr(l_hi, r_hi);)
2536 break;
2537 default: ShouldNotReachHere();
2538 }
2539 }
2540
2541 Register dst_lo = dst->as_register_lo();
2542 Register dst_hi = dst->as_register_hi();
2543
2544 #ifdef _LP64
2545 move_regs(l_lo, dst_lo);
2546 #else
2547 if (dst_lo == l_hi) {
2548 assert(dst_hi != l_lo, "overwriting registers");
2549 move_regs(l_hi, dst_hi);
2550 move_regs(l_lo, dst_lo);
2551 } else {
2552 assert(dst_lo != l_hi, "overwriting registers");
2553 move_regs(l_lo, dst_lo);
2554 move_regs(l_hi, dst_hi);
2555 }
2556 #endif // _LP64
2557 }
2558 }
2559
2560
2561 // we assume that rax, and rdx can be overwritten
2562 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2563
2564 assert(left->is_single_cpu(), "left must be register");
2565 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2566 assert(result->is_single_cpu(), "result must be register");
2567
2568 // assert(left->destroys_register(), "check");
2569 // assert(right->destroys_register(), "check");
2570
2571 Register lreg = left->as_register();
2572 Register dreg = result->as_register();
2573
2574 if (right->is_constant()) {
2575 jint divisor = right->as_constant_ptr()->as_jint();
2576 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2577 if (code == lir_idiv) {
2578 assert(lreg == rax, "must be rax,");
2579 assert(temp->as_register() == rdx, "tmp register must be rdx");
2580 __ cdql(); // sign extend into rdx:rax
2581 if (divisor == 2) {
2582 __ subl(lreg, rdx);
2583 } else {
2584 __ andl(rdx, divisor - 1);
2585 __ addl(lreg, rdx);
2586 }
2587 __ sarl(lreg, log2_jint(divisor));
2588 move_regs(lreg, dreg);
2589 } else if (code == lir_irem) {
2590 Label done;
2591 __ mov(dreg, lreg);
2592 __ andl(dreg, 0x80000000 | (divisor - 1));
2593 __ jcc(Assembler::positive, done);
2594 __ decrement(dreg);
2595 __ orl(dreg, ~(divisor - 1));
2596 __ increment(dreg);
2597 __ bind(done);
2598 } else {
2599 ShouldNotReachHere();
2600 }
2601 } else {
2602 Register rreg = right->as_register();
2603 assert(lreg == rax, "left register must be rax,");
2604 assert(rreg != rdx, "right register must not be rdx");
2605 assert(temp->as_register() == rdx, "tmp register must be rdx");
2606
2607 move_regs(lreg, rax);
2608
2609 int idivl_offset = __ corrected_idivl(rreg);
2610 if (ImplicitDiv0Checks) {
2611 add_debug_info_for_div0(idivl_offset, info);
2612 }
2613 if (code == lir_irem) {
2614 move_regs(rdx, dreg); // result is in rdx
2615 } else {
2616 move_regs(rax, dreg);
2617 }
2618 }
2619 }
2620
2621
2622 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2623 if (opr1->is_single_cpu()) {
2624 Register reg1 = opr1->as_register();
2625 if (opr2->is_single_cpu()) {
2626 // cpu register - cpu register
2627 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2628 __ cmpoop(reg1, opr2->as_register());
2629 } else {
2630 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2631 __ cmpl(reg1, opr2->as_register());
2632 }
2633 } else if (opr2->is_stack()) {
2634 // cpu register - stack
2635 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2636 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2637 } else {
2638 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2639 }
2640 } else if (opr2->is_constant()) {
2641 // cpu register - constant
2642 LIR_Const* c = opr2->as_constant_ptr();
2643 if (c->type() == T_INT) {
2644 __ cmpl(reg1, c->as_jint());
2645 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2646 // In 64bit oops are single register
2647 jobject o = c->as_jobject();
2648 if (o == NULL) {
2649 __ cmpptr(reg1, (int32_t)NULL_WORD);
2650 } else {
2651 __ cmpoop(reg1, o);
2652 }
2653 } else {
2654 fatal("unexpected type: %s", basictype_to_str(c->type()));
2655 }
2656 // cpu register - address
2657 } else if (opr2->is_address()) {
2658 if (op->info() != NULL) {
2659 add_debug_info_for_null_check_here(op->info());
2660 }
2661 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2662 } else {
2663 ShouldNotReachHere();
2664 }
2665
2666 } else if(opr1->is_double_cpu()) {
2667 Register xlo = opr1->as_register_lo();
2668 Register xhi = opr1->as_register_hi();
2669 if (opr2->is_double_cpu()) {
2670 #ifdef _LP64
2671 __ cmpptr(xlo, opr2->as_register_lo());
2672 #else
2673 // cpu register - cpu register
2674 Register ylo = opr2->as_register_lo();
2675 Register yhi = opr2->as_register_hi();
2676 __ subl(xlo, ylo);
2677 __ sbbl(xhi, yhi);
2678 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2679 __ orl(xhi, xlo);
2680 }
2681 #endif // _LP64
2682 } else if (opr2->is_constant()) {
2683 // cpu register - constant 0
2684 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2685 #ifdef _LP64
2686 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2687 #else
2688 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2689 __ orl(xhi, xlo);
2690 #endif // _LP64
2691 } else {
2692 ShouldNotReachHere();
2693 }
2694
2695 } else if (opr1->is_single_xmm()) {
2696 XMMRegister reg1 = opr1->as_xmm_float_reg();
2697 if (opr2->is_single_xmm()) {
2698 // xmm register - xmm register
2699 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2700 } else if (opr2->is_stack()) {
2701 // xmm register - stack
2702 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2703 } else if (opr2->is_constant()) {
2704 // xmm register - constant
2705 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2706 } else if (opr2->is_address()) {
2707 // xmm register - address
2708 if (op->info() != NULL) {
2709 add_debug_info_for_null_check_here(op->info());
2710 }
2711 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2712 } else {
2713 ShouldNotReachHere();
2714 }
2715
2716 } else if (opr1->is_double_xmm()) {
2717 XMMRegister reg1 = opr1->as_xmm_double_reg();
2718 if (opr2->is_double_xmm()) {
2719 // xmm register - xmm register
2720 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2721 } else if (opr2->is_stack()) {
2722 // xmm register - stack
2723 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2724 } else if (opr2->is_constant()) {
2725 // xmm register - constant
2726 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2727 } else if (opr2->is_address()) {
2728 // xmm register - address
2729 if (op->info() != NULL) {
2730 add_debug_info_for_null_check_here(op->info());
2731 }
2732 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2733 } else {
2734 ShouldNotReachHere();
2735 }
2736
2737 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2738 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2739 assert(opr2->is_fpu_register(), "both must be registers");
2740 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2741
2742 } else if (opr1->is_address() && opr2->is_constant()) {
2743 LIR_Const* c = opr2->as_constant_ptr();
2744 #ifdef _LP64
2745 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2746 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2747 __ movoop(rscratch1, c->as_jobject());
2748 }
2749 #endif // LP64
2750 if (op->info() != NULL) {
2751 add_debug_info_for_null_check_here(op->info());
2752 }
2753 // special case: address - constant
2754 LIR_Address* addr = opr1->as_address_ptr();
2755 if (c->type() == T_INT) {
2756 __ cmpl(as_Address(addr), c->as_jint());
2757 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2758 #ifdef _LP64
2759 // %%% Make this explode if addr isn't reachable until we figure out a
2760 // better strategy by giving noreg as the temp for as_Address
2761 __ cmpoop(rscratch1, as_Address(addr, noreg));
2762 #else
2763 __ cmpoop(as_Address(addr), c->as_jobject());
2764 #endif // _LP64
2765 } else {
2766 ShouldNotReachHere();
2767 }
2768
2769 } else {
2770 ShouldNotReachHere();
2771 }
2772 }
2773
2774 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2775 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2776 if (left->is_single_xmm()) {
2777 assert(right->is_single_xmm(), "must match");
2778 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2779 } else if (left->is_double_xmm()) {
2780 assert(right->is_double_xmm(), "must match");
2781 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2782
2783 } else {
2784 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2785 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2786
2787 assert(left->fpu() == 0, "left must be on TOS");
2788 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2789 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2790 }
2791 } else {
2792 assert(code == lir_cmp_l2i, "check");
2793 #ifdef _LP64
2794 Label done;
2795 Register dest = dst->as_register();
2796 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2797 __ movl(dest, -1);
2798 __ jccb(Assembler::less, done);
2799 __ set_byte_if_not_zero(dest);
2800 __ movzbl(dest, dest);
2801 __ bind(done);
2802 #else
2803 __ lcmp2int(left->as_register_hi(),
2804 left->as_register_lo(),
2805 right->as_register_hi(),
2806 right->as_register_lo());
2807 move_regs(left->as_register_hi(), dst->as_register());
2808 #endif // _LP64
2809 }
2810 }
2811
2812
2813 void LIR_Assembler::align_call(LIR_Code code) {
2814 // make sure that the displacement word of the call ends up word aligned
2815 int offset = __ offset();
2816 switch (code) {
2817 case lir_static_call:
2818 case lir_optvirtual_call:
2819 case lir_dynamic_call:
2820 offset += NativeCall::displacement_offset;
2821 break;
2822 case lir_icvirtual_call:
2823 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2824 break;
2825 case lir_virtual_call: // currently, sparc-specific for niagara
2826 default: ShouldNotReachHere();
2827 }
2828 __ align(BytesPerWord, offset);
2829 }
2830
2831
2832 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2833 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2834 "must be aligned");
2835 __ call(AddressLiteral(op->addr(), rtype));
2836 add_call_info(code_offset(), op->info());
2837 }
2838
2839
2840 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2841 __ ic_call(op->addr());
2842 add_call_info(code_offset(), op->info());
2843 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2844 "must be aligned");
2845 }
2846
2847
2848 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2849 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2850 ShouldNotReachHere();
2851 }
2852
2853
2854 void LIR_Assembler::emit_static_call_stub() {
2855 address call_pc = __ pc();
2856 address stub = __ start_a_stub(call_stub_size());
2857 if (stub == NULL) {
2858 bailout("static call stub overflow");
2859 return;
2860 }
2861
2862 int start = __ offset();
2863
2864 // make sure that the displacement word of the call ends up word aligned
2865 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2866 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2867 __ mov_metadata(rbx, (Metadata*)NULL);
2868 // must be set to -1 at code generation time
2869 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2870 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2871 __ jump(RuntimeAddress(__ pc()));
2872
2873 if (UseAOT) {
2874 // Trampoline to aot code
2875 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2876 #ifdef _LP64
2877 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2878 #else
2879 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2880 #endif
2881 __ jmp(rax);
2882 }
2883 assert(__ offset() - start <= call_stub_size(), "stub too big");
2884 __ end_a_stub();
2885 }
2886
2887
2888 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2889 assert(exceptionOop->as_register() == rax, "must match");
2890 assert(exceptionPC->as_register() == rdx, "must match");
2891
2892 // exception object is not added to oop map by LinearScan
2893 // (LinearScan assumes that no oops are in fixed registers)
2894 info->add_register_oop(exceptionOop);
2895 Runtime1::StubID unwind_id;
2896
2897 // get current pc information
2898 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2899 int pc_for_athrow_offset = __ offset();
2900 InternalAddress pc_for_athrow(__ pc());
2901 __ lea(exceptionPC->as_register(), pc_for_athrow);
2902 add_call_info(pc_for_athrow_offset, info); // for exception handler
2903
2904 __ verify_not_null_oop(rax);
2905 // search an exception handler (rax: exception oop, rdx: throwing pc)
2906 if (compilation()->has_fpu_code()) {
2907 unwind_id = Runtime1::handle_exception_id;
2908 } else {
2909 unwind_id = Runtime1::handle_exception_nofpu_id;
2910 }
2911 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2912
2913 // enough room for two byte trap
2914 __ nop();
2915 }
2916
2917
2918 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2919 assert(exceptionOop->as_register() == rax, "must match");
2920
2921 __ jmp(_unwind_handler_entry);
2922 }
2923
2924
2925 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2926
2927 // optimized version for linear scan:
2928 // * count must be already in ECX (guaranteed by LinearScan)
2929 // * left and dest must be equal
2930 // * tmp must be unused
2931 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2932 assert(left == dest, "left and dest must be equal");
2933 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2934
2935 if (left->is_single_cpu()) {
2936 Register value = left->as_register();
2937 assert(value != SHIFT_count, "left cannot be ECX");
2938
2939 switch (code) {
2940 case lir_shl: __ shll(value); break;
2941 case lir_shr: __ sarl(value); break;
2942 case lir_ushr: __ shrl(value); break;
2943 default: ShouldNotReachHere();
2944 }
2945 } else if (left->is_double_cpu()) {
2946 Register lo = left->as_register_lo();
2947 Register hi = left->as_register_hi();
2948 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2949 #ifdef _LP64
2950 switch (code) {
2951 case lir_shl: __ shlptr(lo); break;
2952 case lir_shr: __ sarptr(lo); break;
2953 case lir_ushr: __ shrptr(lo); break;
2954 default: ShouldNotReachHere();
2955 }
2956 #else
2957
2958 switch (code) {
2959 case lir_shl: __ lshl(hi, lo); break;
2960 case lir_shr: __ lshr(hi, lo, true); break;
2961 case lir_ushr: __ lshr(hi, lo, false); break;
2962 default: ShouldNotReachHere();
2963 }
2964 #endif // LP64
2965 } else {
2966 ShouldNotReachHere();
2967 }
2968 }
2969
2970
2971 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2972 if (dest->is_single_cpu()) {
2973 // first move left into dest so that left is not destroyed by the shift
2974 Register value = dest->as_register();
2975 count = count & 0x1F; // Java spec
2976
2977 move_regs(left->as_register(), value);
2978 switch (code) {
2979 case lir_shl: __ shll(value, count); break;
2980 case lir_shr: __ sarl(value, count); break;
2981 case lir_ushr: __ shrl(value, count); break;
2982 default: ShouldNotReachHere();
2983 }
2984 } else if (dest->is_double_cpu()) {
2985 #ifndef _LP64
2986 Unimplemented();
2987 #else
2988 // first move left into dest so that left is not destroyed by the shift
2989 Register value = dest->as_register_lo();
2990 count = count & 0x1F; // Java spec
2991
2992 move_regs(left->as_register_lo(), value);
2993 switch (code) {
2994 case lir_shl: __ shlptr(value, count); break;
2995 case lir_shr: __ sarptr(value, count); break;
2996 case lir_ushr: __ shrptr(value, count); break;
2997 default: ShouldNotReachHere();
2998 }
2999 #endif // _LP64
3000 } else {
3001 ShouldNotReachHere();
3002 }
3003 }
3004
3005
3006 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3007 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3008 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3009 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3010 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3011 }
3012
3013
3014 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3015 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3016 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3017 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3018 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3019 }
3020
3021
3022 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3023 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3024 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3025 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3026 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3027 }
3028
3029
3030 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3031 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3032 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3033 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3034 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3035 }
3036
3037
3038 // This code replaces a call to arraycopy; no exception may
3039 // be thrown in this code, they must be thrown in the System.arraycopy
3040 // activation frame; we could save some checks if this would not be the case
3041 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3042 ciArrayKlass* default_type = op->expected_type();
3043 Register src = op->src()->as_register();
3044 Register dst = op->dst()->as_register();
3045 Register src_pos = op->src_pos()->as_register();
3046 Register dst_pos = op->dst_pos()->as_register();
3047 Register length = op->length()->as_register();
3048 Register tmp = op->tmp()->as_register();
3049
3050 __ resolve(ACCESS_READ, src);
3051 __ resolve(ACCESS_WRITE, dst);
3052
3053 CodeStub* stub = op->stub();
3054 int flags = op->flags();
3055 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3056 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3057
3058 // if we don't know anything, just go through the generic arraycopy
3059 if (default_type == NULL) {
3060 // save outgoing arguments on stack in case call to System.arraycopy is needed
3061 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3062 // for interpreter calling conventions. Now we have to do it in new style conventions.
3063 // For the moment until C1 gets the new register allocator I just force all the
3064 // args to the right place (except the register args) and then on the back side
3065 // reload the register args properly if we go slow path. Yuck
3066
3067 // These are proper for the calling convention
3068 store_parameter(length, 2);
3069 store_parameter(dst_pos, 1);
3070 store_parameter(dst, 0);
3071
3072 // these are just temporary placements until we need to reload
3073 store_parameter(src_pos, 3);
3074 store_parameter(src, 4);
3075 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3076
3077 address copyfunc_addr = StubRoutines::generic_arraycopy();
3078 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3079
3080 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3081 #ifdef _LP64
3082 // The arguments are in java calling convention so we can trivially shift them to C
3083 // convention
3084 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3085 __ mov(c_rarg0, j_rarg0);
3086 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3087 __ mov(c_rarg1, j_rarg1);
3088 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3089 __ mov(c_rarg2, j_rarg2);
3090 assert_different_registers(c_rarg3, j_rarg4);
3091 __ mov(c_rarg3, j_rarg3);
3092 #ifdef _WIN64
3093 // Allocate abi space for args but be sure to keep stack aligned
3094 __ subptr(rsp, 6*wordSize);
3095 store_parameter(j_rarg4, 4);
3096 #ifndef PRODUCT
3097 if (PrintC1Statistics) {
3098 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3099 }
3100 #endif
3101 __ call(RuntimeAddress(copyfunc_addr));
3102 __ addptr(rsp, 6*wordSize);
3103 #else
3104 __ mov(c_rarg4, j_rarg4);
3105 #ifndef PRODUCT
3106 if (PrintC1Statistics) {
3107 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3108 }
3109 #endif
3110 __ call(RuntimeAddress(copyfunc_addr));
3111 #endif // _WIN64
3112 #else
3113 __ push(length);
3114 __ push(dst_pos);
3115 __ push(dst);
3116 __ push(src_pos);
3117 __ push(src);
3118
3119 #ifndef PRODUCT
3120 if (PrintC1Statistics) {
3121 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3122 }
3123 #endif
3124 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3125
3126 #endif // _LP64
3127
3128 __ cmpl(rax, 0);
3129 __ jcc(Assembler::equal, *stub->continuation());
3130
3131 __ mov(tmp, rax);
3132 __ xorl(tmp, -1);
3133
3134 // Reload values from the stack so they are where the stub
3135 // expects them.
3136 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3137 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3138 __ movptr (length, Address(rsp, 2*BytesPerWord));
3139 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3140 __ movptr (src, Address(rsp, 4*BytesPerWord));
3141
3142 __ subl(length, tmp);
3143 __ addl(src_pos, tmp);
3144 __ addl(dst_pos, tmp);
3145 __ jmp(*stub->entry());
3146
3147 __ bind(*stub->continuation());
3148 return;
3149 }
3150
3151 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3152
3153 int elem_size = type2aelembytes(basic_type);
3154 Address::ScaleFactor scale;
3155
3156 switch (elem_size) {
3157 case 1 :
3158 scale = Address::times_1;
3159 break;
3160 case 2 :
3161 scale = Address::times_2;
3162 break;
3163 case 4 :
3164 scale = Address::times_4;
3165 break;
3166 case 8 :
3167 scale = Address::times_8;
3168 break;
3169 default:
3170 scale = Address::no_scale;
3171 ShouldNotReachHere();
3172 }
3173
3174 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3175 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3176 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3177 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3178
3179 // length and pos's are all sign extended at this point on 64bit
3180
3181 // test for NULL
3182 if (flags & LIR_OpArrayCopy::src_null_check) {
3183 __ testptr(src, src);
3184 __ jcc(Assembler::zero, *stub->entry());
3185 }
3186 if (flags & LIR_OpArrayCopy::dst_null_check) {
3187 __ testptr(dst, dst);
3188 __ jcc(Assembler::zero, *stub->entry());
3189 }
3190
3191 // If the compiler was not able to prove that exact type of the source or the destination
3192 // of the arraycopy is an array type, check at runtime if the source or the destination is
3193 // an instance type.
3194 if (flags & LIR_OpArrayCopy::type_check) {
3195 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3196 __ load_klass(tmp, dst);
3197 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3198 __ jcc(Assembler::greaterEqual, *stub->entry());
3199 }
3200
3201 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3202 __ load_klass(tmp, src);
3203 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3204 __ jcc(Assembler::greaterEqual, *stub->entry());
3205 }
3206 }
3207
3208 // check if negative
3209 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3210 __ testl(src_pos, src_pos);
3211 __ jcc(Assembler::less, *stub->entry());
3212 }
3213 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3214 __ testl(dst_pos, dst_pos);
3215 __ jcc(Assembler::less, *stub->entry());
3216 }
3217
3218 if (flags & LIR_OpArrayCopy::src_range_check) {
3219 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3220 __ cmpl(tmp, src_length_addr);
3221 __ jcc(Assembler::above, *stub->entry());
3222 }
3223 if (flags & LIR_OpArrayCopy::dst_range_check) {
3224 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3225 __ cmpl(tmp, dst_length_addr);
3226 __ jcc(Assembler::above, *stub->entry());
3227 }
3228
3229 if (flags & LIR_OpArrayCopy::length_positive_check) {
3230 __ testl(length, length);
3231 __ jcc(Assembler::less, *stub->entry());
3232 }
3233
3234 #ifdef _LP64
3235 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3236 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3237 #endif
3238
3239 if (flags & LIR_OpArrayCopy::type_check) {
3240 // We don't know the array types are compatible
3241 if (basic_type != T_OBJECT) {
3242 // Simple test for basic type arrays
3243 if (UseCompressedClassPointers) {
3244 __ movl(tmp, src_klass_addr);
3245 __ cmpl(tmp, dst_klass_addr);
3246 } else {
3247 __ movptr(tmp, src_klass_addr);
3248 __ cmpptr(tmp, dst_klass_addr);
3249 }
3250 __ jcc(Assembler::notEqual, *stub->entry());
3251 } else {
3252 // For object arrays, if src is a sub class of dst then we can
3253 // safely do the copy.
3254 Label cont, slow;
3255
3256 __ push(src);
3257 __ push(dst);
3258
3259 __ load_klass(src, src);
3260 __ load_klass(dst, dst);
3261
3262 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3263
3264 __ push(src);
3265 __ push(dst);
3266 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3267 __ pop(dst);
3268 __ pop(src);
3269
3270 __ cmpl(src, 0);
3271 __ jcc(Assembler::notEqual, cont);
3272
3273 __ bind(slow);
3274 __ pop(dst);
3275 __ pop(src);
3276
3277 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3278 if (copyfunc_addr != NULL) { // use stub if available
3279 // src is not a sub class of dst so we have to do a
3280 // per-element check.
3281
3282 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3283 if ((flags & mask) != mask) {
3284 // Check that at least both of them object arrays.
3285 assert(flags & mask, "one of the two should be known to be an object array");
3286
3287 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3288 __ load_klass(tmp, src);
3289 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3290 __ load_klass(tmp, dst);
3291 }
3292 int lh_offset = in_bytes(Klass::layout_helper_offset());
3293 Address klass_lh_addr(tmp, lh_offset);
3294 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3295 __ cmpl(klass_lh_addr, objArray_lh);
3296 __ jcc(Assembler::notEqual, *stub->entry());
3297 }
3298
3299 // Spill because stubs can use any register they like and it's
3300 // easier to restore just those that we care about.
3301 store_parameter(dst, 0);
3302 store_parameter(dst_pos, 1);
3303 store_parameter(length, 2);
3304 store_parameter(src_pos, 3);
3305 store_parameter(src, 4);
3306
3307 #ifndef _LP64
3308 __ movptr(tmp, dst_klass_addr);
3309 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3310 __ push(tmp);
3311 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3312 __ push(tmp);
3313 __ push(length);
3314 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3315 __ push(tmp);
3316 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3317 __ push(tmp);
3318
3319 __ call_VM_leaf(copyfunc_addr, 5);
3320 #else
3321 __ movl2ptr(length, length); //higher 32bits must be null
3322
3323 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3324 assert_different_registers(c_rarg0, dst, dst_pos, length);
3325 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3326 assert_different_registers(c_rarg1, dst, length);
3327
3328 __ mov(c_rarg2, length);
3329 assert_different_registers(c_rarg2, dst);
3330
3331 #ifdef _WIN64
3332 // Allocate abi space for args but be sure to keep stack aligned
3333 __ subptr(rsp, 6*wordSize);
3334 __ load_klass(c_rarg3, dst);
3335 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3336 store_parameter(c_rarg3, 4);
3337 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3338 __ call(RuntimeAddress(copyfunc_addr));
3339 __ addptr(rsp, 6*wordSize);
3340 #else
3341 __ load_klass(c_rarg4, dst);
3342 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3343 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3344 __ call(RuntimeAddress(copyfunc_addr));
3345 #endif
3346
3347 #endif
3348
3349 #ifndef PRODUCT
3350 if (PrintC1Statistics) {
3351 Label failed;
3352 __ testl(rax, rax);
3353 __ jcc(Assembler::notZero, failed);
3354 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3355 __ bind(failed);
3356 }
3357 #endif
3358
3359 __ testl(rax, rax);
3360 __ jcc(Assembler::zero, *stub->continuation());
3361
3362 #ifndef PRODUCT
3363 if (PrintC1Statistics) {
3364 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3365 }
3366 #endif
3367
3368 __ mov(tmp, rax);
3369
3370 __ xorl(tmp, -1);
3371
3372 // Restore previously spilled arguments
3373 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3374 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3375 __ movptr (length, Address(rsp, 2*BytesPerWord));
3376 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3377 __ movptr (src, Address(rsp, 4*BytesPerWord));
3378
3379
3380 __ subl(length, tmp);
3381 __ addl(src_pos, tmp);
3382 __ addl(dst_pos, tmp);
3383 }
3384
3385 __ jmp(*stub->entry());
3386
3387 __ bind(cont);
3388 __ pop(dst);
3389 __ pop(src);
3390 }
3391 }
3392
3393 #ifdef ASSERT
3394 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3395 // Sanity check the known type with the incoming class. For the
3396 // primitive case the types must match exactly with src.klass and
3397 // dst.klass each exactly matching the default type. For the
3398 // object array case, if no type check is needed then either the
3399 // dst type is exactly the expected type and the src type is a
3400 // subtype which we can't check or src is the same array as dst
3401 // but not necessarily exactly of type default_type.
3402 Label known_ok, halt;
3403 __ mov_metadata(tmp, default_type->constant_encoding());
3404 #ifdef _LP64
3405 if (UseCompressedClassPointers) {
3406 __ encode_klass_not_null(tmp);
3407 }
3408 #endif
3409
3410 if (basic_type != T_OBJECT) {
3411
3412 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3413 else __ cmpptr(tmp, dst_klass_addr);
3414 __ jcc(Assembler::notEqual, halt);
3415 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3416 else __ cmpptr(tmp, src_klass_addr);
3417 __ jcc(Assembler::equal, known_ok);
3418 } else {
3419 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3420 else __ cmpptr(tmp, dst_klass_addr);
3421 __ jcc(Assembler::equal, known_ok);
3422 __ cmpptr(src, dst);
3423 __ jcc(Assembler::equal, known_ok);
3424 }
3425 __ bind(halt);
3426 __ stop("incorrect type information in arraycopy");
3427 __ bind(known_ok);
3428 }
3429 #endif
3430
3431 #ifndef PRODUCT
3432 if (PrintC1Statistics) {
3433 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3434 }
3435 #endif
3436
3437 #ifdef _LP64
3438 assert_different_registers(c_rarg0, dst, dst_pos, length);
3439 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3440 assert_different_registers(c_rarg1, length);
3441 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3442 __ mov(c_rarg2, length);
3443
3444 #else
3445 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3446 store_parameter(tmp, 0);
3447 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3448 store_parameter(tmp, 1);
3449 store_parameter(length, 2);
3450 #endif // _LP64
3451
3452 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3453 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3454 const char *name;
3455 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3456 __ call_VM_leaf(entry, 0);
3457
3458 __ bind(*stub->continuation());
3459 }
3460
3461 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3462 assert(op->crc()->is_single_cpu(), "crc must be register");
3463 assert(op->val()->is_single_cpu(), "byte value must be register");
3464 assert(op->result_opr()->is_single_cpu(), "result must be register");
3465 Register crc = op->crc()->as_register();
3466 Register val = op->val()->as_register();
3467 Register res = op->result_opr()->as_register();
3468
3469 assert_different_registers(val, crc, res);
3470
3471 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3472 __ notl(crc); // ~crc
3473 __ update_byte_crc32(crc, val, res);
3474 __ notl(crc); // ~crc
3475 __ mov(res, crc);
3476 }
3477
3478 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3479 Register obj = op->obj_opr()->as_register(); // may not be an oop
3480 Register hdr = op->hdr_opr()->as_register();
3481 Register lock = op->lock_opr()->as_register();
3482 if (!UseFastLocking) {
3483 __ jmp(*op->stub()->entry());
3484 } else if (op->code() == lir_lock) {
3485 Register scratch = noreg;
3486 if (UseBiasedLocking) {
3487 scratch = op->scratch_opr()->as_register();
3488 }
3489 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3490 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3491 // add debug info for NullPointerException only if one is possible
3492 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3493 if (op->info() != NULL) {
3494 add_debug_info_for_null_check(null_check_offset, op->info());
3495 }
3496 // done
3497 } else if (op->code() == lir_unlock) {
3498 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3499 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3500 } else {
3501 Unimplemented();
3502 }
3503 __ bind(*op->stub()->continuation());
3504 }
3505
3506
3507 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3508 ciMethod* method = op->profiled_method();
3509 int bci = op->profiled_bci();
3510 ciMethod* callee = op->profiled_callee();
3511
3512 // Update counter for all call types
3513 ciMethodData* md = method->method_data_or_null();
3514 assert(md != NULL, "Sanity");
3515 ciProfileData* data = md->bci_to_data(bci);
3516 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3517 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3518 Register mdo = op->mdo()->as_register();
3519 __ mov_metadata(mdo, md->constant_encoding());
3520 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3521 // Perform additional virtual call profiling for invokevirtual and
3522 // invokeinterface bytecodes
3523 if (op->should_profile_receiver_type()) {
3524 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3525 Register recv = op->recv()->as_register();
3526 assert_different_registers(mdo, recv);
3527 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3528 ciKlass* known_klass = op->known_holder();
3529 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3530 // We know the type that will be seen at this call site; we can
3531 // statically update the MethodData* rather than needing to do
3532 // dynamic tests on the receiver type
3533
3534 // NOTE: we should probably put a lock around this search to
3535 // avoid collisions by concurrent compilations
3536 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3537 uint i;
3538 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3539 ciKlass* receiver = vc_data->receiver(i);
3540 if (known_klass->equals(receiver)) {
3541 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3542 __ addptr(data_addr, DataLayout::counter_increment);
3543 return;
3544 }
3545 }
3546
3547 // Receiver type not found in profile data; select an empty slot
3548
3549 // Note that this is less efficient than it should be because it
3550 // always does a write to the receiver part of the
3551 // VirtualCallData rather than just the first time
3552 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3553 ciKlass* receiver = vc_data->receiver(i);
3554 if (receiver == NULL) {
3555 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3556 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3557 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3558 __ addptr(data_addr, DataLayout::counter_increment);
3559 return;
3560 }
3561 }
3562 } else {
3563 __ load_klass(recv, recv);
3564 Label update_done;
3565 type_profile_helper(mdo, md, data, recv, &update_done);
3566 // Receiver did not match any saved receiver and there is no empty row for it.
3567 // Increment total counter to indicate polymorphic case.
3568 __ addptr(counter_addr, DataLayout::counter_increment);
3569
3570 __ bind(update_done);
3571 }
3572 } else {
3573 // Static call
3574 __ addptr(counter_addr, DataLayout::counter_increment);
3575 }
3576 }
3577
3578 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3579 Register obj = op->obj()->as_register();
3580 Register tmp = op->tmp()->as_pointer_register();
3581 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3582 ciKlass* exact_klass = op->exact_klass();
3583 intptr_t current_klass = op->current_klass();
3584 bool not_null = op->not_null();
3585 bool no_conflict = op->no_conflict();
3586
3587 Label update, next, none;
3588
3589 bool do_null = !not_null;
3590 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3591 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3592
3593 assert(do_null || do_update, "why are we here?");
3594 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3595
3596 __ verify_oop(obj);
3597
3598 if (tmp != obj) {
3599 __ mov(tmp, obj);
3600 }
3601 if (do_null) {
3602 __ testptr(tmp, tmp);
3603 __ jccb(Assembler::notZero, update);
3604 if (!TypeEntries::was_null_seen(current_klass)) {
3605 __ orptr(mdo_addr, TypeEntries::null_seen);
3606 }
3607 if (do_update) {
3608 #ifndef ASSERT
3609 __ jmpb(next);
3610 }
3611 #else
3612 __ jmp(next);
3613 }
3614 } else {
3615 __ testptr(tmp, tmp);
3616 __ jcc(Assembler::notZero, update);
3617 __ stop("unexpect null obj");
3618 #endif
3619 }
3620
3621 __ bind(update);
3622
3623 if (do_update) {
3624 #ifdef ASSERT
3625 if (exact_klass != NULL) {
3626 Label ok;
3627 __ load_klass(tmp, tmp);
3628 __ push(tmp);
3629 __ mov_metadata(tmp, exact_klass->constant_encoding());
3630 __ cmpptr(tmp, Address(rsp, 0));
3631 __ jcc(Assembler::equal, ok);
3632 __ stop("exact klass and actual klass differ");
3633 __ bind(ok);
3634 __ pop(tmp);
3635 }
3636 #endif
3637 if (!no_conflict) {
3638 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3639 if (exact_klass != NULL) {
3640 __ mov_metadata(tmp, exact_klass->constant_encoding());
3641 } else {
3642 __ load_klass(tmp, tmp);
3643 }
3644
3645 __ xorptr(tmp, mdo_addr);
3646 __ testptr(tmp, TypeEntries::type_klass_mask);
3647 // klass seen before, nothing to do. The unknown bit may have been
3648 // set already but no need to check.
3649 __ jccb(Assembler::zero, next);
3650
3651 __ testptr(tmp, TypeEntries::type_unknown);
3652 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3653
3654 if (TypeEntries::is_type_none(current_klass)) {
3655 __ cmpptr(mdo_addr, 0);
3656 __ jccb(Assembler::equal, none);
3657 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3658 __ jccb(Assembler::equal, none);
3659 // There is a chance that the checks above (re-reading profiling
3660 // data from memory) fail if another thread has just set the
3661 // profiling to this obj's klass
3662 __ xorptr(tmp, mdo_addr);
3663 __ testptr(tmp, TypeEntries::type_klass_mask);
3664 __ jccb(Assembler::zero, next);
3665 }
3666 } else {
3667 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3668 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3669
3670 __ movptr(tmp, mdo_addr);
3671 __ testptr(tmp, TypeEntries::type_unknown);
3672 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3673 }
3674
3675 // different than before. Cannot keep accurate profile.
3676 __ orptr(mdo_addr, TypeEntries::type_unknown);
3677
3678 if (TypeEntries::is_type_none(current_klass)) {
3679 __ jmpb(next);
3680
3681 __ bind(none);
3682 // first time here. Set profile type.
3683 __ movptr(mdo_addr, tmp);
3684 }
3685 } else {
3686 // There's a single possible klass at this profile point
3687 assert(exact_klass != NULL, "should be");
3688 if (TypeEntries::is_type_none(current_klass)) {
3689 __ mov_metadata(tmp, exact_klass->constant_encoding());
3690 __ xorptr(tmp, mdo_addr);
3691 __ testptr(tmp, TypeEntries::type_klass_mask);
3692 #ifdef ASSERT
3693 __ jcc(Assembler::zero, next);
3694
3695 {
3696 Label ok;
3697 __ push(tmp);
3698 __ cmpptr(mdo_addr, 0);
3699 __ jcc(Assembler::equal, ok);
3700 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3701 __ jcc(Assembler::equal, ok);
3702 // may have been set by another thread
3703 __ mov_metadata(tmp, exact_klass->constant_encoding());
3704 __ xorptr(tmp, mdo_addr);
3705 __ testptr(tmp, TypeEntries::type_mask);
3706 __ jcc(Assembler::zero, ok);
3707
3708 __ stop("unexpected profiling mismatch");
3709 __ bind(ok);
3710 __ pop(tmp);
3711 }
3712 #else
3713 __ jccb(Assembler::zero, next);
3714 #endif
3715 // first time here. Set profile type.
3716 __ movptr(mdo_addr, tmp);
3717 } else {
3718 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3719 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3720
3721 __ movptr(tmp, mdo_addr);
3722 __ testptr(tmp, TypeEntries::type_unknown);
3723 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3724
3725 __ orptr(mdo_addr, TypeEntries::type_unknown);
3726 }
3727 }
3728
3729 __ bind(next);
3730 }
3731 }
3732
3733 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3734 Unimplemented();
3735 }
3736
3737
3738 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3739 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3740 }
3741
3742
3743 void LIR_Assembler::align_backward_branch_target() {
3744 __ align(BytesPerWord);
3745 }
3746
3747
3748 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3749 if (left->is_single_cpu()) {
3750 __ negl(left->as_register());
3751 move_regs(left->as_register(), dest->as_register());
3752
3753 } else if (left->is_double_cpu()) {
3754 Register lo = left->as_register_lo();
3755 #ifdef _LP64
3756 Register dst = dest->as_register_lo();
3757 __ movptr(dst, lo);
3758 __ negptr(dst);
3759 #else
3760 Register hi = left->as_register_hi();
3761 __ lneg(hi, lo);
3762 if (dest->as_register_lo() == hi) {
3763 assert(dest->as_register_hi() != lo, "destroying register");
3764 move_regs(hi, dest->as_register_hi());
3765 move_regs(lo, dest->as_register_lo());
3766 } else {
3767 move_regs(lo, dest->as_register_lo());
3768 move_regs(hi, dest->as_register_hi());
3769 }
3770 #endif // _LP64
3771
3772 } else if (dest->is_single_xmm()) {
3773 #ifdef _LP64
3774 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3775 assert(tmp->is_valid(), "need temporary");
3776 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3777 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3778 }
3779 else
3780 #endif
3781 {
3782 assert(!tmp->is_valid(), "do not need temporary");
3783 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3784 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3785 }
3786 __ xorps(dest->as_xmm_float_reg(),
3787 ExternalAddress((address)float_signflip_pool));
3788 }
3789 } else if (dest->is_double_xmm()) {
3790 #ifdef _LP64
3791 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3792 assert(tmp->is_valid(), "need temporary");
3793 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3794 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3795 }
3796 else
3797 #endif
3798 {
3799 assert(!tmp->is_valid(), "do not need temporary");
3800 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3801 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3802 }
3803 __ xorpd(dest->as_xmm_double_reg(),
3804 ExternalAddress((address)double_signflip_pool));
3805 }
3806 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3807 assert(left->fpu() == 0, "arg must be on TOS");
3808 assert(dest->fpu() == 0, "dest must be TOS");
3809 __ fchs();
3810
3811 } else {
3812 ShouldNotReachHere();
3813 }
3814 }
3815
3816
3817 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3818 assert(src->is_address(), "must be an address");
3819 assert(dest->is_register(), "must be a register");
3820
3821 PatchingStub* patch = NULL;
3822 if (patch_code != lir_patch_none) {
3823 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3824 }
3825
3826 Register reg = dest->as_pointer_register();
3827 LIR_Address* addr = src->as_address_ptr();
3828 __ lea(reg, as_Address(addr));
3829
3830 if (patch != NULL) {
3831 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3832 }
3833 }
3834
3835
3836
3837 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3838 assert(!tmp->is_valid(), "don't need temporary");
3839 __ call(RuntimeAddress(dest));
3840 if (info != NULL) {
3841 add_call_info_here(info);
3842 }
3843 }
3844
3845
3846 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3847 assert(type == T_LONG, "only for volatile long fields");
3848
3849 if (info != NULL) {
3850 add_debug_info_for_null_check_here(info);
3851 }
3852
3853 if (src->is_double_xmm()) {
3854 if (dest->is_double_cpu()) {
3855 #ifdef _LP64
3856 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3857 #else
3858 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3859 __ psrlq(src->as_xmm_double_reg(), 32);
3860 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3861 #endif // _LP64
3862 } else if (dest->is_double_stack()) {
3863 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3864 } else if (dest->is_address()) {
3865 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3866 } else {
3867 ShouldNotReachHere();
3868 }
3869
3870 } else if (dest->is_double_xmm()) {
3871 if (src->is_double_stack()) {
3872 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3873 } else if (src->is_address()) {
3874 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3875 } else {
3876 ShouldNotReachHere();
3877 }
3878
3879 } else if (src->is_double_fpu()) {
3880 assert(src->fpu_regnrLo() == 0, "must be TOS");
3881 if (dest->is_double_stack()) {
3882 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3883 } else if (dest->is_address()) {
3884 __ fistp_d(as_Address(dest->as_address_ptr()));
3885 } else {
3886 ShouldNotReachHere();
3887 }
3888
3889 } else if (dest->is_double_fpu()) {
3890 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3891 if (src->is_double_stack()) {
3892 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3893 } else if (src->is_address()) {
3894 __ fild_d(as_Address(src->as_address_ptr()));
3895 } else {
3896 ShouldNotReachHere();
3897 }
3898 } else {
3899 ShouldNotReachHere();
3900 }
3901 }
3902
3903 #ifdef ASSERT
3904 // emit run-time assertion
3905 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3906 assert(op->code() == lir_assert, "must be");
3907
3908 if (op->in_opr1()->is_valid()) {
3909 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3910 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3911 } else {
3912 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3913 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3914 }
3915
3916 Label ok;
3917 if (op->condition() != lir_cond_always) {
3918 Assembler::Condition acond = Assembler::zero;
3919 switch (op->condition()) {
3920 case lir_cond_equal: acond = Assembler::equal; break;
3921 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3922 case lir_cond_less: acond = Assembler::less; break;
3923 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3924 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3925 case lir_cond_greater: acond = Assembler::greater; break;
3926 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3927 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3928 default: ShouldNotReachHere();
3929 }
3930 __ jcc(acond, ok);
3931 }
3932 if (op->halt()) {
3933 const char* str = __ code_string(op->msg());
3934 __ stop(str);
3935 } else {
3936 breakpoint();
3937 }
3938 __ bind(ok);
3939 }
3940 #endif
3941
3942 void LIR_Assembler::membar() {
3943 // QQQ sparc TSO uses this,
3944 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3945 }
3946
3947 void LIR_Assembler::membar_acquire() {
3948 // No x86 machines currently require load fences
3949 }
3950
3951 void LIR_Assembler::membar_release() {
3952 // No x86 machines currently require store fences
3953 }
3954
3955 void LIR_Assembler::membar_loadload() {
3956 // no-op
3957 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3958 }
3959
3960 void LIR_Assembler::membar_storestore() {
3961 // no-op
3962 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3963 }
3964
3965 void LIR_Assembler::membar_loadstore() {
3966 // no-op
3967 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3968 }
3969
3970 void LIR_Assembler::membar_storeload() {
3971 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3972 }
3973
3974 void LIR_Assembler::on_spin_wait() {
3975 __ pause ();
3976 }
3977
3978 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3979 assert(result_reg->is_register(), "check");
3980 #ifdef _LP64
3981 // __ get_thread(result_reg->as_register_lo());
3982 __ mov(result_reg->as_register(), r15_thread);
3983 #else
3984 __ get_thread(result_reg->as_register());
3985 #endif // _LP64
3986 }
3987
3988
3989 void LIR_Assembler::peephole(LIR_List*) {
3990 // do nothing for now
3991 }
3992
3993 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3994 assert(data == dest, "xchg/xadd uses only 2 operands");
3995
3996 if (data->type() == T_INT) {
3997 if (code == lir_xadd) {
3998 __ lock();
3999 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4000 } else {
4001 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4002 }
4003 } else if (data->is_oop()) {
4004 assert (code == lir_xchg, "xadd for oops");
4005 Register obj = data->as_register();
4006 #ifdef _LP64
4007 if (UseCompressedOops) {
4008 __ encode_heap_oop(obj);
4009 __ xchgl(obj, as_Address(src->as_address_ptr()));
4010 __ decode_heap_oop(obj);
4011 } else {
4012 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4013 }
4014 #else
4015 __ xchgl(obj, as_Address(src->as_address_ptr()));
4016 #endif
4017 } else if (data->type() == T_LONG) {
4018 #ifdef _LP64
4019 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4020 if (code == lir_xadd) {
4021 __ lock();
4022 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4023 } else {
4024 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4025 }
4026 #else
4027 ShouldNotReachHere();
4028 #endif
4029 } else {
4030 ShouldNotReachHere();
4031 }
4032 }
4033
4034 #undef __